Repository: Awesome-HarmonyOS/HarmonyOS Branch: master Commit: 5d2008e97ea2 Files: 2297 Total size: 43.3 MB Directory structure: gitextract_prpumcnz/ ├── CNAME ├── Huawei_LiteOS/ │ ├── .github/ │ │ └── ISSUE_TEMPLATE/ │ │ ├── bug_report.md │ │ └── feature_request.md │ ├── .travis.yml │ ├── LICENSE │ ├── README.md │ ├── arch/ │ │ ├── arm/ │ │ │ ├── arm-m/ │ │ │ │ ├── cortex-m0/ │ │ │ │ │ ├── gcc/ │ │ │ │ │ │ ├── los_dispatch_gcc.S │ │ │ │ │ │ └── los_hw_exc_gcc.S │ │ │ │ │ ├── iar/ │ │ │ │ │ │ └── los_dispatch_iar.S │ │ │ │ │ ├── keil/ │ │ │ │ │ │ ├── los_dispatch_keil.S │ │ │ │ │ │ └── los_hw_exc_keil.S │ │ │ │ │ ├── los_exc.c │ │ │ │ │ ├── los_exc.inc │ │ │ │ │ └── los_exc.ph │ │ │ │ ├── cortex-m3/ │ │ │ │ │ ├── gcc/ │ │ │ │ │ │ ├── los_dispatch_gcc.S │ │ │ │ │ │ └── los_hw_exc_gcc.S │ │ │ │ │ ├── iar/ │ │ │ │ │ │ └── los_dispatch_iar.S │ │ │ │ │ ├── keil/ │ │ │ │ │ │ ├── los_dispatch_keil.S │ │ │ │ │ │ └── los_hw_exc_keil.S │ │ │ │ │ ├── los_exc.c │ │ │ │ │ ├── los_exc.inc │ │ │ │ │ ├── los_exc.ph │ │ │ │ │ └── test_funcs.S │ │ │ │ ├── cortex-m4/ │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── gcc/ │ │ │ │ │ │ ├── los_dispatch_gcc.S │ │ │ │ │ │ └── los_hw_exc_gcc.S │ │ │ │ │ ├── iar/ │ │ │ │ │ │ ├── los_dispatch_iar.S │ │ │ │ │ │ └── los_hw_exc_iar.S │ │ │ │ │ ├── keil/ │ │ │ │ │ │ ├── los_dispatch_keil.S │ │ │ │ │ │ └── los_hw_exc_keil.S │ │ │ │ │ ├── los_exc.c │ │ │ │ │ ├── los_exc.inc │ │ │ │ │ └── los_exc.ph │ │ │ │ ├── cortex-m7/ │ │ │ │ │ ├── gcc/ │ │ │ │ │ │ ├── los_dispatch_gcc.S │ │ │ │ │ │ └── los_hw_exc_gcc.S │ │ │ │ │ ├── iar/ │ │ │ │ │ │ └── los_dispatch_iar.S │ │ │ │ │ ├── keil/ │ │ │ │ │ │ ├── los_dispatch_keil.S │ │ │ │ │ │ └── los_hw_exc_keil.S │ │ │ │ │ ├── los_exc.c │ │ │ │ │ ├── los_exc.inc │ │ │ │ │ └── los_exc.ph │ │ │ │ ├── include/ │ │ │ │ │ ├── los_exc.h │ │ │ │ │ ├── los_hw.h │ │ │ │ │ ├── los_hw_tick.h │ │ │ │ │ └── los_hwi.h │ │ │ │ └── src/ │ │ │ │ ├── los_hw.c │ │ │ │ ├── los_hw_tick.c │ │ │ │ └── los_hwi.c │ │ │ └── common/ │ │ │ └── cmsis/ │ │ │ ├── arm_common_tables.h │ │ │ ├── arm_const_structs.h │ │ │ ├── arm_math.h │ │ │ ├── cmsis_armcc.h │ │ │ ├── cmsis_armclang.h │ │ │ ├── cmsis_compiler.h │ │ │ ├── cmsis_gcc.h │ │ │ ├── core_armv8mbl.h │ │ │ ├── core_armv8mml.h │ │ │ ├── core_cm0.h │ │ │ ├── core_cm0plus.h │ │ │ ├── core_cm23.h │ │ │ ├── core_cm3.h │ │ │ ├── core_cm33.h │ │ │ ├── core_cm4.h │ │ │ ├── core_cm7.h │ │ │ ├── core_sc000.h │ │ │ ├── core_sc300.h │ │ │ └── tz_context.h │ │ └── msp430/ │ │ ├── include/ │ │ │ ├── los_hw.h │ │ │ └── los_hwi.h │ │ └── src/ │ │ ├── ccsmacros.h │ │ ├── los_dispatch_ccs.asm │ │ ├── los_dispatch_iar.s43 │ │ ├── los_hw.c │ │ ├── los_hw_tick.c │ │ └── los_hwi.c │ ├── build/ │ │ └── Makefile │ ├── components/ │ │ ├── connectivity/ │ │ │ ├── agent_tiny/ │ │ │ │ ├── atiny_lwm2m/ │ │ │ │ │ ├── agent_list.h │ │ │ │ │ ├── agenttiny.c │ │ │ │ │ ├── atiny_context.h │ │ │ │ │ ├── atiny_fota_manager.c │ │ │ │ │ ├── atiny_fota_manager.h │ │ │ │ │ ├── atiny_fota_state.c │ │ │ │ │ ├── atiny_fota_state.h │ │ │ │ │ ├── atiny_rpt.c │ │ │ │ │ ├── atiny_rpt.h │ │ │ │ │ ├── connection.c │ │ │ │ │ ├── connection.h │ │ │ │ │ ├── firmware_update.c │ │ │ │ │ ├── firmware_update.h │ │ │ │ │ ├── object_access_control.c │ │ │ │ │ ├── object_binary_app_data_container.c │ │ │ │ │ ├── object_comm.h │ │ │ │ │ ├── object_connectivity_moni.c │ │ │ │ │ ├── object_connectivity_stat.c │ │ │ │ │ ├── object_device.c │ │ │ │ │ ├── object_firmware.c │ │ │ │ │ ├── object_location.c │ │ │ │ │ ├── object_security.c │ │ │ │ │ ├── object_server.c │ │ │ │ │ ├── platform_adapter.c │ │ │ │ │ ├── util_timer.c │ │ │ │ │ └── util_timer.h │ │ │ │ └── atiny_mqtt/ │ │ │ │ ├── flash_manager.c │ │ │ │ ├── flash_manager.h │ │ │ │ ├── hmac.c │ │ │ │ ├── hmac.h │ │ │ │ └── mqtt_client.c │ │ │ ├── lwm2m/ │ │ │ │ ├── CONTRIBUTING.md │ │ │ │ ├── EDL-v1.0 │ │ │ │ ├── EPL-v1.0 │ │ │ │ ├── README.md │ │ │ │ ├── THIRD PARTY OPEN SOURCE SOFTWARE NOTICE.docx │ │ │ │ ├── TODO │ │ │ │ ├── about.html │ │ │ │ ├── core/ │ │ │ │ │ ├── block1.c │ │ │ │ │ ├── bootstrap.c │ │ │ │ │ ├── data.c │ │ │ │ │ ├── discover.c │ │ │ │ │ ├── er-coap-13/ │ │ │ │ │ │ ├── LICENSE │ │ │ │ │ │ ├── er-coap-13.c │ │ │ │ │ │ └── er-coap-13.h │ │ │ │ │ ├── internals.h │ │ │ │ │ ├── json.c │ │ │ │ │ ├── liblwm2m.c │ │ │ │ │ ├── liblwm2m.h │ │ │ │ │ ├── liblwm2m_api.h │ │ │ │ │ ├── list.c │ │ │ │ │ ├── lwm2m_utils.c │ │ │ │ │ ├── management.c │ │ │ │ │ ├── objects.c │ │ │ │ │ ├── observe.c │ │ │ │ │ ├── packet.c │ │ │ │ │ ├── registration.c │ │ │ │ │ ├── tlv.c │ │ │ │ │ ├── transaction.c │ │ │ │ │ ├── uri.c │ │ │ │ │ └── wakaama.cmake │ │ │ │ └── examples/ │ │ │ │ └── shared/ │ │ │ │ ├── commandline.c │ │ │ │ └── commandline.h │ │ │ ├── mqtt/ │ │ │ │ ├── .cproject │ │ │ │ ├── .gitignore │ │ │ │ ├── .project │ │ │ │ ├── .settings/ │ │ │ │ │ ├── org.eclipse.cdt.core.prefs │ │ │ │ │ └── org.eclipse.cdt.ui.prefs │ │ │ │ ├── .travis.yml │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── CONTRIBUTING.md │ │ │ │ ├── MQTTClient-C/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── samples/ │ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ │ ├── FreeRTOS/ │ │ │ │ │ │ │ └── MQTTEcho.c │ │ │ │ │ │ └── linux/ │ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ │ ├── build.sh │ │ │ │ │ │ └── stdoutsub.c │ │ │ │ │ ├── src/ │ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ │ ├── FreeRTOS/ │ │ │ │ │ │ │ ├── MQTTFreeRTOS.c │ │ │ │ │ │ │ └── MQTTFreeRTOS.h │ │ │ │ │ │ ├── MQTTClient.c │ │ │ │ │ │ ├── MQTTClient.h │ │ │ │ │ │ ├── cc3200/ │ │ │ │ │ │ │ ├── MQTTCC3200.c │ │ │ │ │ │ │ └── MQTTCC3200.h │ │ │ │ │ │ ├── linux/ │ │ │ │ │ │ │ ├── MQTTLinux.c │ │ │ │ │ │ │ └── MQTTLinux.h │ │ │ │ │ │ └── liteOS/ │ │ │ │ │ │ ├── MQTTliteos.c │ │ │ │ │ │ └── MQTTliteos.h │ │ │ │ │ └── test/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── test1.c │ │ │ │ ├── MQTTPacket/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── samples/ │ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ │ ├── baremetalserial/ │ │ │ │ │ │ │ ├── build │ │ │ │ │ │ │ ├── ping_nb.c │ │ │ │ │ │ │ ├── pub0sub1_nb.c │ │ │ │ │ │ │ ├── transport.c │ │ │ │ │ │ │ └── transport.h │ │ │ │ │ │ ├── build │ │ │ │ │ │ ├── null.c │ │ │ │ │ │ ├── ping.c │ │ │ │ │ │ ├── ping_nb.c │ │ │ │ │ │ ├── pub0sub1.c │ │ │ │ │ │ ├── pub0sub1_nb.c │ │ │ │ │ │ ├── qos0pub.c │ │ │ │ │ │ ├── transport.c │ │ │ │ │ │ └── transport.h │ │ │ │ │ ├── src/ │ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ │ ├── MQTTConnect.h │ │ │ │ │ │ ├── MQTTConnectClient.c │ │ │ │ │ │ ├── MQTTConnectServer.c │ │ │ │ │ │ ├── MQTTDeserializePublish.c │ │ │ │ │ │ ├── MQTTFormat.c │ │ │ │ │ │ ├── MQTTFormat.h │ │ │ │ │ │ ├── MQTTPacket.c │ │ │ │ │ │ ├── MQTTPacket.h │ │ │ │ │ │ ├── MQTTPublish.h │ │ │ │ │ │ ├── MQTTSerializePublish.c │ │ │ │ │ │ ├── MQTTSubscribe.h │ │ │ │ │ │ ├── MQTTSubscribeClient.c │ │ │ │ │ │ ├── MQTTSubscribeServer.c │ │ │ │ │ │ ├── MQTTUnsubscribe.h │ │ │ │ │ │ ├── MQTTUnsubscribeClient.c │ │ │ │ │ │ ├── MQTTUnsubscribeServer.c │ │ │ │ │ │ └── StackTrace.h │ │ │ │ │ └── test/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── build_test │ │ │ │ │ └── test1.c │ │ │ │ ├── Makefile │ │ │ │ ├── README.md │ │ │ │ ├── THIRD PARTY OPEN SOURCE SOFTWARE NOTICE.docx │ │ │ │ ├── about.html │ │ │ │ ├── edl-v10 │ │ │ │ ├── epl-v10 │ │ │ │ ├── library.properties │ │ │ │ ├── notice.html │ │ │ │ ├── travis-build.sh │ │ │ │ ├── travis-env-vars │ │ │ │ └── travis-install.sh │ │ │ └── nb_iot/ │ │ │ └── los_nb_api.c │ │ ├── fs/ │ │ │ ├── devfs/ │ │ │ │ └── los_devfs.c │ │ │ ├── fatfs/ │ │ │ │ ├── ff13b/ │ │ │ │ │ ├── LICENSE.txt │ │ │ │ │ └── source/ │ │ │ │ │ ├── 00history.txt │ │ │ │ │ ├── 00readme.txt │ │ │ │ │ ├── default/ │ │ │ │ │ │ └── ffconf.h │ │ │ │ │ ├── diskio.c │ │ │ │ │ ├── diskio.h │ │ │ │ │ ├── ff.c │ │ │ │ │ ├── ff.h │ │ │ │ │ ├── ffsystem.c │ │ │ │ │ ├── ffunicode.c │ │ │ │ │ └── integer.h │ │ │ │ └── los_fatfs.c │ │ │ ├── kifs/ │ │ │ │ └── los_kifs.c │ │ │ ├── ramfs/ │ │ │ │ └── los_ramfs.c │ │ │ ├── spiffs/ │ │ │ │ ├── README │ │ │ │ ├── los_spiffs.c │ │ │ │ └── spiffs_git/ │ │ │ │ ├── FUZZING.md │ │ │ │ ├── LICENSE │ │ │ │ ├── README.md │ │ │ │ ├── docs/ │ │ │ │ │ ├── TECH_SPEC │ │ │ │ │ └── TODO │ │ │ │ └── src/ │ │ │ │ ├── default/ │ │ │ │ │ └── spiffs_config.h │ │ │ │ ├── spiffs.h │ │ │ │ ├── spiffs_cache.c │ │ │ │ ├── spiffs_check.c │ │ │ │ ├── spiffs_gc.c │ │ │ │ ├── spiffs_hydrogen.c │ │ │ │ ├── spiffs_nucleus.c │ │ │ │ └── spiffs_nucleus.h │ │ │ └── vfs/ │ │ │ └── los_vfs.c │ │ ├── lib/ │ │ │ ├── cJSON/ │ │ │ │ ├── cJSON.c │ │ │ │ └── cJSON.h │ │ │ └── libc/ │ │ │ ├── errno.c │ │ │ ├── malloc.c │ │ │ └── newlib_stub.c │ │ ├── log/ │ │ │ └── atiny_log.c │ │ ├── net/ │ │ │ ├── at_device/ │ │ │ │ ├── emtc_bg36/ │ │ │ │ │ ├── bg36.c │ │ │ │ │ └── bg36.h │ │ │ │ ├── gprs_sim900a/ │ │ │ │ │ ├── sim900a.c │ │ │ │ │ └── sim900a.h │ │ │ │ ├── nb_bc95/ │ │ │ │ │ └── bc95.c │ │ │ │ └── wifi_esp8266/ │ │ │ │ ├── esp8266.c │ │ │ │ └── esp8266.h │ │ │ ├── at_frame/ │ │ │ │ ├── at_api.c │ │ │ │ └── at_main.c │ │ │ ├── lwip/ │ │ │ │ ├── THIRD PARTY OPEN SOURCE SOFTWARE NOTICE.docx │ │ │ │ ├── lwip-2.0.3/ │ │ │ │ │ ├── CHANGELOG │ │ │ │ │ ├── COPYING │ │ │ │ │ ├── FILES │ │ │ │ │ ├── README │ │ │ │ │ ├── UPGRADING │ │ │ │ │ ├── doc/ │ │ │ │ │ │ ├── FILES │ │ │ │ │ │ ├── NO_SYS_SampleCode.c │ │ │ │ │ │ ├── contrib.txt │ │ │ │ │ │ ├── doxygen/ │ │ │ │ │ │ │ ├── generate.bat │ │ │ │ │ │ │ ├── generate.sh │ │ │ │ │ │ │ ├── lwip.Doxyfile │ │ │ │ │ │ │ └── main_page.h │ │ │ │ │ │ ├── mdns.txt │ │ │ │ │ │ ├── mqtt_client.txt │ │ │ │ │ │ ├── ppp.txt │ │ │ │ │ │ ├── rawapi.txt │ │ │ │ │ │ ├── savannah.txt │ │ │ │ │ │ └── sys_arch.txt │ │ │ │ │ ├── src/ │ │ │ │ │ │ ├── FILES │ │ │ │ │ │ ├── Filelists.mk │ │ │ │ │ │ ├── api/ │ │ │ │ │ │ │ ├── api_lib.c │ │ │ │ │ │ │ ├── api_msg.c │ │ │ │ │ │ │ ├── err.c │ │ │ │ │ │ │ ├── netbuf.c │ │ │ │ │ │ │ ├── netdb.c │ │ │ │ │ │ │ ├── netifapi.c │ │ │ │ │ │ │ ├── sockets.c │ │ │ │ │ │ │ └── tcpip.c │ │ │ │ │ │ ├── apps/ │ │ │ │ │ │ │ ├── httpd/ │ │ │ │ │ │ │ │ ├── fs.c │ │ │ │ │ │ │ │ ├── fsdata.c │ │ │ │ │ │ │ │ ├── fsdata.h │ │ │ │ │ │ │ │ ├── httpd.c │ │ │ │ │ │ │ │ ├── httpd_structs.h │ │ │ │ │ │ │ │ └── makefsdata/ │ │ │ │ │ │ │ │ ├── makefsdata │ │ │ │ │ │ │ │ ├── makefsdata.c │ │ │ │ │ │ │ │ └── readme.txt │ │ │ │ │ │ │ ├── lwiperf/ │ │ │ │ │ │ │ │ └── lwiperf.c │ │ │ │ │ │ │ ├── mdns/ │ │ │ │ │ │ │ │ └── mdns.c │ │ │ │ │ │ │ ├── mqtt/ │ │ │ │ │ │ │ │ └── mqtt.c │ │ │ │ │ │ │ ├── netbiosns/ │ │ │ │ │ │ │ │ └── netbiosns.c │ │ │ │ │ │ │ ├── snmp/ │ │ │ │ │ │ │ │ ├── snmp_asn1.c │ │ │ │ │ │ │ │ ├── snmp_asn1.h │ │ │ │ │ │ │ │ ├── snmp_core.c │ │ │ │ │ │ │ │ ├── snmp_core_priv.h │ │ │ │ │ │ │ │ ├── snmp_mib2.c │ │ │ │ │ │ │ │ ├── snmp_mib2_icmp.c │ │ │ │ │ │ │ │ ├── snmp_mib2_interfaces.c │ │ │ │ │ │ │ │ ├── snmp_mib2_ip.c │ │ │ │ │ │ │ │ ├── snmp_mib2_snmp.c │ │ │ │ │ │ │ │ ├── snmp_mib2_system.c │ │ │ │ │ │ │ │ ├── snmp_mib2_tcp.c │ │ │ │ │ │ │ │ ├── snmp_mib2_udp.c │ │ │ │ │ │ │ │ ├── snmp_msg.c │ │ │ │ │ │ │ │ ├── snmp_msg.h │ │ │ │ │ │ │ │ ├── snmp_netconn.c │ │ │ │ │ │ │ │ ├── snmp_pbuf_stream.c │ │ │ │ │ │ │ │ ├── snmp_pbuf_stream.h │ │ │ │ │ │ │ │ ├── snmp_raw.c │ │ │ │ │ │ │ │ ├── snmp_scalar.c │ │ │ │ │ │ │ │ ├── snmp_table.c │ │ │ │ │ │ │ │ ├── snmp_threadsync.c │ │ │ │ │ │ │ │ ├── snmp_traps.c │ │ │ │ │ │ │ │ ├── snmpv3.c │ │ │ │ │ │ │ │ ├── snmpv3_dummy.c │ │ │ │ │ │ │ │ ├── snmpv3_mbedtls.c │ │ │ │ │ │ │ │ └── snmpv3_priv.h │ │ │ │ │ │ │ ├── sntp/ │ │ │ │ │ │ │ │ └── sntp.c │ │ │ │ │ │ │ └── tftp/ │ │ │ │ │ │ │ └── tftp_server.c │ │ │ │ │ │ ├── core/ │ │ │ │ │ │ │ ├── def.c │ │ │ │ │ │ │ ├── dns.c │ │ │ │ │ │ │ ├── inet_chksum.c │ │ │ │ │ │ │ ├── init.c │ │ │ │ │ │ │ ├── ip.c │ │ │ │ │ │ │ ├── ipv4/ │ │ │ │ │ │ │ │ ├── autoip.c │ │ │ │ │ │ │ │ ├── dhcp.c │ │ │ │ │ │ │ │ ├── etharp.c │ │ │ │ │ │ │ │ ├── icmp.c │ │ │ │ │ │ │ │ ├── igmp.c │ │ │ │ │ │ │ │ ├── ip4.c │ │ │ │ │ │ │ │ ├── ip4_addr.c │ │ │ │ │ │ │ │ └── ip4_frag.c │ │ │ │ │ │ │ ├── ipv6/ │ │ │ │ │ │ │ │ ├── dhcp6.c │ │ │ │ │ │ │ │ ├── ethip6.c │ │ │ │ │ │ │ │ ├── icmp6.c │ │ │ │ │ │ │ │ ├── inet6.c │ │ │ │ │ │ │ │ ├── ip6.c │ │ │ │ │ │ │ │ ├── ip6_addr.c │ │ │ │ │ │ │ │ ├── ip6_frag.c │ │ │ │ │ │ │ │ ├── mld6.c │ │ │ │ │ │ │ │ └── nd6.c │ │ │ │ │ │ │ ├── mem.c │ │ │ │ │ │ │ ├── memp.c │ │ │ │ │ │ │ ├── netif.c │ │ │ │ │ │ │ ├── pbuf.c │ │ │ │ │ │ │ ├── raw.c │ │ │ │ │ │ │ ├── stats.c │ │ │ │ │ │ │ ├── sys.c │ │ │ │ │ │ │ ├── tcp.c │ │ │ │ │ │ │ ├── tcp_in.c │ │ │ │ │ │ │ ├── tcp_out.c │ │ │ │ │ │ │ ├── timeouts.c │ │ │ │ │ │ │ └── udp.c │ │ │ │ │ │ ├── include/ │ │ │ │ │ │ │ ├── lwip/ │ │ │ │ │ │ │ │ ├── api.h │ │ │ │ │ │ │ │ ├── apps/ │ │ │ │ │ │ │ │ │ ├── FILES │ │ │ │ │ │ │ │ │ ├── fs.h │ │ │ │ │ │ │ │ │ ├── httpd.h │ │ │ │ │ │ │ │ │ ├── httpd_opts.h │ │ │ │ │ │ │ │ │ ├── lwiperf.h │ │ │ │ │ │ │ │ │ ├── mdns.h │ │ │ │ │ │ │ │ │ ├── mdns_opts.h │ │ │ │ │ │ │ │ │ ├── mdns_priv.h │ │ │ │ │ │ │ │ │ ├── mqtt.h │ │ │ │ │ │ │ │ │ ├── mqtt_opts.h │ │ │ │ │ │ │ │ │ ├── netbiosns.h │ │ │ │ │ │ │ │ │ ├── netbiosns_opts.h │ │ │ │ │ │ │ │ │ ├── snmp.h │ │ │ │ │ │ │ │ │ ├── snmp_core.h │ │ │ │ │ │ │ │ │ ├── snmp_mib2.h │ │ │ │ │ │ │ │ │ ├── snmp_opts.h │ │ │ │ │ │ │ │ │ ├── snmp_scalar.h │ │ │ │ │ │ │ │ │ ├── snmp_table.h │ │ │ │ │ │ │ │ │ ├── snmp_threadsync.h │ │ │ │ │ │ │ │ │ ├── snmpv3.h │ │ │ │ │ │ │ │ │ ├── sntp.h │ │ │ │ │ │ │ │ │ ├── sntp_opts.h │ │ │ │ │ │ │ │ │ ├── tftp_opts.h │ │ │ │ │ │ │ │ │ └── tftp_server.h │ │ │ │ │ │ │ │ ├── arch.h │ │ │ │ │ │ │ │ ├── autoip.h │ │ │ │ │ │ │ │ ├── debug.h │ │ │ │ │ │ │ │ ├── def.h │ │ │ │ │ │ │ │ ├── dhcp.h │ │ │ │ │ │ │ │ ├── dhcp6.h │ │ │ │ │ │ │ │ ├── dns.h │ │ │ │ │ │ │ │ ├── err.h │ │ │ │ │ │ │ │ ├── errno.h │ │ │ │ │ │ │ │ ├── etharp.h │ │ │ │ │ │ │ │ ├── ethip6.h │ │ │ │ │ │ │ │ ├── icmp.h │ │ │ │ │ │ │ │ ├── icmp6.h │ │ │ │ │ │ │ │ ├── igmp.h │ │ │ │ │ │ │ │ ├── inet.h │ │ │ │ │ │ │ │ ├── inet_chksum.h │ │ │ │ │ │ │ │ ├── init.h │ │ │ │ │ │ │ │ ├── ip.h │ │ │ │ │ │ │ │ ├── ip4.h │ │ │ │ │ │ │ │ ├── ip4_addr.h │ │ │ │ │ │ │ │ ├── ip4_frag.h │ │ │ │ │ │ │ │ ├── ip6.h │ │ │ │ │ │ │ │ ├── ip6_addr.h │ │ │ │ │ │ │ │ ├── ip6_frag.h │ │ │ │ │ │ │ │ ├── ip_addr.h │ │ │ │ │ │ │ │ ├── mem.h │ │ │ │ │ │ │ │ ├── memp.h │ │ │ │ │ │ │ │ ├── mld6.h │ │ │ │ │ │ │ │ ├── nd6.h │ │ │ │ │ │ │ │ ├── netbuf.h │ │ │ │ │ │ │ │ ├── netdb.h │ │ │ │ │ │ │ │ ├── netif.h │ │ │ │ │ │ │ │ ├── netifapi.h │ │ │ │ │ │ │ │ ├── opt.h │ │ │ │ │ │ │ │ ├── pbuf.h │ │ │ │ │ │ │ │ ├── priv/ │ │ │ │ │ │ │ │ │ ├── api_msg.h │ │ │ │ │ │ │ │ │ ├── memp_priv.h │ │ │ │ │ │ │ │ │ ├── memp_std.h │ │ │ │ │ │ │ │ │ ├── nd6_priv.h │ │ │ │ │ │ │ │ │ ├── tcp_priv.h │ │ │ │ │ │ │ │ │ └── tcpip_priv.h │ │ │ │ │ │ │ │ ├── prot/ │ │ │ │ │ │ │ │ │ ├── autoip.h │ │ │ │ │ │ │ │ │ ├── dhcp.h │ │ │ │ │ │ │ │ │ ├── dns.h │ │ │ │ │ │ │ │ │ ├── etharp.h │ │ │ │ │ │ │ │ │ ├── ethernet.h │ │ │ │ │ │ │ │ │ ├── icmp.h │ │ │ │ │ │ │ │ │ ├── icmp6.h │ │ │ │ │ │ │ │ │ ├── igmp.h │ │ │ │ │ │ │ │ │ ├── ip.h │ │ │ │ │ │ │ │ │ ├── ip4.h │ │ │ │ │ │ │ │ │ ├── ip6.h │ │ │ │ │ │ │ │ │ ├── mld6.h │ │ │ │ │ │ │ │ │ ├── nd6.h │ │ │ │ │ │ │ │ │ ├── tcp.h │ │ │ │ │ │ │ │ │ └── udp.h │ │ │ │ │ │ │ │ ├── raw.h │ │ │ │ │ │ │ │ ├── sio.h │ │ │ │ │ │ │ │ ├── snmp.h │ │ │ │ │ │ │ │ ├── sockets.h │ │ │ │ │ │ │ │ ├── stats.h │ │ │ │ │ │ │ │ ├── sys.h │ │ │ │ │ │ │ │ ├── tcp.h │ │ │ │ │ │ │ │ ├── tcpip.h │ │ │ │ │ │ │ │ ├── timeouts.h │ │ │ │ │ │ │ │ └── udp.h │ │ │ │ │ │ │ ├── netif/ │ │ │ │ │ │ │ │ ├── etharp.h │ │ │ │ │ │ │ │ ├── ethernet.h │ │ │ │ │ │ │ │ ├── lowpan6.h │ │ │ │ │ │ │ │ ├── lowpan6_opts.h │ │ │ │ │ │ │ │ ├── ppp/ │ │ │ │ │ │ │ │ │ ├── ccp.h │ │ │ │ │ │ │ │ │ ├── chap-md5.h │ │ │ │ │ │ │ │ │ ├── chap-new.h │ │ │ │ │ │ │ │ │ ├── chap_ms.h │ │ │ │ │ │ │ │ │ ├── eap.h │ │ │ │ │ │ │ │ │ ├── ecp.h │ │ │ │ │ │ │ │ │ ├── eui64.h │ │ │ │ │ │ │ │ │ ├── fsm.h │ │ │ │ │ │ │ │ │ ├── ipcp.h │ │ │ │ │ │ │ │ │ ├── ipv6cp.h │ │ │ │ │ │ │ │ │ ├── lcp.h │ │ │ │ │ │ │ │ │ ├── magic.h │ │ │ │ │ │ │ │ │ ├── mppe.h │ │ │ │ │ │ │ │ │ ├── polarssl/ │ │ │ │ │ │ │ │ │ │ ├── arc4.h │ │ │ │ │ │ │ │ │ │ ├── des.h │ │ │ │ │ │ │ │ │ │ ├── md4.h │ │ │ │ │ │ │ │ │ │ ├── md5.h │ │ │ │ │ │ │ │ │ │ └── sha1.h │ │ │ │ │ │ │ │ │ ├── ppp.h │ │ │ │ │ │ │ │ │ ├── ppp_impl.h │ │ │ │ │ │ │ │ │ ├── ppp_opts.h │ │ │ │ │ │ │ │ │ ├── pppapi.h │ │ │ │ │ │ │ │ │ ├── pppcrypt.h │ │ │ │ │ │ │ │ │ ├── pppdebug.h │ │ │ │ │ │ │ │ │ ├── pppoe.h │ │ │ │ │ │ │ │ │ ├── pppol2tp.h │ │ │ │ │ │ │ │ │ ├── pppos.h │ │ │ │ │ │ │ │ │ ├── upap.h │ │ │ │ │ │ │ │ │ └── vj.h │ │ │ │ │ │ │ │ └── slipif.h │ │ │ │ │ │ │ └── posix/ │ │ │ │ │ │ │ ├── errno.h │ │ │ │ │ │ │ ├── netdb.h │ │ │ │ │ │ │ └── sys/ │ │ │ │ │ │ │ └── socket.h │ │ │ │ │ │ └── netif/ │ │ │ │ │ │ ├── FILES │ │ │ │ │ │ ├── ethernet.c │ │ │ │ │ │ ├── ethernetif_origin.c │ │ │ │ │ │ ├── lowpan6.c │ │ │ │ │ │ ├── ppp/ │ │ │ │ │ │ │ ├── PPPD_FOLLOWUP │ │ │ │ │ │ │ ├── auth.c │ │ │ │ │ │ │ ├── ccp.c │ │ │ │ │ │ │ ├── chap-md5.c │ │ │ │ │ │ │ ├── chap-new.c │ │ │ │ │ │ │ ├── chap_ms.c │ │ │ │ │ │ │ ├── demand.c │ │ │ │ │ │ │ ├── eap.c │ │ │ │ │ │ │ ├── ecp.c │ │ │ │ │ │ │ ├── eui64.c │ │ │ │ │ │ │ ├── fsm.c │ │ │ │ │ │ │ ├── ipcp.c │ │ │ │ │ │ │ ├── ipv6cp.c │ │ │ │ │ │ │ ├── lcp.c │ │ │ │ │ │ │ ├── magic.c │ │ │ │ │ │ │ ├── mppe.c │ │ │ │ │ │ │ ├── multilink.c │ │ │ │ │ │ │ ├── polarssl/ │ │ │ │ │ │ │ │ ├── README │ │ │ │ │ │ │ │ ├── arc4.c │ │ │ │ │ │ │ │ ├── des.c │ │ │ │ │ │ │ │ ├── md4.c │ │ │ │ │ │ │ │ ├── md5.c │ │ │ │ │ │ │ │ └── sha1.c │ │ │ │ │ │ │ ├── ppp.c │ │ │ │ │ │ │ ├── pppapi.c │ │ │ │ │ │ │ ├── pppcrypt.c │ │ │ │ │ │ │ ├── pppoe.c │ │ │ │ │ │ │ ├── pppol2tp.c │ │ │ │ │ │ │ ├── pppos.c │ │ │ │ │ │ │ ├── upap.c │ │ │ │ │ │ │ ├── utils.c │ │ │ │ │ │ │ └── vj.c │ │ │ │ │ │ └── slipif.c │ │ │ │ │ └── test/ │ │ │ │ │ ├── fuzz/ │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── config.h │ │ │ │ │ │ ├── fuzz.c │ │ │ │ │ │ ├── lwipopts.h │ │ │ │ │ │ └── output_to_pcap.sh │ │ │ │ │ └── unit/ │ │ │ │ │ ├── core/ │ │ │ │ │ │ ├── test_mem.c │ │ │ │ │ │ ├── test_mem.h │ │ │ │ │ │ ├── test_pbuf.c │ │ │ │ │ │ └── test_pbuf.h │ │ │ │ │ ├── dhcp/ │ │ │ │ │ │ ├── test_dhcp.c │ │ │ │ │ │ └── test_dhcp.h │ │ │ │ │ ├── etharp/ │ │ │ │ │ │ ├── test_etharp.c │ │ │ │ │ │ └── test_etharp.h │ │ │ │ │ ├── ip4/ │ │ │ │ │ │ ├── test_ip4.c │ │ │ │ │ │ └── test_ip4.h │ │ │ │ │ ├── lwip_check.h │ │ │ │ │ ├── lwip_unittests.c │ │ │ │ │ ├── lwipopts.h │ │ │ │ │ ├── mdns/ │ │ │ │ │ │ ├── test_mdns.c │ │ │ │ │ │ └── test_mdns.h │ │ │ │ │ ├── tcp/ │ │ │ │ │ │ ├── tcp_helper.c │ │ │ │ │ │ ├── tcp_helper.h │ │ │ │ │ │ ├── test_tcp.c │ │ │ │ │ │ ├── test_tcp.h │ │ │ │ │ │ ├── test_tcp_oos.c │ │ │ │ │ │ └── test_tcp_oos.h │ │ │ │ │ └── udp/ │ │ │ │ │ ├── test_udp.c │ │ │ │ │ └── test_udp.h │ │ │ │ ├── lwip_port/ │ │ │ │ │ ├── OS/ │ │ │ │ │ │ ├── ethernetif.c │ │ │ │ │ │ ├── ethernetif.h │ │ │ │ │ │ ├── lwipopts.h │ │ │ │ │ │ └── sys_arch.c │ │ │ │ │ └── arch/ │ │ │ │ │ ├── bpstruct.h │ │ │ │ │ ├── cc.h │ │ │ │ │ ├── cpu.h │ │ │ │ │ ├── epstruct.h │ │ │ │ │ ├── init.h │ │ │ │ │ ├── lib.h │ │ │ │ │ ├── perf.h │ │ │ │ │ └── sys_arch.h │ │ │ │ └── ppp_port/ │ │ │ │ ├── osport/ │ │ │ │ │ ├── iodev.c │ │ │ │ │ ├── kernel.c │ │ │ │ │ ├── osport.h │ │ │ │ │ └── ring.c │ │ │ │ └── ppppos/ │ │ │ │ ├── atcmd.c │ │ │ │ └── demo.c │ │ │ └── sal/ │ │ │ └── atiny_socket.c │ │ ├── ota/ │ │ │ ├── flag_operate/ │ │ │ │ ├── flag_manager.c │ │ │ │ ├── flag_manager.h │ │ │ │ ├── upgrade_flag.c │ │ │ │ └── upgrade_flag.h │ │ │ ├── package/ │ │ │ │ ├── opt/ │ │ │ │ │ ├── package_sha256.c │ │ │ │ │ ├── package_sha256.h │ │ │ │ │ ├── package_sha256_rsa2048.c │ │ │ │ │ └── package_sha256_rsa2048.h │ │ │ │ ├── package.c │ │ │ │ ├── package_checksum.c │ │ │ │ ├── package_checksum.h │ │ │ │ ├── package_device.h │ │ │ │ ├── package_head.c │ │ │ │ ├── package_head.h │ │ │ │ ├── package_writer.c │ │ │ │ └── package_writer.h │ │ │ ├── script/ │ │ │ │ ├── config.xml │ │ │ │ ├── gen_key.py │ │ │ │ ├── package_software.py │ │ │ │ ├── private_key.pem │ │ │ │ └── public_key.pem │ │ │ ├── sota/ │ │ │ │ ├── sota.c │ │ │ │ ├── sota_hal.c │ │ │ │ └── sota_hal.h │ │ │ └── utility/ │ │ │ ├── ota_crc.c │ │ │ └── ota_crc.h │ │ └── security/ │ │ └── mbedtls/ │ │ ├── THIRD PARTY OPEN SOURCE SOFTWARE NOTICE.docx │ │ ├── mbedtls-2.6.0/ │ │ │ ├── .github/ │ │ │ │ ├── issue_template.md │ │ │ │ └── pull_request_template.md │ │ │ ├── .gitignore │ │ │ ├── .travis.yml │ │ │ ├── CMakeLists.txt │ │ │ ├── ChangeLog │ │ │ ├── DartConfiguration.tcl │ │ │ ├── LICENSE │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── apache-2.0.txt │ │ │ ├── circle.yml │ │ │ ├── configs/ │ │ │ │ ├── README.txt │ │ │ │ ├── config-ccm-psk-tls1_2.h │ │ │ │ ├── config-mini-tls1_1.h │ │ │ │ ├── config-no-entropy.h │ │ │ │ ├── config-picocoin.h │ │ │ │ ├── config-suite-b.h │ │ │ │ └── config-thread.h │ │ │ ├── doxygen/ │ │ │ │ ├── input/ │ │ │ │ │ ├── doc_encdec.h │ │ │ │ │ ├── doc_hashing.h │ │ │ │ │ ├── doc_mainpage.h │ │ │ │ │ ├── doc_rng.h │ │ │ │ │ ├── doc_ssltls.h │ │ │ │ │ ├── doc_tcpip.h │ │ │ │ │ └── doc_x509.h │ │ │ │ └── mbedtls.doxyfile │ │ │ ├── include/ │ │ │ │ ├── .gitignore │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── mbedtls/ │ │ │ │ ├── aes.h │ │ │ │ ├── aesni.h │ │ │ │ ├── arc4.h │ │ │ │ ├── asn1.h │ │ │ │ ├── asn1write.h │ │ │ │ ├── base64.h │ │ │ │ ├── bignum.h │ │ │ │ ├── blowfish.h │ │ │ │ ├── bn_mul.h │ │ │ │ ├── camellia.h │ │ │ │ ├── ccm.h │ │ │ │ ├── certs.h │ │ │ │ ├── check_config.h │ │ │ │ ├── cipher.h │ │ │ │ ├── cipher_internal.h │ │ │ │ ├── cmac.h │ │ │ │ ├── compat-1.3.h │ │ │ │ ├── config.h │ │ │ │ ├── ctr_drbg.h │ │ │ │ ├── debug.h │ │ │ │ ├── des.h │ │ │ │ ├── dhm.h │ │ │ │ ├── ecdh.h │ │ │ │ ├── ecdsa.h │ │ │ │ ├── ecjpake.h │ │ │ │ ├── ecp.h │ │ │ │ ├── ecp_internal.h │ │ │ │ ├── entropy.h │ │ │ │ ├── entropy_poll.h │ │ │ │ ├── error.h │ │ │ │ ├── gcm.h │ │ │ │ ├── havege.h │ │ │ │ ├── hmac_drbg.h │ │ │ │ ├── md.h │ │ │ │ ├── md2.h │ │ │ │ ├── md4.h │ │ │ │ ├── md5.h │ │ │ │ ├── md_internal.h │ │ │ │ ├── memory_buffer_alloc.h │ │ │ │ ├── net.h │ │ │ │ ├── net_sockets.h │ │ │ │ ├── oid.h │ │ │ │ ├── padlock.h │ │ │ │ ├── pem.h │ │ │ │ ├── pk.h │ │ │ │ ├── pk_internal.h │ │ │ │ ├── pkcs11.h │ │ │ │ ├── pkcs12.h │ │ │ │ ├── pkcs5.h │ │ │ │ ├── platform.h │ │ │ │ ├── platform_time.h │ │ │ │ ├── ripemd160.h │ │ │ │ ├── rsa.h │ │ │ │ ├── sha1.h │ │ │ │ ├── sha256.h │ │ │ │ ├── sha512.h │ │ │ │ ├── ssl.h │ │ │ │ ├── ssl_cache.h │ │ │ │ ├── ssl_ciphersuites.h │ │ │ │ ├── ssl_cookie.h │ │ │ │ ├── ssl_internal.h │ │ │ │ ├── ssl_ticket.h │ │ │ │ ├── threading.h │ │ │ │ ├── timing.h │ │ │ │ ├── version.h │ │ │ │ ├── x509.h │ │ │ │ ├── x509_crl.h │ │ │ │ ├── x509_crt.h │ │ │ │ ├── x509_csr.h │ │ │ │ └── xtea.h │ │ │ ├── library/ │ │ │ │ ├── .gitignore │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ ├── aes.c │ │ │ │ ├── aesni.c │ │ │ │ ├── arc4.c │ │ │ │ ├── asn1parse.c │ │ │ │ ├── asn1write.c │ │ │ │ ├── base64.c │ │ │ │ ├── bignum.c │ │ │ │ ├── blowfish.c │ │ │ │ ├── camellia.c │ │ │ │ ├── ccm.c │ │ │ │ ├── certs.c │ │ │ │ ├── cipher.c │ │ │ │ ├── cipher_wrap.c │ │ │ │ ├── cmac.c │ │ │ │ ├── ctr_drbg.c │ │ │ │ ├── debug.c │ │ │ │ ├── des.c │ │ │ │ ├── dhm.c │ │ │ │ ├── ecdh.c │ │ │ │ ├── ecdsa.c │ │ │ │ ├── ecjpake.c │ │ │ │ ├── ecp.c │ │ │ │ ├── ecp_curves.c │ │ │ │ ├── entropy.c │ │ │ │ ├── entropy_poll.c │ │ │ │ ├── error.c │ │ │ │ ├── gcm.c │ │ │ │ ├── havege.c │ │ │ │ ├── hmac_drbg.c │ │ │ │ ├── md.c │ │ │ │ ├── md2.c │ │ │ │ ├── md4.c │ │ │ │ ├── md5.c │ │ │ │ ├── md_wrap.c │ │ │ │ ├── memory_buffer_alloc.c │ │ │ │ ├── net_sockets.c │ │ │ │ ├── oid.c │ │ │ │ ├── padlock.c │ │ │ │ ├── pem.c │ │ │ │ ├── pk.c │ │ │ │ ├── pk_wrap.c │ │ │ │ ├── pkcs11.c │ │ │ │ ├── pkcs12.c │ │ │ │ ├── pkcs5.c │ │ │ │ ├── pkparse.c │ │ │ │ ├── pkwrite.c │ │ │ │ ├── platform.c │ │ │ │ ├── ripemd160.c │ │ │ │ ├── rsa.c │ │ │ │ ├── sha1.c │ │ │ │ ├── sha256.c │ │ │ │ ├── sha512.c │ │ │ │ ├── ssl_cache.c │ │ │ │ ├── ssl_ciphersuites.c │ │ │ │ ├── ssl_cli.c │ │ │ │ ├── ssl_cookie.c │ │ │ │ ├── ssl_srv.c │ │ │ │ ├── ssl_ticket.c │ │ │ │ ├── ssl_tls.c │ │ │ │ ├── threading.c │ │ │ │ ├── timing.c │ │ │ │ ├── version.c │ │ │ │ ├── version_features.c │ │ │ │ ├── x509.c │ │ │ │ ├── x509_create.c │ │ │ │ ├── x509_crl.c │ │ │ │ ├── x509_crt.c │ │ │ │ ├── x509_csr.c │ │ │ │ ├── x509write_crt.c │ │ │ │ ├── x509write_csr.c │ │ │ │ └── xtea.c │ │ │ ├── programs/ │ │ │ │ ├── .gitignore │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ ├── aes/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── aescrypt2.c │ │ │ │ │ └── crypt_and_hash.c │ │ │ │ ├── hash/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── generic_sum.c │ │ │ │ │ └── hello.c │ │ │ │ ├── pkey/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── dh_client.c │ │ │ │ │ ├── dh_genprime.c │ │ │ │ │ ├── dh_prime.txt │ │ │ │ │ ├── dh_server.c │ │ │ │ │ ├── ecdh_curve25519.c │ │ │ │ │ ├── ecdsa.c │ │ │ │ │ ├── gen_key.c │ │ │ │ │ ├── key_app.c │ │ │ │ │ ├── key_app_writer.c │ │ │ │ │ ├── mpi_demo.c │ │ │ │ │ ├── pk_decrypt.c │ │ │ │ │ ├── pk_encrypt.c │ │ │ │ │ ├── pk_sign.c │ │ │ │ │ ├── pk_verify.c │ │ │ │ │ ├── rsa_decrypt.c │ │ │ │ │ ├── rsa_encrypt.c │ │ │ │ │ ├── rsa_genkey.c │ │ │ │ │ ├── rsa_priv.txt │ │ │ │ │ ├── rsa_pub.txt │ │ │ │ │ ├── rsa_sign.c │ │ │ │ │ ├── rsa_sign_pss.c │ │ │ │ │ ├── rsa_verify.c │ │ │ │ │ └── rsa_verify_pss.c │ │ │ │ ├── random/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── gen_entropy.c │ │ │ │ │ ├── gen_random_ctr_drbg.c │ │ │ │ │ └── gen_random_havege.c │ │ │ │ ├── ssl/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── dtls_client.c │ │ │ │ │ ├── dtls_server.c │ │ │ │ │ ├── mini_client.c │ │ │ │ │ ├── ssl_client1.c │ │ │ │ │ ├── ssl_client2.c │ │ │ │ │ ├── ssl_fork_server.c │ │ │ │ │ ├── ssl_mail_client.c │ │ │ │ │ ├── ssl_pthread_server.c │ │ │ │ │ ├── ssl_server.c │ │ │ │ │ └── ssl_server2.c │ │ │ │ ├── test/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── benchmark.c │ │ │ │ │ ├── selftest.c │ │ │ │ │ ├── ssl_cert_test.c │ │ │ │ │ └── udp_proxy.c │ │ │ │ ├── util/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── pem2der.c │ │ │ │ │ └── strerror.c │ │ │ │ ├── wince_main.c │ │ │ │ └── x509/ │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── cert_app.c │ │ │ │ ├── cert_req.c │ │ │ │ ├── cert_write.c │ │ │ │ ├── crl_app.c │ │ │ │ └── req_app.c │ │ │ ├── scripts/ │ │ │ │ ├── apidoc_full.sh │ │ │ │ ├── bump_version.sh │ │ │ │ ├── config.pl │ │ │ │ ├── data_files/ │ │ │ │ │ ├── error.fmt │ │ │ │ │ ├── rename-1.3-2.0.txt │ │ │ │ │ ├── version_features.fmt │ │ │ │ │ ├── vs2010-app-template.vcxproj │ │ │ │ │ ├── vs2010-main-template.vcxproj │ │ │ │ │ ├── vs2010-sln-template.sln │ │ │ │ │ ├── vs6-app-template.dsp │ │ │ │ │ ├── vs6-main-template.dsp │ │ │ │ │ └── vs6-workspace-template.dsw │ │ │ │ ├── ecc-heap.sh │ │ │ │ ├── find-mem-leak.cocci │ │ │ │ ├── footprint.sh │ │ │ │ ├── generate_errors.pl │ │ │ │ ├── generate_features.pl │ │ │ │ ├── generate_visualc_files.pl │ │ │ │ ├── malloc-init.pl │ │ │ │ ├── massif_max.pl │ │ │ │ ├── memory.sh │ │ │ │ ├── output_env.sh │ │ │ │ ├── rename.pl │ │ │ │ ├── rm-malloc-cast.cocci │ │ │ │ └── tmp_ignore_makefiles.sh │ │ │ ├── tests/ │ │ │ │ ├── .gitignore │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Descriptions.txt │ │ │ │ ├── Makefile │ │ │ │ ├── compat.sh │ │ │ │ ├── data_files/ │ │ │ │ │ ├── .gitignore │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── Readme-x509.txt │ │ │ │ │ ├── bitstring-in-dn.pem │ │ │ │ │ ├── cert_example_multi.crt │ │ │ │ │ ├── cert_example_multi_nocn.crt │ │ │ │ │ ├── cert_example_wildcard.crt │ │ │ │ │ ├── cert_md2.crt │ │ │ │ │ ├── cert_md4.crt │ │ │ │ │ ├── cert_md5.crt │ │ │ │ │ ├── cert_sha1.crt │ │ │ │ │ ├── cert_sha224.crt │ │ │ │ │ ├── cert_sha256.crt │ │ │ │ │ ├── cert_sha384.crt │ │ │ │ │ ├── cert_sha512.crt │ │ │ │ │ ├── cert_v1_with_ext.crt │ │ │ │ │ ├── cli-rsa-sha1.crt │ │ │ │ │ ├── cli-rsa-sha256.crt │ │ │ │ │ ├── cli-rsa.key │ │ │ │ │ ├── cli.opensslconf │ │ │ │ │ ├── cli2.crt │ │ │ │ │ ├── cli2.key │ │ │ │ │ ├── crl-ec-sha1.pem │ │ │ │ │ ├── crl-ec-sha224.pem │ │ │ │ │ ├── crl-ec-sha256.pem │ │ │ │ │ ├── crl-ec-sha384.pem │ │ │ │ │ ├── crl-ec-sha512.pem │ │ │ │ │ ├── crl-future.pem │ │ │ │ │ ├── crl-malformed-trailing-spaces.pem │ │ │ │ │ ├── crl-rsa-pss-sha1-badsign.pem │ │ │ │ │ ├── crl-rsa-pss-sha1.pem │ │ │ │ │ ├── crl-rsa-pss-sha224.pem │ │ │ │ │ ├── crl-rsa-pss-sha256.pem │ │ │ │ │ ├── crl-rsa-pss-sha384.pem │ │ │ │ │ ├── crl-rsa-pss-sha512.pem │ │ │ │ │ ├── crl.pem │ │ │ │ │ ├── crl_cat_ec-rsa.pem │ │ │ │ │ ├── crl_cat_ecfut-rsa.pem │ │ │ │ │ ├── crl_cat_rsa-ec.pem │ │ │ │ │ ├── crl_cat_rsabadpem-ec.pem │ │ │ │ │ ├── crl_expired.pem │ │ │ │ │ ├── crl_md2.pem │ │ │ │ │ ├── crl_md4.pem │ │ │ │ │ ├── crl_md5.pem │ │ │ │ │ ├── crl_sha1.pem │ │ │ │ │ ├── crl_sha224.pem │ │ │ │ │ ├── crl_sha256.pem │ │ │ │ │ ├── crl_sha384.pem │ │ │ │ │ ├── crl_sha512.pem │ │ │ │ │ ├── crt_cat_rsaexp-ec.pem │ │ │ │ │ ├── dh.1000.pem │ │ │ │ │ ├── dh.optlen.pem │ │ │ │ │ ├── dhparams.pem │ │ │ │ │ ├── dir-maxpath/ │ │ │ │ │ │ ├── 00.crt │ │ │ │ │ │ ├── 00.key │ │ │ │ │ │ ├── 01.crt │ │ │ │ │ │ ├── 01.key │ │ │ │ │ │ ├── 02.crt │ │ │ │ │ │ ├── 02.key │ │ │ │ │ │ ├── 03.crt │ │ │ │ │ │ ├── 03.key │ │ │ │ │ │ ├── 04.crt │ │ │ │ │ │ ├── 04.key │ │ │ │ │ │ ├── 05.crt │ │ │ │ │ │ ├── 05.key │ │ │ │ │ │ ├── 06.crt │ │ │ │ │ │ ├── 06.key │ │ │ │ │ │ ├── 07.crt │ │ │ │ │ │ ├── 07.key │ │ │ │ │ │ ├── 08.crt │ │ │ │ │ │ ├── 08.key │ │ │ │ │ │ ├── 09.crt │ │ │ │ │ │ ├── 09.key │ │ │ │ │ │ ├── 10.crt │ │ │ │ │ │ ├── 10.key │ │ │ │ │ │ ├── 11.crt │ │ │ │ │ │ ├── 11.key │ │ │ │ │ │ ├── 12.crt │ │ │ │ │ │ ├── 12.key │ │ │ │ │ │ ├── 13.crt │ │ │ │ │ │ ├── 13.key │ │ │ │ │ │ ├── 14.crt │ │ │ │ │ │ ├── 14.key │ │ │ │ │ │ ├── 15.crt │ │ │ │ │ │ ├── 15.key │ │ │ │ │ │ ├── 16.crt │ │ │ │ │ │ ├── 16.key │ │ │ │ │ │ ├── 17.crt │ │ │ │ │ │ ├── 17.key │ │ │ │ │ │ ├── 18.crt │ │ │ │ │ │ ├── 18.key │ │ │ │ │ │ ├── 19.crt │ │ │ │ │ │ ├── 19.key │ │ │ │ │ │ ├── 20.crt │ │ │ │ │ │ ├── 20.key │ │ │ │ │ │ ├── Readme.txt │ │ │ │ │ │ ├── c00.pem │ │ │ │ │ │ ├── c01.pem │ │ │ │ │ │ ├── c02.pem │ │ │ │ │ │ ├── c03.pem │ │ │ │ │ │ ├── c04.pem │ │ │ │ │ │ ├── c05.pem │ │ │ │ │ │ ├── c06.pem │ │ │ │ │ │ ├── c07.pem │ │ │ │ │ │ ├── c08.pem │ │ │ │ │ │ ├── c09.pem │ │ │ │ │ │ ├── c10.pem │ │ │ │ │ │ ├── c11.pem │ │ │ │ │ │ ├── c12.pem │ │ │ │ │ │ ├── c13.pem │ │ │ │ │ │ ├── c14.pem │ │ │ │ │ │ ├── c15.pem │ │ │ │ │ │ ├── c16.pem │ │ │ │ │ │ ├── c17.pem │ │ │ │ │ │ ├── c18.pem │ │ │ │ │ │ ├── c19.pem │ │ │ │ │ │ ├── c20.pem │ │ │ │ │ │ ├── int.opensslconf │ │ │ │ │ │ └── long.sh │ │ │ │ │ ├── dir1/ │ │ │ │ │ │ └── test-ca.crt │ │ │ │ │ ├── dir2/ │ │ │ │ │ │ ├── test-ca.crt │ │ │ │ │ │ └── test-ca2.crt │ │ │ │ │ ├── dir3/ │ │ │ │ │ │ ├── Readme │ │ │ │ │ │ ├── test-ca.crt │ │ │ │ │ │ └── test-ca2.crt │ │ │ │ │ ├── dir4/ │ │ │ │ │ │ ├── Readme │ │ │ │ │ │ ├── cert11.crt │ │ │ │ │ │ ├── cert12.crt │ │ │ │ │ │ ├── cert13.crt │ │ │ │ │ │ ├── cert14.crt │ │ │ │ │ │ ├── cert21.crt │ │ │ │ │ │ ├── cert22.crt │ │ │ │ │ │ ├── cert23.crt │ │ │ │ │ │ ├── cert31.crt │ │ │ │ │ │ ├── cert32.crt │ │ │ │ │ │ ├── cert33.crt │ │ │ │ │ │ ├── cert34.crt │ │ │ │ │ │ ├── cert41.crt │ │ │ │ │ │ ├── cert42.crt │ │ │ │ │ │ ├── cert43.crt │ │ │ │ │ │ ├── cert44.crt │ │ │ │ │ │ ├── cert45.crt │ │ │ │ │ │ ├── cert51.crt │ │ │ │ │ │ ├── cert52.crt │ │ │ │ │ │ ├── cert53.crt │ │ │ │ │ │ ├── cert54.crt │ │ │ │ │ │ ├── cert61.crt │ │ │ │ │ │ ├── cert62.crt │ │ │ │ │ │ ├── cert63.crt │ │ │ │ │ │ ├── cert71.crt │ │ │ │ │ │ ├── cert72.crt │ │ │ │ │ │ ├── cert73.crt │ │ │ │ │ │ ├── cert74.crt │ │ │ │ │ │ ├── cert81.crt │ │ │ │ │ │ ├── cert82.crt │ │ │ │ │ │ ├── cert83.crt │ │ │ │ │ │ ├── cert91.crt │ │ │ │ │ │ └── cert92.crt │ │ │ │ │ ├── ec_224_prv.pem │ │ │ │ │ ├── ec_224_pub.pem │ │ │ │ │ ├── ec_256_prv.pem │ │ │ │ │ ├── ec_256_pub.pem │ │ │ │ │ ├── ec_384_prv.pem │ │ │ │ │ ├── ec_384_pub.pem │ │ │ │ │ ├── ec_521_prv.pem │ │ │ │ │ ├── ec_521_pub.pem │ │ │ │ │ ├── ec_bp256_prv.pem │ │ │ │ │ ├── ec_bp256_pub.pem │ │ │ │ │ ├── ec_bp384_prv.pem │ │ │ │ │ ├── ec_bp384_pub.pem │ │ │ │ │ ├── ec_bp512_prv.pem │ │ │ │ │ ├── ec_bp512_pub.pem │ │ │ │ │ ├── ec_prv.noopt.der │ │ │ │ │ ├── ec_prv.pk8.der │ │ │ │ │ ├── ec_prv.pk8.pem │ │ │ │ │ ├── ec_prv.pk8.pw.der │ │ │ │ │ ├── ec_prv.pk8.pw.pem │ │ │ │ │ ├── ec_prv.sec1.der │ │ │ │ │ ├── ec_prv.sec1.pem │ │ │ │ │ ├── ec_prv.sec1.pw.pem │ │ │ │ │ ├── ec_prv.specdom.der │ │ │ │ │ ├── ec_pub.der │ │ │ │ │ ├── ec_pub.pem │ │ │ │ │ ├── enco-ca-prstr.pem │ │ │ │ │ ├── enco-cert-utf8str.pem │ │ │ │ │ ├── format_gen.key │ │ │ │ │ ├── format_gen.pub │ │ │ │ │ ├── format_pkcs12.fmt │ │ │ │ │ ├── format_rsa.key │ │ │ │ │ ├── hash_file_1 │ │ │ │ │ ├── hash_file_2 │ │ │ │ │ ├── hash_file_3 │ │ │ │ │ ├── hash_file_4 │ │ │ │ │ ├── hash_file_5 │ │ │ │ │ ├── keyUsage.decipherOnly.crt │ │ │ │ │ ├── keyfile │ │ │ │ │ ├── keyfile.3des │ │ │ │ │ ├── keyfile.aes128 │ │ │ │ │ ├── keyfile.aes192 │ │ │ │ │ ├── keyfile.aes256 │ │ │ │ │ ├── keyfile.des │ │ │ │ │ ├── mpi_10 │ │ │ │ │ ├── mpi_too_big │ │ │ │ │ ├── passwd.psk │ │ │ │ │ ├── pkcs8_pbe_sha1_2des.key │ │ │ │ │ ├── pkcs8_pbe_sha1_3des.der │ │ │ │ │ ├── pkcs8_pbe_sha1_3des.key │ │ │ │ │ ├── pkcs8_pbe_sha1_rc4_128.key │ │ │ │ │ ├── pkcs8_pbes2_pbkdf2_3des.der │ │ │ │ │ ├── pkcs8_pbes2_pbkdf2_3des.key │ │ │ │ │ ├── pkcs8_pbes2_pbkdf2_des.key │ │ │ │ │ ├── print_c.pl │ │ │ │ │ ├── rsa4096_prv.pem │ │ │ │ │ ├── rsa4096_pub.pem │ │ │ │ │ ├── server1-nospace.crt │ │ │ │ │ ├── server1-v1.crt │ │ │ │ │ ├── server1.cert_type.crt │ │ │ │ │ ├── server1.crt │ │ │ │ │ ├── server1.ext_ku.crt │ │ │ │ │ ├── server1.key │ │ │ │ │ ├── server1.key_usage.crt │ │ │ │ │ ├── server1.pubkey │ │ │ │ │ ├── server1.req.cert_type │ │ │ │ │ ├── server1.req.key_usage │ │ │ │ │ ├── server1.req.ku-ct │ │ │ │ │ ├── server1.req.md4 │ │ │ │ │ ├── server1.req.md5 │ │ │ │ │ ├── server1.req.sha1 │ │ │ │ │ ├── server1.req.sha224 │ │ │ │ │ ├── server1.req.sha256 │ │ │ │ │ ├── server1.req.sha384 │ │ │ │ │ ├── server1.req.sha512 │ │ │ │ │ ├── server1.v1.crt │ │ │ │ │ ├── server10.key │ │ │ │ │ ├── server10_int3_int-ca2.crt │ │ │ │ │ ├── server10_int3_int-ca2_ca.crt │ │ │ │ │ ├── server1_ca.crt │ │ │ │ │ ├── server2-badsign.crt │ │ │ │ │ ├── server2-sha256.crt │ │ │ │ │ ├── server2-v1-chain.crt │ │ │ │ │ ├── server2-v1.crt │ │ │ │ │ ├── server2.crt │ │ │ │ │ ├── server2.key │ │ │ │ │ ├── server2.ku-ds.crt │ │ │ │ │ ├── server2.ku-ds_ke.crt │ │ │ │ │ ├── server2.ku-ka.crt │ │ │ │ │ ├── server2.ku-ke.crt │ │ │ │ │ ├── server3.crt │ │ │ │ │ ├── server3.key │ │ │ │ │ ├── server4.crt │ │ │ │ │ ├── server4.key │ │ │ │ │ ├── server5-badsign.crt │ │ │ │ │ ├── server5-der0.crt │ │ │ │ │ ├── server5-der1a.crt │ │ │ │ │ ├── server5-der1b.crt │ │ │ │ │ ├── server5-der2.crt │ │ │ │ │ ├── server5-der4.crt │ │ │ │ │ ├── server5-der8.crt │ │ │ │ │ ├── server5-der9.crt │ │ │ │ │ ├── server5-expired.crt │ │ │ │ │ ├── server5-future.crt │ │ │ │ │ ├── server5-selfsigned.crt │ │ │ │ │ ├── server5-sha1.crt │ │ │ │ │ ├── server5-sha224.crt │ │ │ │ │ ├── server5-sha384.crt │ │ │ │ │ ├── server5-sha512.crt │ │ │ │ │ ├── server5.crt │ │ │ │ │ ├── server5.eku-cli.crt │ │ │ │ │ ├── server5.eku-cs.crt │ │ │ │ │ ├── server5.eku-cs_any.crt │ │ │ │ │ ├── server5.eku-srv.crt │ │ │ │ │ ├── server5.eku-srv_cli.crt │ │ │ │ │ ├── server5.key │ │ │ │ │ ├── server5.ku-ds.crt │ │ │ │ │ ├── server5.ku-ka.crt │ │ │ │ │ ├── server5.ku-ke.crt │ │ │ │ │ ├── server5.req.ku.sha1 │ │ │ │ │ ├── server5.req.sha1 │ │ │ │ │ ├── server5.req.sha224 │ │ │ │ │ ├── server5.req.sha256 │ │ │ │ │ ├── server5.req.sha384 │ │ │ │ │ ├── server5.req.sha512 │ │ │ │ │ ├── server6-ss-child.crt │ │ │ │ │ ├── server6.crt │ │ │ │ │ ├── server6.key │ │ │ │ │ ├── server7.crt │ │ │ │ │ ├── server7.key │ │ │ │ │ ├── server7_all_space.crt │ │ │ │ │ ├── server7_int-ca.crt │ │ │ │ │ ├── server7_int-ca_ca2.crt │ │ │ │ │ ├── server7_pem_space.crt │ │ │ │ │ ├── server7_trailing_space.crt │ │ │ │ │ ├── server8.crt │ │ │ │ │ ├── server8.key │ │ │ │ │ ├── server8_int-ca2.crt │ │ │ │ │ ├── server9-bad-mgfhash.crt │ │ │ │ │ ├── server9-bad-saltlen.crt │ │ │ │ │ ├── server9-badsign.crt │ │ │ │ │ ├── server9-defaults.crt │ │ │ │ │ ├── server9-sha224.crt │ │ │ │ │ ├── server9-sha256.crt │ │ │ │ │ ├── server9-sha384.crt │ │ │ │ │ ├── server9-sha512.crt │ │ │ │ │ ├── server9-with-ca.crt │ │ │ │ │ ├── server9.crt │ │ │ │ │ ├── server9.key │ │ │ │ │ ├── server9.req.sha1 │ │ │ │ │ ├── server9.req.sha224 │ │ │ │ │ ├── server9.req.sha256 │ │ │ │ │ ├── server9.req.sha384 │ │ │ │ │ ├── server9.req.sha512 │ │ │ │ │ ├── test-ca-sha1.crt │ │ │ │ │ ├── test-ca-sha256.crt │ │ │ │ │ ├── test-ca-v1.crt │ │ │ │ │ ├── test-ca.crt │ │ │ │ │ ├── test-ca.key │ │ │ │ │ ├── test-ca.opensslconf │ │ │ │ │ ├── test-ca2.crt │ │ │ │ │ ├── test-ca2.key │ │ │ │ │ ├── test-ca2.ku-crl.crt │ │ │ │ │ ├── test-ca2.ku-crt.crt │ │ │ │ │ ├── test-ca2.ku-crt_crl.crt │ │ │ │ │ ├── test-ca2.ku-ds.crt │ │ │ │ │ ├── test-ca2_cat-future-invalid.crt │ │ │ │ │ ├── test-ca2_cat-future-present.crt │ │ │ │ │ ├── test-ca2_cat-past-invalid.crt │ │ │ │ │ ├── test-ca2_cat-past-present.crt │ │ │ │ │ ├── test-ca2_cat-present-future.crt │ │ │ │ │ ├── test-ca2_cat-present-past.crt │ │ │ │ │ ├── test-ca_cat12.crt │ │ │ │ │ ├── test-ca_cat21.crt │ │ │ │ │ ├── test-int-ca.crt │ │ │ │ │ ├── test-int-ca.key │ │ │ │ │ ├── test-int-ca2.crt │ │ │ │ │ ├── test-int-ca2.key │ │ │ │ │ ├── test-int-ca3.crt │ │ │ │ │ └── test-int-ca3.key │ │ │ │ ├── git-scripts/ │ │ │ │ │ ├── README.md │ │ │ │ │ └── pre-push.sh │ │ │ │ ├── scripts/ │ │ │ │ │ ├── all.sh │ │ │ │ │ ├── basic-build-test.sh │ │ │ │ │ ├── check-doxy-blocks.pl │ │ │ │ │ ├── check-generated-files.sh │ │ │ │ │ ├── check-names.sh │ │ │ │ │ ├── curves.pl │ │ │ │ │ ├── doxygen.sh │ │ │ │ │ ├── gen_ctr_drbg.pl │ │ │ │ │ ├── gen_gcm_decrypt.pl │ │ │ │ │ ├── gen_gcm_encrypt.pl │ │ │ │ │ ├── gen_pkcs1_v21_sign_verify.pl │ │ │ │ │ ├── generate-afl-tests.sh │ │ │ │ │ ├── generate_code.pl │ │ │ │ │ ├── key-exchanges.pl │ │ │ │ │ ├── list-enum-consts.pl │ │ │ │ │ ├── list-identifiers.sh │ │ │ │ │ ├── list-macros.sh │ │ │ │ │ ├── list-symbols.sh │ │ │ │ │ ├── recursion.pl │ │ │ │ │ ├── run-test-suites.pl │ │ │ │ │ ├── tcp_client.pl │ │ │ │ │ ├── test-ref-configs.pl │ │ │ │ │ ├── travis-log-failure.sh │ │ │ │ │ └── yotta-build.sh │ │ │ │ ├── ssl-opt.sh │ │ │ │ └── suites/ │ │ │ │ ├── helpers.function │ │ │ │ ├── main_test.function │ │ │ │ ├── test_suite_aes.cbc.data │ │ │ │ ├── test_suite_aes.cfb.data │ │ │ │ ├── test_suite_aes.ecb.data │ │ │ │ ├── test_suite_aes.function │ │ │ │ ├── test_suite_aes.rest.data │ │ │ │ ├── test_suite_arc4.data │ │ │ │ ├── test_suite_arc4.function │ │ │ │ ├── test_suite_asn1write.data │ │ │ │ ├── test_suite_asn1write.function │ │ │ │ ├── test_suite_base64.data │ │ │ │ ├── test_suite_base64.function │ │ │ │ ├── test_suite_blowfish.data │ │ │ │ ├── test_suite_blowfish.function │ │ │ │ ├── test_suite_camellia.data │ │ │ │ ├── test_suite_camellia.function │ │ │ │ ├── test_suite_ccm.data │ │ │ │ ├── test_suite_ccm.function │ │ │ │ ├── test_suite_cipher.aes.data │ │ │ │ ├── test_suite_cipher.arc4.data │ │ │ │ ├── test_suite_cipher.blowfish.data │ │ │ │ ├── test_suite_cipher.camellia.data │ │ │ │ ├── test_suite_cipher.ccm.data │ │ │ │ ├── test_suite_cipher.des.data │ │ │ │ ├── test_suite_cipher.function │ │ │ │ ├── test_suite_cipher.gcm.data │ │ │ │ ├── test_suite_cipher.null.data │ │ │ │ ├── test_suite_cipher.padding.data │ │ │ │ ├── test_suite_cmac.data │ │ │ │ ├── test_suite_cmac.function │ │ │ │ ├── test_suite_ctr_drbg.data │ │ │ │ ├── test_suite_ctr_drbg.function │ │ │ │ ├── test_suite_debug.data │ │ │ │ ├── test_suite_debug.function │ │ │ │ ├── test_suite_des.data │ │ │ │ ├── test_suite_des.function │ │ │ │ ├── test_suite_dhm.data │ │ │ │ ├── test_suite_dhm.function │ │ │ │ ├── test_suite_ecdh.data │ │ │ │ ├── test_suite_ecdh.function │ │ │ │ ├── test_suite_ecdsa.data │ │ │ │ ├── test_suite_ecdsa.function │ │ │ │ ├── test_suite_ecjpake.data │ │ │ │ ├── test_suite_ecjpake.function │ │ │ │ ├── test_suite_ecp.data │ │ │ │ ├── test_suite_ecp.function │ │ │ │ ├── test_suite_entropy.data │ │ │ │ ├── test_suite_entropy.function │ │ │ │ ├── test_suite_error.data │ │ │ │ ├── test_suite_error.function │ │ │ │ ├── test_suite_gcm.aes128_de.data │ │ │ │ ├── test_suite_gcm.aes128_en.data │ │ │ │ ├── test_suite_gcm.aes192_de.data │ │ │ │ ├── test_suite_gcm.aes192_en.data │ │ │ │ ├── test_suite_gcm.aes256_de.data │ │ │ │ ├── test_suite_gcm.aes256_en.data │ │ │ │ ├── test_suite_gcm.camellia.data │ │ │ │ ├── test_suite_gcm.function │ │ │ │ ├── test_suite_hmac_drbg.function │ │ │ │ ├── test_suite_hmac_drbg.misc.data │ │ │ │ ├── test_suite_hmac_drbg.no_reseed.data │ │ │ │ ├── test_suite_hmac_drbg.nopr.data │ │ │ │ ├── test_suite_hmac_drbg.pr.data │ │ │ │ ├── test_suite_md.data │ │ │ │ ├── test_suite_md.function │ │ │ │ ├── test_suite_mdx.data │ │ │ │ ├── test_suite_mdx.function │ │ │ │ ├── test_suite_memory_buffer_alloc.data │ │ │ │ ├── test_suite_memory_buffer_alloc.function │ │ │ │ ├── test_suite_mpi.data │ │ │ │ ├── test_suite_mpi.function │ │ │ │ ├── test_suite_pem.data │ │ │ │ ├── test_suite_pem.function │ │ │ │ ├── test_suite_pk.data │ │ │ │ ├── test_suite_pk.function │ │ │ │ ├── test_suite_pkcs1_v15.data │ │ │ │ ├── test_suite_pkcs1_v15.function │ │ │ │ ├── test_suite_pkcs1_v21.data │ │ │ │ ├── test_suite_pkcs1_v21.function │ │ │ │ ├── test_suite_pkcs5.data │ │ │ │ ├── test_suite_pkcs5.function │ │ │ │ ├── test_suite_pkparse.data │ │ │ │ ├── test_suite_pkparse.function │ │ │ │ ├── test_suite_pkwrite.data │ │ │ │ ├── test_suite_pkwrite.function │ │ │ │ ├── test_suite_rsa.data │ │ │ │ ├── test_suite_rsa.function │ │ │ │ ├── test_suite_shax.data │ │ │ │ ├── test_suite_shax.function │ │ │ │ ├── test_suite_ssl.data │ │ │ │ ├── test_suite_ssl.function │ │ │ │ ├── test_suite_timing.data │ │ │ │ ├── test_suite_timing.function │ │ │ │ ├── test_suite_version.data │ │ │ │ ├── test_suite_version.function │ │ │ │ ├── test_suite_x509parse.data │ │ │ │ ├── test_suite_x509parse.function │ │ │ │ ├── test_suite_x509write.data │ │ │ │ ├── test_suite_x509write.function │ │ │ │ ├── test_suite_xtea.data │ │ │ │ └── test_suite_xtea.function │ │ │ ├── visualc/ │ │ │ │ └── VS2010/ │ │ │ │ ├── aescrypt2.vcxproj │ │ │ │ ├── benchmark.vcxproj │ │ │ │ ├── cert_app.vcxproj │ │ │ │ ├── cert_req.vcxproj │ │ │ │ ├── cert_write.vcxproj │ │ │ │ ├── crl_app.vcxproj │ │ │ │ ├── crypt_and_hash.vcxproj │ │ │ │ ├── dh_client.vcxproj │ │ │ │ ├── dh_genprime.vcxproj │ │ │ │ ├── dh_server.vcxproj │ │ │ │ ├── dtls_client.vcxproj │ │ │ │ ├── dtls_server.vcxproj │ │ │ │ ├── ecdh_curve25519.vcxproj │ │ │ │ ├── ecdsa.vcxproj │ │ │ │ ├── gen_entropy.vcxproj │ │ │ │ ├── gen_key.vcxproj │ │ │ │ ├── gen_random_ctr_drbg.vcxproj │ │ │ │ ├── gen_random_havege.vcxproj │ │ │ │ ├── generic_sum.vcxproj │ │ │ │ ├── hello.vcxproj │ │ │ │ ├── key_app.vcxproj │ │ │ │ ├── key_app_writer.vcxproj │ │ │ │ ├── mbedTLS.sln │ │ │ │ ├── mbedTLS.vcxproj │ │ │ │ ├── md5sum.vcxproj │ │ │ │ ├── mini_client.vcxproj │ │ │ │ ├── mpi_demo.vcxproj │ │ │ │ ├── pem2der.vcxproj │ │ │ │ ├── pk_decrypt.vcxproj │ │ │ │ ├── pk_encrypt.vcxproj │ │ │ │ ├── pk_sign.vcxproj │ │ │ │ ├── pk_verify.vcxproj │ │ │ │ ├── req_app.vcxproj │ │ │ │ ├── rsa_decrypt.vcxproj │ │ │ │ ├── rsa_encrypt.vcxproj │ │ │ │ ├── rsa_genkey.vcxproj │ │ │ │ ├── rsa_sign.vcxproj │ │ │ │ ├── rsa_sign_pss.vcxproj │ │ │ │ ├── rsa_verify.vcxproj │ │ │ │ ├── rsa_verify_pss.vcxproj │ │ │ │ ├── selftest.vcxproj │ │ │ │ ├── sha1sum.vcxproj │ │ │ │ ├── sha2sum.vcxproj │ │ │ │ ├── ssl_cert_test.vcxproj │ │ │ │ ├── ssl_client1.vcxproj │ │ │ │ ├── ssl_client2.vcxproj │ │ │ │ ├── ssl_fork_server.vcxproj │ │ │ │ ├── ssl_mail_client.vcxproj │ │ │ │ ├── ssl_server.vcxproj │ │ │ │ ├── ssl_server2.vcxproj │ │ │ │ ├── strerror.vcxproj │ │ │ │ └── udp_proxy.vcxproj │ │ │ └── yotta/ │ │ │ ├── .gitignore │ │ │ ├── create-module.sh │ │ │ └── data/ │ │ │ ├── README.md │ │ │ ├── adjust-config.sh │ │ │ ├── entropy_hardware_poll.c │ │ │ ├── example-authcrypt/ │ │ │ │ ├── README.md │ │ │ │ └── main.cpp │ │ │ ├── example-benchmark/ │ │ │ │ ├── README.md │ │ │ │ └── main.cpp │ │ │ ├── example-hashing/ │ │ │ │ ├── README.md │ │ │ │ └── main.cpp │ │ │ ├── example-selftest/ │ │ │ │ ├── README.md │ │ │ │ └── main.cpp │ │ │ ├── module.json │ │ │ └── target_config.h │ │ └── mbedtls_port/ │ │ ├── dtls_interface.c │ │ ├── dtls_interface.h │ │ ├── entropy_hardware_poll.c │ │ ├── los_mbedtls_config.h │ │ ├── los_mbedtls_config_cert.h │ │ ├── los_mbedtls_config_psk.h │ │ ├── net_sockets_alt.c │ │ ├── timing_alt.c │ │ └── timing_alt.h │ ├── demos/ │ │ ├── agenttiny_lwm2m/ │ │ │ ├── agent_tiny_cmd_ioctl.c │ │ │ ├── agent_tiny_cmd_ioctl.h │ │ │ ├── agent_tiny_demo.c │ │ │ └── agent_tiny_demo.h │ │ ├── agenttiny_mqtt/ │ │ │ ├── agent_tiny_demo.c │ │ │ └── agent_tiny_demo.h │ │ ├── dtls_server/ │ │ │ ├── test_dtls_server.c │ │ │ └── test_dtls_server.h │ │ ├── fs/ │ │ │ ├── fatfs_demo.c │ │ │ ├── fs_common.c │ │ │ ├── fs_common.h │ │ │ └── spiffs_demo.c │ │ ├── ipv6_client/ │ │ │ └── client_demo.c │ │ ├── kernel/ │ │ │ ├── api/ │ │ │ │ ├── los_api_dynamic_mem.c │ │ │ │ ├── los_api_event.c │ │ │ │ ├── los_api_interrupt.c │ │ │ │ ├── los_api_list.c │ │ │ │ ├── los_api_msgqueue.c │ │ │ │ ├── los_api_mutex.c │ │ │ │ ├── los_api_sem.c │ │ │ │ ├── los_api_static_mem.c │ │ │ │ ├── los_api_systick.c │ │ │ │ ├── los_api_task.c │ │ │ │ ├── los_api_timer.c │ │ │ │ ├── los_demo_entry.c │ │ │ │ └── los_inspect_entry.c │ │ │ └── include/ │ │ │ ├── los_api_dynamic_mem.h │ │ │ ├── los_api_event.h │ │ │ ├── los_api_interrupt.h │ │ │ ├── los_api_list.h │ │ │ ├── los_api_msgqueue.h │ │ │ ├── los_api_mutex.h │ │ │ ├── los_api_sem.h │ │ │ ├── los_api_static_mem.h │ │ │ ├── los_api_systick.h │ │ │ ├── los_api_task.h │ │ │ ├── los_api_timer.h │ │ │ ├── los_demo_debug.h │ │ │ ├── los_demo_entry.h │ │ │ └── los_inspect_entry.h │ │ └── nbiot_without_atiny/ │ │ ├── nb_demo.c │ │ └── sota_demo.c │ ├── doc/ │ │ ├── Huawei_LiteOS_Developer_Guide_en.md │ │ ├── Huawei_LiteOS_Developer_Guide_zh.md │ │ ├── Huawei_LiteOS_SDK_Coap_LwM2M_Developer_Guide_en.md │ │ ├── Huawei_LiteOS_SDK_Coap_LwM2M_Developer_Guide_zh.md │ │ ├── Huawei_LiteOS_SDK_Developer_Guide.md │ │ ├── Huawei_LiteOS_SDK_MQTT_Developer_Guide.md │ │ ├── LiteOS_Code_Info.md │ │ ├── LiteOS_Commit_Message.md │ │ ├── LiteOS_Contribute_Guide_GitGUI.md │ │ ├── LiteOS_Supported_board_list.md │ │ └── meta/ │ │ ├── DevGuide/ │ │ │ └── readme.md │ │ └── guides/ │ │ └── readme.md │ ├── include/ │ │ ├── at_device/ │ │ │ └── bc95.h │ │ ├── at_frame/ │ │ │ ├── at_api.h │ │ │ └── at_main.h │ │ ├── atiny_error.h │ │ ├── atiny_lwm2m/ │ │ │ └── agenttiny.h │ │ ├── atiny_mqtt/ │ │ │ └── mqtt_client.h │ │ ├── fs/ │ │ │ ├── los_devfs.h │ │ │ ├── los_fatfs.h │ │ │ ├── los_kifs.h │ │ │ ├── los_ramfs.h │ │ │ ├── los_spiffs.h │ │ │ ├── los_vfs.h │ │ │ └── sys/ │ │ │ ├── errno.h │ │ │ ├── fcntl.h │ │ │ └── stat.h │ │ ├── log/ │ │ │ └── atiny_log.h │ │ ├── nb_iot/ │ │ │ └── los_nb_api.h │ │ ├── osdepends/ │ │ │ └── atiny_osdep.h │ │ ├── ota/ │ │ │ ├── hwpatch_errno.h │ │ │ ├── ota_api.h │ │ │ ├── package.h │ │ │ └── recover_image.h │ │ ├── sal/ │ │ │ └── atiny_socket.h │ │ └── sota/ │ │ └── sota.h │ ├── kernel/ │ │ ├── Makefile │ │ ├── base/ │ │ │ ├── Makefile │ │ │ ├── core/ │ │ │ │ ├── Makefile │ │ │ │ ├── los_priqueue.c │ │ │ │ ├── los_priqueue.inc │ │ │ │ ├── los_swtmr.c │ │ │ │ ├── los_swtmr.inc │ │ │ │ ├── los_sys.c │ │ │ │ ├── los_sys.inc │ │ │ │ ├── los_task.c │ │ │ │ ├── los_task.inc │ │ │ │ ├── los_tick.c │ │ │ │ ├── los_tick.inc │ │ │ │ ├── los_timeslice.c │ │ │ │ └── los_timeslice.inc │ │ │ ├── include/ │ │ │ │ ├── los_base.ph │ │ │ │ ├── los_err.ph │ │ │ │ ├── los_event.ph │ │ │ │ ├── los_heap.ph │ │ │ │ ├── los_list.ph │ │ │ │ ├── los_membox.ph │ │ │ │ ├── los_memcheck.ph │ │ │ │ ├── los_memory.ph │ │ │ │ ├── los_memstat.ph │ │ │ │ ├── los_multipledlinkhead.ph │ │ │ │ ├── los_mux.ph │ │ │ │ ├── los_printf.ph │ │ │ │ ├── los_priqueue.ph │ │ │ │ ├── los_queue.ph │ │ │ │ ├── los_sem.ph │ │ │ │ ├── los_slab.ph │ │ │ │ ├── los_swtmr.ph │ │ │ │ ├── los_sys.ph │ │ │ │ ├── los_task.ph │ │ │ │ ├── los_tick.ph │ │ │ │ ├── los_timeslice.ph │ │ │ │ └── los_typedef.ph │ │ │ ├── ipc/ │ │ │ │ ├── Makefile │ │ │ │ ├── los_event.c │ │ │ │ ├── los_event.inc │ │ │ │ ├── los_mux.c │ │ │ │ ├── los_mux.inc │ │ │ │ ├── los_queue.c │ │ │ │ ├── los_queue.inc │ │ │ │ ├── los_sem.c │ │ │ │ └── los_sem.inc │ │ │ ├── mem/ │ │ │ │ ├── Makefile │ │ │ │ ├── bestfit/ │ │ │ │ │ ├── los_memory.c │ │ │ │ │ ├── los_memory.inc │ │ │ │ │ ├── los_multipledlinkhead.c │ │ │ │ │ └── los_multipledlinkhead.inc │ │ │ │ ├── bestfit_little/ │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── los_heap.c │ │ │ │ │ └── los_memory.c │ │ │ │ ├── common/ │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── los_memcheck.c │ │ │ │ │ ├── los_memstat.c │ │ │ │ │ ├── los_memstat.inc │ │ │ │ │ ├── los_slab.c │ │ │ │ │ └── los_slabmem.c │ │ │ │ ├── membox/ │ │ │ │ │ └── los_membox.c │ │ │ │ └── tlsf/ │ │ │ │ ├── Makefile │ │ │ │ └── los_memory.c │ │ │ ├── misc/ │ │ │ │ ├── Makefile │ │ │ │ └── los_misc.c │ │ │ └── om/ │ │ │ ├── Makefile │ │ │ ├── los_err.c │ │ │ └── los_err.inc │ │ ├── extended/ │ │ │ ├── Makefile │ │ │ ├── include/ │ │ │ │ └── los_tickless.ph │ │ │ └── tickless/ │ │ │ ├── los_tickless.c │ │ │ └── los_tickless.inc │ │ ├── include/ │ │ │ ├── los_base.h │ │ │ ├── los_compiler.h │ │ │ ├── los_config.h │ │ │ ├── los_err.h │ │ │ ├── los_errno.h │ │ │ ├── los_event.h │ │ │ ├── los_heap.h │ │ │ ├── los_list.h │ │ │ ├── los_membox.h │ │ │ ├── los_memcheck.h │ │ │ ├── los_memory.h │ │ │ ├── los_mux.h │ │ │ ├── los_queue.h │ │ │ ├── los_sem.h │ │ │ ├── los_slab.h │ │ │ ├── los_swtmr.h │ │ │ ├── los_sys.h │ │ │ ├── los_task.h │ │ │ ├── los_tick.h │ │ │ ├── los_tickless.h │ │ │ └── los_typedef.h │ │ └── los_init.c │ ├── osdepends/ │ │ └── liteos/ │ │ ├── atiny_osdep.c │ │ └── cmsis/ │ │ ├── 1.0/ │ │ │ ├── cmsis_liteos1.c │ │ │ └── cmsis_os1.h │ │ ├── 2.0/ │ │ │ ├── cmsis_liteos2.c │ │ │ └── cmsis_os2.h │ │ ├── Makefile │ │ ├── THIRD PARTY OPEN SOURCE SOFTWARE NOTICE.docx │ │ ├── cmsis_liteos.c │ │ └── cmsis_os.h │ ├── targets/ │ │ ├── Cloud_STM32F429IGTx_FIRE/ │ │ │ ├── Drivers/ │ │ │ │ ├── STM32F4xx_HAL_Driver/ │ │ │ │ │ ├── Inc/ │ │ │ │ │ │ ├── Legacy/ │ │ │ │ │ │ │ ├── stm32_hal_legacy.h │ │ │ │ │ │ │ └── stm32f4xx_hal_can_legacy.h │ │ │ │ │ │ ├── stm32_assert_template.h │ │ │ │ │ │ ├── stm32f4xx_hal.h │ │ │ │ │ │ ├── stm32f4xx_hal_adc.h │ │ │ │ │ │ ├── stm32f4xx_hal_adc_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_can.h │ │ │ │ │ │ ├── stm32f4xx_hal_cec.h │ │ │ │ │ │ ├── stm32f4xx_hal_conf_template.h │ │ │ │ │ │ ├── stm32f4xx_hal_cortex.h │ │ │ │ │ │ ├── stm32f4xx_hal_crc.h │ │ │ │ │ │ ├── stm32f4xx_hal_cryp.h │ │ │ │ │ │ ├── stm32f4xx_hal_cryp_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_dac.h │ │ │ │ │ │ ├── stm32f4xx_hal_dac_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_dcmi.h │ │ │ │ │ │ ├── stm32f4xx_hal_dcmi_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_def.h │ │ │ │ │ │ ├── stm32f4xx_hal_dfsdm.h │ │ │ │ │ │ ├── stm32f4xx_hal_dma.h │ │ │ │ │ │ ├── stm32f4xx_hal_dma2d.h │ │ │ │ │ │ ├── stm32f4xx_hal_dma_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_dsi.h │ │ │ │ │ │ ├── stm32f4xx_hal_eth.h │ │ │ │ │ │ ├── stm32f4xx_hal_flash.h │ │ │ │ │ │ ├── stm32f4xx_hal_flash_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_flash_ramfunc.h │ │ │ │ │ │ ├── stm32f4xx_hal_fmpi2c.h │ │ │ │ │ │ ├── stm32f4xx_hal_fmpi2c_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_gpio.h │ │ │ │ │ │ ├── stm32f4xx_hal_gpio_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_hash.h │ │ │ │ │ │ ├── stm32f4xx_hal_hash_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_hcd.h │ │ │ │ │ │ ├── stm32f4xx_hal_i2c.h │ │ │ │ │ │ ├── stm32f4xx_hal_i2c_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_i2s.h │ │ │ │ │ │ ├── stm32f4xx_hal_i2s_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_irda.h │ │ │ │ │ │ ├── stm32f4xx_hal_iwdg.h │ │ │ │ │ │ ├── stm32f4xx_hal_lptim.h │ │ │ │ │ │ ├── stm32f4xx_hal_ltdc.h │ │ │ │ │ │ ├── stm32f4xx_hal_ltdc_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_mmc.h │ │ │ │ │ │ ├── stm32f4xx_hal_nand.h │ │ │ │ │ │ ├── stm32f4xx_hal_nor.h │ │ │ │ │ │ ├── stm32f4xx_hal_pccard.h │ │ │ │ │ │ ├── stm32f4xx_hal_pcd.h │ │ │ │ │ │ ├── stm32f4xx_hal_pcd_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_pwr.h │ │ │ │ │ │ ├── stm32f4xx_hal_pwr_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_qspi.h │ │ │ │ │ │ ├── stm32f4xx_hal_rcc.h │ │ │ │ │ │ ├── stm32f4xx_hal_rcc_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_rng.h │ │ │ │ │ │ ├── stm32f4xx_hal_rtc.h │ │ │ │ │ │ ├── stm32f4xx_hal_rtc_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_sai.h │ │ │ │ │ │ ├── stm32f4xx_hal_sai_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_sd.h │ │ │ │ │ │ ├── stm32f4xx_hal_sdram.h │ │ │ │ │ │ ├── stm32f4xx_hal_smartcard.h │ │ │ │ │ │ ├── stm32f4xx_hal_spdifrx.h │ │ │ │ │ │ ├── stm32f4xx_hal_spi.h │ │ │ │ │ │ ├── stm32f4xx_hal_sram.h │ │ │ │ │ │ ├── stm32f4xx_hal_tim.h │ │ │ │ │ │ ├── stm32f4xx_hal_tim_ex.h │ │ │ │ │ │ ├── stm32f4xx_hal_uart.h │ │ │ │ │ │ ├── stm32f4xx_hal_usart.h │ │ │ │ │ │ └── stm32f4xx_hal_wwdg.h │ │ │ │ │ └── Src/ │ │ │ │ │ ├── stm32f4xx_hal.c │ │ │ │ │ ├── stm32f4xx_hal_adc.c │ │ │ │ │ ├── stm32f4xx_hal_adc_ex.c │ │ │ │ │ ├── stm32f4xx_hal_can.c │ │ │ │ │ ├── stm32f4xx_hal_cec.c │ │ │ │ │ ├── stm32f4xx_hal_cortex.c │ │ │ │ │ ├── stm32f4xx_hal_crc.c │ │ │ │ │ ├── stm32f4xx_hal_cryp.c │ │ │ │ │ ├── stm32f4xx_hal_cryp_ex.c │ │ │ │ │ ├── stm32f4xx_hal_dac.c │ │ │ │ │ ├── stm32f4xx_hal_dac_ex.c │ │ │ │ │ ├── stm32f4xx_hal_dcmi.c │ │ │ │ │ ├── stm32f4xx_hal_dcmi_ex.c │ │ │ │ │ ├── stm32f4xx_hal_dfsdm.c │ │ │ │ │ ├── stm32f4xx_hal_dma.c │ │ │ │ │ ├── stm32f4xx_hal_dma2d.c │ │ │ │ │ ├── stm32f4xx_hal_dma_ex.c │ │ │ │ │ ├── stm32f4xx_hal_dsi.c │ │ │ │ │ ├── stm32f4xx_hal_eth.c │ │ │ │ │ ├── stm32f4xx_hal_flash.c │ │ │ │ │ ├── stm32f4xx_hal_flash_ex.c │ │ │ │ │ ├── stm32f4xx_hal_flash_ramfunc.c │ │ │ │ │ ├── stm32f4xx_hal_fmpi2c.c │ │ │ │ │ ├── stm32f4xx_hal_fmpi2c_ex.c │ │ │ │ │ ├── stm32f4xx_hal_gpio.c │ │ │ │ │ ├── stm32f4xx_hal_hash.c │ │ │ │ │ ├── stm32f4xx_hal_hash_ex.c │ │ │ │ │ ├── stm32f4xx_hal_hcd.c │ │ │ │ │ ├── stm32f4xx_hal_i2c.c │ │ │ │ │ ├── stm32f4xx_hal_i2c_ex.c │ │ │ │ │ ├── stm32f4xx_hal_i2s.c │ │ │ │ │ ├── stm32f4xx_hal_i2s_ex.c │ │ │ │ │ ├── stm32f4xx_hal_irda.c │ │ │ │ │ ├── stm32f4xx_hal_iwdg.c │ │ │ │ │ ├── stm32f4xx_hal_lptim.c │ │ │ │ │ ├── stm32f4xx_hal_ltdc.c │ │ │ │ │ ├── stm32f4xx_hal_ltdc_ex.c │ │ │ │ │ ├── stm32f4xx_hal_mmc.c │ │ │ │ │ ├── stm32f4xx_hal_msp_template.c │ │ │ │ │ ├── stm32f4xx_hal_nand.c │ │ │ │ │ ├── stm32f4xx_hal_nor.c │ │ │ │ │ ├── stm32f4xx_hal_pccard.c │ │ │ │ │ ├── stm32f4xx_hal_pcd.c │ │ │ │ │ ├── stm32f4xx_hal_pcd_ex.c │ │ │ │ │ ├── stm32f4xx_hal_pwr.c │ │ │ │ │ ├── stm32f4xx_hal_pwr_ex.c │ │ │ │ │ ├── stm32f4xx_hal_qspi.c │ │ │ │ │ ├── stm32f4xx_hal_rcc.c │ │ │ │ │ ├── stm32f4xx_hal_rcc_ex.c │ │ │ │ │ ├── stm32f4xx_hal_rng.c │ │ │ │ │ ├── stm32f4xx_hal_rtc.c │ │ │ │ │ ├── stm32f4xx_hal_rtc_ex.c │ │ │ │ │ ├── stm32f4xx_hal_sai.c │ │ │ │ │ ├── stm32f4xx_hal_sai_ex.c │ │ │ │ │ ├── stm32f4xx_hal_sd.c │ │ │ │ │ ├── stm32f4xx_hal_sdram.c │ │ │ │ │ ├── stm32f4xx_hal_smartcard.c │ │ │ │ │ ├── stm32f4xx_hal_spdifrx.c │ │ │ │ │ ├── stm32f4xx_hal_spi.c │ │ │ │ │ ├── stm32f4xx_hal_sram.c │ │ │ │ │ ├── stm32f4xx_hal_tim.c │ │ │ │ │ ├── stm32f4xx_hal_tim_ex.c │ │ │ │ │ ├── stm32f4xx_hal_timebase_rtc_alarm_template.c │ │ │ │ │ ├── stm32f4xx_hal_timebase_rtc_wakeup_template.c │ │ │ │ │ ├── stm32f4xx_hal_timebase_tim_template.c │ │ │ │ │ ├── stm32f4xx_hal_uart.c │ │ │ │ │ ├── stm32f4xx_hal_usart.c │ │ │ │ │ └── stm32f4xx_hal_wwdg.c │ │ │ │ └── THIRD PARTY OPEN SOURCE SOFTWARE NOTICE.docx │ │ │ ├── EWARM/ │ │ │ │ ├── Huawei_LiteOS.ewd │ │ │ │ ├── Huawei_LiteOS.ewp │ │ │ │ ├── Huawei_LiteOS.eww │ │ │ │ ├── STM32F429IGTx-LiteOS.icf │ │ │ │ └── los_startup_iar.s │ │ │ ├── GCC/ │ │ │ │ ├── Makefile │ │ │ │ ├── Makefile_Sota │ │ │ │ ├── STM32F429IGTx_LiteOS.ld │ │ │ │ ├── STM32F429IGTx_LiteOS_bootloader.ld │ │ │ │ ├── config.mk │ │ │ │ ├── config_demos/ │ │ │ │ │ ├── config_bootloader.mk │ │ │ │ │ ├── config_lwm2m.mk │ │ │ │ │ ├── config_mqtt.mk │ │ │ │ │ ├── config_sota.mk │ │ │ │ │ └── config_sota_without_checksum.mk │ │ │ │ ├── los_startup_gcc.s │ │ │ │ └── prune.mk │ │ │ ├── Hardware/ │ │ │ │ ├── Inc/ │ │ │ │ │ ├── hal_flash.h │ │ │ │ │ ├── hal_iwdg.h │ │ │ │ │ ├── hal_rng.h │ │ │ │ │ └── hal_spi_flash.h │ │ │ │ └── Src/ │ │ │ │ ├── hal_flash.c │ │ │ │ ├── hal_iwdg.c │ │ │ │ ├── hal_rng.c │ │ │ │ └── hal_spi_flash.c │ │ │ ├── Inc/ │ │ │ │ ├── at_hal.h │ │ │ │ ├── board.h │ │ │ │ ├── common.h │ │ │ │ ├── dwt.h │ │ │ │ ├── eth.h │ │ │ │ ├── flash_adaptor.h │ │ │ │ ├── main.h │ │ │ │ ├── ota_port.h │ │ │ │ ├── stm32f429xx.h │ │ │ │ ├── stm32f4xx.h │ │ │ │ ├── stm32f4xx_hal_conf.h │ │ │ │ ├── sys_init.h │ │ │ │ ├── system_stm32f4xx.h │ │ │ │ └── usart.h │ │ │ ├── Lib/ │ │ │ │ ├── hwpatch.lib │ │ │ │ ├── hwpatch_iar.a │ │ │ │ └── libhwpatch.a │ │ │ ├── MDK-ARM/ │ │ │ │ ├── Huawei_LiteOS.uvoptx │ │ │ │ ├── Huawei_LiteOS.uvprojx │ │ │ │ ├── STM32F429IGTx-LiteOS.sct │ │ │ │ └── los_startup_keil.s │ │ │ ├── OS_CONFIG/ │ │ │ │ ├── los_builddef.h │ │ │ │ ├── los_printf.h │ │ │ │ └── target_config.h │ │ │ └── Src/ │ │ │ ├── at_hal.c │ │ │ ├── board.c │ │ │ ├── bootloader_recover.c │ │ │ ├── dwt.c │ │ │ ├── eth.c │ │ │ ├── fatfs_hal.c │ │ │ ├── flash_adaptor.c │ │ │ ├── main.c │ │ │ ├── ota_port.c │ │ │ ├── spiffs_hal.c │ │ │ ├── sys_init.c │ │ │ ├── system_stm32f4xx.c │ │ │ ├── usart.c │ │ │ └── user_task.c │ │ ├── Mini_Project/ │ │ │ ├── cortex-m0plus_without_driver/ │ │ │ │ ├── GCC/ │ │ │ │ │ ├── LPC51U68_flash.ld │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── config.mk │ │ │ │ │ ├── prune.mk │ │ │ │ │ └── startup_LPC51U68.s │ │ │ │ ├── Inc/ │ │ │ │ │ ├── __hal_simulate.h │ │ │ │ │ ├── main.h │ │ │ │ │ ├── ota_port.h │ │ │ │ │ └── sys_init.h │ │ │ │ ├── OS_CONFIG/ │ │ │ │ │ ├── los_builddef.h │ │ │ │ │ ├── los_printf.h │ │ │ │ │ └── target_config.h │ │ │ │ └── Src/ │ │ │ │ ├── __hal_simulate.c │ │ │ │ ├── main.c │ │ │ │ └── user_task.c │ │ │ ├── cortex-m3_without_driver/ │ │ │ │ ├── GCC/ │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── config.mk │ │ │ │ │ ├── cortex-m3.ld │ │ │ │ │ ├── los_startup_gcc.s │ │ │ │ │ └── prune.mk │ │ │ │ ├── Inc/ │ │ │ │ │ ├── __hal_simulate.h │ │ │ │ │ ├── main.h │ │ │ │ │ ├── ota_port.h │ │ │ │ │ └── sys_init.h │ │ │ │ ├── OS_CONFIG/ │ │ │ │ │ ├── los_builddef.h │ │ │ │ │ ├── los_printf.h │ │ │ │ │ └── target_config.h │ │ │ │ └── Src/ │ │ │ │ ├── __hal_simulate.c │ │ │ │ ├── main.c │ │ │ │ └── user_task.c │ │ │ └── cortex-m4_without_driver/ │ │ │ ├── GCC/ │ │ │ │ ├── Makefile │ │ │ │ ├── config.mk │ │ │ │ ├── cortex-m4.ld │ │ │ │ ├── los_startup_gcc.s │ │ │ │ └── prune.mk │ │ │ ├── Inc/ │ │ │ │ ├── __hal_simulate.h │ │ │ │ ├── main.h │ │ │ │ ├── ota_port.h │ │ │ │ └── sys_init.h │ │ │ ├── Lib/ │ │ │ │ ├── hwpatch.lib │ │ │ │ └── libhwpatch.a │ │ │ ├── OS_CONFIG/ │ │ │ │ ├── los_builddef.h │ │ │ │ ├── los_printf.h │ │ │ │ └── target_config.h │ │ │ ├── Src/ │ │ │ │ ├── __hal_simulate.c │ │ │ │ ├── main.c │ │ │ │ └── user_task.c │ │ │ └── cortex-m4-without-driver.doc │ │ ├── NXP_LPC51U68/ │ │ │ ├── Driver/ │ │ │ │ ├── LPC51U68/ │ │ │ │ │ ├── LPC51U68.h │ │ │ │ │ ├── LPC51U68.xml │ │ │ │ │ ├── LPC51U68_features.h │ │ │ │ │ ├── cmsis_drivers/ │ │ │ │ │ │ ├── fsl_i2c_cmsis.c │ │ │ │ │ │ ├── fsl_i2c_cmsis.h │ │ │ │ │ │ ├── fsl_spi_cmsis.c │ │ │ │ │ │ ├── fsl_spi_cmsis.h │ │ │ │ │ │ ├── fsl_usart_cmsis.c │ │ │ │ │ │ └── fsl_usart_cmsis.h │ │ │ │ │ ├── drivers/ │ │ │ │ │ │ ├── fsl_adc.c │ │ │ │ │ │ ├── fsl_adc.h │ │ │ │ │ │ ├── fsl_clock.c │ │ │ │ │ │ ├── fsl_clock.h │ │ │ │ │ │ ├── fsl_common.c │ │ │ │ │ │ ├── fsl_common.h │ │ │ │ │ │ ├── fsl_crc.c │ │ │ │ │ │ ├── fsl_crc.h │ │ │ │ │ │ ├── fsl_ctimer.c │ │ │ │ │ │ ├── fsl_ctimer.h │ │ │ │ │ │ ├── fsl_dma.c │ │ │ │ │ │ ├── fsl_dma.h │ │ │ │ │ │ ├── fsl_flashiap.c │ │ │ │ │ │ ├── fsl_flashiap.h │ │ │ │ │ │ ├── fsl_flexcomm.c │ │ │ │ │ │ ├── fsl_flexcomm.h │ │ │ │ │ │ ├── fsl_fmeas.c │ │ │ │ │ │ ├── fsl_fmeas.h │ │ │ │ │ │ ├── fsl_gint.c │ │ │ │ │ │ ├── fsl_gint.h │ │ │ │ │ │ ├── fsl_gpio.c │ │ │ │ │ │ ├── fsl_gpio.h │ │ │ │ │ │ ├── fsl_i2c.c │ │ │ │ │ │ ├── fsl_i2c.h │ │ │ │ │ │ ├── fsl_i2c_dma.c │ │ │ │ │ │ ├── fsl_i2c_dma.h │ │ │ │ │ │ ├── fsl_i2s.c │ │ │ │ │ │ ├── fsl_i2s.h │ │ │ │ │ │ ├── fsl_i2s_dma.c │ │ │ │ │ │ ├── fsl_i2s_dma.h │ │ │ │ │ │ ├── fsl_inputmux.c │ │ │ │ │ │ ├── fsl_inputmux.h │ │ │ │ │ │ ├── fsl_inputmux_connections.h │ │ │ │ │ │ ├── fsl_iocon.h │ │ │ │ │ │ ├── fsl_mrt.c │ │ │ │ │ │ ├── fsl_mrt.h │ │ │ │ │ │ ├── fsl_pint.c │ │ │ │ │ │ ├── fsl_pint.h │ │ │ │ │ │ ├── fsl_power.c │ │ │ │ │ │ ├── fsl_power.h │ │ │ │ │ │ ├── fsl_reset.c │ │ │ │ │ │ ├── fsl_reset.h │ │ │ │ │ │ ├── fsl_rtc.c │ │ │ │ │ │ ├── fsl_rtc.h │ │ │ │ │ │ ├── fsl_sctimer.c │ │ │ │ │ │ ├── fsl_sctimer.h │ │ │ │ │ │ ├── fsl_spi.c │ │ │ │ │ │ ├── fsl_spi.h │ │ │ │ │ │ ├── fsl_spi_dma.c │ │ │ │ │ │ ├── fsl_spi_dma.h │ │ │ │ │ │ ├── fsl_usart.c │ │ │ │ │ │ ├── fsl_usart.h │ │ │ │ │ │ ├── fsl_usart_dma.c │ │ │ │ │ │ ├── fsl_usart_dma.h │ │ │ │ │ │ ├── fsl_utick.c │ │ │ │ │ │ ├── fsl_utick.h │ │ │ │ │ │ ├── fsl_wwdt.c │ │ │ │ │ │ └── fsl_wwdt.h │ │ │ │ │ ├── fsl_device_registers.h │ │ │ │ │ ├── gcc/ │ │ │ │ │ │ ├── LPC51U68_flash.ld │ │ │ │ │ │ ├── LPC51U68_ram.ld │ │ │ │ │ │ ├── libpower.a │ │ │ │ │ │ └── startup_LPC51U68.S │ │ │ │ │ ├── project_template/ │ │ │ │ │ │ ├── board.c │ │ │ │ │ │ ├── board.h │ │ │ │ │ │ ├── clock_config.c │ │ │ │ │ │ ├── clock_config.h │ │ │ │ │ │ ├── peripherals.c │ │ │ │ │ │ ├── peripherals.h │ │ │ │ │ │ ├── pin_mux.c │ │ │ │ │ │ └── pin_mux.h │ │ │ │ │ ├── system_LPC51U68.c │ │ │ │ │ ├── system_LPC51U68.h │ │ │ │ │ ├── template/ │ │ │ │ │ │ └── RTE_Device.h │ │ │ │ │ └── utilities/ │ │ │ │ │ ├── fsl_assert.c │ │ │ │ │ ├── fsl_debug_console.c │ │ │ │ │ ├── fsl_debug_console.h │ │ │ │ │ ├── fsl_debug_console_conf.h │ │ │ │ │ ├── fsl_notifier.c │ │ │ │ │ ├── fsl_notifier.h │ │ │ │ │ ├── fsl_shell.c │ │ │ │ │ ├── fsl_shell.h │ │ │ │ │ ├── io/ │ │ │ │ │ │ ├── fsl_io.c │ │ │ │ │ │ └── fsl_io.h │ │ │ │ │ ├── log/ │ │ │ │ │ │ ├── fsl_log.c │ │ │ │ │ │ └── fsl_log.h │ │ │ │ │ └── str/ │ │ │ │ │ ├── fsl_str.c │ │ │ │ │ └── fsl_str.h │ │ │ │ ├── THIRD PARTY OPEN SOURCE SOFTWARE NOTICE.docx │ │ │ │ └── board/ │ │ │ │ ├── board.c │ │ │ │ ├── board.h │ │ │ │ ├── clock_config.c │ │ │ │ ├── clock_config.h │ │ │ │ ├── example.xml │ │ │ │ ├── hello_world.bak │ │ │ │ ├── hello_world.xml │ │ │ │ ├── libpower.a │ │ │ │ ├── pin_mux.c │ │ │ │ ├── pin_mux.h │ │ │ │ └── readme.txt │ │ │ ├── GCC/ │ │ │ │ ├── LPC51U68_flash.ld │ │ │ │ ├── Makefile │ │ │ │ ├── config.mk │ │ │ │ ├── prune.mk │ │ │ │ └── startup_LPC51U68.s │ │ │ ├── Inc/ │ │ │ │ ├── main.h │ │ │ │ └── ota_port.h │ │ │ ├── OS_CONFIG/ │ │ │ │ ├── los_builddef.h │ │ │ │ ├── los_printf.h │ │ │ │ └── target_config.h │ │ │ └── Src/ │ │ │ ├── ENC28J60.c │ │ │ ├── ENC28J60.h │ │ │ ├── ethernetif.c │ │ │ ├── main.c │ │ │ └── uart.c │ │ └── STM32F103VET6_NB_GCC/ │ │ ├── .mxproject │ │ ├── Drivers/ │ │ │ ├── CMSIS/ │ │ │ │ └── Device/ │ │ │ │ └── ST/ │ │ │ │ └── STM32F1xx/ │ │ │ │ └── Include/ │ │ │ │ ├── stm32f103x6.h │ │ │ │ ├── stm32f103xb.h │ │ │ │ ├── stm32f103xe.h │ │ │ │ ├── stm32f103xg.h │ │ │ │ ├── stm32f1xx.h │ │ │ │ └── system_stm32f1xx.h │ │ │ └── STM32F1xx_HAL_Driver/ │ │ │ ├── Inc/ │ │ │ │ ├── Legacy/ │ │ │ │ │ └── stm32_hal_legacy.h │ │ │ │ ├── stm32_assert_template.h │ │ │ │ ├── stm32f1xx_hal.h │ │ │ │ ├── stm32f1xx_hal_adc.h │ │ │ │ ├── stm32f1xx_hal_adc_ex.h │ │ │ │ ├── stm32f1xx_hal_can.h │ │ │ │ ├── stm32f1xx_hal_can_ex.h │ │ │ │ ├── stm32f1xx_hal_cec.h │ │ │ │ ├── stm32f1xx_hal_conf_template.h │ │ │ │ ├── stm32f1xx_hal_cortex.h │ │ │ │ ├── stm32f1xx_hal_crc.h │ │ │ │ ├── stm32f1xx_hal_dac.h │ │ │ │ ├── stm32f1xx_hal_dac_ex.h │ │ │ │ ├── stm32f1xx_hal_def.h │ │ │ │ ├── stm32f1xx_hal_dma.h │ │ │ │ ├── stm32f1xx_hal_dma_ex.h │ │ │ │ ├── stm32f1xx_hal_eth.h │ │ │ │ ├── stm32f1xx_hal_flash.h │ │ │ │ ├── stm32f1xx_hal_flash_ex.h │ │ │ │ ├── stm32f1xx_hal_gpio.h │ │ │ │ ├── stm32f1xx_hal_gpio_ex.h │ │ │ │ ├── stm32f1xx_hal_hcd.h │ │ │ │ ├── stm32f1xx_hal_i2c.h │ │ │ │ ├── stm32f1xx_hal_i2s.h │ │ │ │ ├── stm32f1xx_hal_irda.h │ │ │ │ ├── stm32f1xx_hal_iwdg.h │ │ │ │ ├── stm32f1xx_hal_mmc.h │ │ │ │ ├── stm32f1xx_hal_nand.h │ │ │ │ ├── stm32f1xx_hal_nor.h │ │ │ │ ├── stm32f1xx_hal_pccard.h │ │ │ │ ├── stm32f1xx_hal_pcd.h │ │ │ │ ├── stm32f1xx_hal_pcd_ex.h │ │ │ │ ├── stm32f1xx_hal_pwr.h │ │ │ │ ├── stm32f1xx_hal_rcc.h │ │ │ │ ├── stm32f1xx_hal_rcc_ex.h │ │ │ │ ├── stm32f1xx_hal_rtc.h │ │ │ │ ├── stm32f1xx_hal_rtc_ex.h │ │ │ │ ├── stm32f1xx_hal_sd.h │ │ │ │ ├── stm32f1xx_hal_smartcard.h │ │ │ │ ├── stm32f1xx_hal_spi.h │ │ │ │ ├── stm32f1xx_hal_sram.h │ │ │ │ ├── stm32f1xx_hal_tim.h │ │ │ │ ├── stm32f1xx_hal_tim_ex.h │ │ │ │ ├── stm32f1xx_hal_uart.h │ │ │ │ ├── stm32f1xx_hal_usart.h │ │ │ │ ├── stm32f1xx_hal_wwdg.h │ │ │ │ ├── stm32f1xx_ll_adc.h │ │ │ │ ├── stm32f1xx_ll_bus.h │ │ │ │ ├── stm32f1xx_ll_cortex.h │ │ │ │ ├── stm32f1xx_ll_crc.h │ │ │ │ ├── stm32f1xx_ll_dac.h │ │ │ │ ├── stm32f1xx_ll_dma.h │ │ │ │ ├── stm32f1xx_ll_exti.h │ │ │ │ ├── stm32f1xx_ll_fsmc.h │ │ │ │ ├── stm32f1xx_ll_gpio.h │ │ │ │ ├── stm32f1xx_ll_i2c.h │ │ │ │ ├── stm32f1xx_ll_iwdg.h │ │ │ │ ├── stm32f1xx_ll_pwr.h │ │ │ │ ├── stm32f1xx_ll_rcc.h │ │ │ │ ├── stm32f1xx_ll_rtc.h │ │ │ │ ├── stm32f1xx_ll_sdmmc.h │ │ │ │ ├── stm32f1xx_ll_spi.h │ │ │ │ ├── stm32f1xx_ll_system.h │ │ │ │ ├── stm32f1xx_ll_tim.h │ │ │ │ ├── stm32f1xx_ll_usart.h │ │ │ │ ├── stm32f1xx_ll_usb.h │ │ │ │ ├── stm32f1xx_ll_utils.h │ │ │ │ └── stm32f1xx_ll_wwdg.h │ │ │ └── Src/ │ │ │ ├── stm32f1xx_hal.c │ │ │ ├── stm32f1xx_hal_adc.c │ │ │ ├── stm32f1xx_hal_adc_ex.c │ │ │ ├── stm32f1xx_hal_can.c │ │ │ ├── stm32f1xx_hal_cec.c │ │ │ ├── stm32f1xx_hal_cortex.c │ │ │ ├── stm32f1xx_hal_crc.c │ │ │ ├── stm32f1xx_hal_dac.c │ │ │ ├── stm32f1xx_hal_dac_ex.c │ │ │ ├── stm32f1xx_hal_dma.c │ │ │ ├── stm32f1xx_hal_eth.c │ │ │ ├── stm32f1xx_hal_flash.c │ │ │ ├── stm32f1xx_hal_flash_ex.c │ │ │ ├── stm32f1xx_hal_gpio.c │ │ │ ├── stm32f1xx_hal_gpio_ex.c │ │ │ ├── stm32f1xx_hal_hcd.c │ │ │ ├── stm32f1xx_hal_i2c.c │ │ │ ├── stm32f1xx_hal_i2s.c │ │ │ ├── stm32f1xx_hal_irda.c │ │ │ ├── stm32f1xx_hal_iwdg.c │ │ │ ├── stm32f1xx_hal_mmc.c │ │ │ ├── stm32f1xx_hal_msp_template.c │ │ │ ├── stm32f1xx_hal_nand.c │ │ │ ├── stm32f1xx_hal_nor.c │ │ │ ├── stm32f1xx_hal_pccard.c │ │ │ ├── stm32f1xx_hal_pcd.c │ │ │ ├── stm32f1xx_hal_pcd_ex.c │ │ │ ├── stm32f1xx_hal_pwr.c │ │ │ ├── stm32f1xx_hal_rcc.c │ │ │ ├── stm32f1xx_hal_rcc_ex.c │ │ │ ├── stm32f1xx_hal_rtc.c │ │ │ ├── stm32f1xx_hal_rtc_ex.c │ │ │ ├── stm32f1xx_hal_sd.c │ │ │ ├── stm32f1xx_hal_smartcard.c │ │ │ ├── stm32f1xx_hal_spi.c │ │ │ ├── stm32f1xx_hal_spi_ex.c │ │ │ ├── stm32f1xx_hal_sram.c │ │ │ ├── stm32f1xx_hal_tim.c │ │ │ ├── stm32f1xx_hal_tim_ex.c │ │ │ ├── stm32f1xx_hal_timebase_rtc_alarm_template.c │ │ │ ├── stm32f1xx_hal_timebase_tim_template.c │ │ │ ├── stm32f1xx_hal_uart.c │ │ │ ├── stm32f1xx_hal_usart.c │ │ │ ├── stm32f1xx_hal_wwdg.c │ │ │ ├── stm32f1xx_ll_adc.c │ │ │ ├── stm32f1xx_ll_crc.c │ │ │ ├── stm32f1xx_ll_dac.c │ │ │ ├── stm32f1xx_ll_dma.c │ │ │ ├── stm32f1xx_ll_exti.c │ │ │ ├── stm32f1xx_ll_fsmc.c │ │ │ ├── stm32f1xx_ll_gpio.c │ │ │ ├── stm32f1xx_ll_i2c.c │ │ │ ├── stm32f1xx_ll_pwr.c │ │ │ ├── stm32f1xx_ll_rcc.c │ │ │ ├── stm32f1xx_ll_rtc.c │ │ │ ├── stm32f1xx_ll_sdmmc.c │ │ │ ├── stm32f1xx_ll_spi.c │ │ │ ├── stm32f1xx_ll_tim.c │ │ │ ├── stm32f1xx_ll_usart.c │ │ │ ├── stm32f1xx_ll_usb.c │ │ │ └── stm32f1xx_ll_utils.c │ │ ├── GCC/ │ │ │ ├── Makefile │ │ │ ├── STM32F103VETx_FLASH.ld │ │ │ └── startup_stm32f103xe.s │ │ ├── Inc/ │ │ │ ├── at_hal.h │ │ │ ├── main.h │ │ │ ├── stm32f1xx_hal_conf.h │ │ │ ├── stm32f1xx_it.h │ │ │ └── usart.h │ │ ├── OS_CONFIG/ │ │ │ ├── los_builddef.h │ │ │ ├── los_printf.h │ │ │ └── target_config.h │ │ ├── STM32F103VET6_NB_GCC.ioc │ │ └── Src/ │ │ ├── at_hal.c │ │ ├── main.c │ │ ├── stm32f1xx_hal_msp.c │ │ ├── stm32f1xx_it.c │ │ ├── system_stm32f1xx.c │ │ └── usart.c │ └── tests/ │ ├── cmockery/ │ │ ├── AUTHORS │ │ ├── COPYING │ │ ├── ChangeLog │ │ ├── INSTALL │ │ ├── LICENSE.txt │ │ ├── Makefile.am │ │ ├── Makefile.in │ │ ├── NEWS │ │ ├── README │ │ ├── THIRD PARTY OPEN SOURCE SOFTWARE NOTICE.docx │ │ ├── aclocal.m4 │ │ ├── autogen.sh │ │ ├── compile │ │ ├── config.guess │ │ ├── config.sub │ │ ├── configure │ │ ├── configure.ac │ │ ├── depcomp │ │ ├── doc/ │ │ │ ├── html2wiki.sh │ │ │ └── index.html │ │ ├── install-sh │ │ ├── ltmain.sh │ │ ├── m4/ │ │ │ ├── ac_have_attribute.m4 │ │ │ ├── ac_rwlock.m4 │ │ │ ├── acx_pthread.m4 │ │ │ ├── compiler_characteristics.m4 │ │ │ ├── google_namespace.m4 │ │ │ ├── namespaces.m4 │ │ │ ├── stl_hash.m4 │ │ │ └── stl_namespace.m4 │ │ ├── missing │ │ ├── mkinstalldirs │ │ ├── packages/ │ │ │ ├── deb/ │ │ │ │ ├── README │ │ │ │ ├── changelog │ │ │ │ ├── compat │ │ │ │ ├── control │ │ │ │ ├── copyright │ │ │ │ ├── docs │ │ │ │ ├── libcmockery-dev.dirs │ │ │ │ ├── libcmockery-dev.install │ │ │ │ ├── libcmockery0.dirs │ │ │ │ ├── libcmockery0.install │ │ │ │ └── rules │ │ │ ├── deb.sh │ │ │ ├── rpm/ │ │ │ │ └── rpm.spec │ │ │ └── rpm.sh │ │ ├── readme.md │ │ ├── src/ │ │ │ ├── cmockery.c │ │ │ ├── config.h │ │ │ ├── example/ │ │ │ │ ├── allocate_module.c │ │ │ │ ├── allocate_module_test.c │ │ │ │ ├── assert_macro.c │ │ │ │ ├── assert_macro_test.c │ │ │ │ ├── assert_module.c │ │ │ │ ├── assert_module_test.c │ │ │ │ ├── calculator.c │ │ │ │ ├── calculator_test.c │ │ │ │ ├── customer_database.c │ │ │ │ ├── customer_database_test.c │ │ │ │ ├── database.h │ │ │ │ ├── key_value.c │ │ │ │ ├── key_value_test.c │ │ │ │ ├── product_database.c │ │ │ │ ├── product_database_test.c │ │ │ │ └── run_tests.c │ │ │ └── google/ │ │ │ └── cmockery.h │ │ └── windows/ │ │ └── makefile │ ├── test_agenttiny/ │ │ ├── It_Los_Agenttiny.c │ │ ├── It_Los_Atiny_Bind.c │ │ ├── It_Los_Atiny_Data_Report.c │ │ ├── It_Los_Atiny_Init.c │ │ └── test_agenttiny.h │ ├── test_main.c │ ├── test_sota/ │ │ ├── sota_test.c │ │ └── sota_test.h │ └── test_suit/ │ ├── agenttiny_test.c │ ├── fs_test.c │ └── regresstest.h ├── Huawei_LiteOS_Kernel/ │ ├── Huawei_LiteOS/ │ │ ├── kernel/ │ │ │ ├── base/ │ │ │ │ ├── core/ │ │ │ │ │ ├── los_priqueue.c │ │ │ │ │ ├── los_priqueue.inc │ │ │ │ │ ├── los_swtmr.c │ │ │ │ │ ├── los_swtmr.inc │ │ │ │ │ ├── los_sys.c │ │ │ │ │ ├── los_sys.inc │ │ │ │ │ ├── los_task.c │ │ │ │ │ ├── los_task.inc │ │ │ │ │ ├── los_tick.c │ │ │ │ │ ├── los_tick.inc │ │ │ │ │ ├── los_timeslice.c │ │ │ │ │ └── los_timeslice.inc │ │ │ │ ├── include/ │ │ │ │ │ ├── los_base.ph │ │ │ │ │ ├── los_event.ph │ │ │ │ │ ├── los_list.ph │ │ │ │ │ ├── los_membox.ph │ │ │ │ │ ├── los_memory.ph │ │ │ │ │ ├── los_memstat.ph │ │ │ │ │ ├── los_multipledlinkhead.ph │ │ │ │ │ ├── los_mux.ph │ │ │ │ │ ├── los_printf.ph │ │ │ │ │ ├── los_priqueue.ph │ │ │ │ │ ├── los_queue.ph │ │ │ │ │ ├── los_sem.ph │ │ │ │ │ ├── los_swtmr.ph │ │ │ │ │ ├── los_sys.ph │ │ │ │ │ ├── los_task.ph │ │ │ │ │ ├── los_tick.ph │ │ │ │ │ ├── los_timeslice.ph │ │ │ │ │ └── los_typedef.ph │ │ │ │ ├── ipc/ │ │ │ │ │ ├── los_event.c │ │ │ │ │ ├── los_event.inc │ │ │ │ │ ├── los_mux.c │ │ │ │ │ ├── los_mux.inc │ │ │ │ │ ├── los_queue.c │ │ │ │ │ ├── los_queue.inc │ │ │ │ │ ├── los_sem.c │ │ │ │ │ └── los_sem.inc │ │ │ │ ├── mem/ │ │ │ │ │ ├── los_membox.c │ │ │ │ │ ├── los_membox.inc │ │ │ │ │ ├── los_memory.c │ │ │ │ │ ├── los_memory.inc │ │ │ │ │ ├── los_memstat.c │ │ │ │ │ ├── los_memstat.inc │ │ │ │ │ ├── los_multipledlinkhead.c │ │ │ │ │ └── los_multipledlinkhead.inc │ │ │ │ └── misc/ │ │ │ │ └── los_misc.c │ │ │ └── include/ │ │ │ ├── los_base.h │ │ │ ├── los_errno.h │ │ │ ├── los_event.h │ │ │ ├── los_list.h │ │ │ ├── los_membox.h │ │ │ ├── los_memory.h │ │ │ ├── los_multipledlinkhead.h │ │ │ ├── los_mux.h │ │ │ ├── los_printf.h │ │ │ ├── los_priqueue.h │ │ │ ├── los_queue.h │ │ │ ├── los_sem.h │ │ │ ├── los_swtmr.h │ │ │ ├── los_sys.h │ │ │ ├── los_tables.h │ │ │ ├── los_task.h │ │ │ ├── los_tick.h │ │ │ └── los_typedef.h │ │ └── platform/ │ │ ├── bsp/ │ │ │ └── sample/ │ │ │ └── config/ │ │ │ ├── los_builddef.h │ │ │ ├── los_config.c │ │ │ └── los_config.h │ │ └── cpu/ │ │ └── arm/ │ │ └── cortex-m4/ │ │ ├── los_dispatch.s │ │ ├── los_hw.c │ │ ├── los_hw.h │ │ ├── los_hw_tick.c │ │ ├── los_hwi.c │ │ ├── los_hwi.h │ │ └── los_vendor.s │ ├── LICENSE │ ├── Projects/ │ │ └── EWARM/ │ │ └── cortex-m4/ │ │ └── stm32f411/ │ │ ├── Application/ │ │ │ └── README.md │ │ ├── Huawei_LiteOS.dep │ │ ├── Huawei_LiteOS.ewd │ │ ├── Huawei_LiteOS.ewp │ │ ├── Huawei_LiteOS.ewt │ │ ├── Huawei_LiteOS.eww │ │ ├── Huawei_LiteOS_cortexMF411.icf │ │ └── settings/ │ │ ├── Huawei_LiteOS.Debug.cspy.bat │ │ ├── Huawei_LiteOS.crun │ │ ├── Huawei_LiteOS.dbgdt │ │ ├── Huawei_LiteOS.dni │ │ ├── Huawei_LiteOS.wsdt │ │ ├── Huawei_LiteOS.wspos │ │ └── Huawei_LiteOS_Debug.jlink │ ├── README.md │ └── doc/ │ └── HuaweiLiteOSKernelDevGuide.chm ├── README.md ├── _config.yml ├── community/ │ └── questions.md ├── doc/ │ ├── README-tr.md │ └── README-zh.md └── products/ └── honor_smart_screen.md ================================================ FILE CONTENTS ================================================ ================================================ FILE: CNAME ================================================ awesome-harmonyos.com ================================================ FILE: Huawei_LiteOS/.github/ISSUE_TEMPLATE/bug_report.md ================================================ --- name: Bug report about: Create a report to help us improve --- * **Describe the bug** *A clear and concise description of what the bug is.* * **To Reproduce** *Steps to reproduce the behavior*: - step 1 - step 2 - step 3 - step 4 * **Expected behavior** *A clear and concise description of what you expected to happen.* * **Current behavior** *A clear and concise description of what happens currently.* * **Please tell us about your environment:** - LiteOS Version: - Chip Architecture: - Board: * **Other information** (*e.g. detailed explanation, stacktraces, related issues, suggestions how to fix, links for us to have context, eg. stackoverflow, gitter, etc*) ================================================ FILE: Huawei_LiteOS/.github/ISSUE_TEMPLATE/feature_request.md ================================================ --- name: Feature request about: Suggest an idea for this project --- * **Is your feature request related to a problem? Please describe.** *A clear and concise description of what the problem is. Ex. I'm always frustrated when [...]* * **Describe the solution you'd like** *A clear and concise description of what you want to happen.* * **Describe alternatives you've considered** *A clear and concise description of any alternative solutions or features you've considered.* * **Other information** *Add any other context or screenshots about the feature request here.* ================================================ FILE: Huawei_LiteOS/.travis.yml ================================================ language: c os: linux dist: trusty compiler: arm-none-eabi-gcc before_install: - sudo add-apt-repository ppa:team-gcc-arm-embedded/ppa -y - sudo apt-get update -q - sudo apt-get install gcc-arm-embedded -y script: - cd targets/Cloud_STM32F429IGTx_FIRE/GCC - make ================================================ FILE: Huawei_LiteOS/LICENSE ================================================ * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ================================================ FILE: Huawei_LiteOS/README.md ================================================ [![Build Status](https://travis-ci.org/LiteOS/LiteOS.svg?branch=develop)](https://travis-ci.org/LiteOS/LiteOS) ## Huawei LiteOS简介 Huawei LiteOS是华为面向物联网领域开发的一个基于实时内核的轻量级操作系统。本项目属于华为物联网操作系统[Huawei LiteOS](http://developer.huawei.com/ict/cn/site-iot/product/liteos)源码，现有基础内核支持任务管理、内存管理、时间管理、通信机制、中断管理、队列管理、事件管理、定时器等操作系统基础组件，更好地支持低功耗场景，支持tickless机制，支持定时器对齐。 同时提供端云协同能力，集成了LwM2M、CoAP、mbedtls、LwIP全套IoT互联协议栈，且在LwM2M的基础上，提供了AgentTiny模块，用户只需关注自身的应用，而不必关注LwM2M实现细节，直接使用AgentTiny封装的接口即可简单快速实现与云平台安全可靠的连接。 Huawei LiteOS自开源社区发布以来，围绕NB-IoT物联网市场从技术、生态、解决方案、商用支持等多维度使能合作伙伴，构建开源的物联网生态,目前已经聚合了30+ MCU和解决方案合作伙伴，共同推出一批开源开发套件和行业解决方案，帮助众多行业客户快速的推出物联网终端和服务，客户涵盖抄表、停车、路灯、环保、共享单车、物流等众多行业，为开发者提供 “一站式” 完整软件平台，有效降低开发门槛、缩短开发周期。 ## LiteOS 代码导读 - [LiteOS内核源代码目录说明](./doc/LiteOS_Code_Info.md) 该文档描述的是LiteOS内核源代码的详细信息。通过此文档读者可以了解LiteOS的源代码结构，以及LiteOS的main()函数的功能。 ## LiteOS 开发指南 [LiteOS开发指南](./doc/Huawei_LiteOS_Developer_Guide_zh.md) [LiteOS移植指南](https://liteos.github.io/porting/) 该文档详细讲解了LiteOS各模块开发及其实现原理。用户可以根据该文档学习各模块的使用。 ## LiteOS 接入云平台开发指南 * [LiteOS接入华为云平台](https://github.com/SuYai/OceanConnectHelp) * [LiteOS SDK端云互通组件开发指南](./doc/Huawei_LiteOS_SDK_Developer_Guide.md) LiteOS SDK是Huawei LiteOS软件开发工具包（Software Development Kit），通过LiteOS SDK端云互通组件，简单快速地实现与华为 OceanConnect IoT平台安全可靠连接，可以大大减少开发周期，快速构建IoT产品。 LiteOS SDK是Huawei LiteOS软件开发工具包（Software Development Kit），通过LiteOS SDK端云互通组件，简单快速地实现与华为 OceanConnect IoT平台安全可靠连接，可以大大减少开发周期，快速构建IoT产品。 * [LiteOS SDK端云互通组件Coap开发指南](./doc/Huawei_LiteOS_SDK_Coap_LwM2M_Developer_Guide_zh.md) * [LiteOS SDK端云互通组件MQTT开发指南](./doc/Huawei_LiteOS_SDK_MQTT_Developer_Guide.md) * [LiteOS接入3rd云平台](https://github.com/LiteOS/LiteOS_Connect_to_3rd_Cloud) ## LiteOS 支持的硬件 * LiteOS开源项目目前支持ARM Cortex-M0，Cortex-M3，Cortex-M4，Cortex-M7等芯片架构 * [LiteOS支持的开发板列表](./doc/LiteOS_Supported_board_list.md) Huawei LiteOS 联合业界主流MCU厂家，通过开发者活动，目前已经适配了30+ 通用 MCU开发套件，5套NB-IoT集成开发套件 ## 开源协议 * 遵循BSD-3开源许可协议 * [Huawei LiteOS 知识产权政策](https://support.huaweicloud.com/productdesc-LiteOS/zh-cn_topic_0145347224.html) ## LiteOS Git入门必读 - [LiteOS Commit Message规则](./doc/LiteOS_Commit_Message.md) 该文档描述如何提交commit到LiteOS仓库，这是LiteOS开发必须遵守的commit规则，否则提交的commit会被驳回。请点链接了解详细信息。 - [Huawei LiteOS代码贡献流程](./doc/LiteOS_Contribute_Guide_GitGUI.md) 该文档描述开发者如何创建自己的仓库，开发然后贡献代码到LiteOS仓库。请点链接了解详细信息。 ## 加入我们 * 欢迎提交issue对关心的问题发起讨论，欢迎提交PR参与特性建设 * 如您有合作意向，希望加入Huawei LiteOS生态合作伙伴，请发邮件至liteos@huawei.com，或访问[LiteOS官网](http://www.huawei.com/liteos)，进一步了解详细信息 ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m0/gcc/los_dispatch_gcc.S ================================================ /** ---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /** ---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**************************************************************************************** * EXPORT FUNCTIONS ****************************************************************************************/ .global LOS_IntLock .global LOS_IntUnLock .global LOS_IntRestore .global LOS_StartToRun .global osTaskSchedule .global PendSV_Handler /**************************************************************************************** * EXTERN PARAMETERS ****************************************************************************************/ .extern g_stLosTask .extern g_pfnTskSwitchHook .extern g_bTaskScheduled /**************************************************************************************** * EQU ****************************************************************************************/ .equ OS_NVIC_INT_CTRL, 0xE000ED04 /* Interrupt Control and State Register. */ .equ OS_NVIC_PENDSVSET, 0x10000000 /* Value to trigger PendSV exception. */ .equ OS_NVIC_SYSPRI2, 0xE000ED20 /* System Handler Priority Register 2. */ .equ OS_NVIC_PENDSV_SYSTICK_PRI, 0xC0C00000 /* SysTick + PendSV priority level (lowest). */ .equ OS_TASK_STATUS_RUNNING, 0x0010 /* Task Status Flag (RUNNING). */ /**************************************************************************************** * CODE GENERATION DIRECTIVES ****************************************************************************************/ .section .text .thumb .syntax unified .arch armv6-m /**************************************************************************************** * Function: * VOID LOS_StartToRun(VOID); * Description: * Start the first task, which is the highest priority task in the priority queue. * Other tasks are started by task scheduling. ****************************************************************************************/ .type LOS_StartToRun, %function LOS_StartToRun: CPSID I /** * Set PendSV and SysTick prority to the lowest. * read ---> modify ---> write-back. */ LDR R0, =OS_NVIC_SYSPRI2 LDR R1, =OS_NVIC_PENDSV_SYSTICK_PRI LDR R2, [R0] ORRS R1, R1, R2 STR R1, [R0] /** * Set g_bTaskScheduled = 1. */ LDR R0, =g_bTaskScheduled MOVS R1, #1 STR R1, [R0] /** * Now PSP is an invalid value, R13 uses MSP as the stack pointer. * After setting the control register, R13 will switch to PSP. * To ensure that R13 is valid, set PSP = MSP. */ MRS R0, MSP MSR PSP, R0 /** * Set the CONTROL register, after schedule start, privilege level and stack = PSP. */ MOVS R0, #2 MSR CONTROL, R0 /** * Set g_stLosTask.pstRunTask = g_stLosTask.pstNewTask. */ LDR R0, =g_stLosTask LDR R1, [R0, #4] STR R1, [R0] /** * Set g_stLosTask.pstRunTask->usTaskStatus |= OS_TASK_STATUS_RUNNING. */ LDR R1, [R0] LDRH R2, [R1, #4] MOVS R3, #OS_TASK_STATUS_RUNNING ORRS R2, R2, R3 STRH R2, [R1, #4] /** * Restore the default stack frame(R0-R3,R12,LR,PC,xPSR) of g_stLosTask.pstRunTask to R0-R7. * Return by setting the CONTROL register. * * The initial stack of the current running task is as follows: * * POP: Restore the context of the current running task ===>| * High addr--->| * Bottom of the stack--->| * ----------+-----------------------+--------------------------------------+ * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | * ----------+-----------------------+--------------------------------------+ * |<---Top of the stack, restored from g_stLosTask.pstRunTask->pStackPointer * |<--- skip --->|<--- copy to R0-R7 --->| * R3 to PSP--->| * Stack pointer after LOS_StartToRun--->| */ LDR R3, [R1] ADDS R3, R3, #36 /* skip R4-R11, PRIMASK. */ LDMFD R3!, {R0-R2} /* restore R0-R2. */ ADDS R3, R3, #4 /* skip R3. */ LDMFD R3!, {R4-R7} /* restore R12,LR,PC,xPSR. */ /** * Set the stack pointer of g_stLosTask.pstRunTask to PSP. */ MSR PSP, R3 SUBS R3, R3, #20 LDR R3, [R3] /* restore R3. */ /** * Enable interrupt. (The default PRIMASK value is 0, so enable directly) */ MOV LR, R5 CPSIE I /** * Jump directly to the default PC of g_stLosTask.pstRunTask, the field information * of the main function will be destroyed and will never be returned. */ BX R6 /**************************************************************************************** * Function: * UINTPTR LOS_IntLock(VOID); * Description: * Disable all interrupts except Reset,NMI and HardFault. * The value of currnet interruption state will be returned to the caller to save. * * Function: * VOID LOS_IntRestore(UINTPTR uvIntSave); * Description: * Restore the locked interruption of LOS_IntLock. * The caller must pass in the value of interruption state previously saved. ****************************************************************************************/ .type LOS_IntLock, %function LOS_IntLock: MRS R0, PRIMASK CPSID I BX LR .type LOS_IntUnLock, %function LOS_IntUnLock: MRS R0, PRIMASK CPSIE I BX LR .type LOS_IntRestore, %function LOS_IntRestore: MSR PRIMASK, R0 BX LR /**************************************************************************************** * Function: * VOID osTaskSchedule(VOID); * Description: * Start the task swtich process by software trigger PendSV interrupt. ****************************************************************************************/ .type osTaskSchedule, %function osTaskSchedule: LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] BX LR /**************************************************************************************** * Function: * VOID PendSV_Handler(VOID); * Description: * PendSV interrupt handler, switch the context of the task. * First: Save the context of the current running task(g_stLosTask.pstRunTask) * to its own stack. * Second: Restore the context of the next running task(g_stLosTask.pstNewTask) * from its own stack. ****************************************************************************************/ .type PendSV_Handler, %function PendSV_Handler: /** * R12: Save the interruption state of the current running task. * Disable all interrupts except Reset,NMI and HardFault */ MRS R12, PRIMASK CPSID I /** * Call task switch hook. */ LDR R2, =g_pfnTskSwitchHook LDR R2, [R2] CMP R2, #0 BEQ TaskSwitch MOV R1, LR PUSH {R0, R1} BLX R2 POP {R0, R1} MOV LR, R1 TaskSwitch: /** * R0 = now stack pointer of the current running task. */ MRS R0, PSP /** * Save the stack frame(R4-R11) of the current running task. * R12 save the PRIMASK value of the current running task. * NOTE: Before entering the exception handler function, these registers * (xPSR,PC,LR,R12,R3-R0) have been automatically * saved by the CPU in the stack of the current running task. * * The stack of the current running task is as follows: * * |<=== PUSH: Save the context of the current running task * | High addr--->| * ----------+-----------------------+--------------------------------------+----- * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | * ----------+-----------------------+--------------------------------------+----- * Stack pointer before entering exception--->| * |<--- cpu auto saved --->| * |<---PSP to R0 * |<---Top of the stack, save to g_stLosTask.pstRunTask->pStackPointer */ SUBS R0, #36 STMIA R0!, {R4-R7} /* save R4-R7. */ MOV R3, R8 /* copy R8-r12 to R3-r7. */ MOV R4, R9 MOV R5, R10 MOV R6, R11 MOV R7, R12 STMIA R0!, {R3-R7} /* save R8-R12. */ SUBS R0, #36 /** * R5,R3. */ LDR R5, =g_stLosTask MOVS R3, #OS_TASK_STATUS_RUNNING /** * Save the stack pointer of the current running task to TCB. * (g_stLosTask.pstRunTask->pStackPointer = R0) */ LDR R6, [R5] STR R0, [R6] /** * Clear the RUNNING state of the current running task. * (g_stLosTask.pstRunTask->usTaskStatus &= ~OS_TASK_STATUS_RUNNING) */ LDRH R7, [R6, #4] BICS R7, R7, R3 STRH R7, [R6, #4] /** * Switch the current running task to the next running task. * (g_stLosTask.pstRunTask = g_stLosTask.pstNewTask) */ LDR R0, [R5, #4] STR R0, [R5] /** * Set the RUNNING state of the next running task. * (g_stLosTask.pstNewTask->usTaskStatus |= OS_TASK_STATUS_RUNNING) */ LDRH R7, [R0, #4] ORRS R7, R7, R3 STRH R7, [R0, #4] /** * Restore the stack pointer of the next running task from TCB. * (R1 = g_stLosTask.pstNewTask->pStackPointer) */ LDR R1, [R0] /** * Restore the stack frame(R4-R11) of the next running task. * R12 restore the PRIMASK value of the next running task. * NOTE: After exiting the exception handler function, these registers * (xPSR,R0-R3,R12,LR,PC) will be automatically * restored by the CPU from the stack of the next running task. * * 1. The stack of the next running task is as follows: * * POP: Restore the context of the next running task ===>| * High addr--->| * ----------+-----------------------+--------------------------------------+----- * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | * ----------+-----------------------+--------------------------------------+----- * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer * R1 to PSP--->| * |<--- cpu auto restoring --->| * Stack pointer after exiting exception--->| * * 2. If the next running task is run for the first time, the stack is as follows: * * POP: Restore the context of the next running task ===>| * High addr--->| * Bottom of the stack--->| * ----------+-----------------------+--------------------------------------+ * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | * ----------+-----------------------+--------------------------------------+ * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer * R1 to PSP--->| * |<--- cpu auto restoring --->| * Stack pointer after exiting exception--->| */ ADDS R1, #16 LDMFD R1!, {R3-R7} /* restore R8-R12 to R3-R7. */ MOV R8, R3 /* copy R3-R7 to R8-R12. */ MOV R9, R4 MOV R10, R5 MOV R11, R6 MOV R12, R7 /** * Set the stack pointer of the next running task to PSP. */ MSR PSP, R1 SUBS R1, #36 LDMFD R1!, {R4-R7} /* restore R4-R7. */ /** * Restore the interruption state of the next running task. */ MSR PRIMASK, R12 BX LR ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m0/gcc/los_hw_exc_gcc.S ================================================ /*---------------------------------------------------------------------------- Copyright (c) <2013-2015>, All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------- Notice of Export Control Law =============================================== Huawei LiteOS may be subject to applicable export control laws and regulations, which might include those applicable to Huawei LiteOS of U.S. and the country in which you are located. Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such applicable export control laws and regulations. ---------------------------------------------------------------------------*/ /**************************************************************************************** CODE GENERATION DIRECTIVES ****************************************************************************************/ .section .text .thumb .syntax unified .arch armv6-m /**************************************************************************************** EXPORT FUNCTIONS ****************************************************************************************/ .global NMI_Handler .global HardFault_Handler .global MemManage_Handler .global BusFault_Handler .global UsageFault_Handler /**************************************************************************************** EXTERN PARAMETERS ****************************************************************************************/ .extern osExcHandleEntry .extern g_uwExcTbl .extern g_bTaskScheduled .extern it_is_memManangeFault .extern it_is_busFault .extern it_is_usageFault /**************************************************************************************** EQU ****************************************************************************************/ .equ OS_EXC_CAUSE_NMI, 18 .equ OS_EXC_CAUSE_HARDFAULT, 19 .equ OS_EXC_CAUSE_MEMFAULT, 20 .equ OS_EXC_CAUSE_BUSFAULT, 21 .equ OS_EXC_CAUSE_USAGEFAULT, 22 .equ OS_EXC_CAUSE_SVC, 23 .equ HF_DEBUGEVT, 24 .equ HF_VECTBL, 25 .equ FLAG_ADDR_VALID, 0x10000 /*bit 16*/ .equ FLAG_HWI_ACTIVE, 0x20000 /*bit 17*/ .equ FLAG_NO_FLOAT, 0x10000000 /*bit 28*/ .equ OS_NVIC_CFSR, 0xE000ED28 /*include BusFault/MemFault/UsageFault State Regeister*/ .equ OS_NVIC_HFSR, 0xE000ED2C /*HardFault State Regeister*/ .equ OS_NVIC_BFAR, 0xE000ED38 .equ OS_NVIC_MMFAR, 0xE000ED34 .equ OS_NVIC_ACT_BASE, 0xE000E300 .equ OS_NVIC_SHCSRS, 0xE000ED24 .equ OS_NVIC_SHCSR_MASK, 0xC00 /*SYSTICKACT and PENDSVACT*/ .equ ADDR_SETPEND, 0XE000E200 /*the addr of setpend register*/ .equ ADDR_CLRPEND, 0XE000E280 /*the addr of clrpend register*/ .equ ADDR_SETENA, 0XE000E100 .equ EXC_RETURN_NEST, 0XFFFFFFF1 /*return to some irq_handler*/ /**************************************************************************************** Function: VOID NMI_Handler(VOID) Description: NMI Handler. ****************************************************************************************/ .type NMI_Handler, %function NMI_Handler: /** * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. * < R0 >: * +------------------------------------------------------+------------------------+ * | 31-8 | 7-0 | * +------------------------------------------------------+------------------------+ * | --- | OS_EXC_CAUSE_NMI | * +------------------------------------------------------+------------------------+ * < R1 >: invalid */ MOVS R0, #OS_EXC_CAUSE_NMI MOVS R1, #0 B osExcDispatch /**************************************************************************************** Function: VOID HardFault_Handler(VOID) Description: HardFault Handler. ****************************************************************************************/ .type HardFault_Handler, %function HardFault_Handler: /** * save fault type to R0 */ MOVS R0, #OS_EXC_CAUSE_HARDFAULT B osExcDispatch /** * When executing osExcDispatch, R2 will be used. */ osExcDispatch: LDR R2, =ADDR_SETPEND LDR R2, [R2] LDR R3,=0X40 LSLS R3,R3,#0X18 SUBS R3,R3,#1 /*R3 =0011 1111 1111 1111 1111 1111 1111 1111 filter the highest active 2 bits error*/ ANDS R2,R2,R3 LDR R3,=ADDR_SETENA LDR R3,[R3] ANDS R2,R2,R3 /*if an interrupt is enabled and active ,it is a nomal exception ,otherwise,it should be ignored*/ MOV R1,LR LDR R3, =EXC_RETURN_NEST CMP R1,R3 BEQ __in_interrupt /*jump when they are equal,if LR equals it,they are in some interrupt*/ B __second_judge __in_interrupt: CMP R2,#0 BEQ __set_R2_33 B _NoFloatInMsp __set_R2_33: MOVS R2,#0x21 /*if in interrupt,but the setpendAddr is 0,sth wrong happened, set id to 33*/ B _NoFloatInMsp __second_judge: CMP R2,#0 BEQ _whether_in_initialization /*jump when no external interrupt occurred*/ /** * Interrupts and initialization phase always use MSP. */ _ExcInMSP: /** * Before executing instruction 'B _handleEntry', MSP is as follows. * MSP: * High addr--->| * +--------------------------------------------------------------------------------+--------- * | R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR | * +--------------------------------------------------------------------------------+--------- * R13--->| Initial R13--->|<--- #32 --->|<---SAVED_SP * | (CPU auto saved) | * */ _NoFloatInMsp: CMP R2,#0 /*check r2 ,find the phase interrupts occurred*/ BEQ __11 MOVS R1,#0x2f /*in interrupt phase ,r1=47*/ LSLS R0,R0,#8 ORRS R0,R0,R1 /*make r1 available*/ B __12 __11: MOVS R1,#0 /*in initialization phase r1=0*/ LSLS R0,R0,#8 ORRS R0,R0,R1 /* make r1 available */ __12: ADD R3, R13, #32 /*#32: skip [R0-R3,R12,LR,PC,xPSR]*/ PUSH {R3} /*push [SAVED_SP]: MSP+32 = Stack pointer in MSP before entering the exception*/ MRS R12, PRIMASK MOV R3,R12 PUSH {R3} MOV R3,R11 PUSH {R3} MOV R3,R10 PUSH {R3} MOV R3,R9 PUSH {R3} MOV R3,R8 PUSH {R3} PUSH {R7} PUSH {R6} PUSH {R5} PUSH {R4} /*push R4-R11,PRIMASK to MSP in certain order*/ B _handleEntry /** * Check whether during the initialization phase. * If g_bTaskScheduled == 0, it is in the initialization phase. */ _whether_in_initialization: LDR R1, =g_bTaskScheduled LDR R1, [R1] MOVS R3,#1 TST R1,R3 BEQ _ExcInMSP /*initialization phase use MSP*/ /** * Before executing _handleEntry, MSP is as follows. * MSP: * High addr--->| * +--------------------------------------------------------------------------------+--------- * | R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR | * +--------------------------------------------------------------------------------+--------- * R13--->| |<--- #32 --->|<---Initial R13 * | (copied from PSP) | * |<---R2(no use) * * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR. */ _NoFloatInPsp: MOVS R1,#1 /*in task ,r1 = 1 */ LSLS R0,R0,#8 ORRS R0,R0,R1 /*make r1 available*/ MOV R1, R13 SUB R13, #32 /*#32: MSP reserved, used to store stack frame in PSP*/ MRS R3, PSP ADDS R3, R3, #32 /*PSP+32 = Stack pointer of the task before entering the exception*/ PUSH {R3} /*push task SP to MSP*/ MRS R3,PRIMASK PUSH {R3} MOV R3,R11 PUSH {R3} MOV R3,R10 PUSH {R3} MOV R3,R9 PUSH {R3} MOV R3,R8 PUSH {R3} PUSH {R7} PUSH {R6} PUSH {R5} PUSH {R4} MRS R3,PSP /* Copy stack frame from the stack of the current running task to MSP */ LDMIA R3!, {R4-R7} SUBS R1,#0X20 STMIA R1!, {R4-R7} LDMIA R3!, {R4-R7} STMIA R1!, {R4-R7} /** * _handleEntry: Call osExcHandleEntry * param1: R0 --- type num and phase * param2: R1 --- the sp being used(in Cortex-M0,it is only for debug ) * param3: R2 --- external interrupt ID * param4: R3 --- Point to the top of the stack(R4 or S16) that the exception stack frame in MSP. */ _handleEntry: MOV R3, R13 MOV R1,R13 CPSID I LDR R4,=osExcHandleEntry MOV PC,R4 NOP ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m0/iar/los_dispatch_iar.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2016-2018>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT LOS_IntLock EXPORT LOS_IntUnLock EXPORT LOS_IntRestore EXPORT LOS_StartToRun EXPORT osTaskSchedule EXPORT PendSV_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT g_stLosTask IMPORT g_pfnTskSwitchHook IMPORT g_bTaskScheduled ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt Control and State Register. OS_NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception. OS_NVIC_SYSPRI2 EQU 0xE000ED20 ; System Handler Priority Register 2. OS_NVIC_PENDSV_SYSTICK_PRI EQU 0xC0C00000 ; SysTick + PendSV priority level (lowest). OS_TASK_STATUS_RUNNING EQU 0x0010 ; Task Status Flag (RUNNING). ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** SECTION .text:CODE(2) THUMB REQUIRE8 PRESERVE8 ;**************************************************************************************** ; Function: ; VOID LOS_StartToRun(VOID); ; Description: ; Start the first task, which is the highest priority task in the priority queue. ; Other tasks are started by task scheduling. ;**************************************************************************************** LOS_StartToRun CPSID I ;/** ; * Set PendSV and SysTick prority to the lowest. ; * read ---> modify ---> write-back. ; */ LDR R0, =OS_NVIC_SYSPRI2 LDR R1, =OS_NVIC_PENDSV_SYSTICK_PRI LDR R2, [R0] ORRS R1, R1, R2 STR R1, [R0] ;/** ; * Set g_bTaskScheduled = 1. ; */ LDR R0, =g_bTaskScheduled MOVS R1, #1 STR R1, [R0] ;/** ; * Now PSP is an invalid value, R13 uses MSP as the stack pointer. ; * After setting the control register, R13 will switch to PSP. ; * To ensure that R13 is valid, set PSP = MSP. ; */ MRS R0, MSP MSR PSP, R0 ;/** ; * Set the CONTROL register, after schedule start, privilege level and stack = PSP. ; */ MOVS R0, #2 MSR CONTROL, R0 ;/** ; * Set g_stLosTask.pstRunTask = g_stLosTask.pstNewTask. ; */ LDR R0, =g_stLosTask LDR R1, [R0, #4] STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask->usTaskStatus |= OS_TASK_STATUS_RUNNING. ; */ LDR R1, [R0] LDRH R2, [R1, #4] MOVS R3, #OS_TASK_STATUS_RUNNING ORRS R2, R2, R3 STRH R2, [R1, #4] ;/** ; * Restore the default stack frame(R0-R3,R12,LR,PC,xPSR) of g_stLosTask.pstRunTask to R0-R7. ; * Return by setting the CONTROL register. ; * ; * The initial stack of the current running task is as follows: ; * ; * POP: Restore the context of the current running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+-----------------------+--------------------------------------+ ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstRunTask->pStackPointer ; * |<--- skip --->|<--- copy to R0-R7 --->| ; * R3 to PSP--->| ; * Stack pointer after LOS_StartToRun--->| ; */ LDR R3, [R1] ADDS R3, R3, #36 ; skip R4-R11, PRIMASK. LDMFD R3!, {R0-R2} ; restore R0-R2. ADDS R3, R3, #4 ; skip R3. LDMFD R3!, {R4-R7} ; restore R12,LR,PC,xPSR. ;/** ; * Set the stack pointer of g_stLosTask.pstRunTask to PSP. ; */ MSR PSP, R3 SUBS R3, R3, #20 LDR R3, [R3] ; restore R3. ;/** ; * Enable interrupt. (The default PRIMASK value is 0, so enable directly) ; */ MOV LR, R5 CPSIE I ;/** ; * Jump directly to the default PC of g_stLosTask.pstRunTask, the field information ; * of the main function will be destroyed and will never be returned. ; */ BX R6 ;**************************************************************************************** ; Function: ; UINTPTR LOS_IntLock(VOID); ; Description: ; Disable all interrupts except Reset,NMI and HardFault. ; The value of currnet interruption state will be returned to the caller to save. ; ; Function: ; VOID LOS_IntRestore(UINTPTR uvIntSave); ; Description: ; Restore the locked interruption of LOS_IntLock. ; The caller must pass in the value of interruption state previously saved. ;**************************************************************************************** LOS_IntLock MRS R0, PRIMASK CPSID I BX LR LOS_IntUnLock MRS R0, PRIMASK CPSIE I BX LR LOS_IntRestore MSR PRIMASK, R0 BX LR ;**************************************************************************************** ; Function: ; VOID osTaskSchedule(VOID); ; Description: ; Start the task swtich process by software trigger PendSV interrupt. ;**************************************************************************************** osTaskSchedule LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] BX LR ;**************************************************************************************** ; Function: ; VOID PendSV_Handler(VOID); ; Description: ; PendSV interrupt handler, switch the context of the task. ; First: Save the context of the current running task(g_stLosTask.pstRunTask) ; to its own stack. ; Second: Restore the context of the next running task(g_stLosTask.pstNewTask) ; from its own stack. ;**************************************************************************************** PendSV_Handler ;/** ; * R12: Save the interruption state of the current running task. ; * Disable all interrupts except Reset,NMI and HardFault ; */ MRS R12, PRIMASK CPSID I ;/** ; * Call task switch hook. ; */ LDR R2, =g_pfnTskSwitchHook LDR R2, [R2] CMP R2, #0 BEQ TaskSwitch MOV R1, LR PUSH {R0, R1} BLX R2 POP {R0, R1} MOV LR, R1 TaskSwitch ;/** ; * R0 = now stack pointer of the current running task. ; */ MRS R0, PSP ;/** ; * Save the stack frame(R4-R11) of the current running task. ; * R12 save the PRIMASK value of the current running task. ; * NOTE: Before entering the exception handler function, these registers ; * (xPSR,PC,LR,R12,R3-R0) have been automatically ; * saved by the CPU in the stack of the current running task. ; * ; * The stack of the current running task is as follows: ; * ; * |<=== PUSH: Save the context of the current running task ; * | High addr--->| ; * ----------+-----------------------+--------------------------------------+----- ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+----- ; * Stack pointer before entering exception--->| ; * |<--- cpu auto saved --->| ; * |<---PSP to R0 ; * |<---Top of the stack, save to g_stLosTask.pstRunTask->pStackPointer ; */ SUBS R0, #36 STMIA R0!, {R4-R7} ; save R4-R7. MOV R3, R8 ; copy R8-r12 to R3-r7. MOV R4, R9 MOV R5, R10 MOV R6, R11 MOV R7, R12 STMIA R0!, {R3-R7} ; save R8-R12. SUBS R0, #36 ;/** ; * R5,R3. ; */ LDR R5, =g_stLosTask MOVS R3, #OS_TASK_STATUS_RUNNING ;/** ; * Save the stack pointer of the current running task to TCB. ; * (g_stLosTask.pstRunTask->pStackPointer = R0) ; */ LDR R6, [R5] STR R0, [R6] ;/** ; * Clear the RUNNING state of the current running task. ; * (g_stLosTask.pstRunTask->usTaskStatus &= ~OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R6, #4] BICS R7, R7, R3 STRH R7, [R6, #4] ;/** ; * Switch the current running task to the next running task. ; * (g_stLosTask.pstRunTask = g_stLosTask.pstNewTask) ; */ LDR R0, [R5, #4] STR R0, [R5] ;/** ; * Set the RUNNING state of the next running task. ; * (g_stLosTask.pstNewTask->usTaskStatus |= OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R0, #4] ORRS R7, R7, R3 STRH R7, [R0, #4] ;/** ; * Restore the stack pointer of the next running task from TCB. ; * (R1 = g_stLosTask.pstNewTask->pStackPointer) ; */ LDR R1, [R0] ;/** ; * Restore the stack frame(R4-R11) of the next running task. ; * R12 restore the PRIMASK value of the next running task. ; * NOTE: After exiting the exception handler function, these registers ; * (xPSR,R0-R3,R12,LR,PC) will be automatically ; * restored by the CPU from the stack of the next running task. ; * ; * 1. The stack of the next running task is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * ----------+-----------------------+--------------------------------------+----- ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+----- ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; * ; * 2. If the next running task is run for the first time, the stack is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+-----------------------+--------------------------------------+ ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; */ ADDS R1, #16 LDMFD R1!, {R3-R7} ; restore R8-R12 to R3-R7. MOV R8, R3 ; copy R3-R7 to R8-R12. MOV R9, R4 MOV R10, R5 MOV R11, R6 MOV R12, R7 ;/** ; * Set the stack pointer of the next running task to PSP. ; */ MSR PSP, R1 SUBS R1, #36 LDMFD R1!, {R4-R7} ; restore R4-R7. ;/** ; * Restore the interruption state of the next running task. ; */ MSR PRIMASK, R12 BX LR END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m0/keil/los_dispatch_keil.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2016-2018>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT LOS_IntLock EXPORT LOS_IntUnLock EXPORT LOS_IntRestore EXPORT LOS_StartToRun EXPORT osTaskSchedule EXPORT PendSV_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT g_stLosTask IMPORT g_pfnTskSwitchHook IMPORT g_bTaskScheduled ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt Control and State Register. OS_NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception. OS_NVIC_SYSPRI2 EQU 0xE000ED20 ; System Handler Priority Register 2. OS_NVIC_PENDSV_SYSTICK_PRI EQU 0xC0C00000 ; SysTick + PendSV priority level (lowest). OS_TASK_STATUS_RUNNING EQU 0x0010 ; Task Status Flag (RUNNING). ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** AREA |.text|, CODE, READONLY THUMB REQUIRE8 PRESERVE8 ;**************************************************************************************** ; Function: ; VOID LOS_StartToRun(VOID); ; Description: ; Start the first task, which is the highest priority task in the priority queue. ; Other tasks are started by task scheduling. ;**************************************************************************************** LOS_StartToRun CPSID I ;/** ; * Set PendSV and SysTick prority to the lowest. ; * read ---> modify ---> write-back. ; */ LDR R0, =OS_NVIC_SYSPRI2 LDR R1, =OS_NVIC_PENDSV_SYSTICK_PRI LDR R2, [R0] ORRS R1, R1, R2 STR R1, [R0] ;/** ; * Set g_bTaskScheduled = 1. ; */ LDR R0, =g_bTaskScheduled MOVS R1, #1 STR R1, [R0] ;/** ; * Now PSP is an invalid value, R13 uses MSP as the stack pointer. ; * After setting the control register, R13 will switch to PSP. ; * To ensure that R13 is valid, set PSP = MSP. ; */ MRS R0, MSP MSR PSP, R0 ;/** ; * Set the CONTROL register, after schedule start, privilege level and stack = PSP. ; */ MOVS R0, #2 MSR CONTROL, R0 ;/** ; * Set g_stLosTask.pstRunTask = g_stLosTask.pstNewTask. ; */ LDR R0, =g_stLosTask LDR R1, [R0, #4] STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask->usTaskStatus |= OS_TASK_STATUS_RUNNING. ; */ LDR R1, [R0] LDRH R2, [R1, #4] MOVS R3, #OS_TASK_STATUS_RUNNING ORRS R2, R2, R3 STRH R2, [R1, #4] ;/** ; * Restore the default stack frame(R0-R3,R12,LR,PC,xPSR) of g_stLosTask.pstRunTask to R0-R7. ; * Return by setting the CONTROL register. ; * ; * The initial stack of the current running task is as follows: ; * ; * POP: Restore the context of the current running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+-----------------------+--------------------------------------+ ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstRunTask->pStackPointer ; * |<--- skip --->|<--- copy to R0-R7 --->| ; * R3 to PSP--->| ; * Stack pointer after LOS_StartToRun--->| ; */ LDR R3, [R1] ADDS R3, R3, #36 ; skip R4-R11, PRIMASK. LDMFD R3!, {R0-R2} ; restore R0-R2. ADDS R3, R3, #4 ; skip R3. LDMFD R3!, {R4-R7} ; restore R12,LR,PC,xPSR. ;/** ; * Set the stack pointer of g_stLosTask.pstRunTask to PSP. ; */ MSR PSP, R3 SUBS R3, R3, #20 LDR R3, [R3] ; restore R3. ;/** ; * Enable interrupt. (The default PRIMASK value is 0, so enable directly) ; */ MOV LR, R5 CPSIE I ;/** ; * Jump directly to the default PC of g_stLosTask.pstRunTask, the field information ; * of the main function will be destroyed and will never be returned. ; */ BX R6 ;**************************************************************************************** ; Function: ; UINTPTR LOS_IntLock(VOID); ; Description: ; Disable all interrupts except Reset,NMI and HardFault. ; The value of currnet interruption state will be returned to the caller to save. ; ; Function: ; VOID LOS_IntRestore(UINTPTR uvIntSave); ; Description: ; Restore the locked interruption of LOS_IntLock. ; The caller must pass in the value of interruption state previously saved. ;**************************************************************************************** LOS_IntLock MRS R0, PRIMASK CPSID I BX LR LOS_IntUnLock MRS R0, PRIMASK CPSIE I BX LR LOS_IntRestore MSR PRIMASK, R0 BX LR ;**************************************************************************************** ; Function: ; VOID osTaskSchedule(VOID); ; Description: ; Start the task swtich process by software trigger PendSV interrupt. ;**************************************************************************************** osTaskSchedule LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] BX LR ;**************************************************************************************** ; Function: ; VOID PendSV_Handler(VOID); ; Description: ; PendSV interrupt handler, switch the context of the task. ; First: Save the context of the current running task(g_stLosTask.pstRunTask) ; to its own stack. ; Second: Restore the context of the next running task(g_stLosTask.pstNewTask) ; from its own stack. ;**************************************************************************************** PendSV_Handler ;/** ; * R12: Save the interruption state of the current running task. ; * Disable all interrupts except Reset,NMI and HardFault ; */ MRS R12, PRIMASK CPSID I ;/** ; * Call task switch hook. ; */ LDR R2, =g_pfnTskSwitchHook LDR R2, [R2] CMP R2, #0 BEQ TaskSwitch MOV R1, LR PUSH {R0, R1} BLX R2 POP {R0, R1} MOV LR, R1 TaskSwitch ;/** ; * R0 = now stack pointer of the current running task. ; */ MRS R0, PSP ;/** ; * Save the stack frame(R4-R11) of the current running task. ; * R12 save the PRIMASK value of the current running task. ; * NOTE: Before entering the exception handler function, these registers ; * (xPSR,PC,LR,R12,R3-R0) have been automatically ; * saved by the CPU in the stack of the current running task. ; * ; * The stack of the current running task is as follows: ; * ; * |<=== PUSH: Save the context of the current running task ; * | High addr--->| ; * ----------+-----------------------+--------------------------------------+----- ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+----- ; * Stack pointer before entering exception--->| ; * |<--- cpu auto saved --->| ; * |<---PSP to R0 ; * |<---Top of the stack, save to g_stLosTask.pstRunTask->pStackPointer ; */ SUBS R0, #36 STMIA R0!, {R4-R7} ; save R4-R7. MOV R3, R8 ; copy R8-r12 to R3-r7. MOV R4, R9 MOV R5, R10 MOV R6, R11 MOV R7, R12 STMIA R0!, {R3-R7} ; save R8-R12. SUBS R0, #36 ;/** ; * R5,R3. ; */ LDR R5, =g_stLosTask MOVS R3, #OS_TASK_STATUS_RUNNING ;/** ; * Save the stack pointer of the current running task to TCB. ; * (g_stLosTask.pstRunTask->pStackPointer = R0) ; */ LDR R6, [R5] STR R0, [R6] ;/** ; * Clear the RUNNING state of the current running task. ; * (g_stLosTask.pstRunTask->usTaskStatus &= ~OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R6, #4] BICS R7, R7, R3 STRH R7, [R6, #4] ;/** ; * Switch the current running task to the next running task. ; * (g_stLosTask.pstRunTask = g_stLosTask.pstNewTask) ; */ LDR R0, [R5, #4] STR R0, [R5] ;/** ; * Set the RUNNING state of the next running task. ; * (g_stLosTask.pstNewTask->usTaskStatus |= OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R0, #4] ORRS R7, R7, R3 STRH R7, [R0, #4] ;/** ; * Restore the stack pointer of the next running task from TCB. ; * (R1 = g_stLosTask.pstNewTask->pStackPointer) ; */ LDR R1, [R0] ;/** ; * Restore the stack frame(R4-R11) of the next running task. ; * R12 restore the PRIMASK value of the next running task. ; * NOTE: After exiting the exception handler function, these registers ; * (xPSR,R0-R3,R12,LR,PC) will be automatically ; * restored by the CPU from the stack of the next running task. ; * ; * 1. The stack of the next running task is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * ----------+-----------------------+--------------------------------------+----- ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+----- ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; * ; * 2. If the next running task is run for the first time, the stack is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+-----------------------+--------------------------------------+ ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; */ ADDS R1, #16 LDMFD R1!, {R3-R7} ; restore R8-R12 to R3-R7. MOV R8, R3 ; copy R3-R7 to R8-R12. MOV R9, R4 MOV R10, R5 MOV R11, R6 MOV R12, R7 ;/** ; * Set the stack pointer of the next running task to PSP. ; */ MSR PSP, R1 SUBS R1, #36 LDMFD R1!, {R4-R7} ; restore R4-R7. ;/** ; * Restore the interruption state of the next running task. ; */ MSR PRIMASK, R12 BX LR ALIGN END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m0/keil/los_hw_exc_keil.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2013-2015>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** PRESERVE8 AREA |.text|, CODE, READONLY THUMB ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT NMI_Handler EXPORT HardFault_Handler EXPORT MemManage_Handler EXPORT BusFault_Handler EXPORT UsageFault_Handler ; EXPORT SVC_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT osExcHandleEntry IMPORT g_uwExcTbl IMPORT g_bTaskScheduled IMPORT it_is_memManangeFault IMPORT it_is_busFault IMPORT it_is_usageFault ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_EXC_CAUSE_NMI EQU 18 OS_EXC_CAUSE_HARDFAULT EQU 19 OS_EXC_CAUSE_MEMFAULT EQU 20 OS_EXC_CAUSE_BUSFAULT EQU 21 OS_EXC_CAUSE_USAGEFAULT EQU 22 OS_EXC_CAUSE_SVC EQU 23 HF_DEBUGEVT EQU 24 HF_VECTBL EQU 25 FLAG_ADDR_VALID EQU 0x10000 ; bit 16 FLAG_HWI_ACTIVE EQU 0x20000 ; bit 17 FLAG_NO_FLOAT EQU 0x10000000 ; bit 28 OS_NVIC_CFSR EQU 0xE000ED28 ; include BusFault/MemFault/UsageFault State Regeister OS_NVIC_HFSR EQU 0xE000ED2C ; HardFault State Regeister OS_NVIC_BFAR EQU 0xE000ED38 OS_NVIC_MMFAR EQU 0xE000ED34 OS_NVIC_ACT_BASE EQU 0xE000E300 OS_NVIC_SHCSRS EQU 0xE000ED24 OS_NVIC_SHCSR_MASK EQU 0xC00 ; SYSTICKACT and PENDSVACT ADDR_SETPEND EQU 0XE000E200 ;the addr of setpend register ADDR_CLRPEND EQU 0XE000E280 ;the addr of clrpend register ;**************************************************************************************** ; Function: ; VOID NMI_Handler(VOID); ; Description: ; NMI Handler. ;**************************************************************************************** NMI_Handler ;/** ; * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +------------------------------------------------------+------------------------+ ; * | 31-8 | 7-0 | ; * +------------------------------------------------------+------------------------+ ; * | --- | OS_EXC_CAUSE_NMI | ; * +------------------------------------------------------+------------------------+ ; * < R1 >: invalid ; */ MOVS R0, #OS_EXC_CAUSE_NMI MOVS R1, #0 B osExcDispatch ;**************************************************************************************** ; Function: ; VOID HardFault_Handler(VOID); ; Description: ; HardFault Handler. ;**************************************************************************************** HardFault_Handler ;/** ; * save fault type to R0 ; */ MOVS R0, #OS_EXC_CAUSE_HARDFAULT B osExcDispatch ;**************************************************************************************** ; Function: ; VOID BusFault_Handler(VOID); ; Description: ; BusFault Handler. ;**************************************************************************************** BusFault_Handler BL it_is_busFault ;**************************************************************************************** ; Function: ; VOID MemManage_Handler(VOID); ; Description: ; MemManage Handler. ;**************************************************************************************** MemManage_Handler BL it_is_memManangeFault ;**************************************************************************************** ; Function: ; VOID UsageFault_Handler(VOID); ; Description: ; UsageFault Handler. ;**************************************************************************************** UsageFault_Handler BL it_is_usageFault ;/** ; * When executing osExcDispatch, R2 will be used. ; */ osExcDispatch LDR R2, =ADDR_SETPEND LDR R2, [R2] CMP R2,#0 BEQ _whether_in_initialization ;NO external interrupt occurred ;/** ; * Interrupts and initialization phase always use MSP. ; */ _ExcInMSP ;/** ; * Before executing instruction 'B _handleEntry', MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR | ; * +--------------------------------------------------------------------------------+--------- ; * R13--->| Initial R13--->|<--- #32 --->|<---SAVED_SP ; * | (CPU auto saved) | ; * ; */ _NoFloatInMsp CMP R2,#0 ;check r2 ,find the phase interrupts occurred BEQ __11 MOVS R1,#0x2f ;in interrupt phase ,r1=47 LSLS R0,R0,#8 ORRS R0,R0,R1 ;make r1 available B __12 __11 MOVS R1,#0 ;in initialization phase r1=0 LSLS R0,R0,#8 ORRS R0,R0,R1 ;make r1 available __12 ADD R3, R13, #32 ; #32: skip [R0-R3,R12,LR,PC,xPSR] PUSH {R3} ; push [SAVED_SP]: MSP+32 = Stack pointer in MSP before entering the exception MRS R12, PRIMASK MOV R3,R12 PUSH {R3} MOV R3,R11 PUSH {R3} MOV R3,R10 PUSH {R3} MOV R3,R9 PUSH {R3} MOV R3,R8 PUSH {R3} PUSH {R7} PUSH {R6} PUSH {R5} PUSH {R4} ; push R4-R11,PRIMASK to MSP in certain order B _handleEntry ;/** ; * Check whether during the initialization phase. ; * If g_bTaskScheduled == 0, it is in the initialization phase. ; */ _whether_in_initialization LDR R1, =g_bTaskScheduled LDR R1, [R1] MOVS R3,#1 TST R1,R3 BEQ _ExcInMSP ; initialization phase use MSP ;/** ; * Before executing _handleEntry, MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR | ; * +--------------------------------------------------------------------------------+--------- ; * R13--->| |<--- #32 --->|<---Initial R13 ; * | (copied from PSP) | ; * |<---R2(no use) ; * ; * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR. ; */ _NoFloatInPsp MOVS R1,#1 ;in task ,r1 = 1 LSLS R0,R0,#8 ORRS R0,R0,R1 ;make r1 available MOV R1, R13 SUB R13, #32 ; #32: MSP reserved, used to store stack frame in PSP MRS R3, PSP ADDS R3, R3, #32 ; PSP+32 = Stack pointer of the task before entering the exception PUSH {R3} ; push task SP to MSP MRS R3,PRIMASK PUSH {R3} MOV R3,R11 PUSH {R3} MOV R3,R10 PUSH {R3} MOV R3,R9 PUSH {R3} MOV R3,R8 PUSH {R3} PUSH {R7} PUSH {R6} PUSH {R5} PUSH {R4} MRS R3,PSP ;/* Copy stack frame from the stack of the current running task to MSP */ LDMIA R3!, {R4-R7} SUBS R1,#0X20 STMIA R1!, {R4-R7} LDMIA R3!, {R4-R7} STMIA R1!, {R4-R7} ;/** ; * _handleEntry: Call osExcHandleEntry ; * param1: R0 --- type num and phase ; * param2: R1 --- the sp being used(in Cortex-M0,it is only for debug ) ; * param3: R2 --- external interrupt ID ; * param4: R3 --- Point to the top of the stack(R4 or S16) that the exception stack frame in MSP. ; */ _handleEntry MOV R3, R13 MOV R1,R13 CPSID I LDR R4,=osExcHandleEntry MOV PC,R4 NOP ALIGN END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m0/los_exc.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "los_exc.inc" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cpluscplus */ #endif /* __cpluscplus */ #if (LOSCFG_PLATFORM_EXC == YES) UINT32 g_uwCurNestCount = 0; EXC_INFO_S m_stExcInfo; /* * CFSR register, include UFSR,BFSR and MFSR. * * +----------------------------------------------------------------------------------+ * | UFSR | * |-----------+-----------+-----------+-------+------+-------+----------+------------| * | 31 - 26 | 25 | 24 | 23-20 | 19 | 18 | 17 | 16 | * |-----------+-----------+-----------+-------+------+-------+----------+------------| * | --- | DIVBYZERO | UNALIGNED | --- | NOCP | INVPC | INVSTATE | UNDEFINSTR | * +----------------------------------------------------------------------------------+ * * +----------------------------------------------------------------------------------+ * | BFSR | * |-----------+-----+--------+--------+----------+-------------+-----------+---------| * | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | * |-----------+-----+--------+--------+----------+-------------+-----------+---------| * | BFARVALID | --- | LSPERR | STKERR | UNSTKERR | IMPRECISERR | PRECISERR | IBUSERR | * +----------------------------------------------------------------------------------+ * * +----------------------------------------------------------------------------------+ * | MFSR | * |-----------+-------+---------+---------+-----------+-------+----------+-----------| * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | * |-----------+-------+---------+---------+-----------+-------+----------+-----------| * | MMARVALID | --- | MLSPERR | MSTKERR | MUNSTKERR | --- | DACCVIOL | ICACCVIOL | * +----------------------------------------------------------------------------------+ */ UINT8 g_uwExcTbl[32] = { 0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED, 0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR, 0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR, 0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL }; #if (LOSCFG_SAVE_EXC_INFO == YES) VOID *m_puwExcContent; UINT32 g_uwArraySize = 0; EXC_INFO_ARRAY_S m_stExcArray[OS_EXC_TYPE_MAX - 1]; static VOID osExcSave2DDR(VOID); #endif extern VOID LOS_Reboot(VOID); /***************************************************************************** Function : osExcInfoDisplay Description : EXC info display Input : pstExc --- Pointer to the EXC data Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osExcInfoDisplay(EXC_INFO_S *pstExc) { //in gcc env PRINT_ERR("Phase = 0x%8x\n", pstExc->usPhase); PRINT_ERR("ThrdPid = 0x%8x\n", pstExc->uwThrdPid); PRINT_ERR("R0 = 0x%8x\t%16u\n", pstExc->pstContext->uwR0,pstExc->pstContext->uwR0); PRINT_ERR("R1 = 0x%8x\t%16u\n", pstExc->pstContext->uwR1,pstExc->pstContext->uwR1); PRINT_ERR("R2 = 0x%8x\t%16u\n", pstExc->pstContext->uwR2,pstExc->pstContext->uwR2); PRINT_ERR("R3 = 0x%8x\t%16u\n", pstExc->pstContext->uwR3,pstExc->pstContext->uwR3); PRINT_ERR("R4 = 0x%8x\t%16u\n", pstExc->pstContext->uwR4,pstExc->pstContext->uwR4); PRINT_ERR("R5 = 0x%8x\t%16u\n", pstExc->pstContext->uwR5,pstExc->pstContext->uwR5); PRINT_ERR("R6 = 0x%8x\t%16u\n", pstExc->pstContext->uwR6,pstExc->pstContext->uwR6); PRINT_ERR("R7 = 0x%8x\t%16u\n", pstExc->pstContext->uwR7,pstExc->pstContext->uwR7); PRINT_ERR("R8 = 0x%8x\t%16u\n", pstExc->pstContext->uwR8,pstExc->pstContext->uwR8); PRINT_ERR("R9 = 0x%8x\t%16u\n", pstExc->pstContext->uwR9,pstExc->pstContext->uwR9); PRINT_ERR("R10 = 0x%8x\t%16u\n", pstExc->pstContext->uwR10,pstExc->pstContext->uwR10); PRINT_ERR("R11 = 0x%8x\t%16u\n", pstExc->pstContext->uwR11,pstExc->pstContext->uwR11); PRINT_ERR("R12 = 0x%8x\t%16u\n", pstExc->pstContext->uwR12,pstExc->pstContext->uwR12); PRINT_ERR("PriMask = 0x%8x\t%16u\n", pstExc->pstContext->uwPriMask,pstExc->pstContext->uwPriMask); PRINT_ERR("SP = 0x%8x\t%16u\n", pstExc->pstContext->uwSP,pstExc->pstContext->uwSP); PRINT_ERR("LR = 0x%8x\t%16u\n", pstExc->pstContext->uwLR,pstExc->pstContext->uwLR); PRINT_ERR("PC = 0x%8x\t%16u\n", pstExc->pstContext->uwPC,pstExc->pstContext->uwPC); PRINT_ERR("xPSR = 0x%8x\t%16u\n", pstExc->pstContext->uwxPSR,pstExc->pstContext->uwxPSR); PRINT_ERR("\nplease use the addr2line tool to analyze the call stack on PC:\n"); PRINT_ERR("addr2line -e (xxx.axf/xxx.elf/xxx.out) -a -f "); for (UINT32 i = 0; i < pstExc->uwCallStackDepth; i++) { printf("%8x", pstExc->uwCallStack[i]); } printf("\n"); return; } /***************************************************************************** Function : osExcCallStackAnalysis Description : Call stack analysis Input : pstExc --- point to exception info Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osExcCallStackAnalysis(EXC_INFO_S *pstExc) { UINT32 uwSP; UINT32 uwLR; UINT32 uwPC; UINT32 uwStackStartAddr; UINT32 uwStackSize; UINT32 uwDepth = 0; BOOL bFirstLrValid = FALSE; uwSP = pstExc->pstContext->uwSP; /* sp pointer before entering exception */ /* * save first and second depth * first: PC before entering exception * second: (LR - 4) before entering exception * NOTE: If an exception occurs in the interrupt, LR may be EXC_RETURN, so we must make sure * that LR is valid, exclude EXC_RETURN. */ pstExc->uwCallStack[uwDepth++] = pstExc->pstContext->uwPC; if ((pstExc->pstContext->uwLR >= LOSCFG_EXC_CODE_START_ADDR) && \ (pstExc->pstContext->uwLR <= LOSCFG_EXC_CODE_START_ADDR + LOSCFG_EXC_CODE_SIZE)) { pstExc->uwCallStack[uwDepth++] = pstExc->pstContext->uwLR - sizeof(VOID *); /* lr = pc + 4 */ bFirstLrValid = TRUE; int tmp = uwDepth - 1; } /* * get the start address and size of the stack before entering the exception */ if (pstExc->usPhase == OS_EXC_IN_TASK) /* task use PSP */ { uwStackStartAddr = g_stLosTask.pstRunTask->uwTopOfStack; uwStackSize = g_stLosTask.pstRunTask->uwStackSize; } else /* init and interrupt use MSP */ { uwStackStartAddr = LOSCFG_EXC_MSP_START_ADDR; uwStackSize = LOSCFG_EXC_MSP_SIZE; } /* * check stack overflow, if so, compensate for overflow, readjust stack start address and size. */ if (uwSP < uwStackStartAddr) /* stack top overflow */ { if (pstExc->usPhase == OS_EXC_IN_TASK) { PRINT_ERR("task %s stack top overflow\n", g_stLosTask.pstRunTask->pcTaskName); } else { PRINT_ERR("MSP top overflow\n"); } uwStackSize += (uwStackStartAddr - uwSP); /* compensate overflow size */ uwStackStartAddr = uwSP; /* readjust stack start address */ } /* * Traverses the entire stack from the top of the stack to the bottom of the stack, * find all LR. */ for (; uwSP < uwStackStartAddr + uwStackSize; uwSP += sizeof(UINT32*)) { uwLR = *(UINT32 *)uwSP; if (uwLR % 2 == 0) /* Thumb instruction, LR bit0 == 1 */ { continue; } /* * It may be LR, which must be further determined based on the start address * and end address of the code segment. */ if ((uwLR >= LOSCFG_EXC_CODE_START_ADDR) && (uwLR <= LOSCFG_EXC_CODE_START_ADDR + LOSCFG_EXC_CODE_SIZE) \ && (uwDepth < LOSCFG_EXC_CALL_STACK_ANALYSIS_MAX_DEPTH)) { uwPC = uwLR - sizeof(VOID *); /* lr = pc + 4 */ /* the second depth(first LR) has been saved */ if ((uwDepth == 2) && (uwPC == pstExc->uwCallStack[1]) && (bFirstLrValid == TRUE)) { continue; } pstExc->uwCallStack[uwDepth++] = uwPC; } } pstExc->uwCallStackDepth = uwDepth; /* save call stack depth */ return; } /***************************************************************************** Function : osExcHandleEntry Description : EXC handler entry Input : uwExcType --- EXC type : uwFaultAddr --- The address of an accurate address access error : uwPid --- Interrupt number : puwExcBufAddr --- Point to the stack frame without FPU Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osExcHandleEntry(UINT32 uwExcType, UINT32 uwUsingSp, UINT32 uwID, EXC_CONTEXT_S *pstExcBufAddr) { g_uwCurNestCount++; #if (LOSCFG_PLATFORM_HWI == YES) extern UINT32 g_vuwIntCount; g_vuwIntCount++; #endif int tmp_type = uwExcType & 0x0000ff00; tmp_type = tmp_type >> 8; /* Save interrupt nesting times */ m_stExcInfo.usNestCnt = (UINT16)g_uwCurNestCount; /* uwExcType 8-15 bits: exc type */ m_stExcInfo.usType = (UINT16)tmp_type; #if (LOSCFG_SAVE_EXC_INFO == YES) /* Initializing a pointer to save an exception context */ m_puwExcContent = (UINT32 *)m_aucTaskArray; #endif /* Save the fault address when an exception occurs if it is valid */ /* Save the phase of the exception */ extern BOOL g_bTaskScheduled; int tmp_phase = uwExcType; tmp_phase = uwExcType & 0x000000ff; m_stExcInfo.usPhase = (UINT16)tmp_phase; m_stExcInfo.uwThrdPid = uwID; /* interrupt number */ m_stExcInfo.usFpuContext = 0; m_stExcInfo.pstContext = pstExcBufAddr; /* point to r3 */ osExcCallStackAnalysis(&m_stExcInfo); osExcInfoDisplay(&m_stExcInfo); LOS_Reboot(); } #if (LOSCFG_SAVE_EXC_INFO == YES) /***************************************************************************** Function : osExcSaveIntStatus Description : Save NVIC register group Input : None Output : None Return : None *****************************************************************************/ static VOID osExcSaveIntStatus(VOID) { /* Save exc type */ *((UINT32 *)m_puwExcContent) = OS_EXC_TYPE_NVIC; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save total size of NVIC */ *((UINT32 *)m_puwExcContent) = 0x164; // = OS_NVIC_INT_ENABLE_SIZE + OS_NVIC_INT_PEND_SIZE + OS_NVIC_INT_ACT_SIZE + OS_NVIC_INT_PRI_SIZE + 12 + 4 + 4 m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save interrupt enable register group (start addr: 0xE000E100, size: 32bytes, CMSIS-Core: NVIC->ISER[0 - 7]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_SETENA_BASE, OS_NVIC_INT_ENABLE_SIZE); m_puwExcContent =(UINT8 *)m_puwExcContent + OS_NVIC_INT_ENABLE_SIZE; /* Save interrupt pend register group (start addr: 0xE000E200, size: 32bytes, CMSIS-Core: NVIC->ISPR[0 - 7]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_SETPEND_BASE, OS_NVIC_INT_PEND_SIZE); m_puwExcContent = (UINT8 *)m_puwExcContent + OS_NVIC_INT_PEND_SIZE; /* Save interrupt active status register group (start addr: 0xE000E300, size: 32bytes, CMSIS-Core: NVIC->IABR[0 - 7]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_INT_ACT_BASE, OS_NVIC_INT_ACT_SIZE); m_puwExcContent = (UINT8 *)m_puwExcContent + OS_NVIC_INT_ACT_SIZE; /* Save interrupt priority register group (start addr: 0xE000E400, size: 240bytes), CMSIS-Core: NVIC->IP[0 - 239] */ memcpy(m_puwExcContent, (const void *)OS_NVIC_PRI_BASE, OS_NVIC_INT_PRI_SIZE); m_puwExcContent = (UINT8 *)m_puwExcContent + OS_NVIC_INT_PRI_SIZE; /* Save system exception priority register group (start addr: 0xE000ED18, size: 12bytes, CMSIS-Core: SCB->SHP[0 - 11]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_EXCPRI_BASE, 12); m_puwExcContent = (UINT8 *)m_puwExcContent + 12; /* Save system processing control and state register group (start addr: 0xE000ED24, size: 4bytes, CMSIS-Core: SCB->SHCSR) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_SHCSR, 4); m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save interrupt control and status register group (start addr: 0xE000ED04, size: 4bytes, CMSIS-Core: SCB->ICSR) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_INT_CTRL, 4); m_puwExcContent = (UINT8 *)m_puwExcContent + 4; return; } /***************************************************************************** Function : osExcRegister Description : Register exception Input : uwType --- exception type : pFunc --- exception callback function : pArg --- exception save info arg, not pFunc Output : None Return : None *****************************************************************************/ VOID osExcRegister(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, VOID *pArg) { EXC_INFO_ARRAY_S *pstExcInfo; if (uwType == 0 || uwType >= OS_EXC_TYPE_MAX || pFunc == NULL) { PRINT_ERR("osExcRegister ERROR!\n"); return; } pstExcInfo = &(m_stExcArray[uwType - 1]); pstExcInfo->uwType = uwType; pstExcInfo->pFnExcInfoCb = pFunc; pstExcInfo->pArg = pArg; pstExcInfo->uwValid = TRUE; } /***************************************************************************** Function : osExcSaveSysInfo Description : Saving exception information by calling callback function recursively Input : uwType --- exception type(OS_EXC_TYPE_CONTEXT+1 ---> OS_EXC_TYPE_MAX-1) : pFunc --- callback function : uwLoop --- loop total count : uwLen --- The size of the data saved each time : uwIdx --- loop index Output : None Return : None *****************************************************************************/ VOID osExcSaveSysInfo(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, UINT32 uwLoop, UINT32 uwLen, UINT32 uwIdx) { UINT32 uwRet; UINT32 uwBuffer[OS_EXC_MAX_BUF_LEN]; /* Save exception type and size */ *((UINT32 *)m_puwExcContent) = uwType; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; *((UINT32 *)m_puwExcContent) = uwLen * (uwLoop - uwIdx); m_puwExcContent = (UINT8 *)m_puwExcContent + 4; for (; uwIdx < uwLoop; uwIdx++) { memset((VOID *)uwBuffer, 0, sizeof(UINT32) * OS_EXC_MAX_BUF_LEN); uwRet = pFunc(uwIdx, (VOID *)uwBuffer); if (LOS_OK == uwRet) { memcpy(m_puwExcContent, (VOID *)uwBuffer, uwLen); } m_puwExcContent =(UINT8 *)m_puwExcContent + uwLen; } } /***************************************************************************** Function : osExcSaveInfo Description : save exception info Input : uwType --- exception type(OS_EXC_TYPE_CONTEXT+1 ---> OS_EXC_TYPE_MAX-1) : pFunc --- exception callback : pArg --- register arg, used to generate the arg passed to the callback Output : None Return : None *****************************************************************************/ static VOID osExcSaveInfo(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, VOID *pArg) { UINT32 uwLen; UINT32 uwIdx; UINT32 uwLoop; UINT32 uwTaskSwitchCount = 0; OS_TASK_SWITCH_INFO *pstTaskSwitchInfo; switch(uwType) { case OS_EXC_TYPE_TSK: /* save task info */ uwLen = sizeof(TSK_INFO_S); uwLoop = *(UINT32 *)pArg; uwIdx = 0; break; case OS_EXC_TYPE_QUE: /* save queue info */ uwLen = sizeof(QUEUE_INFO_S); uwLoop = *(UINT32 *)pArg; uwIdx = 0; break; case OS_EXC_TYPE_NVIC: /* save NVIC info */ (VOID)pFunc(0, 0); goto END; case OS_EXC_TYPE_TSK_SWITCH: /* save task switch info */ pstTaskSwitchInfo = pArg; uwTaskSwitchCount = pstTaskSwitchInfo->ucIsFull & 0x7F; uwLen = sizeof(UINT32) + sizeof(CHAR) * LOS_TASK_NAMELEN; /* auwPID + acName */ if (pstTaskSwitchInfo->ucIsFull & 0x80) { uwIdx = pstTaskSwitchInfo->ucIdx; uwLoop = uwIdx + uwTaskSwitchCount; } else { uwIdx = 0; uwLoop = pstTaskSwitchInfo->ucIdx; } break; case OS_EXC_TYPE_MEM: /* save mem info */ uwLen = sizeof(MEM_INFO_S); uwLoop = *(UINT32 *)pArg; uwIdx = 0; break; default: goto END; } osExcSaveSysInfo(uwType, (EXC_INFO_SAVE_CALLBACK)pFunc, uwLoop, uwLen, uwIdx); END: return; } /***************************************************************************** Function : osExcSave2DDR Description : Save exception info to RAM Input : None Output : None Return : None *****************************************************************************/ static VOID osExcSave2DDR(VOID) { UINT32 uwIdx = 0; UINT32 uwExcContextSize; if (m_stExcInfo.usFpuContext == 1) { uwExcContextSize = sizeof(EXC_CONTEXT_S); } else { uwExcContextSize = sizeof(EXC_CONTEXT_S) - 136; /* except FPU register */ } memset(m_puwExcContent, 0xff, g_uwArraySize); /* Cortex-M type */ *((UINT32 *)m_puwExcContent) = 4; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* * Save exception type: OS_EXC_TYPE_CONTEXT */ *((UINT32 *)m_puwExcContent) = OS_EXC_TYPE_CONTEXT; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* The size of struct EXC_INFO_S(except member EXC_CONTEXT_S*) and exception context size */ *((UINT32 *)m_puwExcContent) = sizeof(EXC_INFO_S) - sizeof(EXC_CONTEXT_S *) + uwExcContextSize; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save struct m_stExcInfo except m_stExcInfo.pstContext */ memcpy((VOID *)m_puwExcContent, (VOID *)&m_stExcInfo, sizeof(EXC_INFO_S) - sizeof(EXC_CONTEXT_S *)); m_puwExcContent = (UINT8 *)m_puwExcContent + sizeof(EXC_INFO_S) - sizeof(EXC_CONTEXT_S *); /* Save struct EXC_CONTEXT_S */ if (m_stExcInfo.usFpuContext == 0) { #if FPU_EXIST /* m_stExcInfo.pstContext: init --- point to S16, S16->S31 invalid * + 64 --- point to uwR4 * copy uwR4 -> uwxPSR */ memcpy((VOID *)m_puwExcContent, (UINT8 *)m_stExcInfo.pstContext + 64, uwExcContextSize); #else memcpy((VOID *)m_puwExcContent, m_stExcInfo.pstContext, uwExcContextSize); #endif } else { memcpy((VOID *)m_puwExcContent, m_stExcInfo.pstContext, uwExcContextSize); } m_puwExcContent = (UINT8 *)m_puwExcContent + uwExcContextSize; /* * Save exception type: OS_EXC_TYPE_CONTEXT+1 ---> OS_EXC_TYPE_MAX-1 */ for (uwIdx = 0; uwIdx < OS_EXC_TYPE_MAX - 1; uwIdx++) { if (m_stExcArray[uwIdx].uwValid == FALSE) { continue; } osExcSaveInfo(m_stExcArray[uwIdx].uwType, m_stExcArray[uwIdx].pFnExcInfoCb, m_stExcArray[uwIdx].pArg); } /* * Save exception type: OS_EXC_TYPE_MAX */ *((UINT32 *)m_puwExcContent) = OS_EXC_TYPE_MAX; m_puwExcContent = (UINT8*)m_puwExcContent + 4; return; } #endif /*(LOSCFG_SAVE_EXC_INFO == YES)*/ /***************************************************************************** Function : osExcInit Description : Initializes the EXC Input : None Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT_INIT VOID osExcInit(UINT32 uwArraySize) { #if (LOSCFG_PLATFORM_HWI == YES) /* Register exception handler to interrupt vector table in RAM */ m_pstHwiForm[-14 + OS_SYS_VECTOR_CNT] = NMI_Handler; m_pstHwiForm[-13 + OS_SYS_VECTOR_CNT] = HardFault_Handler; m_pstHwiForm[-12 + OS_SYS_VECTOR_CNT] = MemManage_Handler; m_pstHwiForm[-11 + OS_SYS_VECTOR_CNT] = BusFault_Handler; m_pstHwiForm[-10 + OS_SYS_VECTOR_CNT] = UsageFault_Handler; m_pstHwiForm[-5 + OS_SYS_VECTOR_CNT] = SVC_Handler; #endif /* Enable USGFAULT(BIT_18), BUSFAULT(BIT_17), MEMFAULT(BIT_16) */ *(volatile UINT32 *)OS_NVIC_SHCSR |= 0x70000; /* Enable DIV 0(BIT_4) exception, unaligned(BIT_3) disable */ *(volatile UINT32 *)OS_NVIC_CCR |= 0x10; #if (LOSCFG_SAVE_EXC_INFO == YES) g_uwArraySize = uwArraySize; osExcRegister((EXC_INFO_TYPE)OS_EXC_TYPE_NVIC, (EXC_INFO_SAVE_CALLBACK)osExcSaveIntStatus, NULL); #endif } VOID osBackTrace(VOID) { return; } #endif /*(LOSCFG_PLATFORM_EXC == YES)*/ #ifdef __cplusplus #if __cplusplus } #endif /* __cpluscplus */ #endif /* __cpluscplus */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m0/los_exc.inc ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _LOS_EXC_INC #define _LOS_EXC_INC #include "los_exc.ph" #include "los_sys.ph" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cpluscplus */ #endif /* __cpluscplus */ #ifdef __cplusplus #if __cplusplus } #endif /* __cpluscplus */ #endif /* __cpluscplus */ #endif /* _LOS_EXC_INC */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m0/los_exc.ph ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _LOS_EXC_PH #define _LOS_EXC_PH #include "los_exc.h" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ #if (LOSCFG_PLATFORM_EXC == YES) typedef enum { OS_EXC_TYPE_CONTEXT = 0, OS_EXC_TYPE_TSK = 1, OS_EXC_TYPE_QUE = 2, OS_EXC_TYPE_NVIC = 3, OS_EXC_TYPE_TSK_SWITCH = 4, OS_EXC_TYPE_MEM = 5, OS_EXC_TYPE_MAX = 6 } EXC_INFO_TYPE; typedef struct tagExcInfoCallBackArray { EXC_INFO_TYPE uwType; UINT32 uwValid; EXC_INFO_SAVE_CALLBACK pFnExcInfoCb; VOID* pArg; }EXC_INFO_ARRAY_S; #define OS_NVIC_SHCSR 0xE000ED24 #define OS_NVIC_CCR 0xE000ED14 #define OS_NVIC_INT_ENABLE_SIZE 0x20 #define OS_NVIC_INT_PRI_SIZE 0xF0 #define OS_NVIC_INT_PEND_SIZE OS_NVIC_INT_ACT_SIZE #define OS_NVIC_INT_ACT_SIZE OS_NVIC_INT_ENABLE_SIZE #define MAX_SCENE_INFO_SIZE (8 + sizeof(EXC_INFO_S) - 4 + sizeof(EXC_CONTEXT_S)) #define MAX_TSK_INFO_SIZE (8 + sizeof(TSK_INFO_S) * (LOSCFG_BASE_CORE_TSK_LIMIT + 1)) #define MAX_INT_INFO_SIZE (8 + 0x164) #if (LOSCFG_BASE_IPC_QUEUE == YES) #define MAX_QUEUE_INFO_SIZE (8 + sizeof(QUEUE_INFO_S) * LOSCFG_BASE_IPC_QUEUE_LIMIT) #else #define MAX_QUEUE_INFO_SIZE (0) #endif #if (LOSCFG_BASE_CORE_EXC_TSK_SWITCH == YES) #define MAX_SWITCH_INFO_SIZE (8 + (sizeof(UINT32) + sizeof(CHAR) * LOS_TASK_NAMELEN) * OS_TASK_SWITCH_INFO_COUNT) #else #define MAX_SWITCH_INFO_SIZE (0) #endif #if (LOSCFG_BASE_MEM_NODE_INTEGRITY_CHECK == YES) #define MAX_MEM_INFO_SIZE (8 + sizeof(MEM_INFO_S) * OS_SYS_MEM_NUM) #else #define MAX_MEM_INFO_SIZE (0) #endif #if (LOSCFG_SAVE_EXC_INFO == YES) #define MAX_EXC_MEM_SIZE ( 4 + MAX_SCENE_INFO_SIZE + MAX_TSK_INFO_SIZE + MAX_QUEUE_INFO_SIZE + MAX_INT_INFO_SIZE + MAX_SWITCH_INFO_SIZE + MAX_MEM_INFO_SIZE + 4) #else #define MAX_EXC_MEM_SIZE ( 0 ) #endif extern VOID osExcRegister(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, VOID *pArg); #endif #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ #endif ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m3/gcc/los_dispatch_gcc.S ================================================ /** ---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /** ---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**************************************************************************************** * EXPORT FUNCTIONS ****************************************************************************************/ .global LOS_IntLock .global LOS_IntUnLock .global LOS_IntRestore .global LOS_StartToRun .global osTaskSchedule .global PendSV_Handler /**************************************************************************************** * EXTERN PARAMETERS ****************************************************************************************/ .extern g_stLosTask .extern g_pfnTskSwitchHook .extern g_bTaskScheduled /**************************************************************************************** * EQU ****************************************************************************************/ .equ OS_NVIC_INT_CTRL, 0xE000ED04 /* Interrupt Control and State Register. */ .equ OS_NVIC_PENDSVSET, 0x10000000 /* Value to trigger PendSV exception. */ .equ OS_NVIC_SYSPRI2, 0xE000ED20 /* System Handler Priority Register 2. */ .equ OS_NVIC_PENDSV_SYSTICK_PRI, 0xFFFF0000 /* SysTick + PendSV priority level (lowest). */ .equ OS_TASK_STATUS_RUNNING, 0x0010 /* Task Status Flag (RUNNING). */ /**************************************************************************************** * CODE GENERATION DIRECTIVES ****************************************************************************************/ .section .text .thumb .syntax unified .arch armv7-m /**************************************************************************************** * Function: * VOID LOS_StartToRun(VOID); * Description: * Start the first task, which is the highest priority task in the priority queue. * Other tasks are started by task scheduling. ****************************************************************************************/ .type LOS_StartToRun, %function LOS_StartToRun: CPSID I /** * Set PendSV and SysTick prority to the lowest. * read ---> modify ---> write-back. */ LDR R0, =OS_NVIC_SYSPRI2 LDR R1, =OS_NVIC_PENDSV_SYSTICK_PRI LDR R2, [R0] ORR R1, R1, R2 STR R1, [R0] /** * Set g_bTaskScheduled = 1. */ LDR R0, =g_bTaskScheduled MOV R1, #1 STR R1, [R0] /** * Set g_stLosTask.pstRunTask = g_stLosTask.pstNewTask. */ LDR R0, =g_stLosTask LDR R1, [R0, #4] STR R1, [R0] /** * Set g_stLosTask.pstRunTask->usTaskStatus |= OS_TASK_STATUS_RUNNING. */ LDR R1, [R0] LDRH R2, [R1, #4] MOV R3, #OS_TASK_STATUS_RUNNING ORR R2, R2, R3 STRH R2, [R1, #4] /** * Restore the default stack frame(R0-R3,R12,LR,PC,xPSR) of g_stLosTask.pstRunTask to R0-R7. * Return by setting the CONTROL register. * * The initial stack of the current running task is as follows: * * POP: Restore the context of the current running task ===>| * High addr--->| * Bottom of the stack--->| * ----------+-----------------------+--------------------------------------+ * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | * ----------+-----------------------+--------------------------------------+ * |<---Top of the stack, restored from g_stLosTask.pstRunTask->pStackPointer * |<--- skip --->|<--- copy to R0-R7 --->| * R12 to PSP--->| * Stack pointer after LOS_StartToRun--->| */ LDR R12, [R1] ADD R12, R12, #36 /* skip R4-R11, PRIMASK. */ LDMFD R12!, {R0-R7} /** * Set the stack pointer of g_stLosTask.pstRunTask to PSP. */ MSR PSP, R12 /** * Set the CONTROL register, after schedule start, privilege level and stack = PSP. */ MOV R12, #2 MSR CONTROL, R12 /** * Enable interrupt. (The default PRIMASK value is 0, so enable directly) */ MOV LR, R5 CPSIE I /** * Jump directly to the default PC of g_stLosTask.pstRunTask, the field information * of the main function will be destroyed and will never be returned. */ BX R6 /**************************************************************************************** * Function: * UINTPTR LOS_IntLock(VOID); * Description: * Disable all interrupts except Reset,NMI and HardFault. * The value of currnet interruption state will be returned to the caller to save. * * Function: * VOID LOS_IntRestore(UINTPTR uvIntSave); * Description: * Restore the locked interruption of LOS_IntLock. * The caller must pass in the value of interruption state previously saved. ****************************************************************************************/ .type LOS_IntLock, %function LOS_IntLock: MRS R0, PRIMASK CPSID I BX LR .type LOS_IntUnLock, %function LOS_IntUnLock: MRS R0, PRIMASK CPSIE I BX LR .type LOS_IntRestore, %function LOS_IntRestore: MSR PRIMASK, R0 BX LR /**************************************************************************************** * Function: * VOID osTaskSchedule(VOID); * Description: * Start the task swtich process by software trigger PendSV interrupt. ****************************************************************************************/ .type osTaskSchedule, %function osTaskSchedule: LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] BX LR /**************************************************************************************** * Function: * VOID PendSV_Handler(VOID); * Description: * PendSV interrupt handler, switch the context of the task. * First: Save the context of the current running task(g_stLosTask.pstRunTask) * to its own stack. * Second: Restore the context of the next running task(g_stLosTask.pstNewTask) * from its own stack. ****************************************************************************************/ .type PendSV_Handler, %function PendSV_Handler: /** * R12: Save the interruption state of the current running task. * Disable all interrupts except Reset,NMI and HardFault */ MRS R12, PRIMASK CPSID I /** * Call task switch hook. */ LDR R2, =g_pfnTskSwitchHook LDR R2, [R2] CBZ R2, TaskSwitch PUSH {R12, LR} BLX R2 POP {R12, LR} TaskSwitch: /** * R0 = now stack pointer of the current running task. */ MRS R0, PSP /** * Save the stack frame(R4-R11) of the current running task. * R12 save the PRIMASK value of the current running task. * NOTE: Before entering the exception handler function, these registers * (xPSR,PC,LR,R12,R3-R0) have been automatically * saved by the CPU in the stack of the current running task. * * The stack of the current running task is as follows: * * |<=== PUSH: Save the context of the current running task * | High addr--->| * ----------+-----------------------+--------------------------------------+----- * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | * ----------+-----------------------+--------------------------------------+----- * Stack pointer before entering exception--->| * |<--- cpu auto saved --->| * |<---PSP to R0 * |<---Top of the stack, save to g_stLosTask.pstRunTask->pStackPointer */ STMFD R0!, {R4-R12} /* save the core registers and PRIMASK. */ /** * R5,R8. */ LDR R5, =g_stLosTask MOV R8, #OS_TASK_STATUS_RUNNING /** * Save the stack pointer of the current running task to TCB. * (g_stLosTask.pstRunTask->pStackPointer = R0) */ LDR R6, [R5] STR R0, [R6] /** * Clear the RUNNING state of the current running task. * (g_stLosTask.pstRunTask->usTaskStatus &= ~OS_TASK_STATUS_RUNNING) */ LDRH R7, [R6, #4] BIC R7, R7, R8 STRH R7, [R6, #4] /** * Switch the current running task to the next running task. * (g_stLosTask.pstRunTask = g_stLosTask.pstNewTask) */ LDR R0, [R5, #4] STR R0, [R5] /** * Set the RUNNING state of the next running task. * (g_stLosTask.pstNewTask->usTaskStatus |= OS_TASK_STATUS_RUNNING) */ LDRH R7, [R0, #4] ORR R7, R7, R8 STRH R7, [R0, #4] /** * Restore the stack pointer of the next running task from TCB. * (R1 = g_stLosTask.pstNewTask->pStackPointer) */ LDR R1, [R0] /** * Restore the stack frame(R4-R11) of the next running task. * R12 restore the PRIMASK value of the next running task. * NOTE: After exiting the exception handler function, these registers * (PC,xPSR,R0-R3,R12,LR) will be automatically * restored by the CPU from the stack of the next running task. * * 1. The stack of the next running task is as follows: * * POP: Restore the context of the next running task ===>| * High addr--->| * ----------+-----------------------+--------------------------------------+----- * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | * ----------+-----------------------+--------------------------------------+----- * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer * R1 to PSP--->| * |<--- cpu auto restoring --->| * Stack pointer after exiting exception--->| * * 2. If the next running task is run for the first time, the stack is as follows: * * POP: Restore the context of the next running task ===>| * High addr--->| * Bottom of the stack--->| * ----------+-----------------------+--------------------------------------+ * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | * ----------+-----------------------+--------------------------------------+ * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer * R1 to PSP--->| * |<--- cpu auto restoring --->| * Stack pointer after exiting exception--->| */ LDMFD R1!, {R4-R12} /* restore the core registers and PRIMASK. */ /** * Set the stack pointer of the next running task to PSP. */ MSR PSP, R1 /** * Restore the interruption state of the next running task. */ MSR PRIMASK, R12 BX LR ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m3/gcc/los_hw_exc_gcc.S ================================================ /*---------------------------------------------------------------------------- Copyright (c) <2013-2015>, All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------- Notice of Export Control Law =============================================== Huawei LiteOS may be subject to applicable export control laws and regulations, which might include those applicable to Huawei LiteOS of U.S. and the country in which you are located. Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such applicable export control laws and regulations. ---------------------------------------------------------------------------*/ /***************************************************************************************** CODE GENERATION DIRECTIVES *****************************************************************************************/ .syntax unified .arch armv7e-m .thumb .section .text /***************************************************************************************** EXPORT FUNCTIONS *****************************************************************************************/ .global NMI_Handler .global HardFault_Handler .global MemManage_Handler .global BusFault_Handler .global UsageFault_Handler .global SVC_Handler .global UART4_IRQHandler /***************************************************************************************** EXTERN PARAMETERS *****************************************************************************************/ .extern osExcHandleEntry .extern g_uwExcTbl .extern g_bTaskScheduled /**************************************************************************************** *****************************************************************************************/ .equ OS_EXC_CAUSE_NMI, 18 .equ OS_EXC_CAUSE_HARDFAULT, 19 .equ OS_EXC_CAUSE_MEMFAULT, 20 .equ OS_EXC_CAUSE_BUSFAULT, 21 .equ OS_EXC_CAUSE_USAGEFAULT, 22 .equ OS_EXC_CAUSE_SVC, 23 .equ HF_DEBUGEVT, 24 .equ HF_VECTBL, 25 .equ FLAG_ADDR_VALID, 0x10000 /* bit 16 */ .equ FLAG_HWI_ACTIVE, 0x20000 /* bit 17 */ .equ FLAG_NO_FLOAT, 0x10000000 /* bit 28 */ .equ OS_NVIC_CFSR, 0xE000ED28 /* include BusFault/MemFault/UsageFault State Regeister */ .equ OS_NVIC_HFSR, 0xE000ED2C /* HardFault State Regeister */ .equ OS_NVIC_BFAR, 0xE000ED38 .equ OS_NVIC_MMFAR, 0xE000ED34 .equ OS_NVIC_ACT_BASE, 0xE000E300 .equ OS_NVIC_SHCSRS, 0xE000ED24 .equ OS_NVIC_SHCSR_MASK, 0xC00 /* SYSTICKACT and PENDSVACT */ /**************************************************************************************** Function: VOID NMI_Handler(VOID) Description: NMI Handler. *****************************************************************************************/ .type NMI_Handler, %function NMI_Handler: /* * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. * < R0 >: * +------------------------------------------------------+------------------------+ * | 31-8 | 7-0 | * +------------------------------------------------------+------------------------+ * | --- | OS_EXC_CAUSE_NMI | * +------------------------------------------------------+------------------------+ * < R1 >: invalid */ MOV R0, #OS_EXC_CAUSE_NMI MOV R1, #0 B osExcDispatch /**************************************************************************************** Function: VOID HardFault_Handler(VOID) Description: HardFault Handler. ****************************************************************************************/ .type HardFault_Handler, %function HardFault_Handler: /** * Check HardFault state register. * * HFSR: * +----------+--------+--------+--------+-------+ * | 31 | 30 | 29 - 2 | 1 | 0 | * +----------+--------+--------+--------+-------+ * | DEBUGEVT | FORCED | -- | VECTBL | -- | * +----------+--------+--------+--------+-------+ */ MOV R0, #OS_EXC_CAUSE_HARDFAULT LDR R2, =OS_NVIC_HFSR LDR R2, [R2] /** * Check whether HardFault are triggered by debugging events. * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. * < R0 >: * +----------------------------------------+-------------+------------------------+ * | 31-16 | 15-8 | 7-0 | * +----------------------------------------+-------------+------------------------+ * | --- | HF_DEBUGEVT | OS_EXC_CAUSE_HARDFAULT | * +----------------------------------------+-------------+------------------------+ * < R1 >: invalid */ MOV R1, #HF_DEBUGEVT ORR R0, R0, R1, LSL #0x8 TST R2, #0x80000000 BNE osExcDispatch /** * Check whether HardFault is caused by the failure of the fetch vector. * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. * < R0 >: * +----------------------------------------+-------------+------------------------+ * | 31-16 | 15-8 | 7-0 | * +----------------------------------------+-------------+------------------------+ * | --- | HF_VECTBL | OS_EXC_CAUSE_HARDFAULT | * +----------------------------------------+-------------+------------------------+ * < R1 >: invalid */ AND R0, R0, #0x000000FF MOV R1, #HF_VECTBL ORR R0, R0, R1, LSL #0x8 TST R2, #0x00000002 BNE osExcDispatch /** * If it`s not DEBUGEVT and VECTBL, that is FORCED, then read the CFSR register to * check BusFault, MemFault and UsageFault. * R0: OS_EXC_CAUSE_HARDFAULT * * CFSR: * +----------------+--------+--------+ * | 31-16 | 15-8 | 7-0 | * +----------------+--------+--------+ * | UFSR | BFSR | MFSR | * +----------------+--------+--------+ */ AND R0, R0, #0x000000FF LDR R2, =OS_NVIC_CFSR LDR R2, [R2] TST R2, #0x8000 /* BFSR->BFARVALID */ BNE _HFBusFault /* BusFault */ TST R2, #0x80 /* MFSR->MMARVALID */ BNE _HFMemFault /* MemFault */ /** * BFARVALID and MMARVALID flag both invalid. * R12: 0 --- The error address is invalid. */ MOV R12, #0 B osHFExcCommonBMU /** * BFARVALID flag valid, read BFAR register. * R1 : BFAR value --- The address value of a bus error. * R12: The error address is valid. */ _HFBusFault: LDR R1, =OS_NVIC_BFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID B osHFExcCommonBMU /** * MMARVALID flag valid, read MMFAR register. * R1 : MMFAR value --- The address value of memory management error. * R12: The error address is valid. */ _HFMemFault: LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID /** * osHFExcCommonBMU: --- Get specific error status from table g_uwExcTbl, stored in R0. * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. * < R0 >: * +-------------------+-----------------+------------------+------------------------+ * | 31-17 | 16 | 15-8 | 7-0 | * +-------------------+-----------------+------------------+------------------------+ * | --- | FLAG_ADDR_VALID | Error state code | OS_EXC_CAUSE_HARDFAULT | * | | or | in | | * | | 0(invalid) | table g_uwExcTbl | | * +-------------------+-----------------+------------------+------------------------+ * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, * else invalid. */ osHFExcCommonBMU: CLZ R2, R2 LDR R3, =g_uwExcTbl ADD R3, R3, R2 LDRB R2, [R3] ORR R0, R0, R2, LSL #0x8 ORR R0, R0, R12 B osExcDispatch /**************************************************************************************** Function: VOID BusFault_Handler(VOID) Description: BusFault Handler. ****************************************************************************************/ .type BusFault_Handler, %function BusFault_Handler: LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_BUSFAULT TST R0, #0x8000 /* BFSR->BFARVALID */ BEQ _ExcBusNoADDR LDR R1, =OS_NVIC_BFAR LDR R1, [R1] /* R1: The value of BFAR */ MOV R12, #FLAG_ADDR_VALID /* R12: BusFault addr valid */ AND R0, R0, #0x3F00 /* R0: Reserved the b13-b8 of the BFSR */ B osExcCommonBMU _ExcBusNoADDR: MOV R12, #0 /* R12: BusFault addr invalid */ AND R0, R0, #0x3F00 /* R0: Reserved the b13-b8 of the BFSR */ B osExcCommonBMU /**************************************************************************************** Function: VOID MemManage_Handler(VOID) Description: MemManage Handler. ****************************************************************************************/ .type MemManage_Handler, %function MemManage_Handler: LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_MEMFAULT TST R0, #0x80 /* MFSR->MMARVALID BEQ _ExcMemNoADDR LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] /* R1: The value of MMFAR */ MOV R12, #FLAG_ADDR_VALID /* R12: MemFault addr valid */ AND R0, R0, #0x3B /* R0: Reserved the b5-b0 of the MFSR */ B osExcCommonBMU _ExcMemNoADDR: MOV R12, #0 /* R12: MemFault addr invalid */ AND R0, R0, #0x3B /* R0: Reserved the b5-b0 of the MFSR */ B osExcCommonBMU /**************************************************************************************** Function: VOID UsageFault_Handler(VOID) Description: UsageFault Handler. ****************************************************************************************/ .type UsageFault_Handler, %function UsageFault_Handler: LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_USAGEFAULT LDR R1, =#0x030F LSL R1, R1, #16 AND R0, R0, R1 /* R0: reserved UFSR */ MOV R12, #0 /* R12: Fault addr invalid */ /** * osExcCommonBMU: BusFault_Handler,MemManage_Handler and UsageFault_Handler share. * Get specific error status from table g_uwExcTbl, stored in R0. * Before executing osExcDispatch, the value of R0 is as follows. * < R0 >: * +-------------------+-----------------+------------------+------------------------+ * | 31-17 | 16 | 15-8 | 7-0 | * +-------------------+-----------------+------------------+------------------------+ * | --- | FLAG_ADDR_VALID | Error state code |OS_EXC_CAUSE_BUSFAULT or| * | | or | in |OS_EXC_CAUSE_MEMFAULT or| * | | 0(invalid) | table g_uwExcTbl |OS_EXC_CAUSE_USAGEFAULT | * +-------------------+-----------------+------------------+------------------------+ * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, * else invalid. */ osExcCommonBMU: CLZ R0, R0 LDR R3, =g_uwExcTbl ADD R3, R3, R0 LDRB R0, [R3] LSL R0, R0, #0x8 ORR R0, R0, R2 ORR R0, R0, R12 MRS R2,PSP /* PSP-->>37D8 */ /* **************************************************************************************** osExcDispatch: NMI_Handler, HardFault_Handler, SVC_Handler, BusFault_Handler, MemManage_Handler, UsageFault_Handler sharing. ****************************************************************************************/ /** * When executing osExcDispatch, R0, R1 will be used. * The possible values of R0 and R1 are as follows. * * < R0 >: * +----------------+-----------------+---------------------+------------------------+ * | 31-17 | 16 | 15-8 | 7-0 | * +----------------+-----------------+---------------------+------------------------+ * | | FLAG_ADDR_VALID | Error state code in | OS_EXC_CAUSE_HARDFAULT | * | --- | or | table g_uwExcTbl |or OS_EXC_CAUSE_MEMFAULT| * | | 0(invalid) | or HF_DEBUGEVT |or OS_EXC_CAUSE_BUSFAULT| * | | | or HF_VECTBL |or OS_EXC_CAUSE_NMI or | * | | | | OS_EXC_CAUSE_USAGEFAULT| * +----------------+-----------------+---------------------+------------------------+ * b17: FLAG_HWI_ACTIVE * b28: FLAG_NO_FLOAT * NOTE: b17 and b28 will be set later. * * < R1 >: * If the bit16 of R0 is 1, then R1 is the value of BFAR or MMFAR, otherwise the * value in R1 is invalid. * */ osExcDispatch: LDR R2, =OS_NVIC_ACT_BASE MOV R12, #8 /* #8: externel interrupt active check loop counter(#0 - #239) */ _hwiActiveCheck: LDR R3, [R2] /* R3 store the value of externel interrupt active status */ CMP R3, #0 BEQ _hwiActiveCheckNext /** * Exception occured in external interrupt. */ ORR R0, R0, #FLAG_HWI_ACTIVE /* R0[b17] = 1, externel interrupt active valid &&&&&&&&&& */ RBIT R2, R3 /* bit reversal */ CLZ R2, R2 RSB R12, R12, #8 /* R12 = 8 - R12 */ ADD R2, R2, R12, LSL #5 /* R2: external interrupt number as uwPid */ /** * Interrupts and initialization phase always use MSP. */ _ExcInMSP: TST LR, #0x10 /* EXC_RETURN[b4] --- FPU(0) or without FPU(1) */ BNE _NoFloatInMsp /** * Before executing instruction 'B _handleEntry', MSP is as follows. * MSP: * High addr--->| * +--------------------------------------------------------------------------------+--------- * | R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR | * +--------------------------------------------------------------------------------+--------- * R13--->| Initial R13--->|<--- #32 --->|<---SAVED_SP * | (CPU auto saved) | * */ _NoFloatInMsp: ADD R3, R13, #32 /* #32: skip [R0-R3,R12,LR,PC,xPSR] */ PUSH {R3} /* push [SAVED_SP]: MSP+32 = Stack pointer in MSP before entering the exception */ MRS R12, PRIMASK PUSH {R4-R12} /* push R4-R11,PRIMASK to MSP */ ORR R0, R0, #FLAG_NO_FLOAT /* R0[b28] = 1, no FPU &&&&&&&&&& */ B _handleEntry _hwiActiveCheckNext: ADD R2, R2, #4 /* next NVIC ACT ADDR */ SUBS R12, R12, #1 BNE _hwiActiveCheck /** * Not in externel interrupt, check whether it is SysTick or PendSV. */ LDR R2, =OS_NVIC_SHCSRS LDRH R2,[R2] LDR R3,=OS_NVIC_SHCSR_MASK AND R2, R2, R3 CMP R2, #0 BNE _ExcInMSP /* SysTick or PendSV active */ /** * Check whether an exception occurs during the initialization phase. * If g_bTaskScheduled == 0, it is in the initialization phase. */ LDR R2, =g_bTaskScheduled LDR R2, [R2] TST R2, #1 BEQ _ExcInMSP /* initialization phase use MSP */ /** * Before executing _handleEntry, MSP is as follows. * MSP: * High addr--->| * +--------------------------------------------------------------------------------+--------- * | R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR | * +--------------------------------------------------------------------------------+--------- * R13--->| |<--- #32 --->|<---Initial R13 * | (copied from PSP) | * |<---R2(no use) * * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR. */ _NoFloatInPsp: MOV R2, R13 SUB R13, #32 /* #32: MSP reserved, used to store stack frame in PSP */ MRS R3, PSP ADD R12, R3, #32 /* PSP+32 = Stack pointer of the task before entering the exception */ PUSH {R12} /* push task SP to MSP */ MRS R12, PRIMASK PUSH {R4-R12} /* push R4-R11,PRIMASK of the current running task to MSP */ /* Copy stack frame from the stack of the current running task to MSP */ LDMFD R3, {R4-R11} /* restore stack frame of PSP to R4-R11 */ STMFD R2!, {R4-R11} /* save stack frame to MSP */ ORR R0, R0, #FLAG_NO_FLOAT /* R0[b28] = 1, no FPU &&&&&&&&&& */ /** * _handleEntry: Call osExcHandleEntry * param1: R0 --- b28: FLAG_NO_FLOAT. * b17: FLAG_HWI_ACTIVE. * b16: FLAG_ADDR_VALID. * b15-b8: Error state code in table g_uwExcTbl or HF_DEBUGEVT or HF_VECTBL. * b7-b0: OS_EXC_CAUSE_HARDFAULT or OS_EXC_CAUSE_NMI or OS_EXC_CAUSE_MEMFAULT * or OS_EXC_CAUSE_BUSFAULT or OS_EXC_CAUSE_USAGEFAULT. * param2: R1 --- The value of BFAR or MMFAR if R0[b16] = 1, otherwise invalid. * param3: R2 --- external interrupt number(0-239) if R0[b17] = 1, otherwise invalid. * param4: R3 --- Point to the top of the stack(R4 or S16) that the exception stack frame in MSP. */ _handleEntry: MOV R3, R13 CPSID I CPSID F B osExcHandleEntry NOP ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m3/iar/los_dispatch_iar.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2016-2018>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT LOS_IntLock EXPORT LOS_IntUnLock EXPORT LOS_IntRestore EXPORT LOS_StartToRun EXPORT osTaskSchedule EXPORT PendSV_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT g_stLosTask IMPORT g_pfnTskSwitchHook IMPORT g_bTaskScheduled ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt Control and State Register. OS_NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception. OS_NVIC_SYSPRI2 EQU 0xE000ED20 ; System Handler Priority Register 2. OS_NVIC_PENDSV_SYSTICK_PRI EQU 0xFFFF0000 ; SysTick + PendSV priority level (lowest). OS_TASK_STATUS_RUNNING EQU 0x0010 ; Task Status Flag (RUNNING). ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** SECTION .text:CODE(2) THUMB REQUIRE8 PRESERVE8 ;**************************************************************************************** ; Function: ; VOID LOS_StartToRun(VOID); ; Description: ; Start the first task, which is the highest priority task in the priority queue. ; Other tasks are started by task scheduling. ;**************************************************************************************** LOS_StartToRun CPSID I ;/** ; * Set PendSV and SysTick prority to the lowest. ; * read ---> modify ---> write-back. ; */ LDR R0, =OS_NVIC_SYSPRI2 LDR R1, =OS_NVIC_PENDSV_SYSTICK_PRI LDR R2, [R0] ORR R1, R1, R2 STR R1, [R0] ;/** ; * Set g_bTaskScheduled = 1. ; */ LDR R0, =g_bTaskScheduled MOV R1, #1 STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask = g_stLosTask.pstNewTask. ; */ LDR R0, =g_stLosTask LDR R1, [R0, #4] STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask->usTaskStatus |= OS_TASK_STATUS_RUNNING. ; */ LDR R1, [R0] LDRH R2, [R1, #4] MOV R3, #OS_TASK_STATUS_RUNNING ORR R2, R2, R3 STRH R2, [R1, #4] ;/** ; * Restore the default stack frame(R0-R3,R12,LR,PC,xPSR) of g_stLosTask.pstRunTask to R0-R7. ; * Return by setting the CONTROL register. ; * ; * The initial stack of the current running task is as follows: ; * ; * POP: Restore the context of the current running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+-----------------------+--------------------------------------+ ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstRunTask->pStackPointer ; * |<--- skip --->|<--- copy to R0-R7 --->| ; * R12 to PSP--->| ; * Stack pointer after LOS_StartToRun--->| ; */ LDR R12, [R1] ADD R12, R12, #36 ; skip R4-R11, PRIMASK. LDMFD R12!, {R0-R7} ;/** ; * Set the stack pointer of g_stLosTask.pstRunTask to PSP. ; */ MSR PSP, R12 ;/** ; * Set the CONTROL register, after schedule start, privilege level and stack = PSP. ; */ MOV R12, #2 MSR CONTROL, R12 ;/** ; * Enable interrupt. (The default PRIMASK value is 0, so enable directly) ; */ MOV LR, R5 CPSIE I ;/** ; * Jump directly to the default PC of g_stLosTask.pstRunTask, the field information ; * of the main function will be destroyed and will never be returned. ; */ BX R6 ;**************************************************************************************** ; Function: ; UINTPTR LOS_IntLock(VOID); ; Description: ; Disable all interrupts except Reset,NMI and HardFault. ; The value of currnet interruption state will be returned to the caller to save. ; ; Function: ; VOID LOS_IntRestore(UINTPTR uvIntSave); ; Description: ; Restore the locked interruption of LOS_IntLock. ; The caller must pass in the value of interruption state previously saved. ;**************************************************************************************** LOS_IntLock MRS R0, PRIMASK CPSID I BX LR LOS_IntUnLock MRS R0, PRIMASK CPSIE I BX LR LOS_IntRestore MSR PRIMASK, R0 BX LR ;**************************************************************************************** ; Function: ; VOID osTaskSchedule(VOID); ; Description: ; Start the task swtich process by software trigger PendSV interrupt. ;**************************************************************************************** osTaskSchedule LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] BX LR ;**************************************************************************************** ; Function: ; VOID PendSV_Handler(VOID); ; Description: ; PendSV interrupt handler, switch the context of the task. ; First: Save the context of the current running task(g_stLosTask.pstRunTask) ; to its own stack. ; Second: Restore the context of the next running task(g_stLosTask.pstNewTask) ; from its own stack. ;**************************************************************************************** PendSV_Handler ;/** ; * R12: Save the interruption state of the current running task. ; * Disable all interrupts except Reset,NMI and HardFault ; */ MRS R12, PRIMASK CPSID I ;/** ; * Call task switch hook. ; */ LDR R2, =g_pfnTskSwitchHook LDR R2, [R2] CBZ R2, TaskSwitch PUSH {R12, LR} BLX R2 POP {R12, LR} TaskSwitch ;/** ; * R0 = now stack pointer of the current running task. ; */ MRS R0, PSP ;/** ; * Save the stack frame(R4-R11) of the current running task. ; * R12 save the PRIMASK value of the current running task. ; * NOTE: Before entering the exception handler function, these registers ; * (xPSR,PC,LR,R12,R3-R0) have been automatically ; * saved by the CPU in the stack of the current running task. ; * ; * The stack of the current running task is as follows: ; * ; * |<=== PUSH: Save the context of the current running task ; * | High addr--->| ; * ----------+-----------------------+--------------------------------------+----- ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+----- ; * Stack pointer before entering exception--->| ; * |<--- cpu auto saved --->| ; * |<---PSP to R0 ; * |<---Top of the stack, save to g_stLosTask.pstRunTask->pStackPointer ; */ STMFD R0!, {R4-R12} ; save the core registers and PRIMASK. ;/** ; * R5,R8. ; */ LDR R5, =g_stLosTask MOV R8, #OS_TASK_STATUS_RUNNING ;/** ; * Save the stack pointer of the current running task to TCB. ; * (g_stLosTask.pstRunTask->pStackPointer = R0) ; */ LDR R6, [R5] STR R0, [R6] ;/** ; * Clear the RUNNING state of the current running task. ; * (g_stLosTask.pstRunTask->usTaskStatus &= ~OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R6, #4] BIC R7, R7, R8 STRH R7, [R6, #4] ;/** ; * Switch the current running task to the next running task. ; * (g_stLosTask.pstRunTask = g_stLosTask.pstNewTask) ; */ LDR R0, [R5, #4] STR R0, [R5] ;/** ; * Set the RUNNING state of the next running task. ; * (g_stLosTask.pstNewTask->usTaskStatus |= OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R0, #4] ORR R7, R7, R8 STRH R7, [R0, #4] ;/** ; * Restore the stack pointer of the next running task from TCB. ; * (R1 = g_stLosTask.pstNewTask->pStackPointer) ; */ LDR R1, [R0] ;/** ; * Restore the stack frame(R4-R11) of the next running task. ; * R12 restore the PRIMASK value of the next running task. ; * NOTE: After exiting the exception handler function, these registers ; * (PC,xPSR,R0-R3,R12,LR) will be automatically ; * restored by the CPU from the stack of the next running task. ; * ; * 1. The stack of the next running task is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * ----------+-----------------------+--------------------------------------+----- ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+----- ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; * ; * 2. If the next running task is run for the first time, the stack is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+-----------------------+--------------------------------------+ ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; */ LDMFD R1!, {R4-R12} ; restore the core registers and PRIMASK. ;/** ; * Set the stack pointer of the next running task to PSP. ; */ MSR PSP, R1 ;/** ; * Restore the interruption state of the next running task. ; */ MSR PRIMASK, R12 BX LR END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m3/keil/los_dispatch_keil.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2016-2018>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT LOS_IntLock EXPORT LOS_IntUnLock EXPORT LOS_IntRestore EXPORT LOS_StartToRun EXPORT osTaskSchedule EXPORT PendSV_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT g_stLosTask IMPORT g_pfnTskSwitchHook IMPORT g_bTaskScheduled ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt Control and State Register. OS_NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception. OS_NVIC_SYSPRI2 EQU 0xE000ED20 ; System Handler Priority Register 2. OS_NVIC_PENDSV_SYSTICK_PRI EQU 0xFFFF0000 ; SysTick + PendSV priority level (lowest). OS_TASK_STATUS_RUNNING EQU 0x0010 ; Task Status Flag (RUNNING). ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** AREA |.text|, CODE, READONLY THUMB REQUIRE8 PRESERVE8 ;**************************************************************************************** ; Function: ; VOID LOS_StartToRun(VOID); ; Description: ; Start the first task, which is the highest priority task in the priority queue. ; Other tasks are started by task scheduling. ;**************************************************************************************** LOS_StartToRun CPSID I ;/** ; * Set PendSV and SysTick prority to the lowest. ; * read ---> modify ---> write-back. ; */ LDR R0, =OS_NVIC_SYSPRI2 LDR R1, =OS_NVIC_PENDSV_SYSTICK_PRI LDR R2, [R0] ORR R1, R1, R2 STR R1, [R0] ;/** ; * Set g_bTaskScheduled = 1. ; */ LDR R0, =g_bTaskScheduled MOV R1, #1 STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask = g_stLosTask.pstNewTask. ; */ LDR R0, =g_stLosTask LDR R1, [R0, #4] STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask->usTaskStatus |= OS_TASK_STATUS_RUNNING. ; */ LDR R1, [R0] LDRH R2, [R1, #4] MOV R3, #OS_TASK_STATUS_RUNNING ORR R2, R2, R3 STRH R2, [R1, #4] ;/** ; * Restore the default stack frame(R0-R3,R12,LR,PC,xPSR) of g_stLosTask.pstRunTask to R0-R7. ; * Return by setting the CONTROL register. ; * ; * The initial stack of the current running task is as follows: ; * ; * POP: Restore the context of the current running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+-----------------------+--------------------------------------+ ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstRunTask->pStackPointer ; * |<--- skip --->|<--- copy to R0-R7 --->| ; * R12 to PSP--->| ; * Stack pointer after LOS_StartToRun--->| ; */ LDR R12, [R1] ADD R12, R12, #36 ; skip R4-R11, PRIMASK. LDMFD R12!, {R0-R7} ;/** ; * Set the stack pointer of g_stLosTask.pstRunTask to PSP. ; */ MSR PSP, R12 ;/** ; * Set the CONTROL register, after schedule start, privilege level and stack = PSP. ; */ MOV R12, #2 MSR CONTROL, R12 ;/** ; * Enable interrupt. (The default PRIMASK value is 0, so enable directly) ; */ MOV LR, R5 CPSIE I ;/** ; * Jump directly to the default PC of g_stLosTask.pstRunTask, the field information ; * of the main function will be destroyed and will never be returned. ; */ BX R6 ;**************************************************************************************** ; Function: ; UINTPTR LOS_IntLock(VOID); ; Description: ; Disable all interrupts except Reset,NMI and HardFault. ; The value of currnet interruption state will be returned to the caller to save. ; ; Function: ; VOID LOS_IntRestore(UINTPTR uvIntSave); ; Description: ; Restore the locked interruption of LOS_IntLock. ; The caller must pass in the value of interruption state previously saved. ;**************************************************************************************** LOS_IntLock MRS R0, PRIMASK CPSID I BX LR LOS_IntUnLock MRS R0, PRIMASK CPSIE I BX LR LOS_IntRestore MSR PRIMASK, R0 BX LR ;**************************************************************************************** ; Function: ; VOID osTaskSchedule(VOID); ; Description: ; Start the task swtich process by software trigger PendSV interrupt. ;**************************************************************************************** osTaskSchedule LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] BX LR ;**************************************************************************************** ; Function: ; VOID PendSV_Handler(VOID); ; Description: ; PendSV interrupt handler, switch the context of the task. ; First: Save the context of the current running task(g_stLosTask.pstRunTask) ; to its own stack. ; Second: Restore the context of the next running task(g_stLosTask.pstNewTask) ; from its own stack. ;**************************************************************************************** PendSV_Handler ;/** ; * R12: Save the interruption state of the current running task. ; * Disable all interrupts except Reset,NMI and HardFault ; */ MRS R12, PRIMASK CPSID I ;/** ; * Call task switch hook. ; */ LDR R2, =g_pfnTskSwitchHook LDR R2, [R2] CBZ R2, TaskSwitch PUSH {R12, LR} BLX R2 POP {R12, LR} TaskSwitch ;/** ; * R0 = now stack pointer of the current running task. ; */ MRS R0, PSP ;/** ; * Save the stack frame(R4-R11) of the current running task. ; * R12 save the PRIMASK value of the current running task. ; * NOTE: Before entering the exception handler function, these registers ; * (xPSR,PC,LR,R12,R3-R0) have been automatically ; * saved by the CPU in the stack of the current running task. ; * ; * The stack of the current running task is as follows: ; * ; * |<=== PUSH: Save the context of the current running task ; * | High addr--->| ; * ----------+-----------------------+--------------------------------------+----- ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+----- ; * Stack pointer before entering exception--->| ; * |<--- cpu auto saved --->| ; * |<---PSP to R0 ; * |<---Top of the stack, save to g_stLosTask.pstRunTask->pStackPointer ; */ STMFD R0!, {R4-R12} ; save the core registers and PRIMASK. ;/** ; * R5,R8. ; */ LDR R5, =g_stLosTask MOV R8, #OS_TASK_STATUS_RUNNING ;/** ; * Save the stack pointer of the current running task to TCB. ; * (g_stLosTask.pstRunTask->pStackPointer = R0) ; */ LDR R6, [R5] STR R0, [R6] ;/** ; * Clear the RUNNING state of the current running task. ; * (g_stLosTask.pstRunTask->usTaskStatus &= ~OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R6, #4] BIC R7, R7, R8 STRH R7, [R6, #4] ;/** ; * Switch the current running task to the next running task. ; * (g_stLosTask.pstRunTask = g_stLosTask.pstNewTask) ; */ LDR R0, [R5, #4] STR R0, [R5] ;/** ; * Set the RUNNING state of the next running task. ; * (g_stLosTask.pstNewTask->usTaskStatus |= OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R0, #4] ORR R7, R7, R8 STRH R7, [R0, #4] ;/** ; * Restore the stack pointer of the next running task from TCB. ; * (R1 = g_stLosTask.pstNewTask->pStackPointer) ; */ LDR R1, [R0] ;/** ; * Restore the stack frame(R4-R11) of the next running task. ; * R12 restore the PRIMASK value of the next running task. ; * NOTE: After exiting the exception handler function, these registers ; * (PC,xPSR,R0-R3,R12,LR) will be automatically ; * restored by the CPU from the stack of the next running task. ; * ; * 1. The stack of the next running task is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * ----------+-----------------------+--------------------------------------+----- ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+----- ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; * ; * 2. If the next running task is run for the first time, the stack is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+-----------------------+--------------------------------------+ ; * | R4-R11, PRIMASK | R0-R3, R12, LR, PC, xPSR | ; * ----------+-----------------------+--------------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; */ LDMFD R1!, {R4-R12} ; restore the core registers and PRIMASK. ;/** ; * Set the stack pointer of the next running task to PSP. ; */ MSR PSP, R1 ;/** ; * Restore the interruption state of the next running task. ; */ MSR PRIMASK, R12 BX LR ALIGN END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m3/keil/los_hw_exc_keil.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2013-2015>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** PRESERVE8 AREA |.text|, CODE, READONLY THUMB ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT NMI_Handler EXPORT HardFault_Handler EXPORT MemManage_Handler EXPORT BusFault_Handler EXPORT UsageFault_Handler EXPORT SVC_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT osExcHandleEntry IMPORT g_uwExcTbl IMPORT g_bTaskScheduled ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_EXC_CAUSE_NMI EQU 18 OS_EXC_CAUSE_HARDFAULT EQU 19 OS_EXC_CAUSE_MEMFAULT EQU 20 OS_EXC_CAUSE_BUSFAULT EQU 21 OS_EXC_CAUSE_USAGEFAULT EQU 22 OS_EXC_CAUSE_SVC EQU 23 HF_DEBUGEVT EQU 24 HF_VECTBL EQU 25 FLAG_ADDR_VALID EQU 0x10000 ; bit 16 FLAG_HWI_ACTIVE EQU 0x20000 ; bit 17 FLAG_NO_FLOAT EQU 0x10000000 ; bit 28 OS_NVIC_CFSR EQU 0xE000ED28 ; include BusFault/MemFault/UsageFault State Regeister OS_NVIC_HFSR EQU 0xE000ED2C ; HardFault State Regeister OS_NVIC_BFAR EQU 0xE000ED38 OS_NVIC_MMFAR EQU 0xE000ED34 OS_NVIC_ACT_BASE EQU 0xE000E300 OS_NVIC_SHCSRS EQU 0xE000ED24 OS_NVIC_SHCSR_MASK EQU 0xC00 ; SYSTICKACT and PENDSVACT ;**************************************************************************************** ; Function: ; VOID NMI_Handler(VOID); ; Description: ; NMI Handler. ;**************************************************************************************** NMI_Handler ;/** ; * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +------------------------------------------------------+------------------------+ ; * | 31-8 | 7-0 | ; * +------------------------------------------------------+------------------------+ ; * | --- | OS_EXC_CAUSE_NMI | ; * +------------------------------------------------------+------------------------+ ; * < R1 >: invalid ; */ MOV R0, #OS_EXC_CAUSE_NMI MOV R1, #0 B osExcDispatch ;**************************************************************************************** ; Function: ; VOID HardFault_Handler(VOID); ; Description: ; HardFault Handler. ;**************************************************************************************** HardFault_Handler ;/** ; * Check HardFault state register. ; * ; * HFSR: ; * +----------+--------+--------+--------+-------+ ; * | 31 | 30 | 29 - 2 | 1 | 0 | ; * +----------+--------+--------+--------+-------+ ; * | DEBUGEVT | FORCED | -- | VECTBL | -- | ; * +----------+--------+--------+--------+-------+ ; */ MOV R0, #OS_EXC_CAUSE_HARDFAULT LDR R2, =OS_NVIC_HFSR LDR R2, [R2] ;/** ; * Check whether HardFault are triggered by debugging events. ; * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +----------------------------------------+-------------+------------------------+ ; * | 31-16 | 15-8 | 7-0 | ; * +----------------------------------------+-------------+------------------------+ ; * | --- | HF_DEBUGEVT | OS_EXC_CAUSE_HARDFAULT | ; * +----------------------------------------+-------------+------------------------+ ; * < R1 >: invalid ; */ MOV R1, #HF_DEBUGEVT ORR R0, R0, R1, LSL #0x8 TST R2, #0x80000000 BNE osExcDispatch ; DEBUGEVT ;/** ; * Check whether HardFault is caused by the failure of the fetch vector. ; * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +----------------------------------------+-------------+------------------------+ ; * | 31-16 | 15-8 | 7-0 | ; * +----------------------------------------+-------------+------------------------+ ; * | --- | HF_VECTBL | OS_EXC_CAUSE_HARDFAULT | ; * +----------------------------------------+-------------+------------------------+ ; * < R1 >: invalid ; */ AND R0, R0, #0x000000FF MOV R1, #HF_VECTBL ORR R0, R0, R1, LSL #0x8 TST R2, #0x00000002 BNE osExcDispatch ; VECTBL ;/** ; * If it`s not DEBUGEVT and VECTBL, that is FORCED, then read the CFSR register to ; * check BusFault, MemFault and UsageFault. ; * R0: OS_EXC_CAUSE_HARDFAULT ; * ; * CFSR: ; * +----------------+--------+--------+ ; * | 31-16 | 15-8 | 7-0 | ; * +----------------+--------+--------+ ; * | UFSR | BFSR | MFSR | ; * +----------------+--------+--------+ ; */ AND R0, R0, #0x000000FF LDR R2, =OS_NVIC_CFSR LDR R2, [R2] TST R2, #0x8000 ; BFSR->BFARVALID BNE _HFBusFault ; BusFault TST R2, #0x80 ; MFSR->MMARVALID BNE _HFMemFault ; MemFault ;/** ; * BFARVALID and MMARVALID flag both invalid. ; * R12: 0 --- The error address is invalid. ; */ MOV R12, #0 B osHFExcCommonBMU ;/** ; * BFARVALID flag valid, read BFAR register. ; * R1 : BFAR value --- The address value of a bus error. ; * R12: The error address is valid. ; */ _HFBusFault LDR R1, =OS_NVIC_BFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID B osHFExcCommonBMU ;/** ; * MMARVALID flag valid, read MMFAR register. ; * R1 : MMFAR value --- The address value of memory management error. ; * R12: The error address is valid. ; */ _HFMemFault LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID ;/** ; * osHFExcCommonBMU: --- Get specific error status from table g_uwExcTbl, stored in R0. ; * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +-------------------+-----------------+------------------+------------------------+ ; * | 31-17 | 16 | 15-8 | 7-0 | ; * +-------------------+-----------------+------------------+------------------------+ ; * | --- | FLAG_ADDR_VALID | Error state code | OS_EXC_CAUSE_HARDFAULT | ; * | | or | in | | ; * | | 0(invalid) | table g_uwExcTbl | | ; * +-------------------+-----------------+------------------+------------------------+ ; * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, ; * else invalid. ; */ osHFExcCommonBMU CLZ R2, R2 LDR R3, =g_uwExcTbl ADD R3, R3, R2 LDRB R2, [R3] ORR R0, R0, R2, LSL #0x8 ORR R0, R0, R12 B osExcDispatch ;**************************************************************************************** ; Function: ; VOID SVC_Handler(VOID); ; Description: ; SVC Handler. ;**************************************************************************************** SVC_Handler TST LR, #0x4 ; EXC_RETURN[b2] --- PSP or MSP ITE EQ MRSEQ R0, MSP MRSNE R0, PSP LDR R1, [R0, #24] ; The PC value in the stack frame LDRB R0, [R1, #-2] ; R0: The number of SVC (0 - 255) MOV R1, #0 ;B osExcDispatch _SvcLoop B _SvcLoop ;**************************************************************************************** ; Function: ; VOID BusFault_Handler(VOID); ; Description: ; BusFault Handler. ;**************************************************************************************** BusFault_Handler LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_BUSFAULT TST R0, #0x8000 ; BFSR->BFARVALID BEQ _ExcBusNoADDR LDR R1, =OS_NVIC_BFAR LDR R1, [R1] ; R1: The value of BFAR MOV R12, #FLAG_ADDR_VALID ; R12: BusFault addr valid AND R0, R0, #0x3F00 ; R0: Reserved the b13-b8 of the BFSR B osExcCommonBMU _ExcBusNoADDR MOV R12, #0 ; R12: BusFault addr invalid AND R0, R0, #0x3F00 ; R0: Reserved the b13-b8 of the BFSR B osExcCommonBMU ;**************************************************************************************** ; Function: ; VOID MemManage_Handler(VOID); ; Description: ; MemManage Handler. ;**************************************************************************************** MemManage_Handler LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_MEMFAULT TST R0, #0x80 ; MFSR->MMARVALID BEQ _ExcMemNoADDR LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] ; R1: The value of MMFAR MOV R12, #FLAG_ADDR_VALID ; R12: MemFault addr valid AND R0, R0, #0x3B ; R0: Reserved the b5-b0 of the MFSR B osExcCommonBMU _ExcMemNoADDR MOV R12, #0 ; R12: MemFault addr invalid AND R0, R0, #0x3B ; R0: Reserved the b5-b0 of the MFSR B osExcCommonBMU ;**************************************************************************************** ; Function: ; VOID UsageFault_Handler(VOID); ; Description: ; UsageFault Handler. ;**************************************************************************************** UsageFault_Handler LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_USAGEFAULT MOV R1, #0x030F LSL R1, R1, #16 AND R0, R0, R1 ; R0: reserved UFSR MOV R12, #0 ; R12: Fault addr invalid ;/** ; * osExcCommonBMU: BusFault_Handler,MemManage_Handler and UsageFault_Handler share. ; * Get specific error status from table g_uwExcTbl, stored in R0. ; * Before executing osExcDispatch, the value of R0 is as follows. ; * < R0 >: ; * +-------------------+-----------------+------------------+------------------------+ ; * | 31-17 | 16 | 15-8 | 7-0 | ; * +-------------------+-----------------+------------------+------------------------+ ; * | --- | FLAG_ADDR_VALID | Error state code |OS_EXC_CAUSE_BUSFAULT or| ; * | | or | in |OS_EXC_CAUSE_MEMFAULT or| ; * | | 0(invalid) | table g_uwExcTbl |OS_EXC_CAUSE_USAGEFAULT | ; * +-------------------+-----------------+------------------+------------------------+ ; * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, ; * else invalid. ; */ osExcCommonBMU CLZ R0, R0 LDR R3, =g_uwExcTbl ADD R3, R3, R0 LDRB R0, [R3] LSL R0, R0, #0x8 ORR R0, R0, R2 ORR R0, R0, R12 ;MRS R2,PSP ;PSP-->>37D8 ;**************************************************************************************** ; osExcDispatch: NMI_Handler, HardFault_Handler, SVC_Handler, BusFault_Handler, MemManage_Handler, ; UsageFault_Handler sharing. ;**************************************************************************************** ;/** ; * When executing osExcDispatch, R0, R1 will be used. ; * The possible values of R0 and R1 are as follows. ; * ; * < R0 >: ; * +----------------+-----------------+---------------------+------------------------+ ; * | 31-17 | 16 | 15-8 | 7-0 | ; * +----------------+-----------------+---------------------+------------------------+ ; * | | FLAG_ADDR_VALID | Error state code in | OS_EXC_CAUSE_HARDFAULT | ; * | --- | or | table g_uwExcTbl |or OS_EXC_CAUSE_MEMFAULT| ; * | | 0(invalid) | or HF_DEBUGEVT |or OS_EXC_CAUSE_BUSFAULT| ; * | | | or HF_VECTBL |or OS_EXC_CAUSE_NMI or | ; * | | | | OS_EXC_CAUSE_USAGEFAULT| ; * +----------------+-----------------+---------------------+------------------------+ ; * b17: FLAG_HWI_ACTIVE ; * b28: FLAG_NO_FLOAT ; * NOTE: b17 and b28 will be set later. ; * ; * < R1 >: ; * If the bit16 of R0 is 1, then R1 is the value of BFAR or MMFAR, otherwise the ; * value in R1 is invalid. ; * ; */ osExcDispatch LDR R2, =OS_NVIC_ACT_BASE MOV R12, #8 ; #8: externel interrupt active check loop counter(#0 - #239) _hwiActiveCheck LDR R3, [R2] ; R3 store the value of externel interrupt active status CMP R3, #0 BEQ _hwiActiveCheckNext ;/** ; * Exception occured in external interrupt. ; */ ORR R0, R0, #FLAG_HWI_ACTIVE ; R0[b17] = 1, externel interrupt active valid &&&&&&&&&& RBIT R2, R3 ; bit reversal CLZ R2, R2 RSB R12, R12, #8 ; R12 = 8 - R12 ADD R2, R2, R12, LSL #5 ; R2: external interrupt number as uwPid ;/** ; * Interrupts and initialization phase always use MSP. ; */ _ExcInMSP ;TST LR, #0x10 ; EXC_RETURN[b4] --- FPU(0) or without FPU(1) ;BNE _NoFloatInMsp ;/** ; * Before executing instruction 'B _handleEntry', MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR | ; * +--------------------------------------------------------------------------------+--------- ; * R13--->| Initial R13--->|<--- #32 --->|<---SAVED_SP ; * | (CPU auto saved) | ; * ; */ _NoFloatInMsp ADD R3, R13, #32 ; #32: skip [R0-R3,R12,LR,PC,xPSR] PUSH {R3} ; push [SAVED_SP]: MSP+32 = Stack pointer in MSP before entering the exception MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK to MSP ORR R0, R0, #FLAG_NO_FLOAT ; R0[b28] = 1, no FPU &&&&&&&&&& B _handleEntry _hwiActiveCheckNext ADD R2, R2, #4 ; next NVIC ACT ADDR SUBS R12, R12, #1 BNE _hwiActiveCheck ;/** ; * Not in externel interrupt, check whether it is SysTick or PendSV. ; */ LDR R2, =OS_NVIC_SHCSRS LDRH R2,[R2] LDR R3,=OS_NVIC_SHCSR_MASK AND R2, R2, R3 CMP R2, #0 BNE _ExcInMSP ; SysTick or PendSV active ;/** ; * Check whether an exception occurs during the initialization phase. ; * If g_bTaskScheduled == 0, it is in the initialization phase. ; */ LDR R2, =g_bTaskScheduled LDR R2, [R2] TST R2, #1 BEQ _ExcInMSP ; initialization phase use MSP ;/** ; * Before executing _handleEntry, MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR | ; * +--------------------------------------------------------------------------------+--------- ; * R13--->| |<--- #32 --->|<---Initial R13 ; * | (copied from PSP) | ; * |<---R2(no use) ; * ; * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR. ; */ _NoFloatInPsp MOV R2, R13 SUB R13, #32 ; #32: MSP reserved, used to store stack frame in PSP MRS R3, PSP ADD R12, R3, #32 ; PSP+32 = Stack pointer of the task before entering the exception PUSH {R12} ; push task SP to MSP MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK of the current running task to MSP ;/* Copy stack frame from the stack of the current running task to MSP */ LDMFD R3, {R4-R11} ; restore stack frame of PSP to R4-R11 STMFD R2!, {R4-R11} ; save stack frame to MSP ORR R0, R0, #FLAG_NO_FLOAT ; R0[b28] = 1, no FPU &&&&&&&&&& ;/** ; * _handleEntry: Call osExcHandleEntry ; * param1: R0 --- b28: FLAG_NO_FLOAT. ; * b17: FLAG_HWI_ACTIVE. ; * b16: FLAG_ADDR_VALID. ; * b15-b8: Error state code in table g_uwExcTbl or HF_DEBUGEVT or HF_VECTBL. ; * b7-b0: OS_EXC_CAUSE_HARDFAULT or OS_EXC_CAUSE_NMI or OS_EXC_CAUSE_MEMFAULT ; * or OS_EXC_CAUSE_BUSFAULT or OS_EXC_CAUSE_USAGEFAULT. ; * param2: R1 --- The value of BFAR or MMFAR if R0[b16] = 1, otherwise invalid. ; * param3: R2 --- external interrupt number(0-239) if R0[b17] = 1, otherwise invalid. ; * param4: R3 --- Point to the top of the stack(R4 or S16) that the exception stack frame in MSP. ; */ _handleEntry MOV R3, R13 CPSID I CPSID F B osExcHandleEntry NOP ALIGN END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m3/los_exc.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "los_exc.inc" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cpluscplus */ #endif /* __cpluscplus */ #if (LOSCFG_PLATFORM_EXC == YES) UINT32 g_uwCurNestCount = 0; EXC_INFO_S m_stExcInfo; /* * CFSR register, include UFSR,BFSR and MFSR. * * +----------------------------------------------------------------------------------+ * | UFSR | * |-----------+-----------+-----------+-------+------+-------+----------+------------| * | 31 - 26 | 25 | 24 | 23-20 | 19 | 18 | 17 | 16 | * |-----------+-----------+-----------+-------+------+-------+----------+------------| * | --- | DIVBYZERO | UNALIGNED | --- | NOCP | INVPC | INVSTATE | UNDEFINSTR | * +----------------------------------------------------------------------------------+ * * +----------------------------------------------------------------------------------+ * | BFSR | * |-----------+-----+--------+--------+----------+-------------+-----------+---------| * | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | * |-----------+-----+--------+--------+----------+-------------+-----------+---------| * | BFARVALID | --- | LSPERR | STKERR | UNSTKERR | IMPRECISERR | PRECISERR | IBUSERR | * +----------------------------------------------------------------------------------+ * * +----------------------------------------------------------------------------------+ * | MFSR | * |-----------+-------+---------+---------+-----------+-------+----------+-----------| * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | * |-----------+-------+---------+---------+-----------+-------+----------+-----------| * | MMARVALID | --- | MLSPERR | MSTKERR | MUNSTKERR | --- | DACCVIOL | ICACCVIOL | * +----------------------------------------------------------------------------------+ */ UINT8 g_uwExcTbl[32] = { 0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED, 0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR, 0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR, 0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL }; #if (LOSCFG_SAVE_EXC_INFO == YES) VOID *m_puwExcContent; UINT32 g_uwArraySize = 0; EXC_INFO_ARRAY_S m_stExcArray[OS_EXC_TYPE_MAX - 1]; static VOID osExcSave2DDR(VOID); #endif extern VOID LOS_Reboot(VOID); /***************************************************************************** Function : osExcInfoDisplay Description : EXC info display Input : pstExc --- Pointer to the EXC data Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osExcInfoDisplay(EXC_INFO_S *pstExc) { printf("\n\n"); PRINT_ERR("Phase = 0x%8x\n", pstExc->usPhase); PRINT_ERR("Type = 0x%8x\n", pstExc->usType); PRINT_ERR("FaultAddr = 0x%8x\n", pstExc->uwFaultAddr); PRINT_ERR("ThrdPid = 0x%8x\n", pstExc->uwThrdPid); PRINT_ERR("R0 = 0x%8x\n", pstExc->pstContext->uwR0); PRINT_ERR("R1 = 0x%8x\n", pstExc->pstContext->uwR1); PRINT_ERR("R2 = 0x%8x\n", pstExc->pstContext->uwR2); PRINT_ERR("R3 = 0x%8x\n", pstExc->pstContext->uwR3); PRINT_ERR("R4 = 0x%8x\n", pstExc->pstContext->uwR4); PRINT_ERR("R5 = 0x%8x\n", pstExc->pstContext->uwR5); PRINT_ERR("R6 = 0x%8x\n", pstExc->pstContext->uwR6); PRINT_ERR("R7 = 0x%8x\n", pstExc->pstContext->uwR7); PRINT_ERR("R8 = 0x%8x\n", pstExc->pstContext->uwR8); PRINT_ERR("R9 = 0x%8x\n", pstExc->pstContext->uwR9); PRINT_ERR("R10 = 0x%8x\n", pstExc->pstContext->uwR10); PRINT_ERR("R11 = 0x%8x\n", pstExc->pstContext->uwR11); PRINT_ERR("R12 = 0x%8x\n", pstExc->pstContext->uwR12); PRINT_ERR("PriMask = 0x%8x\n", pstExc->pstContext->uwPriMask); PRINT_ERR("SP = 0x%8x\n", pstExc->pstContext->uwSP); PRINT_ERR("LR = 0x%8x\n", pstExc->pstContext->uwLR); PRINT_ERR("PC = 0x%8x\n", pstExc->pstContext->uwPC); PRINT_ERR("xPSR = 0x%8x\n", pstExc->pstContext->uwxPSR); PRINT_ERR("\nplease use the addr2line tool to analyze the call stack on PC:\n"); PRINT_ERR("addr2line -e (xxx.axf/xxx.elf/xxx.out) -a -f "); for (UINT32 i = 0; i < pstExc->uwCallStackDepth; i++) { PRINT_ERR("%#x ", pstExc->uwCallStack[i]); } return; } /***************************************************************************** Function : osExcCallStackAnalysis Description : Call stack analysis Input : pstExc --- point to exception info Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osExcCallStackAnalysis(EXC_INFO_S *pstExc) { UINT32 uwSP; UINT32 uwLR; UINT32 uwPC; UINT32 uwStackStartAddr; UINT32 uwStackSize; UINT32 uwDepth = 0; BOOL bFirstLrValid = FALSE; uwSP = pstExc->pstContext->uwSP; /* sp pointer before entering exception */ /* * save first and second depth * first: PC before entering exception * second: (LR - 4) before entering exception * NOTE: If an exception occurs in the interrupt, LR may be EXC_RETURN, so we must make sure * that LR is valid, exclude EXC_RETURN. */ pstExc->uwCallStack[uwDepth++] = pstExc->pstContext->uwPC; if ((pstExc->pstContext->uwLR >= LOSCFG_EXC_CODE_START_ADDR) && \ (pstExc->pstContext->uwLR <= LOSCFG_EXC_CODE_START_ADDR + LOSCFG_EXC_CODE_SIZE)) { pstExc->uwCallStack[uwDepth++] = pstExc->pstContext->uwLR - sizeof(VOID *); /* lr = pc + 4 */ bFirstLrValid = TRUE; } /* * get the start address and size of the stack before entering the exception */ if (pstExc->usPhase == OS_EXC_IN_TASK) /* task use PSP */ { uwStackStartAddr = g_stLosTask.pstRunTask->uwTopOfStack; uwStackSize = g_stLosTask.pstRunTask->uwStackSize; } else /* init and interrupt use MSP */ { uwStackStartAddr = LOSCFG_EXC_MSP_START_ADDR; uwStackSize = LOSCFG_EXC_MSP_SIZE; } /* * check stack overflow, if so, compensate for overflow, readjust stack start address and size. */ if (uwSP < uwStackStartAddr) /* stack top overflow */ { if (pstExc->usPhase == OS_EXC_IN_TASK) { PRINT_ERR("task %s stack top overflow\n", g_stLosTask.pstRunTask->pcTaskName); } else { PRINT_ERR("MSP top overflow\n"); } uwStackSize += (uwStackStartAddr - uwSP); /* compensate overflow size */ uwStackStartAddr = uwSP; /* readjust stack start address */ } /* * Traverses the entire stack from the top of the stack to the bottom of the stack, * find all LR. */ for (; uwSP < uwStackStartAddr + uwStackSize; uwSP += sizeof(UINT32*)) { uwLR = *(UINT32 *)uwSP; if (uwLR % 2 == 0) /* Thumb instruction, LR bit0 == 1 */ { continue; } /* * It may be LR, which must be further determined based on the start address * and end address of the code segment. */ if ((uwLR >= LOSCFG_EXC_CODE_START_ADDR) && (uwLR <= LOSCFG_EXC_CODE_START_ADDR + LOSCFG_EXC_CODE_SIZE) \ && (uwDepth < LOSCFG_EXC_CALL_STACK_ANALYSIS_MAX_DEPTH)) { uwPC = uwLR - sizeof(VOID *); /* lr = pc + 4 */ /* the second depth(first LR) has been saved */ if ((uwDepth == 2) && (uwPC == pstExc->uwCallStack[1]) && (bFirstLrValid == TRUE)) { continue; } pstExc->uwCallStack[uwDepth++] = uwPC; } } pstExc->uwCallStackDepth = uwDepth; /* save call stack depth */ return; } /***************************************************************************** Function : osExcHandleEntry Description : EXC handler entry Input : uwExcType --- EXC type : uwFaultAddr --- The address of an accurate address access error : uwPid --- Interrupt number : puwExcBufAddr --- Point to the stack frame without FPU Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osExcHandleEntry(UINT32 uwExcType, UINT32 uwFaultAddr, UINT32 uwPid, EXC_CONTEXT_S *pstExcBufAddr) { /* uwExcType high 16 bits: 0x01 - uwFaultAddr valid, 0x02 - in hwi */ UINT16 usTmpFlag = (uwExcType >> 16) & 0xFFFF; g_uwCurNestCount++; #if (LOSCFG_PLATFORM_HWI == YES) extern UINT32 g_vuwIntCount; g_vuwIntCount++; #endif /* Save interrupt nesting times */ m_stExcInfo.usNestCnt = (UINT16)g_uwCurNestCount; /* uwExcType low 16 bits: exc type */ m_stExcInfo.usType = (UINT16)uwExcType & 0xFFFF; #if (LOSCFG_SAVE_EXC_INFO == YES) /* Initializing a pointer to save an exception context */ m_puwExcContent = (UINT32 *)m_aucTaskArray; #endif /* Save the fault address when an exception occurs if it is valid */ if (usTmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) { m_stExcInfo.uwFaultAddr = uwFaultAddr; } else { m_stExcInfo.uwFaultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR; } /* Save the phase of the exception */ extern BOOL g_bTaskScheduled; if (g_bTaskScheduled && (NULL != g_stLosTask.pstRunTask)) { if (usTmpFlag & OS_EXC_FLAG_IN_HWI) { m_stExcInfo.usPhase = OS_EXC_IN_HWI; m_stExcInfo.uwThrdPid = uwPid; /* interrupt number */ } else { m_stExcInfo.usPhase = OS_EXC_IN_TASK; m_stExcInfo.uwThrdPid = g_stLosTask.pstRunTask->uwTaskID; /* task id */ } } else { m_stExcInfo.usPhase = OS_EXC_IN_INIT; m_stExcInfo.uwThrdPid = 0xffffffff; } /* uwExcType BIT_28: Wether or not to use FPU */ if(uwExcType & OS_EXC_FLAG_NO_FLOAT) { m_stExcInfo.usFpuContext = 0; #if FPU_EXIST /* NOTE: S16-S31, S0-S15,FPSCR,NO_NAME invalid */ m_stExcInfo.pstContext = (EXC_CONTEXT_S *)((UINT8 *)pstExcBufAddr - 64); /* point to S16 */ #else m_stExcInfo.pstContext = pstExcBufAddr; /* point to uwR4 */ #endif } else { m_stExcInfo.usFpuContext = 1; m_stExcInfo.pstContext = pstExcBufAddr; /* point to S16 */ } osExcCallStackAnalysis(&m_stExcInfo); #if (LOSCFG_SAVE_EXC_INFO == YES) osExcSave2DDR(); #endif osExcInfoDisplay(&m_stExcInfo); LOS_Reboot(); } #if (LOSCFG_SAVE_EXC_INFO == YES) /***************************************************************************** Function : osExcSaveIntStatus Description : Save NVIC register group Input : None Output : None Return : None *****************************************************************************/ static VOID osExcSaveIntStatus(VOID) { /* Save exc type */ *((UINT32 *)m_puwExcContent) = OS_EXC_TYPE_NVIC; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save total size of NVIC */ *((UINT32 *)m_puwExcContent) = 0x164; // = OS_NVIC_INT_ENABLE_SIZE + OS_NVIC_INT_PEND_SIZE + OS_NVIC_INT_ACT_SIZE + OS_NVIC_INT_PRI_SIZE + 12 + 4 + 4 m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save interrupt enable register group (start addr: 0xE000E100, size: 32bytes, CMSIS-Core: NVIC->ISER[0 - 7]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_SETENA_BASE, OS_NVIC_INT_ENABLE_SIZE); m_puwExcContent =(UINT8 *)m_puwExcContent + OS_NVIC_INT_ENABLE_SIZE; /* Save interrupt pend register group (start addr: 0xE000E200, size: 32bytes, CMSIS-Core: NVIC->ISPR[0 - 7]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_SETPEND_BASE, OS_NVIC_INT_PEND_SIZE); m_puwExcContent = (UINT8 *)m_puwExcContent + OS_NVIC_INT_PEND_SIZE; /* Save interrupt active status register group (start addr: 0xE000E300, size: 32bytes, CMSIS-Core: NVIC->IABR[0 - 7]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_INT_ACT_BASE, OS_NVIC_INT_ACT_SIZE); m_puwExcContent = (UINT8 *)m_puwExcContent + OS_NVIC_INT_ACT_SIZE; /* Save interrupt priority register group (start addr: 0xE000E400, size: 240bytes), CMSIS-Core: NVIC->IP[0 - 239] */ memcpy(m_puwExcContent, (const void *)OS_NVIC_PRI_BASE, OS_NVIC_INT_PRI_SIZE); m_puwExcContent = (UINT8 *)m_puwExcContent + OS_NVIC_INT_PRI_SIZE; /* Save system exception priority register group (start addr: 0xE000ED18, size: 12bytes, CMSIS-Core: SCB->SHP[0 - 11]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_EXCPRI_BASE, 12); m_puwExcContent = (UINT8 *)m_puwExcContent + 12; /* Save system processing control and state register group (start addr: 0xE000ED24, size: 4bytes, CMSIS-Core: SCB->SHCSR) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_SHCSR, 4); m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save interrupt control and status register group (start addr: 0xE000ED04, size: 4bytes, CMSIS-Core: SCB->ICSR) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_INT_CTRL, 4); m_puwExcContent = (UINT8 *)m_puwExcContent + 4; return; } /***************************************************************************** Function : osExcRegister Description : Register exception Input : uwType --- exception type : pFunc --- exception callback function : pArg --- exception save info arg, not pFunc Output : None Return : None *****************************************************************************/ VOID osExcRegister(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, VOID *pArg) { EXC_INFO_ARRAY_S *pstExcInfo; if (uwType == 0 || uwType >= OS_EXC_TYPE_MAX || pFunc == NULL) { PRINT_ERR("osExcRegister ERROR!\n"); return; } pstExcInfo = &(m_stExcArray[uwType - 1]); pstExcInfo->uwType = uwType; pstExcInfo->pFnExcInfoCb = pFunc; pstExcInfo->pArg = pArg; pstExcInfo->uwValid = TRUE; } /***************************************************************************** Function : osExcSaveSysInfo Description : Saving exception information by calling callback function recursively Input : uwType --- exception type(OS_EXC_TYPE_CONTEXT+1 ---> OS_EXC_TYPE_MAX-1) : pFunc --- callback function : uwLoop --- loop total count : uwLen --- The size of the data saved each time : uwIdx --- loop index Output : None Return : None *****************************************************************************/ VOID osExcSaveSysInfo(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, UINT32 uwLoop, UINT32 uwLen, UINT32 uwIdx) { UINT32 uwRet; UINT32 uwBuffer[OS_EXC_MAX_BUF_LEN]; /* Save exception type and size */ *((UINT32 *)m_puwExcContent) = uwType; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; *((UINT32 *)m_puwExcContent) = uwLen * (uwLoop - uwIdx); m_puwExcContent = (UINT8 *)m_puwExcContent + 4; for (; uwIdx < uwLoop; uwIdx++) { memset((VOID *)uwBuffer, 0, sizeof(UINT32) * OS_EXC_MAX_BUF_LEN); uwRet = pFunc(uwIdx, (VOID *)uwBuffer); if (LOS_OK == uwRet) { memcpy(m_puwExcContent, (VOID *)uwBuffer, uwLen); } m_puwExcContent =(UINT8 *)m_puwExcContent + uwLen; } } /***************************************************************************** Function : osExcSaveInfo Description : save exception info Input : uwType --- exception type(OS_EXC_TYPE_CONTEXT+1 ---> OS_EXC_TYPE_MAX-1) : pFunc --- exception callback : pArg --- register arg, used to generate the arg passed to the callback Output : None Return : None *****************************************************************************/ static VOID osExcSaveInfo(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, VOID *pArg) { UINT32 uwLen; UINT32 uwIdx; UINT32 uwLoop; UINT32 uwTaskSwitchCount = 0; OS_TASK_SWITCH_INFO *pstTaskSwitchInfo; switch(uwType) { case OS_EXC_TYPE_TSK: /* save task info */ uwLen = sizeof(TSK_INFO_S); uwLoop = *(UINT32 *)pArg; uwIdx = 0; break; case OS_EXC_TYPE_QUE: /* save queue info */ uwLen = sizeof(QUEUE_INFO_S); uwLoop = *(UINT32 *)pArg; uwIdx = 0; break; case OS_EXC_TYPE_NVIC: /* save NVIC info */ (VOID)pFunc(0, 0); goto END; case OS_EXC_TYPE_TSK_SWITCH: /* save task switch info */ pstTaskSwitchInfo = pArg; uwTaskSwitchCount = pstTaskSwitchInfo->ucIsFull & 0x7F; uwLen = sizeof(UINT32) + sizeof(CHAR) * LOS_TASK_NAMELEN; /* auwPID + acName */ if (pstTaskSwitchInfo->ucIsFull & 0x80) { uwIdx = pstTaskSwitchInfo->ucIdx; uwLoop = uwIdx + uwTaskSwitchCount; } else { uwIdx = 0; uwLoop = pstTaskSwitchInfo->ucIdx; } break; case OS_EXC_TYPE_MEM: /* save mem info */ uwLen = sizeof(MEM_INFO_S); uwLoop = *(UINT32 *)pArg; uwIdx = 0; break; default: goto END; } osExcSaveSysInfo(uwType, (EXC_INFO_SAVE_CALLBACK)pFunc, uwLoop, uwLen, uwIdx); END: return; } /***************************************************************************** Function : osExcSave2DDR Description : Save exception info to RAM Input : None Output : None Return : None *****************************************************************************/ static VOID osExcSave2DDR(VOID) { UINT32 uwIdx = 0; UINT32 uwExcContextSize; if (m_stExcInfo.usFpuContext == 1) { uwExcContextSize = sizeof(EXC_CONTEXT_S); } else { uwExcContextSize = sizeof(EXC_CONTEXT_S) - 136; /* except FPU register */ } memset(m_puwExcContent, 0xff, g_uwArraySize); /* Cortex-M type */ *((UINT32 *)m_puwExcContent) = 4; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* * Save exception type: OS_EXC_TYPE_CONTEXT */ *((UINT32 *)m_puwExcContent) = OS_EXC_TYPE_CONTEXT; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* The size of struct EXC_INFO_S(except member EXC_CONTEXT_S*) and exception context size */ *((UINT32 *)m_puwExcContent) = sizeof(EXC_INFO_S) - sizeof(EXC_CONTEXT_S *) + uwExcContextSize; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save struct m_stExcInfo except m_stExcInfo.pstContext */ memcpy((VOID *)m_puwExcContent, (VOID *)&m_stExcInfo, sizeof(EXC_INFO_S) - sizeof(EXC_CONTEXT_S *)); m_puwExcContent = (UINT8 *)m_puwExcContent + sizeof(EXC_INFO_S) - sizeof(EXC_CONTEXT_S *); /* Save struct EXC_CONTEXT_S */ if (m_stExcInfo.usFpuContext == 0) { #if FPU_EXIST /* m_stExcInfo.pstContext: init --- point to S16, S16->S31 invalid * + 64 --- point to uwR4 * copy uwR4 -> uwxPSR */ memcpy((VOID *)m_puwExcContent, (UINT8 *)m_stExcInfo.pstContext + 64, uwExcContextSize); #else memcpy((VOID *)m_puwExcContent, m_stExcInfo.pstContext, uwExcContextSize); #endif } else { memcpy((VOID *)m_puwExcContent, m_stExcInfo.pstContext, uwExcContextSize); } m_puwExcContent = (UINT8 *)m_puwExcContent + uwExcContextSize; /* * Save exception type: OS_EXC_TYPE_CONTEXT+1 ---> OS_EXC_TYPE_MAX-1 */ for (uwIdx = 0; uwIdx < OS_EXC_TYPE_MAX - 1; uwIdx++) { if (m_stExcArray[uwIdx].uwValid == FALSE) { continue; } osExcSaveInfo(m_stExcArray[uwIdx].uwType, m_stExcArray[uwIdx].pFnExcInfoCb, m_stExcArray[uwIdx].pArg); } /* * Save exception type: OS_EXC_TYPE_MAX */ *((UINT32 *)m_puwExcContent) = OS_EXC_TYPE_MAX; m_puwExcContent = (UINT8*)m_puwExcContent + 4; return; } #endif /*(LOSCFG_SAVE_EXC_INFO == YES)*/ /***************************************************************************** Function : osExcInit Description : Initializes the EXC Input : None Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT_INIT VOID osExcInit(UINT32 uwArraySize) { #if (LOSCFG_PLATFORM_HWI == YES) /* Register exception handler to interrupt vector table in RAM */ m_pstHwiForm[-14 + OS_SYS_VECTOR_CNT] = NMI_Handler; m_pstHwiForm[-13 + OS_SYS_VECTOR_CNT] = HardFault_Handler; m_pstHwiForm[-12 + OS_SYS_VECTOR_CNT] = MemManage_Handler; m_pstHwiForm[-11 + OS_SYS_VECTOR_CNT] = BusFault_Handler; m_pstHwiForm[-10 + OS_SYS_VECTOR_CNT] = UsageFault_Handler; m_pstHwiForm[-5 + OS_SYS_VECTOR_CNT] = SVC_Handler; #endif /* Enable USGFAULT(BIT_18), BUSFAULT(BIT_17), MEMFAULT(BIT_16) */ *(volatile UINT32 *)OS_NVIC_SHCSR |= 0x70000; /* Enable DIV 0(BIT_4) exception, unaligned(BIT_3) disable */ *(volatile UINT32 *)OS_NVIC_CCR |= 0x10; #if (LOSCFG_SAVE_EXC_INFO == YES) g_uwArraySize = uwArraySize; osExcRegister((EXC_INFO_TYPE)OS_EXC_TYPE_NVIC, (EXC_INFO_SAVE_CALLBACK)osExcSaveIntStatus, NULL); #endif } VOID osBackTrace(VOID) { return; } #endif /*(LOSCFG_PLATFORM_EXC == YES)*/ #ifdef __cplusplus #if __cplusplus } #endif /* __cpluscplus */ #endif /* __cpluscplus */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m3/los_exc.inc ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _LOS_EXC_INC #define _LOS_EXC_INC #include "los_exc.ph" #include "los_sys.ph" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cpluscplus */ #endif /* __cpluscplus */ #ifdef __cplusplus #if __cplusplus } #endif /* __cpluscplus */ #endif /* __cpluscplus */ #endif /* _LOS_EXC_INC */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m3/los_exc.ph ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _LOS_EXC_PH #define _LOS_EXC_PH #include "los_exc.h" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ #if (LOSCFG_PLATFORM_EXC == YES) typedef enum { OS_EXC_TYPE_CONTEXT = 0, OS_EXC_TYPE_TSK = 1, OS_EXC_TYPE_QUE = 2, OS_EXC_TYPE_NVIC = 3, OS_EXC_TYPE_TSK_SWITCH = 4, OS_EXC_TYPE_MEM = 5, OS_EXC_TYPE_MAX = 6 } EXC_INFO_TYPE; typedef struct tagExcInfoCallBackArray { EXC_INFO_TYPE uwType; UINT32 uwValid; EXC_INFO_SAVE_CALLBACK pFnExcInfoCb; VOID* pArg; }EXC_INFO_ARRAY_S; #define OS_NVIC_SHCSR 0xE000ED24 #define OS_NVIC_CCR 0xE000ED14 #define OS_NVIC_INT_ENABLE_SIZE 0x20 #define OS_NVIC_INT_PRI_SIZE 0xF0 #define OS_NVIC_INT_PEND_SIZE OS_NVIC_INT_ACT_SIZE #define OS_NVIC_INT_ACT_SIZE OS_NVIC_INT_ENABLE_SIZE #define MAX_SCENE_INFO_SIZE (8 + sizeof(EXC_INFO_S) - 4 + sizeof(EXC_CONTEXT_S)) #define MAX_TSK_INFO_SIZE (8 + sizeof(TSK_INFO_S) * (LOSCFG_BASE_CORE_TSK_LIMIT + 1)) #define MAX_INT_INFO_SIZE (8 + 0x164) #if (LOSCFG_BASE_IPC_QUEUE == YES) #define MAX_QUEUE_INFO_SIZE (8 + sizeof(QUEUE_INFO_S) * LOSCFG_BASE_IPC_QUEUE_LIMIT) #else #define MAX_QUEUE_INFO_SIZE (0) #endif #if (LOSCFG_BASE_CORE_EXC_TSK_SWITCH == YES) #define MAX_SWITCH_INFO_SIZE (8 + (sizeof(UINT32) + sizeof(CHAR) * LOS_TASK_NAMELEN) * OS_TASK_SWITCH_INFO_COUNT) #else #define MAX_SWITCH_INFO_SIZE (0) #endif #if (LOSCFG_BASE_MEM_NODE_INTEGRITY_CHECK == YES) #define MAX_MEM_INFO_SIZE (8 + sizeof(MEM_INFO_S) * OS_SYS_MEM_NUM) #else #define MAX_MEM_INFO_SIZE (0) #endif #if (LOSCFG_SAVE_EXC_INFO == YES) #define MAX_EXC_MEM_SIZE ( 4 + MAX_SCENE_INFO_SIZE + MAX_TSK_INFO_SIZE + MAX_QUEUE_INFO_SIZE + MAX_INT_INFO_SIZE + MAX_SWITCH_INFO_SIZE + MAX_MEM_INFO_SIZE + 4) #else #define MAX_EXC_MEM_SIZE ( 0 ) #endif extern VOID osExcRegister(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, VOID *pArg); #endif #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ #endif ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m3/test_funcs.S ================================================ AREA sectionname ,CODE ,READONLY EXPORT TEST_NONALIGNED EXPORT TEST_PREFETCH EXPORT TEST_NOSUPERVISORVISIT EXPORT TEST_TOARM TEST_NONALIGNED FUNCTION SUB R13, #1 MOV R0, #0X13 PUSH {R1} POP {R1} ADD R13,#1 BX LR ENDFUNC TEST_PREFETCH FUNCTION MOV R0 , #0X1F000000 ORR R0,R0,#0XFF0000 ORR R0,R0,#0XC400 MOV PC ,R0;0X1FFFC400 BX LR ENDFUNC TEST_NOSUPERVISORVISIT FUNCTION MOV R0,#0XE0000000 ORR R0,R0,#0X2200 MOV PC,R0 BX LR ENDFUNC TEST_TOARM FUNCTION MOV R3,LR AND R3,0XFFFFFFFE BX R3 ENDFUNC END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m4/Makefile ================================================ objs-y += los_exc.o ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m4/gcc/los_dispatch_gcc.S ================================================ /** ---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /** ---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**************************************************************************************** * EXPORT FUNCTIONS ****************************************************************************************/ .global LOS_IntLock .global LOS_IntUnLock .global LOS_IntRestore .global LOS_StartToRun .global osTaskSchedule .global PendSV_Handler /**************************************************************************************** * EXTERN PARAMETERS ****************************************************************************************/ .extern g_stLosTask .extern g_pfnTskSwitchHook .extern g_bTaskScheduled /**************************************************************************************** * EQU ****************************************************************************************/ .equ OS_NVIC_INT_CTRL, 0xE000ED04 /* Interrupt Control and State Register. */ .equ OS_NVIC_PENDSVSET, 0x10000000 /* Value to trigger PendSV exception. */ .equ OS_NVIC_SYSPRI2, 0xE000ED20 /* System Handler Priority Register 2. */ .equ OS_NVIC_PENDSV_SYSTICK_PRI, 0xFFFF0000 /* SysTick + PendSV priority level (lowest). */ .equ OS_TASK_STATUS_RUNNING, 0x0010 /* Task Status Flag (RUNNING). */ /**************************************************************************************** * CODE GENERATION DIRECTIVES ****************************************************************************************/ .section .text .thumb .syntax unified .arch armv7e-m /**************************************************************************************** * Function: * VOID LOS_StartToRun(VOID); * Description: * Start the first task, which is the highest priority task in the priority queue. * Other tasks are started by task scheduling. ****************************************************************************************/ .type LOS_StartToRun, %function LOS_StartToRun: CPSID I /** * Set PendSV and SysTick prority to the lowest. * read ---> modify ---> write-back. */ LDR R0, =OS_NVIC_SYSPRI2 LDR R1, =OS_NVIC_PENDSV_SYSTICK_PRI LDR R2, [R0] ORR R1, R1, R2 STR R1, [R0] /** * Set g_bTaskScheduled = 1. */ LDR R0, =g_bTaskScheduled MOV R1, #1 STR R1, [R0] /** * Set g_stLosTask.pstRunTask = g_stLosTask.pstNewTask. */ LDR R0, =g_stLosTask LDR R1, [R0, #4] STR R1, [R0] /** * Set g_stLosTask.pstRunTask->usTaskStatus |= OS_TASK_STATUS_RUNNING. */ LDR R1, [R0] LDRH R2, [R1, #4] MOV R3, #OS_TASK_STATUS_RUNNING ORR R2, R2, R3 STRH R2, [R1, #4] /** * Restore the default stack frame(R0-R3,R12,LR,PC,xPSR) of g_stLosTask.pstRunTask to R0-R7. * [Initial EXC_RETURN ignore,] return by setting the CONTROL register. * * The initial stack of the current running task is as follows: * * POP: Restore the context of the current running task ===>| * High addr--->| * Bottom of the stack--->| * ----------+---------------------------------+--------------------------------+ * | R4-R11, PRIMASK, EXC_RETURN | R0-R3, R12, LR, PC, xPSR | * ----------+---------------------------------+--------------------------------+ * |<---Top of the stack, restored from g_stLosTask.pstRunTask->pStackPointer * |<--- skip --->|<--- copy to R0-R7 --->| * R12 to PSP--->| * Stack pointer after LOS_StartToRun--->| */ LDR R12, [R1] ADD R12, R12, #36 /* skip R4-R11, PRIMASK. */ #if defined (__VFP_FP__) && !defined(__SOFTFP__) ADD R12, R12, #4 /* if FPU exist, skip EXC_RETURN. */ #endif LDMFD R12!, {R0-R7} /** * Set the stack pointer of g_stLosTask.pstRunTask to PSP. */ MSR PSP, R12 /** * Set the CONTROL register, after schedule start, privilege level and stack = PSP. */ MOV R12, #2 MSR CONTROL, R12 /** * Enable interrupt. (The default PRIMASK value is 0, so enable directly) */ MOV LR, R5 CPSIE I /** * Jump directly to the default PC of g_stLosTask.pstRunTask, the field information * of the main function will be destroyed and will never be returned. */ BX R6 /**************************************************************************************** * Function: * UINTPTR LOS_IntLock(VOID); * Description: * Disable all interrupts except Reset,NMI and HardFault. * The value of currnet interruption state will be returned to the caller to save. * * Function: * VOID LOS_IntRestore(UINTPTR uvIntSave); * Description: * Restore the locked interruption of LOS_IntLock. * The caller must pass in the value of interruption state previously saved. ****************************************************************************************/ .type LOS_IntLock, %function LOS_IntLock: MRS R0, PRIMASK CPSID I BX LR .type LOS_IntUnLock, %function LOS_IntUnLock: MRS R0, PRIMASK CPSIE I BX LR .type LOS_IntRestore, %function LOS_IntRestore: MSR PRIMASK, R0 BX LR /**************************************************************************************** * Function: * VOID osTaskSchedule(VOID); * Description: * Start the task swtich process by software trigger PendSV interrupt. ****************************************************************************************/ .type osTaskSchedule, %function osTaskSchedule: LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] BX LR /**************************************************************************************** * Function: * VOID PendSV_Handler(VOID); * Description: * PendSV interrupt handler, switch the context of the task. * First: Save the context of the current running task(g_stLosTask.pstRunTask) * to its own stack. * Second: Restore the context of the next running task(g_stLosTask.pstNewTask) * from its own stack. ****************************************************************************************/ .type PendSV_Handler, %function PendSV_Handler: /** * R12: Save the interruption state of the current running task. * Disable all interrupts except Reset,NMI and HardFault */ MRS R12, PRIMASK CPSID I /** * Call task switch hook. */ LDR R2, =g_pfnTskSwitchHook LDR R2, [R2] CBZ R2, TaskSwitch PUSH {R12, LR} BLX R2 POP {R12, LR} TaskSwitch: /** * R0 = now stack pointer of the current running task. */ MRS R0, PSP /** * Save the stack frame([S16-S31],R4-R11) of the current running task. * R12 save the PRIMASK value of the current running task. * NOTE: 1. Before entering the exception handler function, these registers * ([NO_NAME,FPSCR,S15-S0],xPSR,PC,LR,R12,R3-R0) have been automatically * saved by the CPU in the stack of the current running task. * 2. If lazy stacking is enabled, space is reserved on the stack for * the floating-point context(FPSCR,S15-S0), but the floating-point state * is not saved. when the floating-point instruction(VSTMDBEQ R0!, {D8-D15}) * is executed, the floating-point context(FPSCR,S15-S0) is first saved into * the space reserved on the stack. In other words, the instruction * 'VSTMDBEQ R0!, {D8-D15}' will trigger the CPU to save 'FPSCR,S15-S0' first. * * The stack of the current running task is as follows: * * |<=== PUSH: Save the context of the current running task * | High addr--->| * --+-----------------------------------+-------------------------------------------+--- * | R4-R11,PRIMASK,EXC_RETURN,S16-S31 | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | * | [ lazy stacking ]| * --+-----------------------------------+-------------------------------------------+--- * Stack pointer before entering exception--->| * |<--- cpu auto saved --->| * |<---PSP to R0 * |<---Top of the stack, save to g_stLosTask.pstRunTask->pStackPointer */ #if defined (__VFP_FP__) && !defined(__SOFTFP__) /* if FPU exist. */ TST R14, #0x10 /* if the task using the FPU context, push s16-s31. */ IT EQ VSTMDBEQ R0!, {D8-D15} STMFD R0!, {R14} /* save EXC_RETURN. */ #endif STMFD R0!, {R4-R12} /* save the core registers and PRIMASK. */ /** * R5,R8. */ LDR R5, =g_stLosTask MOV R8, #OS_TASK_STATUS_RUNNING /** * Save the stack pointer of the current running task to TCB. * (g_stLosTask.pstRunTask->pStackPointer = R0) */ LDR R6, [R5] STR R0, [R6] /** * Clear the RUNNING state of the current running task. * (g_stLosTask.pstRunTask->usTaskStatus &= ~OS_TASK_STATUS_RUNNING) */ LDRH R7, [R6, #4] BIC R7, R7, R8 STRH R7, [R6, #4] /** * Switch the current running task to the next running task. * (g_stLosTask.pstRunTask = g_stLosTask.pstNewTask) */ LDR R0, [R5, #4] STR R0, [R5] /** * Set the RUNNING state of the next running task. * (g_stLosTask.pstNewTask->usTaskStatus |= OS_TASK_STATUS_RUNNING) */ LDRH R7, [R0, #4] ORR R7, R7, R8 STRH R7, [R0, #4] /** * Restore the stack pointer of the next running task from TCB. * (R1 = g_stLosTask.pstNewTask->pStackPointer) */ LDR R1, [R0] /** * Restore the stack frame(R4-R11,[S16-S31]) of the next running task. * R12 restore the PRIMASK value of the next running task. * NOTE: After exiting the exception handler function, these registers * (PC,xPSR,R0-R3,R12,LR,[S0-S15,FPSCR,NO_NAME]) will be automatically * restored by the CPU from the stack of the next running task. * * 1. The stack of the next running task is as follows: * * POP: Restore the context of the next running task ===>| * High addr--->| * --+-----------------------------------+-------------------------------------------+--- * | R4-R11,PRIMASK,EXC_RETURN,S16-S31 | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | * --+-----------------------------------+-------------------------------------------+--- * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer * R1 to PSP--->| * |<--- cpu auto restoring --->| * Stack pointer after exiting exception--->| * * 2. If the next running task is run for the first time, the stack is as follows: * * POP: Restore the context of the next running task ===>| * High addr--->| * Bottom of the stack--->| * ----------+---------------------------------+--------------------------------+ * | R4-R11, PRIMASK, EXC_RETURN | R0-R3, R12, LR, PC, xPSR | * ----------+---------------------------------+--------------------------------+ * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer * R1 to PSP--->| * |<--- cpu auto restoring --->| * Stack pointer after exiting exception--->| */ LDMFD R1!, {R4-R12} /* restore the core registers and PRIMASK. */ #if defined (__VFP_FP__) && !defined(__SOFTFP__) /* if FPU exist. */ LDMFD R1!, {R14} /* restore EXC_RETURN. */ TST R14, #0x10 /* if the task using the FPU context, pop s16-s31. */ IT EQ VLDMIAEQ R1!, {D8-D15} #endif /** * Set the stack pointer of the next running task to PSP. */ MSR PSP, R1 /** * Restore the interruption state of the next running task. */ MSR PRIMASK, R12 BX LR ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m4/gcc/los_hw_exc_gcc.S ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**************************************************************************************** * CODE GENERATION DIRECTIVES ****************************************************************************************/ .syntax unified .arch armv7e-m .thumb .section .text /**************************************************************************************** * EXPORT FUNCTIONS ****************************************************************************************/ .global NMI_Handler .global HardFault_Handler .global MemManage_Handler .global BusFault_Handler .global UsageFault_Handler .global SVC_Handler /**************************************************************************************** * EXTERN PARAMETERS ****************************************************************************************/ .extern osExcHandleEntry .extern g_uwExcTbl .extern g_bTaskScheduled /**************************************************************************************** * EQU ****************************************************************************************/ .equ OS_EXC_CAUSE_NMI, 18 .equ OS_EXC_CAUSE_HARDFAULT, 19 .equ OS_EXC_CAUSE_MEMFAULT, 20 .equ OS_EXC_CAUSE_BUSFAULT, 21 .equ OS_EXC_CAUSE_USAGEFAULT, 22 .equ OS_EXC_CAUSE_SVC, 23 .equ HF_DEBUGEVT, 24 .equ HF_VECTBL, 25 .equ FLAG_ADDR_VALID, 0x10000 /* bit 16 */ .equ FLAG_HWI_ACTIVE, 0x20000 /* bit 17 */ .equ FLAG_NO_FLOAT, 0x10000000 /* bit 28 */ .equ OS_NVIC_CFSR, 0xE000ED28 /* include BusFault/MemFault/UsageFault State Regeister */ .equ OS_NVIC_HFSR, 0xE000ED2C /* HardFault State Regeister */ .equ OS_NVIC_BFAR, 0xE000ED38 .equ OS_NVIC_MMFAR, 0xE000ED34 .equ OS_NVIC_ACT_BASE, 0xE000E300 .equ OS_NVIC_SHCSRS, 0xE000ED24 .equ OS_NVIC_SHCSR_MASK, 0xC00 /* SYSTICKACT and PENDSVACT */ /**************************************************************************************** * Function: * VOID NMI_Handler(VOID); * Description: * NMI Handler. ****************************************************************************************/ .type NMI_Handler, %function NMI_Handler: /** * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. * < R0 >: * +------------------------------------------------------+------------------------+ * | 31-8 | 7-0 | * +------------------------------------------------------+------------------------+ * | --- | OS_EXC_CAUSE_NMI | * +------------------------------------------------------+------------------------+ * < R1 >: invalid */ MOV R0, #OS_EXC_CAUSE_NMI MOV R1, #0 B osExcDispatch /**************************************************************************************** * Function: * VOID HardFault_Handler(VOID); * Description: * HardFault Handler. ****************************************************************************************/ .type HardFault_Handler, %function HardFault_Handler: /** * Check HardFault state register. * * HFSR: * +----------+--------+--------+--------+-------+ * | 31 | 30 | 29 - 2 | 1 | 0 | * +----------+--------+--------+--------+-------+ * | DEBUGEVT | FORCED | -- | VECTBL | -- | * +----------+--------+--------+--------+-------+ */ MOV R0, #OS_EXC_CAUSE_HARDFAULT LDR R2, =OS_NVIC_HFSR LDR R2, [R2] /** * Check whether HardFault are triggered by debugging events. * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. * < R0 >: * +----------------------------------------+-------------+------------------------+ * | 31-16 | 15-8 | 7-0 | * +----------------------------------------+-------------+------------------------+ * | --- | HF_DEBUGEVT | OS_EXC_CAUSE_HARDFAULT | * +----------------------------------------+-------------+------------------------+ * < R1 >: invalid */ MOV R1, #HF_DEBUGEVT ORR R0, R0, R1, LSL #0x8 TST R2, #0x80000000 BNE osExcDispatch /* DEBUGEVT */ /** * Check whether HardFault is caused by the failure of the fetch vector. * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. * < R0 >: * +----------------------------------------+-------------+------------------------+ * | 31-16 | 15-8 | 7-0 | * +----------------------------------------+-------------+------------------------+ * | --- | HF_VECTBL | OS_EXC_CAUSE_HARDFAULT | * +----------------------------------------+-------------+------------------------+ * < R1 >: invalid */ AND R0, R0, #0x000000FF MOV R1, #HF_VECTBL ORR R0, R0, R1, LSL #0x8 TST R2, #0x00000002 BNE osExcDispatch /* VECTBL */ /** * If it`s not DEBUGEVT and VECTBL, that is FORCED, then read the CFSR register to * check BusFault, MemFault and UsageFault. * R0: OS_EXC_CAUSE_HARDFAULT * * CFSR: * +----------------+--------+--------+ * | 31-16 | 15-8 | 7-0 | * +----------------+--------+--------+ * | UFSR | BFSR | MFSR | * +----------------+--------+--------+ */ AND R0, R0, #0x000000FF LDR R2, =OS_NVIC_CFSR LDR R2, [R2] TST R2, #0x8000 /* BFSR->BFARVALID */ BNE _HFBusFault /* BusFault */ TST R2, #0x80 /* MFSR->MMARVALID */ BNE _HFMemFault /* MemFault */ /** * BFARVALID and MMARVALID flag both invalid. * R12: 0 --- The error address is invalid. */ MOV R12, #0 B osHFExcCommonBMU /** * BFARVALID flag valid, read BFAR register. * R1 : BFAR value --- The address value of a bus error. * R12: The error address is valid. */ _HFBusFault: LDR R1, =OS_NVIC_BFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID B osHFExcCommonBMU /** * MMARVALID flag valid, read MMFAR register. * R1 : MMFAR value --- The address value of memory management error. * R12: The error address is valid. */ _HFMemFault: LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID /** * osHFExcCommonBMU: --- Get specific error status from table g_uwExcTbl, stored in R0. * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. * < R0 >: * +-------------------+-----------------+------------------+------------------------+ * | 31-17 | 16 | 15-8 | 7-0 | * +-------------------+-----------------+------------------+------------------------+ * | --- | FLAG_ADDR_VALID | Error state code | OS_EXC_CAUSE_HARDFAULT | * | | or | in | | * | | 0(invalid) | table g_uwExcTbl | | * +-------------------+-----------------+------------------+------------------------+ * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, * else invalid. */ osHFExcCommonBMU: CLZ R2, R2 LDR R3, =g_uwExcTbl ADD R3, R3, R2 LDRB R2, [R3] ORR R0, R0, R2, LSL #0x8 ORR R0, R0, R12 B osExcDispatch /**************************************************************************************** * Function: * VOID SVC_Handler(VOID); * Description: * SVC Handler. ****************************************************************************************/ .type SVC_Handler, %function SVC_Handler: TST LR, #0x4 /* EXC_RETURN[b2] --- PSP or MSP */ ITE EQ MRSEQ R0, MSP MRSNE R0, PSP LDR R1, [R0, #24] /* The PC value in the stack frame */ LDRB R0, [R1, #-2] /* R0: The number of SVC (0 - 255) */ MOV R1, #0 /* B osExcDispatch */ _SvcLoop: B _SvcLoop /**************************************************************************************** * Function: * VOID BusFault_Handler(VOID); * Description: * BusFault Handler. ****************************************************************************************/ .type BusFault_Handler, %function BusFault_Handler: LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_BUSFAULT TST R0, #0x8000 /* BFSR->BFARVALID */ BEQ _ExcBusNoADDR LDR R1, =OS_NVIC_BFAR LDR R1, [R1] /* R1: The value of BFAR */ MOV R12, #FLAG_ADDR_VALID /* R12: BusFault addr valid */ AND R0, R0, #0x3F00 /* R0: Reserved the b13-b8 of the BFSR */ B osExcCommonBMU _ExcBusNoADDR: MOV R12, #0 /* R12: BusFault addr invalid */ AND R0, R0, #0x3F00 /* R0: Reserved the b13-b8 of the BFSR */ B osExcCommonBMU /**************************************************************************************** * Function: * VOID MemManage_Handler(VOID); * Description: * MemManage Handler. ****************************************************************************************/ .type MemManage_Handler, %function MemManage_Handler: LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_MEMFAULT TST R0, #0x80 /* MFSR->MMARVALID */ BEQ _ExcMemNoADDR LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] /* R1: The value of MMFAR */ MOV R12, #FLAG_ADDR_VALID /* R12: MemFault addr valid */ AND R0, R0, #0x3B /* R0: Reserved the b5-b0 of the MFSR */ B osExcCommonBMU _ExcMemNoADDR: MOV R12, #0 /* R12: MemFault addr invalid */ AND R0, R0, #0x3B /* R0: Reserved the b5-b0 of the MFSR */ B osExcCommonBMU /**************************************************************************************** * Function: * VOID UsageFault_Handler(VOID); * Description: * UsageFault Handler. ****************************************************************************************/ .type UsageFault_Handler, %function UsageFault_Handler: LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_USAGEFAULT LDR R1, =#0x030F LSL R1, R1, #16 AND R0, R0, R1 /* R0: reserved UFSR */ MOV R12, #0 /* R12: Fault addr invalid */ /** * osExcCommonBMU: BusFault_Handler,MemManage_Handler and UsageFault_Handler share. * Get specific error status from table g_uwExcTbl, stored in R0. * Before executing osExcDispatch, the value of R0 is as follows. * < R0 >: * +-------------------+-----------------+------------------+------------------------+ * | 31-17 | 16 | 15-8 | 7-0 | * +-------------------+-----------------+------------------+------------------------+ * | --- | FLAG_ADDR_VALID | Error state code |OS_EXC_CAUSE_BUSFAULT or| * | | or | in |OS_EXC_CAUSE_MEMFAULT or| * | | 0(invalid) | table g_uwExcTbl |OS_EXC_CAUSE_USAGEFAULT | * +-------------------+-----------------+------------------+------------------------+ * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, * else invalid. */ osExcCommonBMU: CLZ R0, R0 LDR R3, =g_uwExcTbl ADD R3, R3, R0 LDRB R0, [R3] LSL R0, R0, #0x8 ORR R0, R0, R2 ORR R0, R0, R12 /**************************************************************************************** * osExcDispatch: NMI_Handler, HardFault_Handler, SVC_Handler, BusFault_Handler, MemManage_Handler, * UsageFault_Handler sharing. ****************************************************************************************/ /** * When executing osExcDispatch, R0, R1 will be used. * The possible values of R0 and R1 are as follows. * * < R0 >: * +----------------+-----------------+---------------------+------------------------+ * | 31-17 | 16 | 15-8 | 7-0 | * +----------------+-----------------+---------------------+------------------------+ * | | FLAG_ADDR_VALID | Error state code in | OS_EXC_CAUSE_HARDFAULT | * | --- | or | table g_uwExcTbl |or OS_EXC_CAUSE_MEMFAULT| * | | 0(invalid) | or HF_DEBUGEVT |or OS_EXC_CAUSE_BUSFAULT| * | | | or HF_VECTBL |or OS_EXC_CAUSE_NMI or | * | | | | OS_EXC_CAUSE_USAGEFAULT| * +----------------+-----------------+---------------------+------------------------+ * b17: FLAG_HWI_ACTIVE * b28: FLAG_NO_FLOAT * NOTE: b17 and b28 will be set later. * * < R1 >: * If the bit16 of R0 is 1, then R1 is the value of BFAR or MMFAR, otherwise the * value in R1 is invalid. * */ osExcDispatch: LDR R2, =OS_NVIC_ACT_BASE MOV R12, #8 /* #8: externel interrupt active check loop counter(#0 - #239) */ _hwiActiveCheck: LDR R3, [R2] /* R3 store the value of externel interrupt active status */ CMP R3, #0 BEQ _hwiActiveCheckNext /** * Exception occured in external interrupt. */ ORR R0, R0, #FLAG_HWI_ACTIVE /* R0[b17] = 1, externel interrupt active valid &&&&&&&&&& */ RBIT R2, R3 /* bit reversal */ CLZ R2, R2 RSB R12, R12, #8 /* R12 = 8 - R12 */ ADD R2, R2, R12, LSL #5 /* R2: external interrupt number as uwPid */ /** * Interrupts and initialization phase always use MSP. */ _ExcInMSP: TST LR, #0x10 /* EXC_RETURN[b4] --- FPU(0) or without FPU(1) */ BNE _NoFloatInMsp /** * Before executing instruction 'B _handleEntry', MSP is as follows. * MSP: * High addr--->| * +--------------------------------------------------------------------------------+--------- * | S16-S31,R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | * +--------------------------------------------------------------------------------+--------- * |<---R13 Initial R13--->|<--- #104 --->|<---SAVED_SP * | (CPU auto saved) | * */ ADD R3, R13, #104 /* #104: skip [R0-xPSR,D0-D7,FPSCR,NO_NAME] */ PUSH {R3} /* push [SAVED_SP]: MSP+104 = Stack pointer in MSP before entering the exception */ MRS R12, PRIMASK PUSH {R4-R12} /* push R4-R11,PRIMASK to MSP */ VPUSH {D8-D15} /* push D8-D15 to MSP */ B _handleEntry /** * Before executing instruction 'B _handleEntry', MSP is as follows. * MSP: * High addr--->| * +--------------------------------------------------------------------------------+--------- * | R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR | * +--------------------------------------------------------------------------------+--------- * R13--->| Initial R13--->|<--- #32 --->|<---SAVED_SP * | (CPU auto saved) | * */ _NoFloatInMsp: ADD R3, R13, #32 /* #32: skip [R0-R3,R12,LR,PC,xPSR] */ PUSH {R3} /* push [SAVED_SP]: MSP+32 = Stack pointer in MSP before entering the exception */ MRS R12, PRIMASK PUSH {R4-R12} /* push R4-R11,PRIMASK to MSP */ ORR R0, R0, #FLAG_NO_FLOAT /* R0[b28] = 1, no FPU &&&&&&&&&& */ B _handleEntry _hwiActiveCheckNext: ADD R2, R2, #4 /* next NVIC ACT ADDR */ SUBS R12, R12, #1 BNE _hwiActiveCheck /** * Not in externel interrupt, check whether it is SysTick or PendSV. */ LDR R2, =OS_NVIC_SHCSRS LDRH R2,[R2] LDR R3,=OS_NVIC_SHCSR_MASK AND R2, R2, R3 CMP R2, #0 BNE _ExcInMSP /* SysTick or PendSV active */ /** * Check whether an exception occurs during the initialization phase. * If g_bTaskScheduled == 0, it is in the initialization phase. */ LDR R2, =g_bTaskScheduled LDR R2, [R2] TST R2, #1 BEQ _ExcInMSP /* initialization phase use MSP */ /** * Exception occured in Task. */ TST LR, #0x10 BNE _NoFloatInPsp /** * Before executing _handleEntry, MSP is as follows. * MSP: * High addr--->| * +--------------------------------------------------------------------------------+--------- * | S16-S31,R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | * +--------------------------------------------------------------------------------+--------- * |<---R13 |<--- #104 --->|<---Initial R13 * | (copied from PSP) | * R2(no use)--->| * * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME. */ MOV R2, R13 SUB R2, R2, #8 /* #8: reserved for [FPSCR,NO_NAME] */ SUB R13, #104 /* #104: MSP reserved, used to store stack frame in PSP */ MRS R3, PSP ADD R12, R3, #104 /* PSP+104 = Stack pointer of the task before entering the exception */ PUSH {R12} /* push task SP to MSP */ MRS R12, PRIMASK PUSH {R4-R12} /* push R4-R11,PRIMASK of the current running task to MSP */ VPUSH {D8-D15} /* push D8-D15 of the currnent running task to MSP */ /* Copy stack frame from the stack of the current running task to MSP */ LDMFD R3!, {R4-R11} /* restore stack frame[R0-xPSR] of PSP to R4-R11 */ VLDMIA R3!, {D8-D15} /* restore stack frame[D0-D7] of PSP to D8-D15 */ VSTMDB R2!, {D8-D15} /* save stack frame[D0-D7] to MSP */ STMFD R2!, {R4-R11} /* save stack frame[R0-xPSR] to MSP */ LDMFD R3, {R4-R5} /* restore stack frame[FPSCR,NO_NAME] to R4-R5 */ ADD R2, R2, #104 /* skip stack frame */ STMFD R2, {R4-R5} /* save stack frame[FPSCR,NO_NAME] to MSP */ B _handleEntry /** * Before executing _handleEntry, MSP is as follows. * MSP: * High addr--->| * +--------------------------------------------------------------------------------+--------- * | R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR | * +--------------------------------------------------------------------------------+--------- * R13--->| |<--- #32 --->|<---Initial R13 * | (copied from PSP) | * |<---R2(no use) * * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR. */ _NoFloatInPsp: MOV R2, R13 SUB R13, #32 /* #32: MSP reserved, used to store stack frame in PSP */ MRS R3, PSP ADD R12, R3, #32 /* PSP+32 = Stack pointer of the task before entering the exception */ PUSH {R12} /* push task SP to MSP */ MRS R12, PRIMASK PUSH {R4-R12} /* push R4-R11,PRIMASK of the current running task to MSP */ /* Copy stack frame from the stack of the current running task to MSP */ LDMFD R3, {R4-R11} /* restore stack frame of PSP to R4-R11 */ STMFD R2!, {R4-R11} /* save stack frame to MSP */ ORR R0, R0, #FLAG_NO_FLOAT /* R0[b28] = 1, no FPU &&&&&&&&&& */ /** * _handleEntry: Call osExcHandleEntry * param1: R0 --- b28: FLAG_NO_FLOAT. * b17: FLAG_HWI_ACTIVE. * b16: FLAG_ADDR_VALID. * b15-b8: Error state code in table g_uwExcTbl or HF_DEBUGEVT or HF_VECTBL. * b7-b0: OS_EXC_CAUSE_HARDFAULT or OS_EXC_CAUSE_NMI or OS_EXC_CAUSE_MEMFAULT * or OS_EXC_CAUSE_BUSFAULT or OS_EXC_CAUSE_USAGEFAULT. * param2: R1 --- The value of BFAR or MMFAR if R0[b16] = 1, otherwise invalid. * param3: R2 --- external interrupt number(0-239) if R0[b17] = 1, otherwise invalid. * param4: R3 --- Point to the top of the stack(R4 or S16) that the exception stack frame in MSP. */ _handleEntry: MOV R3, R13 CPSID I CPSID F B osExcHandleEntry NOP ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m4/iar/los_dispatch_iar.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2016-2018>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT LOS_IntLock EXPORT LOS_IntUnLock EXPORT LOS_IntRestore EXPORT LOS_StartToRun EXPORT osTaskSchedule EXPORT PendSV_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT g_stLosTask IMPORT g_pfnTskSwitchHook IMPORT g_bTaskScheduled ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt Control and State Register. OS_NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception. OS_NVIC_SYSPRI2 EQU 0xE000ED20 ; System Handler Priority Register 2. OS_NVIC_PENDSV_SYSTICK_PRI EQU 0xFFFF0000 ; SysTick + PendSV priority level (lowest). OS_TASK_STATUS_RUNNING EQU 0x0010 ; Task Status Flag (RUNNING). ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** SECTION .text:CODE(2) THUMB REQUIRE8 PRESERVE8 ;**************************************************************************************** ; Function: ; VOID LOS_StartToRun(VOID); ; Description: ; Start the first task, which is the highest priority task in the priority queue. ; Other tasks are started by task scheduling. ;**************************************************************************************** LOS_StartToRun CPSID I ;/** ; * Set PendSV and SysTick prority to the lowest. ; * read ---> modify ---> write-back. ; */ LDR R0, =OS_NVIC_SYSPRI2 LDR R1, =OS_NVIC_PENDSV_SYSTICK_PRI LDR R2, [R0] ORR R1, R1, R2 STR R1, [R0] ;/** ; * Set g_bTaskScheduled = 1. ; */ LDR R0, =g_bTaskScheduled MOV R1, #1 STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask = g_stLosTask.pstNewTask. ; */ LDR R0, =g_stLosTask LDR R1, [R0, #4] STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask->usTaskStatus |= OS_TASK_STATUS_RUNNING. ; */ LDR R1, [R0] LDRH R2, [R1, #4] MOV R3, #OS_TASK_STATUS_RUNNING ORR R2, R2, R3 STRH R2, [R1, #4] ;/** ; * Restore the default stack frame(R0-R3,R12,LR,PC,xPSR) of g_stLosTask.pstRunTask to R0-R7. ; * [Initial EXC_RETURN ignore,] return by setting the CONTROL register. ; * ; * The initial stack of the current running task is as follows: ; * ; * POP: Restore the context of the current running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+---------------------------------+--------------------------------+ ; * | R4-R11, PRIMASK, EXC_RETURN | R0-R3, R12, LR, PC, xPSR | ; * ----------+---------------------------------+--------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstRunTask->pStackPointer ; * |<--- skip --->|<--- copy to R0-R7 --->| ; * R12 to PSP--->| ; * Stack pointer after LOS_StartToRun--->| ; */ LDR R12, [R1] ADD R12, R12, #36 ; skip R4-R11, PRIMASK. #if defined (__ARMVFP__) ADD R12, R12, #4 ; if FPU exist, skip EXC_RETURN. #endif LDMFD R12!, {R0-R7} ;/** ; * Set the stack pointer of g_stLosTask.pstRunTask to PSP. ; */ MSR PSP, R12 ;/** ; * Set the CONTROL register, after schedule start, privilege level and stack = PSP. ; */ MOV R12, #2 MSR CONTROL, R12 ;/** ; * Enable interrupt. (The default PRIMASK value is 0, so enable directly) ; */ MOV LR, R5 CPSIE I ;/** ; * Jump directly to the default PC of g_stLosTask.pstRunTask, the field information ; * of the main function will be destroyed and will never be returned. ; */ BX R6 ;**************************************************************************************** ; Function: ; UINTPTR LOS_IntLock(VOID); ; Description: ; Disable all interrupts except Reset,NMI and HardFault. ; The value of currnet interruption state will be returned to the caller to save. ; ; Function: ; VOID LOS_IntRestore(UINTPTR uvIntSave); ; Description: ; Restore the locked interruption of LOS_IntLock. ; The caller must pass in the value of interruption state previously saved. ;**************************************************************************************** LOS_IntLock MRS R0, PRIMASK CPSID I BX LR LOS_IntUnLock MRS R0, PRIMASK CPSIE I BX LR LOS_IntRestore MSR PRIMASK, R0 BX LR ;**************************************************************************************** ; Function: ; VOID osTaskSchedule(VOID); ; Description: ; Start the task swtich process by software trigger PendSV interrupt. ;**************************************************************************************** osTaskSchedule LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] BX LR ;**************************************************************************************** ; Function: ; VOID PendSV_Handler(VOID); ; Description: ; PendSV interrupt handler, switch the context of the task. ; First: Save the context of the current running task(g_stLosTask.pstRunTask) ; to its own stack. ; Second: Restore the context of the next running task(g_stLosTask.pstNewTask) ; from its own stack. ;**************************************************************************************** PendSV_Handler ;/** ; * R12: Save the interruption state of the current running task. ; * Disable all interrupts except Reset,NMI and HardFault ; */ MRS R12, PRIMASK CPSID I ;/** ; * Call task switch hook. ; */ LDR R2, =g_pfnTskSwitchHook LDR R2, [R2] CBZ R2, TaskSwitch PUSH {R12, LR} BLX R2 POP {R12, LR} TaskSwitch ;/** ; * R0 = now stack pointer of the current running task. ; */ MRS R0, PSP ;/** ; * Save the stack frame([S16-S31],R4-R11) of the current running task. ; * R12 save the PRIMASK value of the current running task. ; * NOTE: 1. Before entering the exception handler function, these registers ; * ([NO_NAME,FPSCR,S15-S0],xPSR,PC,LR,R12,R3-R0) have been automatically ; * saved by the CPU in the stack of the current running task. ; * 2. If lazy stacking is enabled, space is reserved on the stack for ; * the floating-point context(FPSCR,S15-S0), but the floating-point state ; * is not saved. when the floating-point instruction(VSTMDBEQ R0!, {D8-D15}) ; * is executed, the floating-point context(FPSCR,S15-S0) is first saved into ; * the space reserved on the stack. In other words, the instruction ; * 'VSTMDBEQ R0!, {D8-D15}' will trigger the CPU to save 'FPSCR,S15-S0' first. ; * ; * The stack of the current running task is as follows: ; * ; * |<=== PUSH: Save the context of the current running task ; * | High addr--->| ; * --+-----------------------------------+-------------------------------------------+--- ; * | R4-R11,PRIMASK,EXC_RETURN,S16-S31 | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * | [ lazy stacking ]| ; * --+-----------------------------------+-------------------------------------------+--- ; * Stack pointer before entering exception--->| ; * |<--- cpu auto saved --->| ; * |<---PSP to R0 ; * |<---Top of the stack, save to g_stLosTask.pstRunTask->pStackPointer ; */ #if defined (__ARMVFP__) ; if FPU exist. TST R14, #0x10 ; if the task using the FPU context, push s16-s31. IT EQ VSTMDBEQ R0!, {D8-D15} STMFD R0!, {R14} ; save EXC_RETURN. #endif STMFD R0!, {R4-R12} ; save the core registers and PRIMASK. ;/** ; * R5,R8. ; */ LDR R5, =g_stLosTask MOV R8, #OS_TASK_STATUS_RUNNING ;/** ; * Save the stack pointer of the current running task to TCB. ; * (g_stLosTask.pstRunTask->pStackPointer = R0) ; */ LDR R6, [R5] STR R0, [R6] ;/** ; * Clear the RUNNING state of the current running task. ; * (g_stLosTask.pstRunTask->usTaskStatus &= ~OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R6, #4] BIC R7, R7, R8 STRH R7, [R6, #4] ;/** ; * Switch the current running task to the next running task. ; * (g_stLosTask.pstRunTask = g_stLosTask.pstNewTask) ; */ LDR R0, [R5, #4] STR R0, [R5] ;/** ; * Set the RUNNING state of the next running task. ; * (g_stLosTask.pstNewTask->usTaskStatus |= OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R0, #4] ORR R7, R7, R8 STRH R7, [R0, #4] ;/** ; * Restore the stack pointer of the next running task from TCB. ; * (R1 = g_stLosTask.pstNewTask->pStackPointer) ; */ LDR R1, [R0] ;/** ; * Restore the stack frame(R4-R11,[S16-S31]) of the next running task. ; * R12 restore the PRIMASK value of the next running task. ; * NOTE: After exiting the exception handler function, these registers ; * (PC,xPSR,R0-R3,R12,LR,[S0-S15,FPSCR,NO_NAME]) will be automatically ; * restored by the CPU from the stack of the next running task. ; * ; * 1. The stack of the next running task is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * --+-----------------------------------+-------------------------------------------+--- ; * | R4-R11,PRIMASK,EXC_RETURN,S16-S31 | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * --+-----------------------------------+-------------------------------------------+--- ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; * ; * 2. If the next running task is run for the first time, the stack is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+---------------------------------+--------------------------------+ ; * | R4-R11, PRIMASK, EXC_RETURN | R0-R3, R12, LR, PC, xPSR | ; * ----------+---------------------------------+--------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; */ LDMFD R1!, {R4-R12} ; restore the core registers and PRIMASK. #if defined (__ARMVFP__) ; if FPU exist. LDMFD R1!, {R14} ; restore EXC_RETURN. TST R14, #0x10 ; if the task using the FPU context, pop s16-s31. IT EQ VLDMIAEQ R1!, {D8-D15} #endif ;/** ; * Set the stack pointer of the next running task to PSP. ; */ MSR PSP, R1 ;/** ; * Restore the interruption state of the next running task. ; */ MSR PRIMASK, R12 BX LR END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m4/iar/los_hw_exc_iar.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2013-2015>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** PRESERVE8 SECTION .text:CODE(2) THUMB ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT NMI_Handler EXPORT HardFault_Handler EXPORT MemManage_Handler EXPORT BusFault_Handler EXPORT UsageFault_Handler EXPORT SVC_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT osExcHandleEntry IMPORT g_uwExcTbl IMPORT g_bTaskScheduled ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_EXC_CAUSE_NMI EQU 18 OS_EXC_CAUSE_HARDFAULT EQU 19 OS_EXC_CAUSE_MEMFAULT EQU 20 OS_EXC_CAUSE_BUSFAULT EQU 21 OS_EXC_CAUSE_USAGEFAULT EQU 22 OS_EXC_CAUSE_SVC EQU 23 HF_DEBUGEVT EQU 24 HF_VECTBL EQU 25 FLAG_ADDR_VALID EQU 0x10000 ; bit 16 FLAG_HWI_ACTIVE EQU 0x20000 ; bit 17 FLAG_NO_FLOAT EQU 0x10000000 ; bit 28 OS_NVIC_CFSR EQU 0xE000ED28 ; include BusFault/MemFault/UsageFault State Regeister OS_NVIC_HFSR EQU 0xE000ED2C ; HardFault State Regeister OS_NVIC_BFAR EQU 0xE000ED38 OS_NVIC_MMFAR EQU 0xE000ED34 OS_NVIC_ACT_BASE EQU 0xE000E300 OS_NVIC_SHCSRS EQU 0xE000ED24 OS_NVIC_SHCSR_MASK EQU 0xC00 ; SYSTICKACT and PENDSVACT ;**************************************************************************************** ; Function: ; VOID NMI_Handler(VOID); ; Description: ; NMI Handler. ;**************************************************************************************** NMI_Handler ;/** ; * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +------------------------------------------------------+------------------------+ ; * | 31-8 | 7-0 | ; * +------------------------------------------------------+------------------------+ ; * | --- | OS_EXC_CAUSE_NMI | ; * +------------------------------------------------------+------------------------+ ; * < R1 >: invalid ; */ MOV R0, #OS_EXC_CAUSE_NMI MOV R1, #0 B osExcDispatch ;**************************************************************************************** ; Function: ; VOID HardFault_Handler(VOID); ; Description: ; HardFault Handler. ;**************************************************************************************** HardFault_Handler ;/** ; * Check HardFault state register. ; * ; * HFSR: ; * +----------+--------+--------+--------+-------+ ; * | 31 | 30 | 29 - 2 | 1 | 0 | ; * +----------+--------+--------+--------+-------+ ; * | DEBUGEVT | FORCED | -- | VECTBL | -- | ; * +----------+--------+--------+--------+-------+ ; */ MOV R0, #OS_EXC_CAUSE_HARDFAULT LDR R2, =OS_NVIC_HFSR LDR R2, [R2] ;/** ; * Check whether HardFault are triggered by debugging events. ; * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +----------------------------------------+-------------+------------------------+ ; * | 31-16 | 15-8 | 7-0 | ; * +----------------------------------------+-------------+------------------------+ ; * | --- | HF_DEBUGEVT | OS_EXC_CAUSE_HARDFAULT | ; * +----------------------------------------+-------------+------------------------+ ; * < R1 >: invalid ; */ MOV R1, #HF_DEBUGEVT ORR R0, R0, R1, LSL #0x8 TST R2, #0x80000000 BNE osExcDispatch ; DEBUGEVT ;/** ; * Check whether HardFault is caused by the failure of the fetch vector. ; * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +----------------------------------------+-------------+------------------------+ ; * | 31-16 | 15-8 | 7-0 | ; * +----------------------------------------+-------------+------------------------+ ; * | --- | HF_VECTBL | OS_EXC_CAUSE_HARDFAULT | ; * +----------------------------------------+-------------+------------------------+ ; * < R1 >: invalid ; */ AND R0, R0, #0x000000FF MOV R1, #HF_VECTBL ORR R0, R0, R1, LSL #0x8 TST R2, #0x00000002 BNE osExcDispatch ; VECTBL ;/** ; * If it`s not DEBUGEVT and VECTBL, that is FORCED, then read the CFSR register to ; * check BusFault, MemFault and UsageFault. ; * R0: OS_EXC_CAUSE_HARDFAULT ; * ; * CFSR: ; * +----------------+--------+--------+ ; * | 31-16 | 15-8 | 7-0 | ; * +----------------+--------+--------+ ; * | UFSR | BFSR | MFSR | ; * +----------------+--------+--------+ ; */ AND R0, R0, #0x000000FF LDR R2, =OS_NVIC_CFSR LDR R2, [R2] TST R2, #0x8000 ; BFSR->BFARVALID BNE _HFBusFault ; BusFault TST R2, #0x80 ; MFSR->MMARVALID BNE _HFMemFault ; MemFault ;/** ; * BFARVALID and MMARVALID flag both invalid. ; * R12: 0 --- The error address is invalid. ; */ MOV R12, #0 B osHFExcCommonBMU ;/** ; * BFARVALID flag valid, read BFAR register. ; * R1 : BFAR value --- The address value of a bus error. ; * R12: The error address is valid. ; */ _HFBusFault LDR R1, =OS_NVIC_BFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID B osHFExcCommonBMU ;/** ; * MMARVALID flag valid, read MMFAR register. ; * R1 : MMFAR value --- The address value of memory management error. ; * R12: The error address is valid. ; */ _HFMemFault LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID ;/** ; * osHFExcCommonBMU: --- Get specific error status from table g_uwExcTbl, stored in R0. ; * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +-------------------+-----------------+------------------+------------------------+ ; * | 31-17 | 16 | 15-8 | 7-0 | ; * +-------------------+-----------------+------------------+------------------------+ ; * | --- | FLAG_ADDR_VALID | Error state code | OS_EXC_CAUSE_HARDFAULT | ; * | | or | in | | ; * | | 0(invalid) | table g_uwExcTbl | | ; * +-------------------+-----------------+------------------+------------------------+ ; * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, ; * else invalid. ; */ osHFExcCommonBMU CLZ R2, R2 LDR R3, =g_uwExcTbl ADD R3, R3, R2 LDRB R2, [R3] ORR R0, R0, R2, LSL #0x8 ORR R0, R0, R12 B osExcDispatch ;**************************************************************************************** ; Function: ; VOID SVC_Handler(VOID); ; Description: ; SVC Handler. ;**************************************************************************************** SVC_Handler TST LR, #0x4 ; EXC_RETURN[b2] --- PSP or MSP ITE EQ MRSEQ R0, MSP MRSNE R0, PSP LDR R1, [R0, #24] ; The PC value in the stack frame LDRB R0, [R1, #-2] ; R0: The number of SVC (0 - 255) MOV R1, #0 ;B osExcDispatch _SvcLoop B _SvcLoop ;**************************************************************************************** ; Function: ; VOID BusFault_Handler(VOID); ; Description: ; BusFault Handler. ;**************************************************************************************** BusFault_Handler LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_BUSFAULT TST R0, #0x8000 ; BFSR->BFARVALID BEQ _ExcBusNoADDR LDR R1, =OS_NVIC_BFAR LDR R1, [R1] ; R1: The value of BFAR MOV R12, #FLAG_ADDR_VALID ; R12: BusFault addr valid AND R0, R0, #0x3F00 ; R0: Reserved the b13-b8 of the BFSR B osExcCommonBMU _ExcBusNoADDR MOV R12, #0 ; R12: BusFault addr invalid AND R0, R0, #0x3F00 ; R0: Reserved the b13-b8 of the BFSR B osExcCommonBMU ;**************************************************************************************** ; Function: ; VOID MemManage_Handler(VOID); ; Description: ; MemManage Handler. ;**************************************************************************************** MemManage_Handler LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_MEMFAULT TST R0, #0x80 ; MFSR->MMARVALID BEQ _ExcMemNoADDR LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] ; R1: The value of MMFAR MOV R12, #FLAG_ADDR_VALID ; R12: MemFault addr valid AND R0, R0, #0x3B ; R0: Reserved the b5-b0 of the MFSR B osExcCommonBMU _ExcMemNoADDR MOV R12, #0 ; R12: MemFault addr invalid AND R0, R0, #0x3B ; R0: Reserved the b5-b0 of the MFSR B osExcCommonBMU ;**************************************************************************************** ; Function: ; VOID UsageFault_Handler(VOID); ; Description: ; UsageFault Handler. ;**************************************************************************************** UsageFault_Handler LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_USAGEFAULT MOV R1, #0x030F LSL R1, R1, #16 AND R0, R0, R1 ; R0: reserved UFSR MOV R12, #0 ; R12: Fault addr invalid ;/** ; * osExcCommonBMU: BusFault_Handler,MemManage_Handler and UsageFault_Handler share. ; * Get specific error status from table g_uwExcTbl, stored in R0. ; * Before executing osExcDispatch, the value of R0 is as follows. ; * < R0 >: ; * +-------------------+-----------------+------------------+------------------------+ ; * | 31-17 | 16 | 15-8 | 7-0 | ; * +-------------------+-----------------+------------------+------------------------+ ; * | --- | FLAG_ADDR_VALID | Error state code |OS_EXC_CAUSE_BUSFAULT or| ; * | | or | in |OS_EXC_CAUSE_MEMFAULT or| ; * | | 0(invalid) | table g_uwExcTbl |OS_EXC_CAUSE_USAGEFAULT | ; * +-------------------+-----------------+------------------+------------------------+ ; * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, ; * else invalid. ; */ osExcCommonBMU CLZ R0, R0 LDR R3, =g_uwExcTbl ADD R3, R3, R0 LDRB R0, [R3] LSL R0, R0, #0x8 ORR R0, R0, R2 ORR R0, R0, R12 ;**************************************************************************************** ; osExcDispatch: NMI_Handler, HardFault_Handler, SVC_Handler, BusFault_Handler, MemManage_Handler, ; UsageFault_Handler sharing. ;**************************************************************************************** ;/** ; * When executing osExcDispatch, R0, R1 will be used. ; * The possible values of R0 and R1 are as follows. ; * ; * < R0 >: ; * +----------------+-----------------+---------------------+------------------------+ ; * | 31-17 | 16 | 15-8 | 7-0 | ; * +----------------+-----------------+---------------------+------------------------+ ; * | | FLAG_ADDR_VALID | Error state code in | OS_EXC_CAUSE_HARDFAULT | ; * | --- | or | table g_uwExcTbl |or OS_EXC_CAUSE_MEMFAULT| ; * | | 0(invalid) | or HF_DEBUGEVT |or OS_EXC_CAUSE_BUSFAULT| ; * | | | or HF_VECTBL |or OS_EXC_CAUSE_NMI or | ; * | | | | OS_EXC_CAUSE_USAGEFAULT| ; * +----------------+-----------------+---------------------+------------------------+ ; * b17: FLAG_HWI_ACTIVE ; * b28: FLAG_NO_FLOAT ; * NOTE: b17 and b28 will be set later. ; * ; * < R1 >: ; * If the bit16 of R0 is 1, then R1 is the value of BFAR or MMFAR, otherwise the ; * value in R1 is invalid. ; * ; */ osExcDispatch LDR R2, =OS_NVIC_ACT_BASE MOV R12, #8 ; #8: externel interrupt active check loop counter(#0 - #239) _hwiActiveCheck LDR R3, [R2] ; R3 store the value of externel interrupt active status CMP R3, #0 BEQ _hwiActiveCheckNext ;/** ; * Exception occured in external interrupt. ; */ ORR R0, R0, #FLAG_HWI_ACTIVE ; R0[b17] = 1, externel interrupt active valid &&&&&&&&&& RBIT R2, R3 ; bit reversal CLZ R2, R2 RSB R12, R12, #8 ; R12 = 8 - R12 ADD R2, R2, R12, LSL #5 ; R2: external interrupt number as uwPid ;/** ; * Interrupts and initialization phase always use MSP. ; */ _ExcInMSP TST LR, #0x10 ; EXC_RETURN[b4] --- FPU(0) or without FPU(1) BNE _NoFloatInMsp ;/** ; * Before executing instruction 'B _handleEntry', MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | S16-S31,R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * +--------------------------------------------------------------------------------+--------- ; * |<---R13 Initial R13--->|<--- #104 --->|<---SAVED_SP ; * | (CPU auto saved) | ; * ; */ ADD R3, R13, #104 ; #104: skip [R0-xPSR,D0-D7,FPSCR,NO_NAME] PUSH {R3} ; push [SAVED_SP]: MSP+104 = Stack pointer in MSP before entering the exception MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK to MSP VPUSH {D8-D15} ; push D8-D15 to MSP B _handleEntry ;/** ; * Before executing instruction 'B _handleEntry', MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR | ; * +--------------------------------------------------------------------------------+--------- ; * R13--->| Initial R13--->|<--- #32 --->|<---SAVED_SP ; * | (CPU auto saved) | ; * ; */ _NoFloatInMsp ADD R3, R13, #32 ; #32: skip [R0-R3,R12,LR,PC,xPSR] PUSH {R3} ; push [SAVED_SP]: MSP+32 = Stack pointer in MSP before entering the exception MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK to MSP ORR R0, R0, #FLAG_NO_FLOAT ; R0[b28] = 1, no FPU &&&&&&&&&& B _handleEntry _hwiActiveCheckNext ADD R2, R2, #4 ; next NVIC ACT ADDR SUBS R12, R12, #1 BNE _hwiActiveCheck ;/** ; * Not in externel interrupt, check whether it is SysTick or PendSV. ; */ LDR R2, =OS_NVIC_SHCSRS LDRH R2,[R2] LDR R3,=OS_NVIC_SHCSR_MASK AND R2, R2, R3 CMP R2, #0 BNE _ExcInMSP ; SysTick or PendSV active ;/** ; * Check whether an exception occurs during the initialization phase. ; * If g_bTaskScheduled == 0, it is in the initialization phase. ; */ LDR R2, =g_bTaskScheduled LDR R2, [R2] TST R2, #1 BEQ _ExcInMSP ; initialization phase use MSP ;/** ; * Exception occured in Task. ; */ TST LR, #0x10 BNE _NoFloatInPsp ;/** ; * Before executing _handleEntry, MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | S16-S31,R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * +--------------------------------------------------------------------------------+--------- ; * |<---R13 |<--- #104 --->|<---Initial R13 ; * | (copied from PSP) | ; * R2(no use)--->| ; * ; * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME. ; */ MOV R2, R13 SUB R2, R2, #8 ; #8: reserved for [FPSCR,NO_NAME] SUB R13, #104 ; #104: MSP reserved, used to store stack frame in PSP MRS R3, PSP ADD R12, R3, #104 ; PSP+104 = Stack pointer of the task before entering the exception PUSH {R12} ; push task SP to MSP MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK of the current running task to MSP VPUSH {D8-D15} ; push D8-D15 of the currnent running task to MSP ;/* Copy stack frame from the stack of the current running task to MSP */ LDMFD R3!, {R4-R11} ; restore stack frame[R0-xPSR] of PSP to R4-R11 VLDMIA R3!, {D8-D15} ; restore stack frame[D0-D7] of PSP to D8-D15 VSTMDB R2!, {D8-D15} ; save stack frame[D0-D7] to MSP STMFD R2!, {R4-R11} ; save stack frame[R0-xPSR] to MSP LDMFD R3, {R4-R5} ; restore stack frame[FPSCR,NO_NAME] to R4-R5 ADD R2, R2, #104 ; skip stack frame STMFD R2, {R4-R5} ; save stack frame[FPSCR,NO_NAME] to MSP B _handleEntry ;/** ; * Before executing _handleEntry, MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR | ; * +--------------------------------------------------------------------------------+--------- ; * R13--->| |<--- #32 --->|<---Initial R13 ; * | (copied from PSP) | ; * |<---R2(no use) ; * ; * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR. ; */ _NoFloatInPsp MOV R2, R13 SUB R13, #32 ; #32: MSP reserved, used to store stack frame in PSP MRS R3, PSP ADD R12, R3, #32 ; PSP+32 = Stack pointer of the task before entering the exception PUSH {R12} ; push task SP to MSP MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK of the current running task to MSP ;/* Copy stack frame from the stack of the current running task to MSP */ LDMFD R3, {R4-R11} ; restore stack frame of PSP to R4-R11 STMFD R2!, {R4-R11} ; save stack frame to MSP ORR R0, R0, #FLAG_NO_FLOAT ; R0[b28] = 1, no FPU &&&&&&&&&& ;/** ; * _handleEntry: Call osExcHandleEntry ; * param1: R0 --- b28: FLAG_NO_FLOAT. ; * b17: FLAG_HWI_ACTIVE. ; * b16: FLAG_ADDR_VALID. ; * b15-b8: Error state code in table g_uwExcTbl or HF_DEBUGEVT or HF_VECTBL. ; * b7-b0: OS_EXC_CAUSE_HARDFAULT or OS_EXC_CAUSE_NMI or OS_EXC_CAUSE_MEMFAULT ; * or OS_EXC_CAUSE_BUSFAULT or OS_EXC_CAUSE_USAGEFAULT. ; * param2: R1 --- The value of BFAR or MMFAR if R0[b16] = 1, otherwise invalid. ; * param3: R2 --- external interrupt number(0-239) if R0[b17] = 1, otherwise invalid. ; * param4: R3 --- Point to the top of the stack(R4 or S16) that the exception stack frame in MSP. ; */ _handleEntry MOV R3, R13 CPSID I CPSID F B osExcHandleEntry NOP END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m4/keil/los_dispatch_keil.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2016-2018>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT LOS_IntLock EXPORT LOS_IntUnLock EXPORT LOS_IntRestore EXPORT LOS_StartToRun EXPORT osTaskSchedule EXPORT PendSV_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT g_stLosTask IMPORT g_pfnTskSwitchHook IMPORT g_bTaskScheduled ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt Control and State Register. OS_NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception. OS_NVIC_SYSPRI2 EQU 0xE000ED20 ; System Handler Priority Register 2. OS_NVIC_PENDSV_SYSTICK_PRI EQU 0xFFFF0000 ; SysTick + PendSV priority level (lowest). OS_TASK_STATUS_RUNNING EQU 0x0010 ; Task Status Flag (RUNNING). ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** AREA |.text|, CODE, READONLY THUMB REQUIRE8 PRESERVE8 ;**************************************************************************************** ; Function: ; VOID LOS_StartToRun(VOID); ; Description: ; Start the first task, which is the highest priority task in the priority queue. ; Other tasks are started by task scheduling. ;**************************************************************************************** LOS_StartToRun CPSID I ;/** ; * Set PendSV and SysTick prority to the lowest. ; * read ---> modify ---> write-back. ; */ LDR R0, =OS_NVIC_SYSPRI2 LDR R1, =OS_NVIC_PENDSV_SYSTICK_PRI LDR R2, [R0] ORR R1, R1, R2 STR R1, [R0] ;/** ; * Set g_bTaskScheduled = 1. ; */ LDR R0, =g_bTaskScheduled MOV R1, #1 STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask = g_stLosTask.pstNewTask. ; */ LDR R0, =g_stLosTask LDR R1, [R0, #4] STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask->usTaskStatus |= OS_TASK_STATUS_RUNNING. ; */ LDR R1, [R0] LDRH R2, [R1, #4] MOV R3, #OS_TASK_STATUS_RUNNING ORR R2, R2, R3 STRH R2, [R1, #4] ;/** ; * Restore the default stack frame(R0-R3,R12,LR,PC,xPSR) of g_stLosTask.pstRunTask to R0-R7. ; * [Initial EXC_RETURN ignore,] return by setting the CONTROL register. ; * ; * The initial stack of the current running task is as follows: ; * ; * POP: Restore the context of the current running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+---------------------------------+--------------------------------+ ; * | R4-R11, PRIMASK, EXC_RETURN | R0-R3, R12, LR, PC, xPSR | ; * ----------+---------------------------------+--------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstRunTask->pStackPointer ; * |<--- skip --->|<--- copy to R0-R7 --->| ; * R12 to PSP--->| ; * Stack pointer after LOS_StartToRun--->| ; */ LDR R12, [R1] ADD R12, R12, #36 ; skip R4-R11, PRIMASK. IF {FPU} != "SoftVFP" ADD R12, R12, #4 ; if FPU exist, skip EXC_RETURN. ENDIF LDMFD R12!, {R0-R7} ;/** ; * Set the stack pointer of g_stLosTask.pstRunTask to PSP. ; */ MSR PSP, R12 ;/** ; * Set the CONTROL register, after schedule start, privilege level and stack = PSP. ; */ MOV R12, #2 MSR CONTROL, R12 ;/** ; * Enable interrupt. (The default PRIMASK value is 0, so enable directly) ; */ MOV LR, R5 CPSIE I ;/** ; * Jump directly to the default PC of g_stLosTask.pstRunTask, the field information ; * of the main function will be destroyed and will never be returned. ; */ BX R6 ;**************************************************************************************** ; Function: ; UINTPTR LOS_IntLock(VOID); ; Description: ; Disable all interrupts except Reset,NMI and HardFault. ; The value of currnet interruption state will be returned to the caller to save. ; ; Function: ; VOID LOS_IntRestore(UINTPTR uvIntSave); ; Description: ; Restore the locked interruption of LOS_IntLock. ; The caller must pass in the value of interruption state previously saved. ;**************************************************************************************** LOS_IntLock MRS R0, PRIMASK CPSID I BX LR LOS_IntUnLock MRS R0, PRIMASK CPSIE I BX LR LOS_IntRestore MSR PRIMASK, R0 BX LR ;**************************************************************************************** ; Function: ; VOID osTaskSchedule(VOID); ; Description: ; Start the task swtich process by software trigger PendSV interrupt. ;**************************************************************************************** osTaskSchedule LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] BX LR ;**************************************************************************************** ; Function: ; VOID PendSV_Handler(VOID); ; Description: ; PendSV interrupt handler, switch the context of the task. ; First: Save the context of the current running task(g_stLosTask.pstRunTask) ; to its own stack. ; Second: Restore the context of the next running task(g_stLosTask.pstNewTask) ; from its own stack. ;**************************************************************************************** PendSV_Handler ;/** ; * R12: Save the interruption state of the current running task. ; * Disable all interrupts except Reset,NMI and HardFault ; */ MRS R12, PRIMASK CPSID I ;/** ; * Call task switch hook. ; */ LDR R2, =g_pfnTskSwitchHook LDR R2, [R2] CBZ R2, TaskSwitch PUSH {R12, LR} BLX R2 POP {R12, LR} TaskSwitch ;/** ; * R0 = now stack pointer of the current running task. ; */ MRS R0, PSP ;/** ; * Save the stack frame([S16-S31],R4-R11) of the current running task. ; * R12 save the PRIMASK value of the current running task. ; * NOTE: 1. Before entering the exception handler function, these registers ; * ([NO_NAME,FPSCR,S15-S0],xPSR,PC,LR,R12,R3-R0) have been automatically ; * saved by the CPU in the stack of the current running task. ; * 2. If lazy stacking is enabled, space is reserved on the stack for ; * the floating-point context(FPSCR,S15-S0), but the floating-point state ; * is not saved. when the floating-point instruction(VSTMDBEQ R0!, {D8-D15}) ; * is executed, the floating-point context(FPSCR,S15-S0) is first saved into ; * the space reserved on the stack. In other words, the instruction ; * 'VSTMDBEQ R0!, {D8-D15}' will trigger the CPU to save 'FPSCR,S15-S0' first. ; * ; * The stack of the current running task is as follows: ; * ; * |<=== PUSH: Save the context of the current running task ; * | High addr--->| ; * --+-----------------------------------+-------------------------------------------+--- ; * | R4-R11,PRIMASK,EXC_RETURN,S16-S31 | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * | [ lazy stacking ]| ; * --+-----------------------------------+-------------------------------------------+--- ; * Stack pointer before entering exception--->| ; * |<--- cpu auto saved --->| ; * |<---PSP to R0 ; * |<---Top of the stack, save to g_stLosTask.pstRunTask->pStackPointer ; */ IF {FPU} != "SoftVFP" ; if FPU exist. TST R14, #0x10 ; if the task using the FPU context, push s16-s31. IT EQ VSTMDBEQ R0!, {D8-D15} STMFD R0!, {R14} ; save EXC_RETURN. ENDIF STMFD R0!, {R4-R12} ; save the core registers and PRIMASK. ;/** ; * R5,R8. ; */ LDR R5, =g_stLosTask MOV R8, #OS_TASK_STATUS_RUNNING ;/** ; * Save the stack pointer of the current running task to TCB. ; * (g_stLosTask.pstRunTask->pStackPointer = R0) ; */ LDR R6, [R5] STR R0, [R6] ;/** ; * Clear the RUNNING state of the current running task. ; * (g_stLosTask.pstRunTask->usTaskStatus &= ~OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R6, #4] BIC R7, R7, R8 STRH R7, [R6, #4] ;/** ; * Switch the current running task to the next running task. ; * (g_stLosTask.pstRunTask = g_stLosTask.pstNewTask) ; */ LDR R0, [R5, #4] STR R0, [R5] ;/** ; * Set the RUNNING state of the next running task. ; * (g_stLosTask.pstNewTask->usTaskStatus |= OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R0, #4] ORR R7, R7, R8 STRH R7, [R0, #4] ;/** ; * Restore the stack pointer of the next running task from TCB. ; * (R1 = g_stLosTask.pstNewTask->pStackPointer) ; */ LDR R1, [R0] ;/** ; * Restore the stack frame(R4-R11,[S16-S31]) of the next running task. ; * R12 restore the PRIMASK value of the next running task. ; * NOTE: After exiting the exception handler function, these registers ; * (PC,xPSR,R0-R3,R12,LR,[S0-S15,FPSCR,NO_NAME]) will be automatically ; * restored by the CPU from the stack of the next running task. ; * ; * 1. The stack of the next running task is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * --+-----------------------------------+-------------------------------------------+--- ; * | R4-R11,PRIMASK,EXC_RETURN,S16-S31 | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * --+-----------------------------------+-------------------------------------------+--- ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; * ; * 2. If the next running task is run for the first time, the stack is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+---------------------------------+--------------------------------+ ; * | R4-R11, PRIMASK, EXC_RETURN | R0-R3, R12, LR, PC, xPSR | ; * ----------+---------------------------------+--------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; */ LDMFD R1!, {R4-R12} ; restore the core registers and PRIMASK. IF {FPU} != "SoftVFP" ; if FPU exist. LDMFD R1!, {R14} ; restore EXC_RETURN. TST R14, #0x10 ; if the task using the FPU context, pop s16-s31. IT EQ VLDMIAEQ R1!, {D8-D15} ENDIF ;/** ; * Set the stack pointer of the next running task to PSP. ; */ MSR PSP, R1 ;/** ; * Restore the interruption state of the next running task. ; */ MSR PRIMASK, R12 BX LR ALIGN END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m4/keil/los_hw_exc_keil.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2013-2015>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** PRESERVE8 AREA |.text|, CODE, READONLY THUMB ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT NMI_Handler EXPORT HardFault_Handler EXPORT MemManage_Handler EXPORT BusFault_Handler EXPORT UsageFault_Handler EXPORT SVC_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT osExcHandleEntry IMPORT g_uwExcTbl IMPORT g_bTaskScheduled ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_EXC_CAUSE_NMI EQU 18 OS_EXC_CAUSE_HARDFAULT EQU 19 OS_EXC_CAUSE_MEMFAULT EQU 20 OS_EXC_CAUSE_BUSFAULT EQU 21 OS_EXC_CAUSE_USAGEFAULT EQU 22 OS_EXC_CAUSE_SVC EQU 23 HF_DEBUGEVT EQU 24 HF_VECTBL EQU 25 FLAG_ADDR_VALID EQU 0x10000 ; bit 16 FLAG_HWI_ACTIVE EQU 0x20000 ; bit 17 FLAG_NO_FLOAT EQU 0x10000000 ; bit 28 OS_NVIC_CFSR EQU 0xE000ED28 ; include BusFault/MemFault/UsageFault State Regeister OS_NVIC_HFSR EQU 0xE000ED2C ; HardFault State Regeister OS_NVIC_BFAR EQU 0xE000ED38 OS_NVIC_MMFAR EQU 0xE000ED34 OS_NVIC_ACT_BASE EQU 0xE000E300 OS_NVIC_SHCSRS EQU 0xE000ED24 OS_NVIC_SHCSR_MASK EQU 0xC00 ; SYSTICKACT and PENDSVACT ;**************************************************************************************** ; Function: ; VOID NMI_Handler(VOID); ; Description: ; NMI Handler. ;**************************************************************************************** NMI_Handler ;/** ; * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +------------------------------------------------------+------------------------+ ; * | 31-8 | 7-0 | ; * +------------------------------------------------------+------------------------+ ; * | --- | OS_EXC_CAUSE_NMI | ; * +------------------------------------------------------+------------------------+ ; * < R1 >: invalid ; */ MOV R0, #OS_EXC_CAUSE_NMI MOV R1, #0 B osExcDispatch ;**************************************************************************************** ; Function: ; VOID HardFault_Handler(VOID); ; Description: ; HardFault Handler. ;**************************************************************************************** HardFault_Handler ;/** ; * Check HardFault state register. ; * ; * HFSR: ; * +----------+--------+--------+--------+-------+ ; * | 31 | 30 | 29 - 2 | 1 | 0 | ; * +----------+--------+--------+--------+-------+ ; * | DEBUGEVT | FORCED | -- | VECTBL | -- | ; * +----------+--------+--------+--------+-------+ ; */ MOV R0, #OS_EXC_CAUSE_HARDFAULT LDR R2, =OS_NVIC_HFSR LDR R2, [R2] ;/** ; * Check whether HardFault are triggered by debugging events. ; * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +----------------------------------------+-------------+------------------------+ ; * | 31-16 | 15-8 | 7-0 | ; * +----------------------------------------+-------------+------------------------+ ; * | --- | HF_DEBUGEVT | OS_EXC_CAUSE_HARDFAULT | ; * +----------------------------------------+-------------+------------------------+ ; * < R1 >: invalid ; */ MOV R1, #HF_DEBUGEVT ORR R0, R0, R1, LSL #0x8 TST R2, #0x80000000 BNE osExcDispatch ; DEBUGEVT ;/** ; * Check whether HardFault is caused by the failure of the fetch vector. ; * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +----------------------------------------+-------------+------------------------+ ; * | 31-16 | 15-8 | 7-0 | ; * +----------------------------------------+-------------+------------------------+ ; * | --- | HF_VECTBL | OS_EXC_CAUSE_HARDFAULT | ; * +----------------------------------------+-------------+------------------------+ ; * < R1 >: invalid ; */ AND R0, R0, #0x000000FF MOV R1, #HF_VECTBL ORR R0, R0, R1, LSL #0x8 TST R2, #0x00000002 BNE osExcDispatch ; VECTBL ;/** ; * If it`s not DEBUGEVT and VECTBL, that is FORCED, then read the CFSR register to ; * check BusFault, MemFault and UsageFault. ; * R0: OS_EXC_CAUSE_HARDFAULT ; * ; * CFSR: ; * +----------------+--------+--------+ ; * | 31-16 | 15-8 | 7-0 | ; * +----------------+--------+--------+ ; * | UFSR | BFSR | MFSR | ; * +----------------+--------+--------+ ; */ AND R0, R0, #0x000000FF LDR R2, =OS_NVIC_CFSR LDR R2, [R2] TST R2, #0x8000 ; BFSR->BFARVALID BNE _HFBusFault ; BusFault TST R2, #0x80 ; MFSR->MMARVALID BNE _HFMemFault ; MemFault ;/** ; * BFARVALID and MMARVALID flag both invalid. ; * R12: 0 --- The error address is invalid. ; */ MOV R12, #0 B osHFExcCommonBMU ;/** ; * BFARVALID flag valid, read BFAR register. ; * R1 : BFAR value --- The address value of a bus error. ; * R12: The error address is valid. ; */ _HFBusFault LDR R1, =OS_NVIC_BFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID B osHFExcCommonBMU ;/** ; * MMARVALID flag valid, read MMFAR register. ; * R1 : MMFAR value --- The address value of memory management error. ; * R12: The error address is valid. ; */ _HFMemFault LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID ;/** ; * osHFExcCommonBMU: --- Get specific error status from table g_uwExcTbl, stored in R0. ; * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +-------------------+-----------------+------------------+------------------------+ ; * | 31-17 | 16 | 15-8 | 7-0 | ; * +-------------------+-----------------+------------------+------------------------+ ; * | --- | FLAG_ADDR_VALID | Error state code | OS_EXC_CAUSE_HARDFAULT | ; * | | or | in | | ; * | | 0(invalid) | table g_uwExcTbl | | ; * +-------------------+-----------------+------------------+------------------------+ ; * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, ; * else invalid. ; */ osHFExcCommonBMU CLZ R2, R2 LDR R3, =g_uwExcTbl ADD R3, R3, R2 LDRB R2, [R3] ORR R0, R0, R2, LSL #0x8 ORR R0, R0, R12 B osExcDispatch ;**************************************************************************************** ; Function: ; VOID SVC_Handler(VOID); ; Description: ; SVC Handler. ;**************************************************************************************** SVC_Handler TST LR, #0x4 ; EXC_RETURN[b2] --- PSP or MSP ITE EQ MRSEQ R0, MSP MRSNE R0, PSP LDR R1, [R0, #24] ; The PC value in the stack frame LDRB R0, [R1, #-2] ; R0: The number of SVC (0 - 255) MOV R1, #0 ;B osExcDispatch _SvcLoop B _SvcLoop ;**************************************************************************************** ; Function: ; VOID BusFault_Handler(VOID); ; Description: ; BusFault Handler. ;**************************************************************************************** BusFault_Handler LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_BUSFAULT TST R0, #0x8000 ; BFSR->BFARVALID BEQ _ExcBusNoADDR LDR R1, =OS_NVIC_BFAR LDR R1, [R1] ; R1: The value of BFAR MOV R12, #FLAG_ADDR_VALID ; R12: BusFault addr valid AND R0, R0, #0x3F00 ; R0: Reserved the b13-b8 of the BFSR B osExcCommonBMU _ExcBusNoADDR MOV R12, #0 ; R12: BusFault addr invalid AND R0, R0, #0x3F00 ; R0: Reserved the b13-b8 of the BFSR B osExcCommonBMU ;**************************************************************************************** ; Function: ; VOID MemManage_Handler(VOID); ; Description: ; MemManage Handler. ;**************************************************************************************** MemManage_Handler LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_MEMFAULT TST R0, #0x80 ; MFSR->MMARVALID BEQ _ExcMemNoADDR LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] ; R1: The value of MMFAR MOV R12, #FLAG_ADDR_VALID ; R12: MemFault addr valid AND R0, R0, #0x3B ; R0: Reserved the b5-b0 of the MFSR B osExcCommonBMU _ExcMemNoADDR MOV R12, #0 ; R12: MemFault addr invalid AND R0, R0, #0x3B ; R0: Reserved the b5-b0 of the MFSR B osExcCommonBMU ;**************************************************************************************** ; Function: ; VOID UsageFault_Handler(VOID); ; Description: ; UsageFault Handler. ;**************************************************************************************** UsageFault_Handler LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_USAGEFAULT MOV R1, #0x030F LSL R1, R1, #16 AND R0, R0, R1 ; R0: reserved UFSR MOV R12, #0 ; R12: Fault addr invalid ;/** ; * osExcCommonBMU: BusFault_Handler,MemManage_Handler and UsageFault_Handler share. ; * Get specific error status from table g_uwExcTbl, stored in R0. ; * Before executing osExcDispatch, the value of R0 is as follows. ; * < R0 >: ; * +-------------------+-----------------+------------------+------------------------+ ; * | 31-17 | 16 | 15-8 | 7-0 | ; * +-------------------+-----------------+------------------+------------------------+ ; * | --- | FLAG_ADDR_VALID | Error state code |OS_EXC_CAUSE_BUSFAULT or| ; * | | or | in |OS_EXC_CAUSE_MEMFAULT or| ; * | | 0(invalid) | table g_uwExcTbl |OS_EXC_CAUSE_USAGEFAULT | ; * +-------------------+-----------------+------------------+------------------------+ ; * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, ; * else invalid. ; */ osExcCommonBMU CLZ R0, R0 LDR R3, =g_uwExcTbl ADD R3, R3, R0 LDRB R0, [R3] LSL R0, R0, #0x8 ORR R0, R0, R2 ORR R0, R0, R12 ;**************************************************************************************** ; osExcDispatch: NMI_Handler, HardFault_Handler, SVC_Handler, BusFault_Handler, MemManage_Handler, ; UsageFault_Handler sharing. ;**************************************************************************************** ;/** ; * When executing osExcDispatch, R0, R1 will be used. ; * The possible values of R0 and R1 are as follows. ; * ; * < R0 >: ; * +----------------+-----------------+---------------------+------------------------+ ; * | 31-17 | 16 | 15-8 | 7-0 | ; * +----------------+-----------------+---------------------+------------------------+ ; * | | FLAG_ADDR_VALID | Error state code in | OS_EXC_CAUSE_HARDFAULT | ; * | --- | or | table g_uwExcTbl |or OS_EXC_CAUSE_MEMFAULT| ; * | | 0(invalid) | or HF_DEBUGEVT |or OS_EXC_CAUSE_BUSFAULT| ; * | | | or HF_VECTBL |or OS_EXC_CAUSE_NMI or | ; * | | | | OS_EXC_CAUSE_USAGEFAULT| ; * +----------------+-----------------+---------------------+------------------------+ ; * b17: FLAG_HWI_ACTIVE ; * b28: FLAG_NO_FLOAT ; * NOTE: b17 and b28 will be set later. ; * ; * < R1 >: ; * If the bit16 of R0 is 1, then R1 is the value of BFAR or MMFAR, otherwise the ; * value in R1 is invalid. ; * ; */ osExcDispatch LDR R2, =OS_NVIC_ACT_BASE MOV R12, #8 ; #8: externel interrupt active check loop counter(#0 - #239) _hwiActiveCheck LDR R3, [R2] ; R3 store the value of externel interrupt active status CMP R3, #0 BEQ _hwiActiveCheckNext ;/** ; * Exception occured in external interrupt. ; */ ORR R0, R0, #FLAG_HWI_ACTIVE ; R0[b17] = 1, externel interrupt active valid &&&&&&&&&& RBIT R2, R3 ; bit reversal CLZ R2, R2 RSB R12, R12, #8 ; R12 = 8 - R12 ADD R2, R2, R12, LSL #5 ; R2: external interrupt number as uwPid ;/** ; * Interrupts and initialization phase always use MSP. ; */ _ExcInMSP TST LR, #0x10 ; EXC_RETURN[b4] --- FPU(0) or without FPU(1) BNE _NoFloatInMsp ;/** ; * Before executing instruction 'B _handleEntry', MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | S16-S31,R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * +--------------------------------------------------------------------------------+--------- ; * |<---R13 Initial R13--->|<--- #104 --->|<---SAVED_SP ; * | (CPU auto saved) | ; * ; */ ADD R3, R13, #104 ; #104: skip [R0-xPSR,D0-D7,FPSCR,NO_NAME] PUSH {R3} ; push [SAVED_SP]: MSP+104 = Stack pointer in MSP before entering the exception MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK to MSP VPUSH {D8-D15} ; push D8-D15 to MSP B _handleEntry ;/** ; * Before executing instruction 'B _handleEntry', MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR | ; * +--------------------------------------------------------------------------------+--------- ; * R13--->| Initial R13--->|<--- #32 --->|<---SAVED_SP ; * | (CPU auto saved) | ; * ; */ _NoFloatInMsp ADD R3, R13, #32 ; #32: skip [R0-R3,R12,LR,PC,xPSR] PUSH {R3} ; push [SAVED_SP]: MSP+32 = Stack pointer in MSP before entering the exception MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK to MSP ORR R0, R0, #FLAG_NO_FLOAT ; R0[b28] = 1, no FPU &&&&&&&&&& B _handleEntry _hwiActiveCheckNext ADD R2, R2, #4 ; next NVIC ACT ADDR SUBS R12, R12, #1 BNE _hwiActiveCheck ;/** ; * Not in externel interrupt, check whether it is SysTick or PendSV. ; */ LDR R2, =OS_NVIC_SHCSRS LDRH R2,[R2] LDR R3,=OS_NVIC_SHCSR_MASK AND R2, R2, R3 CMP R2, #0 BNE _ExcInMSP ; SysTick or PendSV active ;/** ; * Check whether an exception occurs during the initialization phase. ; * If g_bTaskScheduled == 0, it is in the initialization phase. ; */ LDR R2, =g_bTaskScheduled LDR R2, [R2] TST R2, #1 BEQ _ExcInMSP ; initialization phase use MSP ;/** ; * Exception occured in Task. ; */ TST LR, #0x10 BNE _NoFloatInPsp ;/** ; * Before executing _handleEntry, MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | S16-S31,R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * +--------------------------------------------------------------------------------+--------- ; * |<---R13 |<--- #104 --->|<---Initial R13 ; * | (copied from PSP) | ; * R2(no use)--->| ; * ; * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME. ; */ MOV R2, R13 SUB R2, R2, #8 ; #8: reserved for [FPSCR,NO_NAME] SUB R13, #104 ; #104: MSP reserved, used to store stack frame in PSP MRS R3, PSP ADD R12, R3, #104 ; PSP+104 = Stack pointer of the task before entering the exception PUSH {R12} ; push task SP to MSP MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK of the current running task to MSP VPUSH {D8-D15} ; push D8-D15 of the currnent running task to MSP ;/* Copy stack frame from the stack of the current running task to MSP */ LDMFD R3!, {R4-R11} ; restore stack frame[R0-xPSR] of PSP to R4-R11 VLDMIA R3!, {D8-D15} ; restore stack frame[D0-D7] of PSP to D8-D15 VSTMDB R2!, {D8-D15} ; save stack frame[D0-D7] to MSP STMFD R2!, {R4-R11} ; save stack frame[R0-xPSR] to MSP LDMFD R3, {R4-R5} ; restore stack frame[FPSCR,NO_NAME] to R4-R5 ADD R2, R2, #104 ; skip stack frame STMFD R2, {R4-R5} ; save stack frame[FPSCR,NO_NAME] to MSP B _handleEntry ;/** ; * Before executing _handleEntry, MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR | ; * +--------------------------------------------------------------------------------+--------- ; * R13--->| |<--- #32 --->|<---Initial R13 ; * | (copied from PSP) | ; * |<---R2(no use) ; * ; * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR. ; */ _NoFloatInPsp MOV R2, R13 SUB R13, #32 ; #32: MSP reserved, used to store stack frame in PSP MRS R3, PSP ADD R12, R3, #32 ; PSP+32 = Stack pointer of the task before entering the exception PUSH {R12} ; push task SP to MSP MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK of the current running task to MSP ;/* Copy stack frame from the stack of the current running task to MSP */ LDMFD R3, {R4-R11} ; restore stack frame of PSP to R4-R11 STMFD R2!, {R4-R11} ; save stack frame to MSP ORR R0, R0, #FLAG_NO_FLOAT ; R0[b28] = 1, no FPU &&&&&&&&&& ;/** ; * _handleEntry: Call osExcHandleEntry ; * param1: R0 --- b28: FLAG_NO_FLOAT. ; * b17: FLAG_HWI_ACTIVE. ; * b16: FLAG_ADDR_VALID. ; * b15-b8: Error state code in table g_uwExcTbl or HF_DEBUGEVT or HF_VECTBL. ; * b7-b0: OS_EXC_CAUSE_HARDFAULT or OS_EXC_CAUSE_NMI or OS_EXC_CAUSE_MEMFAULT ; * or OS_EXC_CAUSE_BUSFAULT or OS_EXC_CAUSE_USAGEFAULT. ; * param2: R1 --- The value of BFAR or MMFAR if R0[b16] = 1, otherwise invalid. ; * param3: R2 --- external interrupt number(0-239) if R0[b17] = 1, otherwise invalid. ; * param4: R3 --- Point to the top of the stack(R4 or S16) that the exception stack frame in MSP. ; */ _handleEntry MOV R3, R13 CPSID I CPSID F B osExcHandleEntry NOP ALIGN END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m4/los_exc.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "los_exc.inc" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cpluscplus */ #endif /* __cpluscplus */ #if (LOSCFG_PLATFORM_EXC == YES) UINT32 g_uwCurNestCount = 0; EXC_INFO_S m_stExcInfo; /* * CFSR register, include UFSR,BFSR and MFSR. * * +----------------------------------------------------------------------------------+ * | UFSR | * |-----------+-----------+-----------+-------+------+-------+----------+------------| * | 31 - 26 | 25 | 24 | 23-20 | 19 | 18 | 17 | 16 | * |-----------+-----------+-----------+-------+------+-------+----------+------------| * | --- | DIVBYZERO | UNALIGNED | --- | NOCP | INVPC | INVSTATE | UNDEFINSTR | * +----------------------------------------------------------------------------------+ * * +----------------------------------------------------------------------------------+ * | BFSR | * |-----------+-----+--------+--------+----------+-------------+-----------+---------| * | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | * |-----------+-----+--------+--------+----------+-------------+-----------+---------| * | BFARVALID | --- | LSPERR | STKERR | UNSTKERR | IMPRECISERR | PRECISERR | IBUSERR | * +----------------------------------------------------------------------------------+ * * +----------------------------------------------------------------------------------+ * | MFSR | * |-----------+-------+---------+---------+-----------+-------+----------+-----------| * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | * |-----------+-------+---------+---------+-----------+-------+----------+-----------| * | MMARVALID | --- | MLSPERR | MSTKERR | MUNSTKERR | --- | DACCVIOL | ICACCVIOL | * +----------------------------------------------------------------------------------+ */ UINT8 g_uwExcTbl[32] = { 0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED, 0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR, 0, 0, OS_EXC_BF_LSPERR, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR, 0, 0, OS_EXC_MF_MLSPERR, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL }; #if (LOSCFG_SAVE_EXC_INFO == YES) VOID *m_puwExcContent; UINT32 g_uwArraySize = 0; EXC_INFO_ARRAY_S m_stExcArray[OS_EXC_TYPE_MAX - 1]; static VOID osExcSave2DDR(VOID); #endif extern VOID LOS_Reboot(VOID); /***************************************************************************** Function : osExcInfoDisplay Description : EXC info display Input : pstExc --- Pointer to the EXC data Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osExcInfoDisplay(EXC_INFO_S *pstExc) { PRINT_ERR("Phase = 0x%x\n", pstExc->usPhase); PRINT_ERR("Type = 0x%x\n", pstExc->usType); PRINT_ERR("FaultAddr = 0x%x\n", pstExc->uwFaultAddr); PRINT_ERR("ThrdPid = 0x%x\n", pstExc->uwThrdPid); PRINT_ERR("R0 = 0x%x\n", pstExc->pstContext->uwR0); PRINT_ERR("R1 = 0x%x\n", pstExc->pstContext->uwR1); PRINT_ERR("R2 = 0x%x\n", pstExc->pstContext->uwR2); PRINT_ERR("R3 = 0x%x\n", pstExc->pstContext->uwR3); PRINT_ERR("R4 = 0x%x\n", pstExc->pstContext->uwR4); PRINT_ERR("R5 = 0x%x\n", pstExc->pstContext->uwR5); PRINT_ERR("R6 = 0x%x\n", pstExc->pstContext->uwR6); PRINT_ERR("R7 = 0x%x\n", pstExc->pstContext->uwR7); PRINT_ERR("R8 = 0x%x\n", pstExc->pstContext->uwR8); PRINT_ERR("R9 = 0x%x\n", pstExc->pstContext->uwR9); PRINT_ERR("R10 = 0x%x\n", pstExc->pstContext->uwR10); PRINT_ERR("R11 = 0x%x\n", pstExc->pstContext->uwR11); PRINT_ERR("R12 = 0x%x\n", pstExc->pstContext->uwR12); PRINT_ERR("PriMask = 0x%x\n", pstExc->pstContext->uwPriMask); PRINT_ERR("SP = 0x%x\n", pstExc->pstContext->uwSP); PRINT_ERR("LR = 0x%x\n", pstExc->pstContext->uwLR); PRINT_ERR("PC = 0x%x\n", pstExc->pstContext->uwPC); PRINT_ERR("xPSR = 0x%x\n", pstExc->pstContext->uwxPSR); PRINT_ERR("\nplease use the addr2line tool to analyze the call stack on PC:\n"); PRINT_ERR("addr2line -e (xxx.axf/xxx.elf/xxx.out) -a -f "); for (UINT32 i = 0; i < pstExc->uwCallStackDepth; i++) { PRINT_ERR("%#x ", pstExc->uwCallStack[i]); } return; } /***************************************************************************** Function : osExcCallStackAnalysis Description : Call stack analysis Input : pstExc --- point to exception info Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osExcCallStackAnalysis(EXC_INFO_S *pstExc) { UINT32 uwSP; UINT32 uwLR; UINT32 uwPC; UINT32 uwStackStartAddr; UINT32 uwStackSize; UINT32 uwDepth = 0; BOOL bFirstLrValid = FALSE; uwSP = pstExc->pstContext->uwSP; /* sp pointer before entering exception */ /* * save first and second depth * first: PC before entering exception * second: (LR - 4) before entering exception * NOTE: If an exception occurs in the interrupt, LR may be EXC_RETURN, so we must make sure * that LR is valid, exclude EXC_RETURN. */ pstExc->uwCallStack[uwDepth++] = pstExc->pstContext->uwPC; if ((pstExc->pstContext->uwLR >= LOSCFG_EXC_CODE_START_ADDR) && \ (pstExc->pstContext->uwLR <= LOSCFG_EXC_CODE_START_ADDR + LOSCFG_EXC_CODE_SIZE)) { pstExc->uwCallStack[uwDepth++] = pstExc->pstContext->uwLR - sizeof(VOID *); /* lr = pc + 4 */ bFirstLrValid = TRUE; } /* * get the start address and size of the stack before entering the exception */ if (pstExc->usPhase == OS_EXC_IN_TASK) /* task use PSP */ { uwStackStartAddr = g_stLosTask.pstRunTask->uwTopOfStack; uwStackSize = g_stLosTask.pstRunTask->uwStackSize; } else /* init and interrupt use MSP */ { uwStackStartAddr = LOSCFG_EXC_MSP_START_ADDR; uwStackSize = LOSCFG_EXC_MSP_SIZE; } /* * check stack overflow, if so, compensate for overflow, readjust stack start address and size. */ if (uwSP < uwStackStartAddr) /* stack top overflow */ { if (pstExc->usPhase == OS_EXC_IN_TASK) { PRINT_ERR("task %s stack top overflow\n", g_stLosTask.pstRunTask->pcTaskName); } else { PRINT_ERR("MSP top overflow\n"); } uwStackSize += (uwStackStartAddr - uwSP); /* compensate overflow size */ uwStackStartAddr = uwSP; /* readjust stack start address */ } /* * Traverses the entire stack from the top of the stack to the bottom of the stack, * find all LR. */ for (; uwSP < uwStackStartAddr + uwStackSize; uwSP += sizeof(UINT32)) { uwLR = *(UINT32 *)uwSP; if (uwLR % 2 == 0) /* Thumb instruction, LR bit0 == 1 */ { continue; } /* * It may be LR, which must be further determined based on the start address * and end address of the code segment. */ if ((uwLR >= LOSCFG_EXC_CODE_START_ADDR) && (uwLR <= LOSCFG_EXC_CODE_START_ADDR + LOSCFG_EXC_CODE_SIZE) \ && (uwDepth < LOSCFG_EXC_CALL_STACK_ANALYSIS_MAX_DEPTH)) { uwPC = uwLR - sizeof(VOID *); /* lr = pc + 4 */ /* the second depth(first LR) has been saved */ if ((uwDepth == 2) && (uwPC == pstExc->uwCallStack[1]) && (bFirstLrValid == TRUE)) { continue; } pstExc->uwCallStack[uwDepth++] = uwPC; } } pstExc->uwCallStackDepth = uwDepth; /* save call stack depth */ return; } /***************************************************************************** Function : osExcHandleEntry Description : EXC handler entry Input : uwExcType --- EXC type : uwFaultAddr --- The address of an accurate address access error : uwPid --- Interrupt number : puwExcBufAddr --- Point to the stack frame without FPU Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osExcHandleEntry(UINT32 uwExcType, UINT32 uwFaultAddr, UINT32 uwPid, EXC_CONTEXT_S *pstExcBufAddr) { /* uwExcType high 16 bits: 0x01 - uwFaultAddr valid, 0x02 - in hwi */ UINT16 usTmpFlag = (uwExcType >> 16) & 0xFFFF; g_uwCurNestCount++; #if (LOSCFG_PLATFORM_HWI == YES) extern UINT32 g_vuwIntCount; g_vuwIntCount++; #endif /* Save interrupt nesting times */ m_stExcInfo.usNestCnt = (UINT16)g_uwCurNestCount; /* uwExcType low 16 bits: exc type */ m_stExcInfo.usType = (UINT16)uwExcType & 0xFFFF; #if (LOSCFG_SAVE_EXC_INFO == YES) /* Initializing a pointer to save an exception context */ m_puwExcContent = (UINT32 *)m_aucTaskArray; #endif /* Save the fault address when an exception occurs if it is valid */ if (usTmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) { m_stExcInfo.uwFaultAddr = uwFaultAddr; } else { m_stExcInfo.uwFaultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR; } /* Save the phase of the exception */ extern BOOL g_bTaskScheduled; if (g_bTaskScheduled && (NULL != g_stLosTask.pstRunTask)) { if (usTmpFlag & OS_EXC_FLAG_IN_HWI) { m_stExcInfo.usPhase = OS_EXC_IN_HWI; m_stExcInfo.uwThrdPid = uwPid; /* interrupt number */ } else { m_stExcInfo.usPhase = OS_EXC_IN_TASK; m_stExcInfo.uwThrdPid = g_stLosTask.pstRunTask->uwTaskID; /* task id */ } } else { m_stExcInfo.usPhase = OS_EXC_IN_INIT; m_stExcInfo.uwThrdPid = 0xffffffff; } /* uwExcType BIT_28: Wether or not to use FPU */ if(uwExcType & OS_EXC_FLAG_NO_FLOAT) { m_stExcInfo.usFpuContext = 0; #if FPU_EXIST /* NOTE: S16-S31, S0-S15,FPSCR,NO_NAME invalid */ m_stExcInfo.pstContext = (EXC_CONTEXT_S *)((UINT8 *)pstExcBufAddr - 64); /* point to S16 */ #else m_stExcInfo.pstContext = pstExcBufAddr; /* point to uwR4 */ #endif } else { m_stExcInfo.usFpuContext = 1; m_stExcInfo.pstContext = pstExcBufAddr; /* point to S16 */ } osExcCallStackAnalysis(&m_stExcInfo); #if (LOSCFG_SAVE_EXC_INFO == YES) osExcSave2DDR(); #endif osExcInfoDisplay(&m_stExcInfo); LOS_Reboot(); } #if (LOSCFG_SAVE_EXC_INFO == YES) /***************************************************************************** Function : osExcSaveIntStatus Description : Save NVIC register group Input : None Output : None Return : None *****************************************************************************/ static VOID osExcSaveIntStatus(VOID) { /* Save exc type */ *((UINT32 *)m_puwExcContent) = OS_EXC_TYPE_NVIC; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save total size of NVIC */ *((UINT32 *)m_puwExcContent) = 0x164; // = OS_NVIC_INT_ENABLE_SIZE + OS_NVIC_INT_PEND_SIZE + OS_NVIC_INT_ACT_SIZE + OS_NVIC_INT_PRI_SIZE + 12 + 4 + 4 m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save interrupt enable register group (start addr: 0xE000E100, size: 32bytes, CMSIS-Core: NVIC->ISER[0 - 7]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_SETENA_BASE, OS_NVIC_INT_ENABLE_SIZE); m_puwExcContent =(UINT8 *)m_puwExcContent + OS_NVIC_INT_ENABLE_SIZE; /* Save interrupt pend register group (start addr: 0xE000E200, size: 32bytes, CMSIS-Core: NVIC->ISPR[0 - 7]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_SETPEND_BASE, OS_NVIC_INT_PEND_SIZE); m_puwExcContent = (UINT8 *)m_puwExcContent + OS_NVIC_INT_PEND_SIZE; /* Save interrupt active status register group (start addr: 0xE000E300, size: 32bytes, CMSIS-Core: NVIC->IABR[0 - 7]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_INT_ACT_BASE, OS_NVIC_INT_ACT_SIZE); m_puwExcContent = (UINT8 *)m_puwExcContent + OS_NVIC_INT_ACT_SIZE; /* Save interrupt priority register group (start addr: 0xE000E400, size: 240bytes), CMSIS-Core: NVIC->IP[0 - 239] */ memcpy(m_puwExcContent, (const void *)OS_NVIC_PRI_BASE, OS_NVIC_INT_PRI_SIZE); m_puwExcContent = (UINT8 *)m_puwExcContent + OS_NVIC_INT_PRI_SIZE; /* Save system exception priority register group (start addr: 0xE000ED18, size: 12bytes, CMSIS-Core: SCB->SHP[0 - 11]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_EXCPRI_BASE, 12); m_puwExcContent = (UINT8 *)m_puwExcContent + 12; /* Save system processing control and state register group (start addr: 0xE000ED24, size: 4bytes, CMSIS-Core: SCB->SHCSR) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_SHCSR, 4); m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save interrupt control and status register group (start addr: 0xE000ED04, size: 4bytes, CMSIS-Core: SCB->ICSR) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_INT_CTRL, 4); m_puwExcContent = (UINT8 *)m_puwExcContent + 4; return; } /***************************************************************************** Function : osExcRegister Description : Register exception Input : uwType --- exception type : pFunc --- exception callback function : pArg --- exception save info arg, not pFunc Output : None Return : None *****************************************************************************/ VOID osExcRegister(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, VOID *pArg) { EXC_INFO_ARRAY_S *pstExcInfo; if (uwType == 0 || uwType >= OS_EXC_TYPE_MAX || pFunc == NULL) { PRINT_ERR("osExcRegister ERROR!\n"); return; } pstExcInfo = &(m_stExcArray[uwType - 1]); pstExcInfo->uwType = uwType; pstExcInfo->pFnExcInfoCb = pFunc; pstExcInfo->pArg = pArg; pstExcInfo->uwValid = TRUE; } /***************************************************************************** Function : osExcSaveSysInfo Description : Saving exception information by calling callback function recursively Input : uwType --- exception type(OS_EXC_TYPE_CONTEXT+1 ---> OS_EXC_TYPE_MAX-1) : pFunc --- callback function : uwLoop --- loop total count : uwLen --- The size of the data saved each time : uwIdx --- loop index Output : None Return : None *****************************************************************************/ VOID osExcSaveSysInfo(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, UINT32 uwLoop, UINT32 uwLen, UINT32 uwIdx) { UINT32 uwRet; UINT32 uwBuffer[OS_EXC_MAX_BUF_LEN]; /* Save exception type and size */ *((UINT32 *)m_puwExcContent) = uwType; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; *((UINT32 *)m_puwExcContent) = uwLen * (uwLoop - uwIdx); m_puwExcContent = (UINT8 *)m_puwExcContent + 4; for (; uwIdx < uwLoop; uwIdx++) { memset((VOID *)uwBuffer, 0, sizeof(UINT32) * OS_EXC_MAX_BUF_LEN); uwRet = pFunc(uwIdx, (VOID *)uwBuffer); if (LOS_OK == uwRet) { memcpy(m_puwExcContent, (VOID *)uwBuffer, uwLen); } m_puwExcContent =(UINT8 *)m_puwExcContent + uwLen; } } /***************************************************************************** Function : osExcSaveInfo Description : save exception info Input : uwType --- exception type(OS_EXC_TYPE_CONTEXT+1 ---> OS_EXC_TYPE_MAX-1) : pFunc --- exception callback : pArg --- register arg, used to generate the arg passed to the callback Output : None Return : None *****************************************************************************/ static VOID osExcSaveInfo(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, VOID *pArg) { UINT32 uwLen; UINT32 uwIdx; UINT32 uwLoop; UINT32 uwTaskSwitchCount = 0; OS_TASK_SWITCH_INFO *pstTaskSwitchInfo; switch(uwType) { case OS_EXC_TYPE_TSK: /* save task info */ uwLen = sizeof(TSK_INFO_S); uwLoop = *(UINT32 *)pArg; uwIdx = 0; break; case OS_EXC_TYPE_QUE: /* save queue info */ uwLen = sizeof(QUEUE_INFO_S); uwLoop = *(UINT32 *)pArg; uwIdx = 0; break; case OS_EXC_TYPE_NVIC: /* save NVIC info */ (VOID)pFunc(0, 0); goto END; case OS_EXC_TYPE_TSK_SWITCH: /* save task switch info */ pstTaskSwitchInfo = pArg; uwTaskSwitchCount = pstTaskSwitchInfo->ucIsFull & 0x7F; uwLen = sizeof(UINT32) + sizeof(CHAR) * LOS_TASK_NAMELEN; /* auwPID + acName */ if (pstTaskSwitchInfo->ucIsFull & 0x80) { uwIdx = pstTaskSwitchInfo->ucIdx; uwLoop = uwIdx + uwTaskSwitchCount; } else { uwIdx = 0; uwLoop = pstTaskSwitchInfo->ucIdx; } break; case OS_EXC_TYPE_MEM: /* save mem info */ uwLen = sizeof(MEM_INFO_S); uwLoop = *(UINT32 *)pArg; uwIdx = 0; break; default: goto END; } osExcSaveSysInfo(uwType, (EXC_INFO_SAVE_CALLBACK)pFunc, uwLoop, uwLen, uwIdx); END: return; } /***************************************************************************** Function : osExcSave2DDR Description : Save exception info to RAM Input : None Output : None Return : None *****************************************************************************/ static VOID osExcSave2DDR(VOID) { UINT32 uwIdx = 0; UINT32 uwExcContextSize; if (m_stExcInfo.usFpuContext == 1) { uwExcContextSize = sizeof(EXC_CONTEXT_S); } else { uwExcContextSize = sizeof(EXC_CONTEXT_S) - 136; /* except FPU register */ } memset(m_puwExcContent, 0xff, g_uwArraySize); /* Cortex-M type */ *((UINT32 *)m_puwExcContent) = 4; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* * Save exception type: OS_EXC_TYPE_CONTEXT */ *((UINT32 *)m_puwExcContent) = OS_EXC_TYPE_CONTEXT; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* The size of struct EXC_INFO_S(except member EXC_CONTEXT_S*) and exception context size */ *((UINT32 *)m_puwExcContent) = sizeof(EXC_INFO_S) - sizeof(EXC_CONTEXT_S *) + uwExcContextSize; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save struct m_stExcInfo except m_stExcInfo.pstContext */ memcpy((VOID *)m_puwExcContent, (VOID *)&m_stExcInfo, sizeof(EXC_INFO_S) - sizeof(EXC_CONTEXT_S *)); m_puwExcContent = (UINT8 *)m_puwExcContent + sizeof(EXC_INFO_S) - sizeof(EXC_CONTEXT_S *); /* Save struct EXC_CONTEXT_S */ if (m_stExcInfo.usFpuContext == 0) { #if FPU_EXIST /* m_stExcInfo.pstContext: init --- point to S16, S16->S31 invalid * + 64 --- point to uwR4 * copy uwR4 -> uwxPSR */ memcpy((VOID *)m_puwExcContent, (UINT8 *)m_stExcInfo.pstContext + 64, uwExcContextSize); #else memcpy((VOID *)m_puwExcContent, m_stExcInfo.pstContext, uwExcContextSize); #endif } else { memcpy((VOID *)m_puwExcContent, m_stExcInfo.pstContext, uwExcContextSize); } m_puwExcContent = (UINT8 *)m_puwExcContent + uwExcContextSize; /* * Save exception type: OS_EXC_TYPE_CONTEXT+1 ---> OS_EXC_TYPE_MAX-1 */ for (uwIdx = 0; uwIdx < OS_EXC_TYPE_MAX - 1; uwIdx++) { if (m_stExcArray[uwIdx].uwValid == FALSE) { continue; } osExcSaveInfo(m_stExcArray[uwIdx].uwType, m_stExcArray[uwIdx].pFnExcInfoCb, m_stExcArray[uwIdx].pArg); } /* * Save exception type: OS_EXC_TYPE_MAX */ *((UINT32 *)m_puwExcContent) = OS_EXC_TYPE_MAX; m_puwExcContent = (UINT8*)m_puwExcContent + 4; return; } #endif /*(LOSCFG_SAVE_EXC_INFO == YES)*/ /***************************************************************************** Function : osExcInit Description : Initializes the EXC Input : None Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT_INIT VOID osExcInit(UINT32 uwArraySize) { #if (LOSCFG_PLATFORM_HWI == YES) /* Register exception handler to interrupt vector table in RAM */ m_pstHwiForm[-14 + OS_SYS_VECTOR_CNT] = NMI_Handler; m_pstHwiForm[-13 + OS_SYS_VECTOR_CNT] = HardFault_Handler; m_pstHwiForm[-12 + OS_SYS_VECTOR_CNT] = MemManage_Handler; m_pstHwiForm[-11 + OS_SYS_VECTOR_CNT] = BusFault_Handler; m_pstHwiForm[-10 + OS_SYS_VECTOR_CNT] = UsageFault_Handler; m_pstHwiForm[-5 + OS_SYS_VECTOR_CNT] = SVC_Handler; #endif /* Enable USGFAULT(BIT_18), BUSFAULT(BIT_17), MEMFAULT(BIT_16) */ *(volatile UINT32 *)OS_NVIC_SHCSR |= 0x70000; /* Enable DIV 0(BIT_4) exception, unaligned(BIT_3) disable */ *(volatile UINT32 *)OS_NVIC_CCR |= 0x10; #if (LOSCFG_SAVE_EXC_INFO == YES) g_uwArraySize = uwArraySize; osExcRegister((EXC_INFO_TYPE)OS_EXC_TYPE_NVIC, (EXC_INFO_SAVE_CALLBACK)osExcSaveIntStatus, NULL); #endif } VOID osBackTrace(VOID) { return; } #endif /*(LOSCFG_PLATFORM_EXC == YES)*/ #ifdef __cplusplus #if __cplusplus } #endif /* __cpluscplus */ #endif /* __cpluscplus */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m4/los_exc.inc ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _LOS_EXC_INC #define _LOS_EXC_INC #include "los_exc.ph" #include "los_sys.ph" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cpluscplus */ #endif /* __cpluscplus */ #ifdef __cplusplus #if __cplusplus } #endif /* __cpluscplus */ #endif /* __cpluscplus */ #endif /* _LOS_EXC_INC */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m4/los_exc.ph ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _LOS_EXC_PH #define _LOS_EXC_PH #include "los_exc.h" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ #if (LOSCFG_PLATFORM_EXC == YES) typedef enum { OS_EXC_TYPE_CONTEXT = 0, OS_EXC_TYPE_TSK = 1, OS_EXC_TYPE_QUE = 2, OS_EXC_TYPE_NVIC = 3, OS_EXC_TYPE_TSK_SWITCH = 4, OS_EXC_TYPE_MEM = 5, OS_EXC_TYPE_MAX = 6 } EXC_INFO_TYPE; typedef struct tagExcInfoCallBackArray { EXC_INFO_TYPE uwType; UINT32 uwValid; EXC_INFO_SAVE_CALLBACK pFnExcInfoCb; VOID* pArg; }EXC_INFO_ARRAY_S; #define OS_NVIC_SHCSR 0xE000ED24 #define OS_NVIC_CCR 0xE000ED14 #define OS_NVIC_INT_ENABLE_SIZE 0x20 #define OS_NVIC_INT_PRI_SIZE 0xF0 #define OS_NVIC_INT_PEND_SIZE OS_NVIC_INT_ACT_SIZE #define OS_NVIC_INT_ACT_SIZE OS_NVIC_INT_ENABLE_SIZE #define MAX_SCENE_INFO_SIZE (8 + sizeof(EXC_INFO_S) - 4 + sizeof(EXC_CONTEXT_S)) #define MAX_TSK_INFO_SIZE (8 + sizeof(TSK_INFO_S) * (LOSCFG_BASE_CORE_TSK_LIMIT + 1)) #define MAX_INT_INFO_SIZE (8 + 0x164) #if (LOSCFG_BASE_IPC_QUEUE == YES) #define MAX_QUEUE_INFO_SIZE (8 + sizeof(QUEUE_INFO_S) * LOSCFG_BASE_IPC_QUEUE_LIMIT) #else #define MAX_QUEUE_INFO_SIZE (0) #endif #if (LOSCFG_BASE_CORE_EXC_TSK_SWITCH == YES) #define MAX_SWITCH_INFO_SIZE (8 + (sizeof(UINT32) + sizeof(CHAR) * LOS_TASK_NAMELEN) * OS_TASK_SWITCH_INFO_COUNT) #else #define MAX_SWITCH_INFO_SIZE (0) #endif #if (LOSCFG_BASE_MEM_NODE_INTEGRITY_CHECK == YES) #define MAX_MEM_INFO_SIZE (8 + sizeof(MEM_INFO_S) * OS_SYS_MEM_NUM) #else #define MAX_MEM_INFO_SIZE (0) #endif #if (LOSCFG_SAVE_EXC_INFO == YES) #define MAX_EXC_MEM_SIZE ( 4 + MAX_SCENE_INFO_SIZE + MAX_TSK_INFO_SIZE + MAX_QUEUE_INFO_SIZE + MAX_INT_INFO_SIZE + MAX_SWITCH_INFO_SIZE + MAX_MEM_INFO_SIZE + 4) #else #define MAX_EXC_MEM_SIZE ( 0 ) #endif extern VOID osExcRegister(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, VOID *pArg); #endif #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ #endif ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m7/gcc/los_dispatch_gcc.S ================================================ /** ---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /** ---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**************************************************************************************** * EXPORT FUNCTIONS ****************************************************************************************/ .global LOS_IntLock .global LOS_IntUnLock .global LOS_IntRestore .global LOS_StartToRun .global osTaskSchedule .global PendSV_Handler /**************************************************************************************** * EXTERN PARAMETERS ****************************************************************************************/ .extern g_stLosTask .extern g_pfnTskSwitchHook .extern g_bTaskScheduled /**************************************************************************************** * EQU ****************************************************************************************/ .equ OS_NVIC_INT_CTRL, 0xE000ED04 /* Interrupt Control and State Register. */ .equ OS_NVIC_PENDSVSET, 0x10000000 /* Value to trigger PendSV exception. */ .equ OS_NVIC_SYSPRI2, 0xE000ED20 /* System Handler Priority Register 2. */ .equ OS_NVIC_PENDSV_SYSTICK_PRI, 0xFFFF0000 /* SysTick + PendSV priority level (lowest). */ .equ OS_TASK_STATUS_RUNNING, 0x0010 /* Task Status Flag (RUNNING). */ /**************************************************************************************** * CODE GENERATION DIRECTIVES ****************************************************************************************/ .section .text .thumb .syntax unified .arch armv7e-m /**************************************************************************************** * Function: * VOID LOS_StartToRun(VOID); * Description: * Start the first task, which is the highest priority task in the priority queue. * Other tasks are started by task scheduling. ****************************************************************************************/ .type LOS_StartToRun, %function LOS_StartToRun: CPSID I /** * Set PendSV and SysTick prority to the lowest. * read ---> modify ---> write-back. */ LDR R0, =OS_NVIC_SYSPRI2 LDR R1, =OS_NVIC_PENDSV_SYSTICK_PRI LDR R2, [R0] ORR R1, R1, R2 STR R1, [R0] /** * Set g_bTaskScheduled = 1. */ LDR R0, =g_bTaskScheduled MOV R1, #1 STR R1, [R0] /** * Set g_stLosTask.pstRunTask = g_stLosTask.pstNewTask. */ LDR R0, =g_stLosTask LDR R1, [R0, #4] STR R1, [R0] /** * Set g_stLosTask.pstRunTask->usTaskStatus |= OS_TASK_STATUS_RUNNING. */ LDR R1, [R0] LDRH R2, [R1, #4] MOV R3, #OS_TASK_STATUS_RUNNING ORR R2, R2, R3 STRH R2, [R1, #4] /** * Restore the default stack frame(R0-R3,R12,LR,PC,xPSR) of g_stLosTask.pstRunTask to R0-R7. * [Initial EXC_RETURN ignore,] return by setting the CONTROL register. * * The initial stack of the current running task is as follows: * * POP: Restore the context of the current running task ===>| * High addr--->| * Bottom of the stack--->| * ----------+---------------------------------+--------------------------------+ * | R4-R11, PRIMASK, EXC_RETURN | R0-R3, R12, LR, PC, xPSR | * ----------+---------------------------------+--------------------------------+ * |<---Top of the stack, restored from g_stLosTask.pstRunTask->pStackPointer * |<--- skip --->|<--- copy to R0-R7 --->| * R12 to PSP--->| * Stack pointer after LOS_StartToRun--->| */ LDR R12, [R1] ADD R12, R12, #36 /* skip R4-R11, PRIMASK. */ #if defined (__VFP_FP__) && !defined(__SOFTFP__) ADD R12, R12, #4 /* if FPU exist, skip EXC_RETURN. */ #endif LDMFD R12!, {R0-R7} /** * Set the stack pointer of g_stLosTask.pstRunTask to PSP. */ MSR PSP, R12 /** * Set the CONTROL register, after schedule start, privilege level and stack = PSP. */ MOV R12, #2 MSR CONTROL, R12 /** * Enable interrupt. (The default PRIMASK value is 0, so enable directly) */ MOV LR, R5 CPSIE I /** * Jump directly to the default PC of g_stLosTask.pstRunTask, the field information * of the main function will be destroyed and will never be returned. */ BX R6 /**************************************************************************************** * Function: * UINTPTR LOS_IntLock(VOID); * Description: * Disable all interrupts except Reset,NMI and HardFault. * The value of currnet interruption state will be returned to the caller to save. * * Function: * VOID LOS_IntRestore(UINTPTR uvIntSave); * Description: * Restore the locked interruption of LOS_IntLock. * The caller must pass in the value of interruption state previously saved. ****************************************************************************************/ .type LOS_IntLock, %function LOS_IntLock: MRS R0, PRIMASK CPSID I BX LR .type LOS_IntUnLock, %function LOS_IntUnLock: MRS R0, PRIMASK CPSIE I BX LR .type LOS_IntRestore, %function LOS_IntRestore: MSR PRIMASK, R0 BX LR /**************************************************************************************** * Function: * VOID osTaskSchedule(VOID); * Description: * Start the task swtich process by software trigger PendSV interrupt. ****************************************************************************************/ .type osTaskSchedule, %function osTaskSchedule: LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] BX LR /**************************************************************************************** * Function: * VOID PendSV_Handler(VOID); * Description: * PendSV interrupt handler, switch the context of the task. * First: Save the context of the current running task(g_stLosTask.pstRunTask) * to its own stack. * Second: Restore the context of the next running task(g_stLosTask.pstNewTask) * from its own stack. ****************************************************************************************/ .type PendSV_Handler, %function PendSV_Handler: /** * R12: Save the interruption state of the current running task. * Disable all interrupts except Reset,NMI and HardFault */ MRS R12, PRIMASK CPSID I /** * Call task switch hook. */ LDR R2, =g_pfnTskSwitchHook LDR R2, [R2] CBZ R2, TaskSwitch PUSH {R12, LR} BLX R2 POP {R12, LR} TaskSwitch: /** * R0 = now stack pointer of the current running task. */ MRS R0, PSP /** * Save the stack frame([S16-S31],R4-R11) of the current running task. * R12 save the PRIMASK value of the current running task. * NOTE: 1. Before entering the exception handler function, these registers * ([NO_NAME,FPSCR,S15-S0],xPSR,PC,LR,R12,R3-R0) have been automatically * saved by the CPU in the stack of the current running task. * 2. If lazy stacking is enabled, space is reserved on the stack for * the floating-point context(FPSCR,S15-S0), but the floating-point state * is not saved. when the floating-point instruction(VSTMDBEQ R0!, {D8-D15}) * is executed, the floating-point context(FPSCR,S15-S0) is first saved into * the space reserved on the stack. In other words, the instruction * 'VSTMDBEQ R0!, {D8-D15}' will trigger the CPU to save 'FPSCR,S15-S0' first. * * The stack of the current running task is as follows: * * |<=== PUSH: Save the context of the current running task * | High addr--->| * --+-----------------------------------+-------------------------------------------+--- * | R4-R11,PRIMASK,EXC_RETURN,S16-S31 | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | * | [ lazy stacking ]| * --+-----------------------------------+-------------------------------------------+--- * Stack pointer before entering exception--->| * |<--- cpu auto saved --->| * |<---PSP to R0 * |<---Top of the stack, save to g_stLosTask.pstRunTask->pStackPointer */ #if defined (__VFP_FP__) && !defined(__SOFTFP__) /* if FPU exist. */ TST R14, #0x10 /* if the task using the FPU context, push s16-s31. */ IT EQ VSTMDBEQ R0!, {D8-D15} STMFD R0!, {R14} /* save EXC_RETURN. */ #endif STMFD R0!, {R4-R12} /* save the core registers and PRIMASK. */ /** * R5,R8. */ LDR R5, =g_stLosTask MOV R8, #OS_TASK_STATUS_RUNNING /** * Save the stack pointer of the current running task to TCB. * (g_stLosTask.pstRunTask->pStackPointer = R0) */ LDR R6, [R5] STR R0, [R6] /** * Clear the RUNNING state of the current running task. * (g_stLosTask.pstRunTask->usTaskStatus &= ~OS_TASK_STATUS_RUNNING) */ LDRH R7, [R6, #4] BIC R7, R7, R8 STRH R7, [R6, #4] /** * Switch the current running task to the next running task. * (g_stLosTask.pstRunTask = g_stLosTask.pstNewTask) */ LDR R0, [R5, #4] STR R0, [R5] /** * Set the RUNNING state of the next running task. * (g_stLosTask.pstNewTask->usTaskStatus |= OS_TASK_STATUS_RUNNING) */ LDRH R7, [R0, #4] ORR R7, R7, R8 STRH R7, [R0, #4] /** * Restore the stack pointer of the next running task from TCB. * (R1 = g_stLosTask.pstNewTask->pStackPointer) */ LDR R1, [R0] /** * Restore the stack frame(R4-R11,[S16-S31]) of the next running task. * R12 restore the PRIMASK value of the next running task. * NOTE: After exiting the exception handler function, these registers * (PC,xPSR,R0-R3,R12,LR,[S0-S15,FPSCR,NO_NAME]) will be automatically * restored by the CPU from the stack of the next running task. * * 1. The stack of the next running task is as follows: * * POP: Restore the context of the next running task ===>| * High addr--->| * --+-----------------------------------+-------------------------------------------+--- * | R4-R11,PRIMASK,EXC_RETURN,S16-S31 | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | * --+-----------------------------------+-------------------------------------------+--- * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer * R1 to PSP--->| * |<--- cpu auto restoring --->| * Stack pointer after exiting exception--->| * * 2. If the next running task is run for the first time, the stack is as follows: * * POP: Restore the context of the next running task ===>| * High addr--->| * Bottom of the stack--->| * ----------+---------------------------------+--------------------------------+ * | R4-R11, PRIMASK, EXC_RETURN | R0-R3, R12, LR, PC, xPSR | * ----------+---------------------------------+--------------------------------+ * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer * R1 to PSP--->| * |<--- cpu auto restoring --->| * Stack pointer after exiting exception--->| */ LDMFD R1!, {R4-R12} /* restore the core registers and PRIMASK. */ #if defined (__VFP_FP__) && !defined(__SOFTFP__) /* if FPU exist. */ LDMFD R1!, {R14} /* restore EXC_RETURN. */ TST R14, #0x10 /* if the task using the FPU context, pop s16-s31. */ IT EQ VLDMIAEQ R1!, {D8-D15} #endif /** * Set the stack pointer of the next running task to PSP. */ MSR PSP, R1 /** * Restore the interruption state of the next running task. */ MSR PRIMASK, R12 BX LR ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m7/gcc/los_hw_exc_gcc.S ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**************************************************************************************** * CODE GENERATION DIRECTIVES ****************************************************************************************/ .syntax unified .arch armv7e-m .thumb .section .text /**************************************************************************************** * EXPORT FUNCTIONS ****************************************************************************************/ .global NMI_Handler .global HardFault_Handler .global MemManage_Handler .global BusFault_Handler .global UsageFault_Handler .global SVC_Handler /**************************************************************************************** * EXTERN PARAMETERS ****************************************************************************************/ .extern osExcHandleEntry .extern g_uwExcTbl .extern g_bTaskScheduled /**************************************************************************************** * EQU ****************************************************************************************/ .equ OS_EXC_CAUSE_NMI, 18 .equ OS_EXC_CAUSE_HARDFAULT, 19 .equ OS_EXC_CAUSE_MEMFAULT, 20 .equ OS_EXC_CAUSE_BUSFAULT, 21 .equ OS_EXC_CAUSE_USAGEFAULT, 22 .equ OS_EXC_CAUSE_SVC, 23 .equ HF_DEBUGEVT, 24 .equ HF_VECTBL, 25 .equ FLAG_ADDR_VALID, 0x10000 /* bit 16 */ .equ FLAG_HWI_ACTIVE, 0x20000 /* bit 17 */ .equ FLAG_NO_FLOAT, 0x10000000 /* bit 28 */ .equ OS_NVIC_CFSR, 0xE000ED28 /* include BusFault/MemFault/UsageFault State Regeister */ .equ OS_NVIC_HFSR, 0xE000ED2C /* HardFault State Regeister */ .equ OS_NVIC_BFAR, 0xE000ED38 .equ OS_NVIC_MMFAR, 0xE000ED34 .equ OS_NVIC_ACT_BASE, 0xE000E300 .equ OS_NVIC_SHCSRS, 0xE000ED24 .equ OS_NVIC_SHCSR_MASK, 0xC00 /* SYSTICKACT and PENDSVACT */ /**************************************************************************************** * Function: * VOID NMI_Handler(VOID); * Description: * NMI Handler. ****************************************************************************************/ .type NMI_Handler, %function NMI_Handler: /** * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. * < R0 >: * +------------------------------------------------------+------------------------+ * | 31-8 | 7-0 | * +------------------------------------------------------+------------------------+ * | --- | OS_EXC_CAUSE_NMI | * +------------------------------------------------------+------------------------+ * < R1 >: invalid */ MOV R0, #OS_EXC_CAUSE_NMI MOV R1, #0 B osExcDispatch /**************************************************************************************** * Function: * VOID HardFault_Handler(VOID); * Description: * HardFault Handler. ****************************************************************************************/ .type HardFault_Handler, %function HardFault_Handler: /** * Check HardFault state register. * * HFSR: * +----------+--------+--------+--------+-------+ * | 31 | 30 | 29 - 2 | 1 | 0 | * +----------+--------+--------+--------+-------+ * | DEBUGEVT | FORCED | -- | VECTBL | -- | * +----------+--------+--------+--------+-------+ */ MOV R0, #OS_EXC_CAUSE_HARDFAULT LDR R2, =OS_NVIC_HFSR LDR R2, [R2] /** * Check whether HardFault are triggered by debugging events. * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. * < R0 >: * +----------------------------------------+-------------+------------------------+ * | 31-16 | 15-8 | 7-0 | * +----------------------------------------+-------------+------------------------+ * | --- | HF_DEBUGEVT | OS_EXC_CAUSE_HARDFAULT | * +----------------------------------------+-------------+------------------------+ * < R1 >: invalid */ MOV R1, #HF_DEBUGEVT ORR R0, R0, R1, LSL #0x8 TST R2, #0x80000000 BNE osExcDispatch /* DEBUGEVT */ /** * Check whether HardFault is caused by the failure of the fetch vector. * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. * < R0 >: * +----------------------------------------+-------------+------------------------+ * | 31-16 | 15-8 | 7-0 | * +----------------------------------------+-------------+------------------------+ * | --- | HF_VECTBL | OS_EXC_CAUSE_HARDFAULT | * +----------------------------------------+-------------+------------------------+ * < R1 >: invalid */ AND R0, R0, #0x000000FF MOV R1, #HF_VECTBL ORR R0, R0, R1, LSL #0x8 TST R2, #0x00000002 BNE osExcDispatch /* VECTBL */ /** * If it`s not DEBUGEVT and VECTBL, that is FORCED, then read the CFSR register to * check BusFault, MemFault and UsageFault. * R0: OS_EXC_CAUSE_HARDFAULT * * CFSR: * +----------------+--------+--------+ * | 31-16 | 15-8 | 7-0 | * +----------------+--------+--------+ * | UFSR | BFSR | MFSR | * +----------------+--------+--------+ */ AND R0, R0, #0x000000FF LDR R2, =OS_NVIC_CFSR LDR R2, [R2] TST R2, #0x8000 /* BFSR->BFARVALID */ BNE _HFBusFault /* BusFault */ TST R2, #0x80 /* MFSR->MMARVALID */ BNE _HFMemFault /* MemFault */ /** * BFARVALID and MMARVALID flag both invalid. * R12: 0 --- The error address is invalid. */ MOV R12, #0 B osHFExcCommonBMU /** * BFARVALID flag valid, read BFAR register. * R1 : BFAR value --- The address value of a bus error. * R12: The error address is valid. */ _HFBusFault: LDR R1, =OS_NVIC_BFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID B osHFExcCommonBMU /** * MMARVALID flag valid, read MMFAR register. * R1 : MMFAR value --- The address value of memory management error. * R12: The error address is valid. */ _HFMemFault: LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID /** * osHFExcCommonBMU: --- Get specific error status from table g_uwExcTbl, stored in R0. * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. * < R0 >: * +-------------------+-----------------+------------------+------------------------+ * | 31-17 | 16 | 15-8 | 7-0 | * +-------------------+-----------------+------------------+------------------------+ * | --- | FLAG_ADDR_VALID | Error state code | OS_EXC_CAUSE_HARDFAULT | * | | or | in | | * | | 0(invalid) | table g_uwExcTbl | | * +-------------------+-----------------+------------------+------------------------+ * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, * else invalid. */ osHFExcCommonBMU: CLZ R2, R2 LDR R3, =g_uwExcTbl ADD R3, R3, R2 LDRB R2, [R3] ORR R0, R0, R2, LSL #0x8 ORR R0, R0, R12 B osExcDispatch /**************************************************************************************** * Function: * VOID SVC_Handler(VOID); * Description: * SVC Handler. ****************************************************************************************/ .type SVC_Handler, %function SVC_Handler: TST LR, #0x4 /* EXC_RETURN[b2] --- PSP or MSP */ ITE EQ MRSEQ R0, MSP MRSNE R0, PSP LDR R1, [R0, #24] /* The PC value in the stack frame */ LDRB R0, [R1, #-2] /* R0: The number of SVC (0 - 255) */ MOV R1, #0 /* B osExcDispatch */ _SvcLoop: B _SvcLoop /**************************************************************************************** * Function: * VOID BusFault_Handler(VOID); * Description: * BusFault Handler. ****************************************************************************************/ .type BusFault_Handler, %function BusFault_Handler: LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_BUSFAULT TST R0, #0x8000 /* BFSR->BFARVALID */ BEQ _ExcBusNoADDR LDR R1, =OS_NVIC_BFAR LDR R1, [R1] /* R1: The value of BFAR */ MOV R12, #FLAG_ADDR_VALID /* R12: BusFault addr valid */ AND R0, R0, #0x3F00 /* R0: Reserved the b13-b8 of the BFSR */ B osExcCommonBMU _ExcBusNoADDR: MOV R12, #0 /* R12: BusFault addr invalid */ AND R0, R0, #0x3F00 /* R0: Reserved the b13-b8 of the BFSR */ B osExcCommonBMU /**************************************************************************************** * Function: * VOID MemManage_Handler(VOID); * Description: * MemManage Handler. ****************************************************************************************/ .type MemManage_Handler, %function MemManage_Handler: LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_MEMFAULT TST R0, #0x80 /* MFSR->MMARVALID */ BEQ _ExcMemNoADDR LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] /* R1: The value of MMFAR */ MOV R12, #FLAG_ADDR_VALID /* R12: MemFault addr valid */ AND R0, R0, #0x3B /* R0: Reserved the b5-b0 of the MFSR */ B osExcCommonBMU _ExcMemNoADDR: MOV R12, #0 /* R12: MemFault addr invalid */ AND R0, R0, #0x3B /* R0: Reserved the b5-b0 of the MFSR */ B osExcCommonBMU /**************************************************************************************** * Function: * VOID UsageFault_Handler(VOID); * Description: * UsageFault Handler. ****************************************************************************************/ .type UsageFault_Handler, %function UsageFault_Handler: LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_USAGEFAULT LDR R1, =#0x030F LSL R1, R1, #16 AND R0, R0, R1 /* R0: reserved UFSR */ MOV R12, #0 /* R12: Fault addr invalid */ /** * osExcCommonBMU: BusFault_Handler,MemManage_Handler and UsageFault_Handler share. * Get specific error status from table g_uwExcTbl, stored in R0. * Before executing osExcDispatch, the value of R0 is as follows. * < R0 >: * +-------------------+-----------------+------------------+------------------------+ * | 31-17 | 16 | 15-8 | 7-0 | * +-------------------+-----------------+------------------+------------------------+ * | --- | FLAG_ADDR_VALID | Error state code |OS_EXC_CAUSE_BUSFAULT or| * | | or | in |OS_EXC_CAUSE_MEMFAULT or| * | | 0(invalid) | table g_uwExcTbl |OS_EXC_CAUSE_USAGEFAULT | * +-------------------+-----------------+------------------+------------------------+ * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, * else invalid. */ osExcCommonBMU: CLZ R0, R0 LDR R3, =g_uwExcTbl ADD R3, R3, R0 LDRB R0, [R3] LSL R0, R0, #0x8 ORR R0, R0, R2 ORR R0, R0, R12 /**************************************************************************************** * osExcDispatch: NMI_Handler, HardFault_Handler, SVC_Handler, BusFault_Handler, MemManage_Handler, * UsageFault_Handler sharing. ****************************************************************************************/ /** * When executing osExcDispatch, R0, R1 will be used. * The possible values of R0 and R1 are as follows. * * < R0 >: * +----------------+-----------------+---------------------+------------------------+ * | 31-17 | 16 | 15-8 | 7-0 | * +----------------+-----------------+---------------------+------------------------+ * | | FLAG_ADDR_VALID | Error state code in | OS_EXC_CAUSE_HARDFAULT | * | --- | or | table g_uwExcTbl |or OS_EXC_CAUSE_MEMFAULT| * | | 0(invalid) | or HF_DEBUGEVT |or OS_EXC_CAUSE_BUSFAULT| * | | | or HF_VECTBL |or OS_EXC_CAUSE_NMI or | * | | | | OS_EXC_CAUSE_USAGEFAULT| * +----------------+-----------------+---------------------+------------------------+ * b17: FLAG_HWI_ACTIVE * b28: FLAG_NO_FLOAT * NOTE: b17 and b28 will be set later. * * < R1 >: * If the bit16 of R0 is 1, then R1 is the value of BFAR or MMFAR, otherwise the * value in R1 is invalid. * */ osExcDispatch: LDR R2, =OS_NVIC_ACT_BASE MOV R12, #8 /* #8: externel interrupt active check loop counter(#0 - #239) */ _hwiActiveCheck: LDR R3, [R2] /* R3 store the value of externel interrupt active status */ CMP R3, #0 BEQ _hwiActiveCheckNext /** * Exception occured in external interrupt. */ ORR R0, R0, #FLAG_HWI_ACTIVE /* R0[b17] = 1, externel interrupt active valid &&&&&&&&&& */ RBIT R2, R3 /* bit reversal */ CLZ R2, R2 RSB R12, R12, #8 /* R12 = 8 - R12 */ ADD R2, R2, R12, LSL #5 /* R2: external interrupt number as uwPid */ /** * Interrupts and initialization phase always use MSP. */ _ExcInMSP: TST LR, #0x10 /* EXC_RETURN[b4] --- FPU(0) or without FPU(1) */ BNE _NoFloatInMsp /** * Before executing instruction 'B _handleEntry', MSP is as follows. * MSP: * High addr--->| * +--------------------------------------------------------------------------------+--------- * | S16-S31,R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | * +--------------------------------------------------------------------------------+--------- * |<---R13 Initial R13--->|<--- #104 --->|<---SAVED_SP * | (CPU auto saved) | * */ ADD R3, R13, #104 /* #104: skip [R0-xPSR,D0-D7,FPSCR,NO_NAME] */ PUSH {R3} /* push [SAVED_SP]: MSP+104 = Stack pointer in MSP before entering the exception */ MRS R12, PRIMASK PUSH {R4-R12} /* push R4-R11,PRIMASK to MSP */ VPUSH {D8-D15} /* push D8-D15 to MSP */ B _handleEntry /** * Before executing instruction 'B _handleEntry', MSP is as follows. * MSP: * High addr--->| * +--------------------------------------------------------------------------------+--------- * | R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR | * +--------------------------------------------------------------------------------+--------- * R13--->| Initial R13--->|<--- #32 --->|<---SAVED_SP * | (CPU auto saved) | * */ _NoFloatInMsp: ADD R3, R13, #32 /* #32: skip [R0-R3,R12,LR,PC,xPSR] */ PUSH {R3} /* push [SAVED_SP]: MSP+32 = Stack pointer in MSP before entering the exception */ MRS R12, PRIMASK PUSH {R4-R12} /* push R4-R11,PRIMASK to MSP */ ORR R0, R0, #FLAG_NO_FLOAT /* R0[b28] = 1, no FPU &&&&&&&&&& */ B _handleEntry _hwiActiveCheckNext: ADD R2, R2, #4 /* next NVIC ACT ADDR */ SUBS R12, R12, #1 BNE _hwiActiveCheck /** * Not in externel interrupt, check whether it is SysTick or PendSV. */ LDR R2, =OS_NVIC_SHCSRS LDRH R2,[R2] LDR R3,=OS_NVIC_SHCSR_MASK AND R2, R2, R3 CMP R2, #0 BNE _ExcInMSP /* SysTick or PendSV active */ /** * Check whether an exception occurs during the initialization phase. * If g_bTaskScheduled == 0, it is in the initialization phase. */ LDR R2, =g_bTaskScheduled LDR R2, [R2] TST R2, #1 BEQ _ExcInMSP /* initialization phase use MSP */ /** * Exception occured in Task. */ TST LR, #0x10 BNE _NoFloatInPsp /** * Before executing _handleEntry, MSP is as follows. * MSP: * High addr--->| * +--------------------------------------------------------------------------------+--------- * | S16-S31,R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | * +--------------------------------------------------------------------------------+--------- * |<---R13 |<--- #104 --->|<---Initial R13 * | (copied from PSP) | * R2(no use)--->| * * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME. */ MOV R2, R13 SUB R2, R2, #8 /* #8: reserved for [FPSCR,NO_NAME] */ SUB R13, #104 /* #104: MSP reserved, used to store stack frame in PSP */ MRS R3, PSP ADD R12, R3, #104 /* PSP+104 = Stack pointer of the task before entering the exception */ PUSH {R12} /* push task SP to MSP */ MRS R12, PRIMASK PUSH {R4-R12} /* push R4-R11,PRIMASK of the current running task to MSP */ VPUSH {D8-D15} /* push D8-D15 of the currnent running task to MSP */ /* Copy stack frame from the stack of the current running task to MSP */ LDMFD R3!, {R4-R11} /* restore stack frame[R0-xPSR] of PSP to R4-R11 */ VLDMIA R3!, {D8-D15} /* restore stack frame[D0-D7] of PSP to D8-D15 */ VSTMDB R2!, {D8-D15} /* save stack frame[D0-D7] to MSP */ STMFD R2!, {R4-R11} /* save stack frame[R0-xPSR] to MSP */ LDMFD R3, {R4-R5} /* restore stack frame[FPSCR,NO_NAME] to R4-R5 */ ADD R2, R2, #104 /* skip stack frame */ STMFD R2, {R4-R5} /* save stack frame[FPSCR,NO_NAME] to MSP */ B _handleEntry /** * Before executing _handleEntry, MSP is as follows. * MSP: * High addr--->| * +--------------------------------------------------------------------------------+--------- * | R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR | * +--------------------------------------------------------------------------------+--------- * R13--->| |<--- #32 --->|<---Initial R13 * | (copied from PSP) | * |<---R2(no use) * * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR. */ _NoFloatInPsp: MOV R2, R13 SUB R13, #32 /* #32: MSP reserved, used to store stack frame in PSP */ MRS R3, PSP ADD R12, R3, #32 /* PSP+32 = Stack pointer of the task before entering the exception */ PUSH {R12} /* push task SP to MSP */ MRS R12, PRIMASK PUSH {R4-R12} /* push R4-R11,PRIMASK of the current running task to MSP */ /* Copy stack frame from the stack of the current running task to MSP */ LDMFD R3, {R4-R11} /* restore stack frame of PSP to R4-R11 */ STMFD R2!, {R4-R11} /* save stack frame to MSP */ ORR R0, R0, #FLAG_NO_FLOAT /* R0[b28] = 1, no FPU &&&&&&&&&& */ /** * _handleEntry: Call osExcHandleEntry * param1: R0 --- b28: FLAG_NO_FLOAT. * b17: FLAG_HWI_ACTIVE. * b16: FLAG_ADDR_VALID. * b15-b8: Error state code in table g_uwExcTbl or HF_DEBUGEVT or HF_VECTBL. * b7-b0: OS_EXC_CAUSE_HARDFAULT or OS_EXC_CAUSE_NMI or OS_EXC_CAUSE_MEMFAULT * or OS_EXC_CAUSE_BUSFAULT or OS_EXC_CAUSE_USAGEFAULT. * param2: R1 --- The value of BFAR or MMFAR if R0[b16] = 1, otherwise invalid. * param3: R2 --- external interrupt number(0-239) if R0[b17] = 1, otherwise invalid. * param4: R3 --- Point to the top of the stack(R4 or S16) that the exception stack frame in MSP. */ _handleEntry: MOV R3, R13 CPSID I CPSID F B osExcHandleEntry NOP ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m7/iar/los_dispatch_iar.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2016-2018>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT LOS_IntLock EXPORT LOS_IntUnLock EXPORT LOS_IntRestore EXPORT LOS_StartToRun EXPORT osTaskSchedule EXPORT PendSV_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT g_stLosTask IMPORT g_pfnTskSwitchHook IMPORT g_bTaskScheduled ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt Control and State Register. OS_NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception. OS_NVIC_SYSPRI2 EQU 0xE000ED20 ; System Handler Priority Register 2. OS_NVIC_PENDSV_SYSTICK_PRI EQU 0xFFFF0000 ; SysTick + PendSV priority level (lowest). OS_TASK_STATUS_RUNNING EQU 0x0010 ; Task Status Flag (RUNNING). ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** SECTION .text:CODE(2) THUMB REQUIRE8 PRESERVE8 ;**************************************************************************************** ; Function: ; VOID LOS_StartToRun(VOID); ; Description: ; Start the first task, which is the highest priority task in the priority queue. ; Other tasks are started by task scheduling. ;**************************************************************************************** LOS_StartToRun CPSID I ;/** ; * Set PendSV and SysTick prority to the lowest. ; * read ---> modify ---> write-back. ; */ LDR R0, =OS_NVIC_SYSPRI2 LDR R1, =OS_NVIC_PENDSV_SYSTICK_PRI LDR R2, [R0] ORR R1, R1, R2 STR R1, [R0] ;/** ; * Set g_bTaskScheduled = 1. ; */ LDR R0, =g_bTaskScheduled MOV R1, #1 STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask = g_stLosTask.pstNewTask. ; */ LDR R0, =g_stLosTask LDR R1, [R0, #4] STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask->usTaskStatus |= OS_TASK_STATUS_RUNNING. ; */ LDR R1, [R0] LDRH R2, [R1, #4] MOV R3, #OS_TASK_STATUS_RUNNING ORR R2, R2, R3 STRH R2, [R1, #4] ;/** ; * Restore the default stack frame(R0-R3,R12,LR,PC,xPSR) of g_stLosTask.pstRunTask to R0-R7. ; * [Initial EXC_RETURN ignore,] return by setting the CONTROL register. ; * ; * The initial stack of the current running task is as follows: ; * ; * POP: Restore the context of the current running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+---------------------------------+--------------------------------+ ; * | R4-R11, PRIMASK, EXC_RETURN | R0-R3, R12, LR, PC, xPSR | ; * ----------+---------------------------------+--------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstRunTask->pStackPointer ; * |<--- skip --->|<--- copy to R0-R7 --->| ; * R12 to PSP--->| ; * Stack pointer after LOS_StartToRun--->| ; */ LDR R12, [R1] ADD R12, R12, #36 ; skip R4-R11, PRIMASK. #if defined (__ARMVFP__) ADD R12, R12, #4 ; if FPU exist, skip EXC_RETURN. #endif LDMFD R12!, {R0-R7} ;/** ; * Set the stack pointer of g_stLosTask.pstRunTask to PSP. ; */ MSR PSP, R12 ;/** ; * Set the CONTROL register, after schedule start, privilege level and stack = PSP. ; */ MOV R12, #2 MSR CONTROL, R12 ;/** ; * Enable interrupt. (The default PRIMASK value is 0, so enable directly) ; */ MOV LR, R5 CPSIE I ;/** ; * Jump directly to the default PC of g_stLosTask.pstRunTask, the field information ; * of the main function will be destroyed and will never be returned. ; */ BX R6 ;**************************************************************************************** ; Function: ; UINTPTR LOS_IntLock(VOID); ; Description: ; Disable all interrupts except Reset,NMI and HardFault. ; The value of currnet interruption state will be returned to the caller to save. ; ; Function: ; VOID LOS_IntRestore(UINTPTR uvIntSave); ; Description: ; Restore the locked interruption of LOS_IntLock. ; The caller must pass in the value of interruption state previously saved. ;**************************************************************************************** LOS_IntLock MRS R0, PRIMASK CPSID I BX LR LOS_IntUnLock MRS R0, PRIMASK CPSIE I BX LR LOS_IntRestore MSR PRIMASK, R0 BX LR ;**************************************************************************************** ; Function: ; VOID osTaskSchedule(VOID); ; Description: ; Start the task swtich process by software trigger PendSV interrupt. ;**************************************************************************************** osTaskSchedule LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] BX LR ;**************************************************************************************** ; Function: ; VOID PendSV_Handler(VOID); ; Description: ; PendSV interrupt handler, switch the context of the task. ; First: Save the context of the current running task(g_stLosTask.pstRunTask) ; to its own stack. ; Second: Restore the context of the next running task(g_stLosTask.pstNewTask) ; from its own stack. ;**************************************************************************************** PendSV_Handler ;/** ; * R12: Save the interruption state of the current running task. ; * Disable all interrupts except Reset,NMI and HardFault ; */ MRS R12, PRIMASK CPSID I ;/** ; * Call task switch hook. ; */ LDR R2, =g_pfnTskSwitchHook LDR R2, [R2] CBZ R2, TaskSwitch PUSH {R12, LR} BLX R2 POP {R12, LR} TaskSwitch ;/** ; * R0 = now stack pointer of the current running task. ; */ MRS R0, PSP ;/** ; * Save the stack frame([S16-S31],R4-R11) of the current running task. ; * R12 save the PRIMASK value of the current running task. ; * NOTE: 1. Before entering the exception handler function, these registers ; * ([NO_NAME,FPSCR,S15-S0],xPSR,PC,LR,R12,R3-R0) have been automatically ; * saved by the CPU in the stack of the current running task. ; * 2. If lazy stacking is enabled, space is reserved on the stack for ; * the floating-point context(FPSCR,S15-S0), but the floating-point state ; * is not saved. when the floating-point instruction(VSTMDBEQ R0!, {D8-D15}) ; * is executed, the floating-point context(FPSCR,S15-S0) is first saved into ; * the space reserved on the stack. In other words, the instruction ; * 'VSTMDBEQ R0!, {D8-D15}' will trigger the CPU to save 'FPSCR,S15-S0' first. ; * ; * The stack of the current running task is as follows: ; * ; * |<=== PUSH: Save the context of the current running task ; * | High addr--->| ; * --+-----------------------------------+-------------------------------------------+--- ; * | R4-R11,PRIMASK,EXC_RETURN,S16-S31 | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * | [ lazy stacking ]| ; * --+-----------------------------------+-------------------------------------------+--- ; * Stack pointer before entering exception--->| ; * |<--- cpu auto saved --->| ; * |<---PSP to R0 ; * |<---Top of the stack, save to g_stLosTask.pstRunTask->pStackPointer ; */ #if defined (__ARMVFP__) ; if FPU exist. TST R14, #0x10 ; if the task using the FPU context, push s16-s31. IT EQ VSTMDBEQ R0!, {D8-D15} STMFD R0!, {R14} ; save EXC_RETURN. #endif STMFD R0!, {R4-R12} ; save the core registers and PRIMASK. ;/** ; * R5,R8. ; */ LDR R5, =g_stLosTask MOV R8, #OS_TASK_STATUS_RUNNING ;/** ; * Save the stack pointer of the current running task to TCB. ; * (g_stLosTask.pstRunTask->pStackPointer = R0) ; */ LDR R6, [R5] STR R0, [R6] ;/** ; * Clear the RUNNING state of the current running task. ; * (g_stLosTask.pstRunTask->usTaskStatus &= ~OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R6, #4] BIC R7, R7, R8 STRH R7, [R6, #4] ;/** ; * Switch the current running task to the next running task. ; * (g_stLosTask.pstRunTask = g_stLosTask.pstNewTask) ; */ LDR R0, [R5, #4] STR R0, [R5] ;/** ; * Set the RUNNING state of the next running task. ; * (g_stLosTask.pstNewTask->usTaskStatus |= OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R0, #4] ORR R7, R7, R8 STRH R7, [R0, #4] ;/** ; * Restore the stack pointer of the next running task from TCB. ; * (R1 = g_stLosTask.pstNewTask->pStackPointer) ; */ LDR R1, [R0] ;/** ; * Restore the stack frame(R4-R11,[S16-S31]) of the next running task. ; * R12 restore the PRIMASK value of the next running task. ; * NOTE: After exiting the exception handler function, these registers ; * (PC,xPSR,R0-R3,R12,LR,[S0-S15,FPSCR,NO_NAME]) will be automatically ; * restored by the CPU from the stack of the next running task. ; * ; * 1. The stack of the next running task is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * --+-----------------------------------+-------------------------------------------+--- ; * | R4-R11,PRIMASK,EXC_RETURN,S16-S31 | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * --+-----------------------------------+-------------------------------------------+--- ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; * ; * 2. If the next running task is run for the first time, the stack is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+---------------------------------+--------------------------------+ ; * | R4-R11, PRIMASK, EXC_RETURN | R0-R3, R12, LR, PC, xPSR | ; * ----------+---------------------------------+--------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; */ LDMFD R1!, {R4-R12} ; restore the core registers and PRIMASK. #if defined (__ARMVFP__) ; if FPU exist. LDMFD R1!, {R14} ; restore EXC_RETURN. TST R14, #0x10 ; if the task using the FPU context, pop s16-s31. IT EQ VLDMIAEQ R1!, {D8-D15} #endif ;/** ; * Set the stack pointer of the next running task to PSP. ; */ MSR PSP, R1 ;/** ; * Restore the interruption state of the next running task. ; */ MSR PRIMASK, R12 BX LR END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m7/keil/los_dispatch_keil.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2016-2018>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT LOS_IntLock EXPORT LOS_IntUnLock EXPORT LOS_IntRestore EXPORT LOS_StartToRun EXPORT osTaskSchedule EXPORT PendSV_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT g_stLosTask IMPORT g_pfnTskSwitchHook IMPORT g_bTaskScheduled ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt Control and State Register. OS_NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception. OS_NVIC_SYSPRI2 EQU 0xE000ED20 ; System Handler Priority Register 2. OS_NVIC_PENDSV_SYSTICK_PRI EQU 0xFFFF0000 ; SysTick + PendSV priority level (lowest). OS_TASK_STATUS_RUNNING EQU 0x0010 ; Task Status Flag (RUNNING). ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** AREA |.text|, CODE, READONLY THUMB REQUIRE8 PRESERVE8 ;**************************************************************************************** ; Function: ; VOID LOS_StartToRun(VOID); ; Description: ; Start the first task, which is the highest priority task in the priority queue. ; Other tasks are started by task scheduling. ;**************************************************************************************** LOS_StartToRun CPSID I ;/** ; * Set PendSV and SysTick prority to the lowest. ; * read ---> modify ---> write-back. ; */ LDR R0, =OS_NVIC_SYSPRI2 LDR R1, =OS_NVIC_PENDSV_SYSTICK_PRI LDR R2, [R0] ORR R1, R1, R2 STR R1, [R0] ;/** ; * Set g_bTaskScheduled = 1. ; */ LDR R0, =g_bTaskScheduled MOV R1, #1 STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask = g_stLosTask.pstNewTask. ; */ LDR R0, =g_stLosTask LDR R1, [R0, #4] STR R1, [R0] ;/** ; * Set g_stLosTask.pstRunTask->usTaskStatus |= OS_TASK_STATUS_RUNNING. ; */ LDR R1, [R0] LDRH R2, [R1, #4] MOV R3, #OS_TASK_STATUS_RUNNING ORR R2, R2, R3 STRH R2, [R1, #4] ;/** ; * Restore the default stack frame(R0-R3,R12,LR,PC,xPSR) of g_stLosTask.pstRunTask to R0-R7. ; * [Initial EXC_RETURN ignore,] return by setting the CONTROL register. ; * ; * The initial stack of the current running task is as follows: ; * ; * POP: Restore the context of the current running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+---------------------------------+--------------------------------+ ; * | R4-R11, PRIMASK, EXC_RETURN | R0-R3, R12, LR, PC, xPSR | ; * ----------+---------------------------------+--------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstRunTask->pStackPointer ; * |<--- skip --->|<--- copy to R0-R7 --->| ; * R12 to PSP--->| ; * Stack pointer after LOS_StartToRun--->| ; */ LDR R12, [R1] ADD R12, R12, #36 ; skip R4-R11, PRIMASK. IF {FPU} != "SoftVFP" ADD R12, R12, #4 ; if FPU exist, skip EXC_RETURN. ENDIF LDMFD R12!, {R0-R7} ;/** ; * Set the stack pointer of g_stLosTask.pstRunTask to PSP. ; */ MSR PSP, R12 ;/** ; * Set the CONTROL register, after schedule start, privilege level and stack = PSP. ; */ MOV R12, #2 MSR CONTROL, R12 ;/** ; * Enable interrupt. (The default PRIMASK value is 0, so enable directly) ; */ MOV LR, R5 CPSIE I ;/** ; * Jump directly to the default PC of g_stLosTask.pstRunTask, the field information ; * of the main function will be destroyed and will never be returned. ; */ BX R6 ;**************************************************************************************** ; Function: ; UINTPTR LOS_IntLock(VOID); ; Description: ; Disable all interrupts except Reset,NMI and HardFault. ; The value of currnet interruption state will be returned to the caller to save. ; ; Function: ; VOID LOS_IntRestore(UINTPTR uvIntSave); ; Description: ; Restore the locked interruption of LOS_IntLock. ; The caller must pass in the value of interruption state previously saved. ;**************************************************************************************** LOS_IntLock MRS R0, PRIMASK CPSID I BX LR LOS_IntUnLock MRS R0, PRIMASK CPSIE I BX LR LOS_IntRestore MSR PRIMASK, R0 BX LR ;**************************************************************************************** ; Function: ; VOID osTaskSchedule(VOID); ; Description: ; Start the task swtich process by software trigger PendSV interrupt. ;**************************************************************************************** osTaskSchedule LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] BX LR ;**************************************************************************************** ; Function: ; VOID PendSV_Handler(VOID); ; Description: ; PendSV interrupt handler, switch the context of the task. ; First: Save the context of the current running task(g_stLosTask.pstRunTask) ; to its own stack. ; Second: Restore the context of the next running task(g_stLosTask.pstNewTask) ; from its own stack. ;**************************************************************************************** PendSV_Handler ;/** ; * R12: Save the interruption state of the current running task. ; * Disable all interrupts except Reset,NMI and HardFault ; */ MRS R12, PRIMASK CPSID I ;/** ; * Call task switch hook. ; */ LDR R2, =g_pfnTskSwitchHook LDR R2, [R2] CBZ R2, TaskSwitch PUSH {R12, LR} BLX R2 POP {R12, LR} TaskSwitch ;/** ; * R0 = now stack pointer of the current running task. ; */ MRS R0, PSP ;/** ; * Save the stack frame([S16-S31],R4-R11) of the current running task. ; * R12 save the PRIMASK value of the current running task. ; * NOTE: 1. Before entering the exception handler function, these registers ; * ([NO_NAME,FPSCR,S15-S0],xPSR,PC,LR,R12,R3-R0) have been automatically ; * saved by the CPU in the stack of the current running task. ; * 2. If lazy stacking is enabled, space is reserved on the stack for ; * the floating-point context(FPSCR,S15-S0), but the floating-point state ; * is not saved. when the floating-point instruction(VSTMDBEQ R0!, {D8-D15}) ; * is executed, the floating-point context(FPSCR,S15-S0) is first saved into ; * the space reserved on the stack. In other words, the instruction ; * 'VSTMDBEQ R0!, {D8-D15}' will trigger the CPU to save 'FPSCR,S15-S0' first. ; * ; * The stack of the current running task is as follows: ; * ; * |<=== PUSH: Save the context of the current running task ; * | High addr--->| ; * --+-----------------------------------+-------------------------------------------+--- ; * | R4-R11,PRIMASK,EXC_RETURN,S16-S31 | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * | [ lazy stacking ]| ; * --+-----------------------------------+-------------------------------------------+--- ; * Stack pointer before entering exception--->| ; * |<--- cpu auto saved --->| ; * |<---PSP to R0 ; * |<---Top of the stack, save to g_stLosTask.pstRunTask->pStackPointer ; */ IF {FPU} != "SoftVFP" ; if FPU exist. TST R14, #0x10 ; if the task using the FPU context, push s16-s31. IT EQ VSTMDBEQ R0!, {D8-D15} STMFD R0!, {R14} ; save EXC_RETURN. ENDIF STMFD R0!, {R4-R12} ; save the core registers and PRIMASK. ;/** ; * R5,R8. ; */ LDR R5, =g_stLosTask MOV R8, #OS_TASK_STATUS_RUNNING ;/** ; * Save the stack pointer of the current running task to TCB. ; * (g_stLosTask.pstRunTask->pStackPointer = R0) ; */ LDR R6, [R5] STR R0, [R6] ;/** ; * Clear the RUNNING state of the current running task. ; * (g_stLosTask.pstRunTask->usTaskStatus &= ~OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R6, #4] BIC R7, R7, R8 STRH R7, [R6, #4] ;/** ; * Switch the current running task to the next running task. ; * (g_stLosTask.pstRunTask = g_stLosTask.pstNewTask) ; */ LDR R0, [R5, #4] STR R0, [R5] ;/** ; * Set the RUNNING state of the next running task. ; * (g_stLosTask.pstNewTask->usTaskStatus |= OS_TASK_STATUS_RUNNING) ; */ LDRH R7, [R0, #4] ORR R7, R7, R8 STRH R7, [R0, #4] ;/** ; * Restore the stack pointer of the next running task from TCB. ; * (R1 = g_stLosTask.pstNewTask->pStackPointer) ; */ LDR R1, [R0] ;/** ; * Restore the stack frame(R4-R11,[S16-S31]) of the next running task. ; * R12 restore the PRIMASK value of the next running task. ; * NOTE: After exiting the exception handler function, these registers ; * (PC,xPSR,R0-R3,R12,LR,[S0-S15,FPSCR,NO_NAME]) will be automatically ; * restored by the CPU from the stack of the next running task. ; * ; * 1. The stack of the next running task is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * --+-----------------------------------+-------------------------------------------+--- ; * | R4-R11,PRIMASK,EXC_RETURN,S16-S31 | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * --+-----------------------------------+-------------------------------------------+--- ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; * ; * 2. If the next running task is run for the first time, the stack is as follows: ; * ; * POP: Restore the context of the next running task ===>| ; * High addr--->| ; * Bottom of the stack--->| ; * ----------+---------------------------------+--------------------------------+ ; * | R4-R11, PRIMASK, EXC_RETURN | R0-R3, R12, LR, PC, xPSR | ; * ----------+---------------------------------+--------------------------------+ ; * |<---Top of the stack, restored from g_stLosTask.pstNewTask->pStackPointer ; * R1 to PSP--->| ; * |<--- cpu auto restoring --->| ; * Stack pointer after exiting exception--->| ; */ LDMFD R1!, {R4-R12} ; restore the core registers and PRIMASK. IF {FPU} != "SoftVFP" ; if FPU exist. LDMFD R1!, {R14} ; restore EXC_RETURN. TST R14, #0x10 ; if the task using the FPU context, pop s16-s31. IT EQ VLDMIAEQ R1!, {D8-D15} ENDIF ;/** ; * Set the stack pointer of the next running task to PSP. ; */ MSR PSP, R1 ;/** ; * Restore the interruption state of the next running task. ; */ MSR PRIMASK, R12 BX LR ALIGN END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m7/keil/los_hw_exc_keil.S ================================================ ;---------------------------------------------------------------------------- ; Copyright (c) <2013-2015>, ; All rights reserved. ; Redistribution and use in source and binary forms, with or without modification, ; are permitted provided that the following conditions are met: ; 1. Redistributions of source code must retain the above copyright notice, this list of ; conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, this list ; of conditions and the following disclaimer in the documentation and/or other materials ; provided with the distribution. ; 3. Neither the name of the copyright holder nor the names of its contributors may be used ; to endorse or promote products derived from this software without specific prior written ; permission. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;---------------------------------------------------------------------------*/ ;---------------------------------------------------------------------------- ; Notice of Export Control Law ; =============================================== ; Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; applicable export control laws and regulations. ;---------------------------------------------------------------------------*/ ;**************************************************************************************** ; CODE GENERATION DIRECTIVES ;**************************************************************************************** PRESERVE8 AREA |.text|, CODE, READONLY THUMB ;**************************************************************************************** ; EXPORT FUNCTIONS ;**************************************************************************************** EXPORT NMI_Handler EXPORT HardFault_Handler EXPORT MemManage_Handler EXPORT BusFault_Handler EXPORT UsageFault_Handler EXPORT SVC_Handler ;**************************************************************************************** ; EXTERN PARAMETERS ;**************************************************************************************** IMPORT osExcHandleEntry IMPORT g_uwExcTbl IMPORT g_bTaskScheduled ;**************************************************************************************** ; EQU ;**************************************************************************************** OS_EXC_CAUSE_NMI EQU 18 OS_EXC_CAUSE_HARDFAULT EQU 19 OS_EXC_CAUSE_MEMFAULT EQU 20 OS_EXC_CAUSE_BUSFAULT EQU 21 OS_EXC_CAUSE_USAGEFAULT EQU 22 OS_EXC_CAUSE_SVC EQU 23 HF_DEBUGEVT EQU 24 HF_VECTBL EQU 25 FLAG_ADDR_VALID EQU 0x10000 ; bit 16 FLAG_HWI_ACTIVE EQU 0x20000 ; bit 17 FLAG_NO_FLOAT EQU 0x10000000 ; bit 28 OS_NVIC_CFSR EQU 0xE000ED28 ; include BusFault/MemFault/UsageFault State Regeister OS_NVIC_HFSR EQU 0xE000ED2C ; HardFault State Regeister OS_NVIC_BFAR EQU 0xE000ED38 OS_NVIC_MMFAR EQU 0xE000ED34 OS_NVIC_ACT_BASE EQU 0xE000E300 OS_NVIC_SHCSRS EQU 0xE000ED24 OS_NVIC_SHCSR_MASK EQU 0xC00 ; SYSTICKACT and PENDSVACT ;**************************************************************************************** ; Function: ; VOID NMI_Handler(VOID); ; Description: ; NMI Handler. ;**************************************************************************************** NMI_Handler ;/** ; * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +------------------------------------------------------+------------------------+ ; * | 31-8 | 7-0 | ; * +------------------------------------------------------+------------------------+ ; * | --- | OS_EXC_CAUSE_NMI | ; * +------------------------------------------------------+------------------------+ ; * < R1 >: invalid ; */ MOV R0, #OS_EXC_CAUSE_NMI MOV R1, #0 B osExcDispatch ;**************************************************************************************** ; Function: ; VOID HardFault_Handler(VOID); ; Description: ; HardFault Handler. ;**************************************************************************************** HardFault_Handler ;/** ; * Check HardFault state register. ; * ; * HFSR: ; * +----------+--------+--------+--------+-------+ ; * | 31 | 30 | 29 - 2 | 1 | 0 | ; * +----------+--------+--------+--------+-------+ ; * | DEBUGEVT | FORCED | -- | VECTBL | -- | ; * +----------+--------+--------+--------+-------+ ; */ MOV R0, #OS_EXC_CAUSE_HARDFAULT LDR R2, =OS_NVIC_HFSR LDR R2, [R2] ;/** ; * Check whether HardFault are triggered by debugging events. ; * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +----------------------------------------+-------------+------------------------+ ; * | 31-16 | 15-8 | 7-0 | ; * +----------------------------------------+-------------+------------------------+ ; * | --- | HF_DEBUGEVT | OS_EXC_CAUSE_HARDFAULT | ; * +----------------------------------------+-------------+------------------------+ ; * < R1 >: invalid ; */ MOV R1, #HF_DEBUGEVT ORR R0, R0, R1, LSL #0x8 TST R2, #0x80000000 BNE osExcDispatch ; DEBUGEVT ;/** ; * Check whether HardFault is caused by the failure of the fetch vector. ; * Before executing instruction 'BNE osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +----------------------------------------+-------------+------------------------+ ; * | 31-16 | 15-8 | 7-0 | ; * +----------------------------------------+-------------+------------------------+ ; * | --- | HF_VECTBL | OS_EXC_CAUSE_HARDFAULT | ; * +----------------------------------------+-------------+------------------------+ ; * < R1 >: invalid ; */ AND R0, R0, #0x000000FF MOV R1, #HF_VECTBL ORR R0, R0, R1, LSL #0x8 TST R2, #0x00000002 BNE osExcDispatch ; VECTBL ;/** ; * If it`s not DEBUGEVT and VECTBL, that is FORCED, then read the CFSR register to ; * check BusFault, MemFault and UsageFault. ; * R0: OS_EXC_CAUSE_HARDFAULT ; * ; * CFSR: ; * +----------------+--------+--------+ ; * | 31-16 | 15-8 | 7-0 | ; * +----------------+--------+--------+ ; * | UFSR | BFSR | MFSR | ; * +----------------+--------+--------+ ; */ AND R0, R0, #0x000000FF LDR R2, =OS_NVIC_CFSR LDR R2, [R2] TST R2, #0x8000 ; BFSR->BFARVALID BNE _HFBusFault ; BusFault TST R2, #0x80 ; MFSR->MMARVALID BNE _HFMemFault ; MemFault ;/** ; * BFARVALID and MMARVALID flag both invalid. ; * R12: 0 --- The error address is invalid. ; */ MOV R12, #0 B osHFExcCommonBMU ;/** ; * BFARVALID flag valid, read BFAR register. ; * R1 : BFAR value --- The address value of a bus error. ; * R12: The error address is valid. ; */ _HFBusFault LDR R1, =OS_NVIC_BFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID B osHFExcCommonBMU ;/** ; * MMARVALID flag valid, read MMFAR register. ; * R1 : MMFAR value --- The address value of memory management error. ; * R12: The error address is valid. ; */ _HFMemFault LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] MOV R12, #FLAG_ADDR_VALID ;/** ; * osHFExcCommonBMU: --- Get specific error status from table g_uwExcTbl, stored in R0. ; * Before executing instruction 'B osExcDispatch', the value of R0 is as follows. ; * < R0 >: ; * +-------------------+-----------------+------------------+------------------------+ ; * | 31-17 | 16 | 15-8 | 7-0 | ; * +-------------------+-----------------+------------------+------------------------+ ; * | --- | FLAG_ADDR_VALID | Error state code | OS_EXC_CAUSE_HARDFAULT | ; * | | or | in | | ; * | | 0(invalid) | table g_uwExcTbl | | ; * +-------------------+-----------------+------------------+------------------------+ ; * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, ; * else invalid. ; */ osHFExcCommonBMU CLZ R2, R2 LDR R3, =g_uwExcTbl ADD R3, R3, R2 LDRB R2, [R3] ORR R0, R0, R2, LSL #0x8 ORR R0, R0, R12 B osExcDispatch ;**************************************************************************************** ; Function: ; VOID SVC_Handler(VOID); ; Description: ; SVC Handler. ;**************************************************************************************** SVC_Handler TST LR, #0x4 ; EXC_RETURN[b2] --- PSP or MSP ITE EQ MRSEQ R0, MSP MRSNE R0, PSP LDR R1, [R0, #24] ; The PC value in the stack frame LDRB R0, [R1, #-2] ; R0: The number of SVC (0 - 255) MOV R1, #0 ;B osExcDispatch _SvcLoop B _SvcLoop ;**************************************************************************************** ; Function: ; VOID BusFault_Handler(VOID); ; Description: ; BusFault Handler. ;**************************************************************************************** BusFault_Handler LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_BUSFAULT TST R0, #0x8000 ; BFSR->BFARVALID BEQ _ExcBusNoADDR LDR R1, =OS_NVIC_BFAR LDR R1, [R1] ; R1: The value of BFAR MOV R12, #FLAG_ADDR_VALID ; R12: BusFault addr valid AND R0, R0, #0x3F00 ; R0: Reserved the b13-b8 of the BFSR B osExcCommonBMU _ExcBusNoADDR MOV R12, #0 ; R12: BusFault addr invalid AND R0, R0, #0x3F00 ; R0: Reserved the b13-b8 of the BFSR B osExcCommonBMU ;**************************************************************************************** ; Function: ; VOID MemManage_Handler(VOID); ; Description: ; MemManage Handler. ;**************************************************************************************** MemManage_Handler LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_MEMFAULT TST R0, #0x80 ; MFSR->MMARVALID BEQ _ExcMemNoADDR LDR R1, =OS_NVIC_MMFAR LDR R1, [R1] ; R1: The value of MMFAR MOV R12, #FLAG_ADDR_VALID ; R12: MemFault addr valid AND R0, R0, #0x3B ; R0: Reserved the b5-b0 of the MFSR B osExcCommonBMU _ExcMemNoADDR MOV R12, #0 ; R12: MemFault addr invalid AND R0, R0, #0x3B ; R0: Reserved the b5-b0 of the MFSR B osExcCommonBMU ;**************************************************************************************** ; Function: ; VOID UsageFault_Handler(VOID); ; Description: ; UsageFault Handler. ;**************************************************************************************** UsageFault_Handler LDR R0, =OS_NVIC_CFSR LDR R0, [R0] LDR R2, =OS_EXC_CAUSE_USAGEFAULT MOV R1, #0x030F LSL R1, R1, #16 AND R0, R0, R1 ; R0: reserved UFSR MOV R12, #0 ; R12: Fault addr invalid ;/** ; * osExcCommonBMU: BusFault_Handler,MemManage_Handler and UsageFault_Handler share. ; * Get specific error status from table g_uwExcTbl, stored in R0. ; * Before executing osExcDispatch, the value of R0 is as follows. ; * < R0 >: ; * +-------------------+-----------------+------------------+------------------------+ ; * | 31-17 | 16 | 15-8 | 7-0 | ; * +-------------------+-----------------+------------------+------------------------+ ; * | --- | FLAG_ADDR_VALID | Error state code |OS_EXC_CAUSE_BUSFAULT or| ; * | | or | in |OS_EXC_CAUSE_MEMFAULT or| ; * | | 0(invalid) | table g_uwExcTbl |OS_EXC_CAUSE_USAGEFAULT | ; * +-------------------+-----------------+------------------+------------------------+ ; * < R1 >: The value of BFAR or MMFAR if the bit16(FLAG_ADDR_VALID) of R0 is set to 1, ; * else invalid. ; */ osExcCommonBMU CLZ R0, R0 LDR R3, =g_uwExcTbl ADD R3, R3, R0 LDRB R0, [R3] LSL R0, R0, #0x8 ORR R0, R0, R2 ORR R0, R0, R12 ;**************************************************************************************** ; osExcDispatch: NMI_Handler, HardFault_Handler, SVC_Handler, BusFault_Handler, MemManage_Handler, ; UsageFault_Handler sharing. ;**************************************************************************************** ;/** ; * When executing osExcDispatch, R0, R1 will be used. ; * The possible values of R0 and R1 are as follows. ; * ; * < R0 >: ; * +----------------+-----------------+---------------------+------------------------+ ; * | 31-17 | 16 | 15-8 | 7-0 | ; * +----------------+-----------------+---------------------+------------------------+ ; * | | FLAG_ADDR_VALID | Error state code in | OS_EXC_CAUSE_HARDFAULT | ; * | --- | or | table g_uwExcTbl |or OS_EXC_CAUSE_MEMFAULT| ; * | | 0(invalid) | or HF_DEBUGEVT |or OS_EXC_CAUSE_BUSFAULT| ; * | | | or HF_VECTBL |or OS_EXC_CAUSE_NMI or | ; * | | | | OS_EXC_CAUSE_USAGEFAULT| ; * +----------------+-----------------+---------------------+------------------------+ ; * b17: FLAG_HWI_ACTIVE ; * b28: FLAG_NO_FLOAT ; * NOTE: b17 and b28 will be set later. ; * ; * < R1 >: ; * If the bit16 of R0 is 1, then R1 is the value of BFAR or MMFAR, otherwise the ; * value in R1 is invalid. ; * ; */ osExcDispatch LDR R2, =OS_NVIC_ACT_BASE MOV R12, #8 ; #8: externel interrupt active check loop counter(#0 - #239) _hwiActiveCheck LDR R3, [R2] ; R3 store the value of externel interrupt active status CMP R3, #0 BEQ _hwiActiveCheckNext ;/** ; * Exception occured in external interrupt. ; */ ORR R0, R0, #FLAG_HWI_ACTIVE ; R0[b17] = 1, externel interrupt active valid &&&&&&&&&& RBIT R2, R3 ; bit reversal CLZ R2, R2 RSB R12, R12, #8 ; R12 = 8 - R12 ADD R2, R2, R12, LSL #5 ; R2: external interrupt number as uwPid ;/** ; * Interrupts and initialization phase always use MSP. ; */ _ExcInMSP TST LR, #0x10 ; EXC_RETURN[b4] --- FPU(0) or without FPU(1) BNE _NoFloatInMsp ;/** ; * Before executing instruction 'B _handleEntry', MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | S16-S31,R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * +--------------------------------------------------------------------------------+--------- ; * |<---R13 Initial R13--->|<--- #104 --->|<---SAVED_SP ; * | (CPU auto saved) | ; * ; */ ADD R3, R13, #104 ; #104: skip [R0-xPSR,D0-D7,FPSCR,NO_NAME] PUSH {R3} ; push [SAVED_SP]: MSP+104 = Stack pointer in MSP before entering the exception MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK to MSP VPUSH {D8-D15} ; push D8-D15 to MSP B _handleEntry ;/** ; * Before executing instruction 'B _handleEntry', MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | R4-R11,PRIMASK,SAVED_SP | R0-R3,R12,LR,PC,xPSR | ; * +--------------------------------------------------------------------------------+--------- ; * R13--->| Initial R13--->|<--- #32 --->|<---SAVED_SP ; * | (CPU auto saved) | ; * ; */ _NoFloatInMsp ADD R3, R13, #32 ; #32: skip [R0-R3,R12,LR,PC,xPSR] PUSH {R3} ; push [SAVED_SP]: MSP+32 = Stack pointer in MSP before entering the exception MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK to MSP ORR R0, R0, #FLAG_NO_FLOAT ; R0[b28] = 1, no FPU &&&&&&&&&& B _handleEntry _hwiActiveCheckNext ADD R2, R2, #4 ; next NVIC ACT ADDR SUBS R12, R12, #1 BNE _hwiActiveCheck ;/** ; * Not in externel interrupt, check whether it is SysTick or PendSV. ; */ LDR R2, =OS_NVIC_SHCSRS LDRH R2,[R2] LDR R3,=OS_NVIC_SHCSR_MASK AND R2, R2, R3 CMP R2, #0 BNE _ExcInMSP ; SysTick or PendSV active ;/** ; * Check whether an exception occurs during the initialization phase. ; * If g_bTaskScheduled == 0, it is in the initialization phase. ; */ LDR R2, =g_bTaskScheduled LDR R2, [R2] TST R2, #1 BEQ _ExcInMSP ; initialization phase use MSP ;/** ; * Exception occured in Task. ; */ TST LR, #0x10 BNE _NoFloatInPsp ;/** ; * Before executing _handleEntry, MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | S16-S31,R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME | ; * +--------------------------------------------------------------------------------+--------- ; * |<---R13 |<--- #104 --->|<---Initial R13 ; * | (copied from PSP) | ; * R2(no use)--->| ; * ; * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR,NO_NAME. ; */ MOV R2, R13 SUB R2, R2, #8 ; #8: reserved for [FPSCR,NO_NAME] SUB R13, #104 ; #104: MSP reserved, used to store stack frame in PSP MRS R3, PSP ADD R12, R3, #104 ; PSP+104 = Stack pointer of the task before entering the exception PUSH {R12} ; push task SP to MSP MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK of the current running task to MSP VPUSH {D8-D15} ; push D8-D15 of the currnent running task to MSP ;/* Copy stack frame from the stack of the current running task to MSP */ LDMFD R3!, {R4-R11} ; restore stack frame[R0-xPSR] of PSP to R4-R11 VLDMIA R3!, {D8-D15} ; restore stack frame[D0-D7] of PSP to D8-D15 VSTMDB R2!, {D8-D15} ; save stack frame[D0-D7] to MSP STMFD R2!, {R4-R11} ; save stack frame[R0-xPSR] to MSP LDMFD R3, {R4-R5} ; restore stack frame[FPSCR,NO_NAME] to R4-R5 ADD R2, R2, #104 ; skip stack frame STMFD R2, {R4-R5} ; save stack frame[FPSCR,NO_NAME] to MSP B _handleEntry ;/** ; * Before executing _handleEntry, MSP is as follows. ; * MSP: ; * High addr--->| ; * +--------------------------------------------------------------------------------+--------- ; * | R4-R11,PRIMASK,TASK_SP | R0-R3,R12,LR,PC,xPSR | ; * +--------------------------------------------------------------------------------+--------- ; * R13--->| |<--- #32 --->|<---Initial R13 ; * | (copied from PSP) | ; * |<---R2(no use) ; * ; * NOTE: stack frame: R0-R3,R12,LR,PC,xPSR. ; */ _NoFloatInPsp MOV R2, R13 SUB R13, #32 ; #32: MSP reserved, used to store stack frame in PSP MRS R3, PSP ADD R12, R3, #32 ; PSP+32 = Stack pointer of the task before entering the exception PUSH {R12} ; push task SP to MSP MRS R12, PRIMASK PUSH {R4-R12} ; push R4-R11,PRIMASK of the current running task to MSP ;/* Copy stack frame from the stack of the current running task to MSP */ LDMFD R3, {R4-R11} ; restore stack frame of PSP to R4-R11 STMFD R2!, {R4-R11} ; save stack frame to MSP ORR R0, R0, #FLAG_NO_FLOAT ; R0[b28] = 1, no FPU &&&&&&&&&& ;/** ; * _handleEntry: Call osExcHandleEntry ; * param1: R0 --- b28: FLAG_NO_FLOAT. ; * b17: FLAG_HWI_ACTIVE. ; * b16: FLAG_ADDR_VALID. ; * b15-b8: Error state code in table g_uwExcTbl or HF_DEBUGEVT or HF_VECTBL. ; * b7-b0: OS_EXC_CAUSE_HARDFAULT or OS_EXC_CAUSE_NMI or OS_EXC_CAUSE_MEMFAULT ; * or OS_EXC_CAUSE_BUSFAULT or OS_EXC_CAUSE_USAGEFAULT. ; * param2: R1 --- The value of BFAR or MMFAR if R0[b16] = 1, otherwise invalid. ; * param3: R2 --- external interrupt number(0-239) if R0[b17] = 1, otherwise invalid. ; * param4: R3 --- Point to the top of the stack(R4 or S16) that the exception stack frame in MSP. ; */ _handleEntry MOV R3, R13 CPSID I CPSID F B osExcHandleEntry NOP ALIGN END ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m7/los_exc.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "los_exc.inc" #include "los_task.ph" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cpluscplus */ #endif /* __cpluscplus */ //extern ST_LOS_TASK g_stLosTask; #if (LOSCFG_PLATFORM_EXC == YES) UINT32 g_uwCurNestCount = 0; EXC_INFO_S m_stExcInfo; /* * CFSR register, include UFSR,BFSR and MFSR. * * +----------------------------------------------------------------------------------+ * | UFSR | * |-----------+-----------+-----------+-------+------+-------+----------+------------| * | 31 - 26 | 25 | 24 | 23-20 | 19 | 18 | 17 | 16 | * |-----------+-----------+-----------+-------+------+-------+----------+------------| * | --- | DIVBYZERO | UNALIGNED | --- | NOCP | INVPC | INVSTATE | UNDEFINSTR | * +----------------------------------------------------------------------------------+ * * +----------------------------------------------------------------------------------+ * | BFSR | * |-----------+-----+--------+--------+----------+-------------+-----------+---------| * | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | * |-----------+-----+--------+--------+----------+-------------+-----------+---------| * | BFARVALID | --- | LSPERR | STKERR | UNSTKERR | IMPRECISERR | PRECISERR | IBUSERR | * +----------------------------------------------------------------------------------+ * * +----------------------------------------------------------------------------------+ * | MFSR | * |-----------+-------+---------+---------+-----------+-------+----------+-----------| * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | * |-----------+-------+---------+---------+-----------+-------+----------+-----------| * | MMARVALID | --- | MLSPERR | MSTKERR | MUNSTKERR | --- | DACCVIOL | ICACCVIOL | * +----------------------------------------------------------------------------------+ */ UINT8 g_uwExcTbl[32] = { 0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED, 0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR, 0, 0, OS_EXC_BF_LSPERR, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR, 0, 0, OS_EXC_MF_MLSPERR, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL }; #if (LOSCFG_SAVE_EXC_INFO == YES) VOID *m_puwExcContent; UINT32 g_uwArraySize = 0; EXC_INFO_ARRAY_S m_stExcArray[OS_EXC_TYPE_MAX - 1]; static VOID osExcSave2DDR(VOID); #endif extern VOID LOS_Reboot(VOID); /***************************************************************************** Function : osExcInfoDisplay Description : EXC info display Input : pstExc --- Pointer to the EXC data Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osExcInfoDisplay(EXC_INFO_S *pstExc) { PRINT_ERR("Phase = 0x%x\n", pstExc->usPhase); PRINT_ERR("Type = 0x%x\n", pstExc->usType); PRINT_ERR("FaultAddr = 0x%x\n", pstExc->uwFaultAddr); PRINT_ERR("ThrdPid = 0x%x\n", pstExc->uwThrdPid); PRINT_ERR("R0 = 0x%x\n", pstExc->pstContext->uwR0); PRINT_ERR("R1 = 0x%x\n", pstExc->pstContext->uwR1); PRINT_ERR("R2 = 0x%x\n", pstExc->pstContext->uwR2); PRINT_ERR("R3 = 0x%x\n", pstExc->pstContext->uwR3); PRINT_ERR("R4 = 0x%x\n", pstExc->pstContext->uwR4); PRINT_ERR("R5 = 0x%x\n", pstExc->pstContext->uwR5); PRINT_ERR("R6 = 0x%x\n", pstExc->pstContext->uwR6); PRINT_ERR("R7 = 0x%x\n", pstExc->pstContext->uwR7); PRINT_ERR("R8 = 0x%x\n", pstExc->pstContext->uwR8); PRINT_ERR("R9 = 0x%x\n", pstExc->pstContext->uwR9); PRINT_ERR("R10 = 0x%x\n", pstExc->pstContext->uwR10); PRINT_ERR("R11 = 0x%x\n", pstExc->pstContext->uwR11); PRINT_ERR("R12 = 0x%x\n", pstExc->pstContext->uwR12); PRINT_ERR("PriMask = 0x%x\n", pstExc->pstContext->uwPriMask); PRINT_ERR("SP = 0x%x\n", pstExc->pstContext->uwSP); PRINT_ERR("LR = 0x%x\n", pstExc->pstContext->uwLR); PRINT_ERR("PC = 0x%x\n", pstExc->pstContext->uwPC); PRINT_ERR("xPSR = 0x%x\n", pstExc->pstContext->uwxPSR); PRINT_ERR("\nplease use the addr2line tool to analyze the call stack on PC:\n"); PRINT_ERR("addr2line -e (xxx.axf/xxx.elf/xxx.out) -a -f "); for (UINT32 i = 0; i < pstExc->uwCallStackDepth; i++) { printf("%#x ", pstExc->uwCallStack[i]); } printf("\n"); return; } /***************************************************************************** Function : osExcCallStackAnalysis Description : Call stack analysis Input : pstExc --- point to exception info Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osExcCallStackAnalysis(EXC_INFO_S *pstExc) { UINT32 uwSP; UINT32 uwLR; UINT32 uwPC; UINT32 uwStackStartAddr; UINT32 uwStackSize; UINT32 uwDepth = 0; BOOL bFirstLrValid = FALSE; uwSP = pstExc->pstContext->uwSP; /* sp pointer before entering exception */ /* * save first and second depth * first: PC before entering exception * second: (LR - 4) before entering exception * NOTE: If an exception occurs in the interrupt, LR may be EXC_RETURN, so we must make sure * that LR is valid, exclude EXC_RETURN. */ pstExc->uwCallStack[uwDepth++] = pstExc->pstContext->uwPC; if ((pstExc->pstContext->uwLR >= LOSCFG_EXC_CODE_START_ADDR) && \ (pstExc->pstContext->uwLR <= LOSCFG_EXC_CODE_START_ADDR + LOSCFG_EXC_CODE_SIZE)) { pstExc->uwCallStack[uwDepth++] = pstExc->pstContext->uwLR - sizeof(VOID *); /* lr = pc + 4 */ bFirstLrValid = TRUE; } /* * get the start address and size of the stack before entering the exception */ if (pstExc->usPhase == OS_EXC_IN_TASK) /* task use PSP */ { uwStackStartAddr = g_stLosTask.pstRunTask->uwTopOfStack; uwStackSize = g_stLosTask.pstRunTask->uwStackSize; } else /* init and interrupt use MSP */ { uwStackStartAddr = LOSCFG_EXC_MSP_START_ADDR; uwStackSize = LOSCFG_EXC_MSP_SIZE; } /* * check stack overflow, if so, compensate for overflow, readjust stack start address and size. */ if (uwSP < uwStackStartAddr) /* stack top overflow */ { if (pstExc->usPhase == OS_EXC_IN_TASK) { PRINT_ERR("task %s stack top overflow\n", g_stLosTask.pstRunTask->pcTaskName); } else { PRINT_ERR("MSP top overflow\n"); } uwStackSize += (uwStackStartAddr - uwSP); /* compensate overflow size */ uwStackStartAddr = uwSP; /* readjust stack start address */ } /* * Traverses the entire stack from the top of the stack to the bottom of the stack, * find all LR. */ for (; uwSP < uwStackStartAddr + uwStackSize; uwSP += sizeof(UINT32)) { uwLR = *(UINT32 *)uwSP; if (uwLR % 2 == 0) /* Thumb instruction, LR bit0 == 1 */ { continue; } /* * It may be LR, which must be further determined based on the start address * and end address of the code segment. */ if ((uwLR >= LOSCFG_EXC_CODE_START_ADDR) && (uwLR <= LOSCFG_EXC_CODE_START_ADDR + LOSCFG_EXC_CODE_SIZE) \ && (uwDepth < LOSCFG_EXC_CALL_STACK_ANALYSIS_MAX_DEPTH)) { uwPC = uwLR - sizeof(VOID *); /* lr = pc + 4 */ /* the second depth(first LR) has been saved */ if ((uwDepth == 2) && (uwPC == pstExc->uwCallStack[1]) && (bFirstLrValid == TRUE)) { continue; } pstExc->uwCallStack[uwDepth++] = uwPC; } } pstExc->uwCallStackDepth = uwDepth; /* save call stack depth */ return; } /***************************************************************************** Function : osExcHandleEntry Description : EXC handler entry Input : uwExcType --- EXC type : uwFaultAddr --- The address of an accurate address access error : uwPid --- Interrupt number : puwExcBufAddr --- Point to the stack frame without FPU Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osExcHandleEntry(UINT32 uwExcType, UINT32 uwFaultAddr, UINT32 uwPid, EXC_CONTEXT_S *pstExcBufAddr) { /* uwExcType high 16 bits: 0x01 - uwFaultAddr valid, 0x02 - in hwi */ UINT16 usTmpFlag = (uwExcType >> 16) & 0xFFFF; g_uwCurNestCount++; #if (LOSCFG_PLATFORM_HWI == YES) extern UINT32 g_vuwIntCount; g_vuwIntCount++; #endif /* Save interrupt nesting times */ m_stExcInfo.usNestCnt = (UINT16)g_uwCurNestCount; /* uwExcType low 16 bits: exc type */ m_stExcInfo.usType = (UINT16)uwExcType & 0xFFFF; #if (LOSCFG_SAVE_EXC_INFO == YES) /* Initializing a pointer to save an exception context */ m_puwExcContent = (UINT32 *)m_aucTaskArray; #endif /* Save the fault address when an exception occurs if it is valid */ if (usTmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) { m_stExcInfo.uwFaultAddr = uwFaultAddr; } else { m_stExcInfo.uwFaultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR; } /* Save the phase of the exception */ extern BOOL g_bTaskScheduled; if (g_bTaskScheduled && (NULL != g_stLosTask.pstRunTask)) { if (usTmpFlag & OS_EXC_FLAG_IN_HWI) { m_stExcInfo.usPhase = OS_EXC_IN_HWI; m_stExcInfo.uwThrdPid = uwPid; /* interrupt number */ } else { m_stExcInfo.usPhase = OS_EXC_IN_TASK; m_stExcInfo.uwThrdPid = g_stLosTask.pstRunTask->uwTaskID; /* task id */ } } else { m_stExcInfo.usPhase = OS_EXC_IN_INIT; m_stExcInfo.uwThrdPid = 0xffffffff; } /* uwExcType BIT_28: Wether or not to use FPU */ if(uwExcType & OS_EXC_FLAG_NO_FLOAT) { m_stExcInfo.usFpuContext = 0; #if FPU_EXIST /* NOTE: S16-S31, S0-S15,FPSCR,NO_NAME invalid */ m_stExcInfo.pstContext = (EXC_CONTEXT_S *)((UINT8 *)pstExcBufAddr - 64); /* point to S16 */ #else m_stExcInfo.pstContext = pstExcBufAddr; /* point to uwR4 */ #endif } else { m_stExcInfo.usFpuContext = 1; m_stExcInfo.pstContext = pstExcBufAddr; /* point to S16 */ } osExcCallStackAnalysis(&m_stExcInfo); #if (LOSCFG_SAVE_EXC_INFO == YES) osExcSave2DDR(); #endif osExcInfoDisplay(&m_stExcInfo); LOS_Reboot(); } #if (LOSCFG_SAVE_EXC_INFO == YES) /***************************************************************************** Function : osExcSaveIntStatus Description : Save NVIC register group Input : None Output : None Return : None *****************************************************************************/ static VOID osExcSaveIntStatus(VOID) { /* Save exc type */ *((UINT32 *)m_puwExcContent) = OS_EXC_TYPE_NVIC; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save total size of NVIC */ *((UINT32 *)m_puwExcContent) = 0x164; // = OS_NVIC_INT_ENABLE_SIZE + OS_NVIC_INT_PEND_SIZE + OS_NVIC_INT_ACT_SIZE + OS_NVIC_INT_PRI_SIZE + 12 + 4 + 4 m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save interrupt enable register group (start addr: 0xE000E100, size: 32bytes, CMSIS-Core: NVIC->ISER[0 - 7]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_SETENA_BASE, OS_NVIC_INT_ENABLE_SIZE); m_puwExcContent =(UINT8 *)m_puwExcContent + OS_NVIC_INT_ENABLE_SIZE; /* Save interrupt pend register group (start addr: 0xE000E200, size: 32bytes, CMSIS-Core: NVIC->ISPR[0 - 7]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_SETPEND_BASE, OS_NVIC_INT_PEND_SIZE); m_puwExcContent = (UINT8 *)m_puwExcContent + OS_NVIC_INT_PEND_SIZE; /* Save interrupt active status register group (start addr: 0xE000E300, size: 32bytes, CMSIS-Core: NVIC->IABR[0 - 7]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_INT_ACT_BASE, OS_NVIC_INT_ACT_SIZE); m_puwExcContent = (UINT8 *)m_puwExcContent + OS_NVIC_INT_ACT_SIZE; /* Save interrupt priority register group (start addr: 0xE000E400, size: 240bytes), CMSIS-Core: NVIC->IP[0 - 239] */ memcpy(m_puwExcContent, (const void *)OS_NVIC_PRI_BASE, OS_NVIC_INT_PRI_SIZE); m_puwExcContent = (UINT8 *)m_puwExcContent + OS_NVIC_INT_PRI_SIZE; /* Save system exception priority register group (start addr: 0xE000ED18, size: 12bytes, CMSIS-Core: SCB->SHP[0 - 11]) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_EXCPRI_BASE, 12); m_puwExcContent = (UINT8 *)m_puwExcContent + 12; /* Save system processing control and state register group (start addr: 0xE000ED24, size: 4bytes, CMSIS-Core: SCB->SHCSR) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_SHCSR, 4); m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save interrupt control and status register group (start addr: 0xE000ED04, size: 4bytes, CMSIS-Core: SCB->ICSR) */ memcpy(m_puwExcContent, (const void *)OS_NVIC_INT_CTRL, 4); m_puwExcContent = (UINT8 *)m_puwExcContent + 4; return; } /***************************************************************************** Function : osExcRegister Description : Register exception Input : uwType --- exception type : pFunc --- exception callback function : pArg --- exception save info arg, not pFunc Output : None Return : None *****************************************************************************/ VOID osExcRegister(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, VOID *pArg) { EXC_INFO_ARRAY_S *pstExcInfo; if (uwType == 0 || uwType >= OS_EXC_TYPE_MAX || pFunc == NULL) { PRINT_ERR("osExcRegister ERROR!\n"); return; } pstExcInfo = &(m_stExcArray[uwType - 1]); pstExcInfo->uwType = uwType; pstExcInfo->pFnExcInfoCb = pFunc; pstExcInfo->pArg = pArg; pstExcInfo->uwValid = TRUE; } /***************************************************************************** Function : osExcSaveSysInfo Description : Saving exception information by calling callback function recursively Input : uwType --- exception type(OS_EXC_TYPE_CONTEXT+1 ---> OS_EXC_TYPE_MAX-1) : pFunc --- callback function : uwLoop --- loop total count : uwLen --- The size of the data saved each time : uwIdx --- loop index Output : None Return : None *****************************************************************************/ VOID osExcSaveSysInfo(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, UINT32 uwLoop, UINT32 uwLen, UINT32 uwIdx) { UINT32 uwRet; UINT32 uwBuffer[OS_EXC_MAX_BUF_LEN]; /* Save exception type and size */ *((UINT32 *)m_puwExcContent) = uwType; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; *((UINT32 *)m_puwExcContent) = uwLen * (uwLoop - uwIdx); m_puwExcContent = (UINT8 *)m_puwExcContent + 4; for (; uwIdx < uwLoop; uwIdx++) { memset((VOID *)uwBuffer, 0, sizeof(UINT32) * OS_EXC_MAX_BUF_LEN); uwRet = pFunc(uwIdx, (VOID *)uwBuffer); if (LOS_OK == uwRet) { memcpy(m_puwExcContent, (VOID *)uwBuffer, uwLen); } m_puwExcContent =(UINT8 *)m_puwExcContent + uwLen; } } /***************************************************************************** Function : osExcSaveInfo Description : save exception info Input : uwType --- exception type(OS_EXC_TYPE_CONTEXT+1 ---> OS_EXC_TYPE_MAX-1) : pFunc --- exception callback : pArg --- register arg, used to generate the arg passed to the callback Output : None Return : None *****************************************************************************/ static VOID osExcSaveInfo(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, VOID *pArg) { UINT32 uwLen; UINT32 uwIdx; UINT32 uwLoop; UINT32 uwTaskSwitchCount = 0; OS_TASK_SWITCH_INFO *pstTaskSwitchInfo; switch(uwType) { case OS_EXC_TYPE_TSK: /* save task info */ uwLen = sizeof(TSK_INFO_S); uwLoop = *(UINT32 *)pArg; uwIdx = 0; break; case OS_EXC_TYPE_QUE: /* save queue info */ uwLen = sizeof(QUEUE_INFO_S); uwLoop = *(UINT32 *)pArg; uwIdx = 0; break; case OS_EXC_TYPE_NVIC: /* save NVIC info */ (VOID)pFunc(0, 0); goto END; case OS_EXC_TYPE_TSK_SWITCH: /* save task switch info */ pstTaskSwitchInfo = pArg; uwTaskSwitchCount = pstTaskSwitchInfo->ucIsFull & 0x7F; uwLen = sizeof(UINT32) + sizeof(CHAR) * LOS_TASK_NAMELEN; /* auwPID + acName */ if (pstTaskSwitchInfo->ucIsFull & 0x80) { uwIdx = pstTaskSwitchInfo->ucIdx; uwLoop = uwIdx + uwTaskSwitchCount; } else { uwIdx = 0; uwLoop = pstTaskSwitchInfo->ucIdx; } break; case OS_EXC_TYPE_MEM: /* save mem info */ uwLen = sizeof(MEM_INFO_S); uwLoop = *(UINT32 *)pArg; uwIdx = 0; break; default: goto END; } osExcSaveSysInfo(uwType, (EXC_INFO_SAVE_CALLBACK)pFunc, uwLoop, uwLen, uwIdx); END: return; } /***************************************************************************** Function : osExcSave2DDR Description : Save exception info to RAM Input : None Output : None Return : None *****************************************************************************/ static VOID osExcSave2DDR(VOID) { UINT32 uwIdx = 0; UINT32 uwExcContextSize; if (m_stExcInfo.usFpuContext == 1) { uwExcContextSize = sizeof(EXC_CONTEXT_S); } else { uwExcContextSize = sizeof(EXC_CONTEXT_S) - 136; /* except FPU register */ } memset(m_puwExcContent, 0xff, g_uwArraySize); /* Cortex-M type */ *((UINT32 *)m_puwExcContent) = 4; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* * Save exception type: OS_EXC_TYPE_CONTEXT */ *((UINT32 *)m_puwExcContent) = OS_EXC_TYPE_CONTEXT; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* The size of struct EXC_INFO_S(except member EXC_CONTEXT_S*) and exception context size */ *((UINT32 *)m_puwExcContent) = sizeof(EXC_INFO_S) - sizeof(EXC_CONTEXT_S *) + uwExcContextSize; m_puwExcContent = (UINT8 *)m_puwExcContent + 4; /* Save struct m_stExcInfo except m_stExcInfo.pstContext */ memcpy((VOID *)m_puwExcContent, (VOID *)&m_stExcInfo, sizeof(EXC_INFO_S) - sizeof(EXC_CONTEXT_S *)); m_puwExcContent = (UINT8 *)m_puwExcContent + sizeof(EXC_INFO_S) - sizeof(EXC_CONTEXT_S *); /* Save struct EXC_CONTEXT_S */ if (m_stExcInfo.usFpuContext == 0) { #if FPU_EXIST /* m_stExcInfo.pstContext: init --- point to S16, S16->S31 invalid * + 64 --- point to uwR4 * copy uwR4 -> uwxPSR */ memcpy((VOID *)m_puwExcContent, (UINT8 *)m_stExcInfo.pstContext + 64, uwExcContextSize); #else memcpy((VOID *)m_puwExcContent, m_stExcInfo.pstContext, uwExcContextSize); #endif } else { memcpy((VOID *)m_puwExcContent, m_stExcInfo.pstContext, uwExcContextSize); } m_puwExcContent = (UINT8 *)m_puwExcContent + uwExcContextSize; /* * Save exception type: OS_EXC_TYPE_CONTEXT+1 ---> OS_EXC_TYPE_MAX-1 */ for (uwIdx = 0; uwIdx < OS_EXC_TYPE_MAX - 1; uwIdx++) { if (m_stExcArray[uwIdx].uwValid == FALSE) { continue; } osExcSaveInfo(m_stExcArray[uwIdx].uwType, m_stExcArray[uwIdx].pFnExcInfoCb, m_stExcArray[uwIdx].pArg); } /* * Save exception type: OS_EXC_TYPE_MAX */ *((UINT32 *)m_puwExcContent) = OS_EXC_TYPE_MAX; m_puwExcContent = (UINT8*)m_puwExcContent + 4; return; } #endif /*(LOSCFG_SAVE_EXC_INFO == YES)*/ /***************************************************************************** Function : osExcInit Description : Initializes the EXC Input : None Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT_INIT VOID osExcInit(UINT32 uwArraySize) { #if (LOSCFG_PLATFORM_HWI == YES) /* Register exception handler to interrupt vector table in RAM */ m_pstHwiForm[-14 + OS_SYS_VECTOR_CNT] = NMI_Handler; m_pstHwiForm[-13 + OS_SYS_VECTOR_CNT] = HardFault_Handler; m_pstHwiForm[-12 + OS_SYS_VECTOR_CNT] = MemManage_Handler; m_pstHwiForm[-11 + OS_SYS_VECTOR_CNT] = BusFault_Handler; m_pstHwiForm[-10 + OS_SYS_VECTOR_CNT] = UsageFault_Handler; m_pstHwiForm[-5 + OS_SYS_VECTOR_CNT] = SVC_Handler; #endif /* Enable USGFAULT(BIT_18), BUSFAULT(BIT_17), MEMFAULT(BIT_16) */ *(volatile UINT32 *)OS_NVIC_SHCSR |= 0x70000; /* Enable DIV 0(BIT_4) exception, unaligned(BIT_3) disable */ *(volatile UINT32 *)OS_NVIC_CCR |= 0x10; #if (LOSCFG_SAVE_EXC_INFO == YES) g_uwArraySize = uwArraySize; osExcRegister((EXC_INFO_TYPE)OS_EXC_TYPE_NVIC, (EXC_INFO_SAVE_CALLBACK)osExcSaveIntStatus, NULL); #endif } VOID osBackTrace(VOID) { return; } #endif /*(LOSCFG_PLATFORM_EXC == YES)*/ #ifdef __cplusplus #if __cplusplus } #endif /* __cpluscplus */ #endif /* __cpluscplus */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m7/los_exc.inc ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _LOS_EXC_INC #define _LOS_EXC_INC #include "los_exc.ph" #include "los_sys.ph" #ifdef LOSCFG_LIB_LIBC #include "string.h" #endif #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cpluscplus */ #endif /* __cpluscplus */ /* 定义异常发生的阶段 */ #define OS_EXC_IN_INIT 0 #define OS_EXC_IN_TASK 1 #define OS_EXC_IN_HWI 2 /* *异常类型:uwFaultAddr域是否有效 标志位 */ #define OS_EXC_FLAG_FAULTADDR_VALID 0x01 /* *异常类型:异常是否发生在硬中断中标志位 */ #define OS_EXC_FLAG_IN_HWI 0x02 #define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB #define OS_EXC_FLAG_NO_FLOAT 0x10000000 #define OS_EXC_MAX_BUF_LEN 25 #define OS_EXC_MAX_NEST_DEPTH 1 #define OS_NVIC_SHCSR 0xE000ED24 #define OS_NVIC_CCR 0xE000ED14 #define OS_NVIC_INT_ENABLE_SIZE 0x20 #define OS_NVIC_INT_PRI_SIZE 0xF0 #define OS_NVIC_INT_PEND_SIZE OS_NVIC_INT_ACT_SIZE #define OS_NVIC_INT_ACT_SIZE OS_NVIC_INT_ENABLE_SIZE /** *@ingroup los_exc *Cortex-M4异常具体类型:总线状态寄存器入栈时发生错误 */ #define OS_EXC_BF_STKERR 1 /** *@ingroup los_exc *Cortex-M4异常具体类型:总线状态寄存器出栈时发生错误 */ #define OS_EXC_BF_UNSTKERR 2 /** *@ingroup los_exc *Cortex-M4异常具体类型:总线状态寄存器不精确的数据访问违例 */ #define OS_EXC_BF_IMPRECISERR 3 /** *@ingroup los_exc *Cortex-M4异常具体类型:总线状态寄存器精确的数据访问违例 */ #define OS_EXC_BF_PRECISERR 4 /** *@ingroup los_exc *Cortex-M4异常具体类型:总线状态寄存器取指时的访问违例 */ #define OS_EXC_BF_IBUSERR 5 /** *@ingroup los_exc *Cortex-M4异常具体类型:存储器管理状态寄存器入栈时发生错误 */ #define OS_EXC_MF_MSTKERR 6 /** *@ingroup los_exc *Cortex-M4异常具体类型:存储器管理状态寄存器出栈时发生错误 */ #define OS_EXC_MF_MUNSTKERR 7 /** *@ingroup los_exc *Cortex-M4异常具体类型:存储器管理状态寄存器数据访问违例 */ #define OS_EXC_MF_DACCVIOL 8 /** *@ingroup los_exc *Cortex-M4异常具体类型:存储器管理状态寄存器取指访问违例 */ #define OS_EXC_MF_IACCVIOL 9 /** *@ingroup los_exc *Cortex-M4异常具体类型:用法错误，表示除法运算时除数为零 */ #define OS_EXC_UF_DIVBYZERO 10 /** *@ingroup los_exc *Cortex-M4异常具体类型:用法错误，未对齐访问导致的错误 */ #define OS_EXC_UF_UNALIGNED 11 /** *@ingroup los_exc *Cortex-M4异常具体类型:用法错误，试图执行协处理器相关指令 */ #define OS_EXC_UF_NOCP 12 /** *@ingroup los_exc *Cortex-M4异常具体类型:用法错误，在异常返回时试图非法地加载EXC_RETURN到PC */ #define OS_EXC_UF_INVPC 13 /** *@ingroup los_exc *Cortex-M4异常具体类型:用法错误，试图切入ARM状态 */ #define OS_EXC_UF_INVSTATE 14 /** *@ingroup los_exc *Cortex-M4异常具体类型:用法错误，执行的指令其编码是未定义的——解码不能 */ #define OS_EXC_UF_UNDEFINSTR 15 /** *@ingroup los_exc *Cortex-M4异常具体类型:NMI中断 */ #define OS_EXC_CAUSE_NMI 16 /** *@ingroup los_exc *Cortex-M4异常具体类型:硬fault */ #define OS_EXC_CAUSE_HARDFAULT 17 /** *@ingroup los_exc *Cortex-M4异常具体类型:任务处理函数退出 */ #define OS_EXC_CAUSE_TASK_EXIT 18 /** *@ingroup los_exc *Cortex-M4异常具体类型:致命错误 */ #define OS_EXC_CAUSE_FATAL_ERR 19 /** *@ingroup los_exc *Cortex-M4异常具体类型:调试事件导致的硬fault */ #define OS_EXC_CAUSE_DEBUGEVT 20 /** *@ingroup los_exc *Cortex-M4异常具体类型:取向量时发生的硬fault */ #define OS_EXC_CAUSE_VECTBL 21 #ifdef __cplusplus #if __cplusplus } #endif /* __cpluscplus */ #endif /* __cpluscplus */ #endif /* _LOS_EXC_INC */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/cortex-m7/los_exc.ph ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _LOS_EXC_PH #define _LOS_EXC_PH #include "los_exc.h" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ #if (LOSCFG_PLATFORM_EXC == YES) typedef enum { OS_EXC_TYPE_CONTEXT = 0, OS_EXC_TYPE_TSK = 1, OS_EXC_TYPE_QUE = 2, OS_EXC_TYPE_NVIC = 3, OS_EXC_TYPE_TSK_SWITCH = 4, OS_EXC_TYPE_MEM = 5, OS_EXC_TYPE_MAX = 6 } EXC_INFO_TYPE; typedef struct tagExcInfoCallBackArray { EXC_INFO_TYPE uwType; UINT32 uwValid; EXC_INFO_SAVE_CALLBACK pFnExcInfoCb; VOID* pArg; }EXC_INFO_ARRAY_S; #define MAX_SCENE_INFO_SIZE (8 + sizeof(EXC_INFO_S) - 4 + sizeof(EXC_CONTEXT_S)) #define MAX_TSK_INFO_SIZE (8 + sizeof(TSK_INFO_S)* (LOSCFG_BASE_CORE_TSK_LIMIT + 1)) #define MAX_INT_INFO_SIZE (8 + 0x164) #if (LOSCFG_BASE_IPC_QUEUE == YES) #define MAX_QUEUE_INFO_SIZE (8 + sizeof(QUEUE_INFO_S)* LOSCFG_BASE_IPC_QUEUE_LIMIT) #else #define MAX_QUEUE_INFO_SIZE (0) #endif #if (LOSCFG_BASE_CORE_EXC_TSK_SWITCH == YES) #define MAX_SWITCH_INFO_SIZE (8 + (sizeof(UINT32) + sizeof(CHAR) * LOS_TASK_NAMELEN)* OS_TASK_SWITCH_INFO_COUNT) #else #define MAX_SWITCH_INFO_SIZE (0) #endif #if (LOSCFG_BASE_MEM_NODE_INTEGRITY_CHECK == YES) #define MAX_MEM_INFO_SIZE (8 + sizeof(MEM_INFO_S)* OS_SYS_MEM_NUM) #else #define MAX_MEM_INFO_SIZE (0) #endif #define MAX_EXC_MEM_SIZE ( 4 + MAX_SCENE_INFO_SIZE + MAX_TSK_INFO_SIZE + MAX_QUEUE_INFO_SIZE + MAX_INT_INFO_SIZE + MAX_SWITCH_INFO_SIZE + MAX_MEM_INFO_SIZE + 4) VOID osExcRegister(EXC_INFO_TYPE uwType, EXC_INFO_SAVE_CALLBACK pFunc, VOID* pArg); #endif #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ #endif ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/include/los_exc.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _LOS_EXC_H #define _LOS_EXC_H #include "los_hwi.h" #include "los_task.ph" #include "los_queue.h" #include "los_config.h" #include "los_memcheck.h" #include "los_hw.h" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cpluscplus */ #endif /* __cpluscplus */ #if (LOSCFG_PLATFORM_EXC == YES) #define OS_EXC_IN_INIT 0 #define OS_EXC_IN_TASK 1 #define OS_EXC_IN_HWI 2 #define OS_EXC_MAX_BUF_LEN 25 #define OS_EXC_MAX_NEST_DEPTH 1 #define OS_EXC_FLAG_NO_FLOAT 0x10000000 #define OS_EXC_FLAG_FAULTADDR_VALID 0x01 #define OS_EXC_FLAG_IN_HWI 0x02 #define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB /** *@ingroup los_exc * the struct of register files * * description: the register files that saved when exception triggered * * notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet. */ typedef struct tagExcContext { #if FPU_EXIST UINT32 S16; UINT32 S17; UINT32 S18; UINT32 S19; UINT32 S20; UINT32 S21; UINT32 S22; UINT32 S23; UINT32 S24; UINT32 S25; UINT32 S26; UINT32 S27; UINT32 S28; UINT32 S29; UINT32 S30; UINT32 S31; #endif UINT32 uwR4; UINT32 uwR5; UINT32 uwR6; UINT32 uwR7; UINT32 uwR8; UINT32 uwR9; UINT32 uwR10; UINT32 uwR11; UINT32 uwPriMask; UINT32 uwSP; UINT32 uwR0; UINT32 uwR1; UINT32 uwR2; UINT32 uwR3; UINT32 uwR12; UINT32 uwLR; UINT32 uwPC; UINT32 uwxPSR; #if FPU_EXIST UINT32 S0; UINT32 S1; UINT32 S2; UINT32 S3; UINT32 S4; UINT32 S5; UINT32 S6; UINT32 S7; UINT32 S8; UINT32 S9; UINT32 S10; UINT32 S11; UINT32 S12; UINT32 S13; UINT32 S14; UINT32 S15; UINT32 FPSCR; UINT32 NO_NAME; #endif }EXC_CONTEXT_S; typedef UINT32 (*EXC_INFO_SAVE_CALLBACK)(UINT32 , VOID* ); typedef VOID (* EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *); VOID osExcHandleEntry(UINT32 uwExcType, UINT32 uwFaultAddr, UINT32 uwPid, EXC_CONTEXT_S * pstExcBufAddr); /** * @ingroup los_hwi * @brief: Exception initialization. * * @par Description: * This API is used to configure the exception function vector table. * * @attention: *
  • None.
* *@param uwArraySize [IN] Memory size of exception. * * @retval: None * @par Dependency: *
  • los_hwi.h: the header file that contains the API declaration.
* @see None. * @since Huawei LiteOS V100R001C00 */ VOID osExcInit(UINT32 uwArraySize); extern VOID NMI_Handler(VOID); extern VOID HardFault_Handler(VOID); extern VOID MemManage_Handler(VOID); extern VOID BusFault_Handler(VOID); extern VOID UsageFault_Handler(VOID); extern VOID SVC_Handler(VOID); extern VOID osBackTrace(VOID); extern UINT8 m_aucTaskArray[]; /** *@ingroup los_exc *@brief Kernel panic function. * *@par Description: *Stack function that prints kernel panics. *@attention After this function is called and stack information is printed, the system will fail to respond. *@attention The input parameter can be NULL. *@param fmt [IN] Type #char* : variadic argument. * *@retval #None. * *@par Dependency: *los_exc.h: the header file that contains the API declaration. *@see None. *@since Huawei LiteOS V100R001C00 */ void LOS_Panic(const char * fmt, ...); /** *@ingroup los_exc *Cortex-M异常具体类型:总线状态寄存器入栈时发生错误 */ #define OS_EXC_BF_STKERR 1 /** *@ingroup los_exc *Cortex-M异常具体类型:总线状态寄存器出栈时发生错误 */ #define OS_EXC_BF_UNSTKERR 2 /** *@ingroup los_exc *Cortex-M异常具体类型:总线状态寄存器不精确的数据访问违例 */ #define OS_EXC_BF_IMPRECISERR 3 /** *@ingroup los_exc *Cortex-M异常具体类型:总线状态寄存器精确的数据访问违例 */ #define OS_EXC_BF_PRECISERR 4 /** *@ingroup los_exc *Cortex-M异常具体类型:总线状态寄存器取指时的访问违例 */ #define OS_EXC_BF_IBUSERR 5 /** *@ingroup los_exc *Cortex-M异常具体类型:总线错误，浮点惰性压栈错误，具有浮点单元的cortex-m4及cortex-m7中存在 */ #define OS_EXC_BF_LSPERR 6 /** *@ingroup los_exc *Cortex-M异常具体类型:存储器管理状态寄存器入栈时发生错误 */ #define OS_EXC_MF_MSTKERR 7 /** *@ingroup los_exc *Cortex-M异常具体类型:存储器管理状态寄存器出栈时发生错误 */ #define OS_EXC_MF_MUNSTKERR 8 /** *@ingroup los_exc *Cortex-M异常具体类型:存储器管理状态寄存器数据访问违例 */ #define OS_EXC_MF_DACCVIOL 9 /** *@ingroup los_exc *Cortex-M异常具体类型:存储器管理状态寄存器取指访问违例 */ #define OS_EXC_MF_IACCVIOL 10 /** *@ingroup los_exc *Cortex-M异常具体类型:存储器管理错误，浮点惰性压栈错误，具有浮点单元的cortex-m4及cortex-m7中存在 */ #define OS_EXC_MF_MLSPERR 11 /** *@ingroup los_exc *Cortex-M异常具体类型:用法错误，表示除法运算时除数为零 */ #define OS_EXC_UF_DIVBYZERO 12 /** *@ingroup los_exc *Cortex-M异常具体类型:用法错误，未对齐访问导致的错误 */ #define OS_EXC_UF_UNALIGNED 13 /** *@ingroup los_exc *Cortex-M异常具体类型:用法错误，试图执行协处理器相关指令 */ #define OS_EXC_UF_NOCP 14 /** *@ingroup los_exc *Cortex-M异常具体类型:用法错误，在异常返回时试图非法地加载EXC_RETURN到PC */ #define OS_EXC_UF_INVPC 15 /** *@ingroup los_exc *Cortex-M异常具体类型:用法错误，试图切入ARM状态 */ #define OS_EXC_UF_INVSTATE 16 /** *@ingroup los_exc *Cortex-M异常具体类型:用法错误，执行的指令其编码是未定义的——解码不能 */ #define OS_EXC_UF_UNDEFINSTR 17 /** *@ingroup los_exc *Cortex-M异常具体类型:NMI中断 */ #define OS_EXC_CAUSE_NMI 18 /** *@ingroup los_exc *Cortex-M异常具体类型:硬fault */ #define OS_EXC_CAUSE_HARDFAULT 19 /** *@ingroup los_exc *Cortex-M异常具体类型:存储器管理fault */ #define OS_EXC_CAUSE_MEMFAULT 20 /** *@ingroup los_exc *Cortex-M异常具体类型:总线fault */ #define OS_EXC_CAUSE_BUSFAULT 21 /** *@ingroup los_exc *Cortex-M异常具体类型:使用fault */ #define OS_EXC_CAUSE_USAGEFAULT 22 /** *@ingroup los_exc *Cortex-M异常具体类型:SVC调用 */ #define OS_EXC_CAUSE_SVC 23 /** *@ingroup los_exc *Cortex-M异常具体类型:调试事件导致的硬fault */ #define OS_EXC_CAUSE_DEBUGEVT 24 /** *@ingroup los_exc *Cortex-M异常具体类型:取向量时发生的硬fault */ #define OS_EXC_CAUSE_VECTBL 25 /** *@ingroup los_exc *Cortex-M异常具体类型:任务处理函数退出 */ #define OS_EXC_CAUSE_TASK_EXIT 26 /** *@ingroup los_exc *Cortex-M异常具体类型:致命错误 */ #define OS_EXC_CAUSE_FATAL_ERR 27 /** *@ingroup los_exc * 异常信息结构体 * * 描述:Cortex-M平台下的异常触发时保存的异常信息 * */ typedef struct tagExcInfo { UINT16 usPhase; /**< 异常发生阶段： 0表示异常发生在初始化中，1表示异常发生在任务中，2表示异常发生在中断中 */ UINT16 usType; /**< 异常类型，分高低两字节，出异常时高低字节分别对照上面列出的异常编号 */ UINT32 uwFaultAddr; /**< 若为精确地址访问错误表示异常发生时的错误访问地址 */ UINT32 uwThrdPid; /**< 在中断中发生异常，表示中断号。在任务中发生异常，表示任务id，如果发生在初始化中，则为0xffffffff */ UINT16 usNestCnt; /**< 异常嵌套个数，目前仅支持第一次进入异常时执行注册的钩子函数 */ UINT16 usFpuContext; /**< 是否保存浮点寄存器，1表示需要保存浮点寄存器 */ UINT32 uwCallStackDepth; /**< 异常时调用栈分析深度 */ UINT32 uwCallStack[LOSCFG_EXC_CALL_STACK_ANALYSIS_MAX_DEPTH]; /**< 函数调用地址 */ EXC_CONTEXT_S *pstContext; /**< 异常发生时的寄存器值，由usFpuContext决定寄存器中是否包含浮点寄存器的值 */ }EXC_INFO_S; extern UINT32 g_uwCurNestCount; extern UINT32 g_vuwIntCount; extern EXC_INFO_S m_stExcInfo; VOID osExcInfoDisplay(EXC_INFO_S *pstExc); extern OS_TASK_SWITCH_INFO g_astTskSwitchInfo; extern UINT8 g_uwExcTbl[32]; #endif #ifdef __cplusplus #if __cplusplus } #endif /* __cpluscplus */ #endif /* __cpluscplus */ #endif /* _LOS_EXC_H */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/include/los_hw.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**@defgroup los_hw hardware *@ingroup kernel */ #ifndef _LOS_HW_H #define _LOS_HW_H #include "los_base.h" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ /** * @ingroup los_hw * The initialization value of stack space. */ #define EMPTY_STACK 0xCACA /** * @ingroup los_hw * Trigger a task. */ #define osTaskTrap() __asm(" TRAP #31") /** * @ingroup los_hw * Check task schedule. */ #define LOS_CHECK_SCHEDULE ((!g_usLosTaskLock)) /** * @ingroup los_hw * FPU exist macro: If it exist, save EXC_RETURN value in the context of the task to check * the size of the stack frame(BIT_4: 1 ---> 8 words, 0 ---> 26 wrods) used by the task. */ #define FPU_EXIST ( (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP )) \ || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ )) \ || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined( __SOFTFP__ )) ) /** * @ingroup los_hw * Define the type of a task context control block. */ typedef struct tagTskContext { UINT32 uwR4; UINT32 uwR5; UINT32 uwR6; UINT32 uwR7; UINT32 uwR8; UINT32 uwR9; UINT32 uwR10; UINT32 uwR11; UINT32 uwPriMask; #if FPU_EXIST UINT32 uwExcReturn; #endif UINT32 uwR0; UINT32 uwR1; UINT32 uwR2; UINT32 uwR3; UINT32 uwR12; UINT32 uwLR; UINT32 uwPC; UINT32 uwxPSR; } TSK_CONTEXT_S; /** * @ingroup los_hw * @brief: Task stack initialization. * * @par Description: * This API is used to initialize the task stack. * * @attention: *
  • None.
* * @param uwTaskID [IN] Type#UINT32: TaskID. * @param uwStackSize [IN] Type#UINT32: Total size of the stack. * @param pTopStack [IN] Type#VOID *: Top of task's stack. * * @retval: pstContext Type#TSK_CONTEXT_S *. * @par Dependency: *
  • los_hw.h: the header file that contains the API declaration.
* @see None. * @since Huawei LiteOS V100R001C00 */ extern VOID * osTskStackInit(UINT32 uwTaskID, UINT32 uwStackSize, VOID *pTopStack); /** * @ingroup los_hw * @brief: Task scheduling Function. * * @par Description: * This API is used to scheduling task. * * @attention: *
  • None.
* * @param None. * * @retval: None. * @par Dependency: *
  • los_hw.h: the header file that contains the API declaration.
* @see None. * @since Huawei LiteOS V100R001C00 */ extern VOID osSchedule(VOID); /** * @ingroup los_hw * @brief: Function to determine whether task scheduling is required. * * @par Description: * This API is used to Judge and entry task scheduling. * * @attention: *
  • None.
* * @param None. * * @retval: None. * @par Dependency: *
  • los_hw.h: the header file that contains the API declaration.
* @see None. * @since Huawei LiteOS V100R001C00 */ extern VOID LOS_Schedule(VOID); LITE_OS_SEC_TEXT_MINOR VOID osTaskExit(VOID); /** * @ingroup los_hw * @brief: The M3 wait interrupt instruction. * * @par Description: * This API is used to make CPU enter to power-save mode. * * @attention: *
  • None.
* * @param None. * * @retval: None. * @par Dependency: *
  • los_hw.h: the header file that contains the API declaration.
* @see None. * @since Huawei LiteOS V100R001C00 */ extern VOID osEnterSleep(VOID); #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ #endif /* _LOS_HW_H */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/include/los_hw_tick.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**@defgroup los_hw hardware *@ingroup kernel */ #ifndef _LOS_HW_TICK_H #define _LOS_HW_TICK_H #include "los_base.h" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ #if (LOSCFG_KERNEL_TICKLESS == YES) /** * @ingroup los_hwi * Check whether the counting direction of system tick is decreasing, it will be used to * readjust the value of the system tick, if not decreasing, please set this macro to NO. */ #define LOSCFG_SYSTICK_CNT_DIR_DECREASE YES /** * @ingroup los_hwi * Max reload value of system tick. */ #define LOSCFG_SYSTICK_LOAD_RELOAD_MAX SysTick_LOAD_RELOAD_Msk /***************************************************************************** Function : LOS_SysTickStop Description: stop systick Input : none output : none return : none *****************************************************************************/ LITE_OS_SEC_TEXT_MINOR static inline VOID LOS_SysTickStop(VOID) { SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; } /***************************************************************************** Function : LOS_SysTickStart Description: start systick Input : none output : none return : none *****************************************************************************/ LITE_OS_SEC_TEXT_MINOR static inline VOID LOS_SysTickStart(VOID) { SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; } /***************************************************************************** Function : LOS_SysTickGetIntStatus Description: get systick interrupt status Input : none output : none return : systick interrupt status *****************************************************************************/ LITE_OS_SEC_TEXT_MINOR static inline UINT32 LOS_SysTickGetIntStatus(VOID) { return SCB->ICSR & SCB_ICSR_PENDSTSET_Msk; } extern VOID LOS_SysTickReload(UINT32 uwCyclesPerTick); #endif #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ #endif /* _LOS_HW_H */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/include/los_hwi.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2015>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**@defgroup los_hwi Hardware interrupt *@ingroup kernel */ #ifndef _LOS_HWI_H #define _LOS_HWI_H #include "los_base.h" #include "los_sys.h" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ /** * @ingroup los_hwi * Maximum number of used hardware interrupts. */ /*lint -e553*/ #ifndef OS_HWI_MAX_NUM #if (__CORTEX_M == 0U) /* Cortex-m0 and Cortex-m0plus default 32 */ #define OS_HWI_MAX_NUM 32 #elif (__CORTEX_M == 3U || __CORTEX_M == 4U || __CORTEX_M == 7U) /* Cortex-m3,Cortex-m4 and Cortex-m7 default 240 */ #define OS_HWI_MAX_NUM 240 #endif #endif /*lint +e553*/ /** * @ingroup los_hwi * Highest priority of a hardware interrupt. */ #ifndef OS_HWI_PRIO_HIGHEST #define OS_HWI_PRIO_HIGHEST 0 #endif /** * @ingroup los_hwi * Lowest priority of a hardware interrupt. */ #ifndef OS_HWI_PRIO_LOWEST #define OS_HWI_PRIO_LOWEST 7 #endif /** * @ingroup los_config * Configuration item for interrupt with argument */ #ifndef OS_HWI_WITH_ARG #define OS_HWI_WITH_ARG NO #endif /** * @ingroup los_hwi * Define the type of a hardware interrupt number. */ typedef UINT32 HWI_HANDLE_T; /** * @ingroup los_hwi * Define the type of a hardware interrupt priority. */ typedef UINT16 HWI_PRIOR_T; /** * @ingroup los_hwi * Define the type of hardware interrupt mode configurations. */ typedef UINT16 HWI_MODE_T; /** * @ingroup los_hwi * Define the type of the parameter used for the hardware interrupt creation function. The function of this parameter varies among platforms. */ typedef UINT32 HWI_ARG_T; /** * @ingroup los_hwi * Define the type of a hardware interrupt handling function. */ #if (OS_HWI_WITH_ARG == YES) typedef VOID (* HWI_PROC_FUNC)(VOID *pParm); typedef struct { HWI_PROC_FUNC pfnHandler; VOID* pParm; } HWI_SLAVE_FUNC; #else typedef VOID (* HWI_PROC_FUNC)(void); #endif /** * @ingroup los_hwi * Define the type of a hardware interrupt vector table function. */ typedef VOID (**HWI_VECTOR_FUNC)(void); /** * @ingroup los_hwi * Count of interrupts. */ extern UINT32 g_vuwIntCount; #if (LOSCFG_PLATFORM_HWI == YES) /** * @ingroup los_hwi * An interrupt is active. */ #define OS_INT_ACTIVE (g_vuwIntCount > 0) #else /** * @ingroup los_hwi * An interrupt is active. */ #define OS_INT_ACTIVE (osIntNumGet()) #endif /** * @ingroup los_hwi * An interrupt is inactive. */ #define OS_INT_INACTIVE (!(OS_INT_ACTIVE)) /** * @ingroup los_hwi * Count of M-Core system interrupt vector. */ #define OS_SYS_VECTOR_CNT 16 /** * @ingroup los_hwi * Count of M-Core interrupt vector. */ #define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM) /** * @ingroup los_hwi * AIRCR register priority group parameter . */ #define OS_NVIC_AIRCR_PRIGROUP 7 /** * @ingroup los_hwi * Boot interrupt vector table. */ extern UINT32 _BootVectors[]; /** * @ingroup los_hwi * Hardware interrupt error code: Invalid interrupt number. * * Value: 0x02000900 * * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX]. */ #define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00) /** * @ingroup los_hwi * Hardware interrupt error code: Null hardware interrupt handling function. * * Value: 0x02000901 * * Solution: Pass in a valid non-null hardware interrupt handling function. */ #define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01) /** * @ingroup los_hwi * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation. * * Value: 0x02000902 * * Solution: Increase the configured maximum number of supported hardware interrupts. */ #define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02) /** * @ingroup los_hwi * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization. * * Value: 0x02000903 * * Solution: Expand the configured memory. */ #define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03) /** * @ingroup los_hwi * Hardware interrupt error code: The interrupt has already been created. * * Value: 0x02000904 * * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created. */ #define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04) /** * @ingroup los_hwi * Hardware interrupt error code: Invalid interrupt priority. * * Value: 0x02000905 * * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15]. */ #define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05) /** * @ingroup los_hwi * Hardware interrupt error code: Incorrect interrupt creation mode. * * Value: 0x02000906 * * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1. */ #define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06) /** * @ingroup los_hwi * Hardware interrupt error code: The interrupt has already been created as a fast interrupt. * * Value: 0x02000907 * * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created. */ #define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07) /** * @ingroup los_hwi * SysTick control and status register. */ #define OS_SYSTICK_CONTROL_REG 0xE000E010 /** * @ingroup los_hw * SysTick current value register. */ #define OS_SYSTICK_CURRENT_REG 0xE000E018 /** * @ingroup los_hwi * Interrupt Priority-Level Registers. */ #define OS_NVIC_PRI_BASE 0xE000E400 /** * @ingroup los_hwi * Interrupt enable register for 0-31. */ #define OS_NVIC_SETENA_BASE 0xE000E100 /** * @ingroup los_hwi * interrupt pending register. */ #define OS_NVIC_SETPEND_BASE 0xE000E200 /** * @ingroup los_hwi * ?D??ACTIVE???????? */ #define OS_NVIC_INT_ACT_BASE 0xE000E300 /** * @ingroup los_hwi * Interrupt disable register for 0-31. */ #define OS_NVIC_CLRENA_BASE 0xE000E180 /** * @ingroup los_hwi * Interrupt control and status register. */ #define OS_NVIC_INT_CTRL 0xE000ED04 /** * @ingroup los_hwi * Vector table offset register. */ #define OS_NVIC_VTOR 0xE000ED08 /** * @ingroup los_hwi * Application interrupt and reset control register */ #define OS_NVIC_AIRCR 0xE000ED0C /** * @ingroup los_hwi * System exception priority register. */ #define OS_NVIC_EXCPRI_BASE 0xE000ED18 /** * @ingroup los_hwi * Interrupt No. 1 :reset. */ #define OS_EXC_RESET 1 /** * @ingroup los_hwi * Interrupt No. 2 :Non-Maskable Interrupt. */ #define OS_EXC_NMI 2 /** * @ingroup los_hwi * Interrupt No. 3 :(hard)fault. */ #define OS_EXC_HARD_FAULT 3 /** * @ingroup los_hwi * Interrupt No. 4 :MemManage fault. */ #define OS_EXC_MPU_FAULT 4 /** * @ingroup los_hwi * Interrupt No. 5 :Bus fault. */ #define OS_EXC_BUS_FAULT 5 /** * @ingroup los_hwi * Interrupt No. 6 :Usage fault. */ #define OS_EXC_USAGE_FAULT 6 /** * @ingroup los_hwi * Interrupt No. 11 :SVCall. */ #define OS_EXC_SVC_CALL 11 /** * @ingroup los_hwi * Interrupt No. 12 :Debug monitor. */ #define OS_EXC_DBG_MONITOR 12 /** * @ingroup los_hwi * Interrupt No. 14 :PendSV. */ #define OS_EXC_PEND_SV 14 /** * @ingroup los_hwi * Interrupt No. 15 :SysTick. */ #define OS_EXC_SYS_TICK 15 /** * @ingroup los_hwi * hardware interrupt form mapping handling function array. */ extern HWI_PROC_FUNC m_pstHwiForm[OS_VECTOR_CNT]; #if (OS_HWI_WITH_ARG == YES) /** * @ingroup los_hwi * hardware interrupt Slave form mapping handling function array. */ extern HWI_SLAVE_FUNC m_pstHwiSlaveForm[OS_VECTOR_CNT]; /** * @ingroup los_hwi * Set interrupt vector table. */ #define osSetVector(uwNum, pfnVector, uwArg) \ m_pstHwiForm[uwNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)osInterrupt;\ m_pstHwiSlaveForm[uwNum + OS_SYS_VECTOR_CNT].pfnHandler= pfnVector; \ m_pstHwiSlaveForm[uwNum + OS_SYS_VECTOR_CNT].pParm = (VOID*)uwArg; #else /** * @ingroup los_hwi * hardware interrupt Slave form mapping handling function array. */ extern HWI_PROC_FUNC m_pstHwiSlaveForm[OS_VECTOR_CNT]; /** * @ingroup los_hwi * Set interrupt vector table. */ #define osSetVector(uwNum, pfnVector) \ m_pstHwiForm[uwNum + OS_SYS_VECTOR_CNT] = osInterrupt;\ m_pstHwiSlaveForm[uwNum + OS_SYS_VECTOR_CNT] = pfnVector; #endif /** * @ingroup los_hwi * @brief Create a hardware interrupt. * * @par Description: * This API is used to configure a hardware interrupt and register a hardware interrupt handling function. * * @attention *
    *
  • The hardware interrupt module is usable only when the configuration item for hardware interrupt tailoring is enabled.
    • *
  • Hardware interrupt number value range: [OS_USER_HWI_MIN,OS_USER_HWI_MAX]. The value range applicable for a Cortex-A7 platform is [32,95].
    • *
  • OS_HWI_MAX_NUM specifies the maximum number of interrupts that can be created.
    • *
  • Before executing an interrupt on a platform, refer to the chip manual of the platform.
    • *
* * @param uwHwiNum [IN] Type#HWI_HANDLE_T: hardware interrupt number. The value range applicable for a Cortex-A7 platform is [32,95]. * @param usHwiPrio [IN] Type#HWI_PRIOR_T: hardware interrupt priority. Ignore this parameter temporarily. * @param usMode [IN] Type#HWI_MODE_T: hardware interrupt mode. Ignore this parameter temporarily. * @param pfnHandler [IN] Type#HWI_PROC_FUNC: interrupt handler used when a hardware interrupt is triggered. * @param uwArg [IN] Type#HWI_ARG_T: input parameter of the interrupt handler used when a hardware interrupt is triggered. * * @retval #OS_ERRNO_HWI_PROC_FUNC_NULL 0x02000901: Null hardware interrupt handling function. * @retval #OS_ERRNO_HWI_NUM_INVALID 0x02000900: Invalid interrupt number. * @retval #OS_ERRNO_HWI_NO_MEMORY 0x02000903: Insufficient memory for hardware interrupt creation. * @retval #OS_ERRNO_HWI_ALREADY_CREATED 0x02000904: The interrupt handler being created has already been created. * @retval #LOS_OK 0, : The interrupt is successfully created. * @par Dependency: *
  • los_hwi.h: the header file that contains the API declaration.
* @see None. * @since Huawei LiteOS V100R001C00 */ extern UINT32 LOS_HwiCreate( HWI_HANDLE_T uwHwiNum, HWI_PRIOR_T usHwiPrio, HWI_MODE_T usMode, HWI_PROC_FUNC pfnHandler, HWI_ARG_T uwArg ); /** * @ingroup los_hwi * @brief: Hardware interrupt entry function. * * @par Description: * This API is used as all hardware interrupt handling function entry. * * @attention: *
  • None.
* * @param:None. * * @retval:None. * @par Dependency: *
  • los_hwi.h: the header file that contains the API declaration.
* @see None. * @since Huawei LiteOS V100R001C00 */ extern VOID osInterrupt(VOID); /** * @ingroup los_hwi * @brief: Get a interrupt number. * * @par Description: * This API is used to get the current interrupt number. * * @attention: *
  • None.
* * @param: None. * * @retval: Interrupt Indexes number. * @par Dependency: *
  • los_hwi.h: the header file that contains the API declaration.
* @see None. * @since Huawei LiteOS V100R001C00 */ extern UINT32 osIntNumGet(VOID); /** * @ingroup los_hwi * @brief: Default vector handling function. * * @par Description: * This API is used to configure interrupt for null function. * * @attention: *
  • None.
* * @param:None. * * @retval:None. * @par Dependency: *
  • los_hwi.h: the header file that contains the API declaration.
* @see None. * @since Huawei LiteOS V100R001C00 */ extern VOID osHwiDefaultHandler(VOID); /** * @ingroup los_hwi * @brief: Reset the vector table. * * @par Description: * This API is used to reset the vector table. * * @attention: *
  • None.
* * @param:None. * * @retval:None. * @par Dependency: *
  • los_hwi.h: the header file that contains the API declaration.
* @see None. * @since Huawei LiteOS V100R001C00 */ extern VOID Reset_Handler(VOID); /** * @ingroup los_hwi * @brief: Pended System Call. * * @par Description: * PendSV can be pended and is useful for an OS to pend an exception * so that an action can be performed after other important tasks are completed. * * @attention: *
  • None.
* * @param:None. * * @retval:None. * @par Dependency: *
  • los_hwi.h: the header file that contains the API declaration.
* @see None. * @since Huawei LiteOS V100R001C00 */ extern VOID PendSV_Handler(VOID); /** *@ingroup los_hwi *@brief Enable all interrupts. * *@par Description: *
    *
  • This API is used to enable all IRQ and FIQ interrupts in the CPSR.
    • *
*@attention *
    *
  • None.
    • *
* *@param None. * *@retval CPSR value obtained after all interrupts are enabled. *@par Dependency: *
  • los_hwi.h: the header file that contains the API declaration.
*@see LOS_IntRestore *@since Huawei LiteOS V100R001C00 */ extern UINTPTR LOS_IntUnLock(VOID); /** *@ingroup los_hwi *@brief Disable all interrupts. * *@par Description: *
    *
  • This API is used to disable all IRQ and FIQ interrupts in the CPSR.
    • *
*@attention *
    *
  • None.
    • *
* *@param None. * *@retval CPSR value obtained before all interrupts are disabled. *@par Dependency: *
  • los_hwi.h: the header file that contains the API declaration.
*@see LOS_IntRestore *@since Huawei LiteOS V100R001C00 */ extern UINTPTR LOS_IntLock(VOID); /** *@ingroup los_hwi *@brief Restore interrupts. * *@par Description: *
    *
  • This API is used to restore the CPSR value obtained before all interrupts are disabled.
    • *
*@attention *
    *
  • This API can be called only after all interrupts are disabled, and the input parameter value should be the value returned by calling the all interrupt disabling API.
    • *
* *@param uvIntSave [IN] CPSR value obtained before all interrupts are disabled. * *@retval None. *@par Dependency: *
  • los_hwi.h: the header file that contains the API declaration.
*@see LOS_IntLock *@since Huawei LiteOS V100R001C00 */ extern VOID LOS_IntRestore(UINTPTR uvIntSave); /** *@ingroup los_hwi *@brief Get value from xPSR register. * *@par Description: *
    *
  • This API is used to Get value from xPSR register.
    • *
*@attention *
    *
  • None.
    • *
* *@param None. * *@retval xPSR register value. *@par Dependency: *
  • los_hwi.h: the header file that contains the API declaration.
    • *@see LOS_IntRestore *@since Huawei LiteOS V100R001C00 */ extern VOID LOS_GetCpuCycle(UINT32 *puwCntHi, UINT32 *puwCntLo); extern UINT32 LOS_SysTickCurrCycleGet(VOID); /** * @ingroup los_hwi * @brief Delete hardware interrupt. * * @par Description: * This API is used to delete hardware interrupt. * * @attention *
      *
    • The hardware interrupt module is usable only when the configuration item for hardware interrupt tailoring is enabled.
      • *
    • Hardware interrupt number value range: [OS_USER_HWI_MIN,OS_USER_HWI_MAX]. The value range applicable for a Cortex-A7 platform is [32,95].
      • *
    • OS_HWI_MAX_NUM specifies the maximum number of interrupts that can be created.
      • *
    • Before executing an interrupt on a platform, refer to the chip manual of the platform.
      • *
    * * @param uwHwiNum [IN] Type#HWI_HANDLE_T: hardware interrupt number. The value range applicable for a Cortex-A7 platform is [32,95]. * * @retval #OS_ERRNO_HWI_NUM_INVALID 0x02000900: Invalid interrupt number. * @retval #LOS_OK 0: The interrupt is successfully delete. * @par Dependency: *
    • los_hwi.h: the header file that contains the API declaration.
    * @see None. * @since Huawei LiteOS V100R001C00 */ extern UINT32 LOS_HwiDelete(HWI_HANDLE_T uwHwiNum); #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ #endif /* _LOS_HWI_H */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/src/los_hw.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "los_base.h" #include "los_task.ph" #include "los_hw.h" #include "los_priqueue.ph" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ /***************************************************************************** Function : osSchedule Description : task scheduling Input : None Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osSchedule(VOID) { osTaskSchedule(); } /***************************************************************************** Function : LOS_Schedule Description : Function to determine whether task scheduling is required Input : None Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID LOS_Schedule(VOID) { UINTPTR uvIntSave; uvIntSave = LOS_IntLock(); /* Find the highest task */ g_stLosTask.pstNewTask = LOS_DL_LIST_ENTRY(osPriqueueTop(), LOS_TASK_CB, stPendList); /* In case that running is not highest then reschedule */ if (g_stLosTask.pstRunTask != g_stLosTask.pstNewTask) { if ((!g_usLosTaskLock)) { (VOID)LOS_IntRestore(uvIntSave); osTaskSchedule(); return; } } (VOID)LOS_IntRestore(uvIntSave); } /***************************************************************************** Function : osTaskExit Description : Task exit function Input : None Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT_MINOR VOID osTaskExit(VOID) { __disable_irq(); while(1); } /***************************************************************************** Function : osTskStackInit Description : Task stack initialization function Input : uwTaskID --- TaskID uwStackSize --- Total size of the stack pTopStack --- Top of task's stack Output : None Return : Context pointer *****************************************************************************/ LITE_OS_SEC_TEXT_INIT VOID *osTskStackInit(UINT32 uwTaskID, UINT32 uwStackSize, VOID *pTopStack) { TSK_CONTEXT_S *pstContext; /*initialize the task stack, write magic num to stack top*/ memset(pTopStack, OS_TASK_STACK_INIT, uwStackSize); *((UINT32 *)(pTopStack)) = OS_TASK_MAGIC_WORD; pstContext = (TSK_CONTEXT_S *)(((UINT32)pTopStack + uwStackSize) - sizeof(TSK_CONTEXT_S)); pstContext->uwR4 = 0x04040404L; pstContext->uwR5 = 0x05050505L; pstContext->uwR6 = 0x06060606L; pstContext->uwR7 = 0x07070707L; pstContext->uwR8 = 0x08080808L; pstContext->uwR9 = 0x09090909L; pstContext->uwR10 = 0x10101010L; pstContext->uwR11 = 0x11111111L; /* The initial interruption state(PRIMASK value: 0 --- enable) of the task */ pstContext->uwPriMask = 0; #if FPU_EXIST /** * The initial EXC_RETURN value(use 8 word stack frame, return to thread mode and use PSP). * Please do not modify it. */ pstContext->uwExcReturn = 0xFFFFFFFD; #endif pstContext->uwR0 = uwTaskID; pstContext->uwR1 = 0x01010101L; pstContext->uwR2 = 0x02020202L; pstContext->uwR3 = 0x03030303L; pstContext->uwR12 = 0x12121212L; pstContext->uwLR = (UINT32)osTaskExit; pstContext->uwPC = (UINT32)osTaskEntry; pstContext->uwxPSR = 0x01000000L; return (VOID *)pstContext; } LITE_OS_SEC_TEXT_INIT VOID osEnterSleep(VOID) { __DSB(); __WFI(); __ISB(); } #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/src/los_hw_tick.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "los_tick.ph" #include "los_base.h" #include "los_task.ph" #include "los_swtmr.h" #include "los_hwi.h" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cpluscplus */ #endif /* __cpluscplus */ /***************************************************************************** Function : osTickStart Description: Configure Tick Interrupt Start Input : none output : none return : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed *****************************************************************************/ LITE_OS_SEC_TEXT_INIT UINT32 osTickStart(VOID) { UINT32 uwRet; if ((0 == OS_SYS_CLOCK) || (0 == LOSCFG_BASE_CORE_TICK_PER_SECOND) || (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK))/*lint !e506*/ { return LOS_ERRNO_TICK_CFG_INVALID; } #if (LOSCFG_PLATFORM_HWI == YES) #if (OS_HWI_WITH_ARG == YES) osSetVector(SysTick_IRQn, (HWI_PROC_FUNC)osTickHandler, NULL); #else osSetVector(SysTick_IRQn, osTickHandler); #endif #endif g_uwCyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND; g_ullTickCount = 0; uwRet = SysTick_Config(OS_SYS_CLOCK/LOSCFG_BASE_CORE_TICK_PER_SECOND); if (uwRet == 1) { return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL; } g_bSysTickStart = TRUE; return LOS_OK; } #if (LOSCFG_KERNEL_TICKLESS == YES) /***************************************************************************** Function : LOS_SysTickReload Description: reconfig systick Input : none output : none return : none *****************************************************************************/ LITE_OS_SEC_TEXT_MINOR VOID LOS_SysTickReload(UINT32 uwCyclesPerTick) { SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; SysTick->LOAD = (uint32_t)(uwCyclesPerTick - 1UL); /* set reload register */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; } #endif /***************************************************************************** Function : LOS_SysTickCurrCycleGet Description: Get System cycle count Input : none output : SysTick->VAL return : none *****************************************************************************/ LITE_OS_SEC_TEXT_MINOR UINT32 LOS_SysTickCurrCycleGet(VOID) { UINT32 uwHwCycle; UINTPTR uvIntSave; uvIntSave = LOS_IntLock(); uwHwCycle = SysTick->VAL; /*tick has come, but may interrupt environment, not counting the Tick interrupt response, to do +1 */ if (((SCB->ICSR & 0x4000000) != 0)) { uwHwCycle = SysTick->VAL; uwHwCycle += g_uwCyclesPerTick; } LOS_IntRestore(uvIntSave); return uwHwCycle; } /***************************************************************************** Function : LOS_GetCpuCycle Description: Get System cycle count Input : none output : puwCntHi --- CpuTick High 4 byte puwCntLo --- CpuTick Low 4 byte return : none *****************************************************************************/ LITE_OS_SEC_TEXT_MINOR VOID LOS_GetCpuCycle(UINT32 *puwCntHi, UINT32 *puwCntLo) { UINT64 ullSwTick; UINT64 ullCycle; UINT32 uwHwCycle; UINTPTR uvIntSave; uvIntSave = LOS_IntLock(); ullSwTick = g_ullTickCount; uwHwCycle = SysTick->VAL; /*tick has come, but may interrupt environment, not counting the Tick interrupt response, to do +1 */ if (((SCB->ICSR & 0x4000000) != 0)) { uwHwCycle = SysTick->VAL; ullSwTick++; } ullCycle = (((ullSwTick) * g_uwCyclesPerTick) + (g_uwCyclesPerTick - uwHwCycle)); *puwCntHi = ullCycle >> 32; *puwCntLo = ullCycle & 0xFFFFFFFFU; LOS_IntRestore(uvIntSave); return; } /***************************************************************************** Function : LOS_GetSystickCycle Description: Get Sys tick cycle count Input : none output : puwCntHi --- SysTick count High 4 byte puwCntLo --- SysTick count Low 4 byte return : none *****************************************************************************/ LITE_OS_SEC_TEXT_MINOR VOID LOS_GetSystickCycle(UINT32 *puwCntHi, UINT32 *puwCntLo) { UINT64 ullSwTick; UINT64 ullCycle; UINT32 uwHwCycle; UINTPTR uvIntSave; UINT32 uwSystickLoad; UINT32 uwSystickCur; uvIntSave = LOS_IntLock(); ullSwTick = g_ullTickCount; uwSystickLoad = SysTick->LOAD; uwSystickCur = SysTick->VAL; uwHwCycle = uwSystickLoad - uwSystickCur; /*tick has come, but may interrupt environment, not counting the Tick interrupt response, to do +1 */ if (((SCB->ICSR & 0x4000000) != 0)) { uwHwCycle = uwSystickLoad - uwSystickCur; ullSwTick++; } ullCycle = uwHwCycle + ullSwTick * uwSystickLoad; *puwCntHi = ullCycle >> 32; *puwCntLo = ullCycle & 0xFFFFFFFFU; LOS_IntRestore(uvIntSave); return; } #ifdef __cplusplus #if __cplusplus } #endif /* __cpluscplus */ #endif /* __cpluscplus */ ================================================ FILE: Huawei_LiteOS/arch/arm/arm-m/src/los_hwi.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "los_hwi.h" #if (LOSCFG_KERNEL_TICKLESS == YES) #include "los_tickless.ph" #endif #if (LOSCFG_PLATFORM_HWI == NO) #include "los_tick.ph" #endif #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ #if (LOSCFG_PLATFORM_HWI == YES) /*lint -save -e40 -e522 -e533*/ LITE_OS_SEC_DATA_INIT UINT32 g_vuwIntCount = 0; /*lint -restore*/ #ifdef __ICCARM__ #pragma location = ".data.vector" #elif defined (__CC_ARM) || defined (__GNUC__) LITE_OS_SEC_VEC #endif HWI_PROC_FUNC m_pstHwiForm[OS_VECTOR_CNT] = { (HWI_PROC_FUNC)0, // [0] Top of Stack (HWI_PROC_FUNC)Reset_Handler, // [1] reset (HWI_PROC_FUNC)osHwiDefaultHandler, // [2] NMI Handler (HWI_PROC_FUNC)osHwiDefaultHandler, // [3] Hard Fault Handler (HWI_PROC_FUNC)osHwiDefaultHandler, // [4] MPU Fault Handler (HWI_PROC_FUNC)osHwiDefaultHandler, // [5] Bus Fault Handler (HWI_PROC_FUNC)osHwiDefaultHandler, // [6] Usage Fault Handler (HWI_PROC_FUNC)0, // [7] Reserved (HWI_PROC_FUNC)0, // [8] Reserved (HWI_PROC_FUNC)0, // [9] Reserved (HWI_PROC_FUNC)0, // [10] Reserved (HWI_PROC_FUNC)osHwiDefaultHandler, // [11] SVCall Handler (HWI_PROC_FUNC)osHwiDefaultHandler, // [12] Debug Monitor Handler (HWI_PROC_FUNC)0, // [13] Reserved (HWI_PROC_FUNC)PendSV_Handler, // [14] PendSV Handler (HWI_PROC_FUNC)osHwiDefaultHandler, // [15] SysTick Handler }; #if (OS_HWI_WITH_ARG == YES) LITE_OS_SEC_DATA_INIT HWI_SLAVE_FUNC m_pstHwiSlaveForm[OS_VECTOR_CNT] = {{(HWI_PROC_FUNC)0,(HWI_ARG_T)0}}; #else LITE_OS_SEC_DATA_INIT HWI_PROC_FUNC m_pstHwiSlaveForm[OS_VECTOR_CNT] = {0}; #endif #endif /*(LOSCFG_PLATFORM_HWI == YES)*/ /***************************************************************************** Function : osIntNumGet Description : Get a interrupt number Input : None Output : None Return : Interrupt Indexes number *****************************************************************************/ LITE_OS_SEC_TEXT_MINOR UINT32 osIntNumGet(VOID) { return __get_IPSR(); } #if (LOSCFG_PLATFORM_HWI == YES) /***************************************************************************** Function : osHwiDefaultHandler Description : default handler of the hardware interrupt Input : None Output : None Return : None *****************************************************************************/ /*lint -e529*/ LITE_OS_SEC_TEXT_MINOR VOID osHwiDefaultHandler(VOID) { UINT32 uwIrqNum = osIntNumGet(); PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, uwIrqNum); while(1); } /***************************************************************************** Function : osInterrupt Description : Hardware interrupt entry function Input : None Output : None Return : None *****************************************************************************/ LITE_OS_SEC_TEXT VOID osInterrupt(VOID) { UINT32 uwHwiIndex; UINT32 uwIntSave; #if(LOSCFG_KERNEL_RUNSTOP == YES) SCB->SCR &= (UINT32)~((UINT32)SCB_SCR_SLEEPDEEP_Msk); #endif uwIntSave = LOS_IntLock(); g_vuwIntCount++; LOS_IntRestore(uwIntSave); uwHwiIndex = osIntNumGet(); #if (LOSCFG_KERNEL_TICKLESS == YES) osUpdateKernelTickCount(uwHwiIndex); #endif #if (OS_HWI_WITH_ARG == YES) if (m_pstHwiSlaveForm[uwHwiIndex].pfnHandler!=0) { m_pstHwiSlaveForm[uwHwiIndex].pfnHandler((VOID*)m_pstHwiSlaveForm[uwHwiIndex].pParm); } #else if (m_pstHwiSlaveForm[uwHwiIndex] !=0) { m_pstHwiSlaveForm[uwHwiIndex](); } #endif uwIntSave = LOS_IntLock(); g_vuwIntCount--; LOS_IntRestore(uwIntSave); } /***************************************************************************** Function : osHwiInit Description : initialization of the hardware interrupt Input : None Output : None Return : OS_SUCCESS *****************************************************************************/ LITE_OS_SEC_TEXT_INIT VOID osHwiInit() { UINT32 uwIndex; for(uwIndex = OS_SYS_VECTOR_CNT; uwIndex < OS_VECTOR_CNT; uwIndex++) { m_pstHwiForm[uwIndex] = (HWI_PROC_FUNC)osHwiDefaultHandler; } /* Interrupt vector table location */ SCB->VTOR = (UINT32)m_pstHwiForm; #if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */ NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP); #endif return; } /***************************************************************************** Function : LOS_HwiCreate Description : create hardware interrupt Input : uwHwiNum --- hwi num to create usHwiPrio --- priority of the hwi usMode --- unused pfnHandler --- hwi handler uwArg --- param of the hwi handler Output : None Return : OS_SUCCESS on success or error code on failure *****************************************************************************/ LITE_OS_SEC_TEXT_INIT UINT32 LOS_HwiCreate( HWI_HANDLE_T uwHwiNum, HWI_PRIOR_T usHwiPrio, HWI_MODE_T usMode, HWI_PROC_FUNC pfnHandler, HWI_ARG_T uwArg ) { UINTPTR uvIntSave; if (NULL == pfnHandler) { return OS_ERRNO_HWI_PROC_FUNC_NULL; } if (uwHwiNum >= OS_HWI_MAX_NUM) { return OS_ERRNO_HWI_NUM_INVALID; } if (m_pstHwiForm[uwHwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)osHwiDefaultHandler) { return OS_ERRNO_HWI_ALREADY_CREATED; } if ((usHwiPrio > OS_HWI_PRIO_LOWEST) || (usHwiPrio < OS_HWI_PRIO_HIGHEST)) { return OS_ERRNO_HWI_PRIO_INVALID; } uvIntSave = LOS_IntLock(); #if (OS_HWI_WITH_ARG == YES) osSetVector(uwHwiNum, pfnHandler, uwArg); #else osSetVector(uwHwiNum, pfnHandler); #endif NVIC_EnableIRQ((IRQn_Type)uwHwiNum); NVIC_SetPriority((IRQn_Type)uwHwiNum, usHwiPrio); LOS_IntRestore(uvIntSave); return LOS_OK; } /***************************************************************************** Function : LOS_HwiDelete Description : Delete hardware interrupt Input : uwHwiNum --- hwi num to delete Output : None Return : LOS_OK on success or error code on failure *****************************************************************************/ LITE_OS_SEC_TEXT_INIT UINT32 LOS_HwiDelete(HWI_HANDLE_T uwHwiNum) { UINT32 uwIntSave; if (uwHwiNum >= OS_HWI_MAX_NUM) { return OS_ERRNO_HWI_NUM_INVALID; } NVIC_DisableIRQ((IRQn_Type)uwHwiNum); uwIntSave = LOS_IntLock(); m_pstHwiForm[uwHwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)osHwiDefaultHandler; LOS_IntRestore(uwIntSave); return LOS_OK; } #else /***************************************************************************** Function : SysTick_Handler Description : This function handles SysTick exception, Call LiteOS interface osTickHandler. Input : None Output : None Return : None *****************************************************************************/ void SysTick_Handler(void) { if (g_bSysTickStart) { osTickHandler(); } else { g_ullTickCount++; } } #endif /*(LOSCFG_PLATFORM_HWI == YES)*/ #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/arm_common_tables.h ================================================ /* ---------------------------------------------------------------------- * Project: CMSIS DSP Library * Title: arm_common_tables.h * Description: Extern declaration for common tables * * $Date: 27. January 2017 * $Revision: V.1.5.1 * * Target Processor: Cortex-M cores * -------------------------------------------------------------------- */ /* * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef _ARM_COMMON_TABLES_H #define _ARM_COMMON_TABLES_H #include "arm_math.h" extern const uint16_t armBitRevTable[1024]; extern const q15_t armRecipTableQ15[64]; extern const q31_t armRecipTableQ31[64]; extern const float32_t twiddleCoef_16[32]; extern const float32_t twiddleCoef_32[64]; extern const float32_t twiddleCoef_64[128]; extern const float32_t twiddleCoef_128[256]; extern const float32_t twiddleCoef_256[512]; extern const float32_t twiddleCoef_512[1024]; extern const float32_t twiddleCoef_1024[2048]; extern const float32_t twiddleCoef_2048[4096]; extern const float32_t twiddleCoef_4096[8192]; #define twiddleCoef twiddleCoef_4096 extern const q31_t twiddleCoef_16_q31[24]; extern const q31_t twiddleCoef_32_q31[48]; extern const q31_t twiddleCoef_64_q31[96]; extern const q31_t twiddleCoef_128_q31[192]; extern const q31_t twiddleCoef_256_q31[384]; extern const q31_t twiddleCoef_512_q31[768]; extern const q31_t twiddleCoef_1024_q31[1536]; extern const q31_t twiddleCoef_2048_q31[3072]; extern const q31_t twiddleCoef_4096_q31[6144]; extern const q15_t twiddleCoef_16_q15[24]; extern const q15_t twiddleCoef_32_q15[48]; extern const q15_t twiddleCoef_64_q15[96]; extern const q15_t twiddleCoef_128_q15[192]; extern const q15_t twiddleCoef_256_q15[384]; extern const q15_t twiddleCoef_512_q15[768]; extern const q15_t twiddleCoef_1024_q15[1536]; extern const q15_t twiddleCoef_2048_q15[3072]; extern const q15_t twiddleCoef_4096_q15[6144]; extern const float32_t twiddleCoef_rfft_32[32]; extern const float32_t twiddleCoef_rfft_64[64]; extern const float32_t twiddleCoef_rfft_128[128]; extern const float32_t twiddleCoef_rfft_256[256]; extern const float32_t twiddleCoef_rfft_512[512]; extern const float32_t twiddleCoef_rfft_1024[1024]; extern const float32_t twiddleCoef_rfft_2048[2048]; extern const float32_t twiddleCoef_rfft_4096[4096]; /* floating-point bit reversal tables */ #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; /* fixed-point bit reversal tables */ #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; /* Tables for Fast Math Sine and Cosine */ extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; #endif /* ARM_COMMON_TABLES_H */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/arm_const_structs.h ================================================ /* ---------------------------------------------------------------------- * Project: CMSIS DSP Library * Title: arm_const_structs.h * Description: Constant structs that are initialized for user convenience. * For example, some can be given as arguments to the arm_cfft_f32() function. * * $Date: 27. January 2017 * $Revision: V.1.5.1 * * Target Processor: Cortex-M cores * -------------------------------------------------------------------- */ /* * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef _ARM_CONST_STRUCTS_H #define _ARM_CONST_STRUCTS_H #include "arm_math.h" #include "arm_common_tables.h" extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; #endif ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/arm_math.h ================================================ /* ---------------------------------------------------------------------- * Project: CMSIS DSP Library * Title: arm_math.h * Description: Public header file for CMSIS DSP Library * * $Date: 27. January 2017 * $Revision: V.1.5.1 * * Target Processor: Cortex-M cores * -------------------------------------------------------------------- */ /* * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /** \mainpage CMSIS DSP Software Library * * Introduction * ------------ * * This user manual describes the CMSIS DSP software library, * a suite of common signal processing functions for use on Cortex-M processor based devices. * * The library is divided into a number of functions each covering a specific category: * - Basic math functions * - Fast math functions * - Complex math functions * - Filters * - Matrix functions * - Transforms * - Motor control functions * - Statistical functions * - Support functions * - Interpolation functions * * The library has separate functions for operating on 8-bit integers, 16-bit integers, * 32-bit integer and 32-bit floating-point values. * * Using the Library * ------------ * * The library installer contains prebuilt versions of the libraries in the Lib folder. * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian) * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian) * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit) * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions) * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) * * The library functions are declared in the public file arm_math.h which is placed in the Include folder. * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions. * * * Examples * -------- * * The library ships with a number of examples which demonstrate how to use the library functions. * * Toolchain Support * ------------ * * The library has been developed and tested with MDK-ARM version 5.14.0.0 * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. * * Building the Library * ------------ * * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. * - arm_cortexM_math.uvprojx * * * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. * * Pre-processor Macros * ------------ * * Each library project have differant pre-processor macros. * * - UNALIGNED_SUPPORT_DISABLE: * * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access * * - ARM_MATH_BIG_ENDIAN: * * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. * * - ARM_MATH_MATRIX_CHECK: * * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices * * - ARM_MATH_ROUNDING: * * Define macro ARM_MATH_ROUNDING for rounding on support functions * * - ARM_MATH_CMx: * * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and * ARM_MATH_CM7 for building the library on cortex-M7. * * - ARM_MATH_ARMV8MxL: * * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library * on ARMv8M Mainline target. * * - __FPU_PRESENT: * * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. * * - __DSP_PRESENT: * * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions. * *
    * CMSIS-DSP in ARM::CMSIS Pack * ----------------------------- * * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: * |File/Folder |Content | * |------------------------------|------------------------------------------------------------------------| * |\b CMSIS\\Documentation\\DSP | This documentation | * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | * *
    * Revision History of CMSIS-DSP * ------------ * Please refer to \ref ChangeLog_pg. * * Copyright Notice * ------------ * * Copyright (C) 2010-2015 ARM Limited. All rights reserved. */ /** * @defgroup groupMath Basic Math Functions */ /** * @defgroup groupFastMath Fast Math Functions * This set of functions provides a fast approximation to sine, cosine, and square root. * As compared to most of the other functions in the CMSIS math library, the fast math functions * operate on individual values and not arrays. * There are separate functions for Q15, Q31, and floating-point data. * */ /** * @defgroup groupCmplxMath Complex Math Functions * This set of functions operates on complex data vectors. * The data in the complex arrays is stored in an interleaved fashion * (real, imag, real, imag, ...). * In the API functions, the number of samples in a complex array refers * to the number of complex values; the array contains twice this number of * real values. */ /** * @defgroup groupFilters Filtering Functions */ /** * @defgroup groupMatrix Matrix Functions * * This set of functions provides basic matrix math operations. * The functions operate on matrix data structures. For example, * the type * definition for the floating-point matrix structure is shown * below: * 
     *     typedef struct
 *     {
 *       uint16_t numRows;     // number of rows of the matrix.
 *       uint16_t numCols;     // number of columns of the matrix.
 *       float32_t *pData;     // points to the data of the matrix.
 *     } arm_matrix_instance_f32;
 *
    * There are similar definitions for Q15 and Q31 data types. * * The structure specifies the size of the matrix and then points to * an array of data. The array is of size numRows X numCols * and the values are arranged in row order. That is, the * matrix element (i, j) is stored at: * 
     *     pData[i*numCols + j]
 *
    * * \par Init Functions * There is an associated initialization function for each type of matrix * data structure. * The initialization function sets the values of the internal structure fields. * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. * * \par * Use of the initialization function is optional. However, if initialization function is used * then the instance structure cannot be placed into a const data section. * To place the instance structure in a const data * section, manually initialize the data structure. For example: * 
     * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
 * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
 * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
 *
    * where nRows specifies the number of rows, nColumns * specifies the number of columns, and pData points to the * data array. * * \par Size Checking * By default all of the matrix functions perform size checking on the input and * output matrices. For example, the matrix addition function verifies that the * two input matrices and the output matrix all have the same number of rows and * columns. If the size check fails the functions return: * 
     *     ARM_MATH_SIZE_MISMATCH
 *
    * Otherwise the functions return * 
     *     ARM_MATH_SUCCESS
 *
    * There is some overhead associated with this matrix size checking. * The matrix size checking is enabled via the \#define * 
     *     ARM_MATH_MATRIX_CHECK
 *
    * within the library project settings. By default this macro is defined * and size checking is enabled. By changing the project settings and * undefining this macro size checking is eliminated and the functions * run a bit faster. With size checking disabled the functions always * return ARM_MATH_SUCCESS. */ /** * @defgroup groupTransforms Transform Functions */ /** * @defgroup groupController Controller Functions */ /** * @defgroup groupStats Statistics Functions */ /** * @defgroup groupSupport Support Functions */ /** * @defgroup groupInterpolation Interpolation Functions * These functions perform 1- and 2-dimensional interpolation of data. * Linear interpolation is used for 1-dimensional data and * bilinear interpolation is used for 2-dimensional data. */ /** * @defgroup groupExamples Examples */ #ifndef _ARM_MATH_H #define _ARM_MATH_H /* ignore some GCC warnings */ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" #endif #define __CMSIS_GENERIC /* disable NVIC and Systick functions */ #if defined(ARM_MATH_CM7) #include "core_cm7.h" #define ARM_MATH_DSP #elif defined (ARM_MATH_CM4) #include "core_cm4.h" #define ARM_MATH_DSP #elif defined (ARM_MATH_CM3) #include "core_cm3.h" #elif defined (ARM_MATH_CM0) #include "core_cm0.h" #define ARM_MATH_CM0_FAMILY #elif defined (ARM_MATH_CM0PLUS) #include "core_cm0plus.h" #define ARM_MATH_CM0_FAMILY #elif defined (ARM_MATH_ARMV8MBL) #include "core_armv8mbl.h" #define ARM_MATH_CM0_FAMILY #elif defined (ARM_MATH_ARMV8MML) #include "core_armv8mml.h" #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) #define ARM_MATH_DSP #endif #else #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" #endif #undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ #include "string.h" #include "math.h" #ifdef __cplusplus extern "C" { #endif /** * @brief Macros required for reciprocal calculation in Normalized LMS */ #define DELTA_Q31 (0x100) #define DELTA_Q15 0x5 #define INDEX_MASK 0x0000003F #ifndef PI #define PI 3.14159265358979f #endif /** * @brief Macros required for SINE and COSINE Fast math approximations */ #define FAST_MATH_TABLE_SIZE 512 #define FAST_MATH_Q31_SHIFT (32 - 10) #define FAST_MATH_Q15_SHIFT (16 - 10) #define CONTROLLER_Q31_SHIFT (32 - 9) #define TABLE_SPACING_Q31 0x400000 #define TABLE_SPACING_Q15 0x80 /** * @brief Macros required for SINE and COSINE Controller functions */ /* 1.31(q31) Fixed value of 2/360 */ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ #define INPUT_SPACING 0xB60B61 /** * @brief Macro for Unaligned Support */ #ifndef UNALIGNED_SUPPORT_DISABLE #define ALIGN4 #else #if defined (__GNUC__) #define ALIGN4 __attribute__((aligned(4))) #else #define ALIGN4 __align(4) #endif #endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ /** * @brief Error status returned by some functions in the library. */ typedef enum { ARM_MATH_SUCCESS = 0, /**< No error */ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ } arm_status; /** * @brief 8-bit fractional data type in 1.7 format. */ typedef int8_t q7_t; /** * @brief 16-bit fractional data type in 1.15 format. */ typedef int16_t q15_t; /** * @brief 32-bit fractional data type in 1.31 format. */ typedef int32_t q31_t; /** * @brief 64-bit fractional data type in 1.63 format. */ typedef int64_t q63_t; /** * @brief 32-bit floating-point type definition. */ typedef float float32_t; /** * @brief 64-bit floating-point type definition. */ typedef double float64_t; #define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) #define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) #define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) #define __SIMD64(addr) (*(int64_t **) & (addr)) /* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ #if !defined (ARM_MATH_DSP) /** * @brief definition to pack two 16 bit values. */ #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) /* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ #endif /* !defined (ARM_MATH_DSP) */ /** * @brief definition to pack four 8 bit values. */ #ifndef ARM_MATH_BIG_ENDIAN #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) #else #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) #endif /** * @brief Clips Q63 to Q31 values. */ CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( q63_t x) { return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; } /** * @brief Clips Q63 to Q15 values. */ CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( q63_t x) { return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); } /** * @brief Clips Q31 to Q7 values. */ CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( q31_t x) { return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; } /** * @brief Clips Q31 to Q15 values. */ CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( q31_t x) { return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; } /** * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. */ CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( q63_t x, q31_t y) { return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + (((q63_t) (x >> 32) * y))); } /* #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) #define __CLZ __clz #endif */ /* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ #if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( q31_t data); CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( q31_t data) { uint32_t count = 0; uint32_t mask = 0x80000000; while ((data & mask) == 0) { count += 1u; mask = mask >> 1u; } return (count); } #endif /** * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. */ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( q31_t in, q31_t * dst, q31_t * pRecipTable) { q31_t out; uint32_t tempVal; uint32_t index, i; uint32_t signBits; if (in > 0) { signBits = ((uint32_t) (__CLZ( in) - 1)); } else { signBits = ((uint32_t) (__CLZ(-in) - 1)); } /* Convert input sample to 1.31 format */ in = (in << signBits); /* calculation of index for initial approximated Val */ index = (uint32_t)(in >> 24); index = (index & INDEX_MASK); /* 1.31 with exp 1 */ out = pRecipTable[index]; /* calculation of reciprocal value */ /* running approximation for two iterations */ for (i = 0u; i < 2u; i++) { tempVal = (uint32_t) (((q63_t) in * out) >> 31); tempVal = 0x7FFFFFFFu - tempVal; /* 1.31 with exp 1 */ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); } /* write output */ *dst = out; /* return num of signbits of out = 1/in value */ return (signBits + 1u); } /** * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. */ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( q15_t in, q15_t * dst, q15_t * pRecipTable) { q15_t out = 0; uint32_t tempVal = 0; uint32_t index = 0, i = 0; uint32_t signBits = 0; if (in > 0) { signBits = ((uint32_t)(__CLZ( in) - 17)); } else { signBits = ((uint32_t)(__CLZ(-in) - 17)); } /* Convert input sample to 1.15 format */ in = (in << signBits); /* calculation of index for initial approximated Val */ index = (uint32_t)(in >> 8); index = (index & INDEX_MASK); /* 1.15 with exp 1 */ out = pRecipTable[index]; /* calculation of reciprocal value */ /* running approximation for two iterations */ for (i = 0u; i < 2u; i++) { tempVal = (uint32_t) (((q31_t) in * out) >> 15); tempVal = 0x7FFFu - tempVal; /* 1.15 with exp 1 */ out = (q15_t) (((q31_t) out * tempVal) >> 14); /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ } /* write output */ *dst = out; /* return num of signbits of out = 1/in value */ return (signBits + 1); } /* * @brief C custom defined intrinisic function for only M0 processors */ #if defined(ARM_MATH_CM0_FAMILY) CMSIS_INLINE __STATIC_INLINE q31_t __SSAT( q31_t x, uint32_t y) { int32_t posMax, negMin; uint32_t i; posMax = 1; for (i = 0; i < (y - 1); i++) { posMax = posMax * 2; } if (x > 0) { posMax = (posMax - 1); if (x > posMax) { x = posMax; } } else { negMin = -posMax; if (x < negMin) { x = negMin; } } return (x); } #endif /* end of ARM_MATH_CM0_FAMILY */ /* * @brief C custom defined intrinsic function for M3 and M0 processors */ /* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ #if !defined (ARM_MATH_DSP) /* * @brief C custom defined QADD8 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( uint32_t x, uint32_t y) { q31_t r, s, t, u; r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); } /* * @brief C custom defined QSUB8 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( uint32_t x, uint32_t y) { q31_t r, s, t, u; r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); } /* * @brief C custom defined QADD16 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( uint32_t x, uint32_t y) { /* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ q31_t r = 0, s = 0; r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined SHADD16 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( uint32_t x, uint32_t y) { q31_t r, s; r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined QSUB16 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( uint32_t x, uint32_t y) { q31_t r, s; r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined SHSUB16 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( uint32_t x, uint32_t y) { q31_t r, s; r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined QASX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( uint32_t x, uint32_t y) { q31_t r, s; r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined SHASX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( uint32_t x, uint32_t y) { q31_t r, s; r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined QSAX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( uint32_t x, uint32_t y) { q31_t r, s; r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined SHSAX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( uint32_t x, uint32_t y) { q31_t r, s; r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r ))); } /* * @brief C custom defined SMUSDX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); } /* * @brief C custom defined SMUADX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); } /* * @brief C custom defined QADD for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE int32_t __QADD( int32_t x, int32_t y) { return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); } /* * @brief C custom defined QSUB for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( int32_t x, int32_t y) { return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); } /* * @brief C custom defined SMLAD for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( uint32_t x, uint32_t y, uint32_t sum) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + ( ((q31_t)sum ) ) )); } /* * @brief C custom defined SMLADX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( uint32_t x, uint32_t y, uint32_t sum) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + ( ((q31_t)sum ) ) )); } /* * @brief C custom defined SMLSDX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( uint32_t x, uint32_t y, uint32_t sum) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + ( ((q31_t)sum ) ) )); } /* * @brief C custom defined SMLALD for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( uint32_t x, uint32_t y, uint64_t sum) { /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + ( ((q63_t)sum ) ) )); } /* * @brief C custom defined SMLALDX for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( uint32_t x, uint32_t y, uint64_t sum) { /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + ( ((q63_t)sum ) ) )); } /* * @brief C custom defined SMUAD for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); } /* * @brief C custom defined SMUSD for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); } /* * @brief C custom defined SXTB16 for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( uint32_t x) { return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); } /* * @brief C custom defined SMMLA for M3 and M0 processors */ CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( int32_t x, int32_t y, int32_t sum) { return (sum + (int32_t) (((int64_t) x * y) >> 32)); } #if 0 /* * @brief C custom defined PKHBT for unavailable DSP extension */ CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT( uint32_t x, uint32_t y, uint32_t leftshift) { return ( ((x ) & 0x0000FFFFUL) | ((y << leftshift) & 0xFFFF0000UL) ); } /* * @brief C custom defined PKHTB for unavailable DSP extension */ CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB( uint32_t x, uint32_t y, uint32_t rightshift) { return ( ((x ) & 0xFFFF0000UL) | ((y >> rightshift) & 0x0000FFFFUL) ); } #endif /* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ #endif /* !defined (ARM_MATH_DSP) */ /** * @brief Instance structure for the Q7 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q7; /** * @brief Instance structure for the Q15 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q15; /** * @brief Instance structure for the Q31 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_q31; /** * @brief Instance structure for the floating-point FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_f32; /** * @brief Processing function for the Q7 FIR filter. * @param[in] S points to an instance of the Q7 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_q7( const arm_fir_instance_q7 * S, q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q7 FIR filter. * @param[in,out] S points to an instance of the Q7 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed. */ void arm_fir_init_q7( arm_fir_instance_q7 * S, uint16_t numTaps, q7_t * pCoeffs, q7_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR filter. * @param[in] S points to an instance of the Q15 FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_q15( const arm_fir_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q15 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_fast_q15( const arm_fir_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR filter. * @param[in,out] S points to an instance of the Q15 FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if * numTaps is not a supported value. */ arm_status arm_fir_init_q15( arm_fir_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR filter. * @param[in] S points to an instance of the Q31 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_q31( const arm_fir_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q31 FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_fast_q31( const arm_fir_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR filter. * @param[in,out] S points to an instance of the Q31 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. */ void arm_fir_init_q31( arm_fir_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Processing function for the floating-point FIR filter. * @param[in] S points to an instance of the floating-point FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_f32( const arm_fir_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR filter. * @param[in,out] S points to an instance of the floating-point FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. */ void arm_fir_init_f32( arm_fir_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Instance structure for the Q15 Biquad cascade filter. */ typedef struct { int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ } arm_biquad_casd_df1_inst_q15; /** * @brief Instance structure for the Q31 Biquad cascade filter. */ typedef struct { uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ } arm_biquad_casd_df1_inst_q31; /** * @brief Instance structure for the floating-point Biquad cascade filter. */ typedef struct { uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_casd_df1_inst_f32; /** * @brief Processing function for the Q15 Biquad cascade filter. * @param[in] S points to an instance of the Q15 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_q15( const arm_biquad_casd_df1_inst_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 Biquad cascade filter. * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format */ void arm_biquad_cascade_df1_init_q15( arm_biquad_casd_df1_inst_q15 * S, uint8_t numStages, q15_t * pCoeffs, q15_t * pState, int8_t postShift); /** * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q15 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_fast_q15( const arm_biquad_casd_df1_inst_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Processing function for the Q31 Biquad cascade filter * @param[in] S points to an instance of the Q31 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_q31( const arm_biquad_casd_df1_inst_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q31 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_fast_q31( const arm_biquad_casd_df1_inst_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 Biquad cascade filter. * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format */ void arm_biquad_cascade_df1_init_q31( arm_biquad_casd_df1_inst_q31 * S, uint8_t numStages, q31_t * pCoeffs, q31_t * pState, int8_t postShift); /** * @brief Processing function for the floating-point Biquad cascade filter. * @param[in] S points to an instance of the floating-point Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_f32( const arm_biquad_casd_df1_inst_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point Biquad cascade filter. * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_df1_init_f32( arm_biquad_casd_df1_inst_f32 * S, uint8_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Instance structure for the floating-point matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ float32_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_f32; /** * @brief Instance structure for the floating-point matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ float64_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_f64; /** * @brief Instance structure for the Q15 matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ q15_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_q15; /** * @brief Instance structure for the Q31 matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ q31_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_q31; /** * @brief Floating-point matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_add_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_add_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_add_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_cmplx_mult_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_cmplx_mult_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst, q15_t * pScratch); /** * @brief Q31, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_cmplx_mult_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_trans_f32( const arm_matrix_instance_f32 * pSrc, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_trans_q15( const arm_matrix_instance_q15 * pSrc, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_trans_q31( const arm_matrix_instance_q31 * pSrc, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @param[in] pState points to the array for storing intermediate results * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst, q15_t * pState); /** * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @param[in] pState points to the array for storing intermediate results * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_fast_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst, q15_t * pState); /** * @brief Q31 matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_fast_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_sub_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_sub_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_sub_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix scaling. * @param[in] pSrc points to the input matrix * @param[in] scale scale factor * @param[out] pDst points to the output matrix * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_scale_f32( const arm_matrix_instance_f32 * pSrc, float32_t scale, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix scaling. * @param[in] pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor * @param[in] shift number of bits to shift the result by * @param[out] pDst points to output matrix * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_scale_q15( const arm_matrix_instance_q15 * pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix scaling. * @param[in] pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor * @param[in] shift number of bits to shift the result by * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_scale_q31( const arm_matrix_instance_q31 * pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 * pDst); /** * @brief Q31 matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ void arm_mat_init_q31( arm_matrix_instance_q31 * S, uint16_t nRows, uint16_t nColumns, q31_t * pData); /** * @brief Q15 matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ void arm_mat_init_q15( arm_matrix_instance_q15 * S, uint16_t nRows, uint16_t nColumns, q15_t * pData); /** * @brief Floating-point matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ void arm_mat_init_f32( arm_matrix_instance_f32 * S, uint16_t nRows, uint16_t nColumns, float32_t * pData); /** * @brief Instance structure for the Q15 PID Control. */ typedef struct { q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ #if !defined (ARM_MATH_DSP) q15_t A1; q15_t A2; #else q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ #endif q15_t state[3]; /**< The state array of length 3. */ q15_t Kp; /**< The proportional gain. */ q15_t Ki; /**< The integral gain. */ q15_t Kd; /**< The derivative gain. */ } arm_pid_instance_q15; /** * @brief Instance structure for the Q31 PID Control. */ typedef struct { q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ q31_t A2; /**< The derived gain, A2 = Kd . */ q31_t state[3]; /**< The state array of length 3. */ q31_t Kp; /**< The proportional gain. */ q31_t Ki; /**< The integral gain. */ q31_t Kd; /**< The derivative gain. */ } arm_pid_instance_q31; /** * @brief Instance structure for the floating-point PID Control. */ typedef struct { float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ float32_t A2; /**< The derived gain, A2 = Kd . */ float32_t state[3]; /**< The state array of length 3. */ float32_t Kp; /**< The proportional gain. */ float32_t Ki; /**< The integral gain. */ float32_t Kd; /**< The derivative gain. */ } arm_pid_instance_f32; /** * @brief Initialization function for the floating-point PID Control. * @param[in,out] S points to an instance of the PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ void arm_pid_init_f32( arm_pid_instance_f32 * S, int32_t resetStateFlag); /** * @brief Reset function for the floating-point PID Control. * @param[in,out] S is an instance of the floating-point PID Control structure */ void arm_pid_reset_f32( arm_pid_instance_f32 * S); /** * @brief Initialization function for the Q31 PID Control. * @param[in,out] S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ void arm_pid_init_q31( arm_pid_instance_q31 * S, int32_t resetStateFlag); /** * @brief Reset function for the Q31 PID Control. * @param[in,out] S points to an instance of the Q31 PID Control structure */ void arm_pid_reset_q31( arm_pid_instance_q31 * S); /** * @brief Initialization function for the Q15 PID Control. * @param[in,out] S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ void arm_pid_init_q15( arm_pid_instance_q15 * S, int32_t resetStateFlag); /** * @brief Reset function for the Q15 PID Control. * @param[in,out] S points to an instance of the q15 PID Control structure */ void arm_pid_reset_q15( arm_pid_instance_q15 * S); /** * @brief Instance structure for the floating-point Linear Interpolate function. */ typedef struct { uint32_t nValues; /**< nValues */ float32_t x1; /**< x1 */ float32_t xSpacing; /**< xSpacing */ float32_t *pYData; /**< pointer to the table of Y values */ } arm_linear_interp_instance_f32; /** * @brief Instance structure for the floating-point bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ float32_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_f32; /** * @brief Instance structure for the Q31 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q31_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q31; /** * @brief Instance structure for the Q15 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q15_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q15; /** * @brief Instance structure for the Q15 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q7_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q7; /** * @brief Q7 vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_mult_q7( q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, uint32_t blockSize); /** * @brief Q15 vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_mult_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_mult_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t blockSize); /** * @brief Floating-point vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_mult_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t blockSize); /** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix2_instance_q15; /* Deprecated */ arm_status arm_cfft_radix2_init_q15( arm_cfft_radix2_instance_q15 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_q15( const arm_cfft_radix2_instance_q15 * S, q15_t * pSrc); /** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q15_t *pTwiddle; /**< points to the twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix4_instance_q15; /* Deprecated */ arm_status arm_cfft_radix4_init_q15( arm_cfft_radix4_instance_q15 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix4_q15( const arm_cfft_radix4_instance_q15 * S, q15_t * pSrc); /** * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q31_t *pTwiddle; /**< points to the Twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix2_instance_q31; /* Deprecated */ arm_status arm_cfft_radix2_init_q31( arm_cfft_radix2_instance_q31 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_q31( const arm_cfft_radix2_instance_q31 * S, q31_t * pSrc); /** * @brief Instance structure for the Q31 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q31_t *pTwiddle; /**< points to the twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix4_instance_q31; /* Deprecated */ void arm_cfft_radix4_q31( const arm_cfft_radix4_instance_q31 * S, q31_t * pSrc); /* Deprecated */ arm_status arm_cfft_radix4_init_q31( arm_cfft_radix4_instance_q31 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ float32_t *pTwiddle; /**< points to the Twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ float32_t onebyfftLen; /**< value of 1/fftLen. */ } arm_cfft_radix2_instance_f32; /* Deprecated */ arm_status arm_cfft_radix2_init_f32( arm_cfft_radix2_instance_f32 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_f32( const arm_cfft_radix2_instance_f32 * S, float32_t * pSrc); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ float32_t *pTwiddle; /**< points to the Twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ float32_t onebyfftLen; /**< value of 1/fftLen. */ } arm_cfft_radix4_instance_f32; /* Deprecated */ arm_status arm_cfft_radix4_init_f32( arm_cfft_radix4_instance_f32 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix4_f32( const arm_cfft_radix4_instance_f32 * S, float32_t * pSrc); /** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_q15; void arm_cfft_q15( const arm_cfft_instance_q15 * S, q15_t * p1, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_q31; void arm_cfft_q31( const arm_cfft_instance_q31 * S, q31_t * p1, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_f32; void arm_cfft_f32( const arm_cfft_instance_f32 * S, float32_t * p1, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the Q15 RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_q15; arm_status arm_rfft_init_q15( arm_rfft_instance_q15 * S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); void arm_rfft_q15( const arm_rfft_instance_q15 * S, q15_t * pSrc, q15_t * pDst); /** * @brief Instance structure for the Q31 RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_q31; arm_status arm_rfft_init_q31( arm_rfft_instance_q31 * S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); void arm_rfft_q31( const arm_rfft_instance_q31 * S, q31_t * pSrc, q31_t * pDst); /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint16_t fftLenBy2; /**< length of the complex FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_f32; arm_status arm_rfft_init_f32( arm_rfft_instance_f32 * S, arm_cfft_radix4_instance_f32 * S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); void arm_rfft_f32( const arm_rfft_instance_f32 * S, float32_t * pSrc, float32_t * pDst); /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ typedef struct { arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ uint16_t fftLenRFFT; /**< length of the real sequence */ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ } arm_rfft_fast_instance_f32 ; arm_status arm_rfft_fast_init_f32 ( arm_rfft_fast_instance_f32 * S, uint16_t fftLen); void arm_rfft_fast_f32( arm_rfft_fast_instance_f32 * S, float32_t * p, float32_t * pOut, uint8_t ifftFlag); /** * @brief Instance structure for the floating-point DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ float32_t normalize; /**< normalizing factor. */ float32_t *pTwiddle; /**< points to the twiddle factor table. */ float32_t *pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_f32; /** * @brief Initialization function for the floating-point DCT4/IDCT4. * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. */ arm_status arm_dct4_init_f32( arm_dct4_instance_f32 * S, arm_rfft_instance_f32 * S_RFFT, arm_cfft_radix4_instance_f32 * S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize); /** * @brief Processing function for the floating-point DCT4/IDCT4. * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. * @param[in] pState points to state buffer. * @param[in,out] pInlineBuffer points to the in-place input and output buffer. */ void arm_dct4_f32( const arm_dct4_instance_f32 * S, float32_t * pState, float32_t * pInlineBuffer); /** * @brief Instance structure for the Q31 DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ q31_t normalize; /**< normalizing factor. */ q31_t *pTwiddle; /**< points to the twiddle factor table. */ q31_t *pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_q31; /** * @brief Initialization function for the Q31 DCT4/IDCT4. * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ arm_status arm_dct4_init_q31( arm_dct4_instance_q31 * S, arm_rfft_instance_q31 * S_RFFT, arm_cfft_radix4_instance_q31 * S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize); /** * @brief Processing function for the Q31 DCT4/IDCT4. * @param[in] S points to an instance of the Q31 DCT4 structure. * @param[in] pState points to state buffer. * @param[in,out] pInlineBuffer points to the in-place input and output buffer. */ void arm_dct4_q31( const arm_dct4_instance_q31 * S, q31_t * pState, q31_t * pInlineBuffer); /** * @brief Instance structure for the Q15 DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ q15_t normalize; /**< normalizing factor. */ q15_t *pTwiddle; /**< points to the twiddle factor table. */ q15_t *pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_q15; /** * @brief Initialization function for the Q15 DCT4/IDCT4. * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ arm_status arm_dct4_init_q15( arm_dct4_instance_q15 * S, arm_rfft_instance_q15 * S_RFFT, arm_cfft_radix4_instance_q15 * S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize); /** * @brief Processing function for the Q15 DCT4/IDCT4. * @param[in] S points to an instance of the Q15 DCT4 structure. * @param[in] pState points to state buffer. * @param[in,out] pInlineBuffer points to the in-place input and output buffer. */ void arm_dct4_q15( const arm_dct4_instance_q15 * S, q15_t * pState, q15_t * pInlineBuffer); /** * @brief Floating-point vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_add_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t blockSize); /** * @brief Q7 vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_add_q7( q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, uint32_t blockSize); /** * @brief Q15 vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_add_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_add_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t blockSize); /** * @brief Floating-point vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_sub_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t blockSize); /** * @brief Q7 vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_sub_q7( q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, uint32_t blockSize); /** * @brief Q15 vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_sub_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_sub_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t blockSize); /** * @brief Multiplies a floating-point vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scale scale factor to be applied * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_scale_f32( float32_t * pSrc, float32_t scale, float32_t * pDst, uint32_t blockSize); /** * @brief Multiplies a Q7 vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_scale_q7( q7_t * pSrc, q7_t scaleFract, int8_t shift, q7_t * pDst, uint32_t blockSize); /** * @brief Multiplies a Q15 vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_scale_q15( q15_t * pSrc, q15_t scaleFract, int8_t shift, q15_t * pDst, uint32_t blockSize); /** * @brief Multiplies a Q31 vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_scale_q31( q31_t * pSrc, q31_t scaleFract, int8_t shift, q31_t * pDst, uint32_t blockSize); /** * @brief Q7 vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ void arm_abs_q7( q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Floating-point vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ void arm_abs_f32( float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Q15 vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ void arm_abs_q15( q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ void arm_abs_q31( q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Dot product of floating-point vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ void arm_dot_prod_f32( float32_t * pSrcA, float32_t * pSrcB, uint32_t blockSize, float32_t * result); /** * @brief Dot product of Q7 vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ void arm_dot_prod_q7( q7_t * pSrcA, q7_t * pSrcB, uint32_t blockSize, q31_t * result); /** * @brief Dot product of Q15 vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ void arm_dot_prod_q15( q15_t * pSrcA, q15_t * pSrcB, uint32_t blockSize, q63_t * result); /** * @brief Dot product of Q31 vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ void arm_dot_prod_q31( q31_t * pSrcA, q31_t * pSrcB, uint32_t blockSize, q63_t * result); /** * @brief Shifts the elements of a Q7 vector a specified number of bits. * @param[in] pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_shift_q7( q7_t * pSrc, int8_t shiftBits, q7_t * pDst, uint32_t blockSize); /** * @brief Shifts the elements of a Q15 vector a specified number of bits. * @param[in] pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_shift_q15( q15_t * pSrc, int8_t shiftBits, q15_t * pDst, uint32_t blockSize); /** * @brief Shifts the elements of a Q31 vector a specified number of bits. * @param[in] pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_shift_q31( q31_t * pSrc, int8_t shiftBits, q31_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a floating-point vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_offset_f32( float32_t * pSrc, float32_t offset, float32_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q7 vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_offset_q7( q7_t * pSrc, q7_t offset, q7_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q15 vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_offset_q15( q15_t * pSrc, q15_t offset, q15_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q31 vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_offset_q31( q31_t * pSrc, q31_t offset, q31_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a floating-point vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_negate_f32( float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q7 vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_negate_q7( q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q15 vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_negate_q15( q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q31 vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_negate_q31( q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a floating-point vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_copy_f32( float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q7 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_copy_q7( q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q15 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_copy_q15( q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q31 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_copy_q31( q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a floating-point vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_fill_f32( float32_t value, float32_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q7 vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_fill_q7( q7_t value, q7_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q15 vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_fill_q15( q15_t value, q15_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q31 vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_fill_q31( q31_t value, q31_t * pDst, uint32_t blockSize); /** * @brief Convolution of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. */ void arm_conv_f32( float32_t * pSrcA, uint32_t srcALen, float32_t * pSrcB, uint32_t srcBLen, float32_t * pDst); /** * @brief Convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). */ void arm_conv_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. */ void arm_conv_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_fast_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). */ void arm_conv_fast_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Convolution of Q31 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_fast_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Convolution of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). */ void arm_conv_opt_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Convolution of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst); /** * @brief Partial convolution of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_f32( float32_t * pSrcA, uint32_t srcALen, float32_t * pSrcB, uint32_t srcBLen, float32_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Partial convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Partial convolution of Q31 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q7 sequences * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_opt_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, uint32_t firstIndex, uint32_t numPoints, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Partial convolution of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Instance structure for the Q15 FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_q15; /** * @brief Instance structure for the Q31 FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_q31; /** * @brief Instance structure for the floating-point FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_f32; /** * @brief Processing function for the floating-point FIR decimator. * @param[in] S points to an instance of the floating-point FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_f32( const arm_fir_decimate_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR decimator. * @param[in,out] S points to an instance of the floating-point FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_f32( arm_fir_decimate_instance_f32 * S, uint16_t numTaps, uint8_t M, float32_t * pCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR decimator. * @param[in] S points to an instance of the Q15 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_q15( const arm_fir_decimate_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q15 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_fast_q15( const arm_fir_decimate_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR decimator. * @param[in,out] S points to an instance of the Q15 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_q15( arm_fir_decimate_instance_q15 * S, uint16_t numTaps, uint8_t M, q15_t * pCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR decimator. * @param[in] S points to an instance of the Q31 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_q31( const arm_fir_decimate_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q31 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_fast_q31( arm_fir_decimate_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR decimator. * @param[in,out] S points to an instance of the Q31 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_q31( arm_fir_decimate_instance_q31 * S, uint16_t numTaps, uint8_t M, q31_t * pCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Instance structure for the Q15 FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ } arm_fir_interpolate_instance_q15; /** * @brief Instance structure for the Q31 FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ } arm_fir_interpolate_instance_q31; /** * @brief Instance structure for the floating-point FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ } arm_fir_interpolate_instance_f32; /** * @brief Processing function for the Q15 FIR interpolator. * @param[in] S points to an instance of the Q15 FIR interpolator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_interpolate_q15( const arm_fir_interpolate_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR interpolator. * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficient buffer. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_q15( arm_fir_interpolate_instance_q15 * S, uint8_t L, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR interpolator. * @param[in] S points to an instance of the Q15 FIR interpolator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_interpolate_q31( const arm_fir_interpolate_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR interpolator. * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficient buffer. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_q31( arm_fir_interpolate_instance_q31 * S, uint8_t L, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Processing function for the floating-point FIR interpolator. * @param[in] S points to an instance of the floating-point FIR interpolator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_interpolate_f32( const arm_fir_interpolate_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR interpolator. * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficient buffer. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_f32( arm_fir_interpolate_instance_f32 * S, uint8_t L, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Instance structure for the high precision Q31 Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ } arm_biquad_cas_df1_32x64_ins_q31; /** * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_biquad_cas_df1_32x64_q31( const arm_biquad_cas_df1_32x64_ins_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format */ void arm_biquad_cas_df1_32x64_init_q31( arm_biquad_cas_df1_32x64_ins_q31 * S, uint8_t numStages, q31_t * pCoeffs, q63_t * pState, uint8_t postShift); /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_df2T_instance_f32; /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_stereo_df2T_instance_f32; /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_df2T_instance_f64; /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df2T_f32( const arm_biquad_cascade_df2T_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_stereo_df2T_f32( const arm_biquad_cascade_stereo_df2T_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df2T_f64( const arm_biquad_cascade_df2T_instance_f64 * S, float64_t * pSrc, float64_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_df2T_init_f32( arm_biquad_cascade_df2T_instance_f32 * S, uint8_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_stereo_df2T_init_f32( arm_biquad_cascade_stereo_df2T_instance_f32 * S, uint8_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_df2T_init_f64( arm_biquad_cascade_df2T_instance_f64 * S, uint8_t numStages, float64_t * pCoeffs, float64_t * pState); /** * @brief Instance structure for the Q15 FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_q15; /** * @brief Instance structure for the Q31 FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_q31; /** * @brief Instance structure for the floating-point FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_f32; /** * @brief Initialization function for the Q15 FIR lattice filter. * @param[in] S points to an instance of the Q15 FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] pState points to the state buffer. The array is of length numStages. */ void arm_fir_lattice_init_q15( arm_fir_lattice_instance_q15 * S, uint16_t numStages, q15_t * pCoeffs, q15_t * pState); /** * @brief Processing function for the Q15 FIR lattice filter. * @param[in] S points to an instance of the Q15 FIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_lattice_q15( const arm_fir_lattice_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR lattice filter. * @param[in] S points to an instance of the Q31 FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] pState points to the state buffer. The array is of length numStages. */ void arm_fir_lattice_init_q31( arm_fir_lattice_instance_q31 * S, uint16_t numStages, q31_t * pCoeffs, q31_t * pState); /** * @brief Processing function for the Q31 FIR lattice filter. * @param[in] S points to an instance of the Q31 FIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_fir_lattice_q31( const arm_fir_lattice_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR lattice filter. * @param[in] S points to an instance of the floating-point FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] pState points to the state buffer. The array is of length numStages. */ void arm_fir_lattice_init_f32( arm_fir_lattice_instance_f32 * S, uint16_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Processing function for the floating-point FIR lattice filter. * @param[in] S points to an instance of the floating-point FIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_fir_lattice_f32( const arm_fir_lattice_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Instance structure for the Q15 IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_q15; /** * @brief Instance structure for the Q31 IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_q31; /** * @brief Instance structure for the floating-point IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_f32; /** * @brief Processing function for the floating-point IIR lattice filter. * @param[in] S points to an instance of the floating-point IIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_f32( const arm_iir_lattice_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point IIR lattice filter. * @param[in] S points to an instance of the floating-point IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_init_f32( arm_iir_lattice_instance_f32 * S, uint16_t numStages, float32_t * pkCoeffs, float32_t * pvCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 IIR lattice filter. * @param[in] S points to an instance of the Q31 IIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_q31( const arm_iir_lattice_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 IIR lattice filter. * @param[in] S points to an instance of the Q31 IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_init_q31( arm_iir_lattice_instance_q31 * S, uint16_t numStages, q31_t * pkCoeffs, q31_t * pvCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q15 IIR lattice filter. * @param[in] S points to an instance of the Q15 IIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_q15( const arm_iir_lattice_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 IIR lattice filter. * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. * @param[in] pState points to state buffer. The array is of length numStages+blockSize. * @param[in] blockSize number of samples to process per call. */ void arm_iir_lattice_init_q15( arm_iir_lattice_instance_q15 * S, uint16_t numStages, q15_t * pkCoeffs, q15_t * pvCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Instance structure for the floating-point LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ float32_t mu; /**< step size that controls filter coefficient updates. */ } arm_lms_instance_f32; /** * @brief Processing function for floating-point LMS filter. * @param[in] S points to an instance of the floating-point LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_f32( const arm_lms_instance_f32 * S, float32_t * pSrc, float32_t * pRef, float32_t * pOut, float32_t * pErr, uint32_t blockSize); /** * @brief Initialization function for floating-point LMS filter. * @param[in] S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to the coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. */ void arm_lms_init_f32( arm_lms_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, float32_t mu, uint32_t blockSize); /** * @brief Instance structure for the Q15 LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q15_t mu; /**< step size that controls filter coefficient updates. */ uint32_t postShift; /**< bit shift applied to coefficients. */ } arm_lms_instance_q15; /** * @brief Initialization function for the Q15 LMS filter. * @param[in] S points to an instance of the Q15 LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to the coefficient buffer. * @param[in] pState points to the state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_init_q15( arm_lms_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, q15_t mu, uint32_t blockSize, uint32_t postShift); /** * @brief Processing function for Q15 LMS filter. * @param[in] S points to an instance of the Q15 LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_q15( const arm_lms_instance_q15 * S, q15_t * pSrc, q15_t * pRef, q15_t * pOut, q15_t * pErr, uint32_t blockSize); /** * @brief Instance structure for the Q31 LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q31_t mu; /**< step size that controls filter coefficient updates. */ uint32_t postShift; /**< bit shift applied to coefficients. */ } arm_lms_instance_q31; /** * @brief Processing function for Q31 LMS filter. * @param[in] S points to an instance of the Q15 LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_q31( const arm_lms_instance_q31 * S, q31_t * pSrc, q31_t * pRef, q31_t * pOut, q31_t * pErr, uint32_t blockSize); /** * @brief Initialization function for Q31 LMS filter. * @param[in] S points to an instance of the Q31 LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_init_q31( arm_lms_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, q31_t mu, uint32_t blockSize, uint32_t postShift); /** * @brief Instance structure for the floating-point normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ float32_t mu; /**< step size that control filter coefficient updates. */ float32_t energy; /**< saves previous frame energy. */ float32_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_f32; /** * @brief Processing function for floating-point normalized LMS filter. * @param[in] S points to an instance of the floating-point normalized LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_norm_f32( arm_lms_norm_instance_f32 * S, float32_t * pSrc, float32_t * pRef, float32_t * pOut, float32_t * pErr, uint32_t blockSize); /** * @brief Initialization function for floating-point normalized LMS filter. * @param[in] S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. */ void arm_lms_norm_init_f32( arm_lms_norm_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, float32_t mu, uint32_t blockSize); /** * @brief Instance structure for the Q31 normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q31_t mu; /**< step size that controls filter coefficient updates. */ uint8_t postShift; /**< bit shift applied to coefficients. */ q31_t *recipTable; /**< points to the reciprocal initial value table. */ q31_t energy; /**< saves previous frame energy. */ q31_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_q31; /** * @brief Processing function for Q31 normalized LMS filter. * @param[in] S points to an instance of the Q31 normalized LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_norm_q31( arm_lms_norm_instance_q31 * S, q31_t * pSrc, q31_t * pRef, q31_t * pOut, q31_t * pErr, uint32_t blockSize); /** * @brief Initialization function for Q31 normalized LMS filter. * @param[in] S points to an instance of the Q31 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_norm_init_q31( arm_lms_norm_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, q31_t mu, uint32_t blockSize, uint8_t postShift); /** * @brief Instance structure for the Q15 normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< Number of coefficients in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q15_t mu; /**< step size that controls filter coefficient updates. */ uint8_t postShift; /**< bit shift applied to coefficients. */ q15_t *recipTable; /**< Points to the reciprocal initial value table. */ q15_t energy; /**< saves previous frame energy. */ q15_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_q15; /** * @brief Processing function for Q15 normalized LMS filter. * @param[in] S points to an instance of the Q15 normalized LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_norm_q15( arm_lms_norm_instance_q15 * S, q15_t * pSrc, q15_t * pRef, q15_t * pOut, q15_t * pErr, uint32_t blockSize); /** * @brief Initialization function for Q15 normalized LMS filter. * @param[in] S points to an instance of the Q15 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_norm_init_q15( arm_lms_norm_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, q15_t mu, uint32_t blockSize, uint8_t postShift); /** * @brief Correlation of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_f32( float32_t * pSrcA, uint32_t srcALen, float32_t * pSrcB, uint32_t srcBLen, float32_t * pDst); /** * @brief Correlation of Q15 sequences * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. */ void arm_correlate_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, q15_t * pScratch); /** * @brief Correlation of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_fast_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. */ void arm_correlate_fast_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, q15_t * pScratch); /** * @brief Correlation of Q31 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_fast_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Correlation of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). */ void arm_correlate_opt_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Correlation of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst); /** * @brief Instance structure for the floating-point sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_f32; /** * @brief Instance structure for the Q31 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q31; /** * @brief Instance structure for the Q15 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q15; /** * @brief Instance structure for the Q7 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q7; /** * @brief Processing function for the floating-point sparse FIR filter. * @param[in] S points to an instance of the floating-point sparse FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_f32( arm_fir_sparse_instance_f32 * S, float32_t * pSrc, float32_t * pDst, float32_t * pScratchIn, uint32_t blockSize); /** * @brief Initialization function for the floating-point sparse FIR filter. * @param[in,out] S points to an instance of the floating-point sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] pCoeffs points to the array of filter coefficients. * @param[in] pState points to the state buffer. * @param[in] pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_f32( arm_fir_sparse_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q31 sparse FIR filter. * @param[in] S points to an instance of the Q31 sparse FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_q31( arm_fir_sparse_instance_q31 * S, q31_t * pSrc, q31_t * pDst, q31_t * pScratchIn, uint32_t blockSize); /** * @brief Initialization function for the Q31 sparse FIR filter. * @param[in,out] S points to an instance of the Q31 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] pCoeffs points to the array of filter coefficients. * @param[in] pState points to the state buffer. * @param[in] pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_q31( arm_fir_sparse_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q15 sparse FIR filter. * @param[in] S points to an instance of the Q15 sparse FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] pScratchOut points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_q15( arm_fir_sparse_instance_q15 * S, q15_t * pSrc, q15_t * pDst, q15_t * pScratchIn, q31_t * pScratchOut, uint32_t blockSize); /** * @brief Initialization function for the Q15 sparse FIR filter. * @param[in,out] S points to an instance of the Q15 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] pCoeffs points to the array of filter coefficients. * @param[in] pState points to the state buffer. * @param[in] pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_q15( arm_fir_sparse_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q7 sparse FIR filter. * @param[in] S points to an instance of the Q7 sparse FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] pScratchOut points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_q7( arm_fir_sparse_instance_q7 * S, q7_t * pSrc, q7_t * pDst, q7_t * pScratchIn, q31_t * pScratchOut, uint32_t blockSize); /** * @brief Initialization function for the Q7 sparse FIR filter. * @param[in,out] S points to an instance of the Q7 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] pCoeffs points to the array of filter coefficients. * @param[in] pState points to the state buffer. * @param[in] pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_q7( arm_fir_sparse_instance_q7 * S, uint16_t numTaps, q7_t * pCoeffs, q7_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Floating-point sin_cos function. * @param[in] theta input value in degrees * @param[out] pSinVal points to the processed sine output. * @param[out] pCosVal points to the processed cos output. */ void arm_sin_cos_f32( float32_t theta, float32_t * pSinVal, float32_t * pCosVal); /** * @brief Q31 sin_cos function. * @param[in] theta scaled input value in degrees * @param[out] pSinVal points to the processed sine output. * @param[out] pCosVal points to the processed cosine output. */ void arm_sin_cos_q31( q31_t theta, q31_t * pSinVal, q31_t * pCosVal); /** * @brief Floating-point complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_conj_f32( float32_t * pSrc, float32_t * pDst, uint32_t numSamples); /** * @brief Q31 complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_conj_q31( q31_t * pSrc, q31_t * pDst, uint32_t numSamples); /** * @brief Q15 complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_conj_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples); /** * @brief Floating-point complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_squared_f32( float32_t * pSrc, float32_t * pDst, uint32_t numSamples); /** * @brief Q31 complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_squared_q31( q31_t * pSrc, q31_t * pDst, uint32_t numSamples); /** * @brief Q15 complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_squared_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples); /** * @ingroup groupController */ /** * @defgroup PID PID Motor Control * * A Proportional Integral Derivative (PID) controller is a generic feedback control * loop mechanism widely used in industrial control systems. * A PID controller is the most commonly used type of feedback controller. * * This set of functions implements (PID) controllers * for Q15, Q31, and floating-point data types. The functions operate on a single sample * of data and each call to the function returns a single processed value. * S points to an instance of the PID control data structure. in * is the input sample value. The functions return the output value. * * \par Algorithm: * 
       *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
   *    A0 = Kp + Ki + Kd
   *    A1 = (-Kp ) - (2 * Kd )
   *    A2 = Kd
    * * \par * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant * * \par * \image html PID.gif "Proportional Integral Derivative Controller" * * \par * The PID controller calculates an "error" value as the difference between * the measured output and the reference input. * The controller attempts to minimize the error by adjusting the process control inputs. * The proportional value determines the reaction to the current error, * the integral value determines the reaction based on the sum of recent errors, * and the derivative value determines the reaction based on the rate at which the error has been changing. * * \par Instance Structure * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. * A separate instance structure must be defined for each PID Controller. * There are separate instance structure declarations for each of the 3 supported data types. * * \par Reset Functions * There is also an associated reset function for each data type which clears the state array. * * \par Initialization Functions * There is also an associated initialization function for each data type. * The initialization function performs the following operations: * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. * - Zeros out the values in the state buffer. * * \par * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. * * \par Fixed-Point Behavior * Care must be taken when using the fixed-point versions of the PID Controller functions. * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup PID * @{ */ /** * @brief Process function for the floating-point PID Control. * @param[in,out] S is an instance of the floating-point PID Control structure * @param[in] in input sample to process * @return out processed output sample. */ CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( arm_pid_instance_f32 * S, float32_t in) { float32_t out; /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ out = (S->A0 * in) + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @brief Process function for the Q31 PID Control. * @param[in,out] S points to an instance of the Q31 PID Control structure * @param[in] in input sample to process * @return out processed output sample. * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 64-bit accumulator. * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. * Thus, if the accumulator result overflows it wraps around rather than clip. * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. */ CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( arm_pid_instance_q31 * S, q31_t in) { q63_t acc; q31_t out; /* acc = A0 * x[n] */ acc = (q63_t) S->A0 * in; /* acc += A1 * x[n-1] */ acc += (q63_t) S->A1 * S->state[0]; /* acc += A2 * x[n-2] */ acc += (q63_t) S->A2 * S->state[1]; /* convert output to 1.31 format to add y[n-1] */ out = (q31_t) (acc >> 31u); /* out += y[n-1] */ out += S->state[2]; /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @brief Process function for the Q15 PID Control. * @param[in,out] S points to an instance of the Q15 PID Control structure * @param[in] in input sample to process * @return out processed output sample. * * Scaling and Overflow Behavior: * \par * The function is implemented using a 64-bit internal accumulator. * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. * Lastly, the accumulator is saturated to yield a result in 1.15 format. */ CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( arm_pid_instance_q15 * S, q15_t in) { q63_t acc; q15_t out; #if defined (ARM_MATH_DSP) __SIMD32_TYPE *vstate; /* Implementation of PID controller */ /* acc = A0 * x[n] */ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); /* acc += A1 * x[n-1] + A2 * x[n-2] */ vstate = __SIMD32_CONST(S->state); acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); #else /* acc = A0 * x[n] */ acc = ((q31_t) S->A0) * in; /* acc += A1 * x[n-1] + A2 * x[n-2] */ acc += (q31_t) S->A1 * S->state[0]; acc += (q31_t) S->A2 * S->state[1]; #endif /* acc += y[n-1] */ acc += (q31_t) S->state[2] << 15; /* saturate the output */ out = (q15_t) (__SSAT((acc >> 15), 16)); /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @} end of PID group */ /** * @brief Floating-point matrix inverse. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] dst points to the instance of the output floating-point matrix structure. * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ arm_status arm_mat_inverse_f32( const arm_matrix_instance_f32 * src, arm_matrix_instance_f32 * dst); /** * @brief Floating-point matrix inverse. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] dst points to the instance of the output floating-point matrix structure. * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ arm_status arm_mat_inverse_f64( const arm_matrix_instance_f64 * src, arm_matrix_instance_f64 * dst); /** * @ingroup groupController */ /** * @defgroup clarke Vector Clarke Transform * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents * in the two-phase orthogonal stator axis Ialpha and Ibeta. * When Ialpha is superposed with Ia as shown in the figure below * \image html clarke.gif Stator current space vector and its components in (a,b). * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta * can be calculated using only Ia and Ib. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html clarkeFormula.gif * where Ia and Ib are the instantaneous stator phases and * pIalpha and pIbeta are the two coordinates of time invariant vector. * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Clarke transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup clarke * @{ */ /** * * @brief Floating-point Clarke transform * @param[in] Ia input three-phase coordinate a * @param[in] Ib input three-phase coordinate b * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta */ CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( float32_t Ia, float32_t Ib, float32_t * pIalpha, float32_t * pIbeta) { /* Calculate pIalpha using the equation, pIalpha = Ia */ *pIalpha = Ia; /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); } /** * @brief Clarke transform for Q31 version * @param[in] Ia input three-phase coordinate a * @param[in] Ib input three-phase coordinate b * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition, hence there is no risk of overflow. */ CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( q31_t Ia, q31_t Ib, q31_t * pIalpha, q31_t * pIbeta) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ /* Calculating pIalpha from Ia by equation pIalpha = Ia */ *pIalpha = Ia; /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); /* pIbeta is calculated by adding the intermediate products */ *pIbeta = __QADD(product1, product2); } /** * @} end of clarke group */ /** * @brief Converts the elements of the Q7 vector to Q31 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_q7_to_q31( q7_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup inv_clarke Vector Inverse Clarke Transform * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html clarkeInvFormula.gif * where pIa and pIb are the instantaneous stator phases and * Ialpha and Ibeta are the two coordinates of time invariant vector. * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Clarke transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup inv_clarke * @{ */ /** * @brief Floating-point Inverse Clarke transform * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta * @param[out] pIa points to output three-phase coordinate a * @param[out] pIb points to output three-phase coordinate b */ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( float32_t Ialpha, float32_t Ibeta, float32_t * pIa, float32_t * pIb) { /* Calculating pIa from Ialpha by equation pIa = Ialpha */ *pIa = Ialpha; /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; } /** * @brief Inverse Clarke transform for Q31 version * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta * @param[out] pIa points to output three-phase coordinate a * @param[out] pIb points to output three-phase coordinate b * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the subtraction, hence there is no risk of overflow. */ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( q31_t Ialpha, q31_t Ibeta, q31_t * pIa, q31_t * pIb) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ /* Calculating pIa from Ialpha by equation pIa = Ialpha */ *pIa = Ialpha; /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); /* pIb is calculated by subtracting the products */ *pIb = __QSUB(product2, product1); } /** * @} end of inv_clarke group */ /** * @brief Converts the elements of the Q7 vector to Q15 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_q7_to_q15( q7_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup park Vector Park Transform * * Forward Park transform converts the input two-coordinate vector to flux and torque components. * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents * from the stationary to the moving reference frame and control the spatial relationship between * the stator vector current and rotor flux vector. * If we consider the d axis aligned with the rotor flux, the diagram below shows the * current vector and the relationship from the two reference frames: * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html parkFormula.gif * where Ialpha and Ibeta are the stator vector components, * pId and pIq are rotor vector components and cosVal and sinVal are the * cosine and sine values of theta (rotor flux position). * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Park transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup park * @{ */ /** * @brief Floating-point Park transform * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta * @param[out] pId points to output rotor reference frame d * @param[out] pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * * The function implements the forward Park transform. * */ CMSIS_INLINE __STATIC_INLINE void arm_park_f32( float32_t Ialpha, float32_t Ibeta, float32_t * pId, float32_t * pIq, float32_t sinVal, float32_t cosVal) { /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ *pId = Ialpha * cosVal + Ibeta * sinVal; /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ *pIq = -Ialpha * sinVal + Ibeta * cosVal; } /** * @brief Park transform for Q31 version * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta * @param[out] pId points to output rotor reference frame d * @param[out] pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition and subtraction, hence there is no risk of overflow. */ CMSIS_INLINE __STATIC_INLINE void arm_park_q31( q31_t Ialpha, q31_t Ibeta, q31_t * pId, q31_t * pIq, q31_t sinVal, q31_t cosVal) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ q31_t product3, product4; /* Temporary variables used to store intermediate results */ /* Intermediate product is calculated by (Ialpha * cosVal) */ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); /* Intermediate product is calculated by (Ibeta * sinVal) */ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); /* Intermediate product is calculated by (Ialpha * sinVal) */ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); /* Intermediate product is calculated by (Ibeta * cosVal) */ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); /* Calculate pId by adding the two intermediate products 1 and 2 */ *pId = __QADD(product1, product2); /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ *pIq = __QSUB(product4, product3); } /** * @} end of park group */ /** * @brief Converts the elements of the Q7 vector to floating-point vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q7_to_float( q7_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup inv_park Vector Inverse Park transform * Inverse Park transform converts the input flux and torque components to two-coordinate vector. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html parkInvFormula.gif * where pIalpha and pIbeta are the stator vector components, * Id and Iq are rotor vector components and cosVal and sinVal are the * cosine and sine values of theta (rotor flux position). * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Park transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup inv_park * @{ */ /** * @brief Floating-point Inverse Park transform * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta */ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( float32_t Id, float32_t Iq, float32_t * pIalpha, float32_t * pIbeta, float32_t sinVal, float32_t cosVal) { /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ *pIalpha = Id * cosVal - Iq * sinVal; /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ *pIbeta = Id * sinVal + Iq * cosVal; } /** * @brief Inverse Park transform for Q31 version * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition, hence there is no risk of overflow. */ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( q31_t Id, q31_t Iq, q31_t * pIalpha, q31_t * pIbeta, q31_t sinVal, q31_t cosVal) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ q31_t product3, product4; /* Temporary variables used to store intermediate results */ /* Intermediate product is calculated by (Id * cosVal) */ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); /* Intermediate product is calculated by (Iq * sinVal) */ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); /* Intermediate product is calculated by (Id * sinVal) */ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); /* Intermediate product is calculated by (Iq * cosVal) */ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); /* Calculate pIalpha by using the two intermediate products 1 and 2 */ *pIalpha = __QSUB(product1, product2); /* Calculate pIbeta by using the two intermediate products 3 and 4 */ *pIbeta = __QADD(product4, product3); } /** * @} end of Inverse park group */ /** * @brief Converts the elements of the Q31 vector to floating-point vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q31_to_float( q31_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @ingroup groupInterpolation */ /** * @defgroup LinearInterpolate Linear Interpolation * * Linear interpolation is a method of curve fitting using linear polynomials. * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line * * \par * \image html LinearInterp.gif "Linear interpolation" * * \par * A Linear Interpolate function calculates an output value(y), for the input(x) * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) * * \par Algorithm: * 
       *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
   *       where x0, x1 are nearest values of input x
   *             y0, y1 are nearest values to output y
   *
    * * \par * This set of functions implements Linear interpolation process * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single * sample of data and each call to the function returns a single processed value. * S points to an instance of the Linear Interpolate function data structure. * x is the input sample value. The functions returns the output value. * * \par * if x is outside of the table boundary, Linear interpolation returns first value of the table * if x is below input range and returns last value of table if x is above range. */ /** * @addtogroup LinearInterpolate * @{ */ /** * @brief Process function for the floating-point Linear Interpolation Function. * @param[in,out] S is an instance of the floating-point Linear Interpolation structure * @param[in] x input sample to process * @return y processed output sample. * */ CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( arm_linear_interp_instance_f32 * S, float32_t x) { float32_t y; float32_t x0, x1; /* Nearest input values */ float32_t y0, y1; /* Nearest output values */ float32_t xSpacing = S->xSpacing; /* spacing between input values */ int32_t i; /* Index variable */ float32_t *pYData = S->pYData; /* pointer to output table */ /* Calculation of index */ i = (int32_t) ((x - S->x1) / xSpacing); if (i < 0) { /* Iniatilize output for below specified range as least output value of table */ y = pYData[0]; } else if ((uint32_t)i >= S->nValues) { /* Iniatilize output for above specified range as last output value of table */ y = pYData[S->nValues - 1]; } else { /* Calculation of nearest input values */ x0 = S->x1 + i * xSpacing; x1 = S->x1 + (i + 1) * xSpacing; /* Read of nearest output values */ y0 = pYData[i]; y1 = pYData[i + 1]; /* Calculation of output */ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); } /* returns output value */ return (y); } /** * * @brief Process function for the Q31 Linear Interpolation Function. * @param[in] pYData pointer to Q31 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. * */ CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( q31_t * pYData, q31_t x, uint32_t nValues) { q31_t y; /* output */ q31_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ int32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ index = ((x & (q31_t)0xFFF00000) >> 20); if (index >= (int32_t)(nValues - 1)) { return (pYData[nValues - 1]); } else if (index < 0) { return (pYData[0]); } else { /* 20 bits for the fractional part */ /* shift left by 11 to keep fract in 1.31 format */ fract = (x & 0x000FFFFF) << 11; /* Read two nearest output values from the index in 1.31(q31) format */ y0 = pYData[index]; y1 = pYData[index + 1]; /* Calculation of y0 * (1-fract) and y is in 2.30 format */ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ y += ((q31_t) (((q63_t) y1 * fract) >> 32)); /* Convert y to 1.31 format */ return (y << 1u); } } /** * * @brief Process function for the Q15 Linear Interpolation Function. * @param[in] pYData pointer to Q15 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. * */ CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( q15_t * pYData, q31_t x, uint32_t nValues) { q63_t y; /* output */ q15_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ int32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ index = ((x & (int32_t)0xFFF00000) >> 20); if (index >= (int32_t)(nValues - 1)) { return (pYData[nValues - 1]); } else if (index < 0) { return (pYData[0]); } else { /* 20 bits for the fractional part */ /* fract is in 12.20 format */ fract = (x & 0x000FFFFF); /* Read two nearest output values from the index */ y0 = pYData[index]; y1 = pYData[index + 1]; /* Calculation of y0 * (1-fract) and y is in 13.35 format */ y = ((q63_t) y0 * (0xFFFFF - fract)); /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ y += ((q63_t) y1 * (fract)); /* convert y to 1.15 format */ return (q15_t) (y >> 20); } } /** * * @brief Process function for the Q7 Linear Interpolation Function. * @param[in] pYData pointer to Q7 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. */ CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( q7_t * pYData, q31_t x, uint32_t nValues) { q31_t y; /* output */ q7_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ uint32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ if (x < 0) { return (pYData[0]); } index = (x >> 20) & 0xfff; if (index >= (nValues - 1)) { return (pYData[nValues - 1]); } else { /* 20 bits for the fractional part */ /* fract is in 12.20 format */ fract = (x & 0x000FFFFF); /* Read two nearest output values from the index and are in 1.7(q7) format */ y0 = pYData[index]; y1 = pYData[index + 1]; /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ y = ((y0 * (0xFFFFF - fract))); /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ y += (y1 * fract); /* convert y to 1.7(q7) format */ return (q7_t) (y >> 20); } } /** * @} end of LinearInterpolate group */ /** * @brief Fast approximation to the trigonometric sine function for floating-point data. * @param[in] x input value in radians. * @return sin(x). */ float32_t arm_sin_f32( float32_t x); /** * @brief Fast approximation to the trigonometric sine function for Q31 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ q31_t arm_sin_q31( q31_t x); /** * @brief Fast approximation to the trigonometric sine function for Q15 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ q15_t arm_sin_q15( q15_t x); /** * @brief Fast approximation to the trigonometric cosine function for floating-point data. * @param[in] x input value in radians. * @return cos(x). */ float32_t arm_cos_f32( float32_t x); /** * @brief Fast approximation to the trigonometric cosine function for Q31 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ q31_t arm_cos_q31( q31_t x); /** * @brief Fast approximation to the trigonometric cosine function for Q15 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ q15_t arm_cos_q15( q15_t x); /** * @ingroup groupFastMath */ /** * @defgroup SQRT Square Root * * Computes the square root of a number. * There are separate functions for Q15, Q31, and floating-point data types. * The square root function is computed using the Newton-Raphson algorithm. * This is an iterative algorithm of the form: * 
       *      x1 = x0 - f(x0)/f'(x0)
   *
    * where x1 is the current estimate, * x0 is the previous estimate, and * f'(x0) is the derivative of f() evaluated at x0. * For the square root function, the algorithm reduces to: * 
       *     x0 = in/2                         [initial guess]
   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
   *
    */ /** * @addtogroup SQRT * @{ */ /** * @brief Floating-point square root function. * @param[in] in input value. * @param[out] pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( float32_t in, float32_t * pOut) { if (in >= 0.0f) { #if (__FPU_USED == 1) && defined ( __CC_ARM ) *pOut = __sqrtf(in); #elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) *pOut = __builtin_sqrtf(in); #elif (__FPU_USED == 1) && defined(__GNUC__) *pOut = __builtin_sqrtf(in); #elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); #else *pOut = sqrtf(in); #endif return (ARM_MATH_SUCCESS); } else { *pOut = 0.0f; return (ARM_MATH_ARGUMENT_ERROR); } } /** * @brief Q31 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. * @param[out] pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ arm_status arm_sqrt_q31( q31_t in, q31_t * pOut); /** * @brief Q15 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. * @param[out] pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ arm_status arm_sqrt_q15( q15_t in, q15_t * pOut); /** * @} end of SQRT group */ /** * @brief floating-point Circular write function. */ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( int32_t * circBuffer, int32_t L, uint16_t * writeOffset, int32_t bufferInc, const int32_t * src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0u; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while (i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if (wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = (uint16_t)wOffset; } /** * @brief floating-point Circular Read function. */ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( int32_t * circBuffer, int32_t L, int32_t * readOffset, int32_t bufferInc, int32_t * dst, int32_t * dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0u; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t) (dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while (i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if (dst == (int32_t *) dst_end) { dst = dst_base; } /* Circularly update rOffset. Watch out for positive and negative value */ rOffset += bufferInc; if (rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Q15 Circular write function. */ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( q15_t * circBuffer, int32_t L, uint16_t * writeOffset, int32_t bufferInc, const q15_t * src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0u; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while (i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if (wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = (uint16_t)wOffset; } /** * @brief Q15 Circular Read function. */ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( q15_t * circBuffer, int32_t L, int32_t * readOffset, int32_t bufferInc, q15_t * dst, q15_t * dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t) (dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while (i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if (dst == (q15_t *) dst_end) { dst = dst_base; } /* Circularly update wOffset. Watch out for positive and negative value */ rOffset += bufferInc; if (rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Q7 Circular write function. */ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( q7_t * circBuffer, int32_t L, uint16_t * writeOffset, int32_t bufferInc, const q7_t * src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0u; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while (i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if (wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = (uint16_t)wOffset; } /** * @brief Q7 Circular Read function. */ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( q7_t * circBuffer, int32_t L, int32_t * readOffset, int32_t bufferInc, q7_t * dst, q7_t * dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t) (dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while (i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if (dst == (q7_t *) dst_end) { dst = dst_base; } /* Circularly update rOffset. Watch out for positive and negative value */ rOffset += bufferInc; if (rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Sum of the squares of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_power_q31( q31_t * pSrc, uint32_t blockSize, q63_t * pResult); /** * @brief Sum of the squares of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_power_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Sum of the squares of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_power_q15( q15_t * pSrc, uint32_t blockSize, q63_t * pResult); /** * @brief Sum of the squares of the elements of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_power_q7( q7_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Mean value of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_mean_q7( q7_t * pSrc, uint32_t blockSize, q7_t * pResult); /** * @brief Mean value of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_mean_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Mean value of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_mean_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Mean value of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_mean_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Variance of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_var_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Variance of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_var_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Variance of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_var_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Root Mean Square of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_rms_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Root Mean Square of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_rms_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Root Mean Square of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_rms_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Standard deviation of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_std_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Standard deviation of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_std_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Standard deviation of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_std_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Floating-point complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_f32( float32_t * pSrc, float32_t * pDst, uint32_t numSamples); /** * @brief Q31 complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_q31( q31_t * pSrc, q31_t * pDst, uint32_t numSamples); /** * @brief Q15 complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples); /** * @brief Q15 complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ void arm_cmplx_dot_prod_q15( q15_t * pSrcA, q15_t * pSrcB, uint32_t numSamples, q31_t * realResult, q31_t * imagResult); /** * @brief Q31 complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ void arm_cmplx_dot_prod_q31( q31_t * pSrcA, q31_t * pSrcB, uint32_t numSamples, q63_t * realResult, q63_t * imagResult); /** * @brief Floating-point complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ void arm_cmplx_dot_prod_f32( float32_t * pSrcA, float32_t * pSrcB, uint32_t numSamples, float32_t * realResult, float32_t * imagResult); /** * @brief Q15 complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ void arm_cmplx_mult_real_q15( q15_t * pSrcCmplx, q15_t * pSrcReal, q15_t * pCmplxDst, uint32_t numSamples); /** * @brief Q31 complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ void arm_cmplx_mult_real_q31( q31_t * pSrcCmplx, q31_t * pSrcReal, q31_t * pCmplxDst, uint32_t numSamples); /** * @brief Floating-point complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ void arm_cmplx_mult_real_f32( float32_t * pSrcCmplx, float32_t * pSrcReal, float32_t * pCmplxDst, uint32_t numSamples); /** * @brief Minimum value of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] result is output pointer * @param[in] index is the array index of the minimum value in the input buffer. */ void arm_min_q7( q7_t * pSrc, uint32_t blockSize, q7_t * result, uint32_t * index); /** * @brief Minimum value of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[in] pIndex is the array index of the minimum value in the input buffer. */ void arm_min_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult, uint32_t * pIndex); /** * @brief Minimum value of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ void arm_min_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult, uint32_t * pIndex); /** * @brief Minimum value of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ void arm_min_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a Q7 vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ void arm_max_q7( q7_t * pSrc, uint32_t blockSize, q7_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a Q15 vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ void arm_max_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a Q31 vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ void arm_max_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a floating-point vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ void arm_max_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult, uint32_t * pIndex); /** * @brief Q15 complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_mult_cmplx_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t numSamples); /** * @brief Q31 complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_mult_cmplx_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t numSamples); /** * @brief Floating-point complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_mult_cmplx_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t numSamples); /** * @brief Converts the elements of the floating-point vector to Q31 vector. * @param[in] pSrc points to the floating-point input vector * @param[out] pDst points to the Q31 output vector * @param[in] blockSize length of the input vector */ void arm_float_to_q31( float32_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q15 vector. * @param[in] pSrc points to the floating-point input vector * @param[out] pDst points to the Q15 output vector * @param[in] blockSize length of the input vector */ void arm_float_to_q15( float32_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q7 vector. * @param[in] pSrc points to the floating-point input vector * @param[out] pDst points to the Q7 output vector * @param[in] blockSize length of the input vector */ void arm_float_to_q7( float32_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q31 vector to Q15 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q31_to_q15( q31_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q31 vector to Q7 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q31_to_q7( q31_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to floating-point vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q15_to_float( q15_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to Q31 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q15_to_q31( q15_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to Q7 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q15_to_q7( q15_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @ingroup groupInterpolation */ /** * @defgroup BilinearInterpolate Bilinear Interpolation * * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. * The underlying function f(x, y) is sampled on a regular grid and the interpolation process * determines values between the grid points. * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. * Bilinear interpolation is often used in image processing to rescale images. * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. * * Algorithm * \par * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. * For floating-point, the instance structure is defined as: * 
       *   typedef struct
   *   {
   *     uint16_t numRows;
   *     uint16_t numCols;
   *     float32_t *pData;
   * } arm_bilinear_interp_instance_f32;
   *
    * * \par * where numRows specifies the number of rows in the table; * numCols specifies the number of columns in the table; * and pData points to an array of size numRows*numCols values. * The data table pTable is organized in row order and the supplied data values fall on integer indexes. * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. * * \par * Let (x, y) specify the desired interpolation point. Then define: * 
       *     XF = floor(x)
   *     YF = floor(y)
   *
    * \par * The interpolated output point is computed as: * 
       *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
   *
    * Note that the coordinates (x, y) contain integer and fractional components. * The integer components specify which portion of the table to use while the * fractional components control the interpolation processor. * * \par * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. */ /** * @addtogroup BilinearInterpolate * @{ */ /** * * @brief Floating-point bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate. * @param[in] Y interpolation coordinate. * @return out interpolated value. */ CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( const arm_bilinear_interp_instance_f32 * S, float32_t X, float32_t Y) { float32_t out; float32_t f00, f01, f10, f11; float32_t *pData = S->pData; int32_t xIndex, yIndex, index; float32_t xdiff, ydiff; float32_t b1, b2, b3, b4; xIndex = (int32_t) X; yIndex = (int32_t) Y; /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) { return (0); } /* Calculation of index for two nearest points in X-direction */ index = (xIndex - 1) + (yIndex - 1) * S->numCols; /* Read two nearest points in X-direction */ f00 = pData[index]; f01 = pData[index + 1]; /* Calculation of index for two nearest points in Y-direction */ index = (xIndex - 1) + (yIndex) * S->numCols; /* Read two nearest points in Y-direction */ f10 = pData[index]; f11 = pData[index + 1]; /* Calculation of intermediate values */ b1 = f00; b2 = f01 - f00; b3 = f10 - f00; b4 = f00 - f01 - f10 + f11; /* Calculation of fractional part in X */ xdiff = X - xIndex; /* Calculation of fractional part in Y */ ydiff = Y - yIndex; /* Calculation of bi-linear interpolated output */ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; /* return to application */ return (out); } /** * * @brief Q31 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( arm_bilinear_interp_instance_q31 * S, q31_t X, q31_t Y) { q31_t out; /* Temporary output */ q31_t acc = 0; /* output */ q31_t xfract, yfract; /* X, Y fractional parts */ q31_t x1, x2, y1, y2; /* Nearest output values */ int32_t rI, cI; /* Row and column indices */ q31_t *pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & (q31_t)0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & (q31_t)0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } /* 20 bits for the fractional part */ /* shift left xfract by 11 to keep 1.31 format */ xfract = (X & 0x000FFFFF) << 11u; /* Read two nearest output values from the index */ x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; /* 20 bits for the fractional part */ /* shift left yfract by 11 to keep 1.31 format */ yfract = (Y & 0x000FFFFF) << 11u; /* Read two nearest output values from the index */ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); /* Convert acc to 1.31(q31) format */ return ((q31_t)(acc << 2)); } /** * @brief Q15 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( arm_bilinear_interp_instance_q15 * S, q31_t X, q31_t Y) { q63_t acc = 0; /* output */ q31_t out; /* Temporary output */ q15_t x1, x2, y1, y2; /* Nearest output values */ q31_t xfract, yfract; /* X, Y fractional parts */ int32_t rI, cI; /* Row and column indices */ q15_t *pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & (q31_t)0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & (q31_t)0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } /* 20 bits for the fractional part */ /* xfract should be in 12.20 format */ xfract = (X & 0x000FFFFF); /* Read two nearest output values from the index */ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; /* 20 bits for the fractional part */ /* yfract should be in 12.20 format */ yfract = (Y & 0x000FFFFF); /* Read two nearest output values from the index */ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); acc = ((q63_t) out * (0xFFFFF - yfract)); /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); acc += ((q63_t) out * (xfract)); /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); acc += ((q63_t) out * (yfract)); /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); acc += ((q63_t) out * (yfract)); /* acc is in 13.51 format and down shift acc by 36 times */ /* Convert out to 1.15 format */ return ((q15_t)(acc >> 36)); } /** * @brief Q7 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( arm_bilinear_interp_instance_q7 * S, q31_t X, q31_t Y) { q63_t acc = 0; /* output */ q31_t out; /* Temporary output */ q31_t xfract, yfract; /* X, Y fractional parts */ q7_t x1, x2, y1, y2; /* Nearest output values */ int32_t rI, cI; /* Row and column indices */ q7_t *pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & (q31_t)0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & (q31_t)0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } /* 20 bits for the fractional part */ /* xfract should be in 12.20 format */ xfract = (X & (q31_t)0x000FFFFF); /* Read two nearest output values from the index */ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; /* 20 bits for the fractional part */ /* yfract should be in 12.20 format */ yfract = (Y & (q31_t)0x000FFFFF); /* Read two nearest output values from the index */ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ out = ((x1 * (0xFFFFF - xfract))); acc = (((q63_t) out * (0xFFFFF - yfract))); /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ out = ((x2 * (0xFFFFF - yfract))); acc += (((q63_t) out * (xfract))); /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ out = ((y1 * (0xFFFFF - xfract))); acc += (((q63_t) out * (yfract))); /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ out = ((y2 * (yfract))); acc += (((q63_t) out * (xfract))); /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ return ((q7_t)(acc >> 40)); } /** * @} end of BilinearInterpolate group */ /* SMMLAR */ #define multAcc_32x32_keep32_R(a, x, y) \ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) /* SMMLSR */ #define multSub_32x32_keep32_R(a, x, y) \ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) /* SMMULR */ #define mult_32x32_keep32_R(a, x, y) \ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) /* SMMLA */ #define multAcc_32x32_keep32(a, x, y) \ a += (q31_t) (((q63_t) x * y) >> 32) /* SMMLS */ #define multSub_32x32_keep32(a, x, y) \ a -= (q31_t) (((q63_t) x * y) >> 32) /* SMMUL */ #define mult_32x32_keep32(a, x, y) \ a = (q31_t) (((q63_t) x * y ) >> 32) #if defined ( __CC_ARM ) /* Enter low optimization region - place directly above function definition */ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) #define LOW_OPTIMIZATION_ENTER \ _Pragma ("push") \ _Pragma ("O1") #else #define LOW_OPTIMIZATION_ENTER #endif /* Exit low optimization region - place directly after end of function definition */ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) #define LOW_OPTIMIZATION_EXIT \ _Pragma ("pop") #else #define LOW_OPTIMIZATION_EXIT #endif /* Enter low optimization region - place directly above function definition */ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER /* Exit low optimization region - place directly after end of function definition */ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined ( __GNUC__ ) #define LOW_OPTIMIZATION_ENTER \ __attribute__(( optimize("-O1") )) #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined ( __ICCARM__ ) /* Enter low optimization region - place directly above function definition */ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) #define LOW_OPTIMIZATION_ENTER \ _Pragma ("optimize=low") #else #define LOW_OPTIMIZATION_ENTER #endif /* Exit low optimization region - place directly after end of function definition */ #define LOW_OPTIMIZATION_EXIT /* Enter low optimization region - place directly above function definition */ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ _Pragma ("optimize=low") #else #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #endif /* Exit low optimization region - place directly after end of function definition */ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined ( __TI_ARM__ ) #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined ( __CSMC__ ) #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined ( __TASKING__ ) #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #endif #ifdef __cplusplus } #endif #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif #endif /* _ARM_MATH_H */ /** * * End of file. */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/cmsis_armcc.h ================================================ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler ARMCC (ARM compiler V5) header file * @version V5.0.1 * @date 03. February 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_ARMCC_H #define __CMSIS_ARMCC_H #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) #error "Please use ARM Compiler Toolchain V4.0.677 or later!" #endif /* CMSIS compiler control architecture macros */ #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) #define __ARM_ARCH_6M__ 1 #endif #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) #define __ARM_ARCH_7M__ 1 #endif #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) #define __ARM_ARCH_7EM__ 1 #endif /* __ARM_ARCH_8M_BASE__ not applicable */ /* __ARM_ARCH_8M_MAIN__ not applicable */ /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __declspec(noreturn) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __UNALIGNED_UINT32 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT __packed struct #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return(__regControl); } /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; } /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_INLINE uint32_t __get_IPSR(void) { register uint32_t __regIPSR __ASM("ipsr"); return(__regIPSR); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_INLINE uint32_t __get_APSR(void) { register uint32_t __regAPSR __ASM("apsr"); return(__regAPSR); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_INLINE uint32_t __get_xPSR(void) { register uint32_t __regXPSR __ASM("xpsr"); return(__regXPSR); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t __regProcessStackPointer __ASM("psp"); return(__regProcessStackPointer); } /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { register uint32_t __regProcessStackPointer __ASM("psp"); __regProcessStackPointer = topOfProcStack; } /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t __regMainStackPointer __ASM("msp"); return(__regMainStackPointer); } /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { register uint32_t __regMainStackPointer __ASM("msp"); __regMainStackPointer = topOfMainStack; } /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return(__regPriMask); } /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return(__regBasePri); } /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xFFU); } /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) { register uint32_t __regBasePriMax __ASM("basepri_max"); __regBasePriMax = (basePri & 0xFFU); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return(__regFaultMask); } /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); __regFaultMask = (faultMask & (uint32_t)1U); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_INLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) register uint32_t __regfpscr __ASM("fpscr"); return(__regfpscr); #else return(0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) register uint32_t __regfpscr __ASM("fpscr"); __regfpscr = (fpscr); #else (void)fpscr; #endif } #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() do {\ __schedule_barrier();\ __isb(0xF);\ __schedule_barrier();\ } while (0U) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() do {\ __schedule_barrier();\ __dsb(0xF);\ __schedule_barrier();\ } while (0U) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() do {\ __schedule_barrier();\ __dmb(0xF);\ __schedule_barrier();\ } while (0U) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in integer value. \param [in] value Value to reverse \return Reversed value */ #define __REV __rev /** \brief Reverse byte order (16 bit) \details Reverses the byte order in two unsigned short values. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr } #endif /** \brief Reverse byte order in signed short value \details Reverses the byte order in a signed short value with sign extension to integer. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr } #endif /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ #define __ROR __ror /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __breakpoint(value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) #define __RBIT __rbit #else __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ return(result); } #endif /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) #else #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) #else #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) #else #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXB(value, ptr) __strex(value, ptr) #else #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXH(value, ptr) __strex(value, ptr) #else #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXW(value, ptr) __strex(value, ptr) #else #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __clrex /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr } #endif /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRBT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRHT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRT(value, ptr) __strt(value, ptr) #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) #define __SADD8 __sadd8 #define __QADD8 __qadd8 #define __SHADD8 __shadd8 #define __UADD8 __uadd8 #define __UQADD8 __uqadd8 #define __UHADD8 __uhadd8 #define __SSUB8 __ssub8 #define __QSUB8 __qsub8 #define __SHSUB8 __shsub8 #define __USUB8 __usub8 #define __UQSUB8 __uqsub8 #define __UHSUB8 __uhsub8 #define __SADD16 __sadd16 #define __QADD16 __qadd16 #define __SHADD16 __shadd16 #define __UADD16 __uadd16 #define __UQADD16 __uqadd16 #define __UHADD16 __uhadd16 #define __SSUB16 __ssub16 #define __QSUB16 __qsub16 #define __SHSUB16 __shsub16 #define __USUB16 __usub16 #define __UQSUB16 __uqsub16 #define __UHSUB16 __uhsub16 #define __SASX __sasx #define __QASX __qasx #define __SHASX __shasx #define __UASX __uasx #define __UQASX __uqasx #define __UHASX __uhasx #define __SSAX __ssax #define __QSAX __qsax #define __SHSAX __shsax #define __USAX __usax #define __UQSAX __uqsax #define __UHSAX __uhsax #define __USAD8 __usad8 #define __USADA8 __usada8 #define __SSAT16 __ssat16 #define __USAT16 __usat16 #define __UXTB16 __uxtb16 #define __UXTAB16 __uxtab16 #define __SXTB16 __sxtb16 #define __SXTAB16 __sxtab16 #define __SMUAD __smuad #define __SMUADX __smuadx #define __SMLAD __smlad #define __SMLADX __smladx #define __SMLALD __smlald #define __SMLALDX __smlaldx #define __SMUSD __smusd #define __SMUSDX __smusdx #define __SMLSD __smlsd #define __SMLSDX __smlsdx #define __SMLSLD __smlsld #define __SMLSLDX __smlsldx #define __SEL __sel #define __QADD __qadd #define __QSUB __qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ ((int64_t)(ARG3) << 32U) ) >> 32U)) #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCC_H */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/cmsis_armclang.h ================================================ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file * @version V5.0.1 * @date 02. February 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H #ifndef __ARM_COMPAT_H #include /* Compatibility header for ARM Compiler 5 intrinsics */ #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __UNALIGNED_UINT32 #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); see arm_compat.h */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); see arm_compat.h */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /* see arm_compat.h */ /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /* see arm_compat.h */ /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) { register uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return(result); } #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Get Process Stack Pointer Limit (non-secure) \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer Limit \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); } #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); } #endif /** \brief Get Main Stack Pointer Limit \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) { register uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return(result); } #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Get Main Stack Pointer Limit (non-secure) \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer Limit \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); } #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Set Main Stack Pointer Limit (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ /* #define __get_FPSCR __builtin_arm_get_fpscr */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) uint32_t result; __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); return(result); #else return(0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ /* #define __set_FPSCR __builtin_arm_set_fpscr */ __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory"); #else (void)fpscr; #endif } #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF); /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF); /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF); /** \brief Reverse byte order (32 bit) \details Reverses the byte order in integer value. \param [in] value Value to reverse \return Reversed value */ #define __REV __builtin_bswap32 /** \brief Reverse byte order (16 bit) \details Reverses the byte order in two unsigned short values. \param [in] value Value to reverse \return Reversed value */ #define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ #if 0 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } #endif /** \brief Reverse byte order in signed short value \details Reverses the byte order in a signed short value with sign extension to integer. \param [in] value Value to reverse \return Reversed value */ /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) { int32_t result; __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); #else int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); } /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __builtin_clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t)__builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t)__builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t)__builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t)__builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __builtin_arm_ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDAEXB (uint8_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDAEXH (uint16_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDAEX (uint32_t)__builtin_arm_ldaex /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXB (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXH (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEX (uint32_t)__builtin_arm_stlex #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #if 0 #define __PKHBT(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #define __PKHTB(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ else \ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #endif #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCLANG_H */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/cmsis_compiler.h ================================================ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler generic header file * @version V5.0.1 * @date 30. January 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H #include /* * ARM Compiler 4/5 */ #if defined ( __CC_ARM ) #include "cmsis_armcc.h" /* * ARM Compiler 6 (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #include "cmsis_armclang.h" /* * GNU Compiler */ #elif defined ( __GNUC__ ) #include "cmsis_gcc.h" /* * IAR Compiler */ #elif defined ( __ICCARM__ ) #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #include #ifndef __NO_RETURN #define __NO_RETURN __noreturn #endif #ifndef __USED #define __USED __root #endif #ifndef __WEAK #define __WEAK __weak #endif #ifndef __UNALIGNED_UINT32 __packed struct T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) #endif #ifndef __PACKED #define __PACKED __packed #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT __packed struct #endif /* * TI ARM Compiler */ #elif defined ( __TI_ARM__ ) #include #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __UNALIGNED_UINT32 struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed)) #endif /* * TASKING Compiler */ #elif defined ( __TASKING__ ) /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __UNALIGNED_UINT32 struct __packed__ T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __align(x) #endif #ifndef __PACKED #define __PACKED __packed__ #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __packed__ #endif /* * COSMIC Compiler */ #elif defined ( __CSMC__ ) #include #ifndef __ASM #define __ASM _asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __NO_RETURN // NO RETURN is automatically detected hence no warning here #define __NO_RETURN #endif #ifndef __USED #warning No compiler specific solution for __USED. __USED is ignored. #define __USED #endif #ifndef __WEAK #define __WEAK __weak #endif #ifndef __UNALIGNED_UINT32 @packed struct T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __ALIGNED #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #define __ALIGNED(x) #endif #ifndef __PACKED #define __PACKED @packed #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT @packed struct #endif #else #error Unknown compiler. #endif /** * @brief definition to read/write two 16 bit values. */ #if defined ( __CC_ARM ) #define __SIMD32_TYPE int32_t __packed #define CMSIS_UNUSED __attribute__((unused)) #define CMSIS_INLINE __attribute__((always_inline)) #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED __attribute__((unused)) #define CMSIS_INLINE __attribute__((always_inline)) #elif defined ( __GNUC__ ) #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED __attribute__((unused)) #define CMSIS_INLINE __attribute__((always_inline)) #elif defined ( __ICCARM__ ) #define __SIMD32_TYPE int32_t __packed #define CMSIS_UNUSED #define CMSIS_INLINE #elif defined ( __TI_ARM__ ) #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED __attribute__((unused)) #define CMSIS_INLINE #elif defined ( __CSMC__ ) #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED #define CMSIS_INLINE #elif defined ( __TASKING__ ) #define __SIMD32_TYPE __unaligned int32_t #define CMSIS_UNUSED #define CMSIS_INLINE #else #error Unknown compiler #endif #endif /* __CMSIS_COMPILER_H */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/cmsis_gcc.h ================================================ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file * @version V5.0.1 * @date 02. February 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_GCC_H #define __CMSIS_GCC_H /* ignore some GCC warnings */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __UNALIGNED_UINT32 #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) { register uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return(result); } #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Get Process Stack Pointer Limit (non-secure) \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer Limit \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); } #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); } #endif /** \brief Get Main Stack Pointer Limit \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) { register uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return(result); } #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Get Main Stack Pointer Limit (non-secure) \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) { register uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer Limit \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); } #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Set Main Stack Pointer Limit (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) uint32_t result; __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); return(result); #else return(0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); #else (void)fpscr; #endif } #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ //__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) //{ // __ASM volatile ("nop"); //} #define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ //__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) //{ // __ASM volatile ("wfi"); //} #define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ //__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) //{ // __ASM volatile ("wfe"); //} #define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ //__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) //{ // __ASM volatile ("sev"); //} #define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __attribute__((always_inline)) __STATIC_INLINE void __ISB(void) { __ASM volatile ("isb 0xF":::"memory"); } /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __attribute__((always_inline)) __STATIC_INLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); } /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __attribute__((always_inline)) __STATIC_INLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); } /** \brief Reverse byte order (32 bit) \details Reverses the byte order in integer value. \param [in] value Value to reverse \return Reversed value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); #else uint32_t result; __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); #endif } /** \brief Reverse byte order (16 bit) \details Reverses the byte order in two unsigned short values. \param [in] value Value to reverse \return Reversed value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief Reverse byte order in signed short value \details Reverses the byte order in a signed short value with sign extension to integer. \param [in] value Value to reverse \return Reversed value */ __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (short)__builtin_bswap16(value); #else int32_t result; __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); #endif } /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); #else int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); } /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __builtin_clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); return(result); } /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) { __ASM volatile ("clrex" ::: "memory"); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1,ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined(__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #if 0 #define __PKHBT(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #define __PKHTB(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ else \ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #endif #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #pragma GCC diagnostic pop #endif /* __CMSIS_GCC_H */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/core_armv8mbl.h ================================================ /**************************************************************************//** * @file core_armv8mbl.h * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File * @version V5.0.1 * @date 25. November 2016 ******************************************************************************/ /* * Copyright (c) 2009-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_ARMV8MBL_H_GENERIC #define __CORE_ARMV8MBL_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
    Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
    Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMv8MBL @{ */ /* CMSIS cmGrebe definitions */ #define __ARMv8MBL_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ #define __ARMv8MBL_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_M ( 2U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MBL_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV8MBL_H_DEPENDANT #define __CORE_ARMV8MBL_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv8MBL_REV #define __ARMv8MBL_REV 0x0000U #warning "__ARMv8MBL_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #ifndef __ETM_PRESENT #define __ETM_PRESENT 0U #warning "__ETM_PRESENT not defined in device header file; using default!" #endif #ifndef __MTB_PRESENT #define __MTB_PRESENT 0U #warning "__MTB_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv8MBL */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ uint32_t RESERVED0[6U]; __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #endif } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifndef CMSIS_NVIC_VIRTUAL /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #endif /* CMSIS_NVIC_VIRTUAL */ #ifndef CMSIS_VECTAB_VIRTUAL #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MBL_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/core_armv8mml.h ================================================ /**************************************************************************//** * @file core_armv8mml.h * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File * @version V5.0.2 * @date 07. December 2016 ******************************************************************************/ /* * Copyright (c) 2009-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_ARMV8MML_H_GENERIC #define __CORE_ARMV8MML_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
    Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
    Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMv8MML @{ */ /* CMSIS ARMv8MML definitions */ #define __ARMv8MML_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ #define __ARMv8MML_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_M (81U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MML_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV8MML_H_DEPENDANT #define __CORE_ARMV8MML_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv8MML_REV #define __ARMv8MML_REV 0x0000U #warning "__ARMv8MML_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv8MML */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifndef CMSIS_NVIC_VIRTUAL #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #endif /* CMSIS_NVIC_VIRTUAL */ #ifndef CMSIS_VECTAB_VIRTUAL #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MML_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/core_cm0.h ================================================ /**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @version V5.0.1 * @date 25. November 2016 ******************************************************************************/ /* * Copyright (c) 2009-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0_H_GENERIC #define __CORE_CM0_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
    Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
    Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M0 @{ */ /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0_REV #define __CM0_REV 0x0000U #warning "__CM0_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M0 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0; __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifndef CMSIS_NVIC_VIRTUAL /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #endif /* CMSIS_NVIC_VIRTUAL */ #ifndef CMSIS_VECTAB_VIRTUAL #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. Address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)0x0U; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)0x0U; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/core_cm0plus.h ================================================ /**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File * @version V5.0.1 * @date 25. November 2016 ******************************************************************************/ /* * Copyright (c) 2009-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0PLUS_H_GENERIC #define __CORE_CM0PLUS_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
    Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
    Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex-M0+ @{ */ /* CMSIS CM0+ definitions */ #define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0PLUS_H_DEPENDANT #define __CORE_CM0PLUS_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0PLUS_REV #define __CM0PLUS_REV 0x0000U #warning "__CM0PLUS_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex-M0+ */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0+ header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifndef CMSIS_NVIC_VIRTUAL /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #endif /* CMSIS_NVIC_VIRTUAL */ #ifndef CMSIS_VECTAB_VIRTUAL #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/core_cm23.h ================================================ /**************************************************************************//** * @file core_cm23.h * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File * @version V5.0.1 * @date 25. November 2016 ******************************************************************************/ /* * Copyright (c) 2009-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM23_H_GENERIC #define __CORE_CM23_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
    Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
    Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M23 @{ */ /* CMSIS cmGrebe definitions */ #define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ #define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_M (23U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM23_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM23_H_DEPENDANT #define __CORE_CM23_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM23_REV #define __CM23_REV 0x0000U #warning "__CM23_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #ifndef __ETM_PRESENT #define __ETM_PRESENT 0U #warning "__ETM_PRESENT not defined in device header file; using default!" #endif #ifndef __MTB_PRESENT #define __MTB_PRESENT 0U #warning "__MTB_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M23 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ uint32_t RESERVED0[6U]; __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #endif } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifndef CMSIS_NVIC_VIRTUAL /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #endif /* CMSIS_NVIC_VIRTUAL */ #ifndef CMSIS_VECTAB_VIRTUAL #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM23_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/core_cm3.h ================================================ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V5.0.1 * @date 30. January 2017 ******************************************************************************/ /* * Copyright (c) 2009-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
    Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
    Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M3 @{ */ /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_M (3U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM3_REV #define __CM3_REV 0x0200U #warning "__CM3_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M3 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #else #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else uint32_t RESERVED1[1U]; #endif } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ CMSIS_INLINE __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ CMSIS_INLINE __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ CMSIS_INLINE __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ CMSIS_INLINE __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ CMSIS_INLINE __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ CMSIS_INLINE __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ CMSIS_INLINE __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ CMSIS_INLINE __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ CMSIS_INLINE __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ CMSIS_INLINE __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ CMSIS_INLINE __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ CMSIS_INLINE __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ CMSIS_INLINE __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ CMSIS_INLINE __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ CMSIS_INLINE __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ CMSIS_INLINE __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ CMSIS_INLINE __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ CMSIS_INLINE __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ CMSIS_INLINE __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ CMSIS_INLINE __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ CMSIS_INLINE __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/core_cm33.h ================================================ /**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File * @version V5.0.2 * @date 07. December 2016 ******************************************************************************/ /* * Copyright (c) 2009-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM33_H_GENERIC #define __CORE_CM33_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
    Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
    Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M33 @{ */ /* CMSIS CM33 definitions */ #define __CM33_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ #define __CM33_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ __CM33_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_M (33U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM33_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM33_H_DEPENDANT #define __CORE_CM33_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM33_REV #define __CM33_REV 0x0000U #warning "__CM33_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M33 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifndef CMSIS_NVIC_VIRTUAL #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #endif /* CMSIS_NVIC_VIRTUAL */ #ifndef CMSIS_VECTAB_VIRTUAL #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM33_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/core_cm4.h ================================================ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @version V5.0.1 * @date 30. January 2017 ******************************************************************************/ /* * Copyright (c) 2009-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM4_H_GENERIC #define __CORE_CM4_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
    Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
    Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M4 @{ */ /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_M (4U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM4_H_DEPENDANT #define __CORE_CM4_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM4_REV #define __CM4_REV 0x0000U #warning "__CM4_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M4 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/core_cm7.h ================================================ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File * @version V5.0.1 * @date 25. November 2016 ******************************************************************************/ /* * Copyright (c) 2009-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM7_H_GENERIC #define __CORE_CM7_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
    Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
    Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M7 @{ */ /* CMSIS CM7 definitions */ #define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ #define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_M (7U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM7_H_DEPENDANT #define __CORE_CM7_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM7_REV #define __CM7_REV 0x0000U #warning "__CM7_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __ICACHE_PRESENT #define __ICACHE_PRESENT 0U #warning "__ICACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DCACHE_PRESENT #define __DCACHE_PRESENT 0U #warning "__DCACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DTCM_PRESENT #define __DTCM_PRESENT 0U #warning "__DTCM_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M7 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[1U]; __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED3[93U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED3[981U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 Definitions */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifndef CMSIS_NVIC_VIRTUAL #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #endif /* CMSIS_NVIC_VIRTUAL */ #ifndef CMSIS_VECTAB_VIRTUAL #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = SCB->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## Cache functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_CacheFunctions Cache Functions \brief Functions that configure Instruction and Data cache. @{ */ /* Cache Size ID Register Macros */ #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) /** \brief Enable I-Cache \details Turns on I-Cache */ __STATIC_INLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable I-Cache \details Turns off I-Cache */ __STATIC_INLINE void SCB_DisableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); #endif } /** \brief Invalidate I-Cache \details Invalidates I-Cache */ __STATIC_INLINE void SCB_InvalidateICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; __DSB(); __ISB(); #endif } /** \brief Enable D-Cache \details Turns on D-Cache */ __STATIC_INLINE void SCB_EnableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable D-Cache \details Turns off D-Cache */ __STATIC_INLINE void SCB_DisableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) register uint32_t ccsidr; register uint32_t sets; register uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Invalidate D-Cache \details Invalidates D-Cache */ __STATIC_INLINE void SCB_InvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean D-Cache \details Cleans D-Cache */ __STATIC_INLINE void SCB_CleanDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean & Invalidate D-Cache \details Cleans and Invalidates D-Cache */ __STATIC_INLINE void SCB_CleanInvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief D-Cache Invalidate by address \details Invalidates D-Cache for the given address \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t)addr; int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCIMVAC = op_addr; op_addr += (uint32_t)linesize; op_size -= linesize; } __DSB(); __ISB(); #endif } /** \brief D-Cache Clean by address \details Cleans D-Cache for the given address \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t) addr; int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCCMVAC = op_addr; op_addr += (uint32_t)linesize; op_size -= linesize; } __DSB(); __ISB(); #endif } /** \brief D-Cache Clean and Invalidate by address \details Cleans and invalidates D_Cache for the given address \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t) addr; int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCCIMVAC = op_addr; op_addr += (uint32_t)linesize; op_size -= linesize; } __DSB(); __ISB(); #endif } /*@} end of CMSIS_Core_CacheFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/core_sc000.h ================================================ /**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File * @version V5.0.1 * @date 25. November 2016 ******************************************************************************/ /* * Copyright (c) 2009-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC000_H_GENERIC #define __CORE_SC000_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
    Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
    Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC000 @{ */ /* CMSIS SC000 definitions */ #define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ #define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_SC (000U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC000_H_DEPENDANT #define __CORE_SC000_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC000_REV #define __SC000_REV 0x0000U #warning "__SC000_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC000 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ uint32_t RESERVED1[154U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2U]; __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the SC000 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifndef CMSIS_NVIC_VIRTUAL /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #endif /* CMSIS_NVIC_VIRTUAL */ #ifndef CMSIS_VECTAB_VIRTUAL #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/core_sc300.h ================================================ /**************************************************************************//** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File * @version V5.0.1 * @date 25. November 2016 ******************************************************************************/ /* * Copyright (c) 2009-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC300_H_GENERIC #define __CORE_SC300_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
    Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
    Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC3000 @{ */ /* CMSIS SC300 definitions */ #define __SC300_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ #define __SC300_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_SC (300U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC300_H_DEPENDANT #define __CORE_SC300_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC300_REV #define __SC300_REV 0x0000U #warning "__SC300_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC300 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED1[129U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ uint32_t RESERVED1[1U]; } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifndef CMSIS_NVIC_VIRTUAL #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #endif /* CMSIS_NVIC_VIRTUAL */ #ifndef CMSIS_VECTAB_VIRTUAL #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Huawei_LiteOS/arch/arm/common/cmsis/tz_context.h ================================================ /* * Copyright (c) 2015-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * ---------------------------------------------------------------------------- * * $Date: 21. September 2016 * $Revision: V1.0 * * Project: TrustZone for ARMv8-M * Title: Context Management for ARMv8-M TrustZone * * Version 1.0 * Initial Release *---------------------------------------------------------------------------*/ #ifndef TZ_CONTEXT_H #define TZ_CONTEXT_H #include #ifndef TZ_MODULEID_T #define TZ_MODULEID_T /// \details Data type that identifies secure software modules called by a process. typedef uint32_t TZ_ModuleId_t; #endif /// \details TZ Memory ID identifies an allocated memory slot. typedef uint32_t TZ_MemoryId_t; /// Initialize secure context memory system /// \return execution status (1: success, 0: error) uint32_t TZ_InitContextSystem_S (void); /// Allocate context memory for calling secure software modules in TrustZone /// \param[in] module identifies software modules called from non-secure mode /// \return value != 0 id TrustZone memory slot identifier /// \return value 0 no memory available or internal error TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); /// Load secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); /// Store secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); #endif // TZ_CONTEXT_H ================================================ FILE: Huawei_LiteOS/arch/msp430/include/los_hw.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**@defgroup los_hw hardware *@ingroup kernel */ #ifndef _LOS_HW_H #define _LOS_HW_H #include "los_base.h" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ /** * @ingroup los_hw * The initialization value of stack space. */ #define EMPTY_STACK 0xCACA /** * @ingroup los_hw * Check task schedule. */ #define LOS_CHECK_SCHEDULE ((!g_usLosTaskLock)) /** * @ingroup los_hw * Define the type of a task context control block. */ typedef struct tagTskContext { #if (__CODE_MODEL__ != __CODE_MODEL_LARGE__) && \ (__DATA_MODEL__ != __DATA_MODEL_LARGE__) unsigned int r4; unsigned int r5; unsigned int r6; unsigned int r7; unsigned int r8; unsigned int r9; unsigned int r10; unsigned int r11; unsigned int r12; unsigned int r13; unsigned int r14; unsigned int r15; #else unsigned long r4; unsigned long r5; unsigned long r6; unsigned long r7; unsigned long r8; unsigned long r9; unsigned long r10; unsigned long r11; unsigned long r12; unsigned long r13; unsigned long r14; unsigned long r15; #endif unsigned int sr; unsigned int pc; } TSK_CONTEXT_S; /** * @ingroup los_hw * @brief: Task stack initialization. * * @par Description: * This API is used to initialize the task stack. * * @attention: *
    • None.
    * * @param uwTaskID [IN] Type#UINT32: TaskID. * @param uwStackSize [IN] Type#UINT32: Total size of the stack. * @param pTopStack [IN] Type#VOID *: Top of task's stack. * * @retval: pstContext Type#TSK_CONTEXT_S *. * @par Dependency: *
    • los_hw.h: the header file that contains the API declaration.
    * @see None. * @since Huawei LiteOS V100R001C00 */ extern VOID * osTskStackInit(UINT32 uwTaskID, UINT32 uwStackSize, VOID *pTopStack); /** * @ingroup los_hw * @brief: Task scheduling Function. * * @par Description: * This API is used to scheduling task. * * @attention: *
    • None.
    * * @param None. * * @retval: None. * @par Dependency: *
    • los_hw.h: the header file that contains the API declaration.
    * @see None. * @since Huawei LiteOS V100R001C00 */ extern VOID osSchedule(VOID); /** * @ingroup los_hw * @brief: Function to determine whether task scheduling is required. * * @par Description: * This API is used to Judge and entry task scheduling. * * @attention: *
    • None.
    * * @param None. * * @retval: None. * @par Dependency: *
    • los_hw.h: the header file that contains the API declaration.
    * @see None. * @since Huawei LiteOS V100R001C00 */ extern VOID LOS_Schedule(VOID); LITE_OS_SEC_TEXT_MINOR VOID osTaskExit(VOID); /** * @ingroup los_hw * @brief: Enter CPU low power mode. * * @par Description: * This API is used to make CPU enter to power-save mode. * * @attention: *
    • None.
    * * @param None. * * @retval: None. * @par Dependency: *
    • los_hw.h: the header file that contains the API declaration.
    * @see None. * @since Huawei LiteOS V100R001C00 */ extern VOID osEnterSleep(VOID); #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ #endif /* _LOS_HW_H */ ================================================ FILE: Huawei_LiteOS/arch/msp430/include/los_hwi.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**@defgroup los_hwi Hardware interrupt *@ingroup kernel */ #ifndef _LOS_HWI_H #define _LOS_HWI_H #include "los_errno.h" #include "stdint.h" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ /** * @ingroup los_hwi * Define the type of a hardware interrupt handling function. */ struct hwi_int_handle { void (* pfn) (uintptr_t); uintptr_t arg; }; /** * @ingroup los_hwi * Count of interrupts. */ extern unsigned char g_int_cnt; /** * @ingroup los_hwi * An interrupt is active. */ #define OS_INT_ACTIVE (g_int_cnt > 0) /** * @ingroup los_hwi * An interrupt is inactive. */ #define OS_INT_INACTIVE (!(OS_INT_ACTIVE)) /** * @ingroup los_hwi * Hardware interrupt error code: Invalid interrupt number. * * Value: 0x02000900 * * Solution: Ensure that the interrupt number is valid. The value range of the interrupt vector is [0, RESET_VECTOR], the defination for vector numbers can be found at the SOC header file, for example: msp430f5438a.h. */ #define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00) /** * @ingroup los_hwi * Hardware interrupt error code: Null hardware interrupt handling function. * * Value: 0x02000901 * * Solution: Pass in a valid non-null hardware interrupt handling function. */ #define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01) /** * @ingroup los_hwi * Hardware interrupt error code: The interrupt has already been created. * * Value: 0x02000904 * * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created. */ #define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04) /** * @ingroup los_hwi * @brief Create a hardware interrupt. * * @par Description: * This API is used to configure a hardware interrupt and register a hardware interrupt handling function. * * @attention *
      *
    • Hardware interrupt vector number value range: [0, RESET_VECTOR]. The usable vector numbers can be found at the SOC header files, for example: msp430f5438a.h.
      • *
    • Before executing an interrupt on a platform, refer to the chip manual of the platform.
      • *
    * * @param vector [IN] Type#int: hardware interrupt vector number. For example: WDT_VECTOR, RESET_VECTOR. * @param prio [IN] Type#int: hardware interrupt priority. Not used. * @param mode [IN] Type#int: hardware interrupt mode. Not used. * @param pfn [IN] Type#void (*) (uintptr_t): interrupt handler used when a hardware interrupt is triggered. * @param arg [IN] Type#uintptr_t: input parameter of the interrupt handler used when a hardware interrupt is triggered. * * @retval #OS_ERRNO_HWI_NUM_INVALID 0x02000900: Invalid interrupt number. * @retval #OS_ERRNO_HWI_PROC_FUNC_NULL 0x02000901: Null hardware interrupt handling function. * @retval #OS_ERRNO_HWI_ALREADY_CREATED 0x02000904: The interrupt handler being created has already been created. * @retval #LOS_OK 0x00000000: The interrupt is successfully created. * @par Dependency: *
    • los_hwi.h: the header file that contains the API declaration.
    * @see None. * @since Huawei LiteOS V100R001C00 */ extern UINT32 LOS_HwiCreate (int irq,int prio, int mode, void (*pfn) (uintptr_t), uintptr_t arg); /** *@ingroup los_hwi *@brief Enable all interrupts. * *@par Description: *
      *
    • This API is used to enable all interrupts.
      • *
    *@attention *
      *
    • None.
      • *
    * *@param None. * *@retval original interrupt mask status. *@par Dependency: *
    • los_hwi.h: the header file that contains the API declaration.
    *@see LOS_IntRestore *@since Huawei LiteOS V100R001C00 */ extern uintptr_t LOS_IntUnLock (void); /** *@ingroup los_hwi *@brief Disable all interrupts. * *@par Description: *
      *
    • This API is used to disable all interrupts.
      • *
    *@attention *
      *
    • None.
      • *
    * *@param None. * *@retval original interrupt mask status. *@par Dependency: *
    • los_hwi.h: the header file that contains the API declaration.
    *@see LOS_IntRestore *@since Huawei LiteOS V100R001C00 */ extern uintptr_t LOS_IntLock (void); /** *@ingroup los_hwi *@brief Restore interrupts. * *@par Description: *
      *
    • This API is used to restore the interrupt mask status.
      • *
    *@attention *
      *
    • This API can be called only after all interrupts are disabled, and the input parameter value should be the value returned by calling the all interrupt disabling API.
      • *
    * *@param mask [IN] new interrupt mask. * *@retval None. *@par Dependency: *
    • los_hwi.h: the header file that contains the API declaration.
    *@see LOS_IntLock *@since Huawei LiteOS V100R001C00 */ extern void LOS_IntRestore (uintptr_t mask); /** * @ingroup los_hwi * @brief Delete hardware interrupt. * * @par Description: * This API is used to delete hardware interrupt vector handler. * * @attention *
      *
    • Hardware interrupt vector value range: [0, RESET_VECTOR].
      • *
    • RESET_VECTOR specifies the maximum number of interrupts that can be created.
      • *
    • Before executing an interrupt on a platform, refer to the chip manual of the platform.
      • *
    * * @param vector [IN] Type#int: hardware interrupt vector number. * * @retval #OS_ERRNO_HWI_NUM_INVALID 0x02000900: Invalid interrupt number. * @retval #LOS_OK 0x00000000: The interrupt is successfully delete. * @par Dependency: *
    • los_hwi.h: the header file that contains the API declaration.
    * @see None. * @since Huawei LiteOS V100R001C00 */ extern UINT32 LOS_HwiDelete (int vector); #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ #endif /* _LOS_HWI_H */ ================================================ FILE: Huawei_LiteOS/arch/msp430/src/ccsmacros.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _CCSMACROS_H #define _CCSMACROS_H #if __LARGE_DATA_MODEL__ == 1 #define PTR_SIZE 4 #define PCMP CMPX.A #define PMOV MOVA #define PSUB SUBX.A #else #define PTR_SIZE 2 #define PCMP CMP.W #define PMOV MOV.W #define PSUB SUB.W #endif #if __LARGE_CODE_MODEL__ == 1 #define FRET RETA #define FCALL CALLA #else #define FRET RET #define FCALL CALL #endif #if (__LARGE_DATA_MODEL__ == 1) || (__LARGE_CODE_MODEL__ == 1) #define REG_SIZE 4 #define XMOV MOVA #define XPUSH PUSH.A #define XPUSHM PUSHM.A #define XPOP POP.A #define XPOPM POPM.A #else #define REG_SIZE 2 #define XMOV MOV.W #define XPUSH PUSH.W #define XPUSHM PUSHM.W #define XPOP POP.W #define XPOPM POPM.W #endif #endif ================================================ FILE: Huawei_LiteOS/arch/msp430/src/los_dispatch_ccs.asm ================================================ ;/*---------------------------------------------------------------------------- ; * Copyright (c) <2013-2018>, ; * All rights reserved. ; * Redistribution and use in source and binary forms, with or without modification, ; * are permitted provided that the following conditions are met: ; * 1. Redistributions of source code must retain the above copyright notice, this list of ; * conditions and the following disclaimer. ; * 2. Redistributions in binary form must reproduce the above copyright notice, this list ; * of conditions and the following disclaimer in the documentation and/or other materials ; * provided with the distribution. ; * 3. Neither the name of the copyright holder nor the names of its contributors may be used ; * to endorse or promote products derived from this software without specific prior written ; * permission. ; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ; * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; *---------------------------------------------------------------------------*/ ;/*---------------------------------------------------------------------------- ; * Notice of Export Control Law ; * =============================================== ; * Huawei LiteOS may be subject to applicable export control laws and regulations, which might ; * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. ; * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such ; * applicable export control laws and regulations. ; *---------------------------------------------------------------------------*/ .cdecls C, LIST, "msp430.h" ; Include device header file .cdecls C, LIST, "ccsmacros.h" ; Include macros used ccs header file .data .global _los_heap_start .global _los_heap_end .asg 256, LOSCFG_MSP430_IRQ_SIZE .align 4 _los_heap_start: .ulong __HEAP_START _los_heap_end: .ulong __STACK_END - LOSCFG_MSP430_IRQ_SIZE .text .global LOS_IntLock .global LOS_IntUnLock .global LOS_IntRestore .global LOS_StartToRun .global osSchedule .ref g_bTaskScheduled .ref g_stLosTask .ref g_int_cnt .ref osTaskSwitchCheck .ref g_usLosTaskLock .ref osHwiDispatch .retain .retainrefs .asg 0x10, TASK_STATUS_RUNNING ;------------------------------------------------------------------------------- ; irq vectors ;------------------------------------------------------------------------------- .asg 0, irq .loop .if irq < 10 .sect ".int0:irq:" .else .sect ".int:irq:" .endif .short irq_stub:irq: .break ($symcmp (""".int:irq:""", SYSNMI_VECTOR) = 0) .eval irq + 1, irq .endloop ;------------------------------------------------------------------------------- ; irq entry stubs ;------------------------------------------------------------------------------- .sect ".text:_isr" .asg irq + 1, irqs .asg 0, irq irq_stubs: .loop irqs irq_stub:irq: FCALL #irq_handler .eval irq + 1, irq .endloop .unasg irq .unasg irqs irq_handler: ; ; now the stack: ; ; +-------------------------+----+----+ ; | irq_stubs + irq * 4 + 4 | SR | PC | ; +-------------------------+----+----+ ; XPUSH r14 XPUSH r13 XPUSH r12 XMOV (3 * REG_SIZE)(sp), r12 XMOV r15, (3 * REG_SIZE)(sp) ; ; now the stack: ; ; +-----+-----+-----+-----+----+----+ ; | R12 | R13 | R14 | R15 | SR | PC | ; +-----+-----+-----+-----+----+----+ ; ; now r12 = irq_stubs + irq * 4 + 4, ; ; ((r12 - (irq_stubs + 4)) / 4) is the irq number ; ((r12 - (irq_stubs + 4)) / 2) is the vector number ; INC.B &g_int_cnt CMP.B #1, &g_int_cnt JNE already_on_irq_stack XMOV sp, &__STACK_END - REG_SIZE XMOV #__STACK_END - REG_SIZE, sp already_on_irq_stack: SUB.W #irq_stubs + 4, r12 ; irq_stubs at CODE16 RRA.w r12 RRA.w r12 FCALL #osHwiDispatch ; interrupt can be enabld in osHwiDispatch DINT NOP ; required by architecture DEC.B &g_int_cnt CMP.B #0, &g_int_cnt JNE _rfi XMOV 0(sp), sp CMP.W #0, &g_usLosTaskLock JNE _rfi PCMP &g_stLosTask + PTR_SIZE, &g_stLosTask JEQ _rfi ; need schedule, save context XPUSHM #8, r11 ; save r4-r11 _switch_new: PMOV &g_stLosTask, r12 PMOV sp, 0(r12) BIC.W #TASK_STATUS_RUNNING, PTR_SIZE(r12) FCALL #osTaskSwitchCheck _load_new: PMOV &g_stLosTask + PTR_SIZE, r12 PMOV r12, &g_stLosTask PMOV 0(r12), sp BIS.W #TASK_STATUS_RUNNING, PTR_SIZE(r12) XPOPM #8, r11 _rfi: XPOPM #4, r15 RETI LOS_StartToRun: DINT NOP ; required by architecture MOV.W #1, &g_bTaskScheduled JMP _load_new osSchedule: MOV.W sr, r12 DINT NOP ; required by architecture PCMP &g_stLosTask + PTR_SIZE, &g_stLosTask JEQ _ret .if __LARGE_CODE_MODEL__ = 1 ; ; fake ra for calla as the same with interrupt: ; ; +---------+---------+ +----+----+ ; | ra00:15 | ra16:19 | -> | sr | ra | ; +---------+---------+ +----+----+ ; ; ra16:19 in sr16:19 ; MOV.W 2(sp), r13 RLA r13 RLA r13 RLA r13 RLA r13 SWPB r13 BIS.W r13, r12 MOV.W 0(sp), 2(sp) MOV.W r12, 0(sp) .else PUSH.W r12 .endif PSUB #4 * REG_SIZE, sp ; reserve space for r12-r15, needless save XPUSHM #8, r11 ; save r4-r11 JMP _switch_new _ret: NOP ; required by architecture MOV.W r12, sr NOP ; required by architecture FRET LOS_IntLock: MOV.W sr, r12 AND.W #GIE, r12 DINT NOP ; required by architecture FRET LOS_IntUnLock: MOV.W sr, r12 AND.W #GIE, r12 NOP ; required by architecture EINT NOP FRET LOS_IntRestore: AND.W #GIE, r12 NOP ; required by architecture BIS.W r12, sr NOP ; required by architecture FRET ;------------------------------------------------------------------------------- ; System HEAP ;------------------------------------------------------------------------------- .sect .sysmem .align 8 __HEAP_START: ;------------------------------------------------------------------------------- ; Stack Pointer definition ;------------------------------------------------------------------------------- .global __STACK_END .sect .stack .end ================================================ FILE: Huawei_LiteOS/arch/msp430/src/los_dispatch_iar.s43 ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "msp430.h" ; #define controlled include file #include "macros.m43" #include "target_config.h" EXTERN osHwiDispatch EXTERN g_int_cnt EXTERN g_stLosTask EXTERN g_bTaskScheduled EXTERN osTaskSwitchCheck EXTERN g_usLosTaskLock PUBLIC LOS_IntLock PUBLIC LOS_IntUnLock PUBLIC LOS_IntRestore PUBLIC LOS_StartToRun PUBLIC osSchedule PUBLIC _los_heap_start PUBLIC _los_heap_size #define TASK_STATUS_RUNNING 0x10 #if __DATA_MODEL__ == __DATA_MODEL_LARGE__ #define PTR_SIZE 4 #define PCMP CMPX.A /* pointer compare */ #define PMOV MOVA /* pointer movation */ #define PSUB SUBX.A #else #define PTR_SIZE 2 #define PCMP CMP.W /* pointer compare */ #define PMOV MOV.W /* pointer movation */ #define PSUB SUB.W #endif /* forward declarations of segments */ RSEG CSTACK:DATA:NOROOT RSEG DATA20_HEAP:DATA:NOROOT NAME los_dispatch ; module name /* * create interrupt vector table for all interrupts */ RSEG INTVEC:CONST:CODE:ROOT(1) ORG 0 stub SET irq_stubs REPT RESET_VECTOR / 2 - 1 DC16 stub stub SET stub + 4 ENDR ; entry (reset) at 0xfffe set by __program_start #ifndef LOSCFG_MSP430_IRQ_SIZE #define LOSCFG_MSP430_IRQ_SIZE 256 #endif RSEG DATA16_C _los_heap_start DC32 (sfe (DATA20_HEAP) + 7) & ~7 _los_heap_size DC32 ((sfe (CSTACK)) & ~7) - ((sfe (DATA20_HEAP) + 7) & ~7) - LOSCFG_MSP430_IRQ_SIZE RSEG CODE16 ; place program in 'CODE16' segment irq_stubs: REPT RESET_VECTOR / 2 - 1 #if REG_SIZE == 4 CALLA #irq_handler #else CALL #irq_handler #endif ENDR irq_handler: /* * now the stack: * * +-------------------------+----+----+ * | irq_stubs + irq * 4 + 4 | SR | PC | * +-------------------------+----+----+ */ XPUSH r14 XPUSH r13 XPUSH r12 XMOV (3 * REG_SIZE)(sp), r12 XMOV r15, (3 * REG_SIZE)(sp) /* * now the stack: * * +-----+-----+-----+-----+----+----+ * | R12 | R13 | R14 | R15 | SR | PC | * +-----+-----+-----+-----+----+----+ * * now r12 = irq_stubs + irq * 4 + 4, * * ((r12 - (irq_stubs + 4)) / 4) is the irq number * ((r12 - (irq_stubs + 4)) / 2) is the vector number */ INC.B &g_int_cnt CMP.B #1, &g_int_cnt JNE already_on_irq_stack XMOV sp, &sfe (CSTACK) - REG_SIZE XMOV #sfe (CSTACK) - REG_SIZE, sp already_on_irq_stack: SUB.W #irq_stubs + 4, r12 ; irq_stubs at CODE16 RRA.W r12 FCALL #osHwiDispatch ; interrupt can be enabld in osHwiDispatch DINT NOP ; required by architecture DEC.B &g_int_cnt CMP.B #0, &g_int_cnt JNE _rfi XMOV 0(sp), sp CMP.W #0, &g_usLosTaskLock JNE _rfi PCMP &g_stLosTask + PTR_SIZE, &g_stLosTask JEQ _rfi ; need schedule, save context XPUSHM #8, r11 ; save r4-r11 _switch_new: PMOV &g_stLosTask, r12 PMOV sp, 0(r12) BIC.W #TASK_STATUS_RUNNING, PTR_SIZE(r12) FCALL #osTaskSwitchCheck _load_new: PMOV &g_stLosTask + PTR_SIZE, r12 PMOV r12, &g_stLosTask PMOV 0(r12), sp BIS.W #TASK_STATUS_RUNNING, PTR_SIZE(r12) XPOPM #8, r11 _rfi: XPOPM #4, r15 RETI LOS_StartToRun: DINT NOP ; required by architecture MOV.W #1, &g_bTaskScheduled JMP _load_new osSchedule: MOV.W sr, r12 DINT NOP ; required by architecture PCMP &g_stLosTask + PTR_SIZE, &g_stLosTask JEQ _ret #if __CODE_MODEL__ == __CODE_MODEL_LARGE__ /* * fake ra for calla as the same with interrupt: * * +---------+---------+ +----+----+ * | ra00:15 | ra16:19 | -> | sr | ra | * +---------+---------+ +----+----+ * * ra16:19 in sr16:19 */ MOV.W 2(sp), r13 RLA r13 RLA r13 RLA r13 RLA r13 SWPB r13 BIS.W r13, r12 MOV.W 0(sp), 2(sp) MOV.W r12, 0(sp) #else PUSH.W r12 #endif PSUB #4 * REG_SIZE, sp ; reserve space for r12-r15, needless save XPUSHM #8, r11 ; save r4-r11 JMP _switch_new _ret: NOP ; required by architecture MOV.W r12, sr NOP ; required by architecture FRET LOS_IntLock: MOV.W sr, r12 AND.W #GIE, r12 DINT NOP ; required by architecture FRET LOS_IntUnLock: MOV.W sr, r12 AND.W #GIE, r12 NOP ; required by architecture EINT NOP FRET LOS_IntRestore: AND.W #GIE, r12 NOP ; required by architecture BIS.W r12, sr NOP ; required by architecture FRET END ================================================ FILE: Huawei_LiteOS/arch/msp430/src/los_hw.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "los_base.h" #include "los_hwi.h" #include "los_task.ph" #include "los_memory.h" #include "los_membox.h" #include "los_priqueue.ph" void LOS_Schedule (void) { uintptr_t flags; BOOL need_schedule = FALSE; flags = LOS_IntLock (); g_stLosTask.pstNewTask = LOS_DL_LIST_ENTRY (osPriqueueTop (), LOS_TASK_CB, stPendList);/*lint !e413*/ need_schedule = (g_stLosTask.pstRunTask != g_stLosTask.pstNewTask) && (!g_usLosTaskLock) && (!OS_INT_ACTIVE); (void) LOS_IntRestore (flags); if (need_schedule) { osSchedule (); } } static void osTaskExit (void) { LOS_IntUnLock(); while (1) { LOS_TaskDelay (0xffffffff); }; } /***************************************************************************** Function : osTskStackInit Description : task stack initialization Input : tid -- task id stack_size -- task stack size stack -- task stack Output : None Return : OS_SUCCESS on success or error code on failure *****************************************************************************/ void * osTskStackInit (UINT32 tid, UINT32 stack_size, VOID * stack) { TSK_CONTEXT_S * context; #if (LOSCFG_STATIC_TASK == NO) UINT32 i; /*initialize the task stack, write magic num to stack top*/ for (i = 0; i < (stack_size / sizeof (UINT32)); i++) { ((UINT32 *) stack) [i] = OS_TASK_STACK_INIT; } *((UINT32 *) stack) = OS_TASK_MAGIC_WORD; #endif /* fake return address in stack */ #if __CODE_MODEL__ == __CODE_MODEL_LARGE__ stack = (void *) (((char *) stack + stack_size) - 4); #else stack = (void *) (((char *) stack + stack_size) - 2); #endif *((void (**) (void)) stack) = osTaskExit; /* make extra 4 bytes after the context to fake return address in stack */ context = (TSK_CONTEXT_S *) (((char *) stack) - sizeof (TSK_CONTEXT_S)); /*initialize the task context*/ context->pc = ((((unsigned long) &osTaskEntry)) & 0xffff); #if __CODE_MODEL__ == __CODE_MODEL_LARGE__ context->sr = ((((unsigned long) &osTaskEntry) >> 4) & 0xf000) | GIE; #else context->sr = GIE; #endif context->r12 = tid; context->r13 = 0; return (void *) context; } #if (LOSCFG_KERNEL_RUNSTOP == YES) void osEnterSleep (void) { //_BIS_SR (LPM0_bits + GIE); /* Enter LPM0 w/ interrupt */ } #endif ================================================ FILE: Huawei_LiteOS/arch/msp430/src/los_hw_tick.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include #include #include extern void osTickHandler (void); UINT32 osTickStart (void) { UINT32 ret = LOS_NOK; if (LOSCFG_BASE_CORE_TICK_PER_SECOND > 100) { return ret; } ret = LOS_HwiCreate (TIMER1_A0_VECTOR, 0, 0, (void (*) (uintptr_t)) osTickHandler, 0); if (ret != LOS_OK) { return ret; } TA1CCTL0 = CCIE; /* capture/compare interrupt enable */ TA1CTL = TASSEL_1 + ID_0 + MC_1 + TACLR; /* select 32k clock, input divider = /1, up-mode and clear */ TA1CCR0 = 32768 / LOSCFG_BASE_CORE_TICK_PER_SECOND; return LOS_OK; } ================================================ FILE: Huawei_LiteOS/arch/msp430/src/los_hwi.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "los_hwi.h" #include "los_memory.h" #include "string.h" unsigned char g_int_cnt = 0; #if defined (__ICC430__) static struct hwi_int_handle s_irq_table [RESET_VECTOR >> 1] = {0}; #elif defined (__TI_COMPILER_VERSION__) static struct hwi_int_handle s_irq_table [RESET_VECTOR] = {0}; #endif /***************************************************************************** Function : osHwiInit Description : initialization of the hardware interrupt Input : None Output : None Return : None *****************************************************************************/ void osHwiInit (void) { return; } void osHwiDispatch (int vector) { int irq; if ((vector < 0) || (vector >= RESET_VECTOR)) { PRINT_ERR ("unexpected irq\n"); return; } #if defined (__ICC430__) irq = vector >> 1; #elif defined (__TI_COMPILER_VERSION__) irq = vector; #endif if (s_irq_table [irq].pfn == NULL) { PRINT_ERR ("unexpected irq\n"); return; } s_irq_table [irq].pfn (s_irq_table [irq].arg); } /***************************************************************************** Function : LOS_HwiCreate Description : create hardware interrupt Input : vector --- vector number prio --- not used pfn --- vector handler arg --- param of the vector handler Output : None Return : OS_SUCCESS on success or error code on failure *****************************************************************************/ UINT32 LOS_HwiCreate (int vector, int prio, int mode, void (* pfn) (uintptr_t), uintptr_t arg) { int irq; (void) mode; /* not used for now */ if (pfn == NULL) { return OS_ERRNO_HWI_PROC_FUNC_NULL; } if ((vector < 0) || (vector >= RESET_VECTOR)) { return OS_ERRNO_HWI_NUM_INVALID; } #if defined (__ICC430__) irq = vector >> 1; #elif defined (__TI_COMPILER_VERSION__) irq = vector; #endif if (s_irq_table [irq].pfn != NULL) { return OS_ERRNO_HWI_ALREADY_CREATED; } s_irq_table [irq].pfn = pfn; s_irq_table [irq].arg = arg; return 0; } /***************************************************************************** Function : LOS_HwiDelete Description : delete hardware interrupt Input : vector --- hwi vector to delete Output : None Return : OS_SUCCESS on success or error code on failure *****************************************************************************/ UINT32 LOS_HwiDelete (int vector) { if ((vector < 0) || (vector >= RESET_VECTOR)) { return OS_ERRNO_HWI_NUM_INVALID; } #if defined (__ICC430__) s_irq_table [vector >> 1].pfn = NULL; #elif defined (__TI_COMPILER_VERSION__) s_irq_table [vector].pfn = NULL; #endif return LOS_OK; } ================================================ FILE: Huawei_LiteOS/build/Makefile ================================================ #blank makefile now ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/agent_list.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _ATINY_LIST_H #define _ATINY_LIST_H #define ATINY_INLINE static inline #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ /** *@ingroup atiny_list *Structure of a node in a doubly linked list. */ typedef struct atiny_dl_list { struct atiny_dl_list *prev; /**< Current node's pointer to the previous node*/ struct atiny_dl_list *next; /**< Current node's pointer to the next node*/ } atiny_dl_list; ATINY_INLINE void atiny_list_init(atiny_dl_list *list) { list->next = list; list->prev = list; } #define ATINY_DL_LIST_FIRST(object) ((object)->next) ATINY_INLINE void atiny_list_add(atiny_dl_list *list, atiny_dl_list *node) { node->next = list->next; node->prev = list; list->next->prev = node; list->next = node; } ATINY_INLINE void atiny_list_insert_tail(atiny_dl_list *list, atiny_dl_list *node) { atiny_list_add(list->prev, node); } ATINY_INLINE atiny_dl_list * atiny_list_get_head(atiny_dl_list *header) { return header->next; } ATINY_INLINE void atiny_list_delete(atiny_dl_list *node) { node->next->prev = node->prev; node->prev->next = node->next; node->next = (atiny_dl_list *)NULL; node->prev = (atiny_dl_list *)NULL; } ATINY_INLINE int atiny_list_empty(atiny_dl_list *node) { return (node->next == node); } #define ATINY_OFFSET_OF_FIELD(type, field) ((UINT32)&(((type *)0)->field)) #define ATINY_OFF_SET_OF(type, member) ((long)&((type *)0)->member) /*lint -e(413) */ #define ATINY_FIELD_TO_STRUCT(field_addr, type, member) \ ((type *)((char *)(field_addr) - ATINY_OFF_SET_OF(type, member))) #define ATINY_DL_LIST_ENTRY(item, type, member)\ ((type *)((char *)item - ATINY_OFF_SET_OF(type, member)))\ #define ATINY_DL_LIST_FOR_EACH_ENTRY(item, list, type, member)\ for (item = ATINY_DL_LIST_ENTRY((list)->next, type, member);\ &item->member != (list);\ item = ATINY_DL_LIST_ENTRY(item->member.next, type, member)) #define ATINY_DL_LIST_FOR_EACH_ENTRY_SAFE(item, next, list, type, member)\ for (item = ATINY_DL_LIST_ENTRY((list)->next, type, member),\ next = ATINY_DL_LIST_ENTRY(item->member->next, type, member);\ &item->member != (list);\ item = next, item = ATINY_DL_LIST_ENTRY(item->member.next, type, member)) ATINY_INLINE void ATINY_ListDel(atiny_dl_list *pstPrevNode, atiny_dl_list *pstNextNode) { pstNextNode->prev = pstPrevNode; pstPrevNode->next = pstNextNode; } ATINY_INLINE void ATINY_ListDelInit(atiny_dl_list *pstList) { ATINY_ListDel(pstList->prev, pstList->next); atiny_list_init(pstList); } #define ATINY_DL_LIST_FOR_EACH(item, list)\ for ((item) = (list)->next;\ (item) != (list);\ (item) = (item)->next) #define ATINY_DL_LIST_FOR_EACH_SAFE(item, next, list)\ for (item = (list)->next, next = item->next; item != (list);\ item = next, next = item->next) #define ATINY_DL_LIST_HEAD(list)\ atiny_dl_list list = { &(list), &(list) } #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ #endif /* _ATINY_LIST_H */ ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/agenttiny.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "internals.h" #include "atiny_lwm2m/agenttiny.h" #include "atiny_context.h" #include "connection.h" #include "log/atiny_log.h" #include "atiny_rpt.h" #include "osdepends/atiny_osdep.h" #ifdef CONFIG_FEATURE_FOTA #include "atiny_fota_manager.h" #endif int g_reboot = 0; void observe_handle_ack(lwm2m_transaction_t *transacP, void *message); static int atiny_check_bootstrap_init_param(atiny_param_t *atiny_params); static handle_data_t g_atiny_handle; /* * modify date: 2018-06-20 * description: in order to check the params for the bootstrap, expecialy for the mode and the ip/port * return: * success: ATINY_OK * fail: ATINY_ARG_INVALID * */ static int atiny_check_bootstrap_init_param(atiny_param_t *atiny_params) { if(NULL == atiny_params) { return ATINY_ARG_INVALID; } if(BOOTSTRAP_FACTORY == atiny_params->server_params.bootstrap_mode) { if((NULL == atiny_params->security_params[0].server_ip) || (NULL == atiny_params->security_params[0].server_port)) { LOG("[bootstrap_tag]: BOOTSTRAP_FACTORY mode's params is wrong, should have iot server ip/port"); return ATINY_ARG_INVALID; } } else if(BOOTSTRAP_CLIENT_INITIATED == atiny_params->server_params.bootstrap_mode) { if((NULL == atiny_params->security_params[1].server_ip) || (NULL == atiny_params->security_params[1].server_port)) { LOG("[bootstrap_tag]: BOOTSTRAP_CLIENT_INITIATED mode's params is wrong, should have bootstrap server ip/port"); return ATINY_ARG_INVALID; } } else if(BOOTSTRAP_SEQUENCE == atiny_params->server_params.bootstrap_mode) { return ATINY_OK; } else { //it is ok? if the mode value is not 0,1,2, we all set it to 2 ? LOG("[bootstrap_tag]: BOOTSTRAP only have three mode, should been :0,1,2"); return ATINY_ARG_INVALID; } return ATINY_OK; } #ifdef LWM2M_BOOTSTRAP static int atiny_check_psk_init_param(atiny_param_t *atiny_params) { int i = 0; int psk_id_len = 0; int psk_len = 0; const int PSK_ID_LIMIT_LEN = 128; const int PSK_LIMIT_LEN = 64; int total_element = 0; if(NULL == atiny_params) { return ATINY_ARG_INVALID; } //security_params have 2 element, we have 2 pair psk. total_element = (sizeof(atiny_params->security_params)) / (sizeof(atiny_params->security_params[0])); for(i = 0; i < total_element; i++) { //if there are null, we could run not in security mode if((atiny_params->security_params[i].psk_Id != NULL) && (atiny_params->security_params[i].psk != NULL)) { psk_id_len = strlen(atiny_params->security_params[i].psk_Id); psk_len = strlen(atiny_params->security_params[i].psk); //the limit of the len, please read RFC4279 or OMA-TS-LightweightM2M E.1.1 if((psk_id_len > PSK_ID_LIMIT_LEN) || (psk_len > PSK_LIMIT_LEN)) { LOG("[bootstrap_tag]: psk_Id len over 128 or psk len over 64"); return ATINY_ARG_INVALID; } } } return ATINY_OK; } #endif int atiny_init(atiny_param_t *atiny_params, void **phandle) { int result; result = atiny_init_rpt(); if (result != ATINY_OK) { ATINY_LOG(LOG_FATAL, "atiny_init_rpt fail,ret=%d", result); return result; } if (NULL == atiny_params || NULL == phandle) { ATINY_LOG(LOG_FATAL, "Invalid args"); return ATINY_ARG_INVALID; } if(ATINY_OK != atiny_check_bootstrap_init_param(atiny_params)) { LOG("[bootstrap_tag]: BOOTSTRAP's params are wrong"); return ATINY_ARG_INVALID; } #ifdef LWM2M_BOOTSTRAP if(ATINY_OK != atiny_check_psk_init_param(atiny_params)) { LOG("[bootstrap_tag]: psk params are wrong"); } #endif memset((void *)&g_atiny_handle, 0, sizeof(handle_data_t)); g_atiny_handle.quit_sem = atiny_mutex_create(); if (NULL == g_atiny_handle.quit_sem) { ATINY_LOG(LOG_FATAL, "atiny_mutex_create fail"); return ATINY_RESOURCE_NOT_ENOUGH; } atiny_mutex_lock(g_atiny_handle.quit_sem); g_atiny_handle.atiny_params = *atiny_params; *phandle = &g_atiny_handle; #ifdef CONFIG_FEATURE_FOTA return atiny_fota_manager_set_storage_device(atiny_fota_manager_get_instance()); #else return ATINY_OK; #endif } /* * add date: 2018-06-05 * description: get bootstrap info from atiny_params which from user, set bs_sequence_state and bs_server_uri for lwm2m_context. * * return: none * param: * in: atiny_params * out: lwm2m_context */ void atiny_set_bootstrap_sequence_state(atiny_param_t *atiny_params, lwm2m_context_t *lwm2m_context) { (void)lwm2m_initBootStrap(lwm2m_context, atiny_params->server_params.bootstrap_mode); } /* * modify info: * date: 2018-05-30 * reason: modify for bootstrap mode, origin code only support FACTORY mode. */ int atiny_init_objects(atiny_param_t *atiny_params, const atiny_device_info_t *device_info, handle_data_t *handle) { int result; client_data_t *pdata; lwm2m_context_t *lwm2m_context = NULL; uint16_t serverId = SERVER_ID; char *epname = (char *)device_info->endpoint_name; pdata = &handle->client_data; memset(pdata, 0, sizeof(client_data_t)); ATINY_LOG(LOG_INFO, "Trying to init objects"); lwm2m_context = lwm2m_init(pdata); if (NULL == lwm2m_context) { ATINY_LOG(LOG_FATAL, "lwm2m_init fail"); return ATINY_MALLOC_FAILED; } lwm2m_context->observe_mutex = atiny_mutex_create(); if (NULL == lwm2m_context->observe_mutex) { ATINY_LOG(LOG_FATAL, "atiny_mutex_create fail"); lwm2m_free(lwm2m_context); return ATINY_RESOURCE_NOT_ENOUGH; } pdata->lwm2mH = lwm2m_context; handle->lwm2m_context = lwm2m_context; //even if not in bootstrap sequence mode, still set it NO_BS_SEQUENCE_STATE atiny_set_bootstrap_sequence_state(atiny_params, lwm2m_context); handle->obj_array[OBJ_SECURITY_INDEX] = get_security_object(serverId, atiny_params, lwm2m_context); if (NULL == handle->obj_array[OBJ_SECURITY_INDEX]) { ATINY_LOG(LOG_FATAL, "Failed to create security object"); return ATINY_MALLOC_FAILED; } pdata->securityObjP = handle->obj_array[OBJ_SECURITY_INDEX]; handle->obj_array[OBJ_SERVER_INDEX] = get_server_object(serverId, atiny_params->server_params.binding, atiny_params->server_params.life_time, atiny_params->server_params.storing_cnt != 0); if (NULL == handle->obj_array[OBJ_SERVER_INDEX]) { ATINY_LOG(LOG_FATAL, "Failed to create server object"); return ATINY_MALLOC_FAILED; } handle->obj_array[OBJ_ACCESS_CONTROL_INDEX] = acc_ctrl_create_object(); if (NULL == handle->obj_array[OBJ_ACCESS_CONTROL_INDEX]) { ATINY_LOG(LOG_FATAL, "Failed to create access control object"); return ATINY_MALLOC_FAILED; } handle->obj_array[OBJ_DEVICE_INDEX] = get_object_device(atiny_params, device_info->manufacturer); if (NULL == handle->obj_array[OBJ_DEVICE_INDEX]) { ATINY_LOG(LOG_FATAL, "Failed to create device object"); return ATINY_MALLOC_FAILED; } handle->obj_array[OBJ_CONNECT_INDEX] = get_object_conn_m(atiny_params); if (NULL == handle->obj_array[OBJ_CONNECT_INDEX]) { ATINY_LOG(LOG_FATAL, "Failed to create connect object"); return ATINY_MALLOC_FAILED; } handle->obj_array[OBJ_FIRMWARE_INDEX] = get_object_firmware(atiny_params); #ifdef CONFIG_FEATURE_FOTA if (NULL == handle->obj_array[OBJ_FIRMWARE_INDEX]) { ATINY_LOG(LOG_FATAL, "Failed to create firmware object"); return ATINY_MALLOC_FAILED; } #endif handle->obj_array[OBJ_LOCATION_INDEX] = get_object_location(); if (NULL == handle->obj_array[OBJ_LOCATION_INDEX]) { ATINY_LOG(LOG_FATAL, "Failed to create location object"); return ATINY_MALLOC_FAILED; } handle->obj_array[OBJ_APP_INDEX] = get_binary_app_data_object(atiny_params); if (NULL == handle->obj_array[OBJ_APP_INDEX]) { ATINY_LOG(LOG_FATAL, "Failed to create app object"); return ATINY_MALLOC_FAILED; } result = lwm2m_configure(lwm2m_context, epname, NULL, NULL, OBJ_MAX_NUM, handle->obj_array); if (result != 0) { return ATINY_RESOURCE_NOT_FOUND; } return ATINY_OK; } static int lwm2m_poll(handle_data_t *phandle, uint32_t *timeout) { client_data_t *dataP; int numBytes; connection_t *connP; lwm2m_context_t *contextP = phandle->lwm2m_context; uint8_t *recv_buffer = phandle->recv_buffer; dataP = (client_data_t *)(contextP->userData); connP = dataP->connList; while (connP != NULL) { numBytes = lwm2m_buffer_recv(connP, recv_buffer, MAX_PACKET_SIZE, *timeout); if (numBytes <= 0) { ATINY_LOG(LOG_INFO, "no packet arrived!"); } else { output_buffer(stderr, recv_buffer, numBytes, 0); lwm2m_handle_packet(contextP, recv_buffer, numBytes, connP); } connP = connP->next; } return ATINY_OK; } void atiny_destroy(void *handle) { handle_data_t *handle_data = (handle_data_t *)handle; if (handle_data == NULL) { return; } #ifdef CONFIG_FEATURE_FOTA atiny_fota_manager_destroy(atiny_fota_manager_get_instance()); #endif if(handle_data->recv_buffer != NULL) { lwm2m_free(handle_data->recv_buffer); } if (handle_data->obj_array[OBJ_SECURITY_INDEX] != NULL) { clean_security_object(handle_data->obj_array[OBJ_SECURITY_INDEX]); } if (handle_data->obj_array[OBJ_SERVER_INDEX] != NULL) { clean_server_object(handle_data->obj_array[OBJ_SERVER_INDEX]); } if (handle_data->obj_array[OBJ_ACCESS_CONTROL_INDEX] != NULL) { acl_ctrl_free_object(handle_data->obj_array[OBJ_ACCESS_CONTROL_INDEX]); } if (handle_data->obj_array[OBJ_DEVICE_INDEX] != NULL) { free_object_device(handle_data->obj_array[OBJ_DEVICE_INDEX]); } if (handle_data->obj_array[OBJ_CONNECT_INDEX] != NULL) { free_object_conn_m(handle_data->obj_array[OBJ_CONNECT_INDEX]); } if (handle_data->obj_array[OBJ_FIRMWARE_INDEX] != NULL) { free_object_firmware(handle_data->obj_array[OBJ_FIRMWARE_INDEX]); } if (handle_data->obj_array[OBJ_LOCATION_INDEX] != NULL) { free_object_location(handle_data->obj_array[OBJ_LOCATION_INDEX]); } if (handle_data->obj_array[OBJ_APP_INDEX] != NULL) { free_binary_app_data_object(handle_data->obj_array[OBJ_APP_INDEX]); } atiny_destroy_rpt(); if (handle_data->lwm2m_context != NULL) { if (handle_data->lwm2m_context->observe_mutex != NULL) { atiny_mutex_destroy(handle_data->lwm2m_context->observe_mutex); } lwm2m_close(handle_data->lwm2m_context); } atiny_mutex_unlock(handle_data->quit_sem); } void atiny_event_handle(module_type_t type, int code, const char *arg, int arg_len) { switch (type) { case MODULE_LWM2M: { if (code == STATE_REGISTERED) { atiny_event_notify(ATINY_REG_OK, NULL, 0); #ifdef CONFIG_FEATURE_FOTA (void)atiny_fota_manager_repot_result(atiny_fota_manager_get_instance()); #endif } else if (code == STATE_REG_FAILED) { atiny_event_notify(ATINY_REG_FAIL, NULL, 0); } break; } case MODULE_NET: { break; } case MODULE_URI: { if ((arg == NULL) || (arg_len < sizeof(lwm2m_uri_t))) { break; } if (code == OBSERVE_UNSUBSCRIBE) { if (dm_isUriOpaqueHandle((lwm2m_uri_t *)arg)) { atiny_report_type_e rpt_type = APP_DATA; atiny_event_notify(ATINY_DATA_UNSUBSCRIBLE, (char *)&rpt_type, sizeof(rpt_type)); } (void)atiny_clear_rpt_data((lwm2m_uri_t *)arg, SENT_FAIL); } else if (code == OBSERVE_SUBSCRIBE) { if (dm_isUriOpaqueHandle((lwm2m_uri_t *)arg)) { atiny_report_type_e rpt_type = APP_DATA; atiny_event_notify(ATINY_DATA_SUBSCRIBLE, (char *)&rpt_type, sizeof(rpt_type)); } } break; } default: { break; } } } void reboot_check(void) { if(g_reboot == 1) { (void)atiny_cmd_ioctl(ATINY_DO_DEV_REBOOT, NULL, 0); } } static void atiny_connection_err_notify(lwm2m_context_t *context, connection_err_e err_type, bool boostrap_flag) { handle_data_t *handle = NULL; if((NULL == context) || (NULL == context->userData)) { ATINY_LOG(LOG_ERR, "null point"); return; } if(!boostrap_flag) { handle = ATINY_FIELD_TO_STRUCT(context->userData, handle_data_t, client_data); (void)atiny_reconnect(handle); } ATINY_LOG(LOG_INFO, "connection err type %d bootstrap %d", err_type, boostrap_flag); } static void atiny_handle_reconnect(handle_data_t *handle) { if(handle->reconnect_flag) { (void)lwm2m_reconnect(handle->lwm2m_context); handle->reconnect_flag = false; ATINY_LOG(LOG_INFO, "lwm2m reconnect"); } } int atiny_bind(atiny_device_info_t *device_info, void *phandle) { handle_data_t *handle = (handle_data_t *)phandle; uint32_t timeout; int ret; if ((NULL == device_info) || (NULL == phandle)) { ATINY_LOG(LOG_FATAL, "Parameter null"); atiny_deinit(phandle); return ATINY_ARG_INVALID; } if (NULL == device_info->endpoint_name) { ATINY_LOG(LOG_FATAL, "Endpoint name null"); atiny_deinit(phandle); return ATINY_ARG_INVALID; } if (NULL == device_info->manufacturer) { ATINY_LOG(LOG_FATAL, "Manufacturer name null"); atiny_deinit(phandle); return ATINY_ARG_INVALID; } ret = atiny_init_objects(&handle->atiny_params, device_info, handle); if (ret != ATINY_OK) { ATINY_LOG(LOG_FATAL, "atiny_init_object fail %d", ret); atiny_destroy(handle); return ret; } #ifdef CONFIG_FEATURE_FOTA (void)atiny_fota_manager_set_lwm2m_context(atiny_fota_manager_get_instance(), handle->lwm2m_context); #endif lwm2m_register_observe_ack_call_back(observe_handle_ack); lwm2m_register_event_handler(atiny_event_handle); lwm2m_register_connection_err_notify(atiny_connection_err_notify); handle->recv_buffer = (uint8_t *)lwm2m_malloc(MAX_PACKET_SIZE); if(handle->recv_buffer == NULL) { ATINY_LOG(LOG_FATAL, "memory not enough"); return ATINY_MALLOC_FAILED; } while (!handle->atiny_quit) { timeout = BIND_TIMEOUT; (void)atiny_step_rpt(handle->lwm2m_context); atiny_handle_reconnect(handle); (void)lwm2m_step(handle->lwm2m_context, (time_t *)&timeout); reboot_check(); (void)lwm2m_poll(handle, &timeout); } atiny_destroy(phandle); return ATINY_OK; } void atiny_deinit(void *phandle) { handle_data_t *handle; void *sem = NULL; if (phandle == NULL) { return; } handle = (handle_data_t *)phandle; handle->atiny_quit = 1; sem = handle->quit_sem; atiny_mutex_lock(sem); atiny_mutex_destroy(sem); } int atiny_data_report(void *phandle, data_report_t *report_data) { lwm2m_uri_t uri; int ret; data_report_t data; if (NULL == phandle || NULL == report_data || report_data->len <= 0 || report_data->len > MAX_REPORT_DATA_LEN || NULL == report_data->buf) { ATINY_LOG(LOG_ERR, "invalid args"); return ATINY_ARG_INVALID; } memset((void *)&uri, 0, sizeof(uri)); switch (report_data->type) { case FIRMWARE_UPDATE_STATE: (void)lwm2m_stringToUri("/5/0/3", 6, &uri); break; case APP_DATA: get_resource_uri(BINARY_APP_DATA_OBJECT_ID, 0, BINARY_APP_DATA_RES_ID, &uri); break; default: return ATINY_RESOURCE_NOT_FOUND; } memcpy(&data, report_data, sizeof(data)); data.buf = lwm2m_malloc(report_data->len); if (NULL == data.buf) { ATINY_LOG(LOG_ERR, "lwm2m_malloc fail,len %d", data.len); return ATINY_MALLOC_FAILED;; } memcpy(data.buf, report_data->buf, report_data->len); ret = atiny_queue_rpt_data(&uri, &data); if (ATINY_OK != ret) { if (data.buf != NULL) { lwm2m_free(data.buf); } } return ret; } int atiny_data_change(void *phandle, const char *data_type) { lwm2m_uri_t uri; handle_data_t *handle; if (NULL == phandle || NULL == data_type) { ATINY_LOG(LOG_ERR, "invalid args"); return ATINY_ARG_INVALID; } memset((void *)&uri, 0, sizeof(uri)); handle = (handle_data_t *)phandle; if (handle->lwm2m_context->state != STATE_READY) { ATINY_LOG(LOG_INFO, "not registered"); return ATINY_CLIENT_UNREGISTERED; } (void)lwm2m_stringToUri(data_type, strlen(data_type), &uri); atiny_mutex_lock(handle->lwm2m_context->observe_mutex); lwm2m_resource_value_changed(handle->lwm2m_context, &uri); atiny_mutex_unlock(handle->lwm2m_context->observe_mutex); return ATINY_OK; } void observe_handle_ack(lwm2m_transaction_t *transacP, void *message) { atiny_ack_callback ack_callback = (atiny_ack_callback)transacP->cfg.callback; if (transacP->ack_received) { ack_callback((atiny_report_type_e)(transacP->cfg.type), transacP->cfg.cookie, SENT_SUCCESS); } else if (transacP->retrans_counter > COAP_MAX_RETRANSMIT) { ack_callback((atiny_report_type_e)(transacP->cfg.type), transacP->cfg.cookie, SENT_TIME_OUT); } else { ack_callback((atiny_report_type_e)(transacP->cfg.type), transacP->cfg.cookie, SENT_FAIL); } } int atiny_reconnect(void *phandle) { handle_data_t *handle = (handle_data_t *)phandle; if (NULL == phandle) { ATINY_LOG(LOG_FATAL, "Parameter null"); return ATINY_ARG_INVALID; } handle->reconnect_flag = true; return ATINY_OK; } void atiny_set_reboot_flag() { g_reboot = true; } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/atiny_context.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _ATINY_CONTEXT_H #define _ATINY_CONTEXT_H #include "liblwm2m.h" #include "atiny_lwm2m/agenttiny.h" #include "object_comm.h" #define SERVER_URI_MAX_LEN (64) #define MAX_PACKET_SIZE (1024) #define SERVER_ID (123) #define BIND_TIMEOUT (10) #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** *@ingroup handle_data_t *Structure of agentiny hanle. */ enum { OBJ_SECURITY_INDEX = 0, OBJ_SERVER_INDEX, OBJ_ACCESS_CONTROL_INDEX, OBJ_DEVICE_INDEX, OBJ_CONNECT_INDEX, OBJ_FIRMWARE_INDEX, OBJ_LOCATION_INDEX, OBJ_APP_INDEX, OBJ_MAX_NUM, }; typedef struct { lwm2m_context_t *lwm2m_context; atiny_param_t atiny_params; client_data_t client_data; lwm2m_object_t *obj_array[OBJ_MAX_NUM]; int atiny_quit; int reconnect_flag; void *quit_sem; int reboot_flag; uint8_t *recv_buffer; } handle_data_t; #ifdef __cplusplus } #endif /* __cplusplus */ #endif /* _ATINY_INNER_H */ ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/atiny_fota_manager.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "atiny_fota_manager.h" #include "atiny_fota_state.h" #include #include "firmware_update.h" #include "ota/package.h" struct atiny_fota_manager_tag_s { char *pkg_uri; atiny_fota_state_e state; atiny_update_result_e update_result; atiny_fota_idle_state_s idle_state; atiny_fota_downloading_state_s downloading_state; atiny_fota_downloaded_state_s downloaded_state; atiny_fota_updating_state_s updating_state; atiny_fota_state_s *current; pack_storage_device_api_s *device; lwm2m_context_t *lwm2m_context; uint32_t cookie; bool wait_ack_flag; atiny_fota_state_e rpt_state; ota_opt_s ota_opt; bool init_flag; }; #define PULL_ONLY 0 static uint32_t g_firmware_cookie = 0; char *atiny_fota_manager_get_pkg_uri(const atiny_fota_manager_s *thi) { ASSERT_THIS(return NULL); return thi->pkg_uri; } int atiny_fota_manager_get_state(const atiny_fota_manager_s *thi) { ASSERT_THIS(return ATINY_FOTA_IDLE); return thi->state; } int atiny_fota_manager_get_rpt_state(const atiny_fota_manager_s *thi) { ASSERT_THIS(return ATINY_FOTA_IDLE); return thi->rpt_state; } int atiny_fota_manager_get_update_result(const atiny_fota_manager_s *thi) { ASSERT_THIS(return ATINY_FIRMWARE_UPDATE_NULL); return thi->update_result; } void atiny_fota_manager_set_update_result(atiny_fota_manager_s *thi, atiny_update_result_e result) { ASSERT_THIS(return); thi->update_result = result; } int atiny_fota_manager_get_deliver_method(const atiny_fota_manager_s *thi) { return PULL_ONLY; } int atiny_fota_manager_start_download(atiny_fota_manager_s *thi, const char *uri, uint32_t len) { ASSERT_THIS(return ATINY_ARG_INVALID); if(thi->state != thi->rpt_state) { ATINY_LOG(LOG_ERR, "start download busy state %u rpt state %u", thi->state, thi->rpt_state); return ATINY_ERR; } if(NULL == thi->current || uri == NULL) { ATINY_LOG(LOG_ERR, "null pointer"); return ATINY_ERR; } if(thi->pkg_uri) { atiny_free(thi->pkg_uri); thi->pkg_uri = NULL; } thi->pkg_uri = atiny_malloc(len + 1); if(NULL == thi->pkg_uri) { ATINY_LOG(LOG_ERR, "lwm2m_strdup fail"); return ATINY_ERR; } memcpy(thi->pkg_uri, uri, len); thi->pkg_uri[len] = '\0'; ATINY_LOG(LOG_INFO, "start download"); return thi->current->start_download(thi->current, thi->pkg_uri); } int atiny_fota_manager_execute_update(atiny_fota_manager_s *thi) { ASSERT_THIS(return ATINY_ARG_INVALID); if(thi->state != thi->rpt_state) { ATINY_LOG(LOG_ERR, "execute update busy state %u rpt state %u", thi->state, thi->rpt_state); return ATINY_ERR; } if(NULL == thi->current) { ATINY_LOG(LOG_ERR, "current null pointer"); return ATINY_ERR; } ATINY_LOG(LOG_INFO, "excecute update"); return thi->current->execute_update(thi->current); } int atiny_fota_manager_finish_download(atiny_fota_manager_s *thi, int result) { ASSERT_THIS(return ATINY_ARG_INVALID); if(thi->state != thi->rpt_state) { ATINY_LOG(LOG_ERR, "finish download busy state %u rpt state %u", thi->state, thi->rpt_state); return ATINY_ERR; } if(NULL == thi->current) { ATINY_LOG(LOG_ERR, "current null pointer"); return ATINY_ERR; } ATINY_LOG(LOG_INFO, "finish download result %d", result); return thi->current->finish_download(thi->current, result); } int atiny_fota_manager_repot_result(atiny_fota_manager_s *thi) { ASSERT_THIS(return ATINY_ARG_INVALID); if(NULL == thi->current) { ATINY_LOG(LOG_ERR, "current null pointer"); return ATINY_ERR; } return thi->current->repot_result(thi->current); } int atiny_fota_manager_set_state(atiny_fota_manager_s *thi, atiny_fota_state_e state) { ASSERT_THIS(return ATINY_ARG_INVALID); if(state > ATINY_FOTA_UPDATING) { ATINY_LOG(LOG_ERR, "invalid download state %d", state); return ATINY_ARG_INVALID; } ATINY_LOG(LOG_INFO, "download stat from %d to %d", thi->state, state); if(thi->state != state) { /*lint -e614 */ atiny_fota_state_s *states[ATINY_FOTA_UPDATING + 1]; states[ATINY_FOTA_IDLE] = ATINY_GET_STATE(thi->idle_state); states[ATINY_FOTA_DOWNLOADING] = ATINY_GET_STATE(thi->downloading_state); states[ATINY_FOTA_DOWNLOADED] = ATINY_GET_STATE(thi->downloaded_state); states[ATINY_FOTA_UPDATING] = ATINY_GET_STATE(thi->updating_state); thi->current = states[state]; thi->state = state; thi->wait_ack_flag = false; /*lint +e614 */ } thi->rpt_state = state; atiny_event_notify(ATINY_FOTA_STATE, (const char *)&thi->state, sizeof(thi->state)); return ATINY_OK; } int atiny_fota_manager_rpt_state(atiny_fota_manager_s *thi, atiny_fota_state_e rpt_state) { lwm2m_uri_t uri; const char *uri_str = "/5/0/3"; ASSERT_THIS(return ATINY_ARG_INVALID); atiny_fota_manager_save_rpt_state(thi, rpt_state); memset((void *)&uri, 0, sizeof(uri)); (void)lwm2m_stringToUri(uri_str, strlen(uri_str), &uri); lwm2m_resource_value_changed(thi->lwm2m_context, &uri); return ATINY_OK; } void atiny_fota_manager_save_rpt_state(atiny_fota_manager_s *thi, atiny_fota_state_e rpt_state) { ASSERT_THIS(return); ATINY_LOG(LOG_INFO, "rpt download state %d", rpt_state); thi->rpt_state = rpt_state; thi->wait_ack_flag = true; thi->cookie = g_firmware_cookie++; } static int atiny_fota_manager_flag_read(void* buf, int32_t len) { int (*read_flash)(ota_flash_type_e type, void *buf, int32_t len, uint32_t location) = atiny_fota_manager_get_instance()->ota_opt.read_flash; if (read_flash) { return read_flash(OTA_UPDATE_INFO, buf, len, 0); } ATINY_LOG(LOG_ERR, "write_flash null"); return -1; } static int atiny_fota_manager_flag_write(const void* buf, int32_t len) { int (*write_flash)(ota_flash_type_e type, const void *buf, int32_t len, uint32_t location) = atiny_fota_manager_get_instance()->ota_opt.write_flash; if (write_flash) { return write_flash(OTA_UPDATE_INFO, buf, len, 0); } ATINY_LOG(LOG_ERR, "write_flash null"); return -1; } int atiny_fota_manager_set_storage_device(atiny_fota_manager_s *thi) { int ret; flag_op_s flag_op; pack_params_s pack_param; ASSERT_THIS(return ATINY_ARG_INVALID); ret = atiny_cmd_ioctl(ATINY_GET_OTA_OPT, (char * )&thi->ota_opt, sizeof(thi->ota_opt)); if (ret != ATINY_OK) { ATINY_LOG(LOG_FATAL, "atiny_cmd_ioctl fail"); return ret; } flag_op.func_flag_read = atiny_fota_manager_flag_read; flag_op.func_flag_write = atiny_fota_manager_flag_write; (void)flag_init(&flag_op); ret = flag_upgrade_init(); if (ret != ATINY_OK) { ATINY_LOG(LOG_FATAL, "flag_upgrade_init fail"); return ret; } memcpy(&pack_param.ota_opt, &thi->ota_opt, sizeof(pack_param.ota_opt)); pack_param.malloc = atiny_malloc; pack_param.free = atiny_free; pack_param.printf = atiny_printf; ret = pack_init_device(&pack_param); if (ret != ATINY_OK) { ATINY_LOG(LOG_FATAL, "pack_init_device fail"); return ret; } thi->device = pack_get_device(); return atiny_fota_idle_state_int_report_result(&thi->idle_state); } pack_storage_device_api_s *atiny_fota_manager_get_storage_device(atiny_fota_manager_s *thi) { ASSERT_THIS(return NULL); return thi->device; } void atiny_fota_manager_update_notify(firmware_update_rst_e rst, void *param) { atiny_fota_manager_s *thi = ( atiny_fota_manager_s *)param; (void)atiny_fota_manager_finish_download(thi, rst); } void atiny_fota_manager_init(atiny_fota_manager_s *thi) { memset(thi, 0, sizeof(*thi)); atiny_fota_idle_state_init(&thi->idle_state, thi); atiny_fota_downloading_state_init(&thi->downloading_state, thi); atiny_fota_downloaded_state_init(&thi->downloaded_state, thi); atiny_fota_updating_state_init(&thi->updating_state, thi); thi->current = ATINY_GET_STATE(thi->idle_state); set_firmware_update_notify(atiny_fota_manager_update_notify, thi); atiny_event_notify(ATINY_FOTA_STATE, (const char *)&thi->state, sizeof(thi->state)); thi->init_flag = true; } void atiny_fota_manager_destroy(atiny_fota_manager_s *thi) { ASSERT_THIS(return); if(thi->pkg_uri) { atiny_free(thi->pkg_uri); } /*lint -e668 */ memset(thi, 0, sizeof(*thi)); /*lint +e668 */ } int atiny_fota_manager_set_lwm2m_context(atiny_fota_manager_s *thi, lwm2m_context_t *lwm2m_context) { ASSERT_THIS(return ATINY_ARG_INVALID); thi->lwm2m_context = lwm2m_context; return ATINY_OK; } lwm2m_context_t *atiny_fota_manager_get_lwm2m_context(atiny_fota_manager_s *thi) { ASSERT_THIS(return NULL); return thi->lwm2m_context; } static int atiny_fota_manager_rcv_notify_ack(atiny_fota_manager_s *thi, data_send_status_e status) { ASSERT_THIS(return ATINY_ARG_INVALID); if(NULL == thi->current) { ATINY_LOG(LOG_ERR, "current null pointer"); return ATINY_ERR; } return thi->current->recv_notify_ack(thi->current, status); } static void atiny_fota_manager_notify_ack_callback(atiny_report_type_e type, int cookie, data_send_status_e status) { ATINY_LOG(LOG_INFO, "download state ack type %d rev cookie %u expect cookie %u status %d, rpt stat %d", type, (uint32_t)cookie, atiny_fota_manager_get_instance()->cookie, status, atiny_fota_manager_get_instance()->rpt_state); if((atiny_fota_manager_get_instance()->wait_ack_flag) && atiny_fota_manager_get_instance()->cookie == cookie) { (void)atiny_fota_manager_rcv_notify_ack(atiny_fota_manager_get_instance(), status); atiny_fota_manager_get_instance()->wait_ack_flag = false; } } void atiny_fota_manager_get_data_cfg(const atiny_fota_manager_s *thi, lwm2m_data_cfg_t *data_cfg) { ASSERT_THIS(return); if(NULL == data_cfg) { ATINY_LOG(LOG_ERR, "current null pointer"); return; } data_cfg->callback = (lwm2m_data_process)atiny_fota_manager_notify_ack_callback; data_cfg->cookie = thi->cookie; // ATINY_LOG(LOG_INFO, "download cookie %d", data_cfg->cookie); data_cfg->type = FIRMWARE_UPDATE_STATE; } static atiny_fota_manager_s g_fota_manager; atiny_fota_manager_s *atiny_fota_manager_get_instance(void) { atiny_fota_manager_s *manager = &g_fota_manager; if(manager->init_flag) { return manager; } atiny_fota_manager_init(manager); return manager; } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/atiny_fota_manager.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2014 Bosch Software Innovations GmbH, Germany. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Bosch Software Innovations GmbH - Please refer to git log * *******************************************************************************/ #ifndef ATINY_FOTA_MANAGER_H_ #define ATINY_FOTA_MANAGER_H_ #include "atiny_lwm2m/agenttiny.h" #include "liblwm2m.h" #include "ota/package.h" #define array_size(a) (sizeof(a)/sizeof(*(a))) /* 0: Initial value. Once the updating process is initiated (Download /Update), this Resource MUST be reset to Initial value. 1: Firmware updated successfully, 2: Not enough flash memory for the new firmware package. 3. Out of RAM during downloading process. 4: Connection lost during downloading process. 5: Integrity check failure for new downloaded package. 6: Unsupported package type. 7: Invalid URI 8: Firmware update failed 9: Unsupported protocol */ typedef int atiny_fota_state_e; enum //atiny_fota_state_e { ATINY_FOTA_IDLE = 0, ATINY_FOTA_DOWNLOADING, ATINY_FOTA_DOWNLOADED, ATINY_FOTA_UPDATING }; typedef int atiny_update_result_e; enum { ATINY_FIRMWARE_UPDATE_NULL = 0, ATINY_FIRMWARE_UPDATE_SUCCESS = 1, ATINY_FIRMWARE_UPDATE_FAIL = 8 }; struct atiny_fota_manager_tag_s; typedef struct atiny_fota_manager_tag_s atiny_fota_manager_s; #ifdef __cplusplus extern "C" { #endif char * atiny_fota_manager_get_pkg_uri(const atiny_fota_manager_s *thi); int atiny_fota_manager_get_state(const atiny_fota_manager_s *thi); int atiny_fota_manager_get_update_result(const atiny_fota_manager_s *thi); void atiny_fota_manager_set_update_result(atiny_fota_manager_s *thi, atiny_update_result_e result); int atiny_fota_manager_get_deliver_method(const atiny_fota_manager_s *thi); int atiny_fota_manager_start_download(atiny_fota_manager_s *thi, const char *uri, uint32_t len); int atiny_fota_manager_execute_update(atiny_fota_manager_s *thi); int atiny_fota_manager_repot_result(atiny_fota_manager_s *thi); int atiny_fota_manager_set_state(atiny_fota_manager_s *thi, atiny_fota_state_e state); int atiny_fota_manager_set_storage_device(atiny_fota_manager_s *thi); pack_storage_device_api_s *atiny_fota_manager_get_storage_device(atiny_fota_manager_s *thi); int atiny_fota_manager_set_lwm2m_context(atiny_fota_manager_s *thi, lwm2m_context_t* lwm2m_context); lwm2m_context_t* atiny_fota_manager_get_lwm2m_context(atiny_fota_manager_s *thi); void atiny_fota_manager_get_data_cfg(const atiny_fota_manager_s *thi, lwm2m_data_cfg_t *data_cfg); void atiny_fota_manager_destroy(atiny_fota_manager_s *thi); int atiny_fota_manager_rpt_state(atiny_fota_manager_s *thi, atiny_fota_state_e rpt_state); void atiny_fota_manager_save_rpt_state(atiny_fota_manager_s *thi, atiny_fota_state_e rpt_state); atiny_fota_state_e atiny_fota_manager_get_rpt_state(const atiny_fota_manager_s *thi); atiny_fota_manager_s * atiny_fota_manager_get_instance(void); #ifdef __cplusplus } #endif #endif /* ATINY_FOTA_MANAGER_H_ */ ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/atiny_fota_state.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "atiny_fota_state.h" #include #include "firmware_update.h" //TODO:set the update detail result static int atiny_fota_state_default_handle(struct atiny_fota_state_tag_s *thi) { ASSERT_THIS(return ATINY_ERR); ATINY_LOG(LOG_ERR, "err state handle state %d", thi->manager ? atiny_fota_manager_get_state(thi->manager) : -1); return ATINY_ERR; } void atiny_fota_state_init(atiny_fota_state_s *thi, atiny_fota_manager_s *manager) { thi->start_download = (int (*)(struct atiny_fota_state_tag_s * thi, const char *uri))atiny_fota_state_default_handle; thi->execute_update = atiny_fota_state_default_handle; thi->finish_download = (int (*)(struct atiny_fota_state_tag_s * thi, int result))atiny_fota_state_default_handle; thi->repot_result = atiny_fota_state_default_handle; thi->recv_notify_ack = (int (*)(struct atiny_fota_state_tag_s * thi, data_send_status_e status))atiny_fota_state_default_handle; thi->manager = manager; } static int atiny_fota_start_download(atiny_fota_state_s *thi, const char *uri) { ASSERT_THIS(return ATINY_ARG_INVALID); atiny_fota_manager_set_update_result(thi->manager, ATINY_FIRMWARE_UPDATE_NULL); return atiny_fota_manager_rpt_state(thi->manager, ATINY_FOTA_DOWNLOADING); } static int atiny_fota_idle_state_recv_notify_ack(atiny_fota_state_s *thi, data_send_status_e status) { int ret; atiny_fota_state_e rpt_state; if(SENT_SUCCESS != status) { ATINY_LOG(LOG_ERR, "idle state notify fail %d", status); atiny_fota_manager_set_update_result(thi->manager, ATINY_FIRMWARE_UPDATE_FAIL); return atiny_fota_manager_set_state(thi->manager, ATINY_FOTA_IDLE); } rpt_state = atiny_fota_manager_get_rpt_state(thi->manager) ; //idle and downloaded rpt ack if((ATINY_FOTA_IDLE == rpt_state) || (ATINY_FOTA_DOWNLOADED == rpt_state)) { return atiny_fota_manager_set_state(thi->manager, rpt_state); } //updating rpt ack if(ATINY_FOTA_UPDATING == rpt_state) { ATINY_LOG(LOG_ERR, "idle state recv updaing state ack"); return ATINY_ERR; } //downloading rpt ack //TODO, return then proper result ret = start_firmware_download(atiny_fota_manager_get_lwm2m_context(thi->manager), atiny_fota_manager_get_pkg_uri(thi->manager), atiny_fota_manager_get_storage_device(thi->manager)); if(ret == ATINY_OK) { return atiny_fota_manager_set_state(thi->manager, ATINY_FOTA_DOWNLOADING); } ATINY_LOG(LOG_ERR, "start_firmware_download fail %d", ret); atiny_fota_manager_set_update_result(thi->manager, ATINY_FIRMWARE_UPDATE_FAIL); return atiny_fota_manager_rpt_state(thi->manager, ATINY_FOTA_IDLE); } static int atiny_fota_idle_state_get_result(void) { upgrade_state_e state; if(flag_upgrade_get_result(&state) != ATINY_OK) { ATINY_LOG(LOG_ERR, "ota_check_update_state fail"); return ATINY_ERR; } return (OTA_SUCCEED == state) ? ATINY_OK : ATINY_ERR; } int atiny_fota_idle_state_int_report_result(atiny_fota_idle_state_s *thi) { lwm2m_observe_info_t observe_info; int ret = ATINY_ERR; int result = ATINY_ERR; ASSERT_THIS(return ATINY_ARG_INVALID); thi->report_flag = false; memset(&observe_info, 0, sizeof(lwm2m_observe_info_t)); if(flag_read(FLAG_APP, &observe_info, sizeof(observe_info)) != ATINY_OK) { ATINY_LOG(LOG_ERR, "flag_write fail"); goto EXIT; } if(0 == observe_info.tokenLen) { return ATINY_OK; } ret = atiny_fota_idle_state_get_result(); if(ret != ATINY_OK) { ATINY_LOG(LOG_ERR, "get_software_result fail"); } result = ATINY_OK; thi->report_result = ret; thi->report_flag = true; memcpy(&thi->observe_info, &observe_info, sizeof(thi->observe_info)); ATINY_LOG(LOG_INFO, "need to rpt result %d", ret); EXIT: memset(&observe_info, 0, sizeof(observe_info)); if(flag_write(FLAG_APP, &observe_info, sizeof(observe_info)) != ATINY_OK) { ATINY_LOG(LOG_ERR, "flag_write fail"); } return result; } static int atiny_fota_idle_state_report_result(atiny_fota_state_s *thi) { int ret = ATINY_ERR; atiny_fota_idle_state_s *idle_stat = (atiny_fota_idle_state_s *)thi; int state; lwm2m_data_cfg_t dataCfg = {0}; ASSERT_THIS(return ATINY_ARG_INVALID); if(!idle_stat->report_flag) { return ATINY_OK; } idle_stat->report_flag = false; state = ((ATINY_OK == idle_stat->report_result) ? ATINY_FOTA_IDLE : ATINY_FOTA_DOWNLOADED); atiny_fota_manager_set_update_result(thi->manager, (ATINY_OK == idle_stat->report_result) ? ATINY_FIRMWARE_UPDATE_SUCCESS : ATINY_FIRMWARE_UPDATE_FAIL); atiny_fota_manager_save_rpt_state(thi->manager, state); atiny_fota_manager_get_data_cfg(thi->manager, &dataCfg); ret = lwm2m_send_notify(atiny_fota_manager_get_lwm2m_context(thi->manager), &idle_stat->observe_info, state, &dataCfg); ATINY_LOG(LOG_INFO, "lwm2m_send_notify result %d, state %d", ret, state); return ret; } void atiny_fota_idle_state_init(atiny_fota_idle_state_s *thi, atiny_fota_manager_s *manager) { memset(thi, 0, sizeof(*thi)); atiny_fota_state_init(&thi->interface, manager); thi->interface.start_download = atiny_fota_start_download; thi->interface.repot_result = atiny_fota_idle_state_report_result; thi->interface.recv_notify_ack = atiny_fota_idle_state_recv_notify_ack; } static int atiny_fota_downloading_state_finish_download(atiny_fota_state_s *thi, int result) { ASSERT_THIS(return ATINY_ARG_INVALID); if(ATINY_OK != result) { atiny_fota_manager_set_update_result(thi->manager, ATINY_FIRMWARE_UPDATE_FAIL); } return atiny_fota_manager_rpt_state(thi->manager, (ATINY_OK == result) ? ATINY_FOTA_DOWNLOADED : ATINY_FOTA_IDLE); } static int atiny_fota_downloading_state_recv_notify_ack(atiny_fota_state_s *thi, data_send_status_e status) { atiny_fota_state_e rpt_state; if(SENT_SUCCESS != status) { ATINY_LOG(LOG_ERR, "downloading state notify ack fail %d", status); atiny_fota_manager_set_update_result(thi->manager, ATINY_FIRMWARE_UPDATE_FAIL); return atiny_fota_manager_set_state(thi->manager, ATINY_FOTA_IDLE); } rpt_state = atiny_fota_manager_get_rpt_state(thi->manager); if((ATINY_FOTA_IDLE == rpt_state) || (ATINY_FOTA_DOWNLOADED == rpt_state)) { return atiny_fota_manager_set_state(thi->manager, rpt_state); } else { ATINY_LOG(LOG_ERR, "recv notify ack err in downloading state, rpt state %d", rpt_state); return ATINY_ERR; } } void atiny_fota_downloading_state_init(atiny_fota_downloading_state_s *thi, atiny_fota_manager_s *manager) { atiny_fota_state_init(&thi->interface, manager); thi->interface.finish_download = atiny_fota_downloading_state_finish_download; thi->interface.recv_notify_ack = atiny_fota_downloading_state_recv_notify_ack; } static int atiny_fota_downloaded_state_execute_update(atiny_fota_state_s *thi) { atiny_fota_state_e rpt_state = ATINY_FOTA_UPDATING; ASSERT_THIS(return ATINY_ARG_INVALID); if(atiny_fota_manager_get_update_result(thi->manager) != ATINY_FIRMWARE_UPDATE_NULL) { rpt_state = ATINY_FOTA_IDLE; atiny_fota_manager_set_update_result(thi->manager, ATINY_FIRMWARE_UPDATE_FAIL); } return atiny_fota_manager_rpt_state(thi->manager, rpt_state); } static int atiny_fota_downloaded_state_recv_notify_ack(atiny_fota_state_s *thi, data_send_status_e status) { int ret; atiny_fota_state_e rpt_state; lwm2m_observe_info_t observe_info; pack_storage_device_api_s *device; ASSERT_THIS(return ATINY_ARG_INVALID); if(SENT_SUCCESS != status) { ATINY_LOG(LOG_ERR, "downloaded state notify fail %d", status); atiny_fota_manager_set_update_result(thi->manager, ATINY_FIRMWARE_UPDATE_FAIL); return atiny_fota_manager_set_state(thi->manager, ATINY_FOTA_IDLE); } rpt_state = atiny_fota_manager_get_rpt_state(thi->manager); //rpt downloading state ack if(ATINY_FOTA_DOWNLOADING == rpt_state) { ret = start_firmware_download(atiny_fota_manager_get_lwm2m_context(thi->manager), atiny_fota_manager_get_pkg_uri(thi->manager), atiny_fota_manager_get_storage_device(thi->manager)); if(ret == ATINY_OK) { return atiny_fota_manager_set_state(thi->manager, ATINY_FOTA_DOWNLOADING); } ATINY_LOG(LOG_ERR, "start_firmware_download fail %d", ret); atiny_fota_manager_set_update_result(thi->manager, ATINY_FIRMWARE_UPDATE_FAIL); (void)atiny_fota_manager_rpt_state(thi->manager, ATINY_FOTA_IDLE); return ATINY_ERR; } //rpt idle state ack if(ATINY_FOTA_IDLE == rpt_state) { return atiny_fota_manager_set_state(thi->manager, rpt_state); } //rpt downloaded state ack if(ATINY_FOTA_DOWNLOADED == rpt_state) { return ATINY_OK; } //rpt updating state ack if(lwm2m_get_observe_info(atiny_fota_manager_get_lwm2m_context(thi->manager), &observe_info) != COAP_NO_ERROR || 0 == observe_info.tokenLen) { ATINY_LOG(LOG_ERR, "lwm2m_get_observe_info fail"); goto EXIT_DOWNLOADED; } device = atiny_fota_manager_get_storage_device(thi->manager); if((NULL == device) || (NULL == device->active_software) || (device->active_software(device) != ATINY_OK)) { ATINY_LOG(LOG_ERR, "active_software fail"); goto EXIT_DOWNLOADED; } if(flag_write(FLAG_APP, &observe_info, sizeof(observe_info)) != ATINY_OK) { ATINY_LOG(LOG_ERR, "flag_write fail"); goto EXIT_DOWNLOADED; } atiny_set_reboot_flag(); return atiny_fota_manager_set_state(thi->manager, ATINY_FOTA_UPDATING); EXIT_DOWNLOADED: atiny_fota_manager_set_update_result(thi->manager, ATINY_FIRMWARE_UPDATE_FAIL); (void)atiny_fota_manager_rpt_state(thi->manager, ATINY_FOTA_DOWNLOADED); return ATINY_ERR; } void atiny_fota_downloaded_state_init(atiny_fota_downloaded_state_s *thi, atiny_fota_manager_s *manager) { atiny_fota_state_init(&thi->interface, manager); thi->interface.start_download = atiny_fota_start_download; thi->interface.execute_update = atiny_fota_downloaded_state_execute_update; thi->interface.recv_notify_ack = atiny_fota_downloaded_state_recv_notify_ack; } void atiny_fota_updating_state_init(atiny_fota_updating_state_s *thi, atiny_fota_manager_s *manager) { atiny_fota_state_init(&thi->interface, manager); } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/atiny_fota_state.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2014 Bosch Software Innovations GmbH, Germany. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Bosch Software Innovations GmbH - Please refer to git log * *******************************************************************************/ #ifndef ATINY_FOTA_STATE_H_ #define ATINY_FOTA_STATE_H_ #include "atiny_fota_manager.h" #include "log/atiny_log.h" #include "object_comm.h" #include "flag_manager.h" #include "upgrade_flag.h" #define ASSERT_THIS(do_something) \ if(NULL == thi)\ {\ ATINY_LOG(LOG_ERR, "this null pointer");\ do_something;\ } #define ATINY_GET_STATE(state) (&((state).interface)) #define CALL_MEM_FUNCTION_R(object, func, ret, ...) do\ {\ if(NULL != (object) && (NULL != (object)->func))\ {\ (ret) = (object)->func(__VA_ARGS__);\ }\ }while(0) typedef struct atiny_fota_state_tag_s { int (*start_download)(struct atiny_fota_state_tag_s * thi, const char *uri); int (*execute_update)(struct atiny_fota_state_tag_s * thi); int (*finish_download)(struct atiny_fota_state_tag_s * thi, int result); int (*repot_result)(struct atiny_fota_state_tag_s *thi); int (*recv_notify_ack)(struct atiny_fota_state_tag_s *thi, data_send_status_e status); atiny_fota_manager_s *manager; }atiny_fota_state_s; typedef struct { atiny_fota_state_s interface; lwm2m_observe_info_t observe_info; int report_result; bool report_flag; }atiny_fota_idle_state_s; typedef struct atiny_fota_downloading_state_tag_s { atiny_fota_state_s interface; }atiny_fota_downloading_state_s; typedef atiny_fota_downloading_state_s atiny_fota_downloaded_state_s; typedef atiny_fota_downloading_state_s atiny_fota_updating_state_s; #ifdef __cplusplus extern "C" { #endif void atiny_fota_state_init(atiny_fota_state_s *thi, atiny_fota_manager_s *manager); void atiny_fota_idle_state_init(atiny_fota_idle_state_s *thi, atiny_fota_manager_s *manager); int atiny_fota_idle_state_int_report_result(atiny_fota_idle_state_s * thi); void atiny_fota_downloading_state_init(atiny_fota_downloading_state_s *thi, atiny_fota_manager_s *manager); void atiny_fota_downloaded_state_init(atiny_fota_downloaded_state_s *thi, atiny_fota_manager_s *manager); void atiny_fota_updating_state_init(atiny_fota_updating_state_s *thi, atiny_fota_manager_s *manager); #ifdef __cplusplus } #endif #endif /* ATINY_FOTA_STATE_H_ */ ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/atiny_rpt.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "liblwm2m.h" #include "atiny_rpt.h" #include "log/atiny_log.h" typedef struct _atiny_rpt_list_t { atiny_dl_list node; lwm2m_uri_t uri; atiny_dl_list rpt_list; uint32_t rpt_node_cnt; uint32_t max_cnt; } atiny_rpt_list_t; typedef struct { atiny_dl_list list; data_report_t data; } atiny_rpt_node_t; static atiny_dl_list g_atiny_rpt_table; static void *g_mutex = NULL; // TODO: when free, recorrect then callback code static int atiny_is_uri_equal(const lwm2m_uri_t *uri0, const lwm2m_uri_t *uri1) { if (LWM2M_URI_IS_SET_RESOURCE(uri0) && LWM2M_URI_IS_SET_RESOURCE(uri1)) { return (uri0->objectId == uri1->objectId) && (uri0->instanceId == uri1->instanceId) && (uri0->resourceId == uri1->resourceId); } return (uri0->objectId == uri1->objectId) && (uri0->instanceId == uri1->instanceId); } static atiny_rpt_list_t *atiny_find_rpt_list(const lwm2m_uri_t *uri) { atiny_dl_list *item; atiny_dl_list *next; ATINY_DL_LIST_FOR_EACH_SAFE(item, next, &g_atiny_rpt_table) { atiny_rpt_list_t *data_node = (atiny_rpt_list_t *)item; if (atiny_is_uri_equal(&data_node->uri, uri)) { return data_node; } } return NULL; } static void atiny_free_list(atiny_dl_list *list, void(*free_data)(atiny_dl_list *node, void *param), void *param) { atiny_dl_list *item; atiny_dl_list *next; ATINY_DL_LIST_FOR_EACH_SAFE(item, next, list) { atiny_list_delete(item); if (free_data != NULL) { free_data(item, param); } lwm2m_free(item); } } static void atiny_visit_list(atiny_dl_list *list, void(*visit_data)(atiny_dl_list *node, void *param), void *param) { atiny_dl_list *item; atiny_dl_list *next; ATINY_DL_LIST_FOR_EACH_SAFE(item, next, list) { visit_data(item, param); } } static void atiny_clear_rpt_list_node_data(atiny_dl_list *node, void *result) { atiny_rpt_node_t *rpt_node = (atiny_rpt_node_t *)node; if (rpt_node->data.callback) { rpt_node->data.callback(rpt_node->data.type, rpt_node->data.cookie, (data_send_status_e)(long)result); } if (rpt_node->data.buf) { lwm2m_free(rpt_node->data.buf); rpt_node->data.buf = NULL; } } static void atiny_clear_rpt_list(atiny_dl_list *node, void *result) { atiny_rpt_list_t *rpt_list = (atiny_rpt_list_t *)node; atiny_free_list(&rpt_list->rpt_list, atiny_clear_rpt_list_node_data, result); } static void atiny_notify_stack_rpt_data_change(atiny_dl_list *node, void *context) { atiny_rpt_list_t *rpt_list = (atiny_rpt_list_t *)node; if (!atiny_list_empty(&rpt_list->rpt_list)) { ATINY_LOG(LOG_INFO, "data change cnt %d "URI_FORMAT, rpt_list->rpt_node_cnt, URI_LOG_PARAM(&rpt_list->uri)); lwm2m_resource_value_changed(context, &rpt_list->uri); } } int atiny_init_rpt(void) { atiny_list_init(&g_atiny_rpt_table); g_mutex = atiny_mutex_create(); if (NULL == g_mutex) { ATINY_LOG(LOG_ERR, "atiny_mutex_create fail"); return ATINY_RESOURCE_NOT_ENOUGH;; } return ATINY_OK; } int atiny_add_rpt_uri(const lwm2m_uri_t *uri, rpt_list_t *list) { atiny_rpt_list_t *rpt_list = NULL; int ret = ATINY_ARG_INVALID; if (NULL == uri) { ATINY_LOG(LOG_ERR, "null point"); return ATINY_ARG_INVALID; } if (NULL == list) { ATINY_LOG(LOG_ERR, "null point"); return ATINY_ARG_INVALID; } *list = NULL; atiny_mutex_lock(g_mutex); do { rpt_list = atiny_find_rpt_list(uri); if (rpt_list != NULL) { ATINY_LOG(LOG_ERR, "uri exist," URI_FORMAT, URI_LOG_PARAM(uri)); break; } rpt_list = lwm2m_malloc(sizeof(*rpt_list)); if (NULL == rpt_list) { ATINY_LOG(LOG_ERR, "lwm2m_malloc fail," URI_FORMAT, URI_LOG_PARAM(uri)); break; } memset(rpt_list, 0, sizeof(*rpt_list)); atiny_list_init(&rpt_list->rpt_list); memcpy(&rpt_list->uri, uri, sizeof(rpt_list->uri)); rpt_list->max_cnt = MAX_BUFFER_REPORT_CNT; atiny_list_insert_tail(&g_atiny_rpt_table, &rpt_list->node); ret = ATINY_OK; } while (0); atiny_mutex_unlock(g_mutex); *list = rpt_list; return ret; } int atiny_rm_rpt_uri(const lwm2m_uri_t *uri) { int ret = ATINY_ARG_INVALID; if (NULL == uri) { ATINY_LOG(LOG_ERR, "null point"); return ATINY_ARG_INVALID; } atiny_mutex_lock(g_mutex); do { atiny_rpt_list_t *rpt_list = NULL; rpt_list = atiny_find_rpt_list(uri); if (NULL == rpt_list) { ATINY_LOG(LOG_ERR, "uri not exit," URI_FORMAT, URI_LOG_PARAM(uri)); break; } atiny_list_delete(&rpt_list->node); atiny_free_list(&rpt_list->rpt_list, atiny_clear_rpt_list_node_data, (void *)NOT_SENT); lwm2m_free(rpt_list); ret = ATINY_OK; } while (0); atiny_mutex_unlock(g_mutex); return ret; } int atiny_dequeue_rpt_data(rpt_list_t rpt_list, data_report_t *data) { int ret = ATINY_RESOURCE_NOT_FOUND; if (NULL == rpt_list || (NULL == data)) { ATINY_LOG(LOG_ERR, "null point"); return ATINY_ARG_INVALID; } atiny_mutex_lock(g_mutex); do { atiny_rpt_node_t *data_node; if (atiny_list_empty(&rpt_list->rpt_list)) { ATINY_LOG(LOG_INFO, "dequeue empty rpt list"); break; } data_node = (atiny_rpt_node_t *)rpt_list->rpt_list.next; atiny_list_delete(&data_node->list); rpt_list->rpt_node_cnt--; memcpy((void *)data, (void *)&data_node->data, sizeof(*data)); lwm2m_free(data_node); ret = ATINY_OK; } while (0); atiny_mutex_unlock(g_mutex); return ret; } int atiny_queue_rpt_data(const lwm2m_uri_t *uri, const data_report_t *data) { int ret = ATINY_MALLOC_FAILED; if ((NULL == uri) || (NULL == data)) { ATINY_LOG(LOG_ERR, "null point"); return ATINY_ARG_INVALID; } atiny_mutex_lock(g_mutex); do { atiny_rpt_list_t *rpt_list; atiny_rpt_node_t *data_node; rpt_list = atiny_find_rpt_list(uri); if (NULL == rpt_list) { ATINY_LOG(LOG_INFO, "uri rpt list not exit," URI_FORMAT, URI_LOG_PARAM(uri)); ret = ATINY_RESOURCE_NOT_FOUND; break; } if (rpt_list->rpt_node_cnt >= rpt_list->max_cnt) { ATINY_LOG(LOG_INFO, "uri rpt exceed rpt cnt %d max cnt %d," URI_FORMAT, rpt_list->rpt_node_cnt, rpt_list->max_cnt, URI_LOG_PARAM(uri)); ret = ATINY_RESOURCE_NOT_ENOUGH; break; } data_node = lwm2m_malloc(sizeof(*data_node)); if (NULL == data_node) { ATINY_LOG(LOG_ERR, "malloc fail," URI_FORMAT, URI_LOG_PARAM(uri)); break; } memset((void *)&data_node->list, 0, sizeof(data_node->list)); memcpy((void *)&data_node->data, (void *)data, sizeof(data_node->data)); atiny_list_insert_tail(&rpt_list->rpt_list, &data_node->list); rpt_list->rpt_node_cnt++; ret = ATINY_OK; } while (0); atiny_mutex_unlock(g_mutex); return ret; } int atiny_clear_rpt_data(const lwm2m_uri_t *uri, int result) { int ret = ATINY_RESOURCE_NOT_FOUND; if (NULL == uri) { ATINY_LOG(LOG_ERR, "null point"); return ATINY_ARG_INVALID; } atiny_mutex_lock(g_mutex); do { atiny_rpt_list_t *rpt_list; rpt_list = atiny_find_rpt_list(uri); if (NULL == rpt_list) { ATINY_LOG(LOG_ERR, "uri rpt list not exit," URI_FORMAT, URI_LOG_PARAM(uri)); break; } atiny_free_list(&rpt_list->rpt_list, atiny_clear_rpt_list_node_data, (void *)result); rpt_list->rpt_node_cnt = 0; ret = ATINY_OK; } while (0); atiny_mutex_unlock(g_mutex); return ret; } int atiny_step_rpt(lwm2m_context_t *context) { atiny_mutex_lock(g_mutex); atiny_visit_list(&g_atiny_rpt_table, atiny_notify_stack_rpt_data_change, context); atiny_mutex_unlock(g_mutex); return ATINY_OK; } void atiny_destroy_rpt(void) { atiny_free_list(&g_atiny_rpt_table, atiny_clear_rpt_list, (void *)NOT_SENT); atiny_mutex_destroy(g_mutex); g_mutex = NULL; } int atiny_set_max_rpt_cnt(const lwm2m_uri_t *uri, uint32_t max_rpt_cnt) { int ret = ATINY_RESOURCE_NOT_FOUND; atiny_mutex_lock(g_mutex); do { atiny_rpt_list_t *rpt_list; rpt_list = atiny_find_rpt_list(uri); if (NULL == rpt_list) { ATINY_LOG(LOG_ERR, "uri rpt list not exit," URI_FORMAT, URI_LOG_PARAM(uri)); break; } rpt_list->max_cnt = max_rpt_cnt; ret = ATINY_OK; } while (0); atiny_mutex_unlock(g_mutex); return ret; } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/atiny_rpt.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef ATINY_RPT_H #define ATINY_RPT_H #include "atiny_lwm2m/agenttiny.h" #include "agent_list.h" #ifdef __cplusplus extern "C" { #endif #define URI_FORMAT "uri(flag:0x%x, objId:%d, instId:%d, resId:%d)" #define URI_LOG_PARAM(uri) (uri)->flag, (uri)->objectId, (uri)->instanceId, (uri)->resourceId ATINY_INLINE void get_instance_uri(uint16_t object_id, uint16_t instance_id, lwm2m_uri_t* uri) { if (uri == NULL) { return; } uri->flag = LWM2M_URI_FLAG_OBJECT_ID | LWM2M_URI_FLAG_INSTANCE_ID; uri->objectId = object_id; uri->instanceId = instance_id; uri->resourceId = 0; } ATINY_INLINE void get_resource_uri(uint16_t object_id, uint16_t instance_id, uint16_t resource_id, lwm2m_uri_t* uri) { if (uri == NULL) { return; } uri->flag = LWM2M_URI_FLAG_OBJECT_ID | LWM2M_URI_FLAG_INSTANCE_ID | LWM2M_URI_FLAG_RESOURCE_ID; uri->objectId = object_id; uri->instanceId = instance_id; uri->resourceId = resource_id; } struct _atiny_rpt_list_t; typedef struct _atiny_rpt_list_t* rpt_list_t; int atiny_init_rpt(void); int atiny_add_rpt_uri(const lwm2m_uri_t* uri, rpt_list_t* list); int atiny_rm_rpt_uri(const lwm2m_uri_t* uri); int atiny_dequeue_rpt_data(rpt_list_t rpt_list, data_report_t* data); int atiny_queue_rpt_data(const lwm2m_uri_t* uri, const data_report_t* data); int atiny_clear_rpt_data(const lwm2m_uri_t* uri, int result); int atiny_step_rpt(lwm2m_context_t* context); void atiny_destroy_rpt(void); int atiny_set_max_rpt_cnt(const lwm2m_uri_t* uri, uint32_t max_rpt_cnt); #ifdef __cplusplus } #endif #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/connection.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2015 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Christian Renz - Please refer to git log * *******************************************************************************/ #include #include "connection.h" #if defined (WITH_DTLS) #include "dtls_interface.h" #endif #include "sal/atiny_socket.h" #include "log/atiny_log.h" #include "object_comm.h" #define COAP_PORT "5683" #define COAPS_PORT "5684" static lwm2m_connection_err_notify_t g_connection_err_notify = NULL; static inline void inc_connection_stat(connection_t *connection, connection_err_e type) { static const uint16_t max_num[CONNECTION_ERR_MAX] = {MAX_SEND_ERR_NUM, MAX_RECV_ERR_NUM }; connection->errs[type]++; if(connection->errs[type] >= max_num[type]) { connection->errs[type] = 0; if(g_connection_err_notify) { g_connection_err_notify(connection->lwm2mH, type, connection->bootstrap_flag); } } } int connection_parse_host_ip(char *uri, char **parsed_host, char **parsed_port) { char *host; char *port; char *defaultport; if (uri == NULL) { ATINY_LOG(LOG_INFO, "uri is NULL!!!"); return COAP_500_INTERNAL_SERVER_ERROR; } //ATINY_LOG(LOG_INFO, "uri is %s\n", uri); // parse uri in the form "coaps://[host]:[port]" if (0 == strncmp(uri, "coaps://", strlen("coaps://"))) { host = uri + strlen("coaps://"); defaultport = COAPS_PORT; } else if (0 == strncmp(uri, "coap://", strlen("coap://"))) { host = uri + strlen("coap://"); defaultport = COAP_PORT; } else { ATINY_LOG(LOG_INFO, "come here1!!!"); return COAP_500_INTERNAL_SERVER_ERROR; } port = strrchr(host, ':'); if (port == NULL) { port = defaultport; } else { // remove brackets if (host[0] == '[') { host++; if (*(port - 1) == ']') { *(port - 1) = 0; } else { ATINY_LOG(LOG_INFO, "come here2!!!"); return COAP_500_INTERNAL_SERVER_ERROR; } } // split strings *port = 0; port++; } *parsed_host = host; *parsed_port = port; return COAP_NO_ERROR; } #ifdef LWM2M_BOOTSTRAP void connection_striger_server_initiated_bs(connection_t * sessionH) { (void)sessionH; (void)atiny_cmd_ioctl(ATINY_TRIGER_SERVER_INITIATED_BS, NULL, 0); } #endif #ifdef WITH_DTLS int connection_connect_dtls(connection_t *connP, security_instance_t *targetP, const char *host, const char *port, int client_or_server) { int ret; dtls_shakehand_info_s info; dtls_establish_info_s establish_info; establish_info.psk_or_cert = VERIFY_WITH_PSK; establish_info.udp_or_tcp = MBEDTLS_NET_PROTO_UDP; establish_info.v.p.psk = (const unsigned char *)targetP->secretKey; establish_info.v.p.psk_len = targetP->secretKeyLen; establish_info.v.p.psk_identity = (const unsigned char *)targetP->publicIdentity; connP->net_context = (void *)dtls_ssl_new(&establish_info, client_or_server); if (NULL == connP->net_context) { ATINY_LOG(LOG_INFO, "connP->ssl is NULL in connection_create"); return COAP_500_INTERNAL_SERVER_ERROR; } memset(&info, 0, sizeof(info)); info.client_or_server = client_or_server; info.finish_notify = NULL; info.step_notify = NULL; info.udp_or_tcp = MBEDTLS_NET_PROTO_UDP; info.psk_or_cert = VERIFY_WITH_PSK; #ifdef LWM2M_BOOTSTRAP info.step_notify = (void(*)(void *))lwm2m_step_striger_server_initiated_bs; info.param = (void(*)(void *))connP; #endif if (MBEDTLS_SSL_IS_CLIENT == client_or_server) { info.u.c.host = host; info.u.c.port = port; info.timeout = DTLS_UDP_CLIENT_SHAKEHAND_TIMEOUT; } else { #ifdef LWM2M_BOOTSTRAP info.timeout = targetP->clientHoldOffTime; info.u.s.local_port = port; timer_init(&connP->server_triger_timer, LWM2M_TRIGER_SERVER_MODE_INITIATED_TIME, (void(*)(void*))connection_striger_server_initiated_bs, connP); timer_start(&connP->server_triger_timer); #endif } ret = dtls_shakehand(connP->net_context, &info); #ifdef LWM2M_BOOTSTRAP timer_stop(&connP->server_triger_timer); #endif if (ret != 0) { ATINY_LOG(LOG_INFO, "ret is %d in connection_create", ret); dtls_ssl_destroy((mbedtls_ssl_context *)connP->net_context); connP->net_context = NULL; return COAP_500_INTERNAL_SERVER_ERROR; } connP->dtls_flag = true; return COAP_NO_ERROR; } #endif connection_t *connection_create(connection_t *connList, lwm2m_object_t *securityObj, int instanceId, lwm2m_context_t *lwm2mH, int client_or_server) { connection_t *connP = NULL; char *host; char *port; security_instance_t *targetP; char *uri = NULL; connection_t * ret = NULL; ATINY_LOG(LOG_INFO, "now come into connection_create!!!"); targetP = (security_instance_t *)LWM2M_LIST_FIND(securityObj->instanceList, instanceId); if (NULL == targetP || targetP->uri == NULL) { return NULL; } if (LWM2M_IS_CLIENT == client_or_server) { uri = atiny_strdup(targetP->uri); if (uri == NULL) { ATINY_LOG(LOG_INFO, "atiny_strdup null!!!"); goto fail; } if (connection_parse_host_ip(uri, &host, &port) != COAP_NO_ERROR) { goto fail; } } else { host = NULL; port = (char *)((targetP->securityMode != LWM2M_SECURITY_MODE_NONE) ? COAPS_PORT : COAP_PORT); } connP = (connection_t *)lwm2m_malloc(sizeof(connection_t)); if (connP == NULL) { ATINY_LOG(LOG_INFO, "connP is NULL!!!"); goto fail; } memset(connP, 0, sizeof(connection_t)); #ifdef WITH_DTLS if (targetP->securityMode != LWM2M_SECURITY_MODE_NONE) { if (connection_connect_dtls(connP, targetP, host, port, client_or_server) != COAP_NO_ERROR) { goto fail; } } else #endif { // no dtls session if (LWM2M_IS_CLIENT == client_or_server) { connP->net_context = atiny_net_connect(host, port, ATINY_PROTO_UDP); } else { connP->net_context = atiny_net_bind(host, port, ATINY_PROTO_UDP); #ifdef LWM2M_BOOTSTRAP if (connP->net_context) { connection_striger_server_initiated_bs(connP); timer_init(&connP->server_triger_timer, LWM2M_TRIGER_SERVER_MODE_INITIATED_TIME, (void(*)(void*))connection_striger_server_initiated_bs, connP); timer_start(&connP->server_triger_timer); } #endif } if (NULL == connP->net_context) { ATINY_LOG(LOG_INFO, "net_context is NULL in connection_create"); goto fail; } connP->dtls_flag = false; } connP->next = connList; connP->securityObj = securityObj; connP->securityInstId = instanceId; connP->lwm2mH = lwm2mH; connP->bootstrap_flag = targetP->isBootstrap; ret = connP; fail: if (uri) { lwm2m_free(uri); } if (ret == NULL && connP) { lwm2m_free(connP); } return ret; } void connection_free(connection_t *connP) { if(connP == NULL) { return; } #ifdef WITH_DTLS if (connP->dtls_flag == true) { dtls_ssl_destroy(connP->net_context); } else #endif { atiny_net_close(connP->net_context); } return; } void *lwm2m_connect_server(uint16_t secObjInstID, void *userData, bool isServer) { client_data_t *dataP; lwm2m_list_t *instance; connection_t *newConnP = NULL; lwm2m_object_t *securityObj; dataP = (client_data_t *)userData; securityObj = dataP->securityObjP; ATINY_LOG(LOG_INFO, "Now come into Connection creation in lwm2m_connect_server %d.\n", isServer); instance = LWM2M_LIST_FIND(dataP->securityObjP->instanceList, secObjInstID); if (instance == NULL) { return NULL; } newConnP = connection_create(dataP->connList, securityObj, instance->id, dataP->lwm2mH, isServer ? LWM2M_IS_SERVER : LWM2M_IS_CLIENT); if (newConnP == NULL) { ATINY_LOG(LOG_INFO, "Connection creation failed.\n"); return NULL; } ATINY_LOG(LOG_INFO, "Connection creation successfully in lwm2m_connect_server.\n"); dataP->connList = newConnP; return (void *)newConnP; } void lwm2m_close_connection(void *sessionH, void *userData) { client_data_t *app_data; connection_t *targetP; app_data = (client_data_t *)userData; targetP = (connection_t *)sessionH; #ifdef LWM2M_BOOTSTRAP timer_stop(&targetP->server_triger_timer); #endif if (targetP == app_data->connList) { app_data->connList = targetP->next; connection_free(targetP); lwm2m_free(targetP); } else { connection_t *parentP; parentP = app_data->connList; while (parentP != NULL && parentP->next != targetP) { parentP = parentP->next; } if (parentP != NULL) { parentP->next = targetP->next; connection_free(targetP); lwm2m_free(targetP); } } return; } int lwm2m_buffer_recv(void *sessionH, uint8_t *buffer, size_t length, uint32_t timeout) { connection_t *connP = (connection_t *) sessionH; int ret = -1; const int TIME_OUT = -2; timeout *= 1000; #ifdef WITH_DTLS if (connP->dtls_flag == true) { // security ret = dtls_read(connP->net_context, buffer, length, timeout); } else #endif { ret = atiny_net_recv_timeout(connP->net_context, buffer, length, timeout); } if((ret < 0) && (ret != TIME_OUT)) { inc_connection_stat(connP, CONNECTION_RECV_ERR); } else { connP->errs[CONNECTION_RECV_ERR] = 0; } return ret; } static bool connection_is_valid(void *user_data, void *session) { client_data_t *data = (client_data_t *)user_data; connection_t *conn; if (data == NULL || data->connList == NULL) { return false; } conn = data->connList; while(conn != NULL) { if (conn == session) { return true; } conn = conn->next; } return false; } uint8_t lwm2m_buffer_send(void *sessionH, uint8_t *buffer, size_t length, void *userdata) { connection_t *connP = (connection_t *) sessionH; int ret; /* should check the valid of the connection,because coap tranctions does not update the session */ if (connP == NULL || (!connection_is_valid(userdata, sessionH))) { ATINY_LOG(LOG_INFO, "#> failed sending %lu bytes, missing connection\r\n", (unsigned long)length); return COAP_500_INTERNAL_SERVER_ERROR ; } ATINY_LOG(LOG_INFO, "call connection_send in lwm2m_buffer_send, length is %d\n", length); #ifdef WITH_DTLS if (connP->dtls_flag == true) { // security ret = dtls_write(connP->net_context, buffer, length); } else #endif { ret = atiny_net_send(connP->net_context, buffer, length); } if(ret >= 0) { connP->errs[CONNECTION_SEND_ERR] = 0; return COAP_NO_ERROR; } else { inc_connection_stat(connP, CONNECTION_SEND_ERR); return COAP_500_INTERNAL_SERVER_ERROR; } } bool lwm2m_session_is_equal(void *session1, void *session2, void *userData) { return (session1 == session2); } void lwm2m_register_connection_err_notify(lwm2m_connection_err_notify_t nofiy) { g_connection_err_notify = nofiy; } #ifdef LWM2M_BOOTSTRAP void lwm2m_step_striger_server_initiated_bs(connection_t * sessionH) { if (sessionH == NULL) { return; } timer_step(&sessionH->server_triger_timer); } void lwm2m_stop_striger_server_initiated_bs(connection_t * sessionH) { if (sessionH == NULL) { return; } timer_stop(&sessionH->server_triger_timer); } bool lwm2m_is_sec_obj_uri_valid(uint16_t secObjInstID, void *userData) { client_data_t *dataP; lwm2m_object_t *securityObj; dataP = (client_data_t *)userData; securityObj = dataP->securityObjP; security_instance_t *targetP; targetP = (security_instance_t *)LWM2M_LIST_FIND(securityObj->instanceList, secObjInstID); return !(((NULL == targetP) || (targetP->uri == NULL) || (targetP->uri[0] == '\0'))); } #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/connection.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2015 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Simon Bernard - initial API and implementation * Christian Renz - Please refer to git log * *******************************************************************************/ #ifndef DTLS_CONN_H_ #define DTLS_CONN_H_ #include #include #include #include "util_timer.h" #include "liblwm2m.h" // after 40sec of inactivity we rehandshake #define DTLS_NAT_TIMEOUT 40 #define LWM2M_IS_CLIENT 0 #define LWM2M_IS_SERVER 1 /* timeout for udp client shakehand,the unit is second */ #ifndef DTLS_UDP_CLIENT_SHAKEHAND_TIMEOUT #define DTLS_UDP_CLIENT_SHAKEHAND_TIMEOUT 60 #endif typedef enum { CONNECTION_SEND_ERR, CONNECTION_RECV_ERR, CONNECTION_ERR_MAX } connection_err_e; typedef struct _connection_t { struct _connection_t* next; void* net_context; lwm2m_object_t* securityObj; int securityInstId; uint16_t dtls_flag; uint16_t bootstrap_flag; lwm2m_context_t* lwm2mH; uint16_t errs[CONNECTION_ERR_MAX]; #ifdef LWM2M_BOOTSTRAP util_timer_t server_triger_timer; #endif } connection_t; typedef void (*lwm2m_connection_err_notify_t)(lwm2m_context_t* context, connection_err_e err_type, bool boostrap_flag); int lwm2m_buffer_recv(void* sessionH, uint8_t* buffer, size_t length, uint32_t timeout); void lwm2m_register_connection_err_notify(lwm2m_connection_err_notify_t nofiy); #ifdef LWM2M_BOOTSTRAP void lwm2m_step_striger_server_initiated_bs(connection_t * sessionH); void lwm2m_stop_striger_server_initiated_bs(connection_t * sessionH); bool lwm2m_is_sec_obj_uri_valid(uint16_t secObjInstID, void *userData); #endif #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/firmware_update.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "internals.h" #include "atiny_lwm2m/agenttiny.h" #include "log/atiny_log.h" #include "ota/package.h" #include "firmware_update.h" #define FW_BLOCK_SIZE (512) #define COAP_PROTO_PREFIX "coap://" #define COAPS_PROTO_PREFIX "coaps://" typedef struct fw_update_record { uint8_t in_use; uint8_t block_more; uint16_t block_size; uint32_t block_num; uint32_t block_offset; uint32_t uri_len; char *uri; } fw_update_record_t; static char *g_ota_uri = NULL; static pack_storage_device_api_s *g_fota_storage_device = NULL; static fw_update_record_t g_fw_update_record = {0}; static firmware_update_notify g_firmware_update_notify = NULL; static void *g_firmware_update_notify_param = NULL; static void firmware_download_reply(lwm2m_transaction_t *transacP, void *message) { coap_packet_t *packet = (coap_packet_t *)message; lwm2m_context_t *contextP = (lwm2m_context_t *)(transacP->userData); lwm2m_transaction_t *transaction; uint32_t len = 0; uint32_t block_num = 0; uint8_t block2_more = 0; uint16_t block_size = FW_BLOCK_SIZE; uint32_t block_offset = 0; int ret = 0; if(NULL == message) { ATINY_LOG(LOG_INFO, "transaction timeout"); goto failed_exit; } if(1 != coap_get_header_block2(message, &block_num, &block2_more, &block_size, &block_offset)) { ATINY_LOG(LOG_ERR, "coap_get_header_block2 failed"); goto failed_exit; } ATINY_LOG(LOG_ERR, "block_num : %lu, block2_more : %lu, block_offset : %lu, payload_len is %u", block_num, (uint32_t)block2_more, block_offset, packet->payload_len); if(0 == block_num) { g_fw_update_record.in_use = 1; } g_fw_update_record.block_size = block_size; g_fw_update_record.block_num = block_num; g_fw_update_record.block_offset = block_offset; g_fw_update_record.block_more = block2_more; len = (uint32_t)(packet->payload_len); if(g_fota_storage_device && g_fota_storage_device->write_software) { ret = g_fota_storage_device->write_software(g_fota_storage_device, block_offset, packet->payload, len); if(ret != 0) goto failed_exit; } else if(NULL == g_fota_storage_device) ATINY_LOG(LOG_ERR, "g_fota_storage_device NULL"); else ATINY_LOG(LOG_ERR, "g_fota_storage_device->write_software NULL"); len = block_offset + (uint32_t)(packet->payload_len); if(block2_more) { transaction = transaction_new(transacP->peerH, COAP_GET, NULL, NULL, contextP->nextMID++, 4, NULL); if(!transaction) { ATINY_LOG(LOG_ERR, "transaction_new failed"); goto failed_exit; } ret = coap_set_header_uri_path(transaction->message, g_ota_uri); if(ret < 0 || NULL == transaction->message->uri_path) { transaction_free(transaction); goto failed_exit; } //coap_set_header_uri_query(transaction->message, query); ret = coap_set_header_block2(transaction->message, g_fw_update_record.block_num + 1, 0, g_fw_update_record.block_size); if(ret < 0) { transaction_free(transaction); goto failed_exit; } ATINY_LOG(LOG_DEBUG, "get next : %lu", block_num + 1); transaction->callback = firmware_download_reply; transaction->userData = (void *)contextP; contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transaction); if(transaction_send(contextP, transaction) != 0) { ATINY_LOG(LOG_ERR, "transaction_send failed"); goto failed_exit; } } else { ret = ATINY_ERR; if(g_fota_storage_device && g_fota_storage_device->write_software_end) ret = g_fota_storage_device->write_software_end(g_fota_storage_device, PACK_DOWNLOAD_OK, len); else if(NULL == g_fota_storage_device) ATINY_LOG(LOG_ERR, "g_fota_storage_device NULL"); else ATINY_LOG(LOG_ERR, "g_fota_storage_device->write_software_end NULL"); ATINY_LOG(LOG_ERR, "g_firmware_update_notify FIRMWARE_UPDATE_RST_SUCCESS, write end ret %d", ret); if(g_firmware_update_notify) g_firmware_update_notify((ret == ATINY_OK) ? FIRMWARE_UPDATE_RST_SUCCESS : FIRMWARE_UPDATE_RST_FAILED, g_firmware_update_notify_param); ATINY_LOG(LOG_ERR, "download success, total size : %lu, write end ret %d", len, ret); } return; failed_exit: if(g_fota_storage_device && g_fota_storage_device->write_software_end) (void)g_fota_storage_device->write_software_end(g_fota_storage_device, PACK_DOWNLOAD_FAIL, len); else if(NULL == g_fota_storage_device) ATINY_LOG(LOG_ERR, "g_fota_storage_device NULL"); else ATINY_LOG(LOG_ERR, "g_fota_storage_device->write_software_end NULL"); ATINY_LOG(LOG_INFO, "g_firmware_update_notify FIRMWARE_UPDATE_RST_FAILED"); if(g_firmware_update_notify) g_firmware_update_notify(FIRMWARE_UPDATE_RST_FAILED, g_firmware_update_notify_param); return; } static int record_fw_uri(char *uri, int uri_len) { if(!uri || *uri == '\0' || uri_len <= 0) { return -1; } g_fw_update_record.uri = (char *)lwm2m_malloc(uri_len + 1); if(NULL == g_fw_update_record.uri) { ATINY_LOG(LOG_ERR, "lwm2m_malloc failed"); return -1; } memcpy(g_fw_update_record.uri, uri, uri_len); g_fw_update_record.uri[uri_len] = '\0'; g_fw_update_record.uri_len = uri_len; return 0; } static int update_uri_info(char *uri, int uri_len, unsigned char *update_flag) { int ret = -1; if(!uri || *uri == '\0' || uri_len <= 0 || !update_flag) { return -1; } if(1 == g_fw_update_record.in_use && NULL != g_fw_update_record.uri && 0 == memcmp(g_fw_update_record.uri, uri, uri_len)) { *update_flag = 0; return 0; } else { if(NULL != g_fw_update_record.uri) { lwm2m_free(g_fw_update_record.uri); g_fw_update_record.uri = NULL; } memset(&g_fw_update_record, 0x0, sizeof(g_fw_update_record)); ret = record_fw_uri(uri, uri_len); *update_flag = 1; if(0 != ret) { ATINY_LOG(LOG_ERR, "record_fw_uri failed"); return -1; } return 0; } } void set_firmware_update_notify(firmware_update_notify notify_cb, void *param) { g_firmware_update_notify = notify_cb; g_firmware_update_notify_param = param; return; } int parse_firmware_uri(char *uri, int uri_len) { char *char_p, *path; int path_len, proto_len; if(!uri || *uri == '\0' || uri_len <= 0) { return -1; } if(0 == strncmp(uri, COAP_PROTO_PREFIX, strlen(COAP_PROTO_PREFIX))) proto_len = strlen(COAP_PROTO_PREFIX); else if(0 == strncmp(uri, COAPS_PROTO_PREFIX, strlen(COAPS_PROTO_PREFIX))) proto_len = strlen(COAPS_PROTO_PREFIX); else { ATINY_LOG(LOG_ERR, "unsupported proto"); return -1; } //暂不考虑query char_p = uri + proto_len; if(*char_p == '\0') // eg. just "coap://" return -1; path = strchr(char_p, '/'); if(NULL == path) return -1; path_len = uri_len - (path - uri); g_ota_uri = (char *)lwm2m_malloc(path_len + 1); if(!g_ota_uri) { ATINY_LOG(LOG_ERR, "lwm2m_malloc failed"); return -1; } /*lint -esym(668,memcpy) */ memcpy(g_ota_uri, path, path_len); g_ota_uri[path_len] = '\0'; return 0; } int start_firmware_download(lwm2m_context_t *contextP, char *uri, pack_storage_device_api_s *storage_device_p) { lwm2m_transaction_t *transaction; unsigned char update_flag = 0; int ret = -1; int uri_len; lwm2m_server_t *server; if(!contextP || !uri || *uri == '\0' || !storage_device_p) { ATINY_LOG(LOG_ERR, "invalid params"); return -1; } ATINY_LOG(LOG_ERR, "start download"); g_fota_storage_device = storage_device_p; uri_len = strlen(uri); server = registration_get_registered_server(contextP); if(NULL == server) { ATINY_LOG(LOG_ERR, "registration_get_registered_server failed"); return -1; } ret = update_uri_info(uri, uri_len, &update_flag); if(0 != ret) { ;// continue to although update_uri_info failed } ATINY_LOG(LOG_DEBUG, "update_flag = %u", update_flag); if(!(0 == update_flag && NULL != g_ota_uri)) { if(NULL != g_ota_uri) { lwm2m_free(g_ota_uri); g_ota_uri = NULL; } ret = parse_firmware_uri(uri, uri_len); if(0 != ret) { ATINY_LOG(LOG_ERR, "parse_firmware_uri failed"); return -1; } } transaction = transaction_new(server->sessionH, COAP_GET, NULL, NULL, contextP->nextMID++, 4, NULL); if(!transaction) { ATINY_LOG(LOG_ERR, "transaction_new failed"); return -1; } ret = coap_set_header_uri_path(transaction->message, g_ota_uri); if(ret < 0 || NULL == transaction->message->uri_path) { transaction_free(transaction); return -1; } //coap_set_header_uri_query(transaction->message, query); if(1 == g_fw_update_record.in_use) { ret = coap_set_header_block2(transaction->message, g_fw_update_record.block_num + 1, 0, g_fw_update_record.block_size); } else { ret = coap_set_header_block2(transaction->message, 0, 0, FW_BLOCK_SIZE); } if(ret != 1) { transaction_free(transaction); return -1; } transaction->callback = firmware_download_reply; transaction->userData = (void *)contextP; contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transaction); if(transaction_send(contextP, transaction) != 0) { ATINY_LOG(LOG_ERR, "transaction_send failed"); return -1; } return 0; } void clean_firmware_record(void) { if(NULL != g_ota_uri) { lwm2m_free(g_ota_uri); g_ota_uri = NULL; } if(NULL != g_fw_update_record.uri) { lwm2m_free(g_fw_update_record.uri); g_fw_update_record.uri = NULL; } } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/firmware_update.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef __FIRMWARE_UPDATE_H__ #define __FIRMWARE_UPDATE_H__ typedef enum firmware_update_rst { FIRMWARE_UPDATE_RST_SUCCESS = 0, FIRMWARE_UPDATE_RST_FAILED, FIRMWARE_UPDATE_RST_MAX }firmware_update_rst_e; typedef void (*firmware_update_notify)(firmware_update_rst_e rst, void *param); void set_firmware_update_notify(firmware_update_notify notify_cb, void *param); int start_firmware_download(lwm2m_context_t *contextP, char *uri, pack_storage_device_api_s *storage_device_p); void clean_firmware_record(void); #endif /* __FIRMWARE_UPDATE_H__ */ ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/object_access_control.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2015 Bosch Software Innovations GmbH Germany. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - please refer to git log * ******************************************************************************/ /* * This "Access Control" object is optional and multiple instantiated * * Resources: * * Name | ID | Oper. | Inst. | Mand.| Type | Range | Units | * ---------------------+----+-------+-------+------+---------+-------+-------+ * Object ID | 0 | R | Single| Yes | Integer |1-65534| | * Object instance ID | 1 | R | Single| Yes | Integer |0-65535| | * ACL | 2 | RW | Multi.| No | Integer | 16bit | | * Access Control Owner | 3 | RW | Single| Yes | Integer |0-65535| | */ #include "internals.h" #include "object_comm.h" #include // Resource Id's: #define RES_M_OBJECT_ID 0 #define RES_M_OBJECT_INSTANCE_ID 1 #define RES_O_ACL 2 #define RES_M_ACCESS_CONTROL_OWNER 3 #define MAX_DATA_VAL 65535 typedef struct acc_ctrl_ri_s { // linked list: struct acc_ctrl_ri_s *next; // matches lwm2m_list_t::next uint16_t resInstId; // matches lwm2m_list_t::id, ..serverID // resource data: uint16_t accCtrlValue; } acc_ctrl_ri_t; typedef struct acc_ctrl_oi_s { //linked list: struct acc_ctrl_oi_s *next; // matches lwm2m_list_t::next uint16_t objInstId; // matches lwm2m_list_t::id // resources uint16_t objectId; uint16_t objectInstId; uint16_t accCtrlOwner; acc_ctrl_ri_t *accCtrlValList; } acc_ctrl_oi_t; static uint8_t prv_set_tlv(lwm2m_data_t *dataP, acc_ctrl_oi_t *accCtrlOiP) { switch (dataP->id) { case RES_M_OBJECT_ID: lwm2m_data_encode_int(accCtrlOiP->objectId, dataP); return COAP_205_CONTENT; case RES_M_OBJECT_INSTANCE_ID: lwm2m_data_encode_int(accCtrlOiP->objectInstId, dataP); return COAP_205_CONTENT; case RES_O_ACL: { int ri; acc_ctrl_ri_t *accCtrlRiP; for (accCtrlRiP = accCtrlOiP->accCtrlValList, ri = 0; accCtrlRiP != NULL; accCtrlRiP = accCtrlRiP->next, ri++); if (ri == 0) // no values! { return COAP_404_NOT_FOUND; } else { lwm2m_data_t *subTlvP = lwm2m_data_new(ri); if (subTlvP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; for (accCtrlRiP = accCtrlOiP->accCtrlValList, ri = 0; accCtrlRiP != NULL; accCtrlRiP = accCtrlRiP->next, ri++) { subTlvP[ri].id = accCtrlRiP->resInstId; lwm2m_data_encode_int(accCtrlRiP->accCtrlValue, &subTlvP[ri]); } lwm2m_data_encode_instances(subTlvP, ri, dataP); return COAP_205_CONTENT; } } case RES_M_ACCESS_CONTROL_OWNER: lwm2m_data_encode_int(accCtrlOiP->accCtrlOwner, dataP); return COAP_205_CONTENT; default: return COAP_404_NOT_FOUND ; } } static uint8_t prv_read(uint16_t instanceId, int *numDataP, lwm2m_data_t **dataArrayP, lwm2m_data_cfg_t *dataCfg, lwm2m_object_t *objectP) { uint8_t result; int ri, ni; // multi-instance object: search instance acc_ctrl_oi_t *accCtrlOiP = (acc_ctrl_oi_t *)lwm2m_list_find(objectP->instanceList, instanceId); if (accCtrlOiP == NULL) { return COAP_404_NOT_FOUND ; } // is the server asking for the full object ? if (*numDataP == 0) { uint16_t resList[] = { RES_M_OBJECT_ID, RES_M_OBJECT_INSTANCE_ID, RES_O_ACL, // prv_set_tlv will return COAP_404_NOT_FOUND w/o values! RES_M_ACCESS_CONTROL_OWNER }; int nbRes = sizeof(resList) / sizeof(uint16_t); *dataArrayP = lwm2m_data_new(nbRes); if (*dataArrayP == NULL) return COAP_500_INTERNAL_SERVER_ERROR ; *numDataP = nbRes; for (ri = 0; ri < nbRes; ri++) { (*dataArrayP)[ri].id = resList[ri]; } } ni = ri = 0; do { result = prv_set_tlv((*dataArrayP) + ni, accCtrlOiP); if (result == COAP_404_NOT_FOUND) { ri++; if (*numDataP > 1) result = COAP_205_CONTENT; } else if (ri > 0) // copy new one by ri skipped ones in front { (*dataArrayP)[ni - ri] = (*dataArrayP)[ni]; } ni++; } while (ni < *numDataP && result == COAP_205_CONTENT); *numDataP = ni - ri; return result; } static bool prv_add_ac_val(acc_ctrl_oi_t *accCtrlOiP, uint16_t acResId, uint16_t acValue) { bool ret = false; acc_ctrl_ri_t *accCtrlRiP; accCtrlRiP = (acc_ctrl_ri_t *)lwm2m_malloc(sizeof(acc_ctrl_ri_t)); if (accCtrlRiP == NULL) { return ret; } else { memset(accCtrlRiP, 0, sizeof(acc_ctrl_ri_t)); accCtrlRiP->resInstId = acResId; accCtrlRiP->accCtrlValue = acValue; accCtrlOiP->accCtrlValList = (acc_ctrl_ri_t *) LWM2M_LIST_ADD(accCtrlOiP->accCtrlValList, accCtrlRiP); ret = true; } return ret; } static uint8_t prv_write_resources(uint16_t instanceId, int numData, lwm2m_data_t *tlvArray, lwm2m_object_t *objectP, bool doCreate) { int i; uint8_t result = COAP_NO_ERROR; int64_t value; lwm2m_data_t *subTlvArray; int ri; acc_ctrl_oi_t *accCtrlOiP = (acc_ctrl_oi_t *) lwm2m_list_find(objectP->instanceList, instanceId); if (NULL == accCtrlOiP) return COAP_404_NOT_FOUND ; i = 0; do { switch (tlvArray[i].id) { case RES_M_OBJECT_ID: if (doCreate == false) { result = COAP_405_METHOD_NOT_ALLOWED; } else { if (1 != lwm2m_data_decode_int(&tlvArray[i], &value)) { result = COAP_400_BAD_REQUEST; } else if (value < 1 || value > 65534) { result = COAP_406_NOT_ACCEPTABLE; } else { accCtrlOiP->objectId = value; result = COAP_204_CHANGED; } } break; case RES_M_OBJECT_INSTANCE_ID: if (doCreate == false) { result = COAP_405_METHOD_NOT_ALLOWED; } else { if (1 != lwm2m_data_decode_int(&tlvArray[i], &value)) { result = COAP_400_BAD_REQUEST; } else if (value < 0 || value > MAX_DATA_VAL) { result = COAP_406_NOT_ACCEPTABLE; } else { accCtrlOiP->objectInstId = value; result = COAP_204_CHANGED; } } break; case RES_O_ACL: { if (tlvArray[i].type != LWM2M_TYPE_MULTIPLE_RESOURCE) { result = COAP_400_BAD_REQUEST; } else { // MR-Write: Replace-implementation variant only // see LWM2M-TS:5.4.3 (wakaama has no part-update switch) // 1st: save accValueList! acc_ctrl_ri_t *acValListSave = accCtrlOiP->accCtrlValList; accCtrlOiP->accCtrlValList = NULL; subTlvArray = tlvArray[i].value.asChildren.array; if (tlvArray[i].value.asChildren.count == 0) { result = COAP_204_CHANGED; } else if (subTlvArray == NULL) { result = COAP_400_BAD_REQUEST; } else { for (ri = 0; ri < tlvArray[i].value.asChildren.count; ri++) { if (1 != lwm2m_data_decode_int(&subTlvArray[ri], &value)) { result = COAP_400_BAD_REQUEST; break; } else if (value < 0 || value > 0xFFFF) { result = COAP_406_NOT_ACCEPTABLE; break; } else if (!prv_add_ac_val(accCtrlOiP, subTlvArray[ri].id, (uint16_t)value)) { result = COAP_500_INTERNAL_SERVER_ERROR; break; } else { result = COAP_204_CHANGED; } } } if (result != COAP_204_CHANGED) { // free pot. partial created new ones LWM2M_LIST_FREE(accCtrlOiP->accCtrlValList); // restore old values: accCtrlOiP->accCtrlValList = acValListSave; } else { // final free saved value list LWM2M_LIST_FREE(acValListSave); } } } break; case RES_M_ACCESS_CONTROL_OWNER: { if (1 == lwm2m_data_decode_int(tlvArray + i, &value)) { if (value >= 0 && value <= MAX_DATA_VAL) { accCtrlOiP->accCtrlOwner = value; result = COAP_204_CHANGED; } else { result = COAP_406_NOT_ACCEPTABLE; } } else { result = COAP_400_BAD_REQUEST; } } break; default: return COAP_404_NOT_FOUND ; } i++; } while (i < numData && result == COAP_204_CHANGED ); return result; } static uint8_t prv_write(uint16_t instanceId, int numData, lwm2m_data_t *tlvArray, lwm2m_object_t *objectP) { return prv_write_resources(instanceId, numData, tlvArray, objectP, false); } static uint8_t prv_delete(uint16_t id, lwm2m_object_t *objectP) { acc_ctrl_oi_t *targetP; objectP->instanceList = lwm2m_list_remove(objectP->instanceList, id, (lwm2m_list_t **)&targetP); if (NULL == targetP) return COAP_404_NOT_FOUND; LWM2M_LIST_FREE(targetP->accCtrlValList); lwm2m_free(targetP); return COAP_202_DELETED; } static uint8_t prv_create(uint16_t objInstId, int numData, lwm2m_data_t *tlvArray, lwm2m_object_t *objectP) { acc_ctrl_oi_t *targetP; uint8_t result; targetP = (acc_ctrl_oi_t *)lwm2m_malloc(sizeof(acc_ctrl_oi_t)); if (NULL == targetP) return COAP_500_INTERNAL_SERVER_ERROR; memset(targetP, 0, sizeof(acc_ctrl_oi_t)); targetP->objInstId = objInstId; objectP->instanceList = LWM2M_LIST_ADD(objectP->instanceList, targetP); result = prv_write_resources(objInstId, numData, tlvArray, objectP, true); if (result != COAP_204_CHANGED) { (void)prv_delete(objInstId, objectP); } else { result = COAP_201_CREATED; } return result; } /* * Create an empty multiple instance LWM2M Object: Access Control */ lwm2m_object_t *acc_ctrl_create_object(void) { /* * The acc_ctrl_create_object() function creates an empty object * and returns a pointer to the structure that represents it. */ lwm2m_object_t *accCtrlObj = NULL; accCtrlObj = (lwm2m_object_t *) lwm2m_malloc(sizeof(lwm2m_object_t)); if (NULL != accCtrlObj) { memset(accCtrlObj, 0, sizeof(lwm2m_object_t)); /* * It assign his unique object ID * The 2 is the standard ID for the optional object "Access Control". */ accCtrlObj->objID = LWM2M_ACL_OBJECT_ID; // Init callbacks, empty instanceList! accCtrlObj->readFunc = prv_read; accCtrlObj->writeFunc = prv_write; accCtrlObj->createFunc = prv_create; accCtrlObj->deleteFunc = prv_delete; } return accCtrlObj; } void acl_ctrl_free_object(lwm2m_object_t *objectP) { acc_ctrl_oi_t *accCtrlOiT; acc_ctrl_oi_t *accCtrlOiP = (acc_ctrl_oi_t *)objectP->instanceList; while (accCtrlOiP != NULL) { // first free acl (multiple resource!): LWM2M_LIST_FREE(accCtrlOiP->accCtrlValList); accCtrlOiT = accCtrlOiP; accCtrlOiP = accCtrlOiP->next; lwm2m_free(accCtrlOiT); } lwm2m_free(objectP); } bool acc_ctrl_obj_add_inst (lwm2m_object_t *accCtrlObjP, uint16_t instId, uint16_t acObjectId, uint16_t acObjInstId, uint16_t acOwner) { bool ret = false; if (NULL == accCtrlObjP) { return ret; } else { // create an access control object instance acc_ctrl_oi_t *accCtrlOiP; accCtrlOiP = (acc_ctrl_oi_t *)lwm2m_malloc(sizeof(acc_ctrl_oi_t)); if (NULL == accCtrlOiP) { return ret; } else { memset(accCtrlOiP, 0, sizeof(acc_ctrl_oi_t)); // list: key accCtrlOiP->objInstId = instId; // object instance data: accCtrlOiP->objectId = acObjectId; accCtrlOiP->objectInstId = acObjInstId; accCtrlOiP->accCtrlOwner = acOwner; accCtrlObjP->instanceList = LWM2M_LIST_ADD(accCtrlObjP->instanceList, accCtrlOiP); ret = true; } } return ret; } bool acc_ctrl_oi_add_ac_val (lwm2m_object_t *accCtrlObjP, uint16_t instId, uint16_t acResId, uint16_t acValue) { bool ret = false; acc_ctrl_oi_t *accCtrlOiP = (acc_ctrl_oi_t *) lwm2m_list_find(accCtrlObjP->instanceList, instId); if (NULL == accCtrlOiP) return ret; return prv_add_ac_val (accCtrlOiP, acResId, acValue); } static acc_ctrl_oi_t *prv_get_acc_instance(acc_ctrl_oi_t *accCtrlOiP, uint16_t objId, uint16_t instId) { acc_ctrl_oi_t *itor = accCtrlOiP; while (itor) { if (itor->objectId == objId && itor->objectInstId == instId) { return itor; } itor = itor->next; } return NULL; } static acc_ctrl_ri_t *prv_get_acl_instance(acc_ctrl_ri_t *accCtrlRiP, uint16_t serverId) { acc_ctrl_ri_t *targetP; targetP = (acc_ctrl_ri_t *)LWM2M_LIST_FIND(accCtrlRiP, serverId); if (NULL == targetP) { targetP = (acc_ctrl_ri_t *)LWM2M_LIST_FIND(accCtrlRiP, 0); } return targetP; } static inline bool prv_auth_match(OBJ_ACC_OPERATE op, uint16_t auth_op) { return auth_op & (0x01 << op); } static bool prv_check_instance_auth(acc_ctrl_oi_t *accCtrlOiP, uint16_t objId, uint16_t instId, uint16_t serverId, OBJ_ACC_OPERATE op) { acc_ctrl_oi_t *targetP; acc_ctrl_ri_t *accCtrlRiP; targetP = prv_get_acc_instance(accCtrlOiP, objId, instId); if (NULL == targetP) { return false; } accCtrlRiP = prv_get_acl_instance(targetP->accCtrlValList, serverId); if (NULL == accCtrlRiP) { return targetP->accCtrlOwner == serverId; } return prv_auth_match(op, accCtrlRiP->accCtrlValue); } static uint8_t prv_acc_self_auth_check(acc_ctrl_oi_t *accCtrlOiP, lwm2m_uri_t *uri, OBJ_ACC_OPERATE op, uint16_t serverId) { acc_ctrl_oi_t *targetP; if (LWM2M_URI_IS_SET_INSTANCE(uri)) { targetP = (acc_ctrl_oi_t *)LWM2M_LIST_FIND(accCtrlOiP, uri->instanceId); if (NULL != targetP && targetP->accCtrlOwner == serverId) { return COAP_NO_ERROR; } else { return COAP_401_UNAUTHORIZED; } } else { targetP = accCtrlOiP; while (targetP) { if (targetP->accCtrlOwner != serverId) { return COAP_401_UNAUTHORIZED; } targetP = targetP->next; } return COAP_NO_ERROR; } } static uint8_t prv_pre_auth_check(acc_ctrl_oi_t *accCtrlOiP, lwm2m_uri_t *uri, OBJ_ACC_OPERATE op, uint16_t serverId) { if (OBJ_ACC_CREATE == op) { if (!prv_check_instance_auth(accCtrlOiP, uri->objectId, MAX_DATA_VAL, serverId, op)) { return COAP_401_UNAUTHORIZED; } return COAP_NO_ERROR; } else if (OBJ_ACC_DISCOVER == op) { return COAP_NO_ERROR; } else if (uri->objectId == LWM2M_ACL_OBJECT_ID) { return prv_acc_self_auth_check(accCtrlOiP, uri, op, serverId); } else { if (LWM2M_URI_IS_SET_INSTANCE(uri)) { if (!prv_check_instance_auth(accCtrlOiP, uri->objectId, uri->instanceId, serverId, op)) { return COAP_401_UNAUTHORIZED; } } } return COAP_NO_ERROR; } static uint8_t prv_post_action_check(lwm2m_uri_t *uri, OBJ_ACC_OPERATE op) { if (LWM2M_URI_IS_SET_RESOURCE(uri)) { return COAP_NO_ERROR; } else if (LWM2M_URI_IS_SET_INSTANCE(uri)) { if (OBJ_ACC_EXCUTE == op) { return COAP_405_METHOD_NOT_ALLOWED; } else { /* * For the write operation, check whether the resources * can be written or not, is in the write operation of * the specific object. */ return COAP_NO_ERROR; } } else { if (OBJ_ACC_WRITE_ATTR == op || OBJ_ACC_CREATE == op) { return COAP_NO_ERROR; } else if (OBJ_ACC_NOTIFY == op || OBJ_ACC_READ == op || OBJ_ACC_OBSERVE == op) { /* * We should do the auth check in object_read interface * and just ignore here. */ return COAP_NO_ERROR; } else { return COAP_405_METHOD_NOT_ALLOWED; } } } static int prv_get_srv_cnt(lwm2m_server_t *serverP) { lwm2m_server_t *itor = serverP; int cnt = 0; while (itor) { if (!itor->dirty) { ++cnt; } itor = itor->next; } return cnt; } uint8_t acc_auth_operate(lwm2m_context_t *contextP, lwm2m_uri_t *uri, OBJ_ACC_OPERATE op, uint16_t serverId) { uint8_t ret; lwm2m_object_t *accCtrlObjP; acc_ctrl_oi_t *accCtrlOiP; if (prv_get_srv_cnt(contextP->serverList) <= 1) { return COAP_NO_ERROR; } if (0 == serverId) { return COAP_NO_ERROR; } accCtrlObjP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, LWM2M_ACL_OBJECT_ID); if (NULL == accCtrlObjP) { return COAP_401_UNAUTHORIZED; } accCtrlOiP = (acc_ctrl_oi_t *)(accCtrlObjP->instanceList); if (NULL == accCtrlOiP) { return COAP_401_UNAUTHORIZED; } if ((ret = prv_pre_auth_check(accCtrlOiP, uri, op, serverId)) != COAP_NO_ERROR) { return ret; } if ((ret = prv_post_action_check(uri, op)) != COAP_NO_ERROR) { return ret; } return COAP_NO_ERROR; } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/object_binary_app_data_container.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /* * Implements an object for binary_app_data_container purpose * * Multiple * Object | ID | Instances | Mandatoty | * binary_app_data_container | 19 | Yes | No | * * Resources: * Supported Multiple * Name | ID | Operations | Instances | Mandatory | Type | Range | Units | Description | * Data | 0 | R/W | No | Yes | Opaque | | | | * */ #include "object_comm.h" #include "atiny_rpt.h" #include "log/atiny_log.h" #define PRV_TLV_BUFFER_SIZE 64 #define MIN_SAVE_CNT 1 #define BINARY_APP_DATA_OBJECT_INSTANCE_NUM 2 /* * Multiple instance objects can use userdata to store data that will be shared between the different instances. * The lwm2m_object_t object structure - which represent every object of the liblwm2m as seen in the single instance * object - contain a chained list called instanceList with the object specific structure plat_instance_t: */ typedef struct _prv_instance_ { /* * The first two are mandatories and represent the pointer to the next instance and the ID of this one. The rest * is the instance scope user data (uint8_t test in this case) */ struct _prv_instance_ *next; // matches lwm2m_list_t::next uint16_t shortID; // matches lwm2m_list_t::id rpt_list_t header; uint8_t test; double dec; #define OPAR_NUM 5 uint8_t opaq[OPAR_NUM]; } plat_instance_t; #define ARRAY_MAXNUM 16 static void prv_output_buffer(uint8_t *buffer, int length) { int i; uint8_t array[ARRAY_MAXNUM]; i = 0; while (i < length) { int j; fprintf(stderr, " "); memcpy(array, buffer + i, ARRAY_MAXNUM); for (j = 0 ; j < ARRAY_MAXNUM && i + j < length; j++) { fprintf(stderr, "%02X ", array[j]); } while (j < ARRAY_MAXNUM) { fprintf(stderr, " "); j++; } fprintf(stderr, " "); for (j = 0 ; j < ARRAY_MAXNUM && i + j < length; j++) { if (isprint(array[j])) fprintf(stderr, "%c ", array[j]); else fprintf(stderr, ". "); } fprintf(stderr, "\n"); i += ARRAY_MAXNUM; } } static uint8_t prv_read_data(plat_instance_t *targetP, int data_number, lwm2m_data_t *dataArrayP, lwm2m_data_cfg_t *dataCfg) { int i; data_report_t data; int ret; for (i = 0 ; i < data_number ; i++) { switch (dataArrayP[i].id) { case 0: //printf("19/0/0 read\r\n"); if(NULL == dataCfg) { uint8_t *buf = lwm2m_malloc(sizeof(*buf)); if(NULL == buf) { ATINY_LOG(LOG_ERR, "malloc null"); return COAP_404_NOT_FOUND; } *buf = 0; dataArrayP[i].id = 0; dataArrayP[i].type = LWM2M_TYPE_OPAQUE; dataArrayP[i].value.asBuffer.buffer = buf; dataArrayP[i].value.asBuffer.length = 1; } else { ret = atiny_dequeue_rpt_data((targetP->header), &data); if (ret != ATINY_OK) { ATINY_LOG(LOG_INFO, "atiny_dequeue_rpt_data fail,ret=%d", ret); return COAP_404_NOT_FOUND; } else { ATINY_LOG(LOG_DEBUG, "atiny_dequeue_rpt_data sucessfully"); } dataArrayP[i].id = 0; dataArrayP[i].type = LWM2M_TYPE_OPAQUE; dataArrayP[i].value.asBuffer.buffer = data.buf; dataArrayP[i].value.asBuffer.length = data.len; dataCfg->type = data.type; dataCfg->cookie = data.cookie; dataCfg->callback = (lwm2m_data_process)data.callback; } break; default: return COAP_404_NOT_FOUND; } } return COAP_205_CONTENT; } static void prv_destroy_data_buf(int data_number, lwm2m_data_t *data_array) { int i; for (i = 0 ; i < data_number; i++) { switch (data_array[i].id) { case 0: if(data_array[i].value.asBuffer.buffer != NULL) { lwm2m_free(data_array[i].value.asBuffer.buffer); data_array[i].value.asBuffer.buffer = NULL; data_array[i].value.asBuffer.length = 0; } break; default: break; } } } static uint8_t prv_read(uint16_t instanceId, int *numDataP, lwm2m_data_t **dataArrayP, lwm2m_data_cfg_t *dataCfg, lwm2m_object_t *objectP) { plat_instance_t *targetP; uint8_t ret; int new_data_flag = false; targetP = (plat_instance_t *)lwm2m_list_find(objectP->instanceList, instanceId); if (NULL == targetP) { ATINY_LOG(LOG_ERR, "plat inst not found %d", instanceId); return COAP_404_NOT_FOUND; } if (*numDataP == 0) { *dataArrayP = lwm2m_data_new(1); if (*dataArrayP == NULL) { ATINY_LOG(LOG_ERR, "lwm2m_data_new null"); return COAP_500_INTERNAL_SERVER_ERROR; } *numDataP = 1; (*dataArrayP)[0].id = 0; new_data_flag = true; } ret = prv_read_data(targetP, *numDataP, *dataArrayP, dataCfg); if(ret != COAP_205_CONTENT) { prv_destroy_data_buf(*numDataP, *dataArrayP); if(new_data_flag) { lwm2m_free(*dataArrayP); *dataArrayP = NULL; } } return ret; } static uint8_t prv_discover(uint16_t instanceId, int *numDataP, lwm2m_data_t **dataArrayP, lwm2m_object_t *objectP) { int i; // is the server asking for the full object ? if (*numDataP == 0) { *dataArrayP = lwm2m_data_new(3); if (*dataArrayP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; *numDataP = 3; (*dataArrayP)[0].id = 1; (*dataArrayP)[1].id = 2; (*dataArrayP)[2].id = 3; } else { for (i = 0; i < *numDataP; i++) { switch ((*dataArrayP)[i].id) { case 1: case 2: case 3: break; default: return COAP_404_NOT_FOUND; } } } return COAP_205_CONTENT; } static uint8_t prv_write(uint16_t instanceId, int numData, lwm2m_data_t *dataArray, lwm2m_object_t *objectP) { plat_instance_t *targetP; int i; targetP = (plat_instance_t *)lwm2m_list_find(objectP->instanceList, instanceId); if (NULL == targetP) return COAP_404_NOT_FOUND; for (i = 0 ; i < numData ; i++) { switch (dataArray[i].id) { case 0: { (void)atiny_cmd_ioctl(ATINY_WRITE_APP_DATA, (char *)(dataArray[i].value.asBuffer.buffer), dataArray->value.asBuffer.length); break; } default: return COAP_404_NOT_FOUND; } } return COAP_204_CHANGED; } static uint8_t prv_delete(uint16_t id, lwm2m_object_t *objectP) { plat_instance_t *targetP; lwm2m_uri_t uri; objectP->instanceList = lwm2m_list_remove(objectP->instanceList, id, (lwm2m_list_t **)&targetP); if (NULL == targetP) return COAP_404_NOT_FOUND; get_resource_uri(objectP->objID, targetP->shortID, BINARY_APP_DATA_RES_ID, &uri); (void)atiny_rm_rpt_uri(&uri); lwm2m_free(targetP); return COAP_202_DELETED; } static uint8_t prv_create(uint16_t instanceId, int numData, lwm2m_data_t *dataArray, lwm2m_object_t *objectP) { plat_instance_t *targetP; uint8_t result; int ret; lwm2m_uri_t uri; targetP = (plat_instance_t *)lwm2m_malloc(sizeof(plat_instance_t)); if (NULL == targetP) return COAP_500_INTERNAL_SERVER_ERROR; memset(targetP, 0, sizeof(plat_instance_t)); //atiny_list_init(&(targetP->header)); //TODO: if instanceId not valid get_resource_uri(BINARY_APP_DATA_OBJECT_ID, instanceId, BINARY_APP_DATA_RES_ID, &uri); ret = atiny_add_rpt_uri(&uri, &targetP->header); if(ret != ATINY_OK) { ATINY_LOG(LOG_ERR, "atiny_add_rpt_uri fail %d", ret); lwm2m_free(targetP); return COAP_404_NOT_FOUND; } targetP->shortID = instanceId; objectP->instanceList = LWM2M_LIST_ADD(objectP->instanceList, targetP); result = prv_write(instanceId, numData, dataArray, objectP); if (result != COAP_204_CHANGED) { (void)prv_delete(instanceId, objectP); } else { result = COAP_201_CREATED; } return result; } static uint8_t prv_exec(uint16_t instanceId, uint16_t resourceId, uint8_t *buffer, int length, lwm2m_object_t *objectP) { if (NULL == lwm2m_list_find(objectP->instanceList, instanceId)) return COAP_404_NOT_FOUND; switch (resourceId) { case 0: { ATINY_LOG(LOG_INFO, "no in prv_exec+++++++++++++++++++++++++++"); return COAP_204_CHANGED; } case 1: return COAP_405_METHOD_NOT_ALLOWED; case 2: fprintf(stdout, "\r\n-----------------\r\n" "Execute on %hu/%d/%d\r\n" " Parameter (%d bytes):\r\n", objectP->objID, instanceId, resourceId, length); prv_output_buffer((uint8_t *)buffer, length); fprintf(stdout, "-----------------\r\n\r\n"); return COAP_204_CHANGED; case 3: return COAP_405_METHOD_NOT_ALLOWED; default: return COAP_404_NOT_FOUND; } } void display_binary_app_data_object(lwm2m_object_t *object) { #ifdef WITH_LOGS fprintf(stdout, " /%u: Test object, instances:\r\n", object->objID); plat_instance_t *instance = (plat_instance_t *)object->instanceList; while (instance != NULL) { fprintf(stdout, " /%u/%u: shortId: %u, test: %u\r\n", object->objID, instance->shortID, instance->shortID, instance->test); instance = (plat_instance_t *)instance->next; } #endif } lwm2m_object_t *get_binary_app_data_object(atiny_param_t *atiny_params) { lwm2m_object_t *appObj; appObj = (lwm2m_object_t *)lwm2m_malloc(sizeof(lwm2m_object_t)); if (NULL != appObj) { int i; plat_instance_t *targetP; lwm2m_uri_t uri; int ret = ATINY_OK; memset(appObj, 0, sizeof(lwm2m_object_t)); appObj->objID = BINARY_APP_DATA_OBJECT_ID; for (i = 0 ; i < BINARY_APP_DATA_OBJECT_INSTANCE_NUM; i++) { targetP = (plat_instance_t *)lwm2m_malloc(sizeof(plat_instance_t)); if (NULL == targetP) { break; } memset(targetP, 0, sizeof(plat_instance_t)); get_resource_uri(BINARY_APP_DATA_OBJECT_ID, i, BINARY_APP_DATA_RES_ID, &uri); ret = atiny_add_rpt_uri(&uri, &targetP->header); if(ret != ATINY_OK) { ATINY_LOG(LOG_ERR, "atiny_add_rpt_uri fail %d", ret); lwm2m_free(targetP); break; } (void)atiny_set_max_rpt_cnt(&uri, MAX(MIN_SAVE_CNT, atiny_params->server_params.storing_cnt)); targetP->shortID = i; appObj->instanceList = LWM2M_LIST_ADD(appObj->instanceList, targetP); } if(i < BINARY_APP_DATA_OBJECT_INSTANCE_NUM) { free_binary_app_data_object(appObj); return NULL; } /* * From a single instance object, two more functions are available. * - The first one (createFunc) create a new instance and filled it with the provided informations. If an ID is * provided a check is done for verifying his disponibility, or a new one is generated. * - The other one (deleteFunc) delete an instance by removing it from the instance list (and freeing the memory * allocated to it) */ appObj->readFunc = prv_read; appObj->discoverFunc = prv_discover; appObj->writeFunc = prv_write; appObj->executeFunc = prv_exec; appObj->createFunc = prv_create; appObj->deleteFunc = prv_delete; } return appObj; } static void free_binary_app_data_object_rpt(lwm2m_object_t *object) { lwm2m_list_t *cur = object->instanceList; lwm2m_uri_t uri; while(cur) { get_resource_uri(object->objID, ((plat_instance_t *)cur)->shortID, BINARY_APP_DATA_RES_ID, &uri); (void)atiny_rm_rpt_uri(&uri); cur = cur->next; } } void free_binary_app_data_object(lwm2m_object_t *object) { free_binary_app_data_object_rpt(object); LWM2M_LIST_FREE(object->instanceList); if (object->userData != NULL) { lwm2m_free(object->userData); object->userData = NULL; } lwm2m_free(object); } void set_binary_app_data_object_rpt_max_cnt(uint32_t max_rpt_cnt) { lwm2m_uri_t uri; get_resource_uri(BINARY_APP_DATA_OBJECT_ID, 0, BINARY_APP_DATA_RES_ID, &uri); (void)atiny_set_max_rpt_cnt(&uri, MAX(MIN_SAVE_CNT, max_rpt_cnt)); } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/object_comm.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2014 Bosch Software Innovations GmbH, Germany. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Bosch Software Innovations GmbH - Please refer to git log * *******************************************************************************/ /* * object_comm.h * * General functions of lwm2m test client. * * Created on: 22.01.2015 * Author: Achim Kraus * Copyright (c) 2015 Bosch Software Innovations GmbH, Germany. All rights reserved. */ #ifndef OBJECT_COMM_H_ #define OBJECT_COMM_H_ #include "internals.h" #include "atiny_lwm2m/agenttiny.h" #include "connection.h" #include "agent_list.h" #ifndef MAX #define MAX(a, b) ((a) >= (b)? (a) : (b)) #endif extern int g_reboot; typedef struct { lwm2m_object_t * securityObjP; lwm2m_object_t * serverObject; connection_t *connList; lwm2m_context_t * lwm2mH; } client_data_t; typedef struct _security_instance_ { struct _security_instance_ * next; // matches lwm2m_list_t::next uint16_t instanceId; // matches lwm2m_list_t::id char * uri; bool isBootstrap; uint8_t securityMode; char * publicIdentity; uint16_t publicIdLen; char * serverPublicKey; uint16_t serverPublicKeyLen; char * secretKey; uint16_t secretKeyLen; uint8_t smsSecurityMode; char * smsParams; // SMS binding key parameters uint16_t smsParamsLen; char * smsSecret; // SMS binding secret key uint16_t smsSecretLen; uint16_t shortID; uint32_t clientHoldOffTime; uint32_t bootstrapServerAccountTimeout; } security_instance_t; typedef struct _data_node_t { atiny_dl_list list; data_report_t data; }data_node_t; /* * object_device.c */ lwm2m_object_t * get_object_device(atiny_param_t *atiny_params, const char* manufacturer); void free_object_device(lwm2m_object_t * objectP); void display_device_object(lwm2m_object_t * objectP); /* * object_firmware.c */ lwm2m_object_t * get_object_firmware(atiny_param_t *atiny_params); void free_object_firmware(lwm2m_object_t * objectP); /* * object_location.c */ lwm2m_object_t * get_object_location(void); void free_object_location(lwm2m_object_t * object); void display_location_object(lwm2m_object_t * objectP); /* * object_test.c */ #define TEST_OBJECT_ID 31024 lwm2m_object_t * get_test_object(void); void free_test_object(lwm2m_object_t * object); void display_test_object(lwm2m_object_t * objectP); /* * binary_app_data_object.c */ #define BINARY_APP_DATA_OBJECT_ID 19 #define BINARY_APP_DATA_RES_ID 0 lwm2m_object_t * get_binary_app_data_object(atiny_param_t *atiny_params); void free_binary_app_data_object(lwm2m_object_t * object); void display_binary_app_data_object(lwm2m_object_t * objectP); void set_binary_app_data_object_rpt_max_cnt(uint32_t max_rpt_cnt); /* * object_server.c */ lwm2m_object_t * get_server_object(int serverId, const char* binding, int lifetime, bool storing); void clean_server_object(lwm2m_object_t * object); void display_server_object(lwm2m_object_t * objectP); void copy_server_object(lwm2m_object_t * objectDest, lwm2m_object_t * objectSrc); /* * object_connectivity_moni.c */ lwm2m_object_t * get_object_conn_m(atiny_param_t *atiny_params); void free_object_conn_m(lwm2m_object_t * objectP); uint8_t connectivity_moni_change(lwm2m_data_t * dataArray, lwm2m_object_t * objectP); /* * object_connectivity_stat.c */ extern lwm2m_object_t * get_object_conn_s(void); void free_object_conn_s(lwm2m_object_t * objectP); extern void conn_s_updateTxStatistic(lwm2m_object_t * objectP, uint16_t txDataByte, bool smsBased); extern void conn_s_updateRxStatistic(lwm2m_object_t * objectP, uint16_t rxDataByte, bool smsBased); /* * object_access_control.c */ typedef enum { OBJ_ACC_READ = 0, OBJ_ACC_WRITE_ATTR = 0, OBJ_ACC_OBSERVE = 0, OBJ_ACC_NOTIFY = 0, OBJ_ACC_WRITE = 1, OBJ_ACC_EXCUTE = 2, OBJ_ACC_DELETE = 3, OBJ_ACC_CREATE = 4, OBJ_ACC_DISCOVER = 5, } OBJ_ACC_OPERATE; #define ACC_AUTH_R (0x01 << OBJ_ACC_READ) #define ACC_AUTH_W (0x01 << OBJ_ACC_WRITE) #define ACC_AUTH_E (0x01 << OBJ_ACC_EXCUTE) #define ACC_AUTH_D (0x01 << OBJ_ACC_DELETE) #define ACC_AUTH_C (0x01 << OBJ_ACC_CREATE) lwm2m_object_t* acc_ctrl_create_object(void); void acl_ctrl_free_object(lwm2m_object_t * objectP); bool acc_ctrl_obj_add_inst (lwm2m_object_t* accCtrlObjP, uint16_t instId, uint16_t acObjectId, uint16_t acObjInstId, uint16_t acOwner); bool acc_ctrl_oi_add_ac_val(lwm2m_object_t* accCtrlObjP, uint16_t instId, uint16_t aclResId, uint16_t acValue); uint8_t acc_auth_operate(lwm2m_context_t* contextP, lwm2m_uri_t* uri, OBJ_ACC_OPERATE op, uint16_t serverId); /* * object_comm.c */ void handle_value_changed(lwm2m_context_t* lwm2mH, lwm2m_uri_t* uri, const char * value, size_t valueLength); /* * object_security.c */ lwm2m_object_t * get_security_object(uint16_t serverId,atiny_param_t* atiny_params,lwm2m_context_t* lwm2m_context); void clean_security_object(lwm2m_object_t * objectP); char * get_server_uri(lwm2m_object_t * objectP, uint16_t secObjInstID); void display_security_object(lwm2m_object_t * objectP); void copy_security_object(lwm2m_object_t * objectDest, lwm2m_object_t * objectSrc); int prv_refreshServerList(lwm2m_context_t * contextP); void output_buffer(FILE * stream, uint8_t * buffer, int length, int indent); void atiny_set_reboot_flag(void); #endif /* LWM2MCLIENT_H_ */ ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/object_connectivity_moni.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2014 Bosch Software Innovations GmbH Germany. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - Please refer to git log * *******************************************************************************/ /* * This Connectivity Monitoring object is optional and has a single instance * * Resources: * * Name | ID | Oper. | Inst. | Mand.| Type | Range | Units | * Network Bearer | 0 | R | Single| Yes | Integer | | | * Available Network Bearer | 1 | R | Multi | Yes | Integer | | | * Radio Signal Strength | 2 | R | Single| Yes | Integer | | dBm | * Link Quality | 3 | R | Single| No | Integer | 0-100 | % | * IP Addresses | 4 | R | Multi | Yes | String | | | * Router IP Addresses | 5 | R | Multi | No | String | | | * Link Utilization | 6 | R | Single| No | Integer | 0-100 | % | * APN | 7 | R | Multi | No | String | | | * Cell ID | 8 | R | Single| No | Integer | | | * SMNC | 9 | R | Single| No | Integer | 0-999 | % | * SMCC | 10 | R | Single| No | Integer | 0-999 | | * */ #include "internals.h" #include "atiny_lwm2m/agenttiny.h" // Resource Id's: #define RES_M_NETWORK_BEARER 0 #define RES_M_AVL_NETWORK_BEARER 1 #define RES_M_RADIO_SIGNAL_STRENGTH 2 #define RES_O_LINK_QUALITY 3 #define RES_M_IP_ADDRESSES 4 #define RES_O_ROUTER_IP_ADDRESS 5 #define RES_O_LINK_UTILIZATION 6 #define RES_O_APN 7 #define RES_O_CELL_ID 8 #define RES_O_SMNC 9 #define RES_O_SMCC 10 #define VALUE_NETWORK_BEARER_GSM 0 //GSM see #define VALUE_AVL_NETWORK_BEARER_1 0 //GSM #define VALUE_AVL_NETWORK_BEARER_2 21 //WLAN #define VALUE_AVL_NETWORK_BEARER_3 41 //Ethernet #define VALUE_AVL_NETWORK_BEARER_4 42 //DSL #define VALUE_AVL_NETWORK_BEARER_5 43 //PLC #define VALUE_IP_ADDRESS_1 "192.168.178.101" #define VALUE_IP_ADDRESS_2 "192.168.178.102" #define VALUE_ROUTER_IP_ADDRESS_1 "192.168.178.001" #define VALUE_ROUTER_IP_ADDRESS_2 "192.168.178.002" #define VALUE_APN_1 "web.vodafone.de" #define VALUE_APN_2 "cda.vodafone.de" #define VALUE_CELL_ID 69696969 #define VALUE_RADIO_SIGNAL_STRENGTH 80 //dBm #define VALUE_LINK_QUALITY 98 #define VALUE_LINK_UTILIZATION 666 #define VALUE_SMNC 33 #define VALUE_SMCC 44 #define IP4ADDR_STRLEN_MAX 16 #define IPADDRT_LIMIT 2 typedef struct { char ipAddresses[IPADDRT_LIMIT][IP4ADDR_STRLEN_MAX]; // limited to 2! char routerIpAddresses[IPADDRT_LIMIT][IP4ADDR_STRLEN_MAX]; // limited to 2! long cellId; int signalStrength; int linkQuality; int linkUtilization; } conn_m_data_t; static uint8_t prv_set_value(lwm2m_data_t *dataP, conn_m_data_t *connDataP) { switch (dataP->id) { case RES_M_NETWORK_BEARER: lwm2m_data_encode_int(VALUE_NETWORK_BEARER_GSM, dataP); return COAP_205_CONTENT; case RES_M_AVL_NETWORK_BEARER: { int riCnt = 1; // reduced to 1 instance to fit in one block size lwm2m_data_t *subTlvP; int networkbearer = 0; subTlvP = lwm2m_data_new(riCnt); if (subTlvP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; subTlvP[0].id = 0; (void)atiny_cmd_ioctl(ATINY_GET_NETWORK_BEARER, (char *)&networkbearer, sizeof(int)); lwm2m_data_encode_int(networkbearer, subTlvP); lwm2m_data_encode_instances(subTlvP, riCnt, dataP); return COAP_205_CONTENT ; } case RES_M_RADIO_SIGNAL_STRENGTH: //s-int { int signalstrength = 0; (void)atiny_cmd_ioctl(ATINY_GET_SIGNAL_STRENGTH, (char *)&signalstrength, sizeof(int)); lwm2m_data_encode_int(connDataP->signalStrength, dataP); return COAP_205_CONTENT; } case RES_O_LINK_QUALITY: //s-int { int linkQuality; (void)atiny_cmd_ioctl(ATINY_GET_LINK_QUALITY, (char *)&linkQuality, sizeof(int)); lwm2m_data_encode_int(linkQuality, dataP); return COAP_205_CONTENT ; } case RES_M_IP_ADDRESSES: { int ri, riCnt = 1; // reduced to 1 instance to fit in one block size lwm2m_data_t *subTlvP = lwm2m_data_new(riCnt); if (subTlvP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; for (ri = 0; ri < riCnt; ri++) { subTlvP[ri].id = ri; lwm2m_data_encode_string(connDataP->ipAddresses[ri], subTlvP + ri); } lwm2m_data_encode_instances(subTlvP, riCnt, dataP); return COAP_205_CONTENT ; } case RES_O_ROUTER_IP_ADDRESS: { int ri, riCnt = 1; // reduced to 1 instance to fit in one block size lwm2m_data_t *subTlvP = lwm2m_data_new(riCnt); if (subTlvP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; for (ri = 0; ri < riCnt; ri++) { subTlvP[ri].id = ri; lwm2m_data_encode_string(connDataP->routerIpAddresses[ri], subTlvP + ri); } lwm2m_data_encode_instances(subTlvP, riCnt, dataP); return COAP_205_CONTENT ; } case RES_O_LINK_UTILIZATION: { int linkUtilization; (void)atiny_cmd_ioctl(ATINY_GET_LINK_UTILIZATION, (char *)&linkUtilization, sizeof(int)); lwm2m_data_encode_int(connDataP->linkUtilization, dataP); return COAP_205_CONTENT; } case RES_O_APN: { int riCnt = 1; // reduced to 1 instance to fit in one block size lwm2m_data_t *subTlvP; subTlvP = lwm2m_data_new(riCnt); if (subTlvP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; subTlvP[0].id = 0; lwm2m_data_encode_string(VALUE_APN_1, subTlvP); lwm2m_data_encode_instances(subTlvP, riCnt, dataP); return COAP_205_CONTENT; } case RES_O_CELL_ID: { int cellId = 0; (void)atiny_cmd_ioctl(ATINY_GET_CELL_ID, (char *)&cellId, sizeof(int)); lwm2m_data_encode_int(cellId, dataP); return COAP_205_CONTENT ; } case RES_O_SMNC: lwm2m_data_encode_int(VALUE_SMNC, dataP); return COAP_205_CONTENT ; case RES_O_SMCC: lwm2m_data_encode_int(VALUE_SMCC, dataP); return COAP_205_CONTENT ; default: return COAP_404_NOT_FOUND ; } } static uint8_t prv_read(uint16_t instanceId, int *numDataP, lwm2m_data_t **dataArrayP, lwm2m_data_cfg_t *dataCfg, lwm2m_object_t *objectP) { uint8_t result; int i; // this is a single instance object if (instanceId != 0) { return COAP_404_NOT_FOUND ; } // is the server asking for the full object ? if (*numDataP == 0) { uint16_t resList[] = { RES_M_NETWORK_BEARER, RES_M_AVL_NETWORK_BEARER, RES_M_RADIO_SIGNAL_STRENGTH, RES_O_LINK_QUALITY, RES_M_IP_ADDRESSES, RES_O_ROUTER_IP_ADDRESS, RES_O_LINK_UTILIZATION, RES_O_APN, RES_O_CELL_ID, RES_O_SMNC, RES_O_SMCC }; int nbRes = sizeof(resList) / sizeof(uint16_t); *dataArrayP = lwm2m_data_new(nbRes); if (*dataArrayP == NULL) return COAP_500_INTERNAL_SERVER_ERROR ; *numDataP = nbRes; for (i = 0; i < nbRes; i++) { (*dataArrayP)[i].id = resList[i]; } } i = 0; do { result = prv_set_value((*dataArrayP) + i, (conn_m_data_t *) (objectP->userData)); i++; } while (i < *numDataP && result == COAP_205_CONTENT ); return result; } lwm2m_object_t *get_object_conn_m(atiny_param_t *atiny_params) { /* * The get_object_conn_m() function create the object itself and return a pointer to the structure that represent it. */ lwm2m_object_t *connObj; connObj = (lwm2m_object_t *) lwm2m_malloc(sizeof(lwm2m_object_t)); if (NULL != connObj) { memset(connObj, 0, sizeof(lwm2m_object_t)); /* * It assigns his unique ID */ connObj->objID = LWM2M_CONN_MONITOR_OBJECT_ID; /* * and its unique instance * */ connObj->instanceList = (lwm2m_list_t *)lwm2m_malloc(sizeof(lwm2m_list_t)); if (NULL != connObj->instanceList) { memset(connObj->instanceList, 0, sizeof(lwm2m_list_t)); } else { lwm2m_free(connObj); return NULL; } /* * And the private function that will access the object. * Those function will be called when a read/write/execute query is made by the server. In fact the library don't need to * know the resources of the object, only the server does. */ connObj->readFunc = prv_read; connObj->executeFunc = NULL; connObj->userData = lwm2m_malloc(sizeof(conn_m_data_t)); /* * Also some user data can be stored in the object with a private structure containing the needed variables */ if (NULL != connObj->userData) { conn_m_data_t *myData = (conn_m_data_t *) connObj->userData; memset((void *)myData, 0, sizeof(conn_m_data_t)); myData->cellId = VALUE_CELL_ID; myData->signalStrength = VALUE_RADIO_SIGNAL_STRENGTH; myData->linkQuality = VALUE_LINK_QUALITY; myData->linkUtilization = VALUE_LINK_UTILIZATION; strncpy(myData->ipAddresses[0], VALUE_IP_ADDRESS_1, IP4ADDR_STRLEN_MAX - 1); strncpy(myData->ipAddresses[1], VALUE_IP_ADDRESS_2, IP4ADDR_STRLEN_MAX - 1); strncpy(myData->routerIpAddresses[0], VALUE_ROUTER_IP_ADDRESS_1, IP4ADDR_STRLEN_MAX - 1); strncpy(myData->routerIpAddresses[1], VALUE_ROUTER_IP_ADDRESS_2, IP4ADDR_STRLEN_MAX - 1); } else { lwm2m_list_free(connObj->instanceList); lwm2m_free(connObj); connObj = NULL; } } return connObj; } void free_object_conn_m(lwm2m_object_t *objectP) { lwm2m_free(objectP->userData); lwm2m_list_free(objectP->instanceList); lwm2m_free(objectP); } uint8_t connectivity_moni_change(lwm2m_data_t *dataArray, lwm2m_object_t *objectP) { int64_t value; uint8_t result; conn_m_data_t *data; data = (conn_m_data_t *) (objectP->userData); switch (dataArray->id) { case RES_M_RADIO_SIGNAL_STRENGTH: if (1 == lwm2m_data_decode_int(dataArray, &value)) { data->signalStrength = value; result = COAP_204_CHANGED; } else { result = COAP_400_BAD_REQUEST; } break; case RES_O_LINK_QUALITY: if (1 == lwm2m_data_decode_int(dataArray, &value)) { data->linkQuality = value; result = COAP_204_CHANGED; } else { result = COAP_400_BAD_REQUEST; } break; case RES_M_IP_ADDRESSES: if (sizeof(data->ipAddresses[0]) <= dataArray->value.asBuffer.length) { result = COAP_400_BAD_REQUEST; } else { memset(data->ipAddresses[0], 0, sizeof(data->ipAddresses[0])); memcpy(data->ipAddresses[0], dataArray->value.asBuffer.buffer, dataArray->value.asBuffer.length); data->ipAddresses[0][dataArray->value.asBuffer.length] = 0; result = COAP_204_CHANGED; } break; case RES_O_ROUTER_IP_ADDRESS: if (sizeof(data->routerIpAddresses[0]) <= dataArray->value.asBuffer.length) { result = COAP_400_BAD_REQUEST; } else { memset(data->routerIpAddresses[0], 0, sizeof(data->routerIpAddresses[0])); memcpy(data->routerIpAddresses[0], dataArray->value.asBuffer.buffer, dataArray->value.asBuffer.length); data->routerIpAddresses[0][dataArray->value.asBuffer.length] = 0; result = COAP_204_CHANGED; } break; case RES_O_CELL_ID: if (1 == lwm2m_data_decode_int(dataArray, &value)) { data->cellId = value; result = COAP_204_CHANGED; } else { result = COAP_400_BAD_REQUEST; } break; default: result = COAP_405_METHOD_NOT_ALLOWED; } return result; } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/object_connectivity_stat.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2015 Bosch Software Innovations GmbH Germany. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Bosch Software Innovations GmbH - Please refer to git log * *******************************************************************************/ /* * This connectivity statistics object is optional and single instance only * * Resources: * * Name | ID | Oper. | Inst. | Mand.| Type | Range | Units | Description | * SMS Tx Counter | 0 | R | Single| No | Integer | | | | * SMS Rx Counter | 1 | R | Single| No | Integer | | | | * Tx Data | 2 | R | Single| No | Integer | | kByte | | * Rx Data | 3 | R | Single| No | Integer | | kByte | | * Max Message Size | 4 | R | Single| No | Integer | | Byte | | * Average Message Size | 5 | R | Single| No | Integer | | Byte | | * StartOrReset | 6 | E | Single| Yes | Integer | | | | */ #include "internals.h" // Resource Id's: #define RES_O_SMS_TX_COUNTER 0 #define RES_O_SMS_RX_COUNTER 1 #define RES_O_TX_DATA 2 #define RES_O_RX_DATA 3 #define RES_O_MAX_MESSAGE_SIZE 4 #define RES_O_AVERAGE_MESSAGE_SIZE 5 #define RES_M_START_OR_RESET 6 typedef struct { int64_t smsTxCounter; int64_t smsRxCounter; int64_t txDataByte; // report in kByte! int64_t rxDataByte; // report in kByte! int64_t maxMessageSize; int64_t avrMessageSize; int64_t messageCount; // private for incremental average calc. bool collectDataStarted; } conn_s_data_t; static uint8_t prv_set_tlv(lwm2m_data_t *dataP, conn_s_data_t *connStDataP) { switch (dataP->id) { case RES_O_SMS_TX_COUNTER: lwm2m_data_encode_int(connStDataP->smsTxCounter, dataP); return COAP_205_CONTENT; case RES_O_SMS_RX_COUNTER: lwm2m_data_encode_int(connStDataP->smsRxCounter, dataP); return COAP_205_CONTENT; case RES_O_TX_DATA: lwm2m_data_encode_int(connStDataP->txDataByte / 1024, dataP); return COAP_205_CONTENT; case RES_O_RX_DATA: lwm2m_data_encode_int(connStDataP->rxDataByte / 1024, dataP); return COAP_205_CONTENT; case RES_O_MAX_MESSAGE_SIZE: lwm2m_data_encode_int(connStDataP->maxMessageSize, dataP); return COAP_205_CONTENT; case RES_O_AVERAGE_MESSAGE_SIZE: lwm2m_data_encode_int(connStDataP->avrMessageSize, dataP); return COAP_205_CONTENT; default: return COAP_404_NOT_FOUND ; } } static uint8_t prv_read(uint16_t instanceId, int *numDataP, lwm2m_data_t **dataArrayP, lwm2m_data_cfg_t *dataCfg, lwm2m_object_t *objectP) { uint8_t result; int i; // this is a single instance object if (instanceId != 0) { return COAP_404_NOT_FOUND ; } // is the server asking for the full object ? if (*numDataP == 0) { uint16_t resList[] = { RES_O_SMS_TX_COUNTER, RES_O_SMS_RX_COUNTER, RES_O_TX_DATA, RES_O_RX_DATA, RES_O_MAX_MESSAGE_SIZE, RES_O_AVERAGE_MESSAGE_SIZE }; int nbRes = sizeof(resList) / sizeof(uint16_t); *dataArrayP = lwm2m_data_new(nbRes); if (*dataArrayP == NULL) return COAP_500_INTERNAL_SERVER_ERROR ; *numDataP = nbRes; for (i = 0; i < nbRes; i++) { (*dataArrayP)[i].id = resList[i]; } } i = 0; do { result = prv_set_tlv((*dataArrayP) + i, (conn_s_data_t *) (objectP->userData)); i++; } while (i < *numDataP && result == COAP_205_CONTENT ); return result; } static void prv_resetCounter(lwm2m_object_t *objectP, bool start) { conn_s_data_t *myData = (conn_s_data_t *) objectP->userData; myData->smsTxCounter = 0; myData->smsRxCounter = 0; myData->txDataByte = 0; myData->rxDataByte = 0; myData->maxMessageSize = 0; myData->avrMessageSize = 0; myData->messageCount = 0; myData->collectDataStarted = start; } static uint8_t prv_exec(uint16_t instanceId, uint16_t resourceId, uint8_t *buffer, int length, lwm2m_object_t *objectP) { // this is a single instance object if (instanceId != 0) { return COAP_404_NOT_FOUND; } if (length != 0) return COAP_400_BAD_REQUEST; switch (resourceId) { case RES_M_START_OR_RESET: prv_resetCounter(objectP, true); return COAP_204_CHANGED; default: return COAP_405_METHOD_NOT_ALLOWED; } } void conn_s_updateTxStatistic(lwm2m_object_t *objectP, uint16_t txDataByte, bool smsBased) { conn_s_data_t *myData = (conn_s_data_t *) (objectP->userData); if (myData->collectDataStarted) { myData->txDataByte += txDataByte; myData->messageCount++; myData->avrMessageSize = (myData->txDataByte + myData->rxDataByte) / myData->messageCount; if (txDataByte > myData->maxMessageSize) myData->maxMessageSize = txDataByte; if (smsBased) myData->smsTxCounter++; } } void conn_s_updateRxStatistic(lwm2m_object_t *objectP, uint16_t rxDataByte, bool smsBased) { conn_s_data_t *myData = (conn_s_data_t *) (objectP->userData); if (myData->collectDataStarted) { myData->rxDataByte += rxDataByte; myData->messageCount++; myData->avrMessageSize = (myData->txDataByte + myData->rxDataByte) / myData->messageCount; if (rxDataByte > myData->maxMessageSize) myData->maxMessageSize = rxDataByte; myData->txDataByte += rxDataByte; if (smsBased) myData->smsRxCounter++; } } lwm2m_object_t *get_object_conn_s(void) { /* * The get_object_conn_s() function create the object itself and return * a pointer to the structure that represent it. */ lwm2m_object_t *connObj; connObj = (lwm2m_object_t *) lwm2m_malloc(sizeof(lwm2m_object_t)); if (NULL != connObj) { memset(connObj, 0, sizeof(lwm2m_object_t)); /* * It assign his unique ID * The 7 is the standard ID for the optional object "Connectivity Statistics". */ connObj->objID = LWM2M_CONN_STATS_OBJECT_ID; connObj->instanceList = lwm2m_malloc(sizeof(lwm2m_list_t)); if (NULL != connObj->instanceList) { memset(connObj->instanceList, 0, sizeof(lwm2m_list_t)); } else { lwm2m_free(connObj); return NULL; } /* * And the private function that will access the object. * Those function will be called when a read/execute/close * query is made by the server or core. In fact the library don't need * to know the resources of the object, only the server does. */ connObj->readFunc = prv_read; connObj->executeFunc = prv_exec; connObj->userData = lwm2m_malloc(sizeof(conn_s_data_t)); /* * Also some user data can be stored in the object with a private * structure containing the needed variables. */ if (NULL != connObj->userData) { prv_resetCounter(connObj, false); } else { lwm2m_free(connObj->instanceList); lwm2m_free(connObj); connObj = NULL; } } return connObj; } void free_object_conn_s(lwm2m_object_t *objectP) { lwm2m_free(objectP->userData); lwm2m_list_free(objectP->instanceList); lwm2m_free(objectP); } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/object_device.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * domedambrosio - Please refer to git log * Fabien Fleutot - Please refer to git log * Axel Lorente - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - Please refer to git log * *******************************************************************************/ /* Copyright (c) 2013, 2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. David Navarro */ /* * This object is single instance only, and is mandatory to all LWM2M device as it describe the object such as its * manufacturer, model, etc... */ #include "object_comm.h" #define PRV_OFFSET_MAXLEN 7 //+HH:MM\0 at max #define PRV_TIMEZONE_MAXLEN 25 #define MAX_STRING_LEN 64 // Resource Id's: #define RES_O_MANUFACTURER 0 #define RES_O_MODEL_NUMBER 1 #define RES_O_SERIAL_NUMBER 2 #define RES_O_FIRMWARE_VERSION 3 #define RES_M_REBOOT 4 #define RES_O_FACTORY_RESET 5 #define RES_O_AVL_POWER_SOURCES 6 #define RES_O_POWER_SOURCE_VOLTAGE 7 #define RES_O_POWER_SOURCE_CURRENT 8 #define RES_O_BATTERY_LEVEL 9 #define RES_O_MEMORY_FREE 10 #define RES_M_ERROR_CODE 11 #define RES_O_RESET_ERROR_CODE 12 #define RES_O_CURRENT_TIME 13 #define RES_O_UTC_OFFSET 14 #define RES_O_TIMEZONE 15 #define RES_M_BINDING_MODES 16 // since TS 20141126-C: #define RES_O_DEVICE_TYPE 17 #define RES_O_HARDWARE_VERSION 18 #define RES_O_SOFTWARE_VERSION 19 #define RES_O_BATTERY_STATUS 20 #define RES_O_MEMORY_TOTAL 21 // basic check that the time offset value is at ISO 8601 format // bug: +12:30 is considered a valid value by this function static int prv_check_time_offset(char *buffer, int length) { int min_index; if (length != 3 && length != 5 && length != 6) return 0; if (buffer[0] != '-' && buffer[0] != '+') return 0; switch (buffer[1]) { case '0': if (buffer[2] < '0' || buffer[2] > '9') return 0; break; case '1': if (buffer[2] < '0' || buffer[2] > '2') return 0; break; default: return 0; } switch (length) { case 3: return 1; case 5: min_index = 3; break; case 6: if (buffer[3] != ':') return 0; min_index = 4; break; default: // never happen return 0; } if (buffer[min_index] < '0' || buffer[min_index] > '5') return 0; if (buffer[min_index + 1] < '0' || buffer[min_index + 1] > '9') return 0; return 1; } static uint8_t prv_set_value(lwm2m_data_t *dataP) { char str[MAX_STRING_LEN + 1] = {0}; int64_t current_time; char UTC_offset[PRV_OFFSET_MAXLEN]; char timezone[PRV_TIMEZONE_MAXLEN]; lwm2m_data_t *subTlvP; int power; int voltage; int battery_level; int free_memory; int err; int result; // a simple switch structure is used to respond at the specified resource asked switch (dataP->id) { case RES_O_MANUFACTURER: result = atiny_cmd_ioctl(ATINY_GET_MANUFACTURER, str, MAX_STRING_LEN); if(result == ATINY_OK) { lwm2m_data_encode_string(str, dataP); return COAP_205_CONTENT; } else { return COAP_400_BAD_REQUEST; } case RES_O_MODEL_NUMBER: result = atiny_cmd_ioctl(ATINY_GET_MODEL_NUMBER, str, MAX_STRING_LEN); if(result == ATINY_OK) { lwm2m_data_encode_string(str, dataP); return COAP_205_CONTENT; } else { return COAP_400_BAD_REQUEST; } case RES_O_SERIAL_NUMBER: result = atiny_cmd_ioctl(ATINY_GET_SERIAL_NUMBER, str, MAX_STRING_LEN); if(result == ATINY_OK) { lwm2m_data_encode_string(str, dataP); return COAP_205_CONTENT; } else { return COAP_400_BAD_REQUEST; } case RES_O_FIRMWARE_VERSION: result = atiny_cmd_ioctl(ATINY_GET_FIRMWARE_VER, str, MAX_STRING_LEN); if(result == ATINY_OK) { lwm2m_data_encode_string(str, dataP); return COAP_205_CONTENT; } else { return COAP_400_BAD_REQUEST; } case RES_M_REBOOT: return COAP_405_METHOD_NOT_ALLOWED; case RES_O_FACTORY_RESET: return COAP_405_METHOD_NOT_ALLOWED; case RES_O_AVL_POWER_SOURCES: { subTlvP = lwm2m_data_new(1); if (subTlvP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; subTlvP[0].id = 0; result = atiny_cmd_ioctl(ATINY_GET_POWER_SOURCE, (char *)&power, sizeof(int)); if(result == ATINY_OK) { lwm2m_data_encode_int(power, subTlvP); lwm2m_data_encode_instances(subTlvP, 1, dataP); return COAP_205_CONTENT; } else { lwm2m_free(subTlvP); return COAP_400_BAD_REQUEST; } } case RES_O_POWER_SOURCE_VOLTAGE: { subTlvP = lwm2m_data_new(1); if (subTlvP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; subTlvP[0].id = 0; result = atiny_cmd_ioctl(ATINY_GET_SOURCE_VOLTAGE, (char *)&voltage, sizeof(int)); if(result == ATINY_OK) { lwm2m_data_encode_int(voltage, subTlvP); lwm2m_data_encode_instances(subTlvP, 1, dataP); return COAP_205_CONTENT; } else { lwm2m_free(subTlvP); return COAP_400_BAD_REQUEST; } } case RES_O_POWER_SOURCE_CURRENT: { subTlvP = lwm2m_data_new(1); if (subTlvP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; subTlvP[0].id = 0; result = atiny_cmd_ioctl(ATINY_GET_POWER_CURRENT, (char *)&power, sizeof(int)); if(result == ATINY_OK) { lwm2m_data_encode_int(power, &subTlvP[0]); lwm2m_data_encode_instances(subTlvP, 1, dataP); return COAP_205_CONTENT; } else { lwm2m_free(subTlvP); return COAP_400_BAD_REQUEST; } } case RES_O_BATTERY_LEVEL: { result = atiny_cmd_ioctl(ATINY_GET_BATERRY_LEVEL, (char *)&battery_level, sizeof(int)); if(result == ATINY_OK) { lwm2m_data_encode_int(battery_level, dataP); return COAP_205_CONTENT; } else { return COAP_400_BAD_REQUEST; } } case RES_O_MEMORY_FREE: { result = atiny_cmd_ioctl(ATINY_GET_MEMORY_FREE, (char *)&free_memory, sizeof(int)); if(result == ATINY_OK) { lwm2m_data_encode_int(free_memory, dataP); return COAP_205_CONTENT; } else { return COAP_400_BAD_REQUEST; } } case RES_M_ERROR_CODE: { subTlvP = lwm2m_data_new(1); if (subTlvP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; subTlvP[0].id = 0; result = atiny_cmd_ioctl(ATINY_GET_DEV_ERR, (char *)&err, sizeof(int)); if(result == ATINY_OK) { lwm2m_data_encode_int(err, subTlvP); lwm2m_data_encode_instances(subTlvP, 1, dataP); return COAP_205_CONTENT; } else { lwm2m_free(subTlvP); return COAP_400_BAD_REQUEST; } } case RES_O_RESET_ERROR_CODE: return COAP_405_METHOD_NOT_ALLOWED; case RES_O_CURRENT_TIME: result = atiny_cmd_ioctl(ATINY_GET_CURRENT_TIME, (char *)¤t_time, sizeof(int64_t)); if(result == ATINY_OK) { lwm2m_data_encode_int(current_time, dataP); return COAP_205_CONTENT; } else { return COAP_400_BAD_REQUEST; } case RES_O_UTC_OFFSET: result = atiny_cmd_ioctl(ATINY_GET_UTC_OFFSET, UTC_offset, PRV_OFFSET_MAXLEN); if(result == ATINY_OK) { lwm2m_data_encode_string(UTC_offset, dataP); return COAP_205_CONTENT; } else { return COAP_400_BAD_REQUEST; } case RES_O_TIMEZONE: result = atiny_cmd_ioctl(ATINY_GET_TIMEZONE, timezone, PRV_TIMEZONE_MAXLEN); if(result == ATINY_OK) { lwm2m_data_encode_string(timezone, dataP); return COAP_205_CONTENT; } else { return COAP_400_BAD_REQUEST; } case RES_M_BINDING_MODES: result = atiny_cmd_ioctl(ATINY_GET_BINDING_MODES, str, MAX_STRING_LEN); if(result == ATINY_OK) { lwm2m_data_encode_string(str, dataP); return COAP_205_CONTENT; } else { return COAP_400_BAD_REQUEST; } default: return COAP_404_NOT_FOUND; } } static uint8_t prv_device_read(uint16_t instanceId, int *numDataP, lwm2m_data_t **dataArrayP, lwm2m_data_cfg_t *dataCfg, lwm2m_object_t *objectP) { uint8_t result; int i; // this is a single instance object if (instanceId != 0) { return COAP_404_NOT_FOUND; } // is the server asking for the full object ? if (*numDataP == 0) { uint16_t resList[] = { RES_O_MANUFACTURER, RES_O_MODEL_NUMBER, RES_O_SERIAL_NUMBER, RES_O_FIRMWARE_VERSION, //E: RES_M_REBOOT, //E: RES_O_FACTORY_RESET, RES_O_AVL_POWER_SOURCES, RES_O_POWER_SOURCE_VOLTAGE, RES_O_POWER_SOURCE_CURRENT, RES_O_BATTERY_LEVEL, RES_O_MEMORY_FREE, RES_M_ERROR_CODE, //E: RES_O_RESET_ERROR_CODE, RES_O_CURRENT_TIME, RES_O_UTC_OFFSET, RES_O_TIMEZONE, RES_M_BINDING_MODES }; int nbRes = sizeof(resList) / sizeof(uint16_t); *dataArrayP = lwm2m_data_new(nbRes); if (*dataArrayP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; *numDataP = nbRes; for (i = 0 ; i < nbRes ; i++) { (*dataArrayP)[i].id = resList[i]; } } i = 0; do { result = prv_set_value((*dataArrayP) + i); i++; } while (i < *numDataP && result == COAP_205_CONTENT); return result; } static uint8_t prv_device_discover(uint16_t instanceId, int *numDataP, lwm2m_data_t **dataArrayP, lwm2m_object_t *objectP) { uint8_t result; int i; // this is a single instance object if (instanceId != 0) { return COAP_404_NOT_FOUND; } result = COAP_205_CONTENT; // is the server asking for the full object ? if (*numDataP == 0) { uint16_t resList[] = { RES_O_MANUFACTURER, RES_O_MODEL_NUMBER, RES_O_SERIAL_NUMBER, RES_O_FIRMWARE_VERSION, RES_M_REBOOT, RES_O_FACTORY_RESET, RES_O_AVL_POWER_SOURCES, RES_O_POWER_SOURCE_VOLTAGE, RES_O_POWER_SOURCE_CURRENT, RES_O_BATTERY_LEVEL, RES_O_MEMORY_FREE, RES_M_ERROR_CODE, RES_O_RESET_ERROR_CODE, RES_O_CURRENT_TIME, RES_O_UTC_OFFSET, RES_O_TIMEZONE, RES_M_BINDING_MODES }; int nbRes = sizeof(resList) / sizeof(uint16_t); *dataArrayP = lwm2m_data_new(nbRes); if (*dataArrayP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; *numDataP = nbRes; for (i = 0; i < nbRes; i++) { (*dataArrayP)[i].id = resList[i]; } } else { for (i = 0; i < *numDataP && result == COAP_205_CONTENT; i++) { switch ((*dataArrayP)[i].id) { case RES_O_MANUFACTURER: case RES_O_MODEL_NUMBER: case RES_O_SERIAL_NUMBER: case RES_O_FIRMWARE_VERSION: case RES_M_REBOOT: case RES_O_FACTORY_RESET: case RES_O_AVL_POWER_SOURCES: case RES_O_POWER_SOURCE_VOLTAGE: case RES_O_POWER_SOURCE_CURRENT: case RES_O_BATTERY_LEVEL: case RES_O_MEMORY_FREE: case RES_M_ERROR_CODE: case RES_O_RESET_ERROR_CODE: case RES_O_CURRENT_TIME: case RES_O_UTC_OFFSET: case RES_O_TIMEZONE: case RES_M_BINDING_MODES: break; default: result = COAP_404_NOT_FOUND; } } } return result; } static uint8_t prv_device_write(uint16_t instanceId, int numData, lwm2m_data_t *dataArray, lwm2m_object_t *objectP) { int i; uint8_t result; int64_t current_time; // this is a single instance object if (instanceId != 0) { return COAP_404_NOT_FOUND; } i = 0; do { switch (dataArray[i].id) { case RES_O_CURRENT_TIME: if (1 == lwm2m_data_decode_int(dataArray + i, ¤t_time)) { result = atiny_cmd_ioctl(ATINY_SET_CURRENT_TIME, (char *)¤t_time, sizeof(int64_t)); if(result == ATINY_OK) { return COAP_204_CHANGED; } else { return COAP_400_BAD_REQUEST; } } else { result = COAP_400_BAD_REQUEST; } break; case RES_O_UTC_OFFSET: if (1 == prv_check_time_offset((char *)dataArray[i].value.asBuffer.buffer, dataArray[i].value.asBuffer.length)) { result = atiny_cmd_ioctl(ATINY_SET_UTC_OFFSET, (char *)dataArray[i].value.asBuffer.buffer, dataArray[i].value.asBuffer.length); if(result == ATINY_OK) { return COAP_204_CHANGED; } else { return COAP_400_BAD_REQUEST; } } else { result = COAP_400_BAD_REQUEST; } break; case RES_O_TIMEZONE: result = atiny_cmd_ioctl(ATINY_SET_TIMEZONE, (char *)dataArray[i].value.asBuffer.buffer, dataArray[i].value.asBuffer.length); if(result == ATINY_OK) { return COAP_204_CHANGED; } else { return COAP_400_BAD_REQUEST; } //break; default: result = COAP_405_METHOD_NOT_ALLOWED; } i++; } while (i < numData && result == COAP_204_CHANGED); return result; } static uint8_t prv_device_execute(uint16_t instanceId, uint16_t resourceId, uint8_t *buffer, int length, lwm2m_object_t *objectP) { int result; // this is a single instance object if (instanceId != 0) { return COAP_404_NOT_FOUND; } if (length != 0) return COAP_400_BAD_REQUEST; switch (resourceId) { case RES_M_REBOOT: g_reboot = 1; return COAP_204_CHANGED; case RES_O_FACTORY_RESET: result = atiny_cmd_ioctl(ATINY_DO_FACTORY_RESET, NULL, 0); if(result == ATINY_OK) { return COAP_204_CHANGED; } else { return COAP_503_SERVICE_UNAVAILABLE; } case RES_O_RESET_ERROR_CODE: result = atiny_cmd_ioctl(ATINY_DO_RESET_DEV_ERR, NULL, 0); if(result == ATINY_OK) { return COAP_204_CHANGED; } else { return COAP_503_SERVICE_UNAVAILABLE; } default: return COAP_405_METHOD_NOT_ALLOWED; } } void display_device_object(lwm2m_object_t *object) { #ifdef WITH_LOGS #endif } lwm2m_object_t *get_object_device(atiny_param_t *atiny_params, const char *manufacturer) { /* * The get_object_device function create the object itself and return a pointer to the structure that represent it. */ lwm2m_object_t *deviceObj; deviceObj = (lwm2m_object_t *)lwm2m_malloc(sizeof(lwm2m_object_t)); if (NULL != deviceObj) { memset(deviceObj, 0, sizeof(lwm2m_object_t)); /* * It assigns his unique ID * The 3 is the standard ID for the mandatory object "Object device". */ deviceObj->objID = LWM2M_DEVICE_OBJECT_ID; /* * and its unique instance * */ deviceObj->instanceList = (lwm2m_list_t *)lwm2m_malloc(sizeof(lwm2m_list_t)); if (NULL != deviceObj->instanceList) { memset(deviceObj->instanceList, 0, sizeof(lwm2m_list_t)); } else { lwm2m_free(deviceObj); return NULL; } /* * And the private function that will access the object. * Those function will be called when a read/write/execute query is made by the server. In fact the library don't need to * know the resources of the object, only the server does. */ deviceObj->readFunc = prv_device_read; deviceObj->discoverFunc = prv_device_discover; deviceObj->writeFunc = prv_device_write; deviceObj->executeFunc = prv_device_execute; } return deviceObj; } void free_object_device(lwm2m_object_t *objectP) { if (NULL != objectP->userData) { lwm2m_free(objectP->userData); objectP->userData = NULL; } if (NULL != objectP->instanceList) { lwm2m_list_free(objectP->instanceList); objectP->instanceList = NULL; } lwm2m_free(objectP); } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/object_firmware.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Julien Vermillard - initial implementation * Fabien Fleutot - Please refer to git log * David Navarro, Intel Corporation - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - Please refer to git log * *******************************************************************************/ /* * This object is single instance only, and provide firmware upgrade functionality. * Object ID is 5. */ /* * resources: * 0 package write * 1 package url write * 2 update exec * 3 state read * 4 update supported objects read/write * 5 update result read */ #include "internals.h" #include "atiny_lwm2m/agenttiny.h" #include "log/atiny_log.h" #ifdef CONFIG_FEATURE_FOTA #include "atiny_fota_manager.h" // ---- private object "Firmware" specific defines ---- // Resource Id's: #define RES_M_PACKAGE 0 #define RES_M_PACKAGE_URI 1 #define RES_M_UPDATE 2 #define RES_M_STATE 3 #define RES_O_UPDATE_SUPPORTED_OBJECTS 4 #define RES_M_UPDATE_RESULT 5 #define RES_O_PKG_NAME 6 #define RES_O_PKG_VERSION 7 #define RES_O_FIRMWARE_UPDATE_DELIVER_METHOD 8 static uint8_t prv_firmware_read(uint16_t instanceId, int *numDataP, lwm2m_data_t **dataArrayP, lwm2m_data_cfg_t *dataCfg, lwm2m_object_t *objectP) { uint32_t i; uint8_t result; // this is a single instance object if (instanceId != 0) { return COAP_404_NOT_FOUND; } // is the server asking for the full object ? if (*numDataP == 0) { uint16_t resources[] = {RES_M_PACKAGE_URI, RES_M_STATE, RES_M_UPDATE_RESULT, RES_O_FIRMWARE_UPDATE_DELIVER_METHOD }; *dataArrayP = lwm2m_data_new(array_size(resources)); if (*dataArrayP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; *numDataP = array_size(resources); for(i = 0 ; i < array_size(resources); ++i) { (*dataArrayP)[i].id = resources[i]; } } i = 0; do { switch ((*dataArrayP)[i].id) { case RES_M_PACKAGE: result = COAP_405_METHOD_NOT_ALLOWED; break; case RES_M_PACKAGE_URI: { #ifdef CONFIG_FEATURE_FOTA const char *pkg_uri; pkg_uri = atiny_fota_manager_get_pkg_uri(atiny_fota_manager_get_instance()); if(pkg_uri == NULL) { pkg_uri = ""; } lwm2m_data_encode_nstring(pkg_uri, strlen(pkg_uri) + 1, *dataArrayP + i); result = COAP_205_CONTENT; #else result = COAP_405_METHOD_NOT_ALLOWED; #endif break; } case RES_M_UPDATE: result = COAP_405_METHOD_NOT_ALLOWED; break; case RES_M_STATE: // firmware update state (int) { #ifdef CONFIG_FEATURE_FOTA int state = atiny_fota_manager_get_rpt_state(atiny_fota_manager_get_instance()); lwm2m_data_encode_int(state, *dataArrayP + i); result = COAP_205_CONTENT; #else result = COAP_405_METHOD_NOT_ALLOWED; #endif break; } case RES_M_UPDATE_RESULT: { #ifdef CONFIG_FEATURE_FOTA int updateresult = atiny_fota_manager_get_update_result(atiny_fota_manager_get_instance()); lwm2m_data_encode_int(updateresult, *dataArrayP + i); result = COAP_205_CONTENT; #else result = COAP_405_METHOD_NOT_ALLOWED; #endif break; } case RES_O_FIRMWARE_UPDATE_DELIVER_METHOD: { #ifdef CONFIG_FEATURE_FOTA int method = atiny_fota_manager_get_deliver_method(atiny_fota_manager_get_instance()); lwm2m_data_encode_int(method, *dataArrayP + i); result = COAP_205_CONTENT; #else result = COAP_405_METHOD_NOT_ALLOWED; #endif } break; default: result = COAP_404_NOT_FOUND; } i++; } while (i < *numDataP && result == COAP_205_CONTENT); #ifdef CONFIG_FEATURE_FOTA if(dataCfg && (1 == *numDataP) && (RES_M_STATE == (*dataArrayP)[0].id)) { atiny_fota_manager_get_data_cfg(atiny_fota_manager_get_instance(), dataCfg); } #endif return result; } static uint8_t prv_firmware_write(uint16_t instanceId, int numData, lwm2m_data_t *dataArray, lwm2m_object_t *objectP) { int i; uint8_t result; // this is a single instance object if (instanceId != 0) { return COAP_404_NOT_FOUND; } i = 0; do { switch (dataArray[i].id) { case RES_M_PACKAGE_URI: // URL for download the firmware { int ret; if(dataArray[i].type != LWM2M_TYPE_STRING || NULL == dataArray[i].value.asBuffer.buffer) { ATINY_LOG(LOG_ERR, "type ERR %d", dataArray[i].type); result = COAP_400_BAD_REQUEST; break; } #ifdef CONFIG_FEATURE_FOTA ret = atiny_fota_manager_start_download(atiny_fota_manager_get_instance(), \ (const char *)(dataArray[i].value.asBuffer.buffer), dataArray[i].value.asBuffer.length); #else ret = ATINY_ERR; #endif result = (ATINY_OK == ret ? COAP_204_CHANGED : COAP_405_METHOD_NOT_ALLOWED); break; } default: result = COAP_405_METHOD_NOT_ALLOWED; } i++; } while (i < numData && result == COAP_204_CHANGED); return result; } static uint8_t prv_firmware_execute(uint16_t instanceId, uint16_t resourceId, uint8_t *buffer, int length, lwm2m_object_t *objectP) { // this is a single instance object if (instanceId != 0) { return COAP_404_NOT_FOUND; } if (length != 0) return COAP_400_BAD_REQUEST; // for execute callback, resId is always set. switch (resourceId) { case RES_M_UPDATE: { #ifdef CONFIG_FEATURE_FOTA int ret = atiny_fota_manager_execute_update(atiny_fota_manager_get_instance()); #else int ret = ATINY_ERR; #endif if (ATINY_OK == ret) { return COAP_204_CHANGED; } else { // firmware update already running #ifdef CONFIG_FEATURE_FOTA return COAP_400_BAD_REQUEST; #else return COAP_405_METHOD_NOT_ALLOWED; #endif } } default: return COAP_405_METHOD_NOT_ALLOWED; } } lwm2m_object_t *get_object_firmware(atiny_param_t *atiny_params) { /* * The get_object_firmware function create the object itself and return a pointer to the structure that represent it. */ lwm2m_object_t *firmwareObj; firmwareObj = (lwm2m_object_t *)lwm2m_malloc(sizeof(lwm2m_object_t)); if (NULL != firmwareObj) { memset(firmwareObj, 0, sizeof(lwm2m_object_t)); /* * It assigns its unique ID * The 5 is the standard ID for the optional object "Object firmware". */ firmwareObj->objID = LWM2M_FIRMWARE_UPDATE_OBJECT_ID; /* * and its unique instance * */ firmwareObj->instanceList = (lwm2m_list_t *)lwm2m_malloc(sizeof(lwm2m_list_t)); if (NULL != firmwareObj->instanceList) { memset(firmwareObj->instanceList, 0, sizeof(lwm2m_list_t)); } else { lwm2m_free(firmwareObj); return NULL; } /* * And the private function that will access the object. * Those function will be called when a read/write/execute query is made by the server. In fact the library don't need to * know the resources of the object, only the server does. */ firmwareObj->readFunc = prv_firmware_read; firmwareObj->writeFunc = prv_firmware_write; firmwareObj->executeFunc = prv_firmware_execute; firmwareObj->userData = NULL; /* * Also some user data can be stored in the object with a private structure containing the needed variables */ } return firmwareObj; } void free_object_firmware(lwm2m_object_t *objectP) { if (NULL != objectP->userData) { lwm2m_free(objectP->userData); objectP->userData = NULL; } if (NULL != objectP->instanceList) { lwm2m_free(objectP->instanceList); objectP->instanceList = NULL; } lwm2m_free(objectP); } #else lwm2m_object_t *get_object_firmware(atiny_param_t *atiny_params) { (void)atiny_params; return NULL; } void free_object_firmware(lwm2m_object_t *objectP) { (void)objectP; } #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/object_location.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2014 Bosch Software Innovations GmbH, Germany. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - Please refer to git log * ******************************************************************************/ /*! \file LWM2M object "Location" implementation \author Joerg Hubschneider */ /* * Object | | Multiple | | Description | * Name | ID | Instances |Mand.| | *-------------+------+-----------+-----+-------------------------------+ * Location | 6 | No | No | see TS E.7 page 101 | * * Resources: * Name | ID | Oper.|Instances|Mand.| Type | Range | Units | Description | * -------------+-----+------+---------+-----+---------+-------+-------+----------------------------------------------------------------------------------+ * Latitude | 0 | R | Single | Yes | Float | | Deg | The decimal notation of latitude e.g. - 45.5723 [Worlds Geodetic System 1984].| * Longitude | 1 | R | Single | Yes | Float | | Deg | The decimal notation of longitude e.g. - 153.21760 [Worlds Geodetic System 1984].| * Altitude | 2 | R | Single | No | Float | | m | The decimal notation of altitude in meters above sea level. | * Radius | 3 | R | Single | No | Float | | m | The value in the Radius Resource indicates the size in meters of a circular area | * | | | | | | | | around a point of geometry. | * Velocity | 4 | R | Single | No | Opaque | | * | The velocity of the device as defined in 3GPP 23.032 GAD specification(*). | * | | | | | | | | This set of values may not be available if the device is static. | * | | | | | | | | opaque: see OMA_TS 6.3.2 | * Timestamp | 5 | R | Single | Yes | Time | | s | The timestamp when the location measurement was performed. | * Speed | 6 | R | Single | No | Float | | m/s | Speed is the time rate of change in position of a LwM2M Client without regard | * | | | | | | | | for direction: the scalar component of velocity. | */ #include "internals.h" #include "object_comm.h" #ifdef LWM2M_CLIENT_MODE // ---- private "object location" specific defines ---- // Resource Id's: #define RES_M_LATITUDE 0 #define RES_M_LONGITUDE 1 #define RES_O_ALTITUDE 2 #define RES_O_RADIUS 3 #define RES_O_VELOCITY 4 #define RES_M_TIMESTAMP 5 #define RES_O_SPEED 6 /** implementation for all read-able resources */ static uint8_t prv_res2tlv(lwm2m_data_t *dataP) { //-------------------------------------------------------------------- JH -- uint8_t ret = COAP_205_CONTENT; float get_value; uint64_t timestamp; atiny_velocity_s velocity; switch (dataP->id) // location resourceId { case RES_M_LATITUDE: if (atiny_cmd_ioctl(ATINY_GET_LATITUDE, (char *)&get_value, sizeof(float)) == ATINY_OK) { lwm2m_data_encode_float(get_value, dataP); } else { ret = COAP_400_BAD_REQUEST; } break; case RES_M_LONGITUDE: if (atiny_cmd_ioctl(ATINY_GET_LONGITUDE, (char *)&get_value, sizeof(float)) == ATINY_OK) { lwm2m_data_encode_float(get_value, dataP); } else { ret = COAP_400_BAD_REQUEST; } break; case RES_O_ALTITUDE: if (atiny_cmd_ioctl(ATINY_GET_ALTITUDE, (char *)&get_value, sizeof(float)) == ATINY_OK) { lwm2m_data_encode_float(get_value, dataP); } else { ret = COAP_400_BAD_REQUEST; } break; case RES_O_RADIUS: if (atiny_cmd_ioctl(ATINY_GET_RADIUS, (char *)&get_value, sizeof(float)) == ATINY_OK) { lwm2m_data_encode_float(get_value, dataP); } else { ret = COAP_400_BAD_REQUEST; } break; case RES_O_VELOCITY: if (atiny_cmd_ioctl(ATINY_GET_VELOCITY, (char *)&velocity, sizeof(velocity)) == ATINY_OK) { lwm2m_data_encode_opaque(velocity.opaque, velocity.length, dataP); } else { ret = COAP_400_BAD_REQUEST; } break; case RES_M_TIMESTAMP: if (atiny_cmd_ioctl(ATINY_GET_TIMESTAMP, (char *)×tamp, sizeof(uint64_t)) == ATINY_OK) { lwm2m_data_encode_float(timestamp, dataP); } else { ret = COAP_400_BAD_REQUEST; } break; case RES_O_SPEED: if (atiny_cmd_ioctl(ATINY_GET_SPEED, (char *)&get_value, sizeof(float)) == ATINY_OK) { lwm2m_data_encode_float(get_value, dataP); } else { ret = COAP_400_BAD_REQUEST; } break; default: ret = COAP_404_NOT_FOUND; break; } return ret; } /** * Implementation (callback-) function of reading object resources. For whole * object, single resources or a sequence of resources * see 3GPP TS 23.032 V11.0.0(2012-09) page 23,24. * implemented for: HORIZONTAL_VELOCITY_WITH_UNCERTAINT * @param objInstId in, instances ID of the location object to read * @param numDataP in/out, pointer to the number of resource to read. 0 is the * exception for all readable resource of object instance * @param tlvArrayP in/out, TLV data sequence with initialized resource ID to read * @param objectP in, private location data structure */ static uint8_t prv_location_read(uint16_t objInstId, int *numDataP, lwm2m_data_t **tlvArrayP, lwm2m_data_cfg_t *dataCfg, lwm2m_object_t *objectP) { //-------------------------------------------------------------------- JH -- int i; uint8_t result = COAP_500_INTERNAL_SERVER_ERROR; // defined as single instance object! if (objInstId != 0) return COAP_404_NOT_FOUND; if (*numDataP == 0) // full object, readable resources! { uint16_t readResIds[] = { RES_M_LATITUDE, RES_M_LONGITUDE, RES_O_ALTITUDE, RES_O_RADIUS, RES_O_VELOCITY, RES_M_TIMESTAMP, RES_O_SPEED }; // readable resources! *numDataP = sizeof(readResIds) / sizeof(uint16_t); *tlvArrayP = lwm2m_data_new(*numDataP); if (*tlvArrayP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; // init readable resource id's for (i = 0 ; i < *numDataP ; i++) { (*tlvArrayP)[i].id = readResIds[i]; } } for (i = 0 ; i < *numDataP ; i++) { result = prv_res2tlv ((*tlvArrayP) + i); if (result != COAP_205_CONTENT) break; } return result; } void display_location_object(lwm2m_object_t *object) { #ifdef WITH_LOGS float latitude = 0.0f; float longitude = 0.0f; float altitude = 0.0f; float radius = 0.0f; float speed = 0.0f; uint64_t timestamp = 0U; (void)atiny_cmd_ioctl(ATINY_GET_LATITUDE, &latitude, sizeof(float)); (void)atiny_cmd_ioctl(ATINY_GET_LONGITUDE, &longitude, sizeof(float)); (void)atiny_cmd_ioctl(ATINY_GET_ALTITUDE, &altitude, sizeof(float)); (void)atiny_cmd_ioctl(ATINY_GET_RADIUS, &radius, sizeof(float)); (void)atiny_cmd_ioctl(ATINY_GET_SPEED, &speed, sizeof(float)); (void)atiny_cmd_ioctl(ATINY_GET_TIMESTAMP, ×tamp, sizeof(uint64_t)); fprintf(stdout, " /%u: Location object:\r\n", object->objID); fprintf(stdout, " latitude: %.6f, longitude: %.6f, altitude: %.6f, radius: %.6f, timestamp: %lu, speed: %.6f\r\n", latitude, longitude, altitude, radius, timestamp, speed); #endif } /** * This function creates the LWM2M Location. * @return gives back allocated LWM2M data object structure pointer. On error, * NULL value is returned. */ lwm2m_object_t *get_object_location(void) { //-------------------------------------------------------------------- JH -- lwm2m_object_t *locationObj; locationObj = (lwm2m_object_t *)lwm2m_malloc(sizeof(lwm2m_object_t)); if (NULL != locationObj) { memset(locationObj, 0, sizeof(lwm2m_object_t)); // It assigns its unique ID // The 6 is the standard ID for the optional object "Location". locationObj->objID = LWM2M_LOCATION_OBJECT_ID; // and its unique instance locationObj->instanceList = (lwm2m_list_t *)lwm2m_malloc(sizeof(lwm2m_list_t)); if (NULL != locationObj->instanceList) { memset(locationObj->instanceList, 0, sizeof(lwm2m_list_t)); } else { lwm2m_free(locationObj); return NULL; } // And the private function that will access the object. // Those function will be called when a read query is made by the server. // In fact the library don't need to know the resources of the object, only the server does. // locationObj->readFunc = prv_location_read; } return locationObj; } void free_object_location(lwm2m_object_t *object) { lwm2m_list_free(object->instanceList); lwm2m_free(object->userData); lwm2m_free(object); } #endif //LWM2M_CLIENT_MODE ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/object_security.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - Please refer to git log * Ville Skytt? - Please refer to git log * *******************************************************************************/ /* * Resources: * * Name | ID | Operations | Instances | Mandatory | Type | Range | Units | * Server URI | 0 | | Single | Yes | String | | | * Bootstrap Server | 1 | | Single | Yes | Boolean | | | * Security Mode | 2 | | Single | Yes | Integer | 0-3 | | * Public Key or ID | 3 | | Single | Yes | Opaque | | | * Server Public Key or ID | 4 | | Single | Yes | Opaque | | | * Secret Key | 5 | | Single | Yes | Opaque | | | * SMS Security Mode | 6 | | Single | No | Integer | 0-255 | | * SMS Binding Key Param. | 7 | | Single | No | Opaque | 6 B | | * SMS Binding Secret Keys | 8 | | Single | No | Opaque | 32-48 B | | * Server SMS Number | 9 | | Single | No | String | | | * Short Server ID | 10 | | Single | No | Integer | 1-65535 | | * Client Hold Off Time | 11 | | Single | No | Integer | | s | * BS Account Timeout | 12 | | Single | No | Integer | | s | * */ /* * Here we implement a very basic LWM2M Security Object which only knows NoSec security mode. */ #include "internals.h" #include "object_comm.h" static uint8_t prv_get_value(lwm2m_data_t *dataP, security_instance_t *targetP) { switch (dataP->id) { case LWM2M_SECURITY_URI_ID: lwm2m_data_encode_string(targetP->uri, dataP); return COAP_205_CONTENT; case LWM2M_SECURITY_BOOTSTRAP_ID: lwm2m_data_encode_bool(targetP->isBootstrap, dataP); return COAP_205_CONTENT; case LWM2M_SECURITY_SECURITY_ID: lwm2m_data_encode_int(targetP->securityMode, dataP); return COAP_205_CONTENT; case LWM2M_SECURITY_PUBLIC_KEY_ID: lwm2m_data_encode_opaque((uint8_t *)targetP->publicIdentity, targetP->publicIdLen, dataP); return COAP_205_CONTENT; case LWM2M_SECURITY_SERVER_PUBLIC_KEY_ID: lwm2m_data_encode_opaque((uint8_t *)targetP->serverPublicKey, targetP->serverPublicKeyLen, dataP); return COAP_205_CONTENT; case LWM2M_SECURITY_SECRET_KEY_ID: lwm2m_data_encode_opaque((uint8_t *)targetP->secretKey, targetP->secretKeyLen, dataP); return COAP_205_CONTENT; case LWM2M_SECURITY_SMS_SECURITY_ID: lwm2m_data_encode_int(targetP->smsSecurityMode, dataP); return COAP_205_CONTENT; case LWM2M_SECURITY_SMS_KEY_PARAM_ID: lwm2m_data_encode_opaque((uint8_t *)targetP->smsParams, targetP->smsParamsLen, dataP); return COAP_205_CONTENT; case LWM2M_SECURITY_SMS_SECRET_KEY_ID: lwm2m_data_encode_opaque((uint8_t *)targetP->smsSecret, targetP->smsSecretLen, dataP); return COAP_205_CONTENT; case LWM2M_SECURITY_SMS_SERVER_NUMBER_ID: lwm2m_data_encode_int(0, dataP); return COAP_205_CONTENT; case LWM2M_SECURITY_SHORT_SERVER_ID: lwm2m_data_encode_int(targetP->shortID, dataP); return COAP_205_CONTENT; case LWM2M_SECURITY_HOLD_OFF_ID: lwm2m_data_encode_int(targetP->clientHoldOffTime, dataP); return COAP_205_CONTENT; case LWM2M_SECURITY_BOOTSTRAP_TIMEOUT_ID: lwm2m_data_encode_int(targetP->bootstrapServerAccountTimeout, dataP); return COAP_205_CONTENT; default: return COAP_404_NOT_FOUND; } } static uint8_t prv_security_read(uint16_t instanceId, int *numDataP, lwm2m_data_t **dataArrayP, lwm2m_data_cfg_t *dataCfg, lwm2m_object_t *objectP) { security_instance_t *targetP; uint8_t result; int i; targetP = (security_instance_t *)lwm2m_list_find(objectP->instanceList, instanceId); if (NULL == targetP) return COAP_404_NOT_FOUND; // is the server asking for the full instance ? if (*numDataP == 0) { uint16_t resList[] = {LWM2M_SECURITY_URI_ID, LWM2M_SECURITY_BOOTSTRAP_ID, LWM2M_SECURITY_SECURITY_ID, LWM2M_SECURITY_PUBLIC_KEY_ID, LWM2M_SECURITY_SERVER_PUBLIC_KEY_ID, LWM2M_SECURITY_SECRET_KEY_ID, LWM2M_SECURITY_SMS_SECURITY_ID, LWM2M_SECURITY_SMS_KEY_PARAM_ID, LWM2M_SECURITY_SMS_SECRET_KEY_ID, LWM2M_SECURITY_SMS_SERVER_NUMBER_ID, LWM2M_SECURITY_SHORT_SERVER_ID, LWM2M_SECURITY_HOLD_OFF_ID, LWM2M_SECURITY_BOOTSTRAP_TIMEOUT_ID }; int nbRes = sizeof(resList) / sizeof(uint16_t); *dataArrayP = lwm2m_data_new(nbRes); if (*dataArrayP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; *numDataP = nbRes; for (i = 0 ; i < nbRes ; i++) { (*dataArrayP)[i].id = resList[i]; } } i = 0; do { result = prv_get_value((*dataArrayP) + i, targetP); i++; } while (i < *numDataP && result == COAP_205_CONTENT); return result; } #ifdef LWM2M_BOOTSTRAP static uint8_t prv_security_write(uint16_t instanceId, int numData, lwm2m_data_t *dataArray, lwm2m_object_t *objectP) { security_instance_t *targetP; int i; uint8_t result = COAP_204_CHANGED; targetP = (security_instance_t *)lwm2m_list_find(objectP->instanceList, instanceId); if (NULL == targetP) { return COAP_404_NOT_FOUND; } i = 0; do { switch (dataArray[i].id) { case LWM2M_SECURITY_URI_ID: if (targetP->uri != NULL) lwm2m_free(targetP->uri); targetP->uri = (char *)lwm2m_malloc(dataArray[i].value.asBuffer.length + 1); if (targetP->uri != NULL) { memset(targetP->uri, 0, dataArray[i].value.asBuffer.length + 1); strncpy(targetP->uri, (char *)dataArray[i].value.asBuffer.buffer, dataArray[i].value.asBuffer.length); result = COAP_204_CHANGED; } else { result = COAP_500_INTERNAL_SERVER_ERROR; } break; case LWM2M_SECURITY_BOOTSTRAP_ID: if (1 == lwm2m_data_decode_bool(dataArray + i, &(targetP->isBootstrap))) { result = COAP_204_CHANGED; } else { result = COAP_400_BAD_REQUEST; } break; case LWM2M_SECURITY_SECURITY_ID: { int64_t value; if (1 == lwm2m_data_decode_int(dataArray + i, &value)) { if (value >= 0 && value <= 3) { targetP->securityMode = value; result = COAP_204_CHANGED; } else { result = COAP_406_NOT_ACCEPTABLE; } } else { result = COAP_400_BAD_REQUEST; } } break; case LWM2M_SECURITY_PUBLIC_KEY_ID: if (targetP->publicIdentity != NULL) lwm2m_free(targetP->publicIdentity); targetP->publicIdentity = (char *)lwm2m_malloc(dataArray[i].value.asBuffer.length + 1); if (targetP->publicIdentity != NULL) { memset(targetP->publicIdentity, 0, dataArray[i].value.asBuffer.length + 1); memcpy(targetP->publicIdentity, (char *)dataArray[i].value.asBuffer.buffer, dataArray[i].value.asBuffer.length); targetP->publicIdLen = dataArray[i].value.asBuffer.length; result = COAP_204_CHANGED; } else { result = COAP_500_INTERNAL_SERVER_ERROR; } break; case LWM2M_SECURITY_SERVER_PUBLIC_KEY_ID: if (targetP->serverPublicKey != NULL) lwm2m_free(targetP->serverPublicKey); targetP->serverPublicKey = (char *)lwm2m_malloc(dataArray[i].value.asBuffer.length + 1); if (targetP->serverPublicKey != NULL) { memset(targetP->serverPublicKey, 0, dataArray[i].value.asBuffer.length + 1); memcpy(targetP->serverPublicKey, (char *)dataArray[i].value.asBuffer.buffer, dataArray[i].value.asBuffer.length); targetP->serverPublicKeyLen = dataArray[i].value.asBuffer.length; result = COAP_204_CHANGED; } else { result = COAP_500_INTERNAL_SERVER_ERROR; } break; case LWM2M_SECURITY_SECRET_KEY_ID: if (targetP->secretKey != NULL) lwm2m_free(targetP->secretKey); targetP->secretKey = (char *)lwm2m_malloc(dataArray[i].value.asBuffer.length + 1); if (targetP->secretKey != NULL) { memset(targetP->secretKey, 0, dataArray[i].value.asBuffer.length + 1); memcpy(targetP->secretKey, (char *)dataArray[i].value.asBuffer.buffer, dataArray[i].value.asBuffer.length); targetP->secretKeyLen = dataArray[i].value.asBuffer.length; result = COAP_204_CHANGED; } else { result = COAP_500_INTERNAL_SERVER_ERROR; } break; case LWM2M_SECURITY_SMS_SECURITY_ID: // Let just ignore this result = COAP_204_CHANGED; break; case LWM2M_SECURITY_SMS_KEY_PARAM_ID: // Let just ignore this result = COAP_204_CHANGED; break; case LWM2M_SECURITY_SMS_SECRET_KEY_ID: // Let just ignore this result = COAP_204_CHANGED; break; case LWM2M_SECURITY_SMS_SERVER_NUMBER_ID: // Let just ignore this result = COAP_204_CHANGED; break; case LWM2M_SECURITY_SHORT_SERVER_ID: { int64_t value; if (1 == lwm2m_data_decode_int(dataArray + i, &value)) { if (value >= 0 && value <= 0xFFFF) { targetP->shortID = value; result = COAP_204_CHANGED; } else { result = COAP_406_NOT_ACCEPTABLE; } } else { result = COAP_400_BAD_REQUEST; } } break; case LWM2M_SECURITY_HOLD_OFF_ID: { int64_t value; if (1 == lwm2m_data_decode_int(dataArray + i, &value)) { if (value >= 0 && value <= UINT32_MAX) { targetP->clientHoldOffTime = value; result = COAP_204_CHANGED; } else { result = COAP_406_NOT_ACCEPTABLE; } } else { result = COAP_400_BAD_REQUEST; } break; } case LWM2M_SECURITY_BOOTSTRAP_TIMEOUT_ID: { int64_t value; if (1 == lwm2m_data_decode_int(dataArray + i, &value)) { if (value >= 0 && value <= UINT32_MAX) { targetP->bootstrapServerAccountTimeout = value; result = COAP_204_CHANGED; } else { result = COAP_406_NOT_ACCEPTABLE; } } else { result = COAP_400_BAD_REQUEST; } break; } default: return COAP_400_BAD_REQUEST; } i++; } while (i < numData && result == COAP_204_CHANGED); return result; } static uint8_t prv_security_delete(uint16_t id, lwm2m_object_t *objectP) { security_instance_t *targetP; objectP->instanceList = lwm2m_list_remove(objectP->instanceList, id, (lwm2m_list_t **)&targetP); if (NULL == targetP) return COAP_404_NOT_FOUND; if (NULL != targetP->uri) { lwm2m_free(targetP->uri); } lwm2m_free(targetP); return COAP_202_DELETED; } static uint8_t prv_security_create(uint16_t instanceId, int numData, lwm2m_data_t *dataArray, lwm2m_object_t *objectP) { security_instance_t *targetP; uint8_t result; targetP = (security_instance_t *)lwm2m_malloc(sizeof(security_instance_t)); if (NULL == targetP) return COAP_500_INTERNAL_SERVER_ERROR; memset(targetP, 0, sizeof(security_instance_t)); targetP->instanceId = instanceId; objectP->instanceList = LWM2M_LIST_ADD(objectP->instanceList, targetP); result = prv_security_write(instanceId, numData, dataArray, objectP); if (result != COAP_204_CHANGED) { (void)prv_security_delete(instanceId, objectP); } else { result = COAP_201_CREATED; } return result; } #endif void copy_security_object(lwm2m_object_t *objectDest, lwm2m_object_t *objectSrc) { security_instance_t *instanceSrc; security_instance_t *previousInstanceDest = NULL; memcpy(objectDest, objectSrc, sizeof(lwm2m_object_t)); objectDest->instanceList = NULL; objectDest->userData = NULL; instanceSrc = (security_instance_t *)objectSrc->instanceList; while (instanceSrc != NULL) { security_instance_t *instanceDest = (security_instance_t *)lwm2m_malloc(sizeof(security_instance_t)); if (NULL == instanceDest) { return; } memcpy(instanceDest, instanceSrc, sizeof(security_instance_t)); instanceDest->uri = (char *)lwm2m_malloc(strlen(instanceSrc->uri) + 1); if (instanceDest->uri == NULL) { lwm2m_free(instanceDest); return; } strncpy(instanceDest->uri, instanceSrc->uri, strlen(instanceSrc->uri) + 1); if (instanceSrc->securityMode == LWM2M_SECURITY_MODE_PRE_SHARED_KEY) { instanceDest->publicIdentity = lwm2m_strdup(instanceSrc->publicIdentity); instanceDest->secretKey = lwm2m_strdup(instanceSrc->secretKey); } instanceSrc = (security_instance_t *)instanceSrc->next; if (previousInstanceDest == NULL) { objectDest->instanceList = (lwm2m_list_t *)instanceDest; } else { previousInstanceDest->next = instanceDest; } previousInstanceDest = instanceDest; } } void display_security_object(lwm2m_object_t *object) { #ifdef WITH_LOGS fprintf(stdout, " /%u: Security object, instances:\r\n", object->objID); security_instance_t *instance = (security_instance_t *)object->instanceList; while (instance != NULL) { fprintf(stdout, " /%u/%u: instanceId: %u, uri: %s, isBootstrap: %s, shortId: %u, clientHoldOffTime: %u\r\n", object->objID, instance->instanceId, instance->instanceId, instance->uri, instance->isBootstrap ? "true" : "false", instance->shortID, instance->clientHoldOffTime); instance = (security_instance_t *)instance->next; } #endif } void clean_security_object(lwm2m_object_t *objectP) { if(NULL == objectP) { return; } while (objectP->instanceList != NULL) { security_instance_t *securityInstance = (security_instance_t *)objectP->instanceList; objectP->instanceList = objectP->instanceList->next; if (NULL != securityInstance->uri) { lwm2m_free(securityInstance->uri); } if (securityInstance->securityMode == LWM2M_SECURITY_MODE_PRE_SHARED_KEY) { lwm2m_free(securityInstance->publicIdentity); lwm2m_free(securityInstance->secretKey); } lwm2m_free(securityInstance); } lwm2m_free(objectP); } /* * modify date: 2018-06-25 * description: add one or two instance for security object. id 0 for iot server(uri,psk), id 1 for bs server. * return: a object: lwm2m_object_t * pay attention: */ lwm2m_object_t *get_security_object(uint16_t serverId, atiny_param_t *atiny_params, lwm2m_context_t *lwm2m_context) { //const int URI_MAX_LEN = 64; #define URI_MAX_LEN 64 lwm2m_object_t *securityObj = NULL; char serverUri[URI_MAX_LEN]; security_instance_t *targetP = NULL; int i = 0; char *bsPskId = NULL; char *psk = NULL; uint16_t pskLen = 0; const uint8_t INS_IOT_SERVER_FLAG = 0x01; const uint8_t INS_BS_SERVER_FLAG = 0x02; uint8_t ins_flag = 0x00; uint8_t total_ins = 1; uint8_t security_params_index = 0; switch(atiny_params->server_params.bootstrap_mode) { case BOOTSTRAP_FACTORY: ins_flag |= INS_IOT_SERVER_FLAG; total_ins = 1; break; case BOOTSTRAP_SEQUENCE: if ((atiny_params->security_params[0].server_ip != NULL) && (atiny_params->security_params[0].server_port != NULL)) { ins_flag |= INS_IOT_SERVER_FLAG; ins_flag |= INS_BS_SERVER_FLAG; total_ins = 2; } else { ins_flag |= INS_BS_SERVER_FLAG; total_ins = 1; } break; case BOOTSTRAP_CLIENT_INITIATED: ins_flag |= INS_BS_SERVER_FLAG; total_ins = 1; break; default: return NULL; //break; } securityObj = (lwm2m_object_t *)lwm2m_malloc(sizeof(lwm2m_object_t)); if (NULL == securityObj) { return NULL; } memset(securityObj, 0, sizeof(lwm2m_object_t)); securityObj->objID = LWM2M_SECURITY_OBJECT_ID; //at most, have two instance. in fact for(i = 0; i < total_ins; i++) { //Manually create an hardcoded instance targetP = (security_instance_t *)lwm2m_malloc(sizeof(security_instance_t)); if (NULL == targetP) { //lwm2m_free(securityObj); clean_security_object(securityObj); return NULL; } memset(targetP, 0, sizeof(security_instance_t)); if((ins_flag & INS_IOT_SERVER_FLAG) && (ins_flag & INS_BS_SERVER_FLAG)) { targetP->instanceId = i; //i=0 for iot_server, i=1 for bs_server targetP->isBootstrap = ((i == 0) ? (false) : (true)); security_params_index = i; } else { if(ins_flag & INS_IOT_SERVER_FLAG) { targetP->instanceId = 0; targetP->isBootstrap = false; security_params_index = 0; } else //if(ins_flag & INS_BS_SERVER_FLAG) //even if not set INS_BS_SERVER_FLAG, still run in a certain process. { targetP->instanceId = 1; targetP->isBootstrap = true; security_params_index = 1; } } // After instance id is initialized securityObj->instanceList = LWM2M_LIST_ADD(securityObj->instanceList, targetP); bsPskId = atiny_params->security_params[security_params_index].psk_Id; psk = atiny_params->security_params[security_params_index].psk; pskLen = atiny_params->security_params[security_params_index].psk_len; if (atiny_params->security_params[security_params_index].server_ip && atiny_params->security_params[security_params_index].server_port) { if (psk != NULL) { (void)atiny_snprintf(serverUri, URI_MAX_LEN, "coaps://%s:%s", atiny_params->security_params[security_params_index].server_ip, atiny_params->security_params[security_params_index].server_port); } else { (void)atiny_snprintf(serverUri, URI_MAX_LEN, "coap://%s:%s", atiny_params->security_params[security_params_index].server_ip, atiny_params->security_params[security_params_index].server_port); } } else { serverUri[0] = '\0'; } targetP->uri = (char *)lwm2m_strdup(serverUri); if (NULL == targetP->uri) { //lwm2m_free(securityObj); //lwm2m_free(targetP); clean_security_object(securityObj); return NULL; } targetP->securityMode = LWM2M_SECURITY_MODE_NONE; if (bsPskId != NULL && psk != NULL) { targetP->securityMode = LWM2M_SECURITY_MODE_PRE_SHARED_KEY; targetP->publicIdentity = (char *)lwm2m_strdup(bsPskId); if(targetP->publicIdentity == NULL) { clean_security_object(securityObj); return NULL; } targetP->publicIdLen = strlen(bsPskId); if (pskLen > 0) { targetP->secretKey = (char *)lwm2m_malloc(pskLen); if (targetP->secretKey == NULL) { clean_security_object(securityObj); return NULL; } memcpy(targetP->secretKey, psk, pskLen); targetP->secretKeyLen = pskLen; } } targetP->shortID = serverId; //10? is suitable? it could be changed by the bs server. for lwm2m_server_t member lifetime. targetP->clientHoldOffTime = atiny_params->server_params.hold_off_time; } //end for loop securityObj->readFunc = prv_security_read; #ifdef LWM2M_BOOTSTRAP securityObj->writeFunc = prv_security_write; securityObj->createFunc = prv_security_create; securityObj->deleteFunc = prv_security_delete; #endif return securityObj; } /********************* Security Obj Helpers **********************/ char *security_get_uri(lwm2m_object_t *objectP, uint16_t secObjInstID) { security_instance_t *targetP = (security_instance_t *)LWM2M_LIST_FIND(objectP->instanceList, secObjInstID); if (NULL != targetP) { return lwm2m_strdup(targetP->uri); } return NULL; } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/object_server.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Julien Vermillard, Sierra Wireless * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - Please refer to git log * *******************************************************************************/ /* * Resources: * * Name | ID | Operations | Instances | Mandatory | Type | Range | Units | * Short ID | 0 | R | Single | Yes | Integer | 1-65535 | | * Lifetime | 1 | R/W | Single | Yes | Integer | | s | * Default Min Period | 2 | R/W | Single | No | Integer | | s | * Default Max Period | 3 | R/W | Single | No | Integer | | s | * Disable | 4 | E | Single | No | | | | * Disable Timeout | 5 | R/W | Single | No | Integer | | s | * Notification Storing | 6 | R/W | Single | Yes | Boolean | | | * Binding | 7 | R/W | Single | Yes | String | | | * Registration Update | 8 | E | Single | Yes | | | | * */ #include "internals.h" #include "object_comm.h" typedef struct _server_instance_ { struct _server_instance_ *next; // matches lwm2m_list_t::next uint16_t instanceId; // matches lwm2m_list_t::id uint16_t shortServerId; uint32_t lifetime; uint32_t defaultMinPeriod; uint32_t defaultMaxPeriod; uint32_t disableTimeout; bool storing; char binding[4]; } server_instance_t; static uint8_t prv_get_value(lwm2m_data_t *dataP, server_instance_t *targetP) { switch (dataP->id) { case LWM2M_SERVER_SHORT_ID_ID: lwm2m_data_encode_int(targetP->shortServerId, dataP); return COAP_205_CONTENT; case LWM2M_SERVER_LIFETIME_ID: lwm2m_data_encode_int(targetP->lifetime, dataP); return COAP_205_CONTENT; case LWM2M_SERVER_MIN_PERIOD_ID: lwm2m_data_encode_int(targetP->defaultMinPeriod, dataP); return COAP_205_CONTENT; case LWM2M_SERVER_MAX_PERIOD_ID: lwm2m_data_encode_int(targetP->defaultMaxPeriod, dataP); return COAP_205_CONTENT; case LWM2M_SERVER_DISABLE_ID: return COAP_405_METHOD_NOT_ALLOWED; case LWM2M_SERVER_TIMEOUT_ID: lwm2m_data_encode_int(targetP->disableTimeout, dataP); return COAP_205_CONTENT; case LWM2M_SERVER_STORING_ID: lwm2m_data_encode_bool(targetP->storing, dataP); return COAP_205_CONTENT; case LWM2M_SERVER_BINDING_ID: lwm2m_data_encode_string(targetP->binding, dataP); return COAP_205_CONTENT; case LWM2M_SERVER_UPDATE_ID: return COAP_405_METHOD_NOT_ALLOWED; default: return COAP_404_NOT_FOUND; } } static uint8_t prv_server_read(uint16_t instanceId, int *numDataP, lwm2m_data_t **dataArrayP, lwm2m_data_cfg_t *dataCfg, lwm2m_object_t *objectP) { server_instance_t *targetP; uint8_t result; int i; targetP = (server_instance_t *)lwm2m_list_find(objectP->instanceList, instanceId); if (NULL == targetP) return COAP_404_NOT_FOUND; // is the server asking for the full instance ? if (*numDataP == 0) { uint16_t resList[] = { LWM2M_SERVER_SHORT_ID_ID, LWM2M_SERVER_LIFETIME_ID, LWM2M_SERVER_MIN_PERIOD_ID, LWM2M_SERVER_MAX_PERIOD_ID, LWM2M_SERVER_TIMEOUT_ID, LWM2M_SERVER_STORING_ID, LWM2M_SERVER_BINDING_ID }; int nbRes = sizeof(resList) / sizeof(uint16_t); *dataArrayP = lwm2m_data_new(nbRes); if (*dataArrayP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; *numDataP = nbRes; for (i = 0 ; i < nbRes ; i++) { (*dataArrayP)[i].id = resList[i]; } } i = 0; do { result = prv_get_value((*dataArrayP) + i, targetP); i++; } while (i < *numDataP && result == COAP_205_CONTENT); return result; } static uint8_t prv_server_discover(uint16_t instanceId, int *numDataP, lwm2m_data_t **dataArrayP, lwm2m_object_t *objectP) { uint8_t result; int i; result = COAP_205_CONTENT; // is the server asking for the full object ? if (*numDataP == 0) { uint16_t resList[] = { LWM2M_SERVER_SHORT_ID_ID, LWM2M_SERVER_LIFETIME_ID, LWM2M_SERVER_MIN_PERIOD_ID, LWM2M_SERVER_MAX_PERIOD_ID, LWM2M_SERVER_DISABLE_ID, LWM2M_SERVER_TIMEOUT_ID, LWM2M_SERVER_STORING_ID, LWM2M_SERVER_BINDING_ID, LWM2M_SERVER_UPDATE_ID }; int nbRes = sizeof(resList) / sizeof(uint16_t); *dataArrayP = lwm2m_data_new(nbRes); if (*dataArrayP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; *numDataP = nbRes; for (i = 0; i < nbRes; i++) { (*dataArrayP)[i].id = resList[i]; } } else { for (i = 0; i < *numDataP && result == COAP_205_CONTENT; i++) { switch ((*dataArrayP)[i].id) { case LWM2M_SERVER_SHORT_ID_ID: case LWM2M_SERVER_LIFETIME_ID: case LWM2M_SERVER_MIN_PERIOD_ID: case LWM2M_SERVER_MAX_PERIOD_ID: case LWM2M_SERVER_DISABLE_ID: case LWM2M_SERVER_TIMEOUT_ID: case LWM2M_SERVER_STORING_ID: case LWM2M_SERVER_BINDING_ID: case LWM2M_SERVER_UPDATE_ID: break; default: result = COAP_404_NOT_FOUND; } } } return result; } static uint8_t prv_set_int_value(lwm2m_data_t *dataArray, uint32_t *data) { uint8_t result; int64_t value; if (1 == lwm2m_data_decode_int(dataArray, &value)) { if (value >= 0 && value <= 0xFFFFFFFF) { *data = value; result = COAP_204_CHANGED; } else { result = COAP_406_NOT_ACCEPTABLE; } } else { result = COAP_400_BAD_REQUEST; } return result; } bool prv_server_check_binding_valid(const char *binding, size_t size) { if (binding != NULL && (strncmp(binding, "U", size) == 0 || strncmp(binding, "UQ", size) == 0 || strncmp(binding, "S", size) == 0 || strncmp(binding, "SQ", size) == 0 || strncmp(binding, "US", size) == 0 || strncmp(binding, "UQS", size) == 0)) { return true; } else { return false; } } static uint8_t prv_server_write(uint16_t instanceId, int numData, lwm2m_data_t *dataArray, lwm2m_object_t *objectP) { server_instance_t *targetP; int i; uint8_t result; targetP = (server_instance_t *)lwm2m_list_find(objectP->instanceList, instanceId); if (NULL == targetP) { return COAP_404_NOT_FOUND; } i = 0; do { switch (dataArray[i].id) { case LWM2M_SERVER_SHORT_ID_ID: { uint32_t value = targetP->shortServerId; result = prv_set_int_value(dataArray + i, &value); if (COAP_204_CHANGED == result) { if (0 < value && 0xFFFF >= value) { targetP->shortServerId = value; } else { result = COAP_406_NOT_ACCEPTABLE; } } } break; case LWM2M_SERVER_LIFETIME_ID: result = prv_set_int_value(dataArray + i, (uint32_t *) & (targetP->lifetime)); break; case LWM2M_SERVER_MIN_PERIOD_ID: result = prv_set_int_value(dataArray + i, &(targetP->defaultMinPeriod)); break; case LWM2M_SERVER_MAX_PERIOD_ID: result = prv_set_int_value(dataArray + i, &(targetP->defaultMaxPeriod)); break; case LWM2M_SERVER_DISABLE_ID: result = COAP_405_METHOD_NOT_ALLOWED; break; case LWM2M_SERVER_TIMEOUT_ID: result = prv_set_int_value(dataArray + i, &(targetP->disableTimeout)); break; case LWM2M_SERVER_STORING_ID: { bool value; if (1 == lwm2m_data_decode_bool(dataArray + i, &value)) { targetP->storing = value; if(!value) { set_binary_app_data_object_rpt_max_cnt(value); } result = COAP_204_CHANGED; } else { result = COAP_400_BAD_REQUEST; } } break; case LWM2M_SERVER_BINDING_ID: if ((dataArray[i].type == LWM2M_TYPE_STRING || dataArray[i].type == LWM2M_TYPE_OPAQUE) && dataArray[i].value.asBuffer.length > 0 && dataArray[i].value.asBuffer.length <= 3 && prv_server_check_binding_valid((char *)dataArray[i].value.asBuffer.buffer, dataArray[i].value.asBuffer.length)) { memset(targetP->binding, 0, sizeof(targetP->binding)); strncpy(targetP->binding, (char *)dataArray[i].value.asBuffer.buffer, dataArray[i].value.asBuffer.length); result = COAP_204_CHANGED; } else { result = COAP_400_BAD_REQUEST; } break; case LWM2M_SERVER_UPDATE_ID: result = COAP_405_METHOD_NOT_ALLOWED; break; default: return COAP_404_NOT_FOUND; } i++; } while (i < numData && result == COAP_204_CHANGED); return result; } static uint8_t prv_server_execute(uint16_t instanceId, uint16_t resourceId, uint8_t *buffer, int length, lwm2m_object_t *objectP) { server_instance_t *targetP; targetP = (server_instance_t *)lwm2m_list_find(objectP->instanceList, instanceId); if (NULL == targetP) return COAP_404_NOT_FOUND; switch (resourceId) { case LWM2M_SERVER_DISABLE_ID: // executed in core, if COAP_204_CHANGED is returned if (0 < targetP->disableTimeout) return COAP_204_CHANGED; else return COAP_405_METHOD_NOT_ALLOWED; case LWM2M_SERVER_UPDATE_ID: // executed in core, if COAP_204_CHANGED is returned return COAP_204_CHANGED; default: return COAP_405_METHOD_NOT_ALLOWED; } } static uint8_t prv_server_delete(uint16_t id, lwm2m_object_t *objectP) { server_instance_t *serverInstance; objectP->instanceList = lwm2m_list_remove(objectP->instanceList, id, (lwm2m_list_t **)&serverInstance); if (NULL == serverInstance) return COAP_404_NOT_FOUND; lwm2m_free(serverInstance); return COAP_202_DELETED; } static uint8_t prv_server_create(uint16_t instanceId, int numData, lwm2m_data_t *dataArray, lwm2m_object_t *objectP) { server_instance_t *serverInstance; uint8_t result; serverInstance = (server_instance_t *)lwm2m_malloc(sizeof(server_instance_t)); if (NULL == serverInstance) return COAP_500_INTERNAL_SERVER_ERROR; memset(serverInstance, 0, sizeof(server_instance_t)); serverInstance->instanceId = instanceId; objectP->instanceList = LWM2M_LIST_ADD(objectP->instanceList, serverInstance); result = prv_server_write(instanceId, numData, dataArray, objectP); if (result != COAP_204_CHANGED) { (void)prv_server_delete(instanceId, objectP); } else { result = COAP_201_CREATED; } return result; } void copy_server_object(lwm2m_object_t *objectDest, lwm2m_object_t *objectSrc) { server_instance_t *instanceSrc = NULL; server_instance_t *previousInstanceDest = NULL; memcpy(objectDest, objectSrc, sizeof(lwm2m_object_t)); objectDest->instanceList = NULL; objectDest->userData = NULL; instanceSrc = (server_instance_t *)objectSrc->instanceList; while (instanceSrc != NULL) { server_instance_t *instanceDest = (server_instance_t *)lwm2m_malloc(sizeof(server_instance_t)); if (NULL == instanceDest) { return; } memcpy(instanceDest, instanceSrc, sizeof(server_instance_t)); // not sure it's necessary: strncpy(instanceDest->binding, instanceSrc->binding, 4); instanceSrc = (server_instance_t *)instanceSrc->next; if (previousInstanceDest == NULL) { objectDest->instanceList = (lwm2m_list_t *)instanceDest; } else { previousInstanceDest->next = instanceDest; } previousInstanceDest = instanceDest; } } void display_server_object(lwm2m_object_t *object) { #ifdef WITH_LOGS fprintf(stdout, " /%u: Server object, instances:\r\n", object->objID); server_instance_t *serverInstance = (server_instance_t *)object->instanceList; while (serverInstance != NULL) { fprintf(stdout, " /%u/%u: instanceId: %u, shortServerId: %u, lifetime: %u, storing: %s, binding: %s\r\n", object->objID, serverInstance->instanceId, serverInstance->instanceId, serverInstance->shortServerId, serverInstance->lifetime, serverInstance->storing ? "true" : "false", serverInstance->binding); serverInstance = (server_instance_t *)serverInstance->next; } #endif } //objArray[1] = get_server_object(serverId, "U", lifetime, false); lwm2m_object_t *get_server_object(int serverId, const char *binding, int lifetime, bool storing) { lwm2m_object_t *serverObj; serverObj = (lwm2m_object_t *)lwm2m_malloc(sizeof(lwm2m_object_t)); if (NULL != serverObj) { server_instance_t *serverInstance; memset(serverObj, 0, sizeof(lwm2m_object_t)); serverObj->objID = LWM2M_SERVER_OBJECT_ID; // Manually create an hardcoded server serverInstance = (server_instance_t *)lwm2m_malloc(sizeof(server_instance_t)); if (NULL == serverInstance) { lwm2m_free(serverObj); return NULL; } memset(serverInstance, 0, sizeof(server_instance_t)); serverInstance->instanceId = 0; serverInstance->shortServerId = serverId; if (lifetime <= 0) { serverInstance->lifetime = LWM2M_DEFAULT_LIFETIME; } else { serverInstance->lifetime = lifetime; } serverInstance->storing = storing; if(prv_server_check_binding_valid(binding, strlen(binding))) { memcpy(serverInstance->binding, binding, strlen(binding) + 1); } else { lwm2m_free(serverObj); lwm2m_free(serverInstance); return NULL; } serverObj->instanceList = LWM2M_LIST_ADD(serverObj->instanceList, serverInstance); serverObj->readFunc = prv_server_read; serverObj->discoverFunc = prv_server_discover; serverObj->writeFunc = prv_server_write; serverObj->createFunc = prv_server_create; serverObj->deleteFunc = prv_server_delete; serverObj->executeFunc = prv_server_execute; } return serverObj; } void clean_server_object(lwm2m_object_t *object) { if(NULL == object) { return; } while (object->instanceList != NULL) { server_instance_t *serverInstance = (server_instance_t *)object->instanceList; object->instanceList = object->instanceList->next; lwm2m_free(serverInstance); } lwm2m_free(object); } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/platform_adapter.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014, 2015 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation *******************************************************************************/ #include #include "internals.h" #include "osdepends/atiny_osdep.h" #ifndef LWM2M_MEMORY_TRACE void *lwm2m_malloc(size_t s) { void *mem = NULL; mem = atiny_malloc(s); return mem; } void lwm2m_free(void *p) { if(NULL != p) atiny_free(p); } char *lwm2m_strdup(const char *str) { int len = strlen(str) + 1; void *new = lwm2m_malloc(len); if (new == NULL) return NULL; return (char *)memcpy(new, str, len); } #endif int lwm2m_strncmp(const char *s1, const char *s2, size_t n) { return strncmp(s1, s2, n); } time_t lwm2m_gettime(void) { return (uint32_t)(atiny_gettime_ms() / 1000); } int lwm2m_rand(void *output, size_t len) { return atiny_random(output, len); } void lwm2m_delay(uint32_t second) { atiny_delay(second); } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/util_timer.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifdef LWM2M_BOOTSTRAP #ifdef LWM2M_CLIENT_MODE #include "util_timer.h" #include "liblwm2m.h" void timer_init(util_timer_t *timer, time_t interval, void(*callback)(void *param), void *param) { timer->expireTime = lwm2m_gettime() + interval; timer->interval = interval; timer->startFlag = false; timer->callback = callback; timer->param = param; } void timer_start(util_timer_t *timer) { timer->startFlag = true; } void timer_stop(util_timer_t *timer) { timer->startFlag = false; } void timer_step(util_timer_t *timer) { time_t current; if (!timer->startFlag) { return; } current = lwm2m_gettime(); if (current < timer->expireTime) { return; } if (timer->callback) { timer->callback(timer->param); } timer->expireTime = current + timer->interval; } #endif // LWM2M_CLIENT_MODE #endif // LWM2M_BOOTSTRAP ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_lwm2m/util_timer.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**@defgroup agent AgentTiny * @defgroup agenttiny Agenttiny Definition * @ingroup agent */ #ifndef _UTIL_TIMER_H_ #define _UTIL_TIMER_H_ #include #include #include #include #ifdef __cplusplus extern "C" { #endif #ifdef LWM2M_BOOTSTRAP #ifdef LWM2M_CLIENT_MODE // time uint is second, and max value 0xffffffff is hundreds of years.so ignore the turn to 0 problem typedef struct { time_t expireTime; time_t interval; void(*callback)(void *param); void *param; bool startFlag; }util_timer_t; void timer_init(util_timer_t *timer, time_t interval, void(*callback)(void *param), void *param); void timer_start(util_timer_t *timer); void timer_stop(util_timer_t *timer); void timer_step(util_timer_t *timer); #endif // LWM2M_CLIENT_MODE #endif // LWM2M_BOOTSTRAP #ifdef __cplusplus } #endif #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_mqtt/flash_manager.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "flash_manager.h" #include "log/atiny_log.h" #define FLASH_MAGIC_NUM 0x57381232 #define MAGIC_NUM_POS 0 #define TOTAL_LEN_POS 4 #define DATA_POS 8 #define MAX_FLASH_INFO ((STRING_MAX_LEN + 1) * (MAX_DATA_ITEM) + DATA_POS) static int (*g_cmd_ioctl)(mqtt_cmd_e cmd, void *arg, int32_t len); static int flash_manager_parse(const char *buf, uint32_t len, flash_info_s *flash_info) { uint32_t i; uint32_t tmp_len; int ret; for (i = 0; i < MAX_DATA_ITEM; i++) { tmp_len = strnlen(buf, len); if ((tmp_len >= len) || (tmp_len > STRING_MAX_LEN)) { ATINY_LOG(LOG_FATAL, "string len err tmp_len %ld,len %ld", tmp_len, len); break; } flash_info->items[i] = atiny_strdup(buf); if (flash_info->items[i] == NULL) { ATINY_LOG(LOG_FATAL, "atiny_strdup fail"); ret = ATINY_MALLOC_FAILED; goto EXIT_ERR; } buf += (tmp_len + 1); len -= (tmp_len + 1); } if ((i != MAX_DATA_ITEM) || (len != 0)) { ATINY_LOG(LOG_FATAL, "data info err item num %ld,left len %ld", i, len); ret = ATINY_ERR; goto EXIT_ERR; } ATINY_LOG(LOG_INFO, "deviceid and password exist"); return ATINY_OK; EXIT_ERR: flash_manager_destroy_flash_info(flash_info); return ret; } static int flash_manager_get_need_len(const flash_info_s *flash_info, uint32_t *len) { uint32_t i; *len = DATA_POS; for (i = 0; i < MAX_DATA_ITEM; i++) { uint32_t tmp_len = strnlen(flash_info->items[i], MAX_FLASH_INFO); *len += (tmp_len + 1); if (*len > MAX_FLASH_INFO) { ATINY_LOG(LOG_ERR, "write info exceed max"); return ATINY_ERR; } } return ATINY_OK; } static void flash_manager_write_buffer(const flash_info_s *flash_info, char *buf, uint32_t len) { uint32_t i; *((uint32_t *)buf) = FLASH_MAGIC_NUM; *((uint32_t *)&buf[TOTAL_LEN_POS]) = len; buf += DATA_POS; len -= DATA_POS; for (i = 0; i < MAX_DATA_ITEM; i++) { int32_t tmp_len; tmp_len = snprintf(buf, len, "%s", flash_info->items[i]); if ((tmp_len >= len) || (tmp_len < 0)) { ATINY_LOG(LOG_FATAL, "snprintf err,tmp_len %ld, len %d", tmp_len, len); return; } buf += (tmp_len + 1); len -= (tmp_len + 1); } } void flash_manager_init(int (*cmd_ioctl)(mqtt_cmd_e cmd, void *arg, int32_t len)) { g_cmd_ioctl = cmd_ioctl; } int flash_manager_read(flash_info_s *flash_info) { int ret; uint32_t len; uint32_t magic_num; uint8_t *buf; memset(flash_info, 0, sizeof(*flash_info)); buf = atiny_malloc(MAX_FLASH_INFO); if (buf == NULL) { ATINY_LOG(LOG_ERR, "atiny_malloc fail len %d", MAX_FLASH_INFO); return ATINY_MALLOC_FAILED; } ret = g_cmd_ioctl(MQTT_READ_SECRET_INFO, buf, MAX_FLASH_INFO); if (ret != ATINY_OK) { ATINY_LOG(LOG_FATAL, "g_cmd_ioctl MQTT_READ_SECRET_INFO fail ret %ld", ret); goto EXIT; } magic_num = *((uint32_t*)buf); if (magic_num != FLASH_MAGIC_NUM) { ATINY_LOG(LOG_INFO, "mqtt flash info not valid"); goto EXIT; } len = *((uint32_t*)&buf[TOTAL_LEN_POS]); if ((len > MAX_FLASH_INFO) || (len <= DATA_POS)) { ATINY_LOG(LOG_ERR, "mqtt flash info len %d invalid", len); goto EXIT; } ret = flash_manager_parse((char *)(buf + DATA_POS), len - DATA_POS, flash_info); EXIT: atiny_free(buf); return ret; } int flash_manager_write(const flash_info_s *flash_info) { uint32_t len; int ret; uint8_t *buf; ret = flash_manager_get_need_len(flash_info, &len); if (ret != ATINY_OK) { return ret; } buf = atiny_malloc(MAX_FLASH_INFO); if (buf == NULL) { ATINY_LOG(LOG_ERR, "atiny_malloc fail len %d", len); return ATINY_MALLOC_FAILED; } flash_manager_write_buffer(flash_info, (char *)buf, len); ret = g_cmd_ioctl(MQTT_SAVE_SECRET_INFO, buf, MAX_FLASH_INFO); atiny_free(buf); if (ret != ATINY_OK) { ATINY_LOG(LOG_FATAL, "g_cmd_ioctl MQTT_SAVE_SECRET_INFO fail ret %d, len ld", ret, len); } return ret; } void flash_manager_destroy_flash_info(flash_info_s *flash_info) { uint32_t i; for (i = 0; i < MAX_DATA_ITEM; i++) { TRY_FREE_MEM(flash_info->items[i]); } } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_mqtt/flash_manager.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef FLASH_MANAGER_H #define FLASH_MANAGER_H #include "atiny_mqtt/mqtt_client.h" #ifdef __cplusplus extern "C" { #endif #define STRING_MAX_LEN 256 #ifndef array_size #define array_size(a) (sizeof(a)/sizeof(*(a))) #endif #define TRY_FREE_MEM(mem) \ do\ {\ if(NULL != (mem))\ {\ atiny_free(mem);\ (mem) = NULL;\ }\ }while(0) enum { PRODUCT_IDX, NODEID_IDX, DEVICEID_IDX, PASSWORD_IDX, MAX_DATA_ITEM }; typedef struct { char *items[MAX_DATA_ITEM]; }flash_info_s; /*flash_info info is malloc, should destroy if not used*/ void flash_manager_init(int (*cmd_ioctl)(mqtt_cmd_e cmd, void *arg, int32_t len)); int flash_manager_read(flash_info_s *flash_info); int flash_manager_write(const flash_info_s *flash_info); void flash_manager_destroy_flash_info(flash_info_s *flash_info); #ifdef __cplusplus } #endif #endif /* FLASH_MANAGER_H */ ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_mqtt/hmac.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "hmac.h" #include "mbedtls/ssl.h" #include "mbedtls/entropy.h" #include "mbedtls/ctr_drbg.h" #include "mbedtls/platform.h" #include "mbedtls/md_internal.h" #include "osdepends/atiny_osdep.h" #include "dtls_interface.h" int mbedtls_hmac_calc(mbedtls_hmac_t *hmac_info) { int ret; mbedtls_md_context_t mbedtls_md_ctx; const mbedtls_md_info_t *md_info; if (hmac_info == NULL || hmac_info->secret == NULL || hmac_info->input == NULL || hmac_info->secret_len <= 0 || hmac_info->input_len <= 0 || hmac_info->digest_len <= 0) { return MBEDTLS_ERR_MD_BAD_INPUT_DATA; } md_info = mbedtls_md_info_from_type(hmac_info->hmac_type); if (md_info == NULL || md_info->size > hmac_info->digest_len) { return MBEDTLS_ERR_MD_BAD_INPUT_DATA; } mbedtls_md_init(&mbedtls_md_ctx); memset(hmac_info->digest, 0x00, hmac_info->digest_len); ret = mbedtls_md_setup(&mbedtls_md_ctx, md_info, 1); if (ret != 0) { printf("mbedtls_md_setup() returned -0x%04x\n", -ret); goto exit; } (void)mbedtls_md_hmac_starts(&mbedtls_md_ctx, hmac_info->secret, hmac_info->secret_len); (void)mbedtls_md_hmac_update(&mbedtls_md_ctx, hmac_info->input, hmac_info->input_len); (void)mbedtls_md_hmac_finish(&mbedtls_md_ctx, hmac_info->digest); exit: mbedtls_md_free(&mbedtls_md_ctx); return ret; } ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_mqtt/hmac.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef _HMAC_H_ #define _HMAC_H_ #include "mbedtls/md.h" #ifdef __cplusplus #if __cplusplus extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ typedef struct _mbedtls_hmac_t { const unsigned char *secret; const unsigned char *input; unsigned char *digest; size_t secret_len; size_t input_len; size_t digest_len; mbedtls_md_type_t hmac_type; }mbedtls_hmac_t; int mbedtls_hmac_calc(mbedtls_hmac_t *hmac_info); #ifdef __cplusplus #if __cplusplus } #endif /* __cplusplus */ #endif /* __cplusplus */ #endif /* _HMAC_H_ */ ================================================ FILE: Huawei_LiteOS/components/connectivity/agent_tiny/atiny_mqtt/mqtt_client.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "atiny_mqtt/mqtt_client.h" #include "los_base.h" #include "los_task.ph" #include "los_typedef.h" #include "los_sys.h" #include "log/atiny_log.h" #include "MQTTClient.h" #include "flash_manager.h" #include "dtls_interface.h" #include "cJSON.h" #include "hmac.h" #define MQTT_VERSION_3_1 (3) #define MQTT_VERSION_3_1_1 (4) #define VARIABLE_SIZE (4 + 1) #define CMD_TOPIC_FMT "/huawei/v1/devices/%s/command/%s" #define DATA_TOPIC_FMT "/huawei/v1/devices/%s/data/%s" #define SECRET_NOTIFY_TOPIC_FMT "/huawei/v1/products/%s/sn/%s/secretNotify" #define SECRET_ACK_TOPIC_FMT "/huawei/v1/products/%s/sn/%s/secretACK" #define MQTT_TIME_BUF_LEN 11 #define IS_VALID_NAME_LEN(name) (strnlen((name), STRING_MAX_LEN + 1) <= STRING_MAX_LEN) typedef enum { MQTT_CONNECT_WITH_PRODUCT_ID, MQTT_CONNECT_WITH_DEVICE_ID }mqtt_dynamic_connect_state_e; typedef struct { mqtt_static_connection_info_s save_info; char * got_password; mqtt_dynamic_connect_state_e state; uint8_t connection_update_flag; uint8_t has_device_id; // uint8_t reserve[2]; }mqtt_dynamic_info_s; struct mqtt_client_tag_s { mqtt_device_info_s device_info; MQTTClient client; mqtt_param_s params; mqtt_dynamic_info_s dynamic_info; char *sub_topic; uint8_t init_flag; uint8_t reserve[3]; }; static uint8_t g_mqtt_sendbuf[MQTT_SENDBUF_SIZE]; /* reserve 1 byte for string end 0 for jason */ static uint8_t g_mqtt_readbuf[MQTT_READBUF_SIZE + 1]; static mqtt_client_s g_mqtt_client; static int mqtt_cmd_ioctl(mqtt_cmd_e cmd, void *arg, int32_t len) { mqtt_client_s* handle = &g_mqtt_client; if (handle->params.cmd_ioctl != NULL) { return handle->params.cmd_ioctl(cmd, arg, len); } ATINY_LOG(LOG_FATAL, "cmd_ioctl null"); return ATINY_ERR; } static void mqtt_free_params(mqtt_param_s *param) { TRY_FREE_MEM(param->server_ip); TRY_FREE_MEM(param->server_port); switch(param->info.security_type) { case MQTT_SECURITY_TYPE_PSK: TRY_FREE_MEM(param->info.u.psk.psk_id); TRY_FREE_MEM(param->info.u.psk.psk); break; case MQTT_SECURITY_TYPE_CA: TRY_FREE_MEM(param->info.u.ca.ca_crt); break; default: break; } } static int mqtt_check_param(const mqtt_param_s *param) { if ((param->server_ip == NULL) || (param->server_port == NULL) || (param->info.security_type >= MQTT_SECURITY_TYPE_MAX) || (param->cmd_ioctl == NULL)) { ATINY_LOG(LOG_FATAL, "invalid param, sec type %d", param->info.security_type); return ATINY_ARG_INVALID; } if (param->info.security_type == MQTT_SECURITY_TYPE_PSK) { if ((param->info.u.psk.psk == NULL) || (param->info.u.psk.psk_len <= 0) || (param->info.u.psk.psk_id == NULL) || (param->info.u.psk.psk_id_len <= 0)) { ATINY_LOG(LOG_FATAL, "invalid psk"); return ATINY_ARG_INVALID; } } if (param->info.security_type == MQTT_SECURITY_TYPE_CA) { if (param->info.u.ca.ca_crt == NULL) { ATINY_LOG(LOG_FATAL, "invalid ca"); return ATINY_ARG_INVALID; } } return ATINY_OK; } static int mqtt_dup_param(mqtt_param_s *dest, const mqtt_param_s *src) { memset(dest, 0, sizeof(*dest)); dest->info.security_type = src->info.security_type; dest->cmd_ioctl = src->cmd_ioctl; dest->server_ip = atiny_strdup(src->server_ip); if(NULL == dest->server_ip) { ATINY_LOG(LOG_FATAL, "atiny_strdup NULL"); return ATINY_MALLOC_FAILED; } dest->server_port = atiny_strdup(src->server_port); if(NULL == dest->server_port) { ATINY_LOG(LOG_FATAL, "atiny_strdup NULL"); goto mqtt_param_dup_failed; } switch(src->info.security_type) { case MQTT_SECURITY_TYPE_PSK: dest->info.u.psk.psk_id = (uint8_t *)atiny_malloc(src->info.u.psk.psk_id_len); if(NULL == dest->info.u.psk.psk_id) { ATINY_LOG(LOG_FATAL, "atiny_strdup NULL"); goto mqtt_param_dup_failed; } memcpy(dest->info.u.psk.psk_id, src->info.u.psk.psk_id, src->info.u.psk.psk_id_len); dest->info.u.psk.psk_id_len = src->info.u.psk.psk_id_len; dest->info.u.psk.psk = (unsigned char *)atiny_malloc(src->info.u.psk.psk_len); if(NULL == dest->info.u.psk.psk) { ATINY_LOG(LOG_FATAL, "atiny_strdup NULL"); goto mqtt_param_dup_failed; } memcpy(dest->info.u.psk.psk, src->info.u.psk.psk, src->info.u.psk.psk_len); dest->info.u.psk.psk_len = src->info.u.psk.psk_len; break; case MQTT_SECURITY_TYPE_CA: dest->info.u.ca.ca_crt = (char *)atiny_malloc(src->info.u.ca.ca_len); if(NULL == dest->info.u.ca.ca_crt) { ATINY_LOG(LOG_FATAL, "atiny_strdup NULL"); goto mqtt_param_dup_failed; } memcpy(dest->info.u.ca.ca_crt, src->info.u.ca.ca_crt, src->info.u.ca.ca_len); dest->info.u.ca.ca_len = src->info.u.ca.ca_len; break; default: break; } return ATINY_OK; mqtt_param_dup_failed: mqtt_free_params(dest); return ATINY_MALLOC_FAILED; } static void mqtt_free_device_info(mqtt_device_info_s *info) { TRY_FREE_MEM(info->password); if(MQTT_STATIC_CONNECT == info->connection_type) { TRY_FREE_MEM(info->u.s_info.deviceid); } else { TRY_FREE_MEM(info->u.d_info.productid); TRY_FREE_MEM(info->u.d_info.nodeid); } } static void mqtt_free_dynamic_info(mqtt_client_s* handle) { if (handle->sub_topic) { (void)MQTTSetMessageHandler(&handle->client, handle->sub_topic, NULL); atiny_free(handle->sub_topic); handle->sub_topic = NULL; } TRY_FREE_MEM(handle->dynamic_info.save_info.deviceid); TRY_FREE_MEM(handle->dynamic_info.got_password); } static int mqtt_check_device_info(const mqtt_device_info_s *info) { if((info->connection_type >= MQTT_MAX_CONNECTION_TYPE) || (info->codec_mode >= MQTT_MAX_CODEC_MODE) || (info->sign_type >= MQTT_MAX_SIGN_TYPE) || (NULL == info->password) || (!IS_VALID_NAME_LEN(info->password))) { ATINY_LOG(LOG_FATAL, "invalid device info con_type %d codec_mode %d signe type %d", info->connection_type, info->codec_mode, info->sign_type); return ATINY_ARG_INVALID; } if ((info->connection_type == MQTT_STATIC_CONNECT) && ((NULL == info->u.s_info.deviceid) || (!IS_VALID_NAME_LEN(info->u.s_info.deviceid)))) { ATINY_LOG(LOG_FATAL, "invalid static device info con_type %d codec_mode %d signe type %d", info->connection_type, info->codec_mode, info->sign_type); return ATINY_ARG_INVALID; } if ((info->connection_type == MQTT_DYNAMIC_CONNECT) &&((NULL == info->u.d_info.productid) || (!IS_VALID_NAME_LEN(info->u.d_info.productid)) || (NULL == info->u.d_info.nodeid) || !(IS_VALID_NAME_LEN(info->u.d_info.nodeid)))) { ATINY_LOG(LOG_FATAL, "invalid dynamic device info con_type %d codec_mode %d signe type %d", info->connection_type, info->codec_mode, info->sign_type); return ATINY_ARG_INVALID; } return ATINY_OK; } static int mqtt_dup_device_info(mqtt_device_info_s *dest, const mqtt_device_info_s *src) { memset(dest, 0, sizeof(*dest)); dest->connection_type = src->connection_type; dest->sign_type = src->sign_type; dest->codec_mode = src->codec_mode; dest->password = atiny_strdup(src->password); if (NULL == dest->password) { ATINY_LOG(LOG_FATAL, "atiny_strdup fail"); return ATINY_MALLOC_FAILED; } if(MQTT_STATIC_CONNECT == src->connection_type) { dest->u.s_info.deviceid = atiny_strdup(src->u.s_info.deviceid); if (NULL == dest->u.s_info.deviceid) { ATINY_LOG(LOG_FATAL, "atiny_strdup fail"); goto MALLOC_FAIL; } } else { dest->u.d_info.productid = atiny_strdup(src->u.d_info.productid); if (NULL == dest->u.d_info.productid) { ATINY_LOG(LOG_FATAL, "atiny_strdup fail"); goto MALLOC_FAIL; } dest->u.d_info.nodeid = atiny_strdup(src->u.d_info.nodeid); if (NULL == dest->u.d_info.nodeid) { ATINY_LOG(LOG_FATAL, "atiny_strdup fail"); goto MALLOC_FAIL; } } return ATINY_OK; MALLOC_FAIL: mqtt_free_device_info(dest); return ATINY_MALLOC_FAILED; } static bool mqtt_is_connectting_with_deviceid(const mqtt_client_s* handle) { return (MQTT_STATIC_CONNECT == handle->device_info.connection_type) || (handle->dynamic_info.state == MQTT_CONNECT_WITH_DEVICE_ID); } static char *mqtt_add_strings(const char* strs[], uint32_t tmp_len[], uint32_t str_num) { uint32_t i; const char hyphen = '_'; uint32_t len = 0; char *result; char *cur; for (i = 0; i < str_num; i++) { tmp_len[i] = strnlen(strs[i], STRING_MAX_LEN); len += (tmp_len[i] + 1); } result = atiny_malloc(len); if (result == NULL) { ATINY_LOG(LOG_FATAL, "mqtt_cmd_ioctl fail"); return NULL; } cur = result; for (i = 0; i < str_num; i++) { memcpy(cur, strs[i], tmp_len[i]); cur += tmp_len[i]; if (i != str_num - 1) { *cur = hyphen; cur++; } } *cur = '\0'; return result; } static const char *mqtt_connection_type_to_str(mqtt_connection_type_e type) { return MQTT_STATIC_CONNECT == type ? "0" : "1"; } static const char *mqtt_sign_type_to_str(mqtt_password_sign_type_e type) { return MQTT_SIGN_TYPE_HMACSHA256_NO_CHECK_TIME == type ? "0" : "1"; } static void mqtt_bin_to_str(const uint8_t *bin_buf, char *str_buf, uint32_t bin_len) { uint32_t i; for(i = 0; i < bin_len; i++) { (void)snprintf(str_buf + i * 2, 3, "%02x", bin_buf[i]); } } static char *mqtt_get_send_password(char *password, char *time) { uint8_t hmac[32]; const uint32_t len = sizeof(hmac) * 2 + 1; char *result; int ret; mbedtls_hmac_t hmac_info; hmac_info.secret = (uint8_t *)time; hmac_info.secret_len = strnlen(time, MQTT_TIME_BUF_LEN); hmac_info.input = (uint8_t *)password; hmac_info.input_len = strnlen(password, STRING_MAX_LEN); hmac_info.digest = hmac; hmac_info.digest_len = sizeof(hmac); hmac_info.hmac_type = MBEDTLS_MD_SHA256; ret = mbedtls_hmac_calc(&hmac_info); if (ret != ATINY_OK) { ATINY_LOG(LOG_FATAL, "mbedtls_hmac_calc fail,ret %d", ret); return NULL; } result = atiny_malloc(len); if (result == NULL) { ATINY_LOG(LOG_FATAL, "atiny_malloc fail"); return NULL; } mqtt_bin_to_str(hmac, result, sizeof(hmac)); return result; } static void mqtt_destroy_data_connection_info(MQTTPacket_connectData *data) { TRY_FREE_MEM(data->clientID.cstring); TRY_FREE_MEM(data->password.cstring); } static int mqtt_get_connection_info(mqtt_client_s* handle, MQTTPacket_connectData *data) { char *strs[5]; uint32_t tmp[array_size(strs)]; uint32_t str_num = 0; char time[MQTT_TIME_BUF_LEN]; char *password; if (mqtt_is_connectting_with_deviceid(handle)) { if (handle->device_info.connection_type == MQTT_STATIC_CONNECT) { strs[0] = handle->device_info.u.s_info.deviceid; password = handle->device_info.password; } else { strs[0] = handle->dynamic_info.save_info.deviceid; password = handle->dynamic_info.got_password; } str_num = 1; ATINY_LOG(LOG_INFO, "try static connect"); } else { strs[0] = handle->device_info.u.d_info.productid; strs[1] = handle->device_info.u.d_info.nodeid; str_num = 2; password = handle->device_info.password; ATINY_LOG(LOG_INFO, "try dynamic connect"); } strs[str_num++] = (char *)mqtt_connection_type_to_str( mqtt_is_connectting_with_deviceid(handle) ? MQTT_STATIC_CONNECT : MQTT_DYNAMIC_CONNECT); strs[str_num++] = (char *)mqtt_sign_type_to_str(handle->device_info.sign_type); if (mqtt_cmd_ioctl(MQTT_GET_TIME, time, sizeof(time)) != ATINY_OK) { ATINY_LOG(LOG_FATAL, "mqtt_cmd_ioctl fail"); return ATINY_ERR; } time[sizeof(time) - 1] = '\0'; strs[str_num++] = time; data->clientID.cstring = mqtt_add_strings((const char **)strs, tmp, str_num); if (data->clientID.cstring == NULL) { return ATINY_MALLOC_FAILED; } data->username.cstring = strs[0]; //deviceid or pruoductid data->password.cstring = mqtt_get_send_password(password, time); if (data->password.cstring == NULL) { return ATINY_ERR; } ATINY_LOG(LOG_DEBUG, "send user %s client %s", data->username.cstring, data->clientID.cstring); return ATINY_OK; } static char *mqtt_get_topic(const mqtt_client_s* handle, const char *fmt, uint32_t fixed_size, const char *deviceid_or_productid, const char *sn_or_codec_mode) { uint32_t len; char *topic; len = fixed_size + strnlen(deviceid_or_productid, STRING_MAX_LEN) + strnlen(sn_or_codec_mode, STRING_MAX_LEN) + 1; topic = atiny_malloc(len); if (topic == NULL) { ATINY_LOG(LOG_FATAL, "atiny_malloc fail, len %d", len); return NULL; } (void)snprintf(topic, len, fmt, deviceid_or_productid, sn_or_codec_mode); return topic; } static char *mqtt_get_device_topic(const mqtt_client_s* handle, const char *fmt, uint32_t fixed_size) { char *deviceid; const char *codec_mode[MQTT_MAX_CODEC_MODE] = {"binary", "json"}; deviceid = ((handle->device_info.connection_type == MQTT_STATIC_CONNECT) ? handle->device_info.u.s_info.deviceid : handle->dynamic_info.save_info.deviceid); return mqtt_get_topic(handle, fmt, fixed_size, deviceid, codec_mode[handle->device_info.codec_mode]); } static char *mqtt_get_secret_topic(const mqtt_client_s* handle, const char *fmt, uint32_t fixed_size) { return mqtt_get_topic(handle, fmt, fixed_size, handle->device_info.u.d_info.productid, handle->device_info.u.d_info.nodeid); } static int mqtt_parse_secret_topic(mqtt_client_s* handle, const char *payload, uint32_t len) { //TODO:parse json, log cJSON *msg_type; cJSON *deviceid; cJSON *secret; cJSON * root = NULL; int ret = ATINY_ERR; root = cJSON_Parse(payload); if (root == NULL) { ATINY_LOG(LOG_ERR, "err secret notify, len %d, msg %s", len, payload); goto EXIT; } msg_type = cJSON_GetObjectItem(root, MQTT_MSG_TYPE); if ((msg_type == NULL) || (msg_type->valuestring == NULL) || (strncmp(msg_type->valuestring, "cloudSendSecret", STRING_MAX_LEN + 1) != 0)) { ATINY_LOG(LOG_ERR, "msg_type not right"); goto EXIT; } deviceid = cJSON_GetObjectItem(root, "deviceid"); if ((deviceid == NULL) || (deviceid->valuestring == NULL) || (!IS_VALID_NAME_LEN(deviceid->valuestring))) { ATINY_LOG(LOG_ERR, "deviceid not right"); goto EXIT; } secret = cJSON_GetObjectItem(root, "secret"); if ((secret == NULL) || (secret->valuestring == NULL) || (!IS_VALID_NAME_LEN(secret->valuestring))) { ATINY_LOG(LOG_ERR, "secret not right"); goto EXIT; } handle->dynamic_info.has_device_id = false; TRY_FREE_MEM(handle->dynamic_info.save_info.deviceid); handle->dynamic_info.save_info.deviceid = atiny_strdup(deviceid->valuestring); if (handle->dynamic_info.save_info.deviceid == NULL) { ATINY_LOG(LOG_INFO, "atiny_strdup null"); goto EXIT; } TRY_FREE_MEM(handle->dynamic_info.got_password); handle->dynamic_info.got_password = atiny_strdup(secret->valuestring); if (handle->dynamic_info.got_password == NULL) { ATINY_LOG(LOG_INFO, "atiny_strdup null"); goto EXIT; } handle->dynamic_info.has_device_id = true; handle->dynamic_info.connection_update_flag = true; ret = ATINY_OK; ATINY_LOG(LOG_INFO, "get secret info right"); EXIT: if (root) { cJSON_Delete(root); } return ret; } static void mqtt_send_secret_ack(mqtt_client_s* handle) { MQTTMessage message; int rc; char* topic = mqtt_get_secret_topic(handle, SECRET_ACK_TOPIC_FMT, sizeof(SECRET_ACK_TOPIC_FMT) - VARIABLE_SIZE); if (topic == NULL) { return; } memset(&message, 0, sizeof(message)); message.qos = QOS1; rc = MQTTPublish(&handle->client, topic, &message); atiny_free(topic); if (rc != MQTT_SUCCESS) { ATINY_LOG(LOG_FATAL, "MQTTPublish fail,rc %d", rc); } } /*lint -e529*/ static int mqtt_modify_payload(MessageData *md) { char *end = ((char *)md->message->payload) + md->message->payloadlen; static uint32_t callback_err; /* add for jason parse,then not need to copy in callback */ if ((end >= (char *)g_mqtt_readbuf) && (end < (char *)(g_mqtt_readbuf + sizeof(g_mqtt_readbuf)))) { *end = '\0'; return ATINY_OK; } /* should not happen */ ATINY_LOG(LOG_ERR, "not expect msg callback err, pl %p, len %ld, err num %ld", md->message->payload, md->message->payloadlen, ++callback_err); return ATINY_ERR; } /*lint +e529*/ static void mqtt_recv_secret_topic(MessageData *md) { mqtt_client_s* handle = &g_mqtt_client; if ((md == NULL) || (md->message == NULL) || (md->message->payload == NULL) || (md->message->payloadlen == 0) || (mqtt_modify_payload(md) != ATINY_OK)) { ATINY_LOG(LOG_FATAL, "null point or msg err, len %ld", md->message->payloadlen); return; } if (mqtt_parse_secret_topic(handle, md->message->payload, md->message->payloadlen) == ATINY_OK) { flash_info_s flash_info; flash_info.items[PRODUCT_IDX] = handle->device_info.u.d_info.productid; flash_info.items[NODEID_IDX] = handle->device_info.u.d_info.nodeid; flash_info.items[DEVICEID_IDX] = handle->dynamic_info.save_info.deviceid; flash_info.items[PASSWORD_IDX] = handle->dynamic_info.got_password; if (flash_manager_write(&flash_info) != ATINY_OK) { return; } mqtt_send_secret_ack(handle); } } static void mqtt_recv_cmd_topic(MessageData *md) { if ((md == NULL) || (md->message == NULL) || (mqtt_modify_payload(md) != ATINY_OK)) { ATINY_LOG(LOG_FATAL, "null point"); return; } (void)mqtt_cmd_ioctl(MQTT_RCV_MSG, md->message->payload, md->message->payloadlen); } static int mqtt_subscribe_topic(mqtt_client_s* handle) { char *topic; void (*topi_callback)(MessageData *md); int rc; if (handle->sub_topic) { (void)MQTTSetMessageHandler(&handle->client, handle->sub_topic, NULL); atiny_free(handle->sub_topic); handle->sub_topic = NULL; } if (mqtt_is_connectting_with_deviceid(handle)) { topic = mqtt_get_device_topic(handle, CMD_TOPIC_FMT, sizeof(CMD_TOPIC_FMT) - VARIABLE_SIZE); topi_callback = mqtt_recv_cmd_topic; ATINY_LOG(LOG_INFO, "try subcribe static topic"); } else { topic = mqtt_get_secret_topic(handle, SECRET_NOTIFY_TOPIC_FMT, sizeof(SECRET_NOTIFY_TOPIC_FMT) - VARIABLE_SIZE);; topi_callback = mqtt_recv_secret_topic; ATINY_LOG(LOG_INFO, "try subcribe dynamic topic"); } if (topic == NULL) { return ATINY_ERR; } rc = MQTTSubscribe(&handle->client, topic, QOS1, topi_callback); if (rc != MQTT_SUCCESS) { ATINY_LOG(LOG_FATAL, "MQTTSubscribe fail,rc=%d, topic=%s", rc, topic); atiny_free(topic); } else { handle->sub_topic = topic; } return rc; } static void mqtt_disconnect( MQTTClient *client, Network *n) { if (MQTTIsConnected(client)) { (void)MQTTDisconnect(client); } NetworkDisconnect(n); ATINY_LOG(LOG_ERR, "mqtt_disconnect"); } static inline void mqtt_inc_fail_cnt(int32_t *conn_failed_cnt) { if(*conn_failed_cnt < MQTT_CONN_FAILED_MAX_TIMES) { (*conn_failed_cnt)++; } } static void mqtt_proc_connect_err( MQTTClient *client, Network *n, int32_t *conn_failed_cnt) { mqtt_inc_fail_cnt(conn_failed_cnt); mqtt_disconnect(client, n); } static void mqtt_proc_connect_nack(mqtt_client_s* handle) { if (handle->device_info.connection_type == MQTT_DYNAMIC_CONNECT) { if (handle->dynamic_info.state == MQTT_CONNECT_WITH_DEVICE_ID) { handle->dynamic_info.state = MQTT_CONNECT_WITH_PRODUCT_ID; } else { if (handle->dynamic_info.has_device_id) { handle->dynamic_info.state = MQTT_CONNECT_WITH_DEVICE_ID; } } } } static mqtt_security_info_s *mqtt_get_security_info(void) { mqtt_client_s* handle = &g_mqtt_client; return &handle->params.info; } static void mqtt_read_flash_info(mqtt_client_s* handle) { flash_info_s flash_info; if (handle->device_info.connection_type == MQTT_STATIC_CONNECT) { return; } memset(&handle->dynamic_info, 0, sizeof(handle->dynamic_info)); memset(&flash_info, 0, sizeof(flash_info)); if (flash_manager_read(&flash_info) != ATINY_OK) { return; } if ((strcmp(flash_info.items[PRODUCT_IDX], handle->device_info.u.d_info.productid) != 0) || (strcmp(flash_info.items[NODEID_IDX], handle->device_info.u.d_info.nodeid) != 0)) { ATINY_LOG(LOG_INFO, "flash info for the nodeid and not use"); flash_manager_destroy_flash_info(&flash_info); return; } ATINY_LOG(LOG_DEBUG, "mqtt read info deviceid %s,procid %s,nodid %s", flash_info.items[DEVICEID_IDX], flash_info.items[PRODUCT_IDX], flash_info.items[NODEID_IDX]); handle->dynamic_info.save_info.deviceid = flash_info.items[DEVICEID_IDX]; flash_info.items[DEVICEID_IDX] = NULL; handle->dynamic_info.got_password = flash_info.items[PASSWORD_IDX]; flash_info.items[PASSWORD_IDX] = NULL; handle->dynamic_info.has_device_id = true; handle->dynamic_info.state = MQTT_CONNECT_WITH_DEVICE_ID; flash_manager_destroy_flash_info(&flash_info); } int atiny_mqtt_init(const mqtt_param_s *params, mqtt_client_s **phandle) { cJSON_InitHooks(NULL); if (params == NULL || phandle == NULL || params->info.security_type != MQTT_SECURITY_TYPE_CA || mqtt_check_param(params) != ATINY_OK) { ATINY_LOG(LOG_FATAL, "Invalid args"); return ATINY_ARG_INVALID; } if (g_mqtt_client.init_flag) { ATINY_LOG(LOG_FATAL, "mqtt reinit"); return ATINY_ERR; } memset(&g_mqtt_client, 0, sizeof(g_mqtt_client)); if (ATINY_OK != mqtt_dup_param(&(g_mqtt_client.params), params)) { return ATINY_MALLOC_FAILED; } flash_manager_init(mqtt_cmd_ioctl); *phandle = &g_mqtt_client; g_mqtt_client.init_flag = true; return ATINY_OK; } int atiny_mqtt_bind(const mqtt_device_info_s* device_info, mqtt_client_s* handle) { Network n; MQTTClient *client = NULL; mqtt_param_s *params; int rc; int32_t conn_failed_cnt = 0; MQTTPacket_connectData data = MQTTPacket_connectData_initializer; Timer timer; int result = ATINY_ERR; if (NULL == handle) { ATINY_LOG(LOG_FATAL, "handle null"); return ATINY_ARG_INVALID; } if((device_info == NULL) || (mqtt_check_device_info(device_info) != ATINY_OK)) { ATINY_LOG(LOG_FATAL, "parameter invalid"); result = ATINY_ARG_INVALID; goto atiny_bind_quit; } dtls_init(); client = &(handle->client); params = &(handle->params); rc = mqtt_dup_device_info(&(handle->device_info), device_info); if (rc != ATINY_OK) { goto atiny_bind_quit; } mqtt_read_flash_info(handle); NetworkInit(&n, mqtt_get_security_info); memset(client, 0x0, sizeof(MQTTClient)); rc = MQTTClientInit(client, &n, MQTT_COMMAND_TIMEOUT_MS, g_mqtt_sendbuf, MQTT_SENDBUF_SIZE, g_mqtt_readbuf, MQTT_READBUF_SIZE); if (rc != MQTT_SUCCESS) { ATINY_LOG(LOG_FATAL, "MQTTClientInit fail,rc %d", rc); goto atiny_bind_quit; } data.willFlag = 0; data.MQTTVersion = MQTT_VERSION_3_1_1; data.keepAliveInterval = MQTT_KEEPALIVE_INTERVAL_S; data.cleansession = true; while(true) { if(conn_failed_cnt > 0) { ATINY_LOG(LOG_INFO, "reconnect delay : %d", conn_failed_cnt); (void)LOS_TaskDelay(MQTT_CONN_FAILED_BASE_DELAY << conn_failed_cnt); } rc = NetworkConnect(&n, params->server_ip, atoi(params->server_port)); if(rc != 0) { ATINY_LOG(LOG_ERR, "NetworkConnect fail: %d", rc); mqtt_inc_fail_cnt(&conn_failed_cnt); continue; } if(mqtt_get_connection_info(handle, &data) != ATINY_OK) { mqtt_destroy_data_connection_info(&data); mqtt_proc_connect_err(client, &n, &conn_failed_cnt); continue; } rc = MQTTConnect(client, &data); mqtt_destroy_data_connection_info(&data); ATINY_LOG(LOG_DEBUG, "CONNACK : %d", rc); if(MQTT_SUCCESS != rc) { // receive connection nack value if (rc != MQTT_SUCCESS) { mqtt_proc_connect_nack(handle); } ATINY_LOG(LOG_ERR, "MQTTConnect failed %d", rc); mqtt_proc_connect_err(client, &n, &conn_failed_cnt); continue; } if(ATINY_OK != mqtt_subscribe_topic(handle)) { ATINY_LOG(LOG_ERR, "mqtt_subscribe_topic failed"); mqtt_proc_connect_err(client, &n, &conn_failed_cnt); continue; } conn_failed_cnt = 0; if (!mqtt_is_connectting_with_deviceid(handle)) { TimerInit(&timer); TimerCountdownMS(&timer, MQTT_WRITE_FOR_SECRET_TIMEOUT); } while (rc >= 0 && MQTTIsConnected(client)) { rc = MQTTYield(client, MQTT_EVENTS_HANDLE_PERIOD_MS); // receive secret info if (handle->dynamic_info.connection_update_flag) { ATINY_LOG(LOG_INFO, "recv secret info"); ATINY_LOG(LOG_DEBUG, "secret info deviceid %s", handle->dynamic_info.save_info.deviceid); handle->dynamic_info.connection_update_flag = false; handle->dynamic_info.state = MQTT_CONNECT_WITH_DEVICE_ID; break; } // wait secret info timeout. if (!mqtt_is_connectting_with_deviceid(handle) && (TimerIsExpired(&timer))) { if (handle->dynamic_info.has_device_id) { handle->dynamic_info.state = MQTT_CONNECT_WITH_DEVICE_ID; } break; } } mqtt_disconnect(client, &n); } result = ATINY_OK; atiny_bind_quit: mqtt_free_dynamic_info(handle); mqtt_free_params(&(handle->params)); (void)atiny_task_mutex_lock(&client->mutex); mqtt_free_device_info(&(handle->device_info)); (void)atiny_task_mutex_unlock(&client->mutex); MQTTClientDeInit(client); handle->init_flag = false; return result; } int atiny_mqtt_data_send(mqtt_client_s *phandle, const char *msg, uint32_t msg_len, mqtt_qos_e qos) { MQTTMessage message; int rc; char* topic; size_t payloadlen; if ((phandle == NULL) || (qos >= MQTT_QOS_MAX)) { ATINY_LOG(LOG_FATAL, "Parameter invalid"); return ATINY_ARG_INVALID; } if (phandle->device_info.codec_mode == MQTT_CODEC_MODE_JSON) { if (msg == NULL || msg_len <= 0) { ATINY_LOG(LOG_FATAL, "msg invalid"); return ATINY_ARG_INVALID; } payloadlen = strnlen(msg, msg_len); } else { if (msg == NULL && msg_len > 0) { ATINY_LOG(LOG_FATAL, "msg invalid"); return ATINY_ARG_INVALID; } payloadlen = msg_len; } if (!atiny_mqtt_isconnected(phandle)) { ATINY_LOG(LOG_FATAL, "not connected"); return ATINY_ERR; } topic = mqtt_get_device_topic(phandle, DATA_TOPIC_FMT, sizeof(DATA_TOPIC_FMT) - VARIABLE_SIZE); if (topic == NULL) { return ATINY_MALLOC_FAILED; } memset(&message, 0, sizeof(message)); message.qos = (enum QoS)qos; message.payload = (void *)msg; message.payloadlen = payloadlen; rc = MQTTPublish(&phandle->client, topic, &message); atiny_free(topic); if (rc != MQTT_SUCCESS) { ATINY_LOG(LOG_FATAL, "MQTTPublish fail,rc %d", rc); return ATINY_ERR; } return ATINY_OK; } int atiny_mqtt_isconnected(mqtt_client_s* phandle) { if (NULL == phandle) { ATINY_LOG(LOG_ERR, "invalid args"); return false; } return mqtt_is_connectting_with_deviceid(phandle) && MQTTIsConnected(&(phandle->client)); } ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/CONTRIBUTING.md ================================================ # Guide to contributing Please read this if you intend to contribute to the project. ## Legal stuff Apologies in advance for the extra work required here - this is necessary to comply with the Eclipse Foundation's strict IP policy. Please also read [this](http://wiki.eclipse.org/Development_Resources/Contributing_via_Git) In order for any contributions to be accepted you MUST do the following things. * Sign the [Eclipse Foundation Contributor License Agreement](http://www.eclipse.org/legal/CLA.php). To sign the Eclipse CLA you need to: * Obtain an Eclipse Foundation userid. Anyone who currently uses Eclipse Bugzilla or Gerrit systems already has one of those. If you don’t, you need to [register](https://dev.eclipse.org/site_login/createaccount.php). * Login into the [projects portal](https://projects.eclipse.org/), select “My Account”, and then the “Contributor License Agreement” tab. * Add your github username in your Eclipse Foundation account settings. Log in it to Eclipse and go to account settings. * "Sign-off" your commits Every commit you make in your patch or pull request MUST be "signed off". You do this by adding the `-s` flag when you make the commit(s), e.g. git commit -s -m "Shave the yak some more" ## Making your changes * Fork the repository on GitHub * Create a new branch for your changes * Make your changes * Make sure you include tests * Make sure the test suite passes after your changes * Commit your changes into that branch * Use descriptive and meaningful commit messages * If you have a lot of commits squash them into a single commit * Make sure you use the `-s` flag when committing as explained above. * Push your changes to your branch in your forked repository ## Submitting the changes Submit a pull request via the normal GitHub UI. ## After submitting * Do not use your branch for any other development, otherwise further changes that you make will be visible in the PR. ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/EDL-v1.0 ================================================ *Eclipse Distribution License - v 1.0* Copyright (c) 2007, Eclipse Foundation, Inc. and its licensors. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the Eclipse Foundation, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/EPL-v1.0 ================================================ Eclipse Public License - v 1.0 THE ACCOMPANYING PROGRAM IS PROVIDED UNDER THE TERMS OF THIS ECLIPSE PUBLIC LICENSE ("AGREEMENT"). ANY USE, REPRODUCTION OR DISTRIBUTION OF THE PROGRAM CONSTITUTES RECIPIENT'S ACCEPTANCE OF THIS AGREEMENT. *1. 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Everyone is permitted to copy and distribute copies of this Agreement, but in order to avoid inconsistency the Agreement is copyrighted and may only be modified in the following manner. The Agreement Steward reserves the right to publish new versions (including revisions) of this Agreement from time to time. No one other than the Agreement Steward has the right to modify this Agreement. The Eclipse Foundation is the initial Agreement Steward. The Eclipse Foundation may assign the responsibility to serve as the Agreement Steward to a suitable separate entity. Each new version of the Agreement will be given a distinguishing version number. The Program (including Contributions) may always be distributed subject to the version of the Agreement under which it was received. In addition, after a new version of the Agreement is published, Contributor may elect to distribute the Program (including its Contributions) under the new version. Except as expressly stated in Sections 2(a) and 2(b) above, Recipient receives no rights or licenses to the intellectual property of any Contributor under this Agreement, whether expressly, by implication, estoppel or otherwise. All rights in the Program not expressly granted under this Agreement are reserved. This Agreement is governed by the laws of the State of New York and the intellectual property laws of the United States of America. No party to this Agreement will bring a legal action under this Agreement more than one year after the cause of action arose. Each party waives its rights to a jury trial in any resulting litigation. ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/README.md ================================================ Wakaama (formerly liblwm2m) is an implementation of the Open Mobile Alliance's LightWeight M2M protocol (LWM2M). Developers mailing list: https://dev.eclipse.org/mailman/listinfo/wakaama-dev ## Source Layout -+- core (the LWM2M engine) | | | +- er-coap-13 (Slightly modified Erbium's CoAP engine from | http://people.inf.ethz.ch/mkovatsc/erbium.php | +- tests (test cases) | +- examples | +- bootstrap_server (a command-line LWM2M bootstrap server) | +- client (a command-line LWM2M client with several test objects) | +- lightclient (a very simple command-line LWM2M client with several test objects) | +- server (a command-line LWM2M server) | +- shared (utility functions for connection handling and command- line interface) ## Compiling Wakaama is not a library but files to be built with an application. Wakaama uses CMake >= 3. Look at examples/server/CMakeLists.txt for an example of how to include it. Several compilation switches are used: - LWM2M_BIG_ENDIAN if your target platform uses big-endian format. - LWM2M_LITTLE_ENDIAN if your target platform uses little-endian format. - LWM2M_CLIENT_MODE to enable LWM2M Client interfaces. - LWM2M_SERVER_MODE to enable LWM2M Server interfaces. - LWM2M_BOOTSTRAP_SERVER_MODE to enable LWM2M Bootstrap Server interfaces. - LWM2M_BOOTSTRAP to enable LWM2M Bootstrap support in a LWM2M Client. - LWM2M_SUPPORT_JSON to enable JSON payload support (implicit when defining LWM2M_SERVER_MODE) - LWM2M_OLD_CONTENT_FORMAT_SUPPORT to support the deprecated content format values for TLV and JSON. Depending on your platform, you need to define LWM2M_BIG_ENDIAN or LWM2M_LITTLE_ENDIAN. LWM2M_CLIENT_MODE and LWM2M_SERVER_MODE can be defined at the same time. ## Examples There are some example applications provided to test the server, client and bootstrap capabilities of Wakaama. The following recipes assume you are on a unix like platform and you have cmake and make installed. ### Server example * Create a build directory and change to that. * ``cmake [wakaama directory]/examples/server`` * ``make`` * ``./lwm2mserver [Options]`` The lwm2mserver listens on UDP port 5683. It features a basic command line interface. Type 'help' for a list of supported commands. Options are: - -4 Use IPv4 connection. Default: IPv6 connection ### Test client example * Create a build directory and change to that. * ``cmake [wakaama directory]/examples/client`` * ``make`` * ``./lwm2mclient [Options]`` DTLS feature requires the tinydtls submodule. To include it, on the first run, use the following commands to retrieve the sources: * ``git submodule init`` * ``git submodule update`` You need to install autoconf and automake to build with tinydtls. Build with tinydtls: * Create a build directory and change to that. * ``cmake -DDTLS=1 [wakaama directory]/examples/client`` * ``make`` * ``./lwm2mclient [Options]`` The lwm2mclient features nine LWM2M objects: - Security Object (id: 0) - Server Object (id: 1) - Access Control Object (id: 2) as a skeleton - Device Object (id: 3) containing hard-coded values from the Example LWM2M Client of Appendix E of the LWM2M Technical Specification. - Connectivity Monitoring Object (id: 4) as a skeleton - Firmware Update Object (id: 5) as a skeleton. - Location Object (id: 6) as a skeleton. - Connectivity Statistics Object (id: 7) as a skeleton. - Test Object (id: 31024) with the following description: Multiple Object | ID | Instances | Mandatory | Test | 31024 | Yes | No | Resources: Supported Multiple Name | ID | Operations | Instances | Mandatory | Type | Range | test | 1 | R/W | No | Yes | Integer | 0-255 | exec | 2 | E | No | Yes | | | dec | 3 | R/W | No | Yes | Float | | The lwm2mclient opens udp port 56830 and tries to register to a LWM2M Server at 127.0.0.1:5683. It features a basic command line interface. Type 'help' for a list of supported commands. Options are: - -n NAME Set the endpoint name of the Client. Default: testlwm2mclient - -l PORT Set the local UDP port of the Client. Default: 56830 - -h HOST Set the hostname of the LWM2M Server to connect to. Default: localhost - -p HOST Set the port of the LWM2M Server to connect to. Default: 5683 - -4 Use IPv4 connection. Default: IPv6 connection - -t TIME Set the lifetime of the Client. Default: 300 - -b Bootstrap requested. - -c Change battery level over time. If DTLS feature enable: - -i Set the device management or bootstrap server PSK identity. If not set use none secure mode - -s Set the device management or bootstrap server Pre-Shared-Key. If not set use none secure mode To launch a bootstrap session: ``./lwm2mclient -b`` ### Simpler test client example In the any directory, run the following commands: * Create a build directory and change to that. * ``cmake [wakaama directory]/examples/lightclient`` * ``make`` * ``./lightclient [Options]`` The lightclient is much simpler that the lwm2mclient and features only four LWM2M objects: - Security Object (id: 0) - Server Object (id: 1) - Device Object (id: 3) containing hard-coded values from the Example LWM2M Client of Appendix E of the LWM2M Technical Specification. - Test Object (id: 31024) from the lwm2mclient as described above. The lightclient does not feature any command-line interface. Options are: - -n NAME Set the endpoint name of the Client. Default: testlightclient - -l PORT Set the local UDP port of the Client. Default: 56830 - -4 Use IPv4 connection. Default: IPv6 connection ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/TODO ================================================ LWM2M Features -------------- - Access Control List - JSON support - Add token in every message - Handle Observe parameters - Keep-alive mechanism - Support for Object Link datatype - Discover method support Bugfixes -------- Implementation Improvements --------------------------- - Store lwm2m_transaction_t per peer - bufferize all CoaP messages until all callbacks returned Currently if a server sends a request from its monitoring callback upon client registration, the client will receive the request before the ACK to its register and it will discard it. - Easy access to the lwm2m_context_t from objects callbacks - Use an unified result callback Add some parameter so that the same user callback can be used for all DM operations. - Use lwm2m-*-t types in er-coap-13 To avoid multiple conversions. - Switch to void* parameters in lwm2m_list_* APIs - Utility functions to easily implements objects The utility will just use read and write individual resources. Either statically or through callbacks. See [https://github.com/01org/libdmclient]/tests/mgtobj/utils/static_mo_util.h ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/about.html ================================================ About

    About This Content

    April 24, 2014

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    The Eclipse Foundation makes available all content in this plug-in ("Content"). Unless otherwise indicated below, the Content is provided to you under the terms and conditions of the Eclipse Public License Version 1.0 ("EPL") and the Eclipse Distribution License Version 1.0 ("EDL"). A copy of the EPL is available at http://www.eclipse.org/legal/epl-v10.html. A copy of the EDL is available at http://www.eclipse.org/org/documents/edl-v10.php. For purposes of the EPL, "Program" will mean the Content.

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    er-coap-13

    Erbium's CoAP engine from http://people.inf.ethz.ch/mkovatsc/erbium.php Your use of er-coap-13 is subject to the terms and conditions of the BSD license contained in the file LICENSE in core/er-coap-13

    ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/block1.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2016 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Simon Bernard - initial API and implementation * *******************************************************************************/ /* Copyright (c) 2016 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "internals.h" #include #include #include // the maximum payload transferred by block1 we accumulate per server #define MAX_BLOCK1_SIZE 4096 uint8_t coap_block1_handler(lwm2m_block1_data_t **pBlock1Data, uint16_t mid, uint8_t *buffer, size_t length, uint16_t blockSize, uint32_t blockNum, bool blockMore, uint8_t **outputBuffer, size_t *outputLength) { lwm2m_block1_data_t *block1Data = *pBlock1Data;; // manage new block1 transfer if (blockNum == 0) { // we already have block1 data for this server, clear it if (block1Data != NULL) { lwm2m_free(block1Data->block1buffer); } else { block1Data = lwm2m_malloc(sizeof(lwm2m_block1_data_t)); *pBlock1Data = block1Data; if (NULL == block1Data) return COAP_500_INTERNAL_SERVER_ERROR; } block1Data->block1buffer = lwm2m_malloc(length); block1Data->block1bufferSize = length; if (NULL == block1Data->block1buffer) return COAP_500_INTERNAL_SERVER_ERROR; // write new block in buffer memcpy(block1Data->block1buffer, buffer, length); block1Data->lastmid = mid; } // manage already started block1 transfer else { if (block1Data == NULL) { // we never receive the first block // TODO should we clean block1 data for this server ? return COAP_408_REQ_ENTITY_INCOMPLETE; } // If this is a retransmission, we already did that. if (block1Data->lastmid != mid) { uint8_t *oldBuffer = block1Data->block1buffer; size_t oldSize = block1Data->block1bufferSize; if (block1Data->block1bufferSize != blockSize * blockNum) { // we don't receive block in right order // TODO should we clean block1 data for this server ? return COAP_408_REQ_ENTITY_INCOMPLETE; } // is it too large? if (block1Data->block1bufferSize + length >= MAX_BLOCK1_SIZE) { return COAP_413_ENTITY_TOO_LARGE; } // re-alloc new buffer block1Data->block1bufferSize = oldSize + length; block1Data->block1buffer = lwm2m_malloc(block1Data->block1bufferSize); if (NULL == block1Data->block1buffer) return COAP_500_INTERNAL_SERVER_ERROR; memcpy(block1Data->block1buffer, oldBuffer, oldSize); lwm2m_free(oldBuffer); // write new block in buffer memcpy(block1Data->block1buffer + oldSize, buffer, length); block1Data->lastmid = mid; } } if (blockMore) { *outputLength = (size_t) - 1; return COAP_231_CONTINUE; } else { // buffer is full, set output parameter // we don't free it to be able to send retransmission *outputLength = block1Data->block1bufferSize; *outputBuffer = block1Data->block1buffer; return NO_ERROR; } } void free_block1_buffer(lwm2m_block1_data_t *block1Data) { if (block1Data != NULL) { // free block1 buffer lwm2m_free(block1Data->block1buffer); block1Data->block1bufferSize = 0 ; // free current element lwm2m_free(block1Data); } } ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/bootstrap.c ================================================ /******************************************************************************* * * Copyright (c) 2015 Sierra Wireless and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Pascal Rieux - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * David Navarro, Intel Corporation - Please refer to git log * *******************************************************************************/ #include "internals.h" #include #include #include #ifdef LWM2M_CLIENT_MODE #ifdef LWM2M_BOOTSTRAP #define PRV_QUERY_BUFFER_LENGTH 200 static void prv_handleResponse(lwm2m_server_t *bootstrapServer, coap_packet_t *message) { if (COAP_204_CHANGED == message->code) { LOG("Received ACK/2.04, Bootstrap pending, waiting for DEL/PUT from BS server..."); bootstrapServer->status = STATE_BS_PENDING; bootstrapServer->registration = lwm2m_gettime() + COAP_EXCHANGE_LIFETIME; } else { bootstrapServer->status = STATE_BS_FAILING; } } static void prv_handleBootstrapReply(lwm2m_transaction_t *transaction, void *message) { lwm2m_server_t *bootstrapServer = (lwm2m_server_t *)transaction->userData; coap_packet_t *coapMessage = (coap_packet_t *)message; LOG("Entering"); if (bootstrapServer->status == STATE_BS_INITIATED) { if (NULL != coapMessage && COAP_TYPE_RST != coapMessage->type) { prv_handleResponse(bootstrapServer, coapMessage); } else { bootstrapServer->status = STATE_BS_FAILING; } } } // start a device initiated bootstrap static void prv_requestBootstrap(lwm2m_context_t *context, lwm2m_server_t *bootstrapServer) { char query[PRV_QUERY_BUFFER_LENGTH]; int query_length = 0; int res; LOG("Entering"); query_length = utils_stringCopy(query, PRV_QUERY_BUFFER_LENGTH, QUERY_STARTER QUERY_NAME); if (query_length < 0) { bootstrapServer->status = STATE_BS_FAILING; return; } res = utils_stringCopy(query + query_length, PRV_QUERY_BUFFER_LENGTH - query_length, context->endpointName); if (res < 0) { bootstrapServer->status = STATE_BS_FAILING; return; } query_length += res; if (bootstrapServer->sessionH == NULL) { bootstrapServer->sessionH = lwm2m_connect_server(bootstrapServer->secObjInstID, context->userData, false); } if (bootstrapServer->sessionH != NULL) { lwm2m_transaction_t *transaction = NULL; LOG("Bootstrap server connection opened"); transaction = transaction_new(bootstrapServer->sessionH, COAP_POST, NULL, NULL, context->nextMID++, 4, NULL); if (transaction == NULL) { bootstrapServer->status = STATE_BS_FAILING; return; } coap_set_header_uri_path(transaction->message, "/"URI_BOOTSTRAP_SEGMENT); coap_set_header_uri_query(transaction->message, query); transaction->callback = prv_handleBootstrapReply; transaction->userData = (void *)bootstrapServer; context->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(context->transactionList, transaction); if (transaction_send(context, transaction) == 0) { LOG("CI bootstrap requested to BS server"); bootstrapServer->status = STATE_BS_INITIATED; } } else { LOG("Connecting bootstrap server failed"); bootstrapServer->status = STATE_BS_FAILED; } } static void prv_resetBootstrapServer(lwm2m_server_t *serverP, void *userData) { if (serverP->sessionH != NULL) { lwm2m_close_connection(serverP->sessionH, userData); serverP->sessionH = NULL; } free_block1_buffer(serverP->block1Data); serverP->block1Data = NULL; } static void prv_createBsConnection(lwm2m_context_t *contextP, lwm2m_server_t *targetP) { prv_resetBootstrapServer(targetP, contextP->userData); if (lwm2m_isBsCtrlInServerInitiatedBs(contextP)) { if (targetP != NULL) { targetP->sessionH = lwm2m_connect_server(targetP->secObjInstID, contextP->userData, true); } return; } targetP->sessionH = lwm2m_connect_server(targetP->secObjInstID, contextP->userData, false); } /* * modify info: * modify date: 2019-06-04 * modify place: STATE_BS_HOLD_OFF, STATE_BS_PENDING * pay attention: * the targetP->status are important, change one, should take care of other status. * */ void bootstrap_step(lwm2m_context_t *contextP, uint32_t currentTime, time_t *timeoutP) { lwm2m_server_t *targetP; LOG("entering"); targetP = contextP->bootstrapServerList; while (targetP != NULL) { time_t timeOut; LOG_ARG("Initial status: %s", STR_STATUS(targetP->status)); switch (targetP->status) { case STATE_DEREGISTERED: //pay attention: targetP->lifetime come from securityobj instance, it's init value is 10. too small, too short for //STATE_BS_HOLD_OFF. of course, the value could be wrote by the bs server. encode decode used for securityobj/serverobj instance targetP->registration = currentTime; if(lwm2m_isBsCtrlInServerInitiatedBs(contextP)) { targetP->registration = (currentTime + targetP->lifetime); } prv_createBsConnection(contextP, targetP); currentTime = lwm2m_gettime(); targetP->status = STATE_BS_HOLD_OFF; timeOut = (targetP->registration - currentTime); if (timeOut < 0) { timeOut = 0; } if (*timeoutP > timeOut) { *timeoutP = timeOut; } break; case STATE_BS_HOLD_OFF: if (targetP->registration <= currentTime) { if (lwm2m_isBsCtrlInServerInitiatedBs(contextP)) { lwm2m_stop_striger_server_initiated_bs(targetP->sessionH); targetP->status = STATE_REG_FAILED; } else { prv_requestBootstrap(contextP, targetP); } } else if (*timeoutP > targetP->registration - currentTime) { *timeoutP = targetP->registration - currentTime; lwm2m_step_striger_server_initiated_bs(targetP->sessionH); } break; case STATE_BS_INITIATED: // waiting break; case STATE_BS_PENDING: if (targetP->registration <= currentTime) { targetP->status = STATE_BS_FAILING; *timeoutP = 0; } else if (*timeoutP > targetP->registration - currentTime) { *timeoutP = targetP->registration - currentTime; } break; case STATE_BS_FINISHING: if (targetP->sessionH != NULL) { lwm2m_close_connection(targetP->sessionH, contextP->userData); targetP->sessionH = NULL; } targetP->status = STATE_BS_FINISHED; *timeoutP = 0; break; case STATE_BS_FAILING: if (targetP->sessionH != NULL) { lwm2m_close_connection(targetP->sessionH, contextP->userData); targetP->sessionH = NULL; } targetP->status = STATE_BS_FAILED; *timeoutP = 0; break; default: break; } LOG_ARG("Finalal status: %s", STR_STATUS(targetP->status)); if (lwm2m_isBsCtrlInServerInitiatedBs(contextP)) { return; } targetP = targetP->next; } } uint8_t bootstrap_handleFinish(lwm2m_context_t *context, void *fromSessionH) { lwm2m_server_t *bootstrapServer; LOG("Entering"); bootstrapServer = utils_findBootstrapServer(context, fromSessionH); if (bootstrapServer != NULL && bootstrapServer->status == STATE_BS_PENDING) { if (object_getServers(context, true) == 0) { LOG("Bootstrap server status changed to STATE_BS_FINISHING"); bootstrapServer->status = STATE_BS_FINISHING; return COAP_204_CHANGED; } else { return COAP_406_NOT_ACCEPTABLE; } } return COAP_IGNORE; } bool bootstrap_isBsServerIpValid(const lwm2m_context_t *contextP) { lwm2m_server_t *targetP; targetP = contextP->bootstrapServerList; while (targetP != NULL) { if(lwm2m_is_sec_obj_uri_valid(targetP->secObjInstID, contextP->userData)) { return true; } targetP = targetP->next; } return false; } /* * Reset the bootstrap servers statuses * * TODO: handle LWM2M Servers the client is registered to ? * */ void bootstrap_start(lwm2m_context_t *contextP) { lwm2m_server_t *targetP; LOG("Entering"); targetP = contextP->bootstrapServerList; while (targetP != NULL) { targetP->status = STATE_DEREGISTERED; targetP = targetP->next; } } /* * Returns STATE_BS_PENDING if at least one bootstrap is still pending * Returns STATE_BS_FINISHED if at least one bootstrap succeeded and no bootstrap is pending * Returns STATE_BS_FAILED if all bootstrap failed. */ lwm2m_status_t bootstrap_getStatus(lwm2m_context_t *contextP) { lwm2m_server_t *targetP; lwm2m_status_t bs_status; LOG("Entering"); targetP = contextP->bootstrapServerList; bs_status = STATE_BS_FAILED; while (targetP != NULL) { switch (targetP->status) { case STATE_BS_FINISHED: if (bs_status == STATE_BS_FAILED) { bs_status = STATE_BS_FINISHED; } break; case STATE_BS_HOLD_OFF: case STATE_BS_INITIATED: case STATE_BS_PENDING: case STATE_BS_FINISHING: case STATE_BS_FAILING: bs_status = STATE_BS_PENDING; break; default: break; } targetP = targetP->next; } LOG_ARG("Returned status: %s", STR_STATUS(bs_status)); return bs_status; } static uint8_t prv_checkServerStatus(lwm2m_server_t *serverP) { LOG_ARG("Initial status: %s", STR_STATUS(serverP->status)); switch (serverP->status) { case STATE_BS_HOLD_OFF: serverP->status = STATE_BS_PENDING; LOG_ARG("Status changed to: %s", STR_STATUS(serverP->status)); break; case STATE_BS_INITIATED: // The ACK was probably lost serverP->status = STATE_BS_PENDING; LOG_ARG("Status changed to: %s", STR_STATUS(serverP->status)); break; case STATE_DEREGISTERED: // server initiated bootstrap case STATE_BS_PENDING: serverP->registration = lwm2m_gettime() + COAP_EXCHANGE_LIFETIME; break; case STATE_BS_FINISHED: case STATE_BS_FINISHING: case STATE_BS_FAILING: case STATE_BS_FAILED: default: LOG("Returning COAP_IGNORE"); return COAP_IGNORE; } return COAP_NO_ERROR; } static void prv_tagServer(lwm2m_context_t *contextP, uint16_t id) { lwm2m_server_t *targetP; targetP = (lwm2m_server_t *)LWM2M_LIST_FIND(contextP->bootstrapServerList, id); if (targetP == NULL) { targetP = (lwm2m_server_t *)LWM2M_LIST_FIND(contextP->serverList, id); } if (targetP != NULL) { targetP->dirty = true; } } static void prv_tagAllServer(lwm2m_context_t *contextP, lwm2m_server_t *serverP) { lwm2m_server_t *targetP; targetP = contextP->bootstrapServerList; while (targetP != NULL) { if (targetP != serverP) { targetP->dirty = true; } targetP = targetP->next; } targetP = contextP->serverList; while (targetP != NULL) { targetP->dirty = true; targetP = targetP->next; } } uint8_t bootstrap_handleCommand(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_server_t *serverP, coap_packet_t *message, coap_packet_t *response) { uint8_t result; lwm2m_media_type_t format; LOG_ARG("Code: %02X", message->code); LOG_URI(uriP); format = utils_convertMediaType(message->content_type); result = prv_checkServerStatus(serverP); if (result != COAP_NO_ERROR) return result; switch (message->code) { case COAP_PUT: { if (LWM2M_URI_IS_SET_INSTANCE(uriP)) { if (object_isInstanceNew(contextP, uriP->objectId, uriP->instanceId)) { result = object_create(contextP, uriP, format, message->payload, message->payload_len); if (COAP_201_CREATED == result) { result = COAP_204_CHANGED; } } else { result = object_write(contextP, uriP, format, message->payload, message->payload_len); if (uriP->objectId == LWM2M_SECURITY_OBJECT_ID && result == COAP_204_CHANGED) { prv_tagServer(contextP, uriP->instanceId); } } } else { lwm2m_data_t *dataP = NULL; int size = 0; int i; if (message->payload_len == 0 || message->payload == 0) { result = COAP_400_BAD_REQUEST; } else { size = lwm2m_data_parse(uriP, message->payload, message->payload_len, format, &dataP); if (size == 0) { result = COAP_500_INTERNAL_SERVER_ERROR; break; } for (i = 0 ; i < size ; i++) { if(dataP[i].type == LWM2M_TYPE_OBJECT_INSTANCE) { if (object_isInstanceNew(contextP, uriP->objectId, dataP[i].id)) { result = object_createInstance(contextP, uriP, &dataP[i]); if (COAP_201_CREATED == result) { result = COAP_204_CHANGED; } } else { result = object_writeInstance(contextP, uriP, &dataP[i]); if (uriP->objectId == LWM2M_SECURITY_OBJECT_ID && result == COAP_204_CHANGED) { prv_tagServer(contextP, dataP[i].id); } } if(result != COAP_204_CHANGED) // Stop object create or write when result is error { break; } } else { result = COAP_400_BAD_REQUEST; } } lwm2m_data_free(size, dataP); } } } break; case COAP_DELETE: { if (LWM2M_URI_IS_SET_RESOURCE(uriP)) { result = COAP_400_BAD_REQUEST; } else { result = object_delete(contextP, uriP); if (uriP->objectId == LWM2M_SECURITY_OBJECT_ID && result == COAP_202_DELETED) { if (LWM2M_URI_IS_SET_INSTANCE(uriP)) { prv_tagServer(contextP, uriP->instanceId); } else { prv_tagAllServer(contextP, NULL); } } } } break; case COAP_GET: case COAP_POST: default: result = COAP_400_BAD_REQUEST; break; } if (result == COAP_202_DELETED || result == COAP_204_CHANGED) { if (serverP->status != STATE_BS_PENDING) { serverP->status = STATE_BS_PENDING; contextP->state = STATE_BOOTSTRAPPING; } lwm2m_stop_striger_server_initiated_bs(serverP->sessionH); } LOG_ARG("Server status: %s", STR_STATUS(serverP->status)); return result; } uint8_t bootstrap_handleDeleteAll(lwm2m_context_t *contextP, void *fromSessionH) { lwm2m_server_t *serverP; uint8_t result; lwm2m_object_t *objectP; LOG("Entering"); serverP = utils_findBootstrapServer(contextP, fromSessionH); if (serverP == NULL) return COAP_IGNORE; result = prv_checkServerStatus(serverP); if (result != COAP_NO_ERROR) return result; result = COAP_202_DELETED; for (objectP = contextP->objectList; objectP != NULL; objectP = objectP->next) { lwm2m_uri_t uri; memset(&uri, 0, sizeof(lwm2m_uri_t)); uri.flag = LWM2M_URI_FLAG_OBJECT_ID; uri.objectId = objectP->objID; if (objectP->objID == LWM2M_SECURITY_OBJECT_ID) { lwm2m_list_t *instanceP; instanceP = objectP->instanceList; while (NULL != instanceP && result == COAP_202_DELETED) { if (instanceP->id == serverP->secObjInstID) { instanceP = instanceP->next; } else { uri.flag = LWM2M_URI_FLAG_OBJECT_ID | LWM2M_URI_FLAG_INSTANCE_ID; uri.instanceId = instanceP->id; result = object_delete(contextP, &uri); instanceP = objectP->instanceList; } } if (result == COAP_202_DELETED) { prv_tagAllServer(contextP, serverP); } } else { result = object_delete(contextP, &uri); if (result == COAP_405_METHOD_NOT_ALLOWED) { // Fake a successful deletion for static objects like the Device object. result = COAP_202_DELETED; } } } return result; } #endif #endif #ifdef LWM2M_BOOTSTRAP_SERVER_MODE uint8_t bootstrap_handleRequest(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, void *fromSessionH, coap_packet_t *message, coap_packet_t *response) { uint8_t result; char *name; LOG_URI(uriP); if (contextP->bootstrapCallback == NULL) return COAP_500_INTERNAL_SERVER_ERROR; if (message->code != COAP_POST) return COAP_400_BAD_REQUEST; if (message->uri_query == NULL) return COAP_400_BAD_REQUEST; if (message->payload != NULL) return COAP_400_BAD_REQUEST; if (lwm2m_strncmp((char *)message->uri_query->data, QUERY_NAME, QUERY_NAME_LEN) != 0) { return COAP_400_BAD_REQUEST; } if (message->uri_query->len == QUERY_NAME_LEN) return COAP_400_BAD_REQUEST; if (message->uri_query->next != NULL) return COAP_400_BAD_REQUEST; name = (char *)lwm2m_malloc(message->uri_query->len - QUERY_NAME_LEN + 1); if (name == NULL) return COAP_500_INTERNAL_SERVER_ERROR; memcpy(name, message->uri_query->data + QUERY_NAME_LEN, message->uri_query->len - QUERY_NAME_LEN); name[message->uri_query->len - QUERY_NAME_LEN] = 0; result = contextP->bootstrapCallback(fromSessionH, COAP_NO_ERROR, NULL, name, contextP->bootstrapUserData); lwm2m_free(name); return result; } void lwm2m_set_bootstrap_callback(lwm2m_context_t *contextP, lwm2m_bootstrap_callback_t callback, void *userData) { LOG("Entering"); contextP->bootstrapCallback = callback; contextP->bootstrapUserData = userData; } static void prv_resultCallback(lwm2m_transaction_t *transacP, void *message) { bs_data_t *dataP = (bs_data_t *)transacP->userData; lwm2m_uri_t *uriP; if (dataP->isUri == true) { uriP = &dataP->uri; } else { uriP = NULL; } if (message == NULL) { dataP->callback(transacP->peerH, COAP_503_SERVICE_UNAVAILABLE, uriP, NULL, dataP->userData); } else { coap_packet_t *packet = (coap_packet_t *)message; dataP->callback(transacP->peerH, packet->code, uriP, NULL, dataP->userData); } lwm2m_free(dataP); } int lwm2m_bootstrap_delete(lwm2m_context_t *contextP, void *sessionH, lwm2m_uri_t *uriP) { lwm2m_transaction_t *transaction; bs_data_t *dataP; LOG_URI(uriP); transaction = transaction_new(sessionH, COAP_DELETE, NULL, uriP, contextP->nextMID++, 4, NULL); if (transaction == NULL) return COAP_500_INTERNAL_SERVER_ERROR; dataP = (bs_data_t *)lwm2m_malloc(sizeof(bs_data_t)); if (dataP == NULL) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } if (uriP == NULL) { dataP->isUri = false; } else { dataP->isUri = true; memcpy(&dataP->uri, uriP, sizeof(lwm2m_uri_t)); } dataP->callback = contextP->bootstrapCallback; dataP->userData = contextP->bootstrapUserData; transaction->callback = prv_resultCallback; transaction->userData = (void *)dataP; contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transaction); return transaction_send(contextP, transaction); } int lwm2m_bootstrap_write(lwm2m_context_t *contextP, void *sessionH, lwm2m_uri_t *uriP, lwm2m_media_type_t format, uint8_t *buffer, size_t length) { lwm2m_transaction_t *transaction; bs_data_t *dataP; LOG_URI(uriP); if (uriP == NULL || buffer == NULL || length == 0) { return COAP_400_BAD_REQUEST; } transaction = transaction_new(sessionH, COAP_PUT, NULL, uriP, contextP->nextMID++, 4, NULL); if (transaction == NULL) return COAP_500_INTERNAL_SERVER_ERROR; coap_set_header_content_type(transaction->message, format); coap_set_payload(transaction->message, buffer, length); dataP = (bs_data_t *)lwm2m_malloc(sizeof(bs_data_t)); if (dataP == NULL) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } dataP->isUri = true; memcpy(&dataP->uri, uriP, sizeof(lwm2m_uri_t)); dataP->callback = contextP->bootstrapCallback; dataP->userData = contextP->bootstrapUserData; transaction->callback = prv_resultCallback; transaction->userData = (void *)dataP; contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transaction); return transaction_send(contextP, transaction); } int lwm2m_bootstrap_finish(lwm2m_context_t *contextP, void *sessionH) { lwm2m_transaction_t *transaction; bs_data_t *dataP; LOG("Entering"); transaction = transaction_new(sessionH, COAP_POST, NULL, NULL, contextP->nextMID++, 4, NULL); if (transaction == NULL) return COAP_500_INTERNAL_SERVER_ERROR; coap_set_header_uri_path(transaction->message, "/"URI_BOOTSTRAP_SEGMENT); dataP = (bs_data_t *)lwm2m_malloc(sizeof(bs_data_t)); if (dataP == NULL) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } dataP->isUri = false; dataP->callback = contextP->bootstrapCallback; dataP->userData = contextP->bootstrapUserData; transaction->callback = prv_resultCallback; transaction->userData = (void *)dataP; contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transaction); return transaction_send(contextP, transaction); } #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/data.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Fabien Fleutot - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * *******************************************************************************/ #include "internals.h" #include #define _PRV_STR_LENGTH 32 void lwm2m_data_decode_opaque(const lwm2m_data_t *dataP, int8_t *valueP) { memcpy(valueP, dataP->value.asBuffer.buffer, dataP->value.asBuffer.length); } // dataP array length is assumed to be 1. static int prv_textSerialize(lwm2m_data_t *dataP, uint8_t **bufferP) { size_t res; switch (dataP->type) { case LWM2M_TYPE_STRING: *bufferP = (uint8_t *)lwm2m_malloc(dataP->value.asBuffer.length); if (*bufferP == NULL) return 0; memcpy(*bufferP, dataP->value.asBuffer.buffer, dataP->value.asBuffer.length); return (int)dataP->value.asBuffer.length; case LWM2M_TYPE_INTEGER: { uint8_t intString[_PRV_STR_LENGTH]; res = utils_intToText(dataP->value.asInteger, intString, _PRV_STR_LENGTH); if (res == 0) return -1; *bufferP = (uint8_t *)lwm2m_malloc(res); if (NULL == *bufferP) return -1; memcpy(*bufferP, intString, res); return (int)res; } case LWM2M_TYPE_FLOAT: { uint8_t floatString[_PRV_STR_LENGTH * 2]; res = utils_floatToText(dataP->value.asFloat, floatString, _PRV_STR_LENGTH * 2); if (res == 0) return -1; *bufferP = (uint8_t *)lwm2m_malloc(res); if (NULL == *bufferP) return -1; memcpy(*bufferP, floatString, res); return (int)res; } case LWM2M_TYPE_BOOLEAN: *bufferP = (uint8_t *)lwm2m_malloc(1); if (NULL == *bufferP) return -1; *bufferP[0] = dataP->value.asBoolean ? '1' : '0'; return 1; case LWM2M_TYPE_OBJECT_LINK: { char stringBuffer[11]; size_t length; length = utils_intToText(dataP->value.asObjLink.objectId, (uint8_t *)stringBuffer, 5); if (length == 0) return -1; stringBuffer[5] = ':'; res = length + 1; length = utils_intToText(dataP->value.asObjLink.objectInstanceId, (uint8_t *)stringBuffer + res, 5); if (length == 0) return -1; res += length; *bufferP = (uint8_t *)lwm2m_malloc(res); if (*bufferP == NULL) return -1; memcpy(*bufferP, stringBuffer, res); return res; } case LWM2M_TYPE_OPAQUE: { size_t length; length = utils_base64GetSize(dataP->value.asBuffer.length); *bufferP = (uint8_t *)lwm2m_malloc(length); if (*bufferP == NULL) return 0; length = utils_base64Encode(dataP->value.asBuffer.buffer, dataP->value.asBuffer.length, *bufferP, length); if (length == 0) { lwm2m_free(*bufferP); *bufferP = NULL; return 0; } return (int)length; } case LWM2M_TYPE_UNDEFINED: default: return -1; } } static int prv_setBuffer(lwm2m_data_t *dataP, uint8_t *buffer, size_t bufferLen) { dataP->value.asBuffer.buffer = (uint8_t *)lwm2m_malloc(bufferLen); if (dataP->value.asBuffer.buffer == NULL) { return 0; } dataP->value.asBuffer.length = bufferLen; memcpy(dataP->value.asBuffer.buffer, buffer, bufferLen); return 1; } lwm2m_data_t *lwm2m_data_new(int size) { lwm2m_data_t *dataP; LOG_ARG("size: %d", size); if (size <= 0) return NULL; dataP = (lwm2m_data_t *)lwm2m_malloc(size * sizeof(lwm2m_data_t)); if (dataP != NULL) { memset(dataP, 0, size * sizeof(lwm2m_data_t)); } return dataP; } void lwm2m_data_free(int size, lwm2m_data_t *dataP) { int i; LOG_ARG("size: %d", size); if (size == 0 || dataP == NULL) return; for (i = 0; i < size; i++) { switch (dataP[i].type) { case LWM2M_TYPE_MULTIPLE_RESOURCE: case LWM2M_TYPE_OBJECT_INSTANCE: case LWM2M_TYPE_OBJECT: lwm2m_data_free(dataP[i].value.asChildren.count, dataP[i].value.asChildren.array); break; case LWM2M_TYPE_STRING: case LWM2M_TYPE_OPAQUE: if (dataP[i].value.asBuffer.buffer != NULL) { lwm2m_free(dataP[i].value.asBuffer.buffer); } default: // do nothing break; } } lwm2m_free(dataP); } void lwm2m_data_encode_string(const char *string, lwm2m_data_t *dataP) { size_t len; int res; LOG_ARG("\"%s\"", string); if (string == NULL) { len = 0; } else { for (len = 0; string[len] != 0; len++); } if (len == 0) { dataP->value.asBuffer.length = 0; dataP->value.asBuffer.buffer = NULL; res = 1; } else { res = prv_setBuffer(dataP, (uint8_t *)string, len); } if (res == 1) { dataP->type = LWM2M_TYPE_STRING; } else { dataP->type = LWM2M_TYPE_UNDEFINED; } } void lwm2m_data_encode_opaque(uint8_t *buffer, size_t length, lwm2m_data_t *dataP) { int res; LOG_ARG("length: %d", length); if (length == 0) { dataP->value.asBuffer.length = 0; dataP->value.asBuffer.buffer = NULL; res = 1; } else { res = prv_setBuffer(dataP, buffer, length); } if (res == 1) { dataP->type = LWM2M_TYPE_OPAQUE; } else { dataP->type = LWM2M_TYPE_UNDEFINED; } } void lwm2m_data_encode_nstring(const char *string, size_t length, lwm2m_data_t *dataP) { LOG_ARG("length: %d, string: \"%s\"", length, string); lwm2m_data_encode_opaque((uint8_t *)string, length, dataP); if (dataP->type == LWM2M_TYPE_OPAQUE) { dataP->type = LWM2M_TYPE_STRING; } } void lwm2m_data_encode_int(int64_t value, lwm2m_data_t *dataP) { LOG_ARG("value: %" PRId64 "", value); dataP->type = LWM2M_TYPE_INTEGER; dataP->value.asInteger = value; } int lwm2m_data_decode_int(const lwm2m_data_t *dataP, int64_t *valueP) { int result; LOG("Entering"); switch (dataP->type) { case LWM2M_TYPE_INTEGER: *valueP = dataP->value.asInteger; result = 1; break; case LWM2M_TYPE_STRING: result = utils_textToInt(dataP->value.asBuffer.buffer, dataP->value.asBuffer.length, valueP); break; case LWM2M_TYPE_OPAQUE: switch (dataP->value.asBuffer.length) { case 1: *valueP = (int8_t)dataP->value.asBuffer.buffer[0]; result = 1; break; case 2: { int16_t value; utils_copyValue(&value, dataP->value.asBuffer.buffer, dataP->value.asBuffer.length); *valueP = value; result = 1; break; } case 4: { int32_t value; utils_copyValue(&value, dataP->value.asBuffer.buffer, dataP->value.asBuffer.length); *valueP = value; result = 1; break; } case 8: utils_copyValue(valueP, dataP->value.asBuffer.buffer, dataP->value.asBuffer.length); result = 1; break; default: result = 0; } break; default: return 0; } LOG_ARG("result: %d, value: %" PRId64, result, *valueP); return result; } void lwm2m_data_encode_float(double value, lwm2m_data_t *dataP) { LOG_ARG("value: %f", value); dataP->type = LWM2M_TYPE_FLOAT; dataP->value.asFloat = value; } int lwm2m_data_decode_float(const lwm2m_data_t *dataP, double *valueP) { int result; LOG("Entering"); switch (dataP->type) { case LWM2M_TYPE_FLOAT: *valueP = dataP->value.asFloat; result = 1; break; case LWM2M_TYPE_INTEGER: *valueP = (double)dataP->value.asInteger; result = 1; break; case LWM2M_TYPE_STRING: result = utils_textToFloat(dataP->value.asBuffer.buffer, dataP->value.asBuffer.length, valueP); break; case LWM2M_TYPE_OPAQUE: switch (dataP->value.asBuffer.length) { case 4: { float temp; utils_copyValue(&temp, dataP->value.asBuffer.buffer, dataP->value.asBuffer.length); *valueP = temp; result = 1; } break; case 8: utils_copyValue(valueP, dataP->value.asBuffer.buffer, dataP->value.asBuffer.length); result = 1; break; default: result = 0; } break; default: result = 0; } LOG_ARG("result: %d, value: %f", result, *valueP); return result; } void lwm2m_data_encode_bool(bool value, lwm2m_data_t *dataP) { LOG_ARG("value: %s", value ? "true" : "false"); dataP->type = LWM2M_TYPE_BOOLEAN; dataP->value.asBoolean = value; } int lwm2m_data_decode_bool(const lwm2m_data_t *dataP, bool *valueP) { int result; LOG("Entering"); switch (dataP->type) { case LWM2M_TYPE_BOOLEAN: *valueP = dataP->value.asBoolean; result = 1; break; case LWM2M_TYPE_STRING: if (dataP->value.asBuffer.length != 1) return 0; switch (dataP->value.asBuffer.buffer[0]) { case '0': *valueP = false; result = 1; break; case '1': *valueP = true; result = 1; break; default: result = 0; break; } break; case LWM2M_TYPE_OPAQUE: if (dataP->value.asBuffer.length != 1) return 0; switch (dataP->value.asBuffer.buffer[0]) { case 0: *valueP = false; result = 1; break; case 1: *valueP = true; result = 1; break; default: result = 0; break; } break; default: result = 0; break; } LOG_ARG("result: %d, value: %s", result, *valueP ? "true" : "false"); return result; } void lwm2m_data_encode_objlink(uint16_t objectId, uint16_t objectInstanceId, lwm2m_data_t *dataP) { LOG_ARG("value: %d/%d", objectId, objectInstanceId); dataP->type = LWM2M_TYPE_OBJECT_LINK; dataP->value.asObjLink.objectId = objectId; dataP->value.asObjLink.objectInstanceId = objectInstanceId; } void lwm2m_data_include(lwm2m_data_t *subDataP, size_t count, lwm2m_data_t *dataP) { LOG_ARG("count: %d", count); if (subDataP == NULL || count == 0) return; switch (subDataP[0].type) { case LWM2M_TYPE_STRING: case LWM2M_TYPE_OPAQUE: case LWM2M_TYPE_INTEGER: case LWM2M_TYPE_FLOAT: case LWM2M_TYPE_BOOLEAN: case LWM2M_TYPE_OBJECT_LINK: case LWM2M_TYPE_MULTIPLE_RESOURCE: dataP->type = LWM2M_TYPE_OBJECT_INSTANCE; break; case LWM2M_TYPE_OBJECT_INSTANCE: dataP->type = LWM2M_TYPE_OBJECT; break; default: return; } dataP->value.asChildren.count = count; dataP->value.asChildren.array = subDataP; } void lwm2m_data_encode_instances(lwm2m_data_t *subDataP, size_t count, lwm2m_data_t *dataP) { LOG_ARG("count: %d", count); lwm2m_data_include(subDataP, count, dataP); dataP->type = LWM2M_TYPE_MULTIPLE_RESOURCE; } int lwm2m_data_parse(lwm2m_uri_t *uriP, uint8_t *buffer, size_t bufferLen, lwm2m_media_type_t format, lwm2m_data_t **dataP) { int res; LOG_ARG("format: %s, bufferLen: %d", STR_MEDIA_TYPE(format), bufferLen); LOG_URI(uriP); switch (format) { case LWM2M_CONTENT_TEXT: if (!LWM2M_URI_IS_SET_RESOURCE(uriP)) return 0; *dataP = lwm2m_data_new(1); if (*dataP == NULL) return 0; (*dataP)->id = uriP->resourceId; (*dataP)->type = LWM2M_TYPE_STRING; res = prv_setBuffer(*dataP, buffer, bufferLen); if (res == 0) { lwm2m_data_free(1, *dataP); *dataP = NULL; } return res; case LWM2M_CONTENT_OPAQUE: if (!LWM2M_URI_IS_SET_RESOURCE(uriP)) return 0; *dataP = lwm2m_data_new(1); if (*dataP == NULL) return 0; (*dataP)->id = uriP->resourceId; (*dataP)->type = LWM2M_TYPE_OPAQUE; res = prv_setBuffer(*dataP, buffer, bufferLen); if (res == 0) { lwm2m_data_free(1, *dataP); *dataP = NULL; } return res; #ifdef LWM2M_OLD_CONTENT_FORMAT_SUPPORT case LWM2M_CONTENT_TLV_OLD: #endif case LWM2M_CONTENT_TLV: return tlv_parse(buffer, bufferLen, dataP); #ifdef LWM2M_SUPPORT_JSON #ifdef LWM2M_OLD_CONTENT_FORMAT_SUPPORT case LWM2M_CONTENT_JSON_OLD: #endif case LWM2M_CONTENT_JSON: return json_parse(uriP, buffer, bufferLen, dataP); #endif default: return 0; } } int lwm2m_data_serialize(lwm2m_uri_t *uriP, int size, lwm2m_data_t *dataP, lwm2m_media_type_t *formatP, uint8_t **bufferP) { LOG_URI(uriP); LOG_ARG("size: %d, formatP: %s", size, STR_MEDIA_TYPE(*formatP)); // Check format if (*formatP == LWM2M_CONTENT_TEXT || *formatP == LWM2M_CONTENT_OPAQUE) { if (size != 1 || (uriP != NULL && !LWM2M_URI_IS_SET_RESOURCE(uriP)) || dataP->type == LWM2M_TYPE_OBJECT || dataP->type == LWM2M_TYPE_OBJECT_INSTANCE || dataP->type == LWM2M_TYPE_MULTIPLE_RESOURCE) { #ifdef LWM2M_SUPPORT_JSON *formatP = LWM2M_CONTENT_JSON; #else *formatP = LWM2M_CONTENT_TLV; #endif } } if (*formatP == LWM2M_CONTENT_OPAQUE && dataP->type != LWM2M_TYPE_OPAQUE) { LOG("Opaque format is reserved to opaque resources."); return -1; } if (dm_isUriOpaqueHandle(uriP)) { *formatP = LWM2M_CONTENT_OPAQUE; } LOG_ARG("Final format: %s", STR_MEDIA_TYPE(*formatP)); switch (*formatP) { case LWM2M_CONTENT_TEXT: return prv_textSerialize(dataP, bufferP); case LWM2M_CONTENT_OPAQUE: *bufferP = (uint8_t *)lwm2m_malloc(dataP->value.asBuffer.length); if (*bufferP == NULL) return -1; memcpy(*bufferP, dataP->value.asBuffer.buffer, dataP->value.asBuffer.length); return (int)dataP->value.asBuffer.length; case LWM2M_CONTENT_TLV: case LWM2M_CONTENT_TLV_OLD: { bool isResourceInstance; if (uriP != NULL && LWM2M_URI_IS_SET_RESOURCE(uriP) && (size != 1 || dataP->id != uriP->resourceId)) { isResourceInstance = true; } else { isResourceInstance = false; } return tlv_serialize(isResourceInstance, size, dataP, bufferP); } #ifdef LWM2M_CLIENT_MODE case LWM2M_CONTENT_LINK: return discover_serialize(NULL, uriP, NULL, size, dataP, bufferP); #endif #ifdef LWM2M_SUPPORT_JSON case LWM2M_CONTENT_JSON: case LWM2M_CONTENT_JSON_OLD: return json_serialize(uriP, size, dataP, bufferP); #endif default: return -1; } } ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/discover.c ================================================ /******************************************************************************* * * Copyright (c) 2015 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * *******************************************************************************/ #include "internals.h" #define PRV_LINK_BUFFER_SIZE 1024 #define PRV_CONCAT_STR(buf, len, index, str, str_len) \ { \ if ((len)-(index) < (str_len)) return -1; \ memcpy((buf)+(index), (str), (str_len)); \ (index) += (str_len); \ } #ifdef LWM2M_CLIENT_MODE static lwm2m_attributes_t *prv_findAttributes(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_server_t *serverP) { lwm2m_observed_t *observedP; lwm2m_watcher_t *watcherP; lwm2m_attributes_t *paramP; paramP = NULL; if (contextP == NULL) return NULL; if (serverP == NULL) return NULL; observedP = observe_findByUri(contextP, uriP); if (observedP == NULL || observedP->watcherList == NULL) return NULL; for (watcherP = observedP->watcherList; watcherP != NULL; watcherP = watcherP->next) { if (watcherP->server == serverP) { paramP = watcherP->parameters; } } return paramP; } static int prv_serializeAttributes(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_server_t *serverP, lwm2m_attributes_t *objectParamP, uint8_t *buffer, size_t uriLen, size_t bufferLen) { int head; int res; lwm2m_attributes_t *paramP; head = 0; paramP = prv_findAttributes(contextP, uriP, serverP); if (paramP == NULL) paramP = objectParamP; if (paramP != NULL) { head = uriLen; if (paramP->toSet & LWM2M_ATTR_FLAG_MIN_PERIOD) { PRV_CONCAT_STR(buffer, bufferLen, head, LINK_ATTR_SEPARATOR, LINK_ATTR_SEPARATOR_SIZE); PRV_CONCAT_STR(buffer, bufferLen, head, ATTR_MIN_PERIOD_STR, ATTR_MIN_PERIOD_LEN); res = utils_intToText(paramP->minPeriod, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; } else if (objectParamP->toSet & LWM2M_ATTR_FLAG_MIN_PERIOD) { PRV_CONCAT_STR(buffer, bufferLen, head, LINK_ATTR_SEPARATOR, LINK_ATTR_SEPARATOR_SIZE); PRV_CONCAT_STR(buffer, bufferLen, head, ATTR_MIN_PERIOD_STR, ATTR_MIN_PERIOD_LEN); res = utils_intToText(objectParamP->minPeriod, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; } if (paramP->toSet & LWM2M_ATTR_FLAG_MAX_PERIOD) { PRV_CONCAT_STR(buffer, bufferLen, head, LINK_ATTR_SEPARATOR, LINK_ATTR_SEPARATOR_SIZE); PRV_CONCAT_STR(buffer, bufferLen, head, ATTR_MAX_PERIOD_STR, ATTR_MAX_PERIOD_LEN); res = utils_intToText(paramP->maxPeriod, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; } else if (objectParamP->toSet & LWM2M_ATTR_FLAG_MAX_PERIOD) { PRV_CONCAT_STR(buffer, bufferLen, head, LINK_ATTR_SEPARATOR, LINK_ATTR_SEPARATOR_SIZE); PRV_CONCAT_STR(buffer, bufferLen, head, ATTR_MAX_PERIOD_STR, ATTR_MAX_PERIOD_LEN); res = utils_intToText(objectParamP->maxPeriod, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; } if (paramP->toSet & LWM2M_ATTR_FLAG_GREATER_THAN) { PRV_CONCAT_STR(buffer, bufferLen, head, LINK_ATTR_SEPARATOR, LINK_ATTR_SEPARATOR_SIZE); PRV_CONCAT_STR(buffer, bufferLen, head, ATTR_GREATER_THAN_STR, ATTR_GREATER_THAN_LEN); res = utils_floatToText(paramP->greaterThan, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; } if (paramP->toSet & LWM2M_ATTR_FLAG_LESS_THAN) { PRV_CONCAT_STR(buffer, bufferLen, head, LINK_ATTR_SEPARATOR, LINK_ATTR_SEPARATOR_SIZE); PRV_CONCAT_STR(buffer, bufferLen, head, ATTR_LESS_THAN_STR, ATTR_LESS_THAN_LEN); res = utils_floatToText(paramP->lessThan, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; } if (paramP->toSet & LWM2M_ATTR_FLAG_STEP) { PRV_CONCAT_STR(buffer, bufferLen, head, LINK_ATTR_SEPARATOR, LINK_ATTR_SEPARATOR_SIZE); PRV_CONCAT_STR(buffer, bufferLen, head, ATTR_STEP_STR, ATTR_STEP_LEN); res = utils_floatToText(paramP->step, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; } PRV_CONCAT_STR(buffer, bufferLen, head, LINK_ITEM_ATTR_END, LINK_ITEM_ATTR_END_SIZE); } if (head > 0) head -= uriLen + 1; return head; } static int prv_serializeLinkData(lwm2m_context_t *contextP, lwm2m_data_t *tlvP, lwm2m_server_t *serverP, lwm2m_attributes_t *objectParamP, lwm2m_uri_t *parentUriP, uint8_t *parentUriStr, size_t parentUriLen, uint8_t *buffer, size_t bufferLen) { int head; int res; lwm2m_uri_t uri; head = 0; switch (tlvP->type) { case LWM2M_TYPE_UNDEFINED: case LWM2M_TYPE_STRING: case LWM2M_TYPE_OPAQUE: case LWM2M_TYPE_INTEGER: case LWM2M_TYPE_FLOAT: case LWM2M_TYPE_BOOLEAN: case LWM2M_TYPE_OBJECT_LINK: case LWM2M_TYPE_MULTIPLE_RESOURCE: if (bufferLen < LINK_ITEM_START_SIZE) return -1; memcpy(buffer + head, LINK_ITEM_START, LINK_ITEM_START_SIZE); head = LINK_ITEM_START_SIZE; if (parentUriLen > 0) { if (bufferLen - head < parentUriLen) return -1; memcpy(buffer + head, parentUriStr, parentUriLen); head += parentUriLen; } if (bufferLen - head < LINK_URI_SEPARATOR_SIZE) return -1; memcpy(buffer + head, LINK_URI_SEPARATOR, LINK_URI_SEPARATOR_SIZE); head += LINK_URI_SEPARATOR_SIZE; res = utils_intToText(tlvP->id, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; if (tlvP->type == LWM2M_TYPE_MULTIPLE_RESOURCE) { if (bufferLen - head < LINK_ITEM_DIM_START_SIZE) return -1; memcpy(buffer + head, LINK_ITEM_DIM_START, LINK_ITEM_DIM_START_SIZE); head += LINK_ITEM_DIM_START_SIZE; res = utils_intToText(tlvP->value.asChildren.count, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; if (bufferLen - head < LINK_ITEM_ATTR_END_SIZE) return -1; memcpy(buffer + head, LINK_ITEM_ATTR_END, LINK_ITEM_ATTR_END_SIZE); head += LINK_ITEM_ATTR_END_SIZE; } else { if (bufferLen - head < LINK_ITEM_END_SIZE) return -1; memcpy(buffer + head, LINK_ITEM_END, LINK_ITEM_END_SIZE); head += LINK_ITEM_END_SIZE; } if (serverP != NULL) { memcpy(&uri, parentUriP, sizeof(lwm2m_uri_t)); uri.resourceId = tlvP->id; uri.flag |= LWM2M_URI_FLAG_RESOURCE_ID; res = prv_serializeAttributes(contextP, &uri, serverP, objectParamP, buffer, head - 1, bufferLen); if (res < 0) return -1; // careful, 0 is valid if (res > 0) head += res; } break; case LWM2M_TYPE_OBJECT_INSTANCE: { uint8_t uriStr[URI_MAX_STRING_LEN]; size_t uriLen; size_t index; if (parentUriLen > 0) { if (URI_MAX_STRING_LEN < parentUriLen) return -1; memcpy(uriStr, parentUriStr, parentUriLen); uriLen = parentUriLen; } else { uriLen = 0; } if (URI_MAX_STRING_LEN - uriLen < LINK_URI_SEPARATOR_SIZE) return -1; memcpy(uriStr + uriLen, LINK_URI_SEPARATOR, LINK_URI_SEPARATOR_SIZE); uriLen += LINK_URI_SEPARATOR_SIZE; res = utils_intToText(tlvP->id, uriStr + uriLen, URI_MAX_STRING_LEN - uriLen); if (res <= 0) return -1; uriLen += res; memcpy(&uri, parentUriP, sizeof(lwm2m_uri_t)); uri.instanceId = tlvP->id; uri.flag |= LWM2M_URI_FLAG_INSTANCE_ID; head = 0; PRV_CONCAT_STR(buffer, bufferLen, head, LINK_ITEM_START, LINK_ITEM_START_SIZE); PRV_CONCAT_STR(buffer, bufferLen, head, uriStr, uriLen); PRV_CONCAT_STR(buffer, bufferLen, head, LINK_ITEM_END, LINK_ITEM_END_SIZE); if (serverP != NULL) { res = prv_serializeAttributes(contextP, &uri, serverP, NULL, buffer, head - 1, bufferLen); if (res < 0) return -1; // careful, 0 is valid if (res == 0) head = 0; // rewind else head += res; } for (index = 0; index < tlvP->value.asChildren.count; index++) { res = prv_serializeLinkData(contextP, tlvP->value.asChildren.array + index, serverP, objectParamP, &uri, uriStr, uriLen, buffer + head, bufferLen - head); if (res < 0) return -1; head += res; } } break; case LWM2M_TYPE_OBJECT: default: return -1; } return head; } int discover_serialize(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_server_t *serverP, int size, lwm2m_data_t *dataP, uint8_t **bufferP) { uint8_t bufferLink[PRV_LINK_BUFFER_SIZE]; uint8_t baseUriStr[URI_MAX_STRING_LEN]; int baseUriLen; int index; size_t head; int res; lwm2m_uri_t parentUri; lwm2m_attributes_t *paramP; lwm2m_attributes_t mergedParam; LOG_ARG("size: %d", size); LOG_URI(uriP); head = 0; memset(&parentUri, 0, sizeof(lwm2m_uri_t)); parentUri.objectId = uriP->objectId; parentUri.flag = LWM2M_URI_FLAG_OBJECT_ID; if (LWM2M_URI_IS_SET_RESOURCE(uriP)) { lwm2m_uri_t tempUri; lwm2m_attributes_t *objParamP; lwm2m_attributes_t *instParamP; memset(&parentUri, 0, sizeof(lwm2m_uri_t)); tempUri.objectId = uriP->objectId; tempUri.flag = LWM2M_URI_FLAG_OBJECT_ID; // get object level attributes objParamP = prv_findAttributes(contextP, &tempUri, serverP); // get object instance level attributes tempUri.instanceId = uriP->instanceId; tempUri.flag = LWM2M_URI_FLAG_INSTANCE_ID; instParamP = prv_findAttributes(contextP, &tempUri, serverP); if (objParamP != NULL) { if (instParamP != NULL) { memset(&mergedParam, 0, sizeof(lwm2m_attributes_t)); mergedParam.toSet = objParamP->toSet | instParamP->toSet; if (mergedParam.toSet & LWM2M_ATTR_FLAG_MIN_PERIOD) { if (instParamP->toSet & LWM2M_ATTR_FLAG_MIN_PERIOD) { mergedParam.minPeriod = instParamP->minPeriod; } else { mergedParam.minPeriod = objParamP->minPeriod; } } if (mergedParam.toSet & LWM2M_ATTR_FLAG_MAX_PERIOD) { if (instParamP->toSet & LWM2M_ATTR_FLAG_MAX_PERIOD) { mergedParam.maxPeriod = instParamP->maxPeriod; } else { mergedParam.maxPeriod = objParamP->maxPeriod; } } paramP = &mergedParam; } else { paramP = objParamP; } } else { paramP = instParamP; } uriP->flag &= ~LWM2M_URI_FLAG_RESOURCE_ID; } else { paramP = NULL; if (LWM2M_URI_IS_SET_INSTANCE(uriP)) { PRV_CONCAT_STR(bufferLink, PRV_LINK_BUFFER_SIZE, head, LINK_ITEM_START, LINK_ITEM_START_SIZE); PRV_CONCAT_STR(bufferLink, PRV_LINK_BUFFER_SIZE, head, LINK_URI_SEPARATOR, LINK_URI_SEPARATOR_SIZE); res = utils_intToText(uriP->objectId, bufferLink + head, PRV_LINK_BUFFER_SIZE - head); if (res <= 0) return -1; head += res; PRV_CONCAT_STR(bufferLink, PRV_LINK_BUFFER_SIZE, head, LINK_URI_SEPARATOR, LINK_URI_SEPARATOR_SIZE); res = utils_intToText(uriP->instanceId, bufferLink + head, PRV_LINK_BUFFER_SIZE - head); if (res <= 0) return -1; head += res; PRV_CONCAT_STR(bufferLink, PRV_LINK_BUFFER_SIZE, head, LINK_ITEM_END, LINK_ITEM_END_SIZE); parentUri.instanceId = uriP->instanceId; parentUri.flag = LWM2M_URI_FLAG_INSTANCE_ID; if (serverP != NULL) { res = prv_serializeAttributes(contextP, &parentUri, serverP, NULL, bufferLink, head - 1, PRV_LINK_BUFFER_SIZE); if (res < 0) return -1; // careful, 0 is valid } else { res = 0; } head += res; } else { PRV_CONCAT_STR(bufferLink, PRV_LINK_BUFFER_SIZE, head, LINK_ITEM_START, LINK_ITEM_START_SIZE); PRV_CONCAT_STR(bufferLink, PRV_LINK_BUFFER_SIZE, head, LINK_URI_SEPARATOR, LINK_URI_SEPARATOR_SIZE); res = utils_intToText(uriP->objectId, bufferLink + head, PRV_LINK_BUFFER_SIZE - head); if (res <= 0) return -1; head += res; PRV_CONCAT_STR(bufferLink, PRV_LINK_BUFFER_SIZE, head, LINK_ITEM_END, LINK_ITEM_END_SIZE); if (serverP != NULL) { res = prv_serializeAttributes(contextP, &parentUri, serverP, NULL, bufferLink, head - 1, PRV_LINK_BUFFER_SIZE); if (res < 0) return -1; // careful, 0 is valid head += res; } } } baseUriLen = uri_toString(uriP, baseUriStr, URI_MAX_STRING_LEN, NULL); if (baseUriLen < 0) return -1; baseUriLen -= 1; for (index = 0; index < size && head < PRV_LINK_BUFFER_SIZE; index++) { res = prv_serializeLinkData(contextP, dataP + index, serverP, paramP, uriP, baseUriStr, baseUriLen, bufferLink + head, PRV_LINK_BUFFER_SIZE - head); if (res < 0) return -1; head += res; } if (head > 0) { head -= 1; *bufferP = (uint8_t *)lwm2m_malloc(head); if (*bufferP == NULL) return 0; memcpy(*bufferP, bufferLink, head); } return (int)head; } #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/er-coap-13/LICENSE ================================================ /* * Copyright (c) 2013, Institute for Pervasive Computing, ETH Zurich * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the Institute nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * This file is part of the Contiki operating system. */ ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/er-coap-13/er-coap-13.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /* * Copyright (c) 2013, Institute for Pervasive Computing, ETH Zurich * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the Institute nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * This file is part of the Contiki operating system. */ /** * \file * An implementation of the Constrained Application Protocol (draft 12) * \author * Matthias Kovatsch * \contributors * David Navarro, Intel Corporation - Adapt to usage in liblwm2m */ #include #include #include #include "er-coap-13.h" #include "internals.h" #include "liblwm2m.h" /* for lwm2m_malloc() and lwm2m_free() */ #define DEBUG 0 #if DEBUG #include #define PRINTF(...) printf(__VA_ARGS__) #define PRINT6ADDR(addr) PRINTF("[%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x]", ((uint8_t *)addr)[0], ((uint8_t *)addr)[1], ((uint8_t *)addr)[2], ((uint8_t *)addr)[3], ((uint8_t *)addr)[4], ((uint8_t *)addr)[5], ((uint8_t *)addr)[6], ((uint8_t *)addr)[7], ((uint8_t *)addr)[8], ((uint8_t *)addr)[9], ((uint8_t *)addr)[10], ((uint8_t *)addr)[11], ((uint8_t *)addr)[12], ((uint8_t *)addr)[13], ((uint8_t *)addr)[14], ((uint8_t *)addr)[15]) #define PRINTLLADDR(lladdr) PRINTF("[%02x:%02x:%02x:%02x:%02x:%02x]",(lladdr)->addr[0], (lladdr)->addr[1], (lladdr)->addr[2], (lladdr)->addr[3],(lladdr)->addr[4], (lladdr)->addr[5]) #else #define PRINTF(...) #define PRINT6ADDR(addr) #define PRINTLLADDR(addr) #endif /*-----------------------------------------------------------------------------------*/ /*- Variables -----------------------------------------------------------------------*/ /*-----------------------------------------------------------------------------------*/ static uint16_t current_mid = 0; coap_status_t coap_error_code = NO_ERROR; const char *coap_error_message = ""; /*-----------------------------------------------------------------------------------*/ /*- LOCAL HELP FUNCTIONS ------------------------------------------------------------*/ /*-----------------------------------------------------------------------------------*/ static uint16_t coap_log_2(uint16_t value) { uint16_t result = 0; do { value = value >> 1; result++; } while (value); return result ? result - 1 : result; } /*-----------------------------------------------------------------------------------*/ static uint32_t coap_parse_int_option(uint8_t *bytes, size_t length) { uint32_t var = 0; size_t i = 0; while (i < length) { var <<= 8; var |= bytes[i++]; } return var; } /*-----------------------------------------------------------------------------------*/ static uint8_t coap_option_nibble(unsigned int value) { if (value < 13) { return value; } else if (value <= 0xFF + 13) { return 13; } else { return 14; } } /*-----------------------------------------------------------------------------------*/ static size_t coap_set_option_header(unsigned int delta, size_t length, uint8_t *buffer) { size_t written = 0; unsigned int *x = δ buffer[0] = coap_option_nibble(delta) << 4 | coap_option_nibble(length); /* avoids code duplication without function overhead */ do { if (*x > 268) { buffer[++written] = (*x - 269) >> 8; buffer[++written] = (*x - 269); } else if (*x > 12) { buffer[++written] = (*x - 13); } } while (x != (unsigned int *)&length && NULL != (x = (unsigned int *)&length)); PRINTF("WRITTEN %u B opt header\n", written); return ++written; } /*-----------------------------------------------------------------------------------*/ static size_t coap_serialize_int_option(unsigned int number, unsigned int current_number, uint8_t *buffer, uint32_t value) { size_t i = 0; if (0xFF000000 & value) ++i; if (0xFFFF0000 & value) ++i; if (0xFFFFFF00 & value) ++i; if (0xFFFFFFFF & value) ++i; PRINTF("OPTION %u (delta %u, len %u)\n", number, number - current_number, i); i = coap_set_option_header(number - current_number, i, buffer); if (0xFF000000 & value) buffer[i++] = (uint8_t) (value >> 24); if (0xFFFF0000 & value) buffer[i++] = (uint8_t) (value >> 16); if (0xFFFFFF00 & value) buffer[i++] = (uint8_t) (value >> 8); if (0xFFFFFFFF & value) buffer[i++] = (uint8_t) (value); return i; } /*-----------------------------------------------------------------------------------*/ static size_t coap_serialize_array_option(unsigned int number, unsigned int current_number, uint8_t *buffer, uint8_t *array, size_t length, char split_char) { size_t i = 0; if (split_char != '\0') { size_t j; uint8_t *part_start = array; uint8_t *part_end = NULL; size_t temp_length; for (j = 0; j <= length; ++j) { if (array[j] == split_char || j == length) { part_end = array + j; temp_length = part_end - part_start; i += coap_set_option_header(number - current_number, temp_length, &buffer[i]); memcpy(&buffer[i], part_start, temp_length); i += temp_length; PRINTF("OPTION type %u, delta %u, len %u, part [%.*s]\n", number, number - current_number, i, temp_length, part_start); ++j; /* skip the splitter */ current_number = number; part_start = array + j; } } /* for */ } else { i += coap_set_option_header(number - current_number, length, &buffer[i]); memcpy(&buffer[i], array, length); i += length; PRINTF("OPTION type %u, delta %u, len %u\n", number, number - current_number, length); } return i; } /*-----------------------------------------------------------------------------------*/ static size_t coap_serialize_multi_option(unsigned int number, unsigned int current_number, uint8_t *buffer, multi_option_t *array) { size_t i = 0; multi_option_t *j; for (j = array; j != NULL; j = j->next) { i += coap_set_option_header(number - current_number, j->len, &buffer[i]); current_number = number; memcpy(&buffer[i], j->data, j->len); i += j->len; } /* for */ return i; } /*-----------------------------------------------------------------------------------*/ static void coap_merge_multi_option(uint8_t **dst, size_t *dst_len, uint8_t *option, size_t option_len, char separator) { /* Merge multiple options. */ if (*dst_len > 0) { /* dst already contains an option: concatenate */ (*dst)[*dst_len] = separator; *dst_len += 1; /* memmove handles 2-byte option headers */ memmove((*dst) + (*dst_len), option, option_len); *dst_len += option_len; } else { /* dst is empty: set to option */ *dst = option; *dst_len = option_len; } } void coap_add_multi_option(multi_option_t **dst, uint8_t *option, size_t option_len, uint8_t is_static) { multi_option_t *opt = (multi_option_t *)lwm2m_malloc(sizeof(multi_option_t)); if (opt) { opt->next = NULL; opt->len = (uint8_t)option_len; if (is_static) { opt->data = option; opt->is_static = 1; } else { opt->is_static = 0; opt->data = (uint8_t *)lwm2m_malloc(option_len); if (opt->data == NULL) { lwm2m_free(opt); return; } memcpy(opt->data, option, option_len); } if (*dst) { multi_option_t *i = *dst; while (i->next) { i = i->next; } i->next = opt; } else { *dst = opt; } } } void free_multi_option(multi_option_t *dst) { if (dst) { multi_option_t *n = dst->next; dst->next = NULL; if (dst->is_static == 0) { lwm2m_free(dst->data); } lwm2m_free(dst); free_multi_option(n); } } char *coap_get_multi_option_as_string(multi_option_t *option) { size_t len = 0; multi_option_t *opt; char *output; for (opt = option; opt != NULL; opt = opt->next) { len += opt->len + 1; // for separator } output = lwm2m_malloc(len + 1); // for String terminator if (output != NULL) { size_t i = 0; for (opt = option; opt != NULL; opt = opt->next) { output[i] = '/'; i += 1; memmove(output + i, opt->data, opt->len); i += opt->len; } output[i] = 0; } return output; } /*-----------------------------------------------------------------------------------*/ static int coap_get_variable(const uint8_t *buffer, size_t length, const char *name, const char **output) { const uint8_t *start = NULL; const uint8_t *end = NULL; const uint8_t *value_end = NULL; size_t name_len = 0; /*initialize the output buffer first*/ *output = 0; name_len = strlen(name); end = buffer + length; for (start = buffer; start + name_len < end; ++start) { if ((start == buffer || start[-1] == '&') && start[name_len] == '=' && strncmp(name, (char *)start, name_len) == 0) { /* Point start to variable value */ start += name_len + 1; /* Point end to the end of the value */ value_end = (const uint8_t *) memchr(start, '&', end - start); if (value_end == NULL) { value_end = end; } *output = (char *)start; return (value_end - start); } } return 0; } /*-----------------------------------------------------------------------------------*/ uint16_t coap_get_mid() { return ++current_mid; } /*-----------------------------------------------------------------------------------*/ /*- MEASSAGE PROCESSING -------------------------------------------------------------*/ /*-----------------------------------------------------------------------------------*/ void coap_init_message(void *packet, coap_message_type_t type, uint8_t code, uint16_t mid) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; /* Important thing */ memset(coap_pkt, 0, sizeof(coap_packet_t)); coap_pkt->type = type; coap_pkt->code = code; coap_pkt->mid = mid; } void coap_free_header(void *packet) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; free_multi_option(coap_pkt->uri_path); free_multi_option(coap_pkt->uri_query); free_multi_option(coap_pkt->location_path); coap_pkt->uri_path = NULL; coap_pkt->uri_query = NULL; coap_pkt->location_path = NULL; } /*-----------------------------------------------------------------------------------*/ size_t coap_serialize_get_size(void *packet) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; size_t length = 0; length = COAP_HEADER_LEN + coap_pkt->payload_len + coap_pkt->token_len; if (IS_OPTION(coap_pkt, COAP_OPTION_IF_MATCH)) { length += COAP_MAX_OPTION_HEADER_LEN + coap_pkt->if_match_len; } if (IS_OPTION(coap_pkt, COAP_OPTION_URI_HOST)) { length += COAP_MAX_OPTION_HEADER_LEN + coap_pkt->uri_host_len; } if (IS_OPTION(coap_pkt, COAP_OPTION_ETAG)) { length += COAP_MAX_OPTION_HEADER_LEN + coap_pkt->etag_len; } if (IS_OPTION(coap_pkt, COAP_OPTION_IF_NONE_MATCH)) { // can be stored in extended fields length += COAP_MAX_OPTION_HEADER_LEN; } if (IS_OPTION(coap_pkt, COAP_OPTION_OBSERVE)) { // can be stored in extended fields length += COAP_MAX_OPTION_HEADER_LEN; } if (IS_OPTION(coap_pkt, COAP_OPTION_URI_PORT)) { // can be stored in extended fields length += COAP_MAX_OPTION_HEADER_LEN; } if (IS_OPTION(coap_pkt, COAP_OPTION_LOCATION_PATH)) { multi_option_t *optP; for (optP = coap_pkt->location_path ; optP != NULL ; optP = optP->next) { length += COAP_MAX_OPTION_HEADER_LEN + optP->len; } } if (IS_OPTION(coap_pkt, COAP_OPTION_URI_PATH)) { multi_option_t *optP; for (optP = coap_pkt->uri_path ; optP != NULL ; optP = optP->next) { length += COAP_MAX_OPTION_HEADER_LEN + optP->len; } } if (IS_OPTION(coap_pkt, COAP_OPTION_CONTENT_TYPE)) { // can be stored in extended fields length += COAP_MAX_OPTION_HEADER_LEN; } if (IS_OPTION(coap_pkt, COAP_OPTION_MAX_AGE)) { // can be stored in extended fields length += COAP_MAX_OPTION_HEADER_LEN; } if (IS_OPTION(coap_pkt, COAP_OPTION_URI_QUERY)) { multi_option_t *optP; for (optP = coap_pkt->uri_query ; optP != NULL ; optP = optP->next) { length += COAP_MAX_OPTION_HEADER_LEN + optP->len; } } if (IS_OPTION(coap_pkt, COAP_OPTION_ACCEPT)) { length += coap_pkt->accept_num * COAP_MAX_OPTION_HEADER_LEN; } if (IS_OPTION(coap_pkt, COAP_OPTION_LOCATION_QUERY)) { length += COAP_MAX_OPTION_HEADER_LEN + coap_pkt->location_query_len; } if (IS_OPTION(coap_pkt, COAP_OPTION_BLOCK2)) { // can be stored in extended fields length += COAP_MAX_OPTION_HEADER_LEN; } if (IS_OPTION(coap_pkt, COAP_OPTION_BLOCK1)) { // can be stored in extended fields length += COAP_MAX_OPTION_HEADER_LEN; } if (IS_OPTION(coap_pkt, COAP_OPTION_SIZE)) { // can be stored in extended fields length += COAP_MAX_OPTION_HEADER_LEN; } if (IS_OPTION(coap_pkt, COAP_OPTION_PROXY_URI)) { length += COAP_MAX_OPTION_HEADER_LEN + coap_pkt->proxy_uri_len; } if (coap_pkt->payload_len) { // Account for the payload marker. length += 1; } return length; } /*-----------------------------------------------------------------------------------*/ size_t coap_serialize_message(void *packet, uint8_t *buffer) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; uint8_t *option; unsigned int current_number = 0; /* Initialize */ coap_pkt->buffer = buffer; coap_pkt->version = 1; PRINTF("-Serializing MID %u to %p, ", coap_pkt->mid, coap_pkt->buffer); /* set header fields */ coap_pkt->buffer[0] = 0x00; coap_pkt->buffer[0] |= COAP_HEADER_VERSION_MASK & (coap_pkt->version) << COAP_HEADER_VERSION_POSITION; coap_pkt->buffer[0] |= COAP_HEADER_TYPE_MASK & (coap_pkt->type) << COAP_HEADER_TYPE_POSITION; coap_pkt->buffer[0] |= COAP_HEADER_TOKEN_LEN_MASK & (coap_pkt->token_len) << COAP_HEADER_TOKEN_LEN_POSITION; coap_pkt->buffer[1] = coap_pkt->code; coap_pkt->buffer[2] = (uint8_t) ((coap_pkt->mid) >> 8); coap_pkt->buffer[3] = (uint8_t) (coap_pkt->mid); /* set Token */ PRINTF("Token (len %u)", coap_pkt->token_len); option = coap_pkt->buffer + COAP_HEADER_LEN; for (current_number = 0; current_number < coap_pkt->token_len; ++current_number) { PRINTF(" %02X", coap_pkt->token[current_number]); *option = coap_pkt->token[current_number]; ++option; } PRINTF("-\n"); /* Serialize options */ current_number = 0; PRINTF("-Serializing options at %p-\n", option); /* The options must be serialized in the order of their number */ COAP_SERIALIZE_BYTE_OPTION( COAP_OPTION_IF_MATCH, if_match, "If-Match") COAP_SERIALIZE_STRING_OPTION( COAP_OPTION_URI_HOST, uri_host, '\0', "Uri-Host") COAP_SERIALIZE_BYTE_OPTION( COAP_OPTION_ETAG, etag, "ETag") COAP_SERIALIZE_INT_OPTION( COAP_OPTION_IF_NONE_MATCH, content_type - coap_pkt->content_type, "If-None-Match") /* hack to get a zero field */ COAP_SERIALIZE_INT_OPTION( COAP_OPTION_OBSERVE, observe, "Observe") COAP_SERIALIZE_INT_OPTION( COAP_OPTION_URI_PORT, uri_port, "Uri-Port") COAP_SERIALIZE_MULTI_OPTION( COAP_OPTION_LOCATION_PATH, location_path, "Location-Path") COAP_SERIALIZE_MULTI_OPTION( COAP_OPTION_URI_PATH, uri_path, "Uri-Path") COAP_SERIALIZE_INT_OPTION( COAP_OPTION_CONTENT_TYPE, content_type, "Content-Format") COAP_SERIALIZE_INT_OPTION( COAP_OPTION_MAX_AGE, max_age, "Max-Age") COAP_SERIALIZE_MULTI_OPTION( COAP_OPTION_URI_QUERY, uri_query, "Uri-Query") COAP_SERIALIZE_ACCEPT_OPTION( COAP_OPTION_ACCEPT, accept, "Accept") COAP_SERIALIZE_STRING_OPTION( COAP_OPTION_LOCATION_QUERY, location_query, '&', "Location-Query") COAP_SERIALIZE_BLOCK_OPTION( COAP_OPTION_BLOCK2, block2, "Block2") COAP_SERIALIZE_BLOCK_OPTION( COAP_OPTION_BLOCK1, block1, "Block1") COAP_SERIALIZE_INT_OPTION( COAP_OPTION_SIZE, size, "Size") COAP_SERIALIZE_STRING_OPTION( COAP_OPTION_PROXY_URI, proxy_uri, '\0', "Proxy-Uri") PRINTF("-Done serializing at %p----\n", option); /* Free allocated header fields */ coap_free_header(packet); /* Pack payload */ /* Payload marker */ if (coap_pkt->payload_len) { *option = 0xFF; ++option; } memmove(option, coap_pkt->payload, coap_pkt->payload_len); PRINTF("-Done %u B (header len %u, payload len %u)-\n", coap_pkt->payload_len + option - buffer, option - buffer, coap_pkt->payload_len); PRINTF("Dump [0x%02X %02X %02X %02X %02X %02X %02X %02X]\n", coap_pkt->buffer[0], coap_pkt->buffer[1], coap_pkt->buffer[2], coap_pkt->buffer[3], coap_pkt->buffer[4], coap_pkt->buffer[5], coap_pkt->buffer[6], coap_pkt->buffer[7] ); return (option - buffer) + coap_pkt->payload_len; /* packet length */ } /*-----------------------------------------------------------------------------------*/ coap_status_t coap_parse_message(void *packet, uint8_t *data, uint16_t data_len) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; uint8_t *current_option; unsigned int option_number = 0; unsigned int option_delta = 0; size_t option_length = 0; unsigned int *x; /* Initialize packet */ memset(coap_pkt, 0, sizeof(coap_packet_t)); /* pointer to packet bytes */ coap_pkt->buffer = data; /* parse header fields */ coap_pkt->version = (COAP_HEADER_VERSION_MASK & coap_pkt->buffer[0]) >> COAP_HEADER_VERSION_POSITION; coap_pkt->type = (coap_message_type_t)((COAP_HEADER_TYPE_MASK & coap_pkt->buffer[0]) >> COAP_HEADER_TYPE_POSITION); coap_pkt->token_len = MIN(COAP_TOKEN_LEN, (COAP_HEADER_TOKEN_LEN_MASK & coap_pkt->buffer[0]) >> COAP_HEADER_TOKEN_LEN_POSITION); coap_pkt->code = coap_pkt->buffer[1]; coap_pkt->mid = coap_pkt->buffer[2] << 8 | coap_pkt->buffer[3]; if (coap_pkt->version != 1) { coap_error_message = "CoAP version must be 1"; return BAD_REQUEST_4_00; } current_option = data + COAP_HEADER_LEN; if (coap_pkt->token_len != 0) { memcpy(coap_pkt->token, current_option, coap_pkt->token_len); SET_OPTION(coap_pkt, COAP_OPTION_TOKEN); PRINTF("Token (len %u) [0x%02X%02X%02X%02X%02X%02X%02X%02X]\n", coap_pkt->token_len, coap_pkt->token[0], coap_pkt->token[1], coap_pkt->token[2], coap_pkt->token[3], coap_pkt->token[4], coap_pkt->token[5], coap_pkt->token[6], coap_pkt->token[7] ); /*FIXME always prints 8 bytes */ } /* parse options */ current_option += coap_pkt->token_len; while (current_option < data + data_len) { /* Payload marker 0xFF, currently only checking for 0xF* because rest is reserved */ if ((current_option[0] & 0xF0) == 0xF0) { coap_pkt->payload = ++current_option; coap_pkt->payload_len = data_len - (coap_pkt->payload - data); break; } option_delta = current_option[0] >> 4; option_length = current_option[0] & 0x0F; ++current_option; /* avoids code duplication without function overhead */ x = &option_delta; do { if (*x == 13) { *x += current_option[0]; ++current_option; } else if (*x == 14) { *x += 255; *x += current_option[0] << 8; ++current_option; *x += current_option[0]; ++current_option; } } while (x != (unsigned int *)&option_length && NULL != (x = (unsigned int *)&option_length)); option_number += option_delta; if (current_option + option_length > data + data_len) { PRINTF("OPTION %u (delta %u, len %u) has invalid length.\n", option_number, option_delta, option_length); return BAD_REQUEST_4_00; } else { PRINTF("OPTION %u (delta %u, len %u): ", option_number, option_delta, option_length); } SET_OPTION(coap_pkt, option_number); switch (option_number) { case COAP_OPTION_CONTENT_TYPE: coap_pkt->content_type = (coap_content_type_t)coap_parse_int_option(current_option, option_length); PRINTF("Content-Format [%u]\n", coap_pkt->content_type); break; case COAP_OPTION_MAX_AGE: coap_pkt->max_age = coap_parse_int_option(current_option, option_length); PRINTF("Max-Age [%lu]\n", coap_pkt->max_age); break; case COAP_OPTION_ETAG: coap_pkt->etag_len = (uint8_t)(MIN(COAP_ETAG_LEN, option_length)); memcpy(coap_pkt->etag, current_option, coap_pkt->etag_len); PRINTF("ETag %u [0x%02X%02X%02X%02X%02X%02X%02X%02X]\n", coap_pkt->etag_len, coap_pkt->etag[0], coap_pkt->etag[1], coap_pkt->etag[2], coap_pkt->etag[3], coap_pkt->etag[4], coap_pkt->etag[5], coap_pkt->etag[6], coap_pkt->etag[7] ); /*FIXME always prints 8 bytes */ break; case COAP_OPTION_ACCEPT: if (coap_pkt->accept_num < COAP_MAX_ACCEPT_NUM) { coap_pkt->accept[coap_pkt->accept_num] = coap_parse_int_option(current_option, option_length); coap_pkt->accept_num += 1; PRINTF("Accept [%u]\n", coap_pkt->content_type); } break; case COAP_OPTION_IF_MATCH: /*FIXME support multiple ETags */ coap_pkt->if_match_len = (uint8_t)(MIN(COAP_ETAG_LEN, option_length)); memcpy(coap_pkt->if_match, current_option, coap_pkt->if_match_len); PRINTF("If-Match %u [0x%02X%02X%02X%02X%02X%02X%02X%02X]\n", coap_pkt->if_match_len, coap_pkt->if_match[0], coap_pkt->if_match[1], coap_pkt->if_match[2], coap_pkt->if_match[3], coap_pkt->if_match[4], coap_pkt->if_match[5], coap_pkt->if_match[6], coap_pkt->if_match[7] ); /*FIXME always prints 8 bytes */ break; case COAP_OPTION_IF_NONE_MATCH: coap_pkt->if_none_match = 1; PRINTF("If-None-Match\n"); break; case COAP_OPTION_URI_HOST: coap_pkt->uri_host = current_option; coap_pkt->uri_host_len = option_length; PRINTF("Uri-Host [%.*s]\n", coap_pkt->uri_host_len, coap_pkt->uri_host); break; case COAP_OPTION_URI_PORT: coap_pkt->uri_port = coap_parse_int_option(current_option, option_length); PRINTF("Uri-Port [%u]\n", coap_pkt->uri_port); break; case COAP_OPTION_URI_PATH: /* coap_merge_multi_option() operates in-place on the IPBUF, but final packet field should be const string -> cast to string */ // coap_merge_multi_option( (char **) &(coap_pkt->uri_path), &(coap_pkt->uri_path_len), current_option, option_length, 0); coap_add_multi_option( &(coap_pkt->uri_path), current_option, option_length, 1); PRINTF("Uri-Path [%.*s]\n", option_length, current_option); break; case COAP_OPTION_URI_QUERY: /* coap_merge_multi_option() operates in-place on the IPBUF, but final packet field should be const string -> cast to string */ // coap_merge_multi_option( (char **) &(coap_pkt->uri_query), &(coap_pkt->uri_query_len), current_option, option_length, '&'); coap_add_multi_option( &(coap_pkt->uri_query), current_option, option_length, 1); PRINTF("Uri-Query [%.*s]\n", option_length, current_option); break; case COAP_OPTION_LOCATION_PATH: coap_add_multi_option( &(coap_pkt->location_path), current_option, option_length, 1); break; case COAP_OPTION_LOCATION_QUERY: /* coap_merge_multi_option() operates in-place on the IPBUF, but final packet field should be const string -> cast to string */ coap_merge_multi_option( &(coap_pkt->location_query), &(coap_pkt->location_query_len), current_option, option_length, '&'); PRINTF("Location-Query [%.*s]\n", option_length, current_option); break; case COAP_OPTION_PROXY_URI: /*FIXME check for own end-point */ coap_pkt->proxy_uri = current_option; coap_pkt->proxy_uri_len = option_length; /*TODO length > 270 not implemented (actually not required) */ PRINTF("Proxy-Uri NOT IMPLEMENTED [%.*s]\n", coap_pkt->proxy_uri_len, coap_pkt->proxy_uri); coap_error_message = "This is a constrained server (Contiki)"; return PROXYING_NOT_SUPPORTED_5_05; // break; case COAP_OPTION_OBSERVE: coap_pkt->observe = coap_parse_int_option(current_option, option_length); PRINTF("Observe [%lu]\n", coap_pkt->observe); break; case COAP_OPTION_BLOCK2: coap_pkt->block2_num = coap_parse_int_option(current_option, option_length); coap_pkt->block2_more = (coap_pkt->block2_num & 0x08) >> 3; coap_pkt->block2_size = 16 << (coap_pkt->block2_num & 0x07); coap_pkt->block2_offset = (coap_pkt->block2_num & ~0x0000000F) << (coap_pkt->block2_num & 0x07); coap_pkt->block2_num >>= 4; PRINTF("Block2 [%lu%s (%u B/blk)]\n", coap_pkt->block2_num, coap_pkt->block2_more ? "+" : "", coap_pkt->block2_size); break; case COAP_OPTION_BLOCK1: coap_pkt->block1_num = coap_parse_int_option(current_option, option_length); coap_pkt->block1_more = (coap_pkt->block1_num & 0x08) >> 3; coap_pkt->block1_size = 16 << (coap_pkt->block1_num & 0x07); coap_pkt->block1_offset = (coap_pkt->block1_num & ~0x0000000F) << (coap_pkt->block1_num & 0x07); coap_pkt->block1_num >>= 4; PRINTF("Block1 [%lu%s (%u B/blk)]\n", coap_pkt->block1_num, coap_pkt->block1_more ? "+" : "", coap_pkt->block1_size); break; case COAP_OPTION_SIZE: coap_pkt->size = coap_parse_int_option(current_option, option_length); PRINTF("Size [%lu]\n", coap_pkt->size); break; default: PRINTF("unknown (%u)\n", option_number); /* Check if critical (odd) */ if (option_number & 1) { coap_error_message = "Unsupported critical option"; return BAD_OPTION_4_02; } } current_option += option_length; } /* for */ PRINTF("-Done parsing-------\n"); return NO_ERROR; } /*-----------------------------------------------------------------------------------*/ /*- REST FRAMEWORK FUNCTIONS --------------------------------------------------------*/ /*-----------------------------------------------------------------------------------*/ int coap_get_query_variable(void *packet, const char *name, const char **output) { /* coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (IS_OPTION(coap_pkt, COAP_OPTION_URI_QUERY)) { return coap_get_variable(coap_pkt->uri_query, coap_pkt->uri_query_len, name, output); } */ return 0; } int coap_get_post_variable(void *packet, const char *name, const char **output) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (coap_pkt->payload_len) { return coap_get_variable(coap_pkt->payload, coap_pkt->payload_len, name, output); } return 0; } /*-----------------------------------------------------------------------------------*/ int coap_set_status_code(void *packet, unsigned int code) { if (code <= 0xFF) { ((coap_packet_t *)packet)->code = (uint8_t) code; return 1; } else { return 0; } } /*-----------------------------------------------------------------------------------*/ /*- HEADER OPTION GETTERS AND SETTERS -----------------------------------------------*/ /*-----------------------------------------------------------------------------------*/ unsigned int coap_get_header_content_type(void *packet) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_CONTENT_TYPE)) return (unsigned int) - 1; return coap_pkt->content_type; } int coap_set_header_content_type(void *packet, unsigned int content_type) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; coap_pkt->content_type = (coap_content_type_t) content_type; SET_OPTION(coap_pkt, COAP_OPTION_CONTENT_TYPE); return 1; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_accept(void *packet, const uint16_t **accept) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_ACCEPT)) return 0; *accept = coap_pkt->accept; return coap_pkt->accept_num; } int coap_set_header_accept(void *packet, uint16_t accept) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (coap_pkt->accept_num < COAP_MAX_ACCEPT_NUM) { coap_pkt->accept[coap_pkt->accept_num] = accept; coap_pkt->accept_num += 1; SET_OPTION(coap_pkt, COAP_OPTION_ACCEPT); } return coap_pkt->accept_num; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_max_age(void *packet, uint32_t *age) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_MAX_AGE)) { *age = COAP_DEFAULT_MAX_AGE; } else { *age = coap_pkt->max_age; } return 1; } int coap_set_header_max_age(void *packet, uint32_t age) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; coap_pkt->max_age = age; SET_OPTION(coap_pkt, COAP_OPTION_MAX_AGE); return 1; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_etag(void *packet, const uint8_t **etag) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_ETAG)) return 0; *etag = coap_pkt->etag; return coap_pkt->etag_len; } int coap_set_header_etag(void *packet, const uint8_t *etag, size_t etag_len) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; coap_pkt->etag_len = (uint8_t)(MIN(COAP_ETAG_LEN, etag_len)); memcpy(coap_pkt->etag, etag, coap_pkt->etag_len); SET_OPTION(coap_pkt, COAP_OPTION_ETAG); return coap_pkt->etag_len; } /*-----------------------------------------------------------------------------------*/ /*FIXME support multiple ETags */ int coap_get_header_if_match(void *packet, const uint8_t **etag) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_IF_MATCH)) return 0; *etag = coap_pkt->if_match; return coap_pkt->if_match_len; } int coap_set_header_if_match(void *packet, const uint8_t *etag, size_t etag_len) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; coap_pkt->if_match_len = (uint8_t)(MIN(COAP_ETAG_LEN, etag_len)); memcpy(coap_pkt->if_match, etag, coap_pkt->if_match_len); SET_OPTION(coap_pkt, COAP_OPTION_IF_MATCH); return coap_pkt->if_match_len; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_if_none_match(void *packet) { return IS_OPTION((coap_packet_t *)packet, COAP_OPTION_IF_NONE_MATCH) ? 1 : 0; } int coap_set_header_if_none_match(void *packet) { SET_OPTION((coap_packet_t *)packet, COAP_OPTION_IF_NONE_MATCH); return 1; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_token(void *packet, const uint8_t **token) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_TOKEN)) return 0; *token = coap_pkt->token; return coap_pkt->token_len; } int coap_set_header_token(void *packet, const uint8_t *token, size_t token_len) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; coap_pkt->token_len = (uint8_t)(MIN(COAP_TOKEN_LEN, token_len)); memcpy(coap_pkt->token, token, coap_pkt->token_len); SET_OPTION(coap_pkt, COAP_OPTION_TOKEN); return coap_pkt->token_len; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_proxy_uri(void *packet, const char **uri) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_PROXY_URI)) return 0; *uri = (const char *)coap_pkt->proxy_uri; return coap_pkt->proxy_uri_len; } int coap_set_header_proxy_uri(void *packet, const char *uri) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; coap_pkt->proxy_uri = (uint8_t *)uri; coap_pkt->proxy_uri_len = strlen(uri); SET_OPTION(coap_pkt, COAP_OPTION_PROXY_URI); return coap_pkt->proxy_uri_len; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_uri_host(void *packet, const char **host) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_URI_HOST)) return 0; *host = (char *)coap_pkt->uri_host; return coap_pkt->uri_host_len; } int coap_set_header_uri_host(void *packet, const char *host) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; coap_pkt->uri_host = (uint8_t *)host; coap_pkt->uri_host_len = strlen(host); SET_OPTION(coap_pkt, COAP_OPTION_URI_HOST); return coap_pkt->uri_host_len; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_uri_path(void *packet, const char **path) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_URI_PATH)) return 0; *path = NULL; //coap_pkt->uri_path; return 0; //coap_pkt->uri_path_len; } int coap_set_header_uri_path(void *packet, const char *path) { coap_packet_t *coap_pkt = (coap_packet_t *) packet; int length = 0; free_multi_option(coap_pkt->uri_path); coap_pkt->uri_path = NULL; if (path[0] == '/') ++path; do { int i = 0; while (path[i] != 0 && path[i] != '/') i++; coap_add_multi_option(&(coap_pkt->uri_path), (uint8_t *)path, i, 0); if (path[i] == '/') i++; path += i; length += i; } while (path[0] != 0); SET_OPTION(coap_pkt, COAP_OPTION_URI_PATH); return length; } int coap_set_header_uri_path_segment(void *packet, const char *segment) { coap_packet_t *coap_pkt = (coap_packet_t *) packet; int length; if (segment == NULL || segment[0] == 0) { coap_add_multi_option(&(coap_pkt->uri_path), NULL, 0, 1); length = 0; } else { length = strlen(segment); coap_add_multi_option(&(coap_pkt->uri_path), (uint8_t *)segment, length, 0); } SET_OPTION(coap_pkt, COAP_OPTION_URI_PATH); return length; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_uri_query(void *packet, const char **query) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_URI_QUERY)) return 0; *query = NULL; //coap_pkt->uri_query; return 0; //coap_pkt->uri_query_len; } int coap_set_header_uri_query(void *packet, const char *query) { int length = 0; coap_packet_t *const coap_pkt = (coap_packet_t *) packet; free_multi_option(coap_pkt->uri_query); coap_pkt->uri_query = NULL; if (query[0] == '?') ++query; do { int i = 0; while (query[i] != 0 && query[i] != '&') i++; coap_add_multi_option(&(coap_pkt->uri_query), (uint8_t *)query, i, 0); if (query[i] == '&') i++; query += i; length += i; } while (query[0] != 0); SET_OPTION(coap_pkt, COAP_OPTION_URI_QUERY); return length; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_location_path(void *packet, const char **path) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_LOCATION_PATH)) return 0; *path = NULL; //coap_pkt->location_path; return 0; //coap_pkt->location_path_len; } int coap_set_header_location_path(void *packet, const char *path) { coap_packet_t *coap_pkt = (coap_packet_t *) packet; int length = 0; free_multi_option(coap_pkt->location_path); coap_pkt->location_path = NULL; if (path[0] == '/') ++path; do { int i = 0; while (path[i] != 0 && path[i] != '/') i++; coap_add_multi_option(&(coap_pkt->location_path), (uint8_t *)path, i, 0); if (path[i] == '/') i++; path += i; length += i; } while (path[0] != 0); SET_OPTION(coap_pkt, COAP_OPTION_LOCATION_PATH); return length; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_location_query(void *packet, const char **query) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_LOCATION_QUERY)) return 0; *query = (const char *)coap_pkt->location_query; return coap_pkt->location_query_len; } int coap_set_header_location_query(void *packet, char *query) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; while (query[0] == '?') ++query; coap_pkt->location_query = (uint8_t *)query; coap_pkt->location_query_len = strlen(query); SET_OPTION(coap_pkt, COAP_OPTION_LOCATION_QUERY); return coap_pkt->location_query_len; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_observe(void *packet, uint32_t *observe) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_OBSERVE)) return 0; *observe = coap_pkt->observe; return 1; } int coap_set_header_observe(void *packet, uint32_t observe) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; coap_pkt->observe = 0x00FFFFFF & observe; SET_OPTION(coap_pkt, COAP_OPTION_OBSERVE); return 1; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_block2(void *packet, uint32_t *num, uint8_t *more, uint16_t *size, uint32_t *offset) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_BLOCK2)) return 0; /* pointers may be NULL to get only specific block parameters */ if (num != NULL) *num = coap_pkt->block2_num; if (more != NULL) *more = coap_pkt->block2_more; if (size != NULL) *size = coap_pkt->block2_size; if (offset != NULL) *offset = coap_pkt->block2_offset; return 1; } int coap_set_header_block2(void *packet, uint32_t num, uint8_t more, uint16_t size) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (size < 16) return 0; if (size > 2048) return 0; if (num > 0x0FFFFF) return 0; coap_pkt->block2_num = num; coap_pkt->block2_more = more ? 1 : 0; coap_pkt->block2_size = size; SET_OPTION(coap_pkt, COAP_OPTION_BLOCK2); return 1; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_block1(void *packet, uint32_t *num, uint8_t *more, uint16_t *size, uint32_t *offset) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_BLOCK1)) return 0; /* pointers may be NULL to get only specific block parameters */ if (num != NULL) *num = coap_pkt->block1_num; if (more != NULL) *more = coap_pkt->block1_more; if (size != NULL) *size = coap_pkt->block1_size; if (offset != NULL) *offset = coap_pkt->block1_offset; return 1; } int coap_set_header_block1(void *packet, uint32_t num, uint8_t more, uint16_t size) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (size < 16) return 0; if (size > 2048) return 0; if (num > 0x0FFFFF) return 0; coap_pkt->block1_num = num; coap_pkt->block1_more = more; coap_pkt->block1_size = size; SET_OPTION(coap_pkt, COAP_OPTION_BLOCK1); return 1; } /*-----------------------------------------------------------------------------------*/ int coap_get_header_size(void *packet, uint32_t *size) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (!IS_OPTION(coap_pkt, COAP_OPTION_SIZE)) return 0; *size = coap_pkt->size; return 1; } int coap_set_header_size(void *packet, uint32_t size) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; coap_pkt->size = size; SET_OPTION(coap_pkt, COAP_OPTION_SIZE); return 1; } /*-----------------------------------------------------------------------------------*/ /*- PAYLOAD -------------------------------------------------------------------------*/ /*-----------------------------------------------------------------------------------*/ int coap_get_payload(void *packet, const uint8_t **payload) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; if (coap_pkt->payload) { *payload = coap_pkt->payload; return coap_pkt->payload_len; } else { *payload = NULL; return 0; } } int coap_set_payload(void *packet, const void *payload, size_t length) { coap_packet_t *const coap_pkt = (coap_packet_t *) packet; coap_pkt->payload = (uint8_t *) payload; coap_pkt->payload_len = (uint16_t)(length); return coap_pkt->payload_len; } /*-----------------------------------------------------------------------------------*/ ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/er-coap-13/er-coap-13.h ================================================ /* * Copyright (c) 2013, Institute for Pervasive Computing, ETH Zurich * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the Institute nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * This file is part of the Contiki operating system. */ /** * \file * An implementation of the Constrained Application Protocol (draft 12) * \author * Matthias Kovatsch * \contributors * David Navarro, Intel Corporation - Adapt to usage in liblwm2m */ #ifndef COAP_13_H_ #define COAP_13_H_ #include #include /* for size_t */ /* * The maximum buffer size that is provided for resource responses and must be respected due to the limited IP buffer. * Larger data must be handled by the resource and will be sent chunk-wise through a TCP stream or CoAP blocks. */ #ifndef REST_MAX_CHUNK_SIZE #define REST_MAX_CHUNK_SIZE 128 #endif #define COAP_DEFAULT_MAX_AGE 60 #define COAP_RESPONSE_TIMEOUT 4 #define COAP_MAX_RETRANSMIT 4 #define COAP_ACK_RANDOM_FACTOR 1.5 #define COAP_MAX_LATENCY 100 #define COAP_PROCESSING_DELAY COAP_RESPONSE_TIMEOUT #define COAP_MAX_TRANSMIT_WAIT ((COAP_RESPONSE_TIMEOUT * ( (1 << (COAP_MAX_RETRANSMIT + 1) ) - 1) * COAP_ACK_RANDOM_FACTOR)) #define COAP_MAX_TRANSMIT_SPAN ((COAP_RESPONSE_TIMEOUT * ( (1 << COAP_MAX_RETRANSMIT) - 1) * COAP_ACK_RANDOM_FACTOR)) #define COAP_EXCHANGE_LIFETIME (COAP_MAX_TRANSMIT_SPAN + (2 * COAP_MAX_LATENCY) + COAP_PROCESSING_DELAY) #define COAP_HEADER_LEN 4 /* | version:0x03 type:0x0C tkl:0xF0 | code | mid:0x00FF | mid:0xFF00 | */ #define COAP_ETAG_LEN 8 /* The maximum number of bytes for the ETag */ #define COAP_TOKEN_LEN 8 /* The maximum number of bytes for the Token */ #define COAP_MAX_ACCEPT_NUM 2 /* The maximum number of accept preferences to parse/store */ #define COAP_MAX_OPTION_HEADER_LEN 5 #define COAP_HEADER_VERSION_MASK 0xC0 #define COAP_HEADER_VERSION_POSITION 6 #define COAP_HEADER_TYPE_MASK 0x30 #define COAP_HEADER_TYPE_POSITION 4 #define COAP_HEADER_TOKEN_LEN_MASK 0x0F #define COAP_HEADER_TOKEN_LEN_POSITION 0 #define COAP_HEADER_OPTION_DELTA_MASK 0xF0 #define COAP_HEADER_OPTION_SHORT_LENGTH_MASK 0x0F /* * Conservative size limit, as not all options have to be set at the same time. */ #ifndef COAP_MAX_HEADER_SIZE /* Hdr CoT Age Tag Obs Tok Blo strings */ #define COAP_MAX_HEADER_SIZE (4 + 3 + 5 + 1+COAP_ETAG_LEN + 3 + 1+COAP_TOKEN_LEN + 4 + 30) /* 70 */ #endif /* COAP_MAX_HEADER_SIZE */ #define COAP_MAX_PACKET_SIZE (COAP_MAX_HEADER_SIZE + REST_MAX_CHUNK_SIZE) /* 0/14 48 for IPv6 (28 for IPv4) */ #if COAP_MAX_PACKET_SIZE > (UIP_BUFSIZE - UIP_LLH_LEN - UIP_IPUDPH_LEN) //#error "UIP_CONF_BUFFER_SIZE too small for REST_MAX_CHUNK_SIZE" #endif /* Bitmap for set options */ enum { OPTION_MAP_SIZE = sizeof(uint8_t) * 8 }; #define SET_OPTION(packet, opt) {if (opt <= sizeof((packet)->options) * OPTION_MAP_SIZE) {(packet)->options[opt / OPTION_MAP_SIZE] |= 1 << (opt % OPTION_MAP_SIZE);}} #define IS_OPTION(packet, opt) ((opt <= sizeof((packet)->options) * OPTION_MAP_SIZE)?(packet)->options[opt / OPTION_MAP_SIZE] & (1 << (opt % OPTION_MAP_SIZE)):0) #ifndef MIN #define MIN(a, b) ((a) < (b)? (a) : (b)) #endif /* MIN */ /* CoAP message types */ typedef enum { COAP_TYPE_CON, /* confirmables */ COAP_TYPE_NON, /* non-confirmables */ COAP_TYPE_ACK, /* acknowledgements */ COAP_TYPE_RST /* reset */ } coap_message_type_t; /* CoAP request method codes */ typedef enum { COAP_GET = 1, COAP_POST, COAP_PUT, COAP_DELETE } coap_method_t; /* CoAP response codes */ typedef enum { NO_ERROR = 0, CREATED_2_01 = 65, /* CREATED */ DELETED_2_02 = 66, /* DELETED */ VALID_2_03 = 67, /* NOT_MODIFIED */ CHANGED_2_04 = 68, /* CHANGED */ CONTENT_2_05 = 69, /* OK */ BAD_REQUEST_4_00 = 128, /* BAD_REQUEST */ UNAUTHORIZED_4_01 = 129, /* UNAUTHORIZED */ BAD_OPTION_4_02 = 130, /* BAD_OPTION */ FORBIDDEN_4_03 = 131, /* FORBIDDEN */ NOT_FOUND_4_04 = 132, /* NOT_FOUND */ METHOD_NOT_ALLOWED_4_05 = 133, /* METHOD_NOT_ALLOWED */ NOT_ACCEPTABLE_4_06 = 134, /* NOT_ACCEPTABLE */ PRECONDITION_FAILED_4_12 = 140, /* BAD_REQUEST */ REQUEST_ENTITY_TOO_LARGE_4_13 = 141, /* REQUEST_ENTITY_TOO_LARGE */ UNSUPPORTED_MEDIA_TYPE_4_15 = 143, /* UNSUPPORTED_MEDIA_TYPE */ INTERNAL_SERVER_ERROR_5_00 = 160, /* INTERNAL_SERVER_ERROR */ NOT_IMPLEMENTED_5_01 = 161, /* NOT_IMPLEMENTED */ BAD_GATEWAY_5_02 = 162, /* BAD_GATEWAY */ SERVICE_UNAVAILABLE_5_03 = 163, /* SERVICE_UNAVAILABLE */ GATEWAY_TIMEOUT_5_04 = 164, /* GATEWAY_TIMEOUT */ PROXYING_NOT_SUPPORTED_5_05 = 165, /* PROXYING_NOT_SUPPORTED */ /* Erbium errors */ MEMORY_ALLOCATION_ERROR = 192, PACKET_SERIALIZATION_ERROR, /* Erbium hooks */ MANUAL_RESPONSE } coap_status_t; /* CoAP header options */ typedef enum { COAP_OPTION_IF_MATCH = 1, /* 0-8 B */ COAP_OPTION_URI_HOST = 3, /* 1-255 B */ COAP_OPTION_ETAG = 4, /* 1-8 B */ COAP_OPTION_IF_NONE_MATCH = 5, /* 0 B */ COAP_OPTION_OBSERVE = 6, /* 0-3 B */ COAP_OPTION_URI_PORT = 7, /* 0-2 B */ COAP_OPTION_LOCATION_PATH = 8, /* 0-255 B */ COAP_OPTION_URI_PATH = 11, /* 0-255 B */ COAP_OPTION_CONTENT_TYPE = 12, /* 0-2 B */ COAP_OPTION_MAX_AGE = 14, /* 0-4 B */ COAP_OPTION_URI_QUERY = 15, /* 0-270 B */ COAP_OPTION_ACCEPT = 17, /* 0-2 B */ COAP_OPTION_TOKEN = 19, /* 1-8 B */ COAP_OPTION_LOCATION_QUERY = 20, /* 1-270 B */ COAP_OPTION_BLOCK2 = 23, /* 1-3 B */ COAP_OPTION_BLOCK1 = 27, /* 1-3 B */ COAP_OPTION_SIZE = 28, /* 0-4 B */ COAP_OPTION_PROXY_URI = 35, /* 1-270 B */ OPTION_MAX_VALUE = 0xFFFF } coap_option_t; /* CoAP Content-Types */ typedef enum { TEXT_PLAIN = 0, TEXT_XML = 1, /* Indented types are not in the initial registry. */ TEXT_CSV = 2, TEXT_HTML = 3, IMAGE_GIF = 21, IMAGE_JPEG = 22, IMAGE_PNG = 23, IMAGE_TIFF = 24, AUDIO_RAW = 25, VIDEO_RAW = 26, APPLICATION_LINK_FORMAT = 40, APPLICATION_XML = 41, APPLICATION_OCTET_STREAM = 42, APPLICATION_RDF_XML = 43, APPLICATION_SOAP_XML = 44, APPLICATION_ATOM_XML = 45, APPLICATION_XMPP_XML = 46, APPLICATION_EXI = 47, APPLICATION_FASTINFOSET = 48, APPLICATION_SOAP_FASTINFOSET = 49, APPLICATION_JSON = 50, APPLICATION_X_OBIX_BINARY = 51, CONTENT_MAX_VALUE = 0xFFFF } coap_content_type_t; typedef struct _multi_option_t { struct _multi_option_t* next; uint8_t is_static; uint8_t len; uint8_t* data; } multi_option_t; /* Parsed message struct */ typedef struct { uint8_t* buffer; /* pointer to CoAP header / incoming packet buffer / memory to serialize packet */ uint8_t version; coap_message_type_t type; uint8_t code; uint16_t mid; uint8_t options[COAP_OPTION_PROXY_URI / OPTION_MAP_SIZE + 1]; /* Bitmap to check if option is set */ coap_content_type_t content_type; /* Parse options once and store; allows setting options in random order */ uint32_t max_age; size_t proxy_uri_len; const uint8_t* proxy_uri; uint8_t etag_len; uint8_t etag[COAP_ETAG_LEN]; size_t uri_host_len; const uint8_t* uri_host; multi_option_t* location_path; uint16_t uri_port; size_t location_query_len; uint8_t* location_query; multi_option_t* uri_path; uint32_t observe; uint8_t token_len; uint8_t token[COAP_TOKEN_LEN]; uint8_t accept_num; uint16_t accept[COAP_MAX_ACCEPT_NUM]; uint8_t if_match_len; uint8_t if_match[COAP_ETAG_LEN]; uint32_t block2_num; uint8_t block2_more; uint16_t block2_size; uint32_t block2_offset; uint32_t block1_num; uint8_t block1_more; uint16_t block1_size; uint32_t block1_offset; uint32_t size; multi_option_t* uri_query; uint8_t if_none_match; uint16_t payload_len; uint8_t* payload; } coap_packet_t; /* Option format serialization*/ #define COAP_SERIALIZE_INT_OPTION(number, field, text) \ if (IS_OPTION(coap_pkt, number)) { \ PRINTF(text" [%u]\n", coap_pkt->field); \ option += coap_serialize_int_option(number, current_number, option, coap_pkt->field); \ current_number = number; \ } #define COAP_SERIALIZE_BYTE_OPTION(number, field, text) \ if (IS_OPTION(coap_pkt, number)) { \ PRINTF(text" %u [0x%02X%02X%02X%02X%02X%02X%02X%02X]\n", coap_pkt->field##_len, \ coap_pkt->field[0], \ coap_pkt->field[1], \ coap_pkt->field[2], \ coap_pkt->field[3], \ coap_pkt->field[4], \ coap_pkt->field[5], \ coap_pkt->field[6], \ coap_pkt->field[7] \ ); /*FIXME always prints 8 bytes */ \ option += coap_serialize_array_option(number, current_number, option, coap_pkt->field, coap_pkt->field##_len, '\0'); \ current_number = number; \ } #define COAP_SERIALIZE_STRING_OPTION(number, field, splitter, text) \ if (IS_OPTION(coap_pkt, number)) { \ PRINTF(text" [%.*s]\n", coap_pkt->field##_len, coap_pkt->field); \ option += coap_serialize_array_option(number, current_number, option, (uint8_t *) coap_pkt->field, coap_pkt->field##_len, splitter); \ current_number = number; \ } #define COAP_SERIALIZE_MULTI_OPTION(number, field, text) \ if (IS_OPTION(coap_pkt, number)) { \ PRINTF(text); \ option += coap_serialize_multi_option(number, current_number, option, coap_pkt->field); \ current_number = number; \ } #define COAP_SERIALIZE_ACCEPT_OPTION(number, field, text) \ if (IS_OPTION(coap_pkt, number)) { \ int i; \ for (i=0; ifield##_num; ++i) \ { \ PRINTF(text" [%u]\n", coap_pkt->field[i]); \ option += coap_serialize_int_option(number, current_number, option, coap_pkt->field[i]); \ current_number = number; \ } \ } #define COAP_SERIALIZE_BLOCK_OPTION(number, field, text) \ if (IS_OPTION(coap_pkt, number)) \ { \ uint32_t block = coap_pkt->field##_num << 4; \ PRINTF(text" [%lu%s (%u B/blk)]\n", coap_pkt->field##_num, coap_pkt->field##_more ? "+" : "", coap_pkt->field##_size); \ if (coap_pkt->field##_more) block |= 0x8; \ block |= 0xF & coap_log_2(coap_pkt->field##_size/16); \ PRINTF(text" encoded: 0x%lX\n", block); \ option += coap_serialize_int_option(number, current_number, option, block); \ current_number = number; \ } /* To store error code and human-readable payload */ extern const char* coap_error_message; uint16_t coap_get_mid(void); void coap_init_message(void* packet, coap_message_type_t type, uint8_t code, uint16_t mid); size_t coap_serialize_get_size(void* packet); size_t coap_serialize_message(void* packet, uint8_t* buffer); coap_status_t coap_parse_message(void* request, uint8_t* data, uint16_t data_len); void coap_free_header(void* packet); char* coap_get_multi_option_as_string(multi_option_t* option); void coap_add_multi_option(multi_option_t** dst, uint8_t* option, size_t option_len, uint8_t is_static); void free_multi_option(multi_option_t* dst); int coap_get_query_variable(void* packet, const char* name, const char** output); int coap_get_post_variable(void* packet, const char* name, const char** output); /*-----------------------------------------------------------------------------------*/ int coap_set_status_code(void* packet, unsigned int code); unsigned int coap_get_header_content_type(void* packet); int coap_set_header_content_type(void* packet, unsigned int content_type); int coap_get_header_accept(void* packet, const uint16_t** accept); int coap_set_header_accept(void* packet, uint16_t accept); int coap_get_header_max_age(void* packet, uint32_t* age); int coap_set_header_max_age(void* packet, uint32_t age); int coap_get_header_etag(void* packet, const uint8_t** etag); int coap_set_header_etag(void* packet, const uint8_t* etag, size_t etag_len); int coap_get_header_if_match(void* packet, const uint8_t** etag); int coap_set_header_if_match(void* packet, const uint8_t* etag, size_t etag_len); int coap_get_header_if_none_match(void* packet); int coap_set_header_if_none_match(void* packet); int coap_get_header_token(void* packet, const uint8_t** token); int coap_set_header_token(void* packet, const uint8_t* token, size_t token_len); int coap_get_header_proxy_uri(void* packet, const char** uri); /* In-place string might not be 0-terminated. */ int coap_set_header_proxy_uri(void* packet, const char* uri); int coap_get_header_uri_host(void* packet, const char** host); /* In-place string might not be 0-terminated. */ int coap_set_header_uri_host(void* packet, const char* host); int coap_get_header_uri_path(void* packet, const char** path); /* In-place string might not be 0-terminated. */ int coap_set_header_uri_path(void* packet, const char* path); int coap_set_header_uri_path_segment(void* packet, const char* path); int coap_get_header_uri_query(void* packet, const char** query); /* In-place string might not be 0-terminated. */ int coap_set_header_uri_query(void* packet, const char* query); int coap_get_header_location_path(void* packet, const char** path); /* In-place string might not be 0-terminated. */ int coap_set_header_location_path(void* packet, const char* path); /* Also splits optional query into Location-Query option. */ int coap_get_header_location_query(void* packet, const char** query); /* In-place string might not be 0-terminated. */ int coap_set_header_location_query(void* packet, char* query); int coap_get_header_observe(void* packet, uint32_t* observe); int coap_set_header_observe(void* packet, uint32_t observe); int coap_get_header_block2(void* packet, uint32_t* num, uint8_t* more, uint16_t* size, uint32_t* offset); int coap_set_header_block2(void* packet, uint32_t num, uint8_t more, uint16_t size); int coap_get_header_block1(void* packet, uint32_t* num, uint8_t* more, uint16_t* size, uint32_t* offset); int coap_set_header_block1(void* packet, uint32_t num, uint8_t more, uint16_t size); int coap_get_header_size(void* packet, uint32_t* size); int coap_set_header_size(void* packet, uint32_t size); int coap_get_payload(void* packet, const uint8_t** payload); int coap_set_payload(void* packet, const void* payload, size_t length); #endif /* COAP_13_H_ */ ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/internals.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Fabien Fleutot - Please refer to git log * Toby Jaffey - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - Please refer to git log * Scott Bertin - Please refer to git log * *******************************************************************************/ /* Copyright (c) 2013, 2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. David Navarro */ #ifndef _LWM2M_INTERNALS_H_ #define _LWM2M_INTERNALS_H_ #include "liblwm2m.h" #include #include #include #include #include #include #include #include "er-coap-13/er-coap-13.h" #include "connection.h" #ifdef LWM2M_WITH_LOGS #include #define LOG(STR) (void)lwm2m_printf("[%d][%s:%d] " STR "\r\n", (uint32_t)lwm2m_gettime(), __func__ , __LINE__) #define LOG_ARG(FMT, ...) (void)lwm2m_printf("[%d][%s:%d] " FMT "\r\n", (uint32_t)lwm2m_gettime(), __func__ , __LINE__ , __VA_ARGS__) #define LOG_URI(URI) \ { \ if ((URI) == NULL) (void)lwm2m_printf("[%s:%d] NULL\r\n", __func__ , __LINE__); \ else \ { \ (void)lwm2m_printf("[%s:%d] /%d", __func__ , __LINE__ , (URI)->objectId); \ if (LWM2M_URI_IS_SET_INSTANCE(URI)) (void)lwm2m_printf("/%d", (URI)->instanceId); \ if (LWM2M_URI_IS_SET_RESOURCE(URI)) (void)lwm2m_printf("/%d", (URI)->resourceId); \ (void)lwm2m_printf("\r\n"); \ } \ } #define UNUSEX(x) #define STR_STATUS(S) \ ((S) == STATE_DEREGISTERED ? "STATE_DEREGISTERED" : \ ((S) == STATE_REG_PENDING ? "STATE_REG_PENDING" : \ ((S) == STATE_REGISTERED ? "STATE_REGISTERED" : \ ((S) == STATE_REG_FAILED ? "STATE_REG_FAILED" : \ ((S) == STATE_REG_UPDATE_PENDING ? "STATE_REG_UPDATE_PENDING" : \ ((S) == STATE_REG_UPDATE_NEEDED ? "STATE_REG_UPDATE_NEEDED" : \ ((S) == STATE_REG_FULL_UPDATE_NEEDED ? "STATE_REG_FULL_UPDATE_NEEDED" : \ ((S) == STATE_DEREG_PENDING ? "STATE_DEREG_PENDING" : \ ((S) == STATE_BS_HOLD_OFF ? "STATE_BS_HOLD_OFF" : \ ((S) == STATE_BS_INITIATED ? "STATE_BS_INITIATED" : \ ((S) == STATE_BS_PENDING ? "STATE_BS_PENDING" : \ ((S) == STATE_BS_FINISHED ? "STATE_BS_FINISHED" : \ ((S) == STATE_BS_FINISHING ? "STATE_BS_FINISHING" : \ ((S) == STATE_BS_FAILING ? "STATE_BS_FAILING" : \ ((S) == STATE_BS_FAILED ? "STATE_BS_FAILED" : \ "Unknown"))))))))))))))) #define STR_MEDIA_TYPE(M) \ ((M) == LWM2M_CONTENT_TEXT ? "LWM2M_CONTENT_TEXT" : \ ((M) == LWM2M_CONTENT_LINK ? "LWM2M_CONTENT_LINK" : \ ((M) == LWM2M_CONTENT_OPAQUE ? "LWM2M_CONTENT_OPAQUE" : \ ((M) == LWM2M_CONTENT_TLV ? "LWM2M_CONTENT_TLV" : \ ((M) == LWM2M_CONTENT_JSON ? "LWM2M_CONTENT_JSON" : \ "Unknown"))))) #define STR_STATE(S) \ ((S) == STATE_INITIAL ? "STATE_INITIAL" : \ ((S) == STATE_BOOTSTRAP_REQUIRED ? "STATE_BOOTSTRAP_REQUIRED" : \ ((S) == STATE_BOOTSTRAPPING ? "STATE_BOOTSTRAPPING" : \ ((S) == STATE_REGISTER_REQUIRED ? "STATE_REGISTER_REQUIRED" : \ ((S) == STATE_REGISTERING ? "STATE_REGISTERING" : \ ((S) == STATE_READY ? "STATE_READY" : \ "Unknown")))))) #else #define UNUSEX(x) (x)=(x) #define LOG_ARG(FMT, ...) #define LOG(STR) #define LOG_URI(URI) #endif #define LWM2M_DEFAULT_LIFETIME 86400 #ifdef LWM2M_SUPPORT_JSON #define REG_LWM2M_RESOURCE_TYPE ">;rt=\"oma.lwm2m\";ct=11543," #define REG_LWM2M_RESOURCE_TYPE_LEN 25 #else #define REG_LWM2M_RESOURCE_TYPE ">;rt=\"oma.lwm2m\"," #define REG_LWM2M_RESOURCE_TYPE_LEN 17 #endif #define REG_START "<" #define REG_DEFAULT_PATH "/" #define REG_OBJECT_MIN_LEN 5 // "," #define REG_PATH_END ">," #define REG_PATH_SEPARATOR "/" #define REG_OBJECT_PATH "<%s/%hu>," #define REG_OBJECT_INSTANCE_PATH "<%s/%hu/%hu>," #define URI_REGISTRATION_SEGMENT "rd" #define URI_REGISTRATION_SEGMENT_LEN 2 #define URI_BOOTSTRAP_SEGMENT "bs" #define URI_BOOTSTRAP_SEGMENT_LEN 2 #define QUERY_STARTER "?" #define QUERY_NAME "ep=" #define QUERY_NAME_LEN 3 // strlen("ep=") #define QUERY_SMS "sms=" #define QUERY_SMS_LEN 4 #define QUERY_LIFETIME "lt=" #define QUERY_LIFETIME_LEN 3 #define QUERY_VERSION "lwm2m=" #define QUERY_VERSION_LEN 6 #define QUERY_BINDING "b=" #define QUERY_BINDING_LEN 2 #define QUERY_DELIMITER "&" #define LWM2M_VERSION "1.0" #define LWM2M_VERSION_LEN 3 #define QUERY_VERSION_FULL QUERY_VERSION LWM2M_VERSION #define QUERY_VERSION_FULL_LEN QUERY_VERSION_LEN+LWM2M_VERSION_LEN #define REG_URI_START '<' #define REG_URI_END '>' #define REG_DELIMITER ',' #define REG_ATTR_SEPARATOR ';' #define REG_ATTR_EQUALS '=' #define REG_ATTR_TYPE_KEY "rt" #define REG_ATTR_TYPE_KEY_LEN 2 #define REG_ATTR_TYPE_VALUE "\"oma.lwm2m\"" #define REG_ATTR_TYPE_VALUE_LEN 11 #define REG_ATTR_CONTENT_KEY "ct" #define REG_ATTR_CONTENT_KEY_LEN 2 #define REG_ATTR_CONTENT_JSON "11543" // Temporary value #define REG_ATTR_CONTENT_JSON_LEN 5 #define ATTR_SERVER_ID_STR "ep=" #define ATTR_SERVER_ID_LEN 3 #define ATTR_MIN_PERIOD_STR "pmin=" #define ATTR_MIN_PERIOD_LEN 5 #define ATTR_MAX_PERIOD_STR "pmax=" #define ATTR_MAX_PERIOD_LEN 5 #define ATTR_GREATER_THAN_STR "gt=" #define ATTR_GREATER_THAN_LEN 3 #define ATTR_LESS_THAN_STR "lt=" #define ATTR_LESS_THAN_LEN 3 #define ATTR_STEP_STR "st=" #define ATTR_STEP_LEN 3 #define ATTR_DIMENSION_STR "dim=" #define ATTR_DIMENSION_LEN 4 #define URI_MAX_STRING_LEN 18 // /65535/65535/65535 #define _PRV_64BIT_BUFFER_SIZE 8 #define LINK_ITEM_START "<" #define LINK_ITEM_START_SIZE 1 #define LINK_ITEM_END ">," #define LINK_ITEM_END_SIZE 2 #define LINK_ITEM_DIM_START ">;dim=" #define LINK_ITEM_DIM_START_SIZE 6 #define LINK_ITEM_ATTR_END "," #define LINK_ITEM_ATTR_END_SIZE 1 #define LINK_URI_SEPARATOR "/" #define LINK_URI_SEPARATOR_SIZE 1 #define LINK_ATTR_SEPARATOR ";" #define LINK_ATTR_SEPARATOR_SIZE 1 #define ATTR_FLAG_NUMERIC (uint8_t)(LWM2M_ATTR_FLAG_LESS_THAN | LWM2M_ATTR_FLAG_GREATER_THAN | LWM2M_ATTR_FLAG_STEP) #define LWM2M_URI_FLAG_DM (uint8_t)0x00 #define LWM2M_URI_FLAG_DELETE_ALL (uint8_t)0x10 #define LWM2M_URI_FLAG_REGISTRATION (uint8_t)0x20 #define LWM2M_URI_FLAG_BOOTSTRAP (uint8_t)0x40 #define LWM2M_URI_MASK_TYPE (uint8_t)0x70 #define LWM2M_URI_MASK_ID (uint8_t)0x07 typedef struct { uint16_t clientID; lwm2m_uri_t uri; lwm2m_result_callback_t callback; void * userData; } dm_data_t; typedef enum { URI_DEPTH_OBJECT, URI_DEPTH_OBJECT_INSTANCE, URI_DEPTH_RESOURCE, URI_DEPTH_RESOURCE_INSTANCE } uri_depth_t; #ifdef LWM2M_BOOTSTRAP_SERVER_MODE typedef struct { bool isUri; lwm2m_uri_t uri; lwm2m_bootstrap_callback_t callback; void * userData; } bs_data_t; #endif // defined in uri.c lwm2m_uri_t * uri_decode(char * altPath, multi_option_t *uriPath); int uri_getNumber(uint8_t * uriString, size_t uriLength); int uri_toString(lwm2m_uri_t * uriP, uint8_t * buffer, size_t bufferLen, uri_depth_t * depthP); // defined in objects.c uint8_t object_readData(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, int * sizeP, lwm2m_data_t ** dataP, lwm2m_data_cfg_t *cfg, uint16_t serverId); uint8_t object_read(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, lwm2m_media_type_t * formatP, uint8_t ** bufferP, size_t * lengthP, uint16_t serverId); uint8_t object_write(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, lwm2m_media_type_t format, uint8_t * buffer, size_t length); uint8_t object_create(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, lwm2m_media_type_t format, uint8_t * buffer, size_t length); uint8_t object_execute(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, uint8_t * buffer, size_t length); uint8_t object_delete(lwm2m_context_t * contextP, lwm2m_uri_t * uriP); uint8_t object_discover(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, lwm2m_server_t * serverP, uint8_t ** bufferP, size_t * lengthP); uint8_t object_checkReadable(lwm2m_context_t * contextP, lwm2m_uri_t * uriP); uint8_t object_checkNumeric(lwm2m_context_t * contextP, lwm2m_uri_t * uriP); bool object_isInstanceNew(lwm2m_context_t * contextP, uint16_t objectId, uint16_t instanceId); int object_getRegisterPayloadBufferLength(lwm2m_context_t * contextP); int object_getRegisterPayload(lwm2m_context_t * contextP, uint8_t * buffer, size_t length); int object_getServers(lwm2m_context_t * contextP, bool checkOnly); uint8_t object_createInstance(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, lwm2m_data_t * dataP); uint8_t object_writeInstance(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, lwm2m_data_t * dataP); // defined in transaction.c lwm2m_transaction_t * transaction_new(void * sessionH, unsigned char method, char * altPath, lwm2m_uri_t * uriP, uint16_t mID, uint8_t token_len, uint8_t* token); int transaction_send(lwm2m_context_t * contextP, lwm2m_transaction_t * transacP); void transaction_free(lwm2m_transaction_t * transacP); void transaction_remove(lwm2m_context_t * contextP, lwm2m_transaction_t * transacP); bool transaction_handleResponse(lwm2m_context_t * contextP, void * fromSessionH, coap_packet_t * message, coap_packet_t * response); void transaction_step(lwm2m_context_t * contextP, time_t currentTime, time_t * timeoutP); // defined in management.c uint8_t dm_handleRequest(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, lwm2m_server_t * serverP, coap_packet_t * message, coap_packet_t * response); // defined in observe.c uint8_t observe_handleRequest(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, lwm2m_server_t * serverP, int size, lwm2m_data_t * dataP, coap_packet_t * message, coap_packet_t * response); void observe_cancel(lwm2m_context_t * contextP, uint16_t mid, void * fromSessionH); uint8_t observe_setParameters(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, lwm2m_server_t * serverP, lwm2m_attributes_t * attrP); void observe_step(lwm2m_context_t * contextP, time_t currentTime, time_t * timeoutP); void observe_clear(lwm2m_context_t * contextP, lwm2m_uri_t * uriP); //bool observe_handleNotify(lwm2m_context_t * contextP, void * fromSessionH, coap_packet_t * message, coap_packet_t * response); void observe_remove(lwm2m_observation_t * observationP); lwm2m_observed_t * observe_findByUri(lwm2m_context_t * contextP, lwm2m_uri_t * uriP); // defined in registration.c //uint8_t registration_handleRequest(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, void * fromSessionH, coap_packet_t * message, coap_packet_t * response); void registration_deregister(lwm2m_context_t * contextP, lwm2m_server_t * serverP); void registration_freeClient(lwm2m_client_t * clientP); uint8_t registration_start(lwm2m_context_t * contextP); void registration_step(lwm2m_context_t * contextP, time_t currentTime, time_t * timeoutP); lwm2m_status_t registration_getStatus(lwm2m_context_t * contextP); void registration_reset(lwm2m_context_t * contextP, lwm2m_server_t * serverP); // defined in packet.c uint8_t message_send(lwm2m_context_t * contextP, coap_packet_t * message, void * sessionH); // defined in bootstrap.c void bootstrap_step(lwm2m_context_t * contextP, uint32_t currentTime, time_t* timeoutP); uint8_t bootstrap_handleCommand(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, lwm2m_server_t * serverP, coap_packet_t * message, coap_packet_t * response); uint8_t bootstrap_handleDeleteAll(lwm2m_context_t * context, void * fromSessionH); uint8_t bootstrap_handleFinish(lwm2m_context_t * context, void * fromSessionH); uint8_t bootstrap_handleRequest(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, void * fromSessionH, coap_packet_t * message, coap_packet_t * response); void bootstrap_start(lwm2m_context_t * contextP); lwm2m_status_t bootstrap_getStatus(lwm2m_context_t * contextP); bool bootstrap_isBsServerIpValid(const lwm2m_context_t *contextP); // defined in tlv.c int tlv_parse(uint8_t * buffer, size_t bufferLen, lwm2m_data_t ** dataP); int tlv_serialize(bool isResourceInstance, int size, lwm2m_data_t * dataP, uint8_t ** bufferP); // defined in json.c #ifdef LWM2M_SUPPORT_JSON int json_parse(lwm2m_uri_t * uriP, uint8_t * buffer, size_t bufferLen, lwm2m_data_t ** dataP); int json_serialize(lwm2m_uri_t * uriP, int size, lwm2m_data_t * tlvP, uint8_t ** bufferP); #endif // defined in discover.c int discover_serialize(lwm2m_context_t * contextP, lwm2m_uri_t * uriP, lwm2m_server_t * serverP, int size, lwm2m_data_t * dataP, uint8_t ** bufferP); // defined in block1.c uint8_t coap_block1_handler(lwm2m_block1_data_t ** block1Data, uint16_t mid, uint8_t * buffer, size_t length, uint16_t blockSize, uint32_t blockNum, bool blockMore, uint8_t ** outputBuffer, size_t * outputLength); void free_block1_buffer(lwm2m_block1_data_t * block1Data); // defined in utils.c lwm2m_data_type_t utils_depthToDatatype(uri_depth_t depth); lwm2m_binding_t utils_stringToBinding(uint8_t *buffer, size_t length); lwm2m_media_type_t utils_convertMediaType(coap_content_type_t type); int utils_isAltPathValid(const char * altPath); int utils_stringCopy(char * buffer, size_t length, const char * str); size_t utils_intToText(int64_t data, uint8_t * string, size_t length); size_t utils_floatToText(double data, uint8_t * string, size_t length); int utils_textToInt(uint8_t * buffer, int length, int64_t * dataP); int utils_textToFloat(uint8_t * buffer, int length, double * dataP); void utils_copyValue(void * dst, const void * src, size_t len); size_t utils_base64GetSize(size_t dataLen); size_t utils_base64Encode(uint8_t * dataP, size_t dataLen, uint8_t * bufferP, size_t bufferLen); #ifdef LWM2M_CLIENT_MODE lwm2m_server_t * utils_findServer(lwm2m_context_t * contextP, void * fromSessionH); lwm2m_server_t * utils_findBootstrapServer(lwm2m_context_t * contextP, void * fromSessionH); #endif static inline int dm_isUriOpaqueHandle(const lwm2m_uri_t * uriP) { return (19 == uriP->objectId); } lwm2m_server_t * registration_get_registered_server(lwm2m_context_t * contextP); bool lwm2m_isBsCtrlInServerInitiatedBs(const lwm2m_context_t *contextP); #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/json.c ================================================ /******************************************************************************* * * Copyright (c) 2015 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * *******************************************************************************/ #include "internals.h" #include #include #include #include #ifdef LWM2M_SUPPORT_JSON #define PRV_JSON_BUFFER_SIZE 1024 #define JSON_MIN_ARRAY_LEN 21 // e":[{"n":"N","v":X}]} #define JSON_MIN_BASE_LEN 7 // n":"N", #define JSON_ITEM_MAX_SIZE 36 // with ten characters for value #define JSON_MIN_BX_LEN 5 // bt":1 #define JSON_FALSE_STRING "false" #define JSON_TRUE_STRING "true" #define JSON_RES_ITEM_URI "{\"n\":\"" #define JSON_RES_ITEM_URI_SIZE 6 #define JSON_ITEM_BOOL_TRUE "\",\"bv\":true}," #define JSON_ITEM_BOOL_TRUE_SIZE 13 #define JSON_ITEM_BOOL_FALSE "\",\"bv\":false}," #define JSON_ITEM_BOOL_FALSE_SIZE 14 #define JSON_ITEM_NUM "\",\"v\":" #define JSON_ITEM_NUM_SIZE 6 #define JSON_ITEM_NUM_END "}," #define JSON_ITEM_NUM_END_SIZE 2 #define JSON_ITEM_STRING_BEGIN "\",\"sv\":\"" #define JSON_ITEM_STRING_BEGIN_SIZE 8 #define JSON_ITEM_STRING_END "\"}," #define JSON_ITEM_STRING_END_SIZE 3 #define JSON_BN_HEADER_1 "{\"bn\":\"" #define JSON_BN_HEADER_1_SIZE 7 #define JSON_BN_HEADER_2 "\",\"e\":[" #define JSON_BN_HEADER_2_SIZE 7 #define JSON_HEADER "{\"e\":[" #define JSON_HEADER_SIZE 6 #define JSON_FOOTER "]}" #define JSON_FOOTER_SIZE 2 #define _GO_TO_NEXT_CHAR(I,B,L) \ { \ I++; \ I += prv_skipSpace(B+I, L-I); \ if (I == L) goto error; \ } typedef enum { _STEP_START, _STEP_TOKEN, _STEP_ANY_SEPARATOR, _STEP_SEPARATOR, _STEP_QUOTED_VALUE, _STEP_VALUE, _STEP_DONE } _itemState; typedef enum { _TYPE_UNSET, _TYPE_FALSE, _TYPE_TRUE, _TYPE_FLOAT, _TYPE_STRING } _type; typedef struct { uint16_t ids[4]; _type type; uint8_t *value; size_t valueLen; } _record_t; static int prv_isReserved(char sign) { if (sign == '[' || sign == '{' || sign == ']' || sign == '}' || sign == ':' || sign == ',' || sign == '"') { return 1; } return 0; } static int prv_isWhiteSpace(uint8_t sign) { if (sign == 0x20 || sign == 0x09 || sign == 0x0A || sign == 0x0D) { return 1; } return 0; } static size_t prv_skipSpace(uint8_t *buffer, size_t bufferLen) { size_t i; i = 0; while ((i < bufferLen) && prv_isWhiteSpace(buffer[i])) { i++; } return i; } static int prv_split(uint8_t *buffer, size_t bufferLen, int *tokenStartP, int *tokenLenP, int *valueStartP, int *valueLenP) { size_t index; _itemState step; index = 0; step = _STEP_START; index = prv_skipSpace(buffer + index, bufferLen - index); if (index == bufferLen) return -1; while ((index < bufferLen) && (buffer[index] != ',')) { switch (step) { case _STEP_START: if (buffer[index] != '"') return -1; *tokenStartP = index + 1; step = _STEP_TOKEN; break; case _STEP_TOKEN: if (buffer[index] == '"') { *tokenLenP = index - *tokenStartP; step = _STEP_ANY_SEPARATOR; } break; case _STEP_ANY_SEPARATOR: if (buffer[index] != ':') return -1; step = _STEP_SEPARATOR; break; case _STEP_SEPARATOR: if (buffer[index] == '"') { *valueStartP = index; step = _STEP_QUOTED_VALUE; } else if (!prv_isReserved(buffer[index])) { *valueStartP = index; step = _STEP_VALUE; } else { return -1; } break; case _STEP_QUOTED_VALUE: if (buffer[index] == '"' && buffer[index - 1] != '\\' ) { *valueLenP = index - *valueStartP + 1; step = _STEP_DONE; } break; case _STEP_VALUE: if (prv_isWhiteSpace(buffer[index])) { *valueLenP = index - *valueStartP; step = _STEP_DONE; } break; case _STEP_DONE: default: return -1; } index++; if (step == _STEP_START || step == _STEP_ANY_SEPARATOR || step == _STEP_SEPARATOR || step == _STEP_DONE) { index += prv_skipSpace(buffer + index, bufferLen - index); } } if (step == _STEP_VALUE) { *valueLenP = index - *valueStartP; step = _STEP_DONE; } if (step != _STEP_DONE) return -1; return (int)index; } static int prv_countItems(uint8_t *buffer, size_t bufferLen) { int count; size_t index; int in; count = 0; index = 0; in = 0; while (index < bufferLen) { if (in == 0) { if (buffer[index] != '{') return -1; in = 1; _GO_TO_NEXT_CHAR(index, buffer, bufferLen); } else { if (buffer[index] == '{') return -1; if (buffer[index] == '}') { in = 0; count++; _GO_TO_NEXT_CHAR(index, buffer, bufferLen); if (buffer[index] == ']') { break; } if (buffer[index] != ',') return -1; _GO_TO_NEXT_CHAR(index, buffer, bufferLen); } else { _GO_TO_NEXT_CHAR(index, buffer, bufferLen); } } } if (in == 1) return -1; return count; error: return -1; } static int prv_parseItem(uint8_t *buffer, size_t bufferLen, _record_t *recordP) { size_t index; memset(recordP->ids, 0xFF, 4 * sizeof(uint16_t)); recordP->type = _TYPE_UNSET; recordP->value = NULL; recordP->valueLen = 0; index = 0; do { int tokenStart; int tokenLen; int valueStart; int valueLen; int next; next = prv_split(buffer + index, bufferLen - index, &tokenStart, &tokenLen, &valueStart, &valueLen); if (next < 0) return -1; switch (tokenLen) { case 1: { switch (buffer[index + tokenStart]) { case 'n': { int i; int j; if (recordP->ids[0] != LWM2M_MAX_ID) return -1; // Check for " around URI if (valueLen < 3 || buffer[index + valueStart] != '"' || buffer[index + valueStart + valueLen - 1] != '"') { return -1; } // Ignore starting / if (buffer[index + valueStart + 1] == '/') { if (valueLen < 4) { return -1; } valueStart += 1; valueLen -= 1; } i = 0; j = 0; do { uint32_t readId; readId = 0; i++; while (i < valueLen - 1 && buffer[index + valueStart + i] != '/') { if (buffer[index + valueStart + i] < '0' || buffer[index + valueStart + i] > '9') { return -1; } readId *= 10; readId += buffer[index + valueStart + i] - '0'; if (readId > LWM2M_MAX_ID) return -1; i++; } recordP->ids[j] = readId; j++; } while (i < valueLen - 1 && j < 4 && buffer[index + valueStart + i] == '/'); if (i < valueLen - 1 ) return -1; } break; case 'v': if (recordP->type != _TYPE_UNSET) return -1; recordP->type = _TYPE_FLOAT; recordP->value = buffer + index + valueStart; recordP->valueLen = valueLen; break; case 't': // TODO: support time break; default: return -1; } } break; case 2: { // "bv", "ov", or "sv" if (buffer[index + tokenStart + 1] != 'v') return -1; switch (buffer[index + tokenStart]) { case 'b': if (recordP->type != _TYPE_UNSET) return -1; if (0 == lwm2m_strncmp(JSON_TRUE_STRING, (char *)buffer + index + valueStart, valueLen)) { recordP->type = _TYPE_TRUE; } else if (0 == lwm2m_strncmp(JSON_FALSE_STRING, (char *)buffer + index + valueStart, valueLen)) { recordP->type = _TYPE_FALSE; } else { return -1; } break; case 'o': if (recordP->type != _TYPE_UNSET) return -1; // TODO: support object link break; case 's': if (recordP->type != _TYPE_UNSET) return -1; // Check for " around value if (valueLen < 2 || buffer[index + valueStart] != '"' || buffer[index + valueStart + valueLen - 1] != '"') { return -1; } recordP->type = _TYPE_STRING; recordP->value = buffer + index + valueStart + 1; recordP->valueLen = valueLen - 2; break; default: return -1; } } break; default: return -1; } index += next + 1; } while (index < bufferLen); return 0; } static bool prv_convertValue(_record_t *recordP, lwm2m_data_t *targetP) { switch (recordP->type) { case _TYPE_FALSE: lwm2m_data_encode_bool(false, targetP); break; case _TYPE_TRUE: lwm2m_data_encode_bool(true, targetP); break; case _TYPE_FLOAT: { size_t i; i = 0; while (i < recordP->valueLen && recordP->value[i] != '.') { i++; } if (i == recordP->valueLen) { int64_t value; if ( 1 != utils_textToInt(recordP->value, recordP->valueLen, &value)) { return false; } lwm2m_data_encode_int(value, targetP); } else { double value; if ( 1 != utils_textToFloat(recordP->value, recordP->valueLen, &value)) { return false; } lwm2m_data_encode_float(value, targetP); } } break; case _TYPE_STRING: lwm2m_data_encode_opaque(recordP->value, recordP->valueLen, targetP); targetP->type = LWM2M_TYPE_STRING; break; case _TYPE_UNSET: default: return false; } return true; } static lwm2m_data_t *prv_findDataItem(lwm2m_data_t *listP, int count, uint16_t id) { int i; i = 0; while (i < count) { if (listP[i].type != LWM2M_TYPE_UNDEFINED && listP[i].id == id) { return listP + i; } i++; } return NULL; } static uri_depth_t prv_decreaseLevel(uri_depth_t level) { switch(level) { case URI_DEPTH_OBJECT: return URI_DEPTH_OBJECT_INSTANCE; case URI_DEPTH_OBJECT_INSTANCE: return URI_DEPTH_RESOURCE; case URI_DEPTH_RESOURCE: return URI_DEPTH_RESOURCE_INSTANCE; case URI_DEPTH_RESOURCE_INSTANCE: return URI_DEPTH_RESOURCE_INSTANCE; default: return URI_DEPTH_RESOURCE; } } static lwm2m_data_t *prv_extendData(lwm2m_data_t *parentP) { lwm2m_data_t *newP; newP = lwm2m_data_new(parentP->value.asChildren.count + 1); if (newP == NULL) return NULL; if (parentP->value.asChildren.array != NULL) { memcpy(newP, parentP->value.asChildren.array, parentP->value.asChildren.count * sizeof(lwm2m_data_t)); lwm2m_free(parentP->value.asChildren.array); // do not use lwm2m_data_free() to keep pointed values } parentP->value.asChildren.array = newP; parentP->value.asChildren.count += 1; return newP + parentP->value.asChildren.count - 1; } static int prv_convertRecord(lwm2m_uri_t *uriP, _record_t *recordArray, int count, lwm2m_data_t **dataP) { int index; int freeIndex; lwm2m_data_t *rootP; int size; uri_depth_t rootLevel; if (uriP == NULL) { size = count; *dataP = lwm2m_data_new(count); if (NULL == *dataP) return -1; rootLevel = URI_DEPTH_OBJECT; rootP = *dataP; } else { lwm2m_data_t *parentP; size = 1; *dataP = lwm2m_data_new(1); if (NULL == *dataP) return -1; (*dataP)->type = LWM2M_TYPE_OBJECT; (*dataP)->id = uriP->objectId; rootLevel = URI_DEPTH_OBJECT_INSTANCE; parentP = *dataP; if (LWM2M_URI_IS_SET_INSTANCE(uriP)) { parentP->value.asChildren.count = 1; parentP->value.asChildren.array = lwm2m_data_new(1); if (NULL == parentP->value.asChildren.array) goto error; parentP = parentP->value.asChildren.array; parentP->type = LWM2M_TYPE_OBJECT_INSTANCE; parentP->id = uriP->instanceId; rootLevel = URI_DEPTH_RESOURCE; if (LWM2M_URI_IS_SET_RESOURCE(uriP)) { parentP->value.asChildren.count = 1; parentP->value.asChildren.array = lwm2m_data_new(1); if (NULL == parentP->value.asChildren.array) goto error; parentP = parentP->value.asChildren.array; parentP->type = LWM2M_TYPE_UNDEFINED; parentP->id = uriP->resourceId; rootLevel = URI_DEPTH_RESOURCE_INSTANCE; } } parentP->value.asChildren.count = count; parentP->value.asChildren.array = lwm2m_data_new(count); if (NULL == parentP->value.asChildren.array) goto error; rootP = parentP->value.asChildren.array; } freeIndex = 0; for (index = 0 ; index < count ; index++) { lwm2m_data_t *targetP; int resSegmentIndex; int i; // check URI depth // resSegmentIndex is set to the resource segment position switch(rootLevel) { case URI_DEPTH_OBJECT: resSegmentIndex = 2; break; case URI_DEPTH_OBJECT_INSTANCE: resSegmentIndex = 1; break; case URI_DEPTH_RESOURCE: resSegmentIndex = 0; break; case URI_DEPTH_RESOURCE_INSTANCE: resSegmentIndex = -1; break; default: goto error; } for (i = 0 ; i <= resSegmentIndex ; i++) { if (recordArray[index].ids[i] == LWM2M_MAX_ID) goto error; } if (resSegmentIndex < 2) { if (recordArray[index].ids[resSegmentIndex + 2] != LWM2M_MAX_ID) goto error; } targetP = prv_findDataItem(rootP, count, recordArray[index].ids[0]); if (targetP == NULL) { targetP = rootP + freeIndex; freeIndex++; targetP->id = recordArray[index].ids[0]; targetP->type = utils_depthToDatatype(rootLevel); } if (recordArray[index].ids[1] != LWM2M_MAX_ID) { lwm2m_data_t *parentP; uri_depth_t level; parentP = targetP; level = prv_decreaseLevel(rootLevel); for (i = 1 ; i <= resSegmentIndex ; i++) { targetP = prv_findDataItem(parentP->value.asChildren.array, parentP->value.asChildren.count, recordArray[index].ids[i]); if (targetP == NULL) { targetP = prv_extendData(parentP); if (targetP == NULL) goto error; targetP->id = recordArray[index].ids[i]; targetP->type = utils_depthToDatatype(level); } level = prv_decreaseLevel(level); parentP = targetP; } if (recordArray[index].ids[resSegmentIndex + 1] != LWM2M_MAX_ID) { targetP->type = LWM2M_TYPE_MULTIPLE_RESOURCE; targetP = prv_extendData(targetP); if (targetP == NULL) goto error; targetP->id = recordArray[index].ids[resSegmentIndex + 1]; targetP->type = LWM2M_TYPE_UNDEFINED; } } if (true != prv_convertValue(recordArray + index, targetP)) goto error; } return size; error: lwm2m_data_free(size, *dataP); *dataP = NULL; return -1; } static int prv_dataStrip(int size, lwm2m_data_t *dataP, lwm2m_data_t **resultP) { int i; int j; int realSize; realSize = 0; for (i = 0 ; i < size ; i++) { if (dataP[i].type != LWM2M_TYPE_UNDEFINED) { realSize++; } } *resultP = lwm2m_data_new(realSize); if (*resultP == NULL) return -1; j = 0; for (i = 0 ; i < size ; i++) { if (dataP[i].type != LWM2M_TYPE_UNDEFINED) { memcpy((*resultP) + j, dataP + i, sizeof(lwm2m_data_t)); if (dataP[i].type == LWM2M_TYPE_OBJECT || dataP[i].type == LWM2M_TYPE_OBJECT_INSTANCE || dataP[i].type == LWM2M_TYPE_MULTIPLE_RESOURCE) { int childLen; childLen = prv_dataStrip(dataP[i].value.asChildren.count, dataP[i].value.asChildren.array, &((*resultP)[j].value.asChildren.array)); if (childLen <= 0) { // skip this one j--; } else { (*resultP)[j].value.asChildren.count = childLen; } } else { dataP[i].value.asBuffer.buffer = NULL; } j++; } } return realSize; } int json_parse(lwm2m_uri_t *uriP, uint8_t *buffer, size_t bufferLen, lwm2m_data_t **dataP) { size_t index; int count = 0; bool eFound = false; bool bnFound = false; bool btFound = false; int bnStart; int bnLen; _record_t *recordArray; lwm2m_data_t *parsedP; LOG_ARG("bufferLen: %d, buffer: \"%s\"", bufferLen, (char *)buffer); LOG_URI(uriP); *dataP = NULL; recordArray = NULL; parsedP = NULL; index = prv_skipSpace(buffer, bufferLen); if (index == bufferLen) return -1; if (buffer[index] != '{') return -1; do { _GO_TO_NEXT_CHAR(index, buffer, bufferLen); if (buffer[index] != '"') goto error; if (index++ >= bufferLen) goto error; switch (buffer[index]) { case 'e': { int recordIndex; if (bufferLen - index < JSON_MIN_ARRAY_LEN) goto error; index++; if (buffer[index] != '"') goto error; if (eFound == true) goto error; eFound = true; _GO_TO_NEXT_CHAR(index, buffer, bufferLen); if (buffer[index] != ':') goto error; _GO_TO_NEXT_CHAR(index, buffer, bufferLen); if (buffer[index] != '[') goto error; _GO_TO_NEXT_CHAR(index, buffer, bufferLen); count = prv_countItems(buffer + index, bufferLen - index); if (count <= 0) goto error; recordArray = (_record_t *)lwm2m_malloc(count * sizeof(_record_t)); if (recordArray == NULL) goto error; // at this point we are sure buffer[index] is '{' and all { and } are matching recordIndex = 0; while (recordIndex < count) { int itemLen; if (buffer[index] != '{') goto error; itemLen = 0; while (buffer[index + itemLen] != '}') itemLen++; if (0 != prv_parseItem(buffer + index + 1, itemLen - 1, recordArray + recordIndex)) { goto error; } recordIndex++; index += itemLen; _GO_TO_NEXT_CHAR(index, buffer, bufferLen); switch (buffer[index]) { case ',': _GO_TO_NEXT_CHAR(index, buffer, bufferLen); break; case ']': if (recordIndex == count) break; // else this is an error default: goto error; } } if (buffer[index] != ']') goto error; } break; case 'b': if (bufferLen - index < JSON_MIN_BX_LEN) goto error; index++; switch (buffer[index]) { case 't': index++; if (buffer[index] != '"') goto error; if (btFound == true) goto error; btFound = true; // TODO: handle timed values // temp: skip this token while(index < bufferLen && buffer[index] != ',' && buffer[index] != '}') index++; if (index == bufferLen) goto error; index--; // end temp break; case 'n': { int next; int tokenStart; int tokenLen; int itemLen; index++; if (buffer[index] != '"') goto error; if (bnFound == true) goto error; bnFound = true; index -= 3; itemLen = 0; while (buffer[index + itemLen] != '}' && buffer[index + itemLen] != ',' && index + itemLen < bufferLen) { itemLen++; } if (index + itemLen == bufferLen) goto error; next = prv_split(buffer + index, itemLen, &tokenStart, &tokenLen, &bnStart, &bnLen); if (next < 0) goto error; bnStart += index; index += next - 1; } break; default: goto error; } break; default: goto error; } _GO_TO_NEXT_CHAR(index, buffer, bufferLen); } while (buffer[index] == ','); if (buffer[index] != '}') goto error; if (eFound == true) { lwm2m_uri_t baseURI; lwm2m_uri_t *baseUriP; lwm2m_data_t *resultP; int size; memset(&baseURI, 0, sizeof(lwm2m_uri_t)); if (bnFound == false) { baseUriP = uriP; } else { int res; // we ignore the request URI and use the bn one. // Check for " around URI if (bnLen < 3 || buffer[bnStart] != '"' || buffer[bnStart + bnLen - 1] != '"') { goto error; } bnStart += 1; bnLen -= 2; if (bnLen == 1) { if (buffer[bnStart] != '/') goto error; baseUriP = NULL; } else { res = lwm2m_stringToUri((char *)buffer + bnStart, bnLen, &baseURI); if (res < 0 || res != bnLen) goto error; baseUriP = &baseURI; } } count = prv_convertRecord(baseUriP, recordArray, count, &parsedP); lwm2m_free(recordArray); recordArray = NULL; if (count > 0 && uriP != NULL) { if (parsedP->type != LWM2M_TYPE_OBJECT || parsedP->id != uriP->objectId) goto error; if (!LWM2M_URI_IS_SET_INSTANCE(uriP)) { size = parsedP->value.asChildren.count; resultP = parsedP->value.asChildren.array; } else { int i; resultP = NULL; // be permissive and allow full object JSON when requesting for a single instance for (i = 0 ; i < (int)parsedP->value.asChildren.count && resultP == NULL; i++) { lwm2m_data_t *targetP; targetP = parsedP->value.asChildren.array + i; if (targetP->id == uriP->instanceId) { resultP = targetP->value.asChildren.array; size = targetP->value.asChildren.count; } } if (resultP == NULL) goto error; if (LWM2M_URI_IS_SET_RESOURCE(uriP)) { lwm2m_data_t *resP; resP = NULL; for (i = 0 ; i < size && resP == NULL; i++) { lwm2m_data_t *targetP; targetP = resultP + i; if (targetP->id == uriP->resourceId) { if (targetP->type == LWM2M_TYPE_MULTIPLE_RESOURCE) { resP = targetP->value.asChildren.array; size = targetP->value.asChildren.count; } else { size = prv_dataStrip(1, targetP, &resP); if (size <= 0) goto error; lwm2m_data_free(count, parsedP); parsedP = NULL; } } } if (resP == NULL) goto error; resultP = resP; } } } else { resultP = parsedP; size = count; } if (parsedP != NULL) { lwm2m_data_t *tempP; size = prv_dataStrip(size, resultP, &tempP); if (size <= 0) goto error; lwm2m_data_free(count, parsedP); resultP = tempP; } count = size; *dataP = resultP; } LOG_ARG("Parsing successful. count: %d", count); return count; error: LOG("Parsing failed"); if (parsedP != NULL) { lwm2m_data_free(count, parsedP); parsedP = NULL; } if (recordArray != NULL) { lwm2m_free(recordArray); } return -1; } static int prv_serializeValue(lwm2m_data_t *tlvP, uint8_t *buffer, size_t bufferLen) { int res; int head; switch (tlvP->type) { case LWM2M_TYPE_STRING: if (bufferLen < JSON_ITEM_STRING_BEGIN_SIZE) return -1; memcpy(buffer, JSON_ITEM_STRING_BEGIN, JSON_ITEM_STRING_BEGIN_SIZE); head = JSON_ITEM_STRING_BEGIN_SIZE; if (bufferLen - head < tlvP->value.asBuffer.length) return -1; memcpy(buffer + head, tlvP->value.asBuffer.buffer, tlvP->value.asBuffer.length); head += tlvP->value.asBuffer.length; if (bufferLen - head < JSON_ITEM_STRING_END_SIZE) return -1; memcpy(buffer + head, JSON_ITEM_STRING_END, JSON_ITEM_STRING_END_SIZE); head += JSON_ITEM_STRING_END_SIZE; break; case LWM2M_TYPE_INTEGER: { int64_t value; if (0 == lwm2m_data_decode_int(tlvP, &value)) return -1; if (bufferLen < JSON_ITEM_NUM_SIZE) return -1; memcpy(buffer, JSON_ITEM_NUM, JSON_ITEM_NUM_SIZE); head = JSON_ITEM_NUM_SIZE; res = utils_intToText(value, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; if (bufferLen - head < JSON_ITEM_NUM_END_SIZE) return -1; memcpy(buffer + head, JSON_ITEM_NUM_END, JSON_ITEM_NUM_END_SIZE); head += JSON_ITEM_NUM_END_SIZE; } break; case LWM2M_TYPE_FLOAT: { double value; if (0 == lwm2m_data_decode_float(tlvP, &value)) return -1; if (bufferLen < JSON_ITEM_NUM_SIZE) return -1; memcpy(buffer, JSON_ITEM_NUM, JSON_ITEM_NUM_SIZE); head = JSON_ITEM_NUM_SIZE; res = utils_floatToText(value, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; if (bufferLen - head < JSON_ITEM_NUM_END_SIZE) return -1; memcpy(buffer + head, JSON_ITEM_NUM_END, JSON_ITEM_NUM_END_SIZE); head += JSON_ITEM_NUM_END_SIZE; } break; case LWM2M_TYPE_BOOLEAN: { bool value; if (0 == lwm2m_data_decode_bool(tlvP, &value)) return -1; if (value == true) { if (bufferLen < JSON_ITEM_BOOL_TRUE_SIZE) return -1; memcpy(buffer, JSON_ITEM_BOOL_TRUE, JSON_ITEM_BOOL_TRUE_SIZE); head = JSON_ITEM_BOOL_TRUE_SIZE; } else { if (bufferLen < JSON_ITEM_BOOL_FALSE_SIZE) return -1; memcpy(buffer, JSON_ITEM_BOOL_FALSE, JSON_ITEM_BOOL_FALSE_SIZE); head = JSON_ITEM_BOOL_FALSE_SIZE; } } break; case LWM2M_TYPE_OPAQUE: if (bufferLen < JSON_ITEM_STRING_BEGIN_SIZE) return -1; memcpy(buffer, JSON_ITEM_STRING_BEGIN, JSON_ITEM_STRING_BEGIN_SIZE); head = JSON_ITEM_STRING_BEGIN_SIZE; res = utils_base64Encode(tlvP->value.asBuffer.buffer, tlvP->value.asBuffer.length, buffer + head, bufferLen - head); if (res == 0) return -1; head += res; if (bufferLen - head < JSON_ITEM_STRING_END_SIZE) return -1; memcpy(buffer + head, JSON_ITEM_STRING_END, JSON_ITEM_STRING_END_SIZE); head += JSON_ITEM_STRING_END_SIZE; break; case LWM2M_TYPE_OBJECT_LINK: // TODO: implement return -1; default: return -1; } return head; } int prv_serializeData(lwm2m_data_t *tlvP, uint8_t *parentUriStr, size_t parentUriLen, uint8_t *buffer, size_t bufferLen) { int head; int res; head = 0; switch (tlvP->type) { case LWM2M_TYPE_OBJECT: case LWM2M_TYPE_OBJECT_INSTANCE: case LWM2M_TYPE_MULTIPLE_RESOURCE: { uint8_t uriStr[URI_MAX_STRING_LEN]; size_t uriLen; size_t index; if (parentUriLen > 0) { if (URI_MAX_STRING_LEN < parentUriLen) return -1; memcpy(uriStr, parentUriStr, parentUriLen); uriLen = parentUriLen; } else { uriLen = 0; } res = utils_intToText(tlvP->id, uriStr + uriLen, URI_MAX_STRING_LEN - uriLen); if (res <= 0) return -1; uriLen += res; uriStr[uriLen] = '/'; uriLen++; head = 0; for (index = 0 ; index < tlvP->value.asChildren.count; index++) { res = prv_serializeData(tlvP->value.asChildren.array + index, uriStr, uriLen, buffer + head, bufferLen - head); if (res < 0) return -1; head += res; } } break; default: if (bufferLen < JSON_RES_ITEM_URI_SIZE) return -1; memcpy(buffer, JSON_RES_ITEM_URI, JSON_RES_ITEM_URI_SIZE); head = JSON_RES_ITEM_URI_SIZE; if (parentUriLen > 0) { if (bufferLen - head < parentUriLen) return -1; memcpy(buffer + head, parentUriStr, parentUriLen); head += parentUriLen; } res = utils_intToText(tlvP->id, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; res = prv_serializeValue(tlvP, buffer + head, bufferLen - head); if (res < 0) return -1; head += res; break; } return head; } static int prv_findAndCheckData(lwm2m_uri_t *uriP, uri_depth_t level, size_t size, lwm2m_data_t *tlvP, lwm2m_data_t **targetP) { size_t index; int result; if (size == 0) return 0; if (size > 1) { if (tlvP[0].type == LWM2M_TYPE_OBJECT || tlvP[0].type == LWM2M_TYPE_OBJECT_INSTANCE) { for (index = 0; index < size; index++) { if (tlvP[index].type != tlvP[0].type) { *targetP = NULL; return -1; } } } else { for (index = 0; index < size; index++) { if (tlvP[index].type == LWM2M_TYPE_OBJECT || tlvP[index].type == LWM2M_TYPE_OBJECT_INSTANCE) { *targetP = NULL; return -1; } } } } *targetP = NULL; result = -1; switch (level) { case URI_DEPTH_OBJECT: if (tlvP[0].type == LWM2M_TYPE_OBJECT) { *targetP = tlvP; result = (int)size; } break; case URI_DEPTH_OBJECT_INSTANCE: switch (tlvP[0].type) { case LWM2M_TYPE_OBJECT: for (index = 0; index < size; index++) { if (tlvP[index].id == uriP->objectId) { return prv_findAndCheckData(uriP, level, tlvP[index].value.asChildren.count, tlvP[index].value.asChildren.array, targetP); } } break; case LWM2M_TYPE_OBJECT_INSTANCE: *targetP = tlvP; result = (int)size; break; default: break; } break; case URI_DEPTH_RESOURCE: switch (tlvP[0].type) { case LWM2M_TYPE_OBJECT: for (index = 0; index < size; index++) { if (tlvP[index].id == uriP->objectId) { return prv_findAndCheckData(uriP, level, tlvP[index].value.asChildren.count, tlvP[index].value.asChildren.array, targetP); } } break; case LWM2M_TYPE_OBJECT_INSTANCE: for (index = 0; index < size; index++) { if (tlvP[index].id == uriP->instanceId) { return prv_findAndCheckData(uriP, level, tlvP[index].value.asChildren.count, tlvP[index].value.asChildren.array, targetP); } } break; default: *targetP = tlvP; result = (int)size; break; } break; case URI_DEPTH_RESOURCE_INSTANCE: switch (tlvP[0].type) { case LWM2M_TYPE_OBJECT: for (index = 0; index < size; index++) { if (tlvP[index].id == uriP->objectId) { return prv_findAndCheckData(uriP, level, tlvP[index].value.asChildren.count, tlvP[index].value.asChildren.array, targetP); } } break; case LWM2M_TYPE_OBJECT_INSTANCE: for (index = 0; index < size; index++) { if (tlvP[index].id == uriP->instanceId) { return prv_findAndCheckData(uriP, level, tlvP[index].value.asChildren.count, tlvP[index].value.asChildren.array, targetP); } } break; case LWM2M_TYPE_MULTIPLE_RESOURCE: for (index = 0; index < size; index++) { if (tlvP[index].id == uriP->resourceId) { return prv_findAndCheckData(uriP, level, tlvP[index].value.asChildren.count, tlvP[index].value.asChildren.array, targetP); } } break; default: *targetP = tlvP; result = (int)size; break; } break; default: break; } return result; } int json_serialize(lwm2m_uri_t *uriP, int size, lwm2m_data_t *tlvP, uint8_t **bufferP) { int index; size_t head; uint8_t bufferJSON[PRV_JSON_BUFFER_SIZE]; uint8_t baseUriStr[URI_MAX_STRING_LEN]; int baseUriLen; uri_depth_t rootLevel; int num; lwm2m_data_t *targetP; LOG_ARG("size: %d", size); LOG_URI(uriP); if (size != 0 && tlvP == NULL) return -1; baseUriLen = uri_toString(uriP, baseUriStr, URI_MAX_STRING_LEN, &rootLevel); if (baseUriLen < 0) return -1; num = prv_findAndCheckData(uriP, rootLevel, size, tlvP, &targetP); if (num < 0) return -1; while (num == 1 && (targetP->type == LWM2M_TYPE_OBJECT || targetP->type == LWM2M_TYPE_OBJECT_INSTANCE || targetP->type == LWM2M_TYPE_MULTIPLE_RESOURCE)) { int res; res = utils_intToText(targetP->id, baseUriStr + baseUriLen, URI_MAX_STRING_LEN - baseUriLen); if (res <= 0) return 0; baseUriLen += res; if (baseUriLen >= URI_MAX_STRING_LEN - 1) return 0; num = targetP->value.asChildren.count; targetP = targetP->value.asChildren.array; baseUriStr[baseUriLen] = '/'; baseUriLen++; } if (baseUriLen > 0) { memcpy(bufferJSON, JSON_BN_HEADER_1, JSON_BN_HEADER_1_SIZE); head = JSON_BN_HEADER_1_SIZE; memcpy(bufferJSON + head, baseUriStr, baseUriLen); head += baseUriLen; memcpy(bufferJSON + head, JSON_BN_HEADER_2, JSON_BN_HEADER_2_SIZE); head += JSON_BN_HEADER_2_SIZE; } else { memcpy(bufferJSON, JSON_HEADER, JSON_HEADER_SIZE); head = JSON_HEADER_SIZE; } for (index = 0 ; index < num && head < PRV_JSON_BUFFER_SIZE ; index++) { int res; res = prv_serializeData(targetP + index, NULL, 0, bufferJSON + head, PRV_JSON_BUFFER_SIZE - head); if (res < 0) return 0; head += res; } if (head + JSON_FOOTER_SIZE - 1 > PRV_JSON_BUFFER_SIZE) return 0; if (num > 0) head = head - 1; memcpy(bufferJSON + head, JSON_FOOTER, JSON_FOOTER_SIZE); head = head + JSON_FOOTER_SIZE; *bufferP = (uint8_t *)lwm2m_malloc(head); if (*bufferP == NULL) return 0; memcpy(*bufferP, bufferJSON, head); return head; } #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/liblwm2m.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Fabien Fleutot - Please refer to git log * Simon Bernard - Please refer to git log * Toby Jaffey - Please refer to git log * Pascal Rieux - Please refer to git log * *******************************************************************************/ /* Copyright (c) 2013, 2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. David Navarro */ #include "internals.h" #include "osdepends/atiny_osdep.h" #include #include #include lwm2m_context_t *lwm2m_init(void *userData) { lwm2m_context_t *contextP; LOG("Entering"); contextP = (lwm2m_context_t *)lwm2m_malloc(sizeof(lwm2m_context_t)); if (NULL != contextP) { memset(contextP, 0, sizeof(lwm2m_context_t)); contextP->userData = userData; lwm2m_rand((void *)&contextP->nextMID, sizeof(contextP->nextMID)); } return contextP; } #ifdef LWM2M_CLIENT_MODE static lwm2m_event_handler_t event_handler = NULL; void lwm2m_register_event_handler(lwm2m_event_handler_t callback) { event_handler = callback; } void lwm2m_notify_even(module_type_t type, int code, const char *arg, int arg_len) { if(event_handler != NULL) { event_handler(type, code, arg, arg_len); } } void lwm2m_deregister(lwm2m_context_t *context) { lwm2m_server_t *server = context->serverList; LOG("Entering"); while (NULL != server) { registration_deregister(context, server); server = server->next; } } static void prv_deleteServer(lwm2m_server_t *serverP, void *userData) { // TODO parse transaction and observation to remove the ones related to this server if (serverP->sessionH != NULL) { lwm2m_close_connection(serverP->sessionH, userData); } if (NULL != serverP->location) { lwm2m_free(serverP->location); } free_block1_buffer(serverP->block1Data); lwm2m_free(serverP); } static void prv_deleteServerList(lwm2m_context_t *context) { while (NULL != context->serverList) { lwm2m_server_t *server; server = context->serverList; context->serverList = server->next; prv_deleteServer(server, context->userData); } } #ifdef LWM2M_BOOTSTRAP static void prv_deleteBootstrapServer(lwm2m_server_t *serverP, void *userData) { // TODO should we free location as in prv_deleteServer ? // TODO should we parse transaction and observation to remove the ones related to this server ? if (serverP->sessionH != NULL) { lwm2m_close_connection(serverP->sessionH, userData); } free_block1_buffer(serverP->block1Data); lwm2m_free(serverP); } static void prv_deleteBootstrapServerList(lwm2m_context_t *context) { while (NULL != context->bootstrapServerList) { lwm2m_server_t *server; server = context->bootstrapServerList; context->bootstrapServerList = server->next; lwm2m_stop_striger_server_initiated_bs(server->sessionH); prv_deleteBootstrapServer(server, context->userData); } } #endif static void prv_deleteObservedList(lwm2m_context_t *contextP) { atiny_mutex_lock(contextP->observe_mutex); while (NULL != contextP->observedList) { lwm2m_observed_t *targetP; lwm2m_watcher_t *watcherP; targetP = contextP->observedList; contextP->observedList = contextP->observedList->next; lwm2m_notify_even(MODULE_URI, OBSERVE_UNSUBSCRIBE, (char *) & (targetP->uri), sizeof(targetP->uri)); for (watcherP = targetP->watcherList ; watcherP != NULL ; watcherP = watcherP->next) { if (watcherP->parameters != NULL) lwm2m_free(watcherP->parameters); } LWM2M_LIST_FREE(targetP->watcherList); lwm2m_free(targetP); } atiny_mutex_unlock(contextP->observe_mutex); } #endif void prv_deleteTransactionList(lwm2m_context_t *context) { while (NULL != context->transactionList) { lwm2m_transaction_t *transaction; transaction = context->transactionList; context->transactionList = context->transactionList->next; if (transaction->callback != NULL) { transaction->callback(transaction, NULL); } transaction_free(transaction); } } void lwm2m_close(lwm2m_context_t *contextP) { #ifdef LWM2M_CLIENT_MODE LOG("Entering"); lwm2m_deregister(contextP); prv_deleteServerList(contextP); #ifdef LWM2M_BOOTSTRAP prv_deleteBootstrapServerList(contextP); #endif prv_deleteObservedList(contextP); lwm2m_free(contextP->endpointName); //lwm2m_free(contextP->bs_server_uri); if (contextP->msisdn != NULL) { lwm2m_free(contextP->msisdn); } if (contextP->altPath != NULL) { lwm2m_free(contextP->altPath); } #endif #ifdef LWM2M_SERVER_MODE while (NULL != contextP->clientList) { lwm2m_client_t *clientP; clientP = contextP->clientList; contextP->clientList = contextP->clientList->next; registration_freeClient(clientP); } #endif prv_deleteTransactionList(contextP); lwm2m_free(contextP); } static bool prv_isBoostrpEnable(const lwm2m_context_t *contextP) { #ifdef LWM2M_BOOTSTRAP return contextP->bsCtrl.bsType != BOOTSTRAP_FACTORY; #else return false; #endif } /* BsCtrl bootstrap control is used to control the register(factory bootstrap(FBS)), client initiated bootstrap(CIBS), and server initiated bootstrap(CIBS).it try max time to register and the change to bootstrap(CIBS and SIBS) as the bs type. the state is STATE_REGISTER_REQUIRED, STATE_BOOTSTRAP_REQUIRED and STATE_NON. CIBS is only state is STATE_BOOTSTRAP_REQUIRED, ,cnt is 0 and bs type is BOOTSTRAP_SEQUENCE. cnt is used to calculte the delay for the next retry. Delay(cnt) = Base + Interval * cnt; Base and Interval are configured by different macros. */ bool lwm2m_isBsCtrlInServerInitiatedBs(const lwm2m_context_t *contextP) { return (contextP->bsCtrl.bsType == BOOTSTRAP_SEQUENCE) && (contextP->bsCtrl.cnt == 0); } void lwm2m_initBsCtrlStat(lwm2m_context_t *contextP, lwm2m_bootstrap_type_e bs_type) { memset(&contextP->bsCtrl, 0, sizeof(contextP->bsCtrl)); contextP->bsCtrl.bsType = bs_type; contextP->bsCtrl.state = STATE_INITIAL; } static void lwm2m_setBsCtrlStatWithoutCheck(lwm2m_context_t *contextP, lwm2m_client_state_t state) { if (contextP->bsCtrl.state != state) { contextP->bsCtrl.state = state; contextP->bsCtrl.cnt = 0; return; } { uint32_t maxValue = ((STATE_REGISTER_REQUIRED == state) ? MAX_FACTORY_BS_RETRY_CNT : MAX_CLIENT_INITIATED_BS_RETRY_CNT); if ((STATE_BOOTSTRAP_REQUIRED == state) && (BOOTSTRAP_SEQUENCE == contextP->bsCtrl.bsType)) { maxValue++; } if(++(contextP->bsCtrl.cnt) >= maxValue) { contextP->bsCtrl.state = ((STATE_REGISTER_REQUIRED == contextP->bsCtrl.state) ? STATE_BOOTSTRAP_REQUIRED :STATE_REGISTER_REQUIRED); contextP->bsCtrl.cnt = 0; } } } void lwm2m_setBsCtrlStat(lwm2m_context_t *contextP, lwm2m_client_state_t state) { lwm2m_client_state_t oldState = contextP->bsCtrl.state; uint32_t oldCnt = contextP->bsCtrl.cnt; lwm2m_setBsCtrlStatWithoutCheck(contextP, state); if (STATE_REGISTER_REQUIRED == contextP->bsCtrl.state) { if (contextP->serverList == NULL) { contextP->bsCtrl.state = STATE_BOOTSTRAP_REQUIRED; contextP->bsCtrl.cnt = 0; } } if (STATE_BOOTSTRAP_REQUIRED == contextP->bsCtrl.state) { if ((!prv_isBoostrpEnable(contextP)) || (contextP->bootstrapServerList == NULL)) { contextP->bsCtrl.state = STATE_REGISTER_REQUIRED; contextP->bsCtrl.cnt = 0; goto END; } // bootstrapServerList not empty, int CIBS but bs ip not valid. if((!lwm2m_isBsCtrlInServerInitiatedBs(contextP)) #if defined(LWM2M_BOOTSTRAP) && (!bootstrap_isBsServerIpValid(contextP)) #endif ) { //FBS if (contextP->serverList) { contextP->bsCtrl.state = STATE_REGISTER_REQUIRED; contextP->bsCtrl.cnt = 0; } // only in SIBS else if ((contextP->serverList == NULL) && (contextP->bsCtrl.bsType == BOOTSTRAP_SEQUENCE)) { contextP->bsCtrl.cnt = 0; } else { } } } END: if ((oldState != contextP->bsCtrl.state) || (oldCnt != contextP->bsCtrl.cnt)) { LOG_ARG("bsctrlstat (%d,%d) to (%d,%d)", oldState, oldCnt, contextP->bsCtrl.state, contextP->bsCtrl.cnt); } } static void lwm2m_delayBsRetry(lwm2m_context_t *contextP) { uint32_t delayBase; uint32_t delayInterval; uint32_t cnt = contextP->bsCtrl.cnt; uint32_t expireTime; if (contextP->bsCtrl.state == STATE_REGISTER_REQUIRED) { delayBase = FACTORY_BS_DELAY_BASE; delayInterval = FACTORY_BS_DELAY_INTERVAL; } else { delayBase = CLIENT_INITIATED_BS_DELAY_BASE; delayInterval = CLIENT_INITIATED_BS_DELAY_INTERVAL; if ((contextP->bsCtrl.bsType == BOOTSTRAP_SEQUENCE) && (cnt > 0)) { cnt--; } } expireTime = delayBase + delayInterval * cnt; if (expireTime > 0) { lwm2m_delay(expireTime); } } lwm2m_client_state_t lwm2m_getBsCtrlStat(const lwm2m_context_t *contextP) { return contextP->bsCtrl.state; } #ifdef LWM2M_CLIENT_MODE static int prv_refreshServerList(lwm2m_context_t *contextP) { lwm2m_server_t *targetP; lwm2m_server_t *nextP; // Remove all servers marked as dirty targetP = contextP->bootstrapServerList; contextP->bootstrapServerList = NULL; while (targetP != NULL) { nextP = targetP->next; targetP->next = NULL; if (!targetP->dirty) { targetP->status = STATE_DEREGISTERED; contextP->bootstrapServerList = (lwm2m_server_t *)LWM2M_LIST_ADD(contextP->bootstrapServerList, targetP); } else { prv_deleteServer(targetP, contextP->userData); } targetP = nextP; } targetP = contextP->serverList; contextP->serverList = NULL; while (targetP != NULL) { nextP = targetP->next; targetP->next = NULL; if (!targetP->dirty) { // TODO: Should we revert the status to STATE_DEREGISTERED ? contextP->serverList = (lwm2m_server_t *)LWM2M_LIST_ADD(contextP->serverList, targetP); } else { prv_deleteServer(targetP, contextP->userData); } targetP = nextP; } return object_getServers(contextP, false); } //result = lwm2m_configure(lwm2mH, name, NULL, NULL, OBJ_COUNT, objArray) int lwm2m_configure(lwm2m_context_t *contextP, const char *endpointName, const char *msisdn, const char *altPath, uint16_t numObject, lwm2m_object_t *objectList[]) { int i; uint8_t found; //LOG_ARG("endpointName: \"%s\", msisdn: \"%s\", altPath: \"%s\", numObject: %d", endpointName, msisdn, altPath, numObject); // This API can be called only once for now if (contextP->endpointName != NULL || contextP->objectList != NULL) return COAP_400_BAD_REQUEST; if (endpointName == NULL) return COAP_400_BAD_REQUEST; if (numObject < 3) return COAP_400_BAD_REQUEST; // Check that mandatory objects are present found = 0; for (i = 0 ; i < numObject ; i++) { if(objectList[i] == NULL) // happens when undef CONFIG_FEATURE_FOTA continue; if (objectList[i]->objID == LWM2M_SECURITY_OBJECT_ID) found |= 0x01; if (objectList[i]->objID == LWM2M_SERVER_OBJECT_ID) found |= 0x02; if (objectList[i]->objID == LWM2M_DEVICE_OBJECT_ID) found |= 0x04; } if (found != 0x07) return COAP_400_BAD_REQUEST; if (altPath != NULL) { if (0 == utils_isAltPathValid(altPath)) { return COAP_400_BAD_REQUEST; } if (altPath[1] == 0) { altPath = NULL; } } contextP->endpointName = lwm2m_strdup(endpointName); if (contextP->endpointName == NULL) { return COAP_500_INTERNAL_SERVER_ERROR; } if (msisdn != NULL) { contextP->msisdn = lwm2m_strdup(msisdn); if (contextP->msisdn == NULL) { return COAP_500_INTERNAL_SERVER_ERROR; } } if (altPath != NULL) { contextP->altPath = lwm2m_strdup(altPath); if (contextP->altPath == NULL) { return COAP_500_INTERNAL_SERVER_ERROR; } } for (i = 0; i < numObject; i++) { if(objectList[i] == NULL) // happens when undef CONFIG_FEATURE_FOTA continue; objectList[i]->next = NULL; contextP->objectList = (lwm2m_object_t *)LWM2M_LIST_ADD(contextP->objectList, objectList[i]); } return COAP_NO_ERROR; } int lwm2m_add_object(lwm2m_context_t *contextP, lwm2m_object_t *objectP) { lwm2m_object_t *targetP; LOG_ARG("ID: %d", objectP->objID); targetP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, objectP->objID); if (targetP != NULL) return COAP_406_NOT_ACCEPTABLE; objectP->next = NULL; contextP->objectList = (lwm2m_object_t *)LWM2M_LIST_ADD(contextP->objectList, objectP); if (contextP->state == STATE_READY) { return lwm2m_update_registration(contextP, 0, true); } return COAP_NO_ERROR; } int lwm2m_remove_object(lwm2m_context_t *contextP, uint16_t id) { lwm2m_object_t *targetP; LOG_ARG("ID: %d", id); contextP->objectList = (lwm2m_object_t *)LWM2M_LIST_RM(contextP->objectList, id, &targetP); if (targetP == NULL) return COAP_404_NOT_FOUND; if (contextP->state == STATE_READY) { return lwm2m_update_registration(contextP, 0, true); } return 0; } static void lwm2m_reset_register(lwm2m_context_t *context) { lwm2m_server_t *server = context->serverList; LOG("Entering"); while (NULL != server) { registration_reset(context, server); server = server->next; } } int lwm2m_reconnect(lwm2m_context_t *context) { if(NULL == context) { LOG("context null point"); return COAP_405_METHOD_NOT_ALLOWED; } lwm2m_reset_register(context); prv_deleteObservedList(context); prv_deleteTransactionList(context); lwm2m_setBsCtrlStat(context, STATE_REGISTER_REQUIRED); context->state = lwm2m_getBsCtrlStat(context); lwm2m_notify_even(MODULE_LWM2M, STATE_REG_FAILED, NULL, 0); return COAP_NO_ERROR; } int lwm2m_initBootStrap(lwm2m_context_t *contextP, lwm2m_bootstrap_type_e bsType) { if (NULL == contextP) { LOG("context null point"); return COAP_500_INTERNAL_SERVER_ERROR; } contextP->regist_first_flag = ((bsType == BOOTSTRAP_CLIENT_INITIATED) ? false : true); lwm2m_initBsCtrlStat(contextP, bsType); return COAP_NO_ERROR; } #endif #define SET_BS_LATER(contextP, newState) \ do{\ lwm2m_setBsCtrlStat(contextP, newState);\ contextP->state = lwm2m_getBsCtrlStat(contextP);\ lwm2m_delayBsRetry(contextP);\ }while(0) int lwm2m_step(lwm2m_context_t *contextP, time_t *timeoutP) { time_t tv_sec; int result; lwm2m_client_state_t state; int ret = 0; LOG_ARG("timeoutP: %" PRId64, *timeoutP); tv_sec = lwm2m_gettime(); //if (tv_sec < 0) return COAP_500_INTERNAL_SERVER_ERROR; #ifdef LWM2M_CLIENT_MODE LOG_ARG("State: %s", STR_STATE(contextP->state)); // state can also be modified in bootstrap_handleCommand(). next_step: switch (contextP->state) { case STATE_INITIAL: if (0 != prv_refreshServerList(contextP)) { LOG("prv_refreshServerList fail"); return COAP_503_SERVICE_UNAVAILABLE; } state = ((!prv_isBoostrpEnable(contextP)) || ((contextP->serverList != NULL) && contextP->regist_first_flag) ? STATE_REGISTER_REQUIRED : STATE_BOOTSTRAP_REQUIRED); contextP->regist_first_flag = true; SET_BS_LATER(contextP, state); goto next_step; //break; case STATE_BOOTSTRAP_REQUIRED: #ifdef LWM2M_BOOTSTRAP if (contextP->bootstrapServerList != NULL) { bootstrap_start(contextP); contextP->state = STATE_BOOTSTRAPPING; bootstrap_step(contextP, tv_sec, timeoutP); break; } else #endif { SET_BS_LATER(contextP, STATE_BOOTSTRAP_REQUIRED); ret = COAP_503_SERVICE_UNAVAILABLE; break; } #ifdef LWM2M_BOOTSTRAP case STATE_BOOTSTRAPPING: switch (bootstrap_getStatus(contextP)) { case STATE_BS_FINISHED: contextP->state = STATE_INITIAL; lwm2m_setBsCtrlStat(contextP, STATE_INITIAL); goto next_step; break; case STATE_BS_FAILED: SET_BS_LATER(contextP, STATE_BOOTSTRAP_REQUIRED); ret = COAP_503_SERVICE_UNAVAILABLE; break; default: // keep on waiting bootstrap_step(contextP, tv_sec, timeoutP); break; } break; #endif case STATE_REGISTER_REQUIRED: result = registration_start(contextP); LOG_ARG("[bootstrap_tag]: ---the return value result = %d of registration_start-----", result); if (COAP_NO_ERROR != result) { SET_BS_LATER(contextP, STATE_REGISTER_REQUIRED); ret = result; break; } contextP->state = STATE_REGISTERING; break; case STATE_REGISTERING: { switch (registration_getStatus(contextP)) { case STATE_REGISTERED: contextP->state = STATE_READY; lwm2m_notify_even(MODULE_LWM2M, STATE_REGISTERED, NULL, 0); lwm2m_setBsCtrlStat(contextP, STATE_INITIAL); break; case STATE_REG_FAILED: // TODO avoid infinite loop by checking the bootstrap info is different //contextP->state = STATE_BOOTSTRAP_REQUIRED; lwm2m_notify_even(MODULE_LWM2M,STATE_REG_FAILED, NULL, 0); SET_BS_LATER(contextP, STATE_REGISTER_REQUIRED); break; case STATE_REG_PENDING: default: // keep on waiting break; } } break; case STATE_READY: if (registration_getStatus(contextP) == STATE_REG_FAILED) { // TODO avoid infinite loop by checking the bootstrap info is different //contextP->state = STATE_BOOTSTRAP_REQUIRED; contextP->state = STATE_REGISTER_REQUIRED; lwm2m_setBsCtrlStat(contextP, STATE_REGISTER_REQUIRED); goto next_step; // break; } break; default: // do nothing break; } observe_step(contextP, tv_sec, timeoutP); #endif registration_step(contextP, tv_sec, timeoutP); transaction_step(contextP, tv_sec, timeoutP); LOG_ARG("Final timeoutP: %" PRId64, *timeoutP); #ifdef LWM2M_CLIENT_MODE LOG_ARG("Final state: %s", STR_STATE(contextP->state)); #endif return ret; } ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/liblwm2m.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Fabien Fleutot - Please refer to git log * Simon Bernard - Please refer to git log * Toby Jaffey - Please refer to git log * Julien Vermillard - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - Please refer to git log * Ville Skyttä - Please refer to git log * *******************************************************************************/ /* Copyright (c) 2013, 2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. David Navarro */ #ifndef _LWM2M_CLIENT_H_ #define _LWM2M_CLIENT_H_ #include "liblwm2m_api.h" #ifdef __cplusplus extern "C" { #endif #include #include #include #include #include "er-coap-13/er-coap-13.h" #include "osdepends/atiny_osdep.h" #ifdef LWM2M_SERVER_MODE #ifndef LWM2M_SUPPORT_JSON #define LWM2M_SUPPORT_JSON #endif #endif #if defined(LWM2M_BOOTSTRAP) && defined(LWM2M_BOOTSTRAP_SERVER_MODE) #error "LWM2M_BOOTSTRAP and LWM2M_BOOTSTRAP_SERVER_MODE cannot be defined at the same time!" #endif /* * Platform abstraction functions to be implemented by the user */ #ifndef LWM2M_MEMORY_TRACE // Allocate a block of size bytes of memory, returning a pointer to the beginning of the block. void* lwm2m_malloc(size_t s); // Deallocate a block of memory previously allocated by lwm2m_malloc() or lwm2m_strdup() void lwm2m_free(void* p); // Allocate a memory block, duplicate the string str in it and return a pointer to this new block. char* lwm2m_strdup(const char* str); #else // same functions as above with caller location for debugging purposes char* lwm2m_trace_strdup(const char* str, const char* file, const char* function, int lineno); void* lwm2m_trace_malloc(size_t size, const char* file, const char* function, int lineno); void lwm2m_trace_free(void* mem, const char* file, const char* function, int lineno); #define lwm2m_strdup(S) lwm2m_trace_strdup(S, __FILE__, __FUNCTION__, __LINE__) #define lwm2m_malloc(S) lwm2m_trace_malloc(S, __FILE__, __FUNCTION__, __LINE__) #define lwm2m_free(M) lwm2m_trace_free(M, __FILE__, __FUNCTION__, __LINE__) #endif // Compare at most the n first bytes of s1 and s2, return 0 if they match int lwm2m_strncmp(const char* s1, const char* s2, size_t n); // This function must return the number of seconds elapsed since origin. // The origin (Epoch, system boot, etc...) does not matter as this // function is used only to determine the elapsed time since the last // call to it. // In case of error, this must return a negative value. // Per POSIX specifications, time_t is a signed integer. time_t lwm2m_gettime(void); //get len of random bytes in output. int lwm2m_rand(void *output, size_t len); //delay sometime void lwm2m_delay(uint32_t second); //#define LWM2M_WITH_LOGS #ifdef LWM2M_WITH_LOGS // Same usage as C89 printf() #define lwm2m_printf atiny_printf #endif // communication layer #ifdef LWM2M_CLIENT_MODE // Returns a session handle that MUST uniquely identify a peer. // secObjInstID: ID of the Securty Object instance to open a connection to // userData: parameter to lwm2m_init() // bootstrap_flag: If BootstrapServer void *lwm2m_connect_server(uint16_t secObjInstID, void *userData, bool isServer); // Close a session created by lwm2m_connect_server() // sessionH: session handle identifying the peer (opaque to the core) // userData: parameter to lwm2m_init() void lwm2m_close_connection(void* sessionH, void* userData); #endif // Send data to a peer // Returns COAP_NO_ERROR or a COAP_NNN error code // sessionH: session handle identifying the peer (opaque to the core) // buffer, length: data to send // userData: parameter to lwm2m_init() uint8_t lwm2m_buffer_send(void* sessionH, uint8_t* buffer, size_t length, void* userdata); // Compare two session handles // Returns true if the two sessions identify the same peer. false otherwise. // userData: parameter to lwm2m_init() bool lwm2m_session_is_equal(void* session1, void* session2, void* userData); /* * Error code */ #define COAP_NO_ERROR (uint8_t)0x00 #define COAP_IGNORE (uint8_t)0x01 #define COAP_201_CREATED (uint8_t)0x41 #define COAP_202_DELETED (uint8_t)0x42 #define COAP_204_CHANGED (uint8_t)0x44 #define COAP_205_CONTENT (uint8_t)0x45 #define COAP_231_CONTINUE (uint8_t)0x5F #define COAP_400_BAD_REQUEST (uint8_t)0x80 #define COAP_401_UNAUTHORIZED (uint8_t)0x81 #define COAP_402_BAD_OPTION (uint8_t)0x82 #define COAP_404_NOT_FOUND (uint8_t)0x84 #define COAP_405_METHOD_NOT_ALLOWED (uint8_t)0x85 #define COAP_406_NOT_ACCEPTABLE (uint8_t)0x86 #define COAP_408_REQ_ENTITY_INCOMPLETE (uint8_t)0x88 #define COAP_412_PRECONDITION_FAILED (uint8_t)0x8C #define COAP_413_ENTITY_TOO_LARGE (uint8_t)0x8D #define COAP_500_INTERNAL_SERVER_ERROR (uint8_t)0xA0 #define COAP_501_NOT_IMPLEMENTED (uint8_t)0xA1 #define COAP_503_SERVICE_UNAVAILABLE (uint8_t)0xA3 /* * Standard Object IDs */ #define LWM2M_SECURITY_OBJECT_ID 0 #define LWM2M_SERVER_OBJECT_ID 1 #define LWM2M_ACL_OBJECT_ID 2 #define LWM2M_DEVICE_OBJECT_ID 3 #define LWM2M_CONN_MONITOR_OBJECT_ID 4 #define LWM2M_FIRMWARE_UPDATE_OBJECT_ID 5 #define LWM2M_LOCATION_OBJECT_ID 6 #define LWM2M_CONN_STATS_OBJECT_ID 7 /* * Resource IDs for the LWM2M Security Object */ #define LWM2M_SECURITY_URI_ID 0 #define LWM2M_SECURITY_BOOTSTRAP_ID 1 #define LWM2M_SECURITY_SECURITY_ID 2 #define LWM2M_SECURITY_PUBLIC_KEY_ID 3 #define LWM2M_SECURITY_SERVER_PUBLIC_KEY_ID 4 #define LWM2M_SECURITY_SECRET_KEY_ID 5 #define LWM2M_SECURITY_SMS_SECURITY_ID 6 #define LWM2M_SECURITY_SMS_KEY_PARAM_ID 7 #define LWM2M_SECURITY_SMS_SECRET_KEY_ID 8 #define LWM2M_SECURITY_SMS_SERVER_NUMBER_ID 9 #define LWM2M_SECURITY_SHORT_SERVER_ID 10 #define LWM2M_SECURITY_HOLD_OFF_ID 11 #define LWM2M_SECURITY_BOOTSTRAP_TIMEOUT_ID 12 /* * Resource IDs for the LWM2M Server Object */ #define LWM2M_SERVER_SHORT_ID_ID 0 #define LWM2M_SERVER_LIFETIME_ID 1 #define LWM2M_SERVER_MIN_PERIOD_ID 2 #define LWM2M_SERVER_MAX_PERIOD_ID 3 #define LWM2M_SERVER_DISABLE_ID 4 #define LWM2M_SERVER_TIMEOUT_ID 5 #define LWM2M_SERVER_STORING_ID 6 #define LWM2M_SERVER_BINDING_ID 7 #define LWM2M_SERVER_UPDATE_ID 8 #define LWM2M_SECURITY_MODE_PRE_SHARED_KEY 0 #define LWM2M_SECURITY_MODE_RAW_PUBLIC_KEY 1 #define LWM2M_SECURITY_MODE_CERTIFICATE 2 #define LWM2M_SECURITY_MODE_NONE 3 #define LWM2M_TRIGER_SERVER_MODE_INITIATED_TIME 60 #define MAX_FACTORY_BS_RETRY_CNT 3 #define MAX_CLIENT_INITIATED_BS_RETRY_CNT 3 #define FACTORY_BS_DELAY_BASE 0 #define CLIENT_INITIATED_BS_DELAY_BASE 0 #define FACTORY_BS_DELAY_INTERVAL 10 #define CLIENT_INITIATED_BS_DELAY_INTERVAL 10 /* * Utility functions for sorted linked list */ typedef struct _lwm2m_list_t { struct _lwm2m_list_t* next; uint16_t id; } lwm2m_list_t; // defined in list.c // Add 'node' to the list 'head' and return the new list lwm2m_list_t* lwm2m_list_add(lwm2m_list_t* head, lwm2m_list_t* node); // Return the node with ID 'id' from the list 'head' or NULL if not found lwm2m_list_t* lwm2m_list_find(lwm2m_list_t* head, uint16_t id); // Remove the node with ID 'id' from the list 'head' and return the new list lwm2m_list_t* lwm2m_list_remove(lwm2m_list_t* head, uint16_t id, lwm2m_list_t** nodeP); // Return the lowest unused ID in the list 'head' uint16_t lwm2m_list_newId(lwm2m_list_t* head); // Free a list. Do not use if nodes contain allocated pointers as it calls lwm2m_free on nodes only. // If the nodes of the list need to do more than just "free()" their instances, don't use lwm2m_list_free(). void lwm2m_list_free(lwm2m_list_t* head); #define LWM2M_LIST_ADD(H,N) lwm2m_list_add((lwm2m_list_t *)H, (lwm2m_list_t *)N); #define LWM2M_LIST_RM(H,I,N) lwm2m_list_remove((lwm2m_list_t *)H, I, (lwm2m_list_t **)N); #define LWM2M_LIST_FIND(H,I) lwm2m_list_find((lwm2m_list_t *)H, I) #define LWM2M_LIST_FREE(H) lwm2m_list_free((lwm2m_list_t *)H) /* * URI * * objectId is always set * instanceId or resourceId are set according to the flag bit-field * */ #define LWM2M_MAX_ID ((uint16_t)0xFFFF) #define LWM2M_URI_FLAG_OBJECT_ID (uint8_t)0x04 #define LWM2M_URI_FLAG_INSTANCE_ID (uint8_t)0x02 #define LWM2M_URI_FLAG_RESOURCE_ID (uint8_t)0x01 #define LWM2M_URI_IS_SET_INSTANCE(uri) (((uri)->flag & LWM2M_URI_FLAG_INSTANCE_ID) != 0) #define LWM2M_URI_IS_SET_RESOURCE(uri) (((uri)->flag & LWM2M_URI_FLAG_RESOURCE_ID) != 0) typedef struct { uint8_t flag; // indicates which segments are set uint16_t objectId; uint16_t instanceId; uint16_t resourceId; } lwm2m_uri_t; #define LWM2M_STRING_ID_MAX_LEN 6 // Parse an URI in LWM2M format and fill the lwm2m_uri_t. // Return the number of characters read from buffer or 0 in case of error. // Valid URIs: /1, /1/, /1/2, /1/2/, /1/2/3 // Invalid URIs: /, //, //2, /1//, /1//3, /1/2/3/, /1/2/3/4 int lwm2m_stringToUri(const char* buffer, size_t buffer_len, lwm2m_uri_t* uriP); /* * The lwm2m_data_t is used to store LWM2M resource values in a hierarchical way. * Depending on the type the value is different: * - LWM2M_TYPE_OBJECT, LWM2M_TYPE_OBJECT_INSTANCE, LWM2M_TYPE_MULTIPLE_RESOURCE: value.asChildren * - LWM2M_TYPE_STRING, LWM2M_TYPE_OPAQUE: value.asBuffer * - LWM2M_TYPE_INTEGER, LWM2M_TYPE_TIME: value.asInteger * - LWM2M_TYPE_FLOAT: value.asFloat * - LWM2M_TYPE_BOOLEAN: value.asBoolean * * LWM2M_TYPE_STRING is also used when the data is in text format. */ typedef enum { LWM2M_TYPE_UNDEFINED = 0, LWM2M_TYPE_OBJECT, LWM2M_TYPE_OBJECT_INSTANCE, LWM2M_TYPE_MULTIPLE_RESOURCE, LWM2M_TYPE_STRING, LWM2M_TYPE_OPAQUE, LWM2M_TYPE_INTEGER, LWM2M_TYPE_FLOAT, LWM2M_TYPE_BOOLEAN, LWM2M_TYPE_OBJECT_LINK } lwm2m_data_type_t; typedef struct _lwm2m_data_t lwm2m_data_t; struct _lwm2m_data_t { lwm2m_data_type_t type; uint16_t id; union { bool asBoolean; int64_t asInteger; double asFloat; struct { size_t length; uint8_t* buffer; } asBuffer; struct { size_t count; lwm2m_data_t* array; } asChildren; struct { uint16_t objectId; uint16_t objectInstanceId; } asObjLink; } value; }; typedef void (*lwm2m_data_process) (void*); typedef struct _lwm2m_data_cfg_t { int type; /*Êý¾ÝÉϱ¨ÀàÐÍ*/ int cookie; /*Êý¾Ýcookie,ÓÃÒÔÔÚack»Øµ÷ÖУ¬Çø·Ö²»Í¬µÄÊý¾Ý*/ lwm2m_data_process callback; /*ack»Øµ÷*/ } lwm2m_data_cfg_t; typedef enum { LWM2M_CONTENT_TEXT = 0, // Also used as undefined LWM2M_CONTENT_LINK = 40, LWM2M_CONTENT_OPAQUE = 42, LWM2M_CONTENT_TLV_OLD = 1542, // Keep old value for backward-compatibility LWM2M_CONTENT_TLV = 11542, LWM2M_CONTENT_JSON_OLD = 1543, // Keep old value for backward-compatibility LWM2M_CONTENT_JSON = 11543 } lwm2m_media_type_t; lwm2m_data_t* lwm2m_data_new(int size); int lwm2m_data_parse(lwm2m_uri_t* uriP, uint8_t* buffer, size_t bufferLen, lwm2m_media_type_t format, lwm2m_data_t** dataP); int lwm2m_data_serialize(lwm2m_uri_t* uriP, int size, lwm2m_data_t* dataP, lwm2m_media_type_t* formatP, uint8_t** bufferP); void lwm2m_data_free(int size, lwm2m_data_t* dataP); void lwm2m_data_decode_opaque(const lwm2m_data_t* dataP, int8_t* valueP); void lwm2m_data_encode_string(const char* string, lwm2m_data_t* dataP); void lwm2m_data_encode_nstring(const char* string, size_t length, lwm2m_data_t* dataP); void lwm2m_data_encode_opaque(uint8_t* buffer, size_t length, lwm2m_data_t* dataP); void lwm2m_data_encode_int(int64_t value, lwm2m_data_t* dataP); int lwm2m_data_decode_int(const lwm2m_data_t* dataP, int64_t* valueP); void lwm2m_data_encode_float(double value, lwm2m_data_t* dataP); int lwm2m_data_decode_float(const lwm2m_data_t* dataP, double* valueP); void lwm2m_data_encode_bool(bool value, lwm2m_data_t* dataP); int lwm2m_data_decode_bool(const lwm2m_data_t* dataP, bool* valueP); void lwm2m_data_encode_objlink(uint16_t objectId, uint16_t objectInstanceId, lwm2m_data_t* dataP); void lwm2m_data_encode_instances(lwm2m_data_t* subDataP, size_t count, lwm2m_data_t* dataP); void lwm2m_data_include(lwm2m_data_t* subDataP, size_t count, lwm2m_data_t* dataP); /* * Utility function to parse TLV buffers directly * * Returned value: number of bytes parsed * buffer: buffer to parse * buffer_len: length in bytes of buffer * oType: (OUT) type of the parsed TLV record. can be: * - LWM2M_TYPE_OBJECT * - LWM2M_TYPE_OBJECT_INSTANCE * - LWM2M_TYPE_MULTIPLE_RESOURCE * - LWM2M_TYPE_OPAQUE * oID: (OUT) ID of the parsed TLV record * oDataIndex: (OUT) index of the data of the parsed TLV record in the buffer * oDataLen: (OUT) length of the data of the parsed TLV record */ #define LWM2M_TLV_HEADER_MAX_LENGTH 6 int lwm2m_decode_TLV(const uint8_t* buffer, size_t buffer_len, lwm2m_data_type_t* oType, uint16_t* oID, size_t* oDataIndex, size_t* oDataLen); /* * LWM2M Objects * * For the read callback, if *numDataP is not zero, *dataArrayP is pre-allocated * and contains the list of resources to read. * */ typedef struct _lwm2m_object_t lwm2m_object_t; typedef uint8_t (*lwm2m_read_callback_t) (uint16_t instanceId, int* numDataP, lwm2m_data_t** dataArrayP, lwm2m_data_cfg_t* dataCfg, lwm2m_object_t* objectP); typedef uint8_t (*lwm2m_discover_callback_t) (uint16_t instanceId, int* numDataP, lwm2m_data_t** dataArrayP, lwm2m_object_t* objectP); typedef uint8_t (*lwm2m_write_callback_t) (uint16_t instanceId, int numData, lwm2m_data_t* dataArray, lwm2m_object_t* objectP); typedef uint8_t (*lwm2m_execute_callback_t) (uint16_t instanceId, uint16_t resourceId, uint8_t* buffer, int length, lwm2m_object_t* objectP); typedef uint8_t (*lwm2m_create_callback_t) (uint16_t instanceId, int numData, lwm2m_data_t* dataArray, lwm2m_object_t* objectP); typedef uint8_t (*lwm2m_delete_callback_t) (uint16_t instanceId, lwm2m_object_t* objectP); typedef uint8_t (*lwm2m_change_callback_t) (uint16_t instanceId, uint8_t* buffer, int length, lwm2m_object_t* objectP); struct _lwm2m_object_t { struct _lwm2m_object_t* next; // for internal use only. uint16_t objID; lwm2m_list_t* instanceList; lwm2m_read_callback_t readFunc; lwm2m_write_callback_t writeFunc; lwm2m_execute_callback_t executeFunc; lwm2m_change_callback_t change; lwm2m_create_callback_t createFunc; lwm2m_delete_callback_t deleteFunc; lwm2m_discover_callback_t discoverFunc; void* userData; }; /* * LWM2M Servers * * Since LWM2M Server Object instances are not accessible to LWM2M servers, * there is no need to store them as lwm2m_objects_t */ typedef enum { STATE_DEREGISTERED = 0, // not registered or boostrap not started STATE_REG_PENDING, // registration pending STATE_REGISTERED, // successfully registered STATE_REG_FAILED, // last registration failed STATE_REG_UPDATE_PENDING, // registration update pending STATE_REG_UPDATE_NEEDED, // registration update required STATE_REG_FULL_UPDATE_NEEDED, // registration update with objects required STATE_DEREG_PENDING, // deregistration pending STATE_BS_HOLD_OFF, // bootstrap hold off time STATE_BS_INITIATED, // bootstrap request sent STATE_BS_PENDING, // boostrap ongoing STATE_BS_FINISHING, // boostrap finish received STATE_BS_FINISHED, // bootstrap done STATE_BS_FAILING, // bootstrap error occurred STATE_BS_FAILED, // bootstrap failed } lwm2m_status_t; typedef enum { BINDING_UNKNOWN = 0, BINDING_U, // UDP BINDING_UQ, // UDP queue mode BINDING_S, // SMS BINDING_SQ, // SMS queue mode BINDING_US, // UDP plus SMS BINDING_UQS // UDP queue mode plus SMS } lwm2m_binding_t; typedef enum { MODULE_LWM2M, MODULE_NET, MODULE_URI, }module_type_t; enum { OBSERVE_UNSUBSCRIBE, OBSERVE_SUBSCRIBE, }; /* * LWM2M block1 data * * Temporary data needed to handle block1 request. * Currently support only one block1 request by server. */ typedef struct _lwm2m_block1_data_ lwm2m_block1_data_t; struct _lwm2m_block1_data_ { uint8_t* block1buffer; // data buffer size_t block1bufferSize; // buffer size uint16_t lastmid; // mid of the last message received }; typedef struct _lwm2m_server_ { struct _lwm2m_server_* next; // matches lwm2m_list_t::next uint16_t secObjInstID; // matches lwm2m_list_t::id uint16_t shortID; // servers short ID, may be 0 for bootstrap server time_t lifetime; // lifetime of the registration in sec or 0 if default value (86400 sec), also used as hold off time for bootstrap servers time_t registration; // date of the last registration in sec or end of client hold off time for bootstrap servers lwm2m_binding_t binding; // client connection mode with this server void* sessionH; lwm2m_status_t status; char* location; bool dirty; lwm2m_block1_data_t* block1Data; // buffer to handle block1 data, should be replace by a list to support several block1 transfer by server. } lwm2m_server_t; /* * LWM2M result callback * * When used with an observe, if 'data' is not nil, 'status' holds the observe counter. */ typedef void (*lwm2m_result_callback_t) (uint16_t clientID, lwm2m_uri_t* uriP, int status, lwm2m_media_type_t format, uint8_t* data, int dataLength, void* userData); /* * LWM2M Observations * * Used to store observation of remote clients resources. * status STATE_REG_PENDING means the observe request was sent to the client but not yet answered. * status STATE_REGISTERED means the client acknowledged the observe request. * status STATE_DEREG_PENDING means the user canceled the request before the client answered it. */ typedef struct _lwm2m_observation_ { struct _lwm2m_observation_* next; // matches lwm2m_list_t::next uint16_t id; // matches lwm2m_list_t::id struct _lwm2m_client_* clientP; lwm2m_uri_t uri; lwm2m_status_t status; lwm2m_result_callback_t callback; void* userData; } lwm2m_observation_t; /* * LWM2M Link Attributes * * Used for observation parameters. * */ #define LWM2M_ATTR_FLAG_MIN_PERIOD (uint8_t)0x01 #define LWM2M_ATTR_FLAG_MAX_PERIOD (uint8_t)0x02 #define LWM2M_ATTR_FLAG_GREATER_THAN (uint8_t)0x04 #define LWM2M_ATTR_FLAG_LESS_THAN (uint8_t)0x08 #define LWM2M_ATTR_FLAG_STEP (uint8_t)0x10 typedef struct { uint8_t toSet; uint8_t toClear; uint32_t minPeriod; uint32_t maxPeriod; double greaterThan; double lessThan; double step; } lwm2m_attributes_t; /* * LWM2M Clients * * Be careful not to mix lwm2m_client_object_t used to store list of objects of remote clients * and lwm2m_object_t describing objects exposed to remote servers. * */ typedef struct _lwm2m_client_object_ { struct _lwm2m_client_object_* next; // matches lwm2m_list_t::next uint16_t id; // matches lwm2m_list_t::id lwm2m_list_t* instanceList; } lwm2m_client_object_t; typedef struct _lwm2m_client_ { struct _lwm2m_client_* next; // matches lwm2m_list_t::next uint16_t internalID; // matches lwm2m_list_t::id char* name; lwm2m_binding_t binding; char* msisdn; char* altPath; bool supportJSON; uint32_t lifetime; time_t endOfLife; void* sessionH; lwm2m_client_object_t* objectList; lwm2m_observation_t* observationList; } lwm2m_client_t; /* * LWM2M transaction * * Adaptation of Erbium's coap_transaction_t */ typedef struct _lwm2m_transaction_ lwm2m_transaction_t; typedef void (*lwm2m_transaction_callback_t) (lwm2m_transaction_t* transacP, void* message); struct _lwm2m_transaction_ { lwm2m_transaction_t* next; // matches lwm2m_list_t::next uint16_t mID; // matches lwm2m_list_t::id void* peerH; uint8_t ack_received; // indicates, that the ACK was received time_t response_timeout; // timeout to wait for response, if token is used. When 0, use calculated acknowledge timeout. uint8_t retrans_counter; time_t retrans_time; coap_packet_t* message; uint16_t buffer_len; uint8_t* buffer; lwm2m_data_cfg_t cfg; lwm2m_transaction_callback_t callback; void* userData; }; /* * LWM2M observed resources */ typedef struct _lwm2m_watcher_ { struct _lwm2m_watcher_* next; bool active; bool update; lwm2m_server_t* server; lwm2m_attributes_t* parameters; lwm2m_media_type_t format; uint8_t token[8]; size_t tokenLen; time_t lastTime; uint32_t counter; uint16_t lastMid; union { int64_t asInteger; double asFloat; } lastValue; } lwm2m_watcher_t; typedef struct _lwm2m_observed_ { struct _lwm2m_observed_* next; lwm2m_uri_t uri; lwm2m_watcher_t* watcherList; } lwm2m_observed_t; #ifdef LWM2M_CLIENT_MODE typedef enum { STATE_INITIAL = 0, STATE_BOOTSTRAP_REQUIRED, STATE_BOOTSTRAPPING, STATE_REGISTER_REQUIRED, STATE_REGISTERING, STATE_READY } lwm2m_client_state_t; typedef enum { BS_SEQUENCE_STATE_INITIAL = 0, BS_SEQUENCE_STATE_FACTORY, BS_SEQUENCE_STATE_SERVER_INITIATED, BS_SEQUENCE_STATE_CLIENT_INITIATED, NO_BS_SEQUENCE_STATE } lwm2m_bs_sequence_state_t; #endif /* * LWM2M Context */ #ifdef LWM2M_BOOTSTRAP_SERVER_MODE // In all the following APIs, the session handle MUST uniquely identify a peer. // LWM2M bootstrap callback // When a LWM2M client requests bootstrap information, the callback is called with status COAP_NO_ERROR, uriP is nil and // name is set. The callback must return a COAP_* error code. COAP_204_CHANGED for success. // After a lwm2m_bootstrap_delete() or a lwm2m_bootstrap_write(), the callback is called with the status returned by the // client, the URI of the operation (may be nil) and name is nil. The callback return value is ignored. typedef int (*lwm2m_bootstrap_callback_t) (void* sessionH, uint8_t status, lwm2m_uri_t* uriP, char* name, void* userData); #endif #ifdef LWM2M_CLIENT_MODE /* use to control the bootstrap, factory bootstrap, client initiated bootstrap, server initiated bootstrap. factory bootstrap is used security object to register. */ typedef struct { lwm2m_bootstrap_type_e bsType; lwm2m_client_state_t state; uint32_t cnt; }lwm2m_bs_control_t; #endif typedef struct _lwm2m_context_t { #ifdef LWM2M_CLIENT_MODE lwm2m_client_state_t state; //char* bs_server_uri; // coaps:// coap://malloc memory bool regist_first_flag; //when serverlist and bootstrapServerList are all exist, we use regist or bootstrap. char* endpointName; char* msisdn; char* altPath; lwm2m_server_t* bootstrapServerList; lwm2m_server_t* serverList; lwm2m_object_t* objectList; lwm2m_observed_t* observedList; void* observe_mutex; lwm2m_bs_control_t bsCtrl; #endif #ifdef LWM2M_SERVER_MODE lwm2m_client_t* clientList; lwm2m_result_callback_t monitorCallback; void* monitorUserData; #endif #ifdef LWM2M_BOOTSTRAP_SERVER_MODE lwm2m_bootstrap_callback_t bootstrapCallback; void* bootstrapUserData; #endif uint16_t nextMID; lwm2m_transaction_t* transactionList; void* userData; } lwm2m_context_t; // initialize a liblwm2m context. lwm2m_context_t* lwm2m_init(void* userData); // close a liblwm2m context. void lwm2m_close(lwm2m_context_t* contextP); // perform any required pending operation and adjust timeoutP to the maximal time interval to wait in seconds. int lwm2m_step(lwm2m_context_t* contextP, time_t* timeoutP); // dispatch received data to liblwm2m void lwm2m_handle_packet(lwm2m_context_t* contextP, uint8_t* buffer, int length, void* fromSessionH); #ifdef LWM2M_CLIENT_MODE // configure the client side with the Endpoint Name, binding, MSISDN (can be nil), alternative path // for objects (can be nil) and a list of objects. // LWM2M Security Object (ID 0) must be present with either a bootstrap server or a LWM2M server and // its matching LWM2M Server Object (ID 1) instance int lwm2m_configure(lwm2m_context_t* contextP, const char* endpointName, const char* msisdn, const char* altPath, uint16_t numObject, lwm2m_object_t* objectList[]); int lwm2m_add_object(lwm2m_context_t* contextP, lwm2m_object_t* objectP); int lwm2m_remove_object(lwm2m_context_t* contextP, uint16_t id); // send a registration update to the server specified by the server short identifier // or all if the ID is 0. // If withObjects is true, the registration update contains the object list. int lwm2m_update_registration(lwm2m_context_t* contextP, uint16_t shortServerID, bool withObjects); void lwm2m_resource_value_changed(lwm2m_context_t* contextP, lwm2m_uri_t* uriP); void lwm2m_register_observe_ack_call_back(lwm2m_transaction_callback_t callback); typedef void(*lwm2m_event_handler_t)(module_type_t type, int code, const char* arg, int arg_len); void lwm2m_register_event_handler(lwm2m_event_handler_t callback); void lwm2m_notify_even(module_type_t type, int code, const char* arg, int arg_len); int lwm2m_reconnect(lwm2m_context_t * context); typedef struct { uint32_t format; uint8_t token[8]; uint32_t tokenLen; uint32_t counter; }lwm2m_observe_info_t; uint8_t lwm2m_get_observe_info(lwm2m_context_t * contextP, lwm2m_observe_info_t *observe_info); uint8_t lwm2m_send_notify(lwm2m_context_t * contextP, lwm2m_observe_info_t *observe_info, int firmware_update_state, lwm2m_data_cfg_t *cfg); int lwm2m_initBootStrap(lwm2m_context_t *contextP, lwm2m_bootstrap_type_e bsType); #endif #ifdef LWM2M_SERVER_MODE // Clients registration/deregistration monitoring API. // When a LWM2M client registers, the callback is called with status COAP_201_CREATED. // When a LWM2M client deregisters, the callback is called with status COAP_202_DELETED. // clientID is the internal ID of the LWM2M Client. // The callback's parameters uri, data, dataLength are always NULL. // The lwm2m_client_t is present in the lwm2m_context_t's clientList when the callback is called. On a deregistration, it deleted when the callback returns. void lwm2m_set_monitoring_callback(lwm2m_context_t* contextP, lwm2m_result_callback_t callback, void* userData); // Device Management APIs int lwm2m_dm_read(lwm2m_context_t* contextP, uint16_t clientID, lwm2m_uri_t* uriP, lwm2m_result_callback_t callback, void* userData); int lwm2m_dm_discover(lwm2m_context_t* contextP, uint16_t clientID, lwm2m_uri_t* uriP, lwm2m_result_callback_t callback, void* userData); int lwm2m_dm_write(lwm2m_context_t* contextP, uint16_t clientID, lwm2m_uri_t* uriP, lwm2m_media_type_t format, uint8_t* buffer, int length, lwm2m_result_callback_t callback, void* userData); int lwm2m_dm_write_attributes(lwm2m_context_t* contextP, uint16_t clientID, lwm2m_uri_t* uriP, lwm2m_attributes_t* attrP, lwm2m_result_callback_t callback, void* userData); int lwm2m_dm_execute(lwm2m_context_t* contextP, uint16_t clientID, lwm2m_uri_t* uriP, lwm2m_media_type_t format, uint8_t* buffer, int length, lwm2m_result_callback_t callback, void* userData); int lwm2m_dm_create(lwm2m_context_t* contextP, uint16_t clientID, lwm2m_uri_t* uriP, lwm2m_media_type_t format, uint8_t* buffer, int length, lwm2m_result_callback_t callback, void* userData); int lwm2m_dm_delete(lwm2m_context_t* contextP, uint16_t clientID, lwm2m_uri_t* uriP, lwm2m_result_callback_t callback, void* userData); // Information Reporting APIs int lwm2m_observe(lwm2m_context_t* contextP, uint16_t clientID, lwm2m_uri_t* uriP, lwm2m_result_callback_t callback, void* userData); int lwm2m_observe_cancel(lwm2m_context_t* contextP, uint16_t clientID, lwm2m_uri_t* uriP, lwm2m_result_callback_t callback, void* userData); #endif #ifdef LWM2M_BOOTSTRAP_SERVER_MODE // Clients bootstrap request monitoring API. // When a LWM2M client sends a bootstrap request, the callback is called with the client's endpoint name. void lwm2m_set_bootstrap_callback(lwm2m_context_t* contextP, lwm2m_bootstrap_callback_t callback, void* userData); // Boostrap Interface APIs // if uriP is nil, a "Delete /" is sent to the client int lwm2m_bootstrap_delete(lwm2m_context_t* contextP, void* sessionH, lwm2m_uri_t* uriP); int lwm2m_bootstrap_write(lwm2m_context_t* contextP, void* sessionH, lwm2m_uri_t* uriP, lwm2m_media_type_t format, uint8_t* buffer, size_t length); int lwm2m_bootstrap_finish(lwm2m_context_t* contextP, void* sessionH); #endif #ifdef __cplusplus } #endif #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/liblwm2m_api.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /**@defgroup agent AgentTiny * @defgroup agenttiny Agenttiny Definition * @ingroup agent */ #ifndef LIB_LWM2M_API_H #define LIB_LWM2M_API_H #include #include #ifdef __cplusplus extern "C" { #endif //bootstrap at least have one mode, we have three mode. typedef enum { BOOTSTRAP_FACTORY = 0, BOOTSTRAP_CLIENT_INITIATED, BOOTSTRAP_SEQUENCE } lwm2m_bootstrap_type_e; #ifdef __cplusplus } #endif #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/list.c ================================================ /******************************************************************************* * * Copyright (c) 2013 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * *******************************************************************************/ #include "internals.h" lwm2m_list_t *lwm2m_list_add(lwm2m_list_t *head, lwm2m_list_t *node) { lwm2m_list_t *target; if (NULL == head) return node; if (head->id > node->id) { node->next = head; return node; } target = head; while (NULL != target->next && target->next->id < node->id) { target = target->next; } node->next = target->next; target->next = node; return head; } lwm2m_list_t *lwm2m_list_find(lwm2m_list_t *head, uint16_t id) { while (NULL != head && head->id < id) { head = head->next; } if (NULL != head && head->id == id) return head; return NULL; } lwm2m_list_t *lwm2m_list_remove(lwm2m_list_t *head, uint16_t id, lwm2m_list_t **nodeP) { lwm2m_list_t *target; if (head == NULL) { if (nodeP) *nodeP = NULL; return NULL; } if (head->id == id) { if (nodeP) *nodeP = head; return head->next; } target = head; while (NULL != target->next && target->next->id < id) { target = target->next; } if (NULL != target->next && target->next->id == id) { if (nodeP) *nodeP = target->next; target->next = target->next->next; } else { if (nodeP) *nodeP = NULL; } return head; } uint16_t lwm2m_list_newId(lwm2m_list_t *head) { uint16_t id; lwm2m_list_t *target; id = 0; target = head; while (target != NULL && id == target->id) { id = target->id + 1; target = target->next; } return id; } void lwm2m_list_free(lwm2m_list_t *head) { if (head != NULL) { lwm2m_list_t *nextP; nextP = head->next; lwm2m_free(head); lwm2m_list_free(nextP); } } ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/lwm2m_utils.c ================================================ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Toby Jaffey - Please refer to git log * *******************************************************************************/ /* Copyright (c) 2013, 2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. David Navarro */ #include "internals.h" #include #include #include #include int utils_textToInt(uint8_t *buffer, int length, int64_t *dataP) { uint64_t result = 0; int sign = 1; int i = 0; if (0 == length) return 0; if (buffer[0] == '-') { sign = -1; i = 1; } while (i < length) { if ('0' <= buffer[i] && buffer[i] <= '9') { if (result > (UINT64_MAX / 10)) return 0; result *= 10; result += buffer[i] - '0'; } else { return 0; } i++; } if (result > INT64_MAX) return 0; if (sign == -1) { *dataP = 0 - result; } else { *dataP = result; } return 1; } int utils_textToFloat(uint8_t *buffer, int length, double *dataP) { double result; int sign; int i; if (0 == length) return 0; if (buffer[0] == '-') { sign = -1; i = 1; } else { sign = 1; i = 0; } result = 0; while (i < length && buffer[i] != '.') { if ('0' <= buffer[i] && buffer[i] <= '9') { if (result > (DBL_MAX / 10)) return 0; result *= 10; result += (buffer[i] - '0'); } else { return 0; } i++; } if (buffer[i] == '.') { double dec; i++; if (i == length) return 0; dec = 0.1; while (i < length) { if ('0' <= buffer[i] && buffer[i] <= '9') { if (result > (DBL_MAX - 1)) return 0; result += (buffer[i] - '0') * dec; dec /= 10; } else { return 0; } i++; } } *dataP = result * sign; return 1; } size_t utils_intToText(int64_t data, uint8_t *string, size_t length) { int index; bool minus; size_t result; if (data < 0) { minus = true; data = 0 - data; } else { minus = false; } index = length - 1; do { string[index] = '0' + data % 10; data /= 10; index --; } while (index >= 0 && data > 0); if (data > 0) return 0; if (minus == true) { if (index == 0) return 0; string[index] = '-'; } else { index++; } result = length - index; if (result < length) { memmove(string, string + index, result); } return result; } size_t utils_floatToText(double data, uint8_t *string, size_t length) { size_t intLength; size_t decLength; int64_t intPart; double decPart; if (data <= (double)INT64_MIN || data >= (double)INT64_MAX) return 0; intPart = (int64_t)data; decPart = data - intPart; if (decPart < 0) { decPart = 1 - decPart; } else { decPart = 1 + decPart; } if (decPart <= 1 + FLT_EPSILON) { decPart = 0; } if (intPart == 0 && data < 0) { // deal with numbers between -1 and 0 if (length < 4) return 0; // "-0.n" string[0] = '-'; string[1] = '0'; intLength = 2; } else { intLength = utils_intToText(intPart, string, length); if (intLength == 0) return 0; } decLength = 0; if (decPart >= FLT_EPSILON) { double noiseFloor; if (intLength >= length - 1) return 0; noiseFloor = FLT_EPSILON; do { decPart *= 10; noiseFloor *= 10; } while (decPart - (int64_t)decPart > noiseFloor); decLength = utils_intToText(decPart, string + intLength, length - intLength); if (decLength <= 1) return 0; // replace the leading 1 with a dot string[intLength] = '.'; } return intLength + decLength; } lwm2m_binding_t utils_stringToBinding(uint8_t *buffer, size_t length) { if (length == 0) return BINDING_UNKNOWN; switch (buffer[0]) { case 'U': switch (length) { case 1: return BINDING_U; case 2: switch (buffer[1]) { case 'Q': return BINDING_UQ; case 'S': return BINDING_US; default: break; } break; case 3: if (buffer[1] == 'Q' && buffer[2] == 'S') { return BINDING_UQS; } break; default: break; } break; case 'S': switch (length) { case 1: return BINDING_S; case 2: if (buffer[1] == 'Q') { return BINDING_SQ; } break; default: break; } break; default: break; } return BINDING_UNKNOWN; } lwm2m_media_type_t utils_convertMediaType(coap_content_type_t type) { // Here we just check the content type is a valid value for LWM2M switch((uint16_t)type) { case TEXT_PLAIN: return LWM2M_CONTENT_TEXT; case APPLICATION_OCTET_STREAM: return LWM2M_CONTENT_OPAQUE; case LWM2M_CONTENT_TLV_OLD: return LWM2M_CONTENT_TLV_OLD; case LWM2M_CONTENT_TLV: return LWM2M_CONTENT_TLV; case LWM2M_CONTENT_JSON_OLD: return LWM2M_CONTENT_JSON_OLD; case LWM2M_CONTENT_JSON: return LWM2M_CONTENT_JSON; case APPLICATION_LINK_FORMAT: return LWM2M_CONTENT_LINK; default: return LWM2M_CONTENT_TEXT; } } #ifdef LWM2M_CLIENT_MODE lwm2m_server_t *utils_findServer(lwm2m_context_t *contextP, void *fromSessionH) { lwm2m_server_t *targetP; targetP = contextP->serverList; while (targetP != NULL && false == lwm2m_session_is_equal(targetP->sessionH, fromSessionH, contextP->userData)) { targetP = targetP->next; } return targetP; } #endif #ifdef LWM2M_BOOTSTRAP lwm2m_server_t *utils_findBootstrapServer(lwm2m_context_t *contextP, void *fromSessionH) { #ifdef LWM2M_CLIENT_MODE lwm2m_server_t *targetP; targetP = contextP->bootstrapServerList; while (targetP != NULL && false == lwm2m_session_is_equal(targetP->sessionH, fromSessionH, contextP->userData)) { targetP = targetP->next; } return targetP; #else return NULL; #endif } #endif int utils_isAltPathValid(const char *altPath) { int i; if (altPath == NULL) return 0; if (altPath[0] != '/') return 0; for (i = 1 ; altPath[i] != 0 ; i++) { // TODO: Support multi-segment alternative path if (altPath[i] == '/') return 0; // TODO: Check needs for sub-delims, ':' and '@' if ((altPath[i] < 'A' || altPath[i] > 'Z') // ALPHA && (altPath[i] < 'a' || altPath[i] > 'z') && (altPath[i] < '0' || altPath[i] > '9') // DIGIT && (altPath[i] != '-') // Other unreserved && (altPath[i] != '.') && (altPath[i] != '_') && (altPath[i] != '~') && (altPath[i] != '%')) // pct_encoded { return 0; } } return 1; } // copy a string in a buffer. // return the number of copied bytes or -1 if the buffer is not large enough int utils_stringCopy(char *buffer, size_t length, const char *str) { size_t i; for (i = 0 ; i < length && str[i] != 0 ; i++) { buffer[i] = str[i]; } if (i == length) return -1; buffer[i] = 0; return (int)i; } void utils_copyValue(void *dst, const void *src, size_t len) { #ifdef LWM2M_BIG_ENDIAN memcpy(dst, src, len); #else #ifdef LWM2M_LITTLE_ENDIAN size_t i; for (i = 0; i < len; i++) { ((uint8_t *)dst)[i] = ((uint8_t *)src)[len - 1 - i]; } #endif #endif } #define PRV_B64_PADDING '=' static char b64Alphabet[64] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '+', '/' }; static void prv_encodeBlock(uint8_t input[3], uint8_t output[4]) { output[0] = b64Alphabet[input[0] >> 2]; output[1] = b64Alphabet[((input[0] & 0x03) << 4) | (input[1] >> 4)]; output[2] = b64Alphabet[((input[1] & 0x0F) << 2) | (input[2] >> 6)]; output[3] = b64Alphabet[input[2] & 0x3F]; } size_t utils_base64GetSize(size_t dataLen) { size_t result_len; result_len = 4 * (dataLen / 3); if (dataLen % 3) result_len += 4; return result_len; } size_t utils_base64Encode(uint8_t *dataP, size_t dataLen, uint8_t *bufferP, size_t bufferLen) { unsigned int data_index; unsigned int result_index; size_t result_len; result_len = utils_base64GetSize(dataLen); if (result_len > bufferLen) return 0; data_index = 0; result_index = 0; while (data_index < dataLen) { switch (dataLen - data_index) { case 0: // should never happen break; case 1: bufferP[result_index] = b64Alphabet[dataP[data_index] >> 2]; bufferP[result_index + 1] = b64Alphabet[(dataP[data_index] & 0x03) << 4]; bufferP[result_index + 2] = PRV_B64_PADDING; bufferP[result_index + 3] = PRV_B64_PADDING; break; case 2: bufferP[result_index] = b64Alphabet[dataP[data_index] >> 2]; bufferP[result_index + 1] = b64Alphabet[(dataP[data_index] & 0x03) << 4 | (dataP[data_index + 1] >> 4)]; bufferP[result_index + 2] = b64Alphabet[(dataP[data_index + 1] & 0x0F) << 2]; bufferP[result_index + 3] = PRV_B64_PADDING; break; default: prv_encodeBlock(dataP + data_index, bufferP + result_index); break; } data_index += 3; result_index += 4; } return result_len; } lwm2m_data_type_t utils_depthToDatatype(uri_depth_t depth) { switch (depth) { case URI_DEPTH_OBJECT: return LWM2M_TYPE_OBJECT; case URI_DEPTH_OBJECT_INSTANCE: return LWM2M_TYPE_OBJECT_INSTANCE; default: break; } return LWM2M_TYPE_UNDEFINED; } ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/management.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * domedambrosio - Please refer to git log * Toby Jaffey - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - Please refer to git log * *******************************************************************************/ /* Copyright (c) 2013, 2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. David Navarro */ #include "internals.h" #include "object_comm.h" #include #ifdef LWM2M_CLIENT_MODE static int prv_readAttributes(multi_option_t *query, lwm2m_attributes_t *attrP) { int64_t intValue; double floatValue; memset(attrP, 0, sizeof(lwm2m_attributes_t)); while (query != NULL) { if (lwm2m_strncmp((char *)query->data, ATTR_MIN_PERIOD_STR, ATTR_MIN_PERIOD_LEN) == 0) { if (0 != ((attrP->toSet | attrP->toClear) & LWM2M_ATTR_FLAG_MIN_PERIOD)) return -1; if (query->len == ATTR_MIN_PERIOD_LEN) return -1; if (1 != utils_textToInt(query->data + ATTR_MIN_PERIOD_LEN, query->len - ATTR_MIN_PERIOD_LEN, &intValue)) return -1; if (intValue < 0) return -1; attrP->toSet |= LWM2M_ATTR_FLAG_MIN_PERIOD; attrP->minPeriod = intValue; } else if (lwm2m_strncmp((char *)query->data, ATTR_MIN_PERIOD_STR, ATTR_MIN_PERIOD_LEN - 1) == 0) { if (0 != ((attrP->toSet | attrP->toClear) & LWM2M_ATTR_FLAG_MIN_PERIOD)) return -1; if (query->len != ATTR_MIN_PERIOD_LEN - 1) return -1; attrP->toClear |= LWM2M_ATTR_FLAG_MIN_PERIOD; } else if (lwm2m_strncmp((char *)query->data, ATTR_MAX_PERIOD_STR, ATTR_MAX_PERIOD_LEN) == 0) { if (0 != ((attrP->toSet | attrP->toClear) & LWM2M_ATTR_FLAG_MAX_PERIOD)) return -1; if (query->len == ATTR_MAX_PERIOD_LEN) return -1; if (1 != utils_textToInt(query->data + ATTR_MAX_PERIOD_LEN, query->len - ATTR_MAX_PERIOD_LEN, &intValue)) return -1; if (intValue < 0) return -1; attrP->toSet |= LWM2M_ATTR_FLAG_MAX_PERIOD; attrP->maxPeriod = intValue; } else if (lwm2m_strncmp((char *)query->data, ATTR_MAX_PERIOD_STR, ATTR_MAX_PERIOD_LEN - 1) == 0) { if (0 != ((attrP->toSet | attrP->toClear) & LWM2M_ATTR_FLAG_MAX_PERIOD)) return -1; if (query->len != ATTR_MAX_PERIOD_LEN - 1) return -1; attrP->toClear |= LWM2M_ATTR_FLAG_MAX_PERIOD; } else if (lwm2m_strncmp((char *)query->data, ATTR_GREATER_THAN_STR, ATTR_GREATER_THAN_LEN) == 0) { if (0 != ((attrP->toSet | attrP->toClear) & LWM2M_ATTR_FLAG_GREATER_THAN)) return -1; if (query->len == ATTR_GREATER_THAN_LEN) return -1; if (1 != utils_textToFloat(query->data + ATTR_GREATER_THAN_LEN, query->len - ATTR_GREATER_THAN_LEN, &floatValue)) return -1; attrP->toSet |= LWM2M_ATTR_FLAG_GREATER_THAN; attrP->greaterThan = floatValue; } else if (lwm2m_strncmp((char *)query->data, ATTR_GREATER_THAN_STR, ATTR_GREATER_THAN_LEN - 1) == 0) { if (0 != ((attrP->toSet | attrP->toClear) & LWM2M_ATTR_FLAG_GREATER_THAN)) return -1; if (query->len != ATTR_GREATER_THAN_LEN - 1) return -1; attrP->toClear |= LWM2M_ATTR_FLAG_GREATER_THAN; } else if (lwm2m_strncmp((char *)query->data, ATTR_LESS_THAN_STR, ATTR_LESS_THAN_LEN) == 0) { if (0 != ((attrP->toSet | attrP->toClear) & LWM2M_ATTR_FLAG_LESS_THAN)) return -1; if (query->len == ATTR_LESS_THAN_LEN) return -1; if (1 != utils_textToFloat(query->data + ATTR_LESS_THAN_LEN, query->len - ATTR_LESS_THAN_LEN, &floatValue)) return -1; attrP->toSet |= LWM2M_ATTR_FLAG_LESS_THAN; attrP->lessThan = floatValue; } else if (lwm2m_strncmp((char *)query->data, ATTR_LESS_THAN_STR, ATTR_LESS_THAN_LEN - 1) == 0) { if (0 != ((attrP->toSet | attrP->toClear) & LWM2M_ATTR_FLAG_LESS_THAN)) return -1; if (query->len != ATTR_LESS_THAN_LEN - 1) return -1; attrP->toClear |= LWM2M_ATTR_FLAG_LESS_THAN; } else if (lwm2m_strncmp((char *)query->data, ATTR_STEP_STR, ATTR_STEP_LEN) == 0) { if (0 != ((attrP->toSet | attrP->toClear) & LWM2M_ATTR_FLAG_STEP)) return -1; if (query->len == ATTR_STEP_LEN) return -1; if (1 != utils_textToFloat(query->data + ATTR_STEP_LEN, query->len - ATTR_STEP_LEN, &floatValue)) return -1; if (floatValue < 0) return -1; attrP->toSet |= LWM2M_ATTR_FLAG_STEP; attrP->step = floatValue; } else if (lwm2m_strncmp((char *)query->data, ATTR_STEP_STR, ATTR_STEP_LEN - 1) == 0) { if (0 != ((attrP->toSet | attrP->toClear) & LWM2M_ATTR_FLAG_STEP)) return -1; if (query->len != ATTR_STEP_LEN - 1) return -1; attrP->toClear |= LWM2M_ATTR_FLAG_STEP; } else return -1; query = query->next; } return 0; } uint8_t dm_handleRequest(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_server_t *serverP, coap_packet_t *message, coap_packet_t *response) { uint8_t result; lwm2m_media_type_t format; LOG_ARG("Code: %02X, server status: %s", message->code, STR_STATUS(serverP->status)); LOG_URI(uriP); if (IS_OPTION(message, COAP_OPTION_CONTENT_TYPE)) { format = utils_convertMediaType(message->content_type); } else { format = (dm_isUriOpaqueHandle(uriP) ? LWM2M_CONTENT_OPAQUE : LWM2M_CONTENT_TLV); } if (uriP->objectId == LWM2M_SECURITY_OBJECT_ID) { return COAP_404_NOT_FOUND; } if (serverP->status != STATE_REGISTERED && serverP->status != STATE_REG_UPDATE_NEEDED && serverP->status != STATE_REG_FULL_UPDATE_NEEDED && serverP->status != STATE_REG_UPDATE_PENDING) { return COAP_IGNORE; } switch (message->code) { case COAP_GET: { uint8_t *buffer = NULL; size_t length = 0; int res; if (IS_OPTION(message, COAP_OPTION_OBSERVE)) { lwm2m_data_t *dataP = NULL; int size = 0; if ((result = acc_auth_operate(contextP, uriP, OBJ_ACC_OBSERVE, serverP->shortID)) != COAP_NO_ERROR) { return result; } result = object_readData(contextP, uriP, &size, &dataP, NULL, serverP->shortID); if (COAP_205_CONTENT == result) { result = observe_handleRequest(contextP, uriP, serverP, size, dataP, message, response); if (COAP_205_CONTENT == result) { if (IS_OPTION(message, COAP_OPTION_ACCEPT)) { format = utils_convertMediaType((coap_content_type_t)message->accept[0]); } else { format = LWM2M_CONTENT_TLV; } if(dm_isUriOpaqueHandle(uriP)) { buffer = NULL; length = 0; format = LWM2M_CONTENT_OPAQUE; } else { res = lwm2m_data_serialize(uriP, size, dataP, &format, &buffer); if (res < 0) { result = COAP_500_INTERNAL_SERVER_ERROR; } else { length = (size_t)res; LOG_ARG("Observe Request[/%d/%d/%d]: %.*s\n", uriP->objectId, uriP->instanceId, uriP->resourceId, length, buffer); } } } lwm2m_data_free(size, dataP); } } else if (IS_OPTION(message, COAP_OPTION_ACCEPT) && message->accept_num == 1 && message->accept[0] == APPLICATION_LINK_FORMAT) { if ((result = acc_auth_operate(contextP, uriP, OBJ_ACC_DISCOVER, serverP->shortID)) != COAP_NO_ERROR) { return result; } format = LWM2M_CONTENT_LINK; result = object_discover(contextP, uriP, serverP, &buffer, &length); } else { if ((result = acc_auth_operate(contextP, uriP, OBJ_ACC_READ, serverP->shortID)) != COAP_NO_ERROR) { return result; } if (IS_OPTION(message, COAP_OPTION_ACCEPT)) { format = utils_convertMediaType((coap_content_type_t)message->accept[0]); } result = object_read(contextP, uriP, &format, &buffer, &length, serverP->shortID); } if (COAP_205_CONTENT == result) { coap_set_header_content_type(response, format); coap_set_payload(response, buffer, length); // lwm2m_handle_packet will free buffer } else { lwm2m_free(buffer); } } break; case COAP_POST: { if (!LWM2M_URI_IS_SET_INSTANCE(uriP)) { if ((result = acc_auth_operate(contextP, uriP, OBJ_ACC_CREATE, serverP->shortID)) != COAP_NO_ERROR) { return result; } result = object_create(contextP, uriP, format, message->payload, message->payload_len); if (result == COAP_201_CREATED) { //longest uri is /65535/65535 = 12 + 1 (null) chars char location_path[13] = ""; //instanceId expected if ((uriP->flag & LWM2M_URI_FLAG_INSTANCE_ID) == 0) { result = COAP_500_INTERNAL_SERVER_ERROR; break; } if (sprintf(location_path, "/%d/%d", uriP->objectId, uriP->instanceId) < 0) { result = COAP_500_INTERNAL_SERVER_ERROR; break; } coap_set_header_location_path(response, location_path); lwm2m_update_registration(contextP, 0, true); } } else if (!LWM2M_URI_IS_SET_RESOURCE(uriP)) { if ((result = acc_auth_operate(contextP, uriP, OBJ_ACC_WRITE, serverP->shortID)) != COAP_NO_ERROR) { return result; } result = object_write(contextP, uriP, format, message->payload, message->payload_len); } else { if ((result = acc_auth_operate(contextP, uriP, OBJ_ACC_EXCUTE, serverP->shortID)) != COAP_NO_ERROR) { return result; } result = object_execute(contextP, uriP, message->payload, message->payload_len); } } break; case COAP_PUT: { if (IS_OPTION(message, COAP_OPTION_URI_QUERY)) { lwm2m_attributes_t attr; if ((result = acc_auth_operate(contextP, uriP, OBJ_ACC_WRITE_ATTR, serverP->shortID)) != COAP_NO_ERROR) { return result; } if (0 != prv_readAttributes(message->uri_query, &attr)) { result = COAP_400_BAD_REQUEST; } else { result = observe_setParameters(contextP, uriP, serverP, &attr); } } else if (LWM2M_URI_IS_SET_INSTANCE(uriP)) { if ((result = acc_auth_operate(contextP, uriP, OBJ_ACC_WRITE, serverP->shortID)) != COAP_NO_ERROR) { return result; } result = object_write(contextP, uriP, format, message->payload, message->payload_len); } else { result = COAP_400_BAD_REQUEST; } } break; case COAP_DELETE: { if (!LWM2M_URI_IS_SET_INSTANCE(uriP) || LWM2M_URI_IS_SET_RESOURCE(uriP)) { result = COAP_400_BAD_REQUEST; } else { if ((result = acc_auth_operate(contextP, uriP, OBJ_ACC_DELETE, serverP->shortID)) != COAP_NO_ERROR) { return result; } result = object_delete(contextP, uriP); if (result == COAP_202_DELETED) { lwm2m_update_registration(contextP, 0, true); } } } break; default: result = COAP_400_BAD_REQUEST; break; } return result; } #endif #ifdef LWM2M_SERVER_MODE #define ID_AS_STRING_MAX_LEN 8 static void prv_resultCallback(lwm2m_transaction_t *transacP, void *message) { dm_data_t *dataP = (dm_data_t *)transacP->userData; if (message == NULL) { dataP->callback(dataP->clientID, &dataP->uri, COAP_503_SERVICE_UNAVAILABLE, LWM2M_CONTENT_TEXT, NULL, 0, dataP->userData); } else { coap_packet_t *packet = (coap_packet_t *)message; //if packet is a CREATE response and the instanceId was assigned by the client if (packet->code == COAP_201_CREATED && packet->location_path != NULL) { char *locationString = NULL; int result = 0; lwm2m_uri_t locationUri; locationString = coap_get_multi_option_as_string(packet->location_path); if (locationString == NULL) { LOG("Error: coap_get_multi_option_as_string() failed for Location_path option in prv_resultCallback()"); return; } result = lwm2m_stringToUri(locationString, strlen(locationString), &locationUri); if (result == 0) { LOG("Error: lwm2m_stringToUri() failed for Location_path option in prv_resultCallback()"); lwm2m_free(locationString); return; } ((dm_data_t *)transacP->userData)->uri.instanceId = locationUri.instanceId; ((dm_data_t *)transacP->userData)->uri.flag = locationUri.flag; lwm2m_free(locationString); } dataP->callback(dataP->clientID, &dataP->uri, packet->code, utils_convertMediaType(packet->content_type), packet->payload, packet->payload_len, dataP->userData); } lwm2m_free(dataP); } static int prv_makeOperation(lwm2m_context_t *contextP, uint16_t clientID, lwm2m_uri_t *uriP, coap_method_t method, lwm2m_media_type_t format, uint8_t *buffer, int length, lwm2m_result_callback_t callback, void *userData) { lwm2m_client_t *clientP; lwm2m_transaction_t *transaction; dm_data_t *dataP; clientP = (lwm2m_client_t *)lwm2m_list_find((lwm2m_list_t *)contextP->clientList, clientID); if (clientP == NULL) return COAP_404_NOT_FOUND; transaction = transaction_new(clientP->sessionH, method, clientP->altPath, uriP, contextP->nextMID++, 4, NULL); if (transaction == NULL) return COAP_500_INTERNAL_SERVER_ERROR; if (method == COAP_GET) { coap_set_header_accept(transaction->message, format); } else if (buffer != NULL) { coap_set_header_content_type(transaction->message, format); // TODO: Take care of fragmentation coap_set_payload(transaction->message, buffer, length); } if (callback != NULL) { dataP = (dm_data_t *)lwm2m_malloc(sizeof(dm_data_t)); if (dataP == NULL) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } memcpy(&dataP->uri, uriP, sizeof(lwm2m_uri_t)); dataP->clientID = clientP->internalID; dataP->callback = callback; dataP->userData = userData; transaction->callback = prv_resultCallback; transaction->userData = (void *)dataP; } contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transaction); return transaction_send(contextP, transaction); } int lwm2m_dm_read(lwm2m_context_t *contextP, uint16_t clientID, lwm2m_uri_t *uriP, lwm2m_result_callback_t callback, void *userData) { lwm2m_client_t *clientP; lwm2m_media_type_t format; LOG_ARG("clientID: %d", clientID); LOG_URI(uriP); clientP = (lwm2m_client_t *)lwm2m_list_find((lwm2m_list_t *)contextP->clientList, clientID); if (clientP == NULL) return COAP_404_NOT_FOUND; if (clientP->supportJSON == true) { format = LWM2M_CONTENT_JSON; } else { format = LWM2M_CONTENT_TLV; } return prv_makeOperation(contextP, clientID, uriP, COAP_GET, format, NULL, 0, callback, userData); } int lwm2m_dm_write(lwm2m_context_t *contextP, uint16_t clientID, lwm2m_uri_t *uriP, lwm2m_media_type_t format, uint8_t *buffer, int length, lwm2m_result_callback_t callback, void *userData) { LOG_ARG("clientID: %d, format: %s, length: %d", clientID, STR_MEDIA_TYPE(format), length); LOG_URI(uriP); if (!LWM2M_URI_IS_SET_INSTANCE(uriP) || length == 0) { return COAP_400_BAD_REQUEST; } if (LWM2M_URI_IS_SET_RESOURCE(uriP)) { return prv_makeOperation(contextP, clientID, uriP, COAP_PUT, format, buffer, length, callback, userData); } else { return prv_makeOperation(contextP, clientID, uriP, COAP_POST, format, buffer, length, callback, userData); } } int lwm2m_dm_execute(lwm2m_context_t *contextP, uint16_t clientID, lwm2m_uri_t *uriP, lwm2m_media_type_t format, uint8_t *buffer, int length, lwm2m_result_callback_t callback, void *userData) { LOG_ARG("clientID: %d, format: %s, length: %d", clientID, STR_MEDIA_TYPE(format), length); LOG_URI(uriP); if (!LWM2M_URI_IS_SET_RESOURCE(uriP)) { return COAP_400_BAD_REQUEST; } return prv_makeOperation(contextP, clientID, uriP, COAP_POST, format, buffer, length, callback, userData); } int lwm2m_dm_create(lwm2m_context_t *contextP, uint16_t clientID, lwm2m_uri_t *uriP, lwm2m_media_type_t format, uint8_t *buffer, int length, lwm2m_result_callback_t callback, void *userData) { LOG_ARG("clientID: %d, format: %s, length: %d", clientID, STR_MEDIA_TYPE(format), length); LOG_URI(uriP); if (LWM2M_URI_IS_SET_INSTANCE(uriP) || length == 0) { return COAP_400_BAD_REQUEST; } return prv_makeOperation(contextP, clientID, uriP, COAP_POST, format, buffer, length, callback, userData); } int lwm2m_dm_delete(lwm2m_context_t *contextP, uint16_t clientID, lwm2m_uri_t *uriP, lwm2m_result_callback_t callback, void *userData) { LOG_ARG("clientID: %d", clientID); LOG_URI(uriP); if (!LWM2M_URI_IS_SET_INSTANCE(uriP) || LWM2M_URI_IS_SET_RESOURCE(uriP)) { return COAP_400_BAD_REQUEST; } return prv_makeOperation(contextP, clientID, uriP, COAP_DELETE, LWM2M_CONTENT_TEXT, NULL, 0, callback, userData); } int lwm2m_dm_write_attributes(lwm2m_context_t *contextP, uint16_t clientID, lwm2m_uri_t *uriP, lwm2m_attributes_t *attrP, lwm2m_result_callback_t callback, void *userData) { #define _PRV_BUFFER_SIZE 32 lwm2m_client_t *clientP; lwm2m_transaction_t *transaction; coap_packet_t *coap_pkt; uint8_t buffer[_PRV_BUFFER_SIZE]; size_t length; LOG_ARG("clientID: %d", clientID); LOG_URI(uriP); if (attrP == NULL) return COAP_400_BAD_REQUEST; if (0 != (attrP->toSet & attrP->toClear)) return COAP_400_BAD_REQUEST; if (0 != (attrP->toSet & ATTR_FLAG_NUMERIC) && !LWM2M_URI_IS_SET_RESOURCE(uriP)) return COAP_400_BAD_REQUEST; if (ATTR_FLAG_NUMERIC == (attrP->toSet & ATTR_FLAG_NUMERIC) && (attrP->lessThan + 2 * attrP->step >= attrP->greaterThan)) return COAP_400_BAD_REQUEST; clientP = (lwm2m_client_t *)lwm2m_list_find((lwm2m_list_t *)contextP->clientList, clientID); if (clientP == NULL) return COAP_404_NOT_FOUND; transaction = transaction_new(clientP->sessionH, COAP_PUT, clientP->altPath, uriP, contextP->nextMID++, 4, NULL); if (transaction == NULL) return COAP_500_INTERNAL_SERVER_ERROR; if (callback != NULL) { dm_data_t *dataP; dataP = (dm_data_t *)lwm2m_malloc(sizeof(dm_data_t)); if (dataP == NULL) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } memcpy(&dataP->uri, uriP, sizeof(lwm2m_uri_t)); dataP->clientID = clientP->internalID; dataP->callback = callback; dataP->userData = userData; transaction->callback = prv_resultCallback; transaction->userData = (void *)dataP; } coap_pkt = (coap_packet_t *)transaction->message; free_multi_option(coap_pkt->uri_query); if (attrP->toSet & LWM2M_ATTR_FLAG_MIN_PERIOD) { memcpy(buffer, ATTR_MIN_PERIOD_STR, ATTR_MIN_PERIOD_LEN); length = utils_intToText(attrP->minPeriod, buffer + ATTR_MIN_PERIOD_LEN, _PRV_BUFFER_SIZE - ATTR_MIN_PERIOD_LEN); if (length == 0) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } coap_add_multi_option(&(coap_pkt->uri_query), buffer, ATTR_MIN_PERIOD_LEN + length, 0); SET_OPTION(coap_pkt, COAP_OPTION_URI_QUERY); } if (attrP->toSet & LWM2M_ATTR_FLAG_MAX_PERIOD) { memcpy(buffer, ATTR_MAX_PERIOD_STR, ATTR_MAX_PERIOD_LEN); length = utils_intToText(attrP->maxPeriod, buffer + ATTR_MAX_PERIOD_LEN, _PRV_BUFFER_SIZE - ATTR_MAX_PERIOD_LEN); if (length == 0) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } coap_add_multi_option(&(coap_pkt->uri_query), buffer, ATTR_MAX_PERIOD_LEN + length, 0); SET_OPTION(coap_pkt, COAP_OPTION_URI_QUERY); } if (attrP->toSet & LWM2M_ATTR_FLAG_GREATER_THAN) { memcpy(buffer, ATTR_GREATER_THAN_STR, ATTR_GREATER_THAN_LEN); length = utils_floatToText(attrP->greaterThan, buffer + ATTR_GREATER_THAN_LEN, _PRV_BUFFER_SIZE - ATTR_GREATER_THAN_LEN); if (length == 0) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } coap_add_multi_option(&(coap_pkt->uri_query), buffer, ATTR_GREATER_THAN_LEN + length, 0); SET_OPTION(coap_pkt, COAP_OPTION_URI_QUERY); } if (attrP->toSet & LWM2M_ATTR_FLAG_LESS_THAN) { memcpy(buffer, ATTR_LESS_THAN_STR, ATTR_LESS_THAN_LEN); length = utils_floatToText(attrP->lessThan, buffer + ATTR_LESS_THAN_LEN, _PRV_BUFFER_SIZE - ATTR_LESS_THAN_LEN); if (length == 0) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } coap_add_multi_option(&(coap_pkt->uri_query), buffer, ATTR_LESS_THAN_LEN + length, 0); SET_OPTION(coap_pkt, COAP_OPTION_URI_QUERY); } if (attrP->toSet & LWM2M_ATTR_FLAG_STEP) { memcpy(buffer, ATTR_STEP_STR, ATTR_STEP_LEN); length = utils_floatToText(attrP->step, buffer + ATTR_STEP_LEN, _PRV_BUFFER_SIZE - ATTR_STEP_LEN); if (length == 0) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } coap_add_multi_option(&(coap_pkt->uri_query), buffer, ATTR_STEP_LEN + length, 0); SET_OPTION(coap_pkt, COAP_OPTION_URI_QUERY); } if (attrP->toClear & LWM2M_ATTR_FLAG_MIN_PERIOD) { coap_add_multi_option(&(coap_pkt->uri_query), (uint8_t *)ATTR_MIN_PERIOD_STR, ATTR_MIN_PERIOD_LEN - 1, 0); SET_OPTION(coap_pkt, COAP_OPTION_URI_QUERY); } if (attrP->toClear & LWM2M_ATTR_FLAG_MAX_PERIOD) { coap_add_multi_option(&(coap_pkt->uri_query), (uint8_t *)ATTR_MAX_PERIOD_STR, ATTR_MAX_PERIOD_LEN - 1, 0); SET_OPTION(coap_pkt, COAP_OPTION_URI_QUERY); } if (attrP->toClear & LWM2M_ATTR_FLAG_GREATER_THAN) { coap_add_multi_option(&(coap_pkt->uri_query), (uint8_t *)ATTR_GREATER_THAN_STR, ATTR_GREATER_THAN_LEN - 1, 0); SET_OPTION(coap_pkt, COAP_OPTION_URI_QUERY); } if (attrP->toClear & LWM2M_ATTR_FLAG_LESS_THAN) { coap_add_multi_option(&(coap_pkt->uri_query), (uint8_t *)ATTR_LESS_THAN_STR, ATTR_LESS_THAN_LEN - 1, 0); SET_OPTION(coap_pkt, COAP_OPTION_URI_QUERY); } if (attrP->toClear & LWM2M_ATTR_FLAG_STEP) { coap_add_multi_option(&(coap_pkt->uri_query), (uint8_t *)ATTR_STEP_STR, ATTR_STEP_LEN - 1, 0); SET_OPTION(coap_pkt, COAP_OPTION_URI_QUERY); } contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transaction); return transaction_send(contextP, transaction); } int lwm2m_dm_discover(lwm2m_context_t *contextP, uint16_t clientID, lwm2m_uri_t *uriP, lwm2m_result_callback_t callback, void *userData) { lwm2m_client_t *clientP; lwm2m_transaction_t *transaction; dm_data_t *dataP; LOG_ARG("clientID: %d", clientID); LOG_URI(uriP); clientP = (lwm2m_client_t *)lwm2m_list_find((lwm2m_list_t *)contextP->clientList, clientID); if (clientP == NULL) return COAP_404_NOT_FOUND; transaction = transaction_new(clientP->sessionH, COAP_GET, clientP->altPath, uriP, contextP->nextMID++, 4, NULL); if (transaction == NULL) return COAP_500_INTERNAL_SERVER_ERROR; coap_set_header_accept(transaction->message, LWM2M_CONTENT_LINK); if (callback != NULL) { dataP = (dm_data_t *)lwm2m_malloc(sizeof(dm_data_t)); if (dataP == NULL) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } memcpy(&dataP->uri, uriP, sizeof(lwm2m_uri_t)); dataP->clientID = clientP->internalID; dataP->callback = callback; dataP->userData = userData; transaction->callback = prv_resultCallback; transaction->userData = (void *)dataP; } contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transaction); return transaction_send(contextP, transaction); } #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/objects.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Fabien Fleutot - Please refer to git log * Toby Jaffey - Please refer to git log * Benjamin Cabe? - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - Please refer to git log * Scott Bertin - Please refer to git log * *******************************************************************************/ /* Copyright (c) 2013, 2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. David Navarro */ #include "internals.h" #ifdef LWM2M_CLIENT_MODE #include #include #include #include "object_comm.h" uint8_t object_checkReadable(lwm2m_context_t *contextP, lwm2m_uri_t *uriP) { uint8_t result; lwm2m_object_t *targetP; lwm2m_data_t *dataP = NULL; int size; LOG_URI(uriP); targetP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, uriP->objectId); if (NULL == targetP) return COAP_404_NOT_FOUND; if (NULL == targetP->readFunc) return COAP_405_METHOD_NOT_ALLOWED; if (!LWM2M_URI_IS_SET_INSTANCE(uriP)) return COAP_205_CONTENT; if (NULL == lwm2m_list_find(targetP->instanceList, uriP->instanceId)) return COAP_404_NOT_FOUND; if (!LWM2M_URI_IS_SET_RESOURCE(uriP)) return COAP_205_CONTENT; size = 1; dataP = lwm2m_data_new(1); if (dataP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; dataP->id = uriP->resourceId; result = targetP->readFunc(uriP->instanceId, &size, &dataP, NULL, targetP); lwm2m_data_free(1, dataP); return result; } uint8_t object_checkNumeric(lwm2m_context_t *contextP, lwm2m_uri_t *uriP) { uint8_t result; lwm2m_object_t *targetP; lwm2m_data_t *dataP = NULL; int size; LOG_URI(uriP); if (!LWM2M_URI_IS_SET_RESOURCE(uriP)) return COAP_405_METHOD_NOT_ALLOWED; targetP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, uriP->objectId); if (NULL == targetP) return COAP_404_NOT_FOUND; if (NULL == targetP->readFunc) return COAP_405_METHOD_NOT_ALLOWED; size = 1; dataP = lwm2m_data_new(1); if (dataP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; dataP->id = uriP->resourceId; result = targetP->readFunc(uriP->instanceId, &size, &dataP, NULL, targetP); if (result == COAP_205_CONTENT) { switch (dataP->type) { case LWM2M_TYPE_INTEGER: case LWM2M_TYPE_FLOAT: break; default: result = COAP_405_METHOD_NOT_ALLOWED; } } lwm2m_data_free(1, dataP); return result; } static uint8_t prv_init_forbidden(lwm2m_context_t *contextP, lwm2m_object_t *targetP, uint16_t objId, uint16_t serverId, int *sizeP, uint8_t **forbidden) { lwm2m_list_t *instanceP; lwm2m_uri_t uriP; int i; uriP.flag = LWM2M_URI_FLAG_INSTANCE_ID; uriP.objectId = objId; i = 0; *forbidden = (uint8_t *)lwm2m_malloc(*sizeP); if (*forbidden == NULL) { return COAP_500_INTERNAL_SERVER_ERROR; } memset(*forbidden, 0, *sizeP); for (instanceP = targetP->instanceList; instanceP != NULL ; instanceP = instanceP->next) { uriP.instanceId = instanceP->id; if (acc_auth_operate(contextP, &uriP, OBJ_ACC_READ, serverId) != COAP_NO_ERROR) { (*sizeP)--; (*forbidden)[i] = 1; } ++i; } if (*sizeP == 0) { lwm2m_free(*forbidden); return COAP_500_INTERNAL_SERVER_ERROR; } return COAP_NO_ERROR; } uint8_t object_readData(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, int *sizeP, lwm2m_data_t **dataP, lwm2m_data_cfg_t *cfg, uint16_t serverId) { uint8_t result; lwm2m_object_t *targetP; LOG_URI(uriP); targetP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, uriP->objectId); if (NULL == targetP) return COAP_404_NOT_FOUND; if (NULL == targetP->readFunc) return COAP_405_METHOD_NOT_ALLOWED; if (LWM2M_URI_IS_SET_INSTANCE(uriP)) { if (NULL == lwm2m_list_find(targetP->instanceList, uriP->instanceId)) return COAP_404_NOT_FOUND; // single instance read if (LWM2M_URI_IS_SET_RESOURCE(uriP)) { *sizeP = 1; *dataP = lwm2m_data_new(*sizeP); if (*dataP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; (*dataP)->id = uriP->resourceId; } result = targetP->readFunc(uriP->instanceId, sizeP, dataP, cfg, targetP); } else { // multiple object instances read lwm2m_list_t *instanceP; uint8_t *forbidden = NULL; int i; int j; result = COAP_205_CONTENT; *sizeP = 0; for (instanceP = targetP->instanceList; instanceP != NULL ; instanceP = instanceP->next) { (*sizeP)++; } if (*sizeP == 0) { *dataP = NULL; } else { if ((result = prv_init_forbidden(contextP, targetP, uriP->objectId, serverId, sizeP, &forbidden)) != COAP_NO_ERROR) { *dataP = NULL; return result; } *dataP = lwm2m_data_new(*sizeP); if (*dataP == NULL) { if (forbidden != NULL) { lwm2m_free(forbidden); } return COAP_500_INTERNAL_SERVER_ERROR; } instanceP = targetP->instanceList; i = 0; j = 0; while (instanceP != NULL && result == COAP_205_CONTENT) { if (forbidden[i] == 0) { result = targetP->readFunc(instanceP->id, (int *) & ((*dataP)[j].value.asChildren.count), &((*dataP)[j].value.asChildren.array), cfg, targetP); (*dataP)[j].type = LWM2M_TYPE_OBJECT_INSTANCE; (*dataP)[j].id = instanceP->id; j++; } instanceP = instanceP->next; i++; } } if (forbidden != NULL) { lwm2m_free(forbidden); } } LOG_ARG("result: %u.%2u, size: %d", (result & 0xFF) >> 5, (result & 0x1F), *sizeP); return result; } uint8_t object_read(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_media_type_t *formatP, uint8_t **bufferP, size_t *lengthP, uint16_t serverId) { uint8_t result; lwm2m_data_t *dataP = NULL; int size = 0; int res; LOG_URI(uriP); result = object_readData(contextP, uriP, &size, &dataP, NULL, serverId); if (result == COAP_205_CONTENT) { res = lwm2m_data_serialize(uriP, size, dataP, formatP, bufferP); if (res < 0) { result = COAP_500_INTERNAL_SERVER_ERROR; } else { *lengthP = (size_t)res; } } lwm2m_data_free(size, dataP); LOG_ARG("result: %u.%2u, length: %d", (result & 0xFF) >> 5, (result & 0x1F), *lengthP); return result; } uint8_t object_write(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_media_type_t format, uint8_t *buffer, size_t length) { uint8_t result = NO_ERROR; lwm2m_object_t *targetP; lwm2m_data_t *dataP = NULL; int size = 0; LOG_URI(uriP); targetP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, uriP->objectId); if (NULL == targetP) { result = COAP_404_NOT_FOUND; } else if (NULL == targetP->writeFunc) { result = COAP_405_METHOD_NOT_ALLOWED; } else { size = lwm2m_data_parse(uriP, buffer, length, format, &dataP); if (size == 0) { result = COAP_406_NOT_ACCEPTABLE; } } if (result == NO_ERROR) { result = targetP->writeFunc(uriP->instanceId, size, dataP, targetP); lwm2m_data_free(size, dataP); } LOG_ARG("result: %u.%2u", (result & 0xFF) >> 5, (result & 0x1F)); return result; } uint8_t object_execute(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, uint8_t *buffer, size_t length) { lwm2m_object_t *targetP; LOG_URI(uriP); targetP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, uriP->objectId); if (NULL == targetP) return COAP_404_NOT_FOUND; if (NULL == targetP->executeFunc) return COAP_405_METHOD_NOT_ALLOWED; if (NULL == lwm2m_list_find(targetP->instanceList, uriP->instanceId)) return COAP_404_NOT_FOUND; return targetP->executeFunc(uriP->instanceId, uriP->resourceId, buffer, length, targetP); } uint8_t object_create(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_media_type_t format, uint8_t *buffer, size_t length) { lwm2m_object_t *targetP; lwm2m_data_t *dataP = NULL; int size = 0; uint8_t result; LOG_URI(uriP); if (length == 0 || buffer == 0) { return COAP_400_BAD_REQUEST; } targetP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, uriP->objectId); if (NULL == targetP) return COAP_404_NOT_FOUND; if (NULL == targetP->createFunc) return COAP_405_METHOD_NOT_ALLOWED; size = lwm2m_data_parse(uriP, buffer, length, format, &dataP); if (size <= 0) return COAP_400_BAD_REQUEST; switch (dataP[0].type) { case LWM2M_TYPE_OBJECT: result = COAP_400_BAD_REQUEST; goto exit; case LWM2M_TYPE_OBJECT_INSTANCE: if (size != 1) { result = COAP_400_BAD_REQUEST; goto exit; } if (NULL != lwm2m_list_find(targetP->instanceList, dataP[0].id)) { // Instance already exists result = COAP_406_NOT_ACCEPTABLE; goto exit; } result = targetP->createFunc(dataP[0].id, dataP[0].value.asChildren.count, dataP[0].value.asChildren.array, targetP); uriP->instanceId = dataP[0].id; uriP->flag |= LWM2M_URI_FLAG_INSTANCE_ID; break; default: if (!LWM2M_URI_IS_SET_INSTANCE(uriP)) { uriP->instanceId = lwm2m_list_newId(targetP->instanceList); uriP->flag |= LWM2M_URI_FLAG_INSTANCE_ID; } result = targetP->createFunc(uriP->instanceId, size, dataP, targetP); break; } exit: lwm2m_data_free(size, dataP); LOG_ARG("result: %u.%2u", (result & 0xFF) >> 5, (result & 0x1F)); return result; } uint8_t object_delete(lwm2m_context_t *contextP, lwm2m_uri_t *uriP) { lwm2m_object_t *objectP; uint8_t result; LOG_URI(uriP); objectP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, uriP->objectId); if (NULL == objectP) return COAP_404_NOT_FOUND; if (NULL == objectP->deleteFunc) return COAP_405_METHOD_NOT_ALLOWED; LOG("Entering"); if (LWM2M_URI_IS_SET_INSTANCE(uriP)) { result = objectP->deleteFunc(uriP->instanceId, objectP); if (result == COAP_202_DELETED) { observe_clear(contextP, uriP); } } else { lwm2m_list_t *instanceP; result = COAP_202_DELETED; instanceP = objectP->instanceList; while (NULL != instanceP && result == COAP_202_DELETED) { uriP->instanceId = instanceP->id; result = objectP->deleteFunc(instanceP->id, objectP); if (result == COAP_202_DELETED) { uriP->flag |= LWM2M_URI_FLAG_INSTANCE_ID; observe_clear(contextP, uriP); uriP->flag &= ~LWM2M_URI_FLAG_INSTANCE_ID; } instanceP = objectP->instanceList; } } LOG_ARG("result: %u.%2u", (result & 0xFF) >> 5, (result & 0x1F)); return result; } uint8_t object_discover(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_server_t *serverP, uint8_t **bufferP, size_t *lengthP) { uint8_t result; lwm2m_object_t *targetP; lwm2m_data_t *dataP = NULL; int size = 0; LOG_URI(uriP); targetP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, uriP->objectId); if (NULL == targetP) return COAP_404_NOT_FOUND; if (NULL == targetP->discoverFunc) return COAP_501_NOT_IMPLEMENTED; if (LWM2M_URI_IS_SET_INSTANCE(uriP)) { if (NULL == lwm2m_list_find(targetP->instanceList, uriP->instanceId)) return COAP_404_NOT_FOUND; // single instance read if (LWM2M_URI_IS_SET_RESOURCE(uriP)) { size = 1; dataP = lwm2m_data_new(size); if (dataP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; dataP->id = uriP->resourceId; } result = targetP->discoverFunc(uriP->instanceId, &size, &dataP, targetP); } else { // multiple object instances read lwm2m_list_t *instanceP; int i; result = COAP_205_CONTENT; size = 0; for (instanceP = targetP->instanceList; instanceP != NULL ; instanceP = instanceP->next) { size++; } if (size != 0) { dataP = lwm2m_data_new(size); if (dataP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; instanceP = targetP->instanceList; i = 0; while (instanceP != NULL && result == COAP_205_CONTENT) { result = targetP->discoverFunc(instanceP->id, (int *) & (dataP[i].value.asChildren.count), &(dataP[i].value.asChildren.array), targetP); dataP[i].type = LWM2M_TYPE_OBJECT_INSTANCE; dataP[i].id = instanceP->id; i++; instanceP = instanceP->next; } } } if (result == COAP_205_CONTENT) { int len; len = discover_serialize(contextP, uriP, serverP, size, dataP, bufferP); if (len <= 0) result = COAP_500_INTERNAL_SERVER_ERROR; else *lengthP = len; } lwm2m_data_free(size, dataP); LOG_ARG("result: %u.%2u", (result & 0xFF) >> 5, (result & 0x1F)); return result; } bool object_isInstanceNew(lwm2m_context_t *contextP, uint16_t objectId, uint16_t instanceId) { lwm2m_object_t *targetP; LOG("Entering"); targetP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, objectId); if (targetP != NULL) { if (NULL != lwm2m_list_find(targetP->instanceList, instanceId)) { return false; } } return true; } static int prv_getObjectTemplate(uint8_t *buffer, size_t length, uint16_t id) { int index; int result; if (length < REG_OBJECT_MIN_LEN) return -1; buffer[0] = '<'; buffer[1] = '/'; index = 2; result = utils_intToText(id, buffer + index, length - index); if (result == 0) return -1; index += result; if (length - index < REG_OBJECT_MIN_LEN - 3) return -1; buffer[index] = '/'; index++; return index; } int object_getRegisterPayloadBufferLength(lwm2m_context_t *contextP) { size_t index; int result; lwm2m_object_t *objectP; char buffer[REG_OBJECT_MIN_LEN + 5]; LOG("Entering"); index = strlen(REG_START); if ((contextP->altPath != NULL) && (contextP->altPath[0] != 0)) { index += strlen(contextP->altPath); } else { index += strlen(REG_DEFAULT_PATH); // "/" } index += strlen(REG_LWM2M_RESOURCE_TYPE);//">;rt=\"oma.lwm2m\";ct=11543," for (objectP = contextP->objectList; objectP != NULL; objectP = objectP->next) { size_t start; size_t length; if (objectP->objID == LWM2M_SECURITY_OBJECT_ID) continue; start = index; result = prv_getObjectTemplate((uint8_t *)buffer, sizeof(buffer), objectP->objID); if (result < 0) return 0; length = result; index += length; if (objectP->instanceList == NULL) { index -= 1; index += strlen(REG_PATH_END); //">," } else { lwm2m_list_t *targetP; for (targetP = objectP->instanceList ; targetP != NULL ; targetP = targetP->next) { if (index != start + length) { index += length; } result = utils_intToText(targetP->id, (uint8_t *)buffer, sizeof(buffer)); if (result == 0) return 0; index += result; index += strlen(REG_PATH_END); } } } index += 1; // account for trailing null // Note that object_getRegisterPayload() has REG_PATH_END added after each // object or instance, and then the trailing comma is replaced by null. The // trailing nulls are not counted as part of the payload length, so this // will return a size two bytes greater than what // object_getRegisterPayload() returns. return index; } int object_getRegisterPayload(lwm2m_context_t *contextP, uint8_t *buffer, size_t bufferLen) { size_t index; int result; lwm2m_object_t *objectP; LOG("Entering"); // index can not be greater than bufferLen index = 0; result = utils_stringCopy((char *)buffer, bufferLen, REG_START); if (result < 0) return 0; index += result; if ((contextP->altPath != NULL) && (contextP->altPath[0] != 0)) { result = utils_stringCopy((char *)buffer + index, bufferLen - index, contextP->altPath); } else { result = utils_stringCopy((char *)buffer + index, bufferLen - index, REG_DEFAULT_PATH); } if (result < 0) return 0; index += result; result = utils_stringCopy((char *)buffer + index, bufferLen - index, REG_LWM2M_RESOURCE_TYPE); if (result < 0) return 0; index += result; for (objectP = contextP->objectList; objectP != NULL; objectP = objectP->next) { size_t start; size_t length; if (objectP->objID == LWM2M_SECURITY_OBJECT_ID) continue; start = index; result = prv_getObjectTemplate(buffer + index, bufferLen - index, objectP->objID); if (result < 0) return 0; length = result; index += length; if (objectP->instanceList == NULL) { index--; result = utils_stringCopy((char *)buffer + index, bufferLen - index, REG_PATH_END); if (result < 0) return 0; index += result; } else { lwm2m_list_t *targetP; for (targetP = objectP->instanceList ; targetP != NULL ; targetP = targetP->next) { if (index != start + length) { if (bufferLen - index <= length) return 0; memcpy(buffer + index, buffer + start, length); index += length; } result = utils_intToText(targetP->id, buffer + index, bufferLen - index); if (result == 0) return 0; index += result; result = utils_stringCopy((char *)buffer + index, bufferLen - index, REG_PATH_END); if (result < 0) return 0; index += result; } } } if (index > 0) { index = index - 1; // remove trailing ',' } buffer[index] = 0; return index; } static lwm2m_list_t *prv_findServerInstance(lwm2m_object_t *objectP, uint16_t shortID) { lwm2m_list_t *instanceP; instanceP = objectP->instanceList; while (NULL != instanceP) { int64_t value; lwm2m_data_t *dataP; int size; size = 1; dataP = lwm2m_data_new(size); if (dataP == NULL) return NULL; dataP->id = LWM2M_SERVER_SHORT_ID_ID; if (objectP->readFunc(instanceP->id, &size, &dataP, NULL, objectP) != COAP_205_CONTENT) { lwm2m_data_free(size, dataP); return NULL; } if (1 == lwm2m_data_decode_int(dataP, &value)) { if (value == shortID) { lwm2m_data_free(size, dataP); break; } } lwm2m_data_free(size, dataP); instanceP = instanceP->next; } return instanceP; } static int prv_getMandatoryInfo(lwm2m_object_t *objectP, uint16_t instanceID, lwm2m_server_t *targetP) { lwm2m_data_t *dataP; int size; int64_t value; size = 2; dataP = lwm2m_data_new(size); if (dataP == NULL) return -1; dataP[0].id = LWM2M_SERVER_LIFETIME_ID; dataP[1].id = LWM2M_SERVER_BINDING_ID; if (objectP->readFunc(instanceID, &size, &dataP, NULL, objectP) != COAP_205_CONTENT) { lwm2m_data_free(size, dataP); return -1; } if (0 == lwm2m_data_decode_int(dataP, &value) || value < 0 || value > 0xFFFFFFFF) // This is an implementation limit { lwm2m_data_free(size, dataP); return -1; } targetP->lifetime = value; targetP->binding = utils_stringToBinding(dataP[1].value.asBuffer.buffer, dataP[1].value.asBuffer.length); lwm2m_data_free(size, dataP); if (targetP->binding == BINDING_UNKNOWN) { return -1; } return 0; } int object_getServers(lwm2m_context_t *contextP, bool checkOnly) { lwm2m_object_t *objectP; lwm2m_object_t *securityObjP = NULL; lwm2m_object_t *serverObjP = NULL; lwm2m_list_t *securityInstP; // instanceID of the server in the LWM2M Security Object LOG("Entering"); for (objectP = contextP->objectList; objectP != NULL; objectP = objectP->next) { if (objectP->objID == LWM2M_SECURITY_OBJECT_ID) { securityObjP = objectP; } else if (objectP->objID == LWM2M_SERVER_OBJECT_ID) { serverObjP = objectP; } } if (NULL == securityObjP) return -1; securityInstP = securityObjP->instanceList; while (securityInstP != NULL) { if (LWM2M_LIST_FIND(contextP->bootstrapServerList, securityInstP->id) == NULL && LWM2M_LIST_FIND(contextP->serverList, securityInstP->id) == NULL) { // This server is new. eg created by last bootstrap lwm2m_data_t *dataP; int size; lwm2m_server_t *targetP; bool isBootstrap; int64_t value = 0; size = 3; dataP = lwm2m_data_new(size); if (dataP == NULL) return -1; dataP[0].id = LWM2M_SECURITY_BOOTSTRAP_ID; dataP[1].id = LWM2M_SECURITY_SHORT_SERVER_ID; dataP[2].id = LWM2M_SECURITY_HOLD_OFF_ID; if (securityObjP->readFunc(securityInstP->id, &size, &dataP, NULL, securityObjP) != COAP_205_CONTENT) { LOG_ARG("securityObjP->readFunc fail id %d", securityInstP->id); lwm2m_data_free(size, dataP); return -1; } targetP = (lwm2m_server_t *)lwm2m_malloc(sizeof(lwm2m_server_t)); if (targetP == NULL) { LOG_ARG("lwm2m_malloc fail id %d", securityInstP->id); lwm2m_data_free(size, dataP); return -1; } memset(targetP, 0, sizeof(lwm2m_server_t)); targetP->secObjInstID = securityInstP->id; if (0 == lwm2m_data_decode_bool(dataP + 0, &isBootstrap)) { LOG_ARG("lwm2m_data_decode_bool fail id %d", securityInstP->id); lwm2m_free(targetP); lwm2m_data_free(size, dataP); return -1; } if (0 == lwm2m_data_decode_int(dataP + 1, &value) || value < (isBootstrap ? 0 : 1) || value > 0xFFFF) // 0 is forbidden as a Short Server ID { LOG_ARG("lwm2m_data_decode_int fail id %d", securityInstP->id); lwm2m_free(targetP); lwm2m_data_free(size, dataP); return -1; } targetP->shortID = value; if (isBootstrap == true) { if (0 == lwm2m_data_decode_int(dataP + 2, &value) || value < 0 || value > 0xFFFFFFFF) // This is an implementation limit { LOG_ARG("lwm2m_data_decode_int fail id %d", securityInstP->id); lwm2m_free(targetP); lwm2m_data_free(size, dataP); return -1; } // lifetime of a bootstrap server is set to ClientHoldOffTime targetP->lifetime = value; if (checkOnly) { lwm2m_free(targetP); } else { contextP->bootstrapServerList = (lwm2m_server_t *)LWM2M_LIST_ADD(contextP->bootstrapServerList, targetP); } } else { lwm2m_list_t *serverInstP; // instanceID of the server in the LWM2M Server Object serverInstP = prv_findServerInstance(serverObjP, targetP->shortID); if (serverInstP == NULL) { lwm2m_free(targetP); } else { if (0 != prv_getMandatoryInfo(serverObjP, serverInstP->id, targetP)) { LOG_ARG("prv_getMandatoryInfo fail id %d", securityInstP->id); lwm2m_free(targetP); lwm2m_data_free(size, dataP); return -1; } targetP->status = STATE_DEREGISTERED; if (checkOnly) { lwm2m_free(targetP); } else { contextP->serverList = (lwm2m_server_t *)LWM2M_LIST_ADD(contextP->serverList, targetP); } } } lwm2m_data_free(size, dataP); } securityInstP = securityInstP->next; } return 0; } #ifdef LWM2M_BOOTSTRAP uint8_t object_createInstance(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_data_t *dataP) { lwm2m_object_t *targetP; LOG_URI(uriP); targetP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, uriP->objectId); if (NULL == targetP) return COAP_404_NOT_FOUND; if (NULL == targetP->createFunc) { return COAP_405_METHOD_NOT_ALLOWED; } return targetP->createFunc(lwm2m_list_newId(targetP->instanceList), dataP->value.asChildren.count, dataP->value.asChildren.array, targetP); } uint8_t object_writeInstance(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_data_t *dataP) { lwm2m_object_t *targetP; LOG_URI(uriP); targetP = (lwm2m_object_t *)LWM2M_LIST_FIND(contextP->objectList, uriP->objectId); if (NULL == targetP) return COAP_404_NOT_FOUND; if (NULL == targetP->writeFunc) { return COAP_405_METHOD_NOT_ALLOWED; } return targetP->writeFunc(dataP->id, dataP->value.asChildren.count, dataP->value.asChildren.array, targetP); } #endif #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/observe.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Toby Jaffey - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * *******************************************************************************/ /* Copyright (c) 2013, 2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. David Navarro */ #include "internals.h" #include "osdepends/atiny_osdep.h" #include #ifdef LWM2M_CLIENT_MODE #define RES_M_STATE 3 static lwm2m_transaction_callback_t observe_call_back; void lwm2m_register_observe_ack_call_back(lwm2m_transaction_callback_t callback) { observe_call_back = callback; } static lwm2m_observed_t *prv_findObserved(lwm2m_context_t *contextP, lwm2m_uri_t *uriP) { lwm2m_observed_t *targetP; targetP = contextP->observedList; while (targetP != NULL && (targetP->uri.objectId != uriP->objectId || targetP->uri.flag != uriP->flag || (LWM2M_URI_IS_SET_INSTANCE(uriP) && targetP->uri.instanceId != uriP->instanceId) || (LWM2M_URI_IS_SET_RESOURCE(uriP) && targetP->uri.resourceId != uriP->resourceId))) { targetP = targetP->next; } return targetP; } static void prv_unlinkObserved(lwm2m_context_t *contextP, lwm2m_observed_t *observedP) { if (contextP->observedList == observedP) { contextP->observedList = contextP->observedList->next; } else { lwm2m_observed_t *parentP; parentP = contextP->observedList; while (parentP->next != NULL && parentP->next != observedP) { parentP = parentP->next; } if (parentP->next != NULL) { parentP->next = parentP->next->next; } } } static lwm2m_watcher_t *prv_findWatcher(lwm2m_observed_t *observedP, lwm2m_server_t *serverP) { lwm2m_watcher_t *targetP; targetP = observedP->watcherList; while (targetP != NULL && targetP->server != serverP) { targetP = targetP->next; } return targetP; } static lwm2m_watcher_t *prv_getWatcher(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_server_t *serverP) { lwm2m_observed_t *observedP; bool allocatedObserver; lwm2m_watcher_t *watcherP; allocatedObserver = false; observedP = prv_findObserved(contextP, uriP); if (observedP == NULL) { observedP = (lwm2m_observed_t *)lwm2m_malloc(sizeof(lwm2m_observed_t)); if (observedP == NULL) return NULL; allocatedObserver = true; memset(observedP, 0, sizeof(lwm2m_observed_t)); memcpy(&(observedP->uri), uriP, sizeof(lwm2m_uri_t)); atiny_mutex_lock(contextP->observe_mutex); observedP->next = contextP->observedList; contextP->observedList = observedP; atiny_mutex_unlock(contextP->observe_mutex); } watcherP = prv_findWatcher(observedP, serverP); if (watcherP == NULL) { watcherP = (lwm2m_watcher_t *)lwm2m_malloc(sizeof(lwm2m_watcher_t)); if (watcherP == NULL) { if (allocatedObserver == true) { lwm2m_free(observedP); } return NULL; } memset(watcherP, 0, sizeof(lwm2m_watcher_t)); watcherP->active = false; watcherP->server = serverP; atiny_mutex_lock(contextP->observe_mutex); watcherP->next = observedP->watcherList; observedP->watcherList = watcherP; atiny_mutex_unlock(contextP->observe_mutex); } return watcherP; } uint8_t observe_handleRequest(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_server_t *serverP, int size, lwm2m_data_t *dataP, coap_packet_t *message, coap_packet_t *response) { lwm2m_observed_t * observedP; lwm2m_watcher_t *watcherP; uint32_t count; LOG_ARG("Code: %02X, server status: %s", message->code, STR_STATUS(serverP->status)); LOG_URI(uriP); coap_get_header_observe(message, &count); switch (count) { case 0: if (!LWM2M_URI_IS_SET_INSTANCE(uriP) && LWM2M_URI_IS_SET_RESOURCE(uriP)) return COAP_400_BAD_REQUEST; if (message->token_len == 0) return COAP_400_BAD_REQUEST; watcherP = prv_getWatcher(contextP, uriP, serverP); if (watcherP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; watcherP->tokenLen = message->token_len; memcpy(watcherP->token, message->token, message->token_len); watcherP->active = true; watcherP->lastTime = lwm2m_gettime(); watcherP->lastMid = response->mid; if (IS_OPTION(message, COAP_OPTION_ACCEPT)) { watcherP->format = utils_convertMediaType((coap_content_type_t)message->accept[0]); } else { watcherP->format = LWM2M_CONTENT_TLV; } if (LWM2M_URI_IS_SET_RESOURCE(uriP)) { switch (dataP->type) { case LWM2M_TYPE_INTEGER: if (1 != lwm2m_data_decode_int(dataP, &(watcherP->lastValue.asInteger))) return COAP_500_INTERNAL_SERVER_ERROR; break; case LWM2M_TYPE_FLOAT: if (1 != lwm2m_data_decode_float(dataP, &(watcherP->lastValue.asFloat))) return COAP_500_INTERNAL_SERVER_ERROR; break; default: break; } } coap_set_header_observe(response, watcherP->counter++); return COAP_205_CONTENT; case 1: // cancellation observedP = prv_findObserved(contextP, uriP); if (observedP) { watcherP = prv_findWatcher(observedP, serverP); if (watcherP) { observe_cancel(contextP, watcherP->lastMid, serverP->sessionH); } } return COAP_205_CONTENT; default: return COAP_400_BAD_REQUEST; } } void observe_cancel(lwm2m_context_t *contextP, uint16_t mid, void *fromSessionH) { lwm2m_observed_t *observedP; LOG_ARG("mid: %d", mid); for (observedP = contextP->observedList; observedP != NULL; observedP = observedP->next) { lwm2m_watcher_t *targetP = NULL; if (observedP->watcherList->lastMid == mid && lwm2m_session_is_equal(observedP->watcherList->server->sessionH, fromSessionH, contextP->userData)) { targetP = observedP->watcherList; observedP->watcherList = observedP->watcherList->next; } else { lwm2m_watcher_t *parentP; parentP = observedP->watcherList; while (parentP->next != NULL && (parentP->next->lastMid != mid || !lwm2m_session_is_equal(parentP->next->server->sessionH, fromSessionH, contextP->userData))) { parentP = parentP->next; } if (parentP->next != NULL) { targetP = parentP->next; parentP->next = parentP->next->next; } } if (targetP != NULL) { atiny_mutex_lock(contextP->observe_mutex); lwm2m_notify_even(MODULE_URI, OBSERVE_UNSUBSCRIBE, (char *) & (observedP->uri), sizeof(observedP->uri)); if (targetP->parameters != NULL) lwm2m_free(targetP->parameters); lwm2m_free(targetP); if (observedP->watcherList == NULL) { prv_unlinkObserved(contextP, observedP); lwm2m_free(observedP); } atiny_mutex_unlock(contextP->observe_mutex); return; } } } void observe_clear(lwm2m_context_t *contextP, lwm2m_uri_t *uriP) { lwm2m_observed_t *observedP; LOG_URI(uriP); observedP = contextP->observedList; while(observedP != NULL) { if (observedP->uri.objectId == uriP->objectId && (LWM2M_URI_IS_SET_INSTANCE(uriP) == false || observedP->uri.instanceId == uriP->instanceId)) { lwm2m_observed_t *nextP; lwm2m_watcher_t *watcherP; atiny_mutex_lock(contextP->observe_mutex); nextP = observedP->next; for (watcherP = observedP->watcherList; watcherP != NULL; watcherP = watcherP->next) { if (watcherP->parameters != NULL) lwm2m_free(watcherP->parameters); } LWM2M_LIST_FREE(observedP->watcherList); prv_unlinkObserved(contextP, observedP); lwm2m_free(observedP); observedP = nextP; atiny_mutex_unlock(contextP->observe_mutex); } else { observedP = observedP->next; } } } uint8_t observe_setParameters(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, lwm2m_server_t *serverP, lwm2m_attributes_t *attrP) { uint8_t result; lwm2m_watcher_t *watcherP; LOG_URI(uriP); LOG_ARG("toSet: %08X, toClear: %08X, minPeriod: %d, maxPeriod: %d, greaterThan: %f, lessThan: %f, step: %f", attrP->toSet, attrP->toClear, attrP->minPeriod, attrP->maxPeriod, attrP->greaterThan, attrP->lessThan, attrP->step); if (!LWM2M_URI_IS_SET_INSTANCE(uriP) && LWM2M_URI_IS_SET_RESOURCE(uriP)) return COAP_400_BAD_REQUEST; result = object_checkReadable(contextP, uriP); if (COAP_205_CONTENT != result) return result; if (0 != (attrP->toSet & ATTR_FLAG_NUMERIC)) { result = object_checkNumeric(contextP, uriP); if (COAP_205_CONTENT != result) return result; } watcherP = prv_getWatcher(contextP, uriP, serverP); if (watcherP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; // Check rule “lt?value + 2*”stp?values < “gt?value if ((((attrP->toSet | (watcherP->parameters ? watcherP->parameters->toSet : 0)) & ~attrP->toClear) & ATTR_FLAG_NUMERIC) == ATTR_FLAG_NUMERIC) { float gt; float lt; float stp; if (0 != (attrP->toSet & LWM2M_ATTR_FLAG_GREATER_THAN)) { gt = attrP->greaterThan; } else { gt = watcherP->parameters->greaterThan; } if (0 != (attrP->toSet & LWM2M_ATTR_FLAG_LESS_THAN)) { lt = attrP->lessThan; } else { lt = watcherP->parameters->lessThan; } if (0 != (attrP->toSet & LWM2M_ATTR_FLAG_STEP)) { stp = attrP->step; } else { stp = watcherP->parameters->step; } if (lt + (2 * stp) >= gt) return COAP_400_BAD_REQUEST; } if (watcherP->parameters == NULL) { if (attrP->toSet != 0) { watcherP->parameters = (lwm2m_attributes_t *)lwm2m_malloc(sizeof(lwm2m_attributes_t)); if (watcherP->parameters == NULL) return COAP_500_INTERNAL_SERVER_ERROR; memcpy(watcherP->parameters, attrP, sizeof(lwm2m_attributes_t)); } } else { watcherP->parameters->toSet &= ~attrP->toClear; if (attrP->toSet & LWM2M_ATTR_FLAG_MIN_PERIOD) { watcherP->parameters->minPeriod = attrP->minPeriod; } if (attrP->toSet & LWM2M_ATTR_FLAG_MAX_PERIOD) { watcherP->parameters->maxPeriod = attrP->maxPeriod; } if (attrP->toSet & LWM2M_ATTR_FLAG_GREATER_THAN) { watcherP->parameters->greaterThan = attrP->greaterThan; } if (attrP->toSet & LWM2M_ATTR_FLAG_LESS_THAN) { watcherP->parameters->lessThan = attrP->lessThan; } if (attrP->toSet & LWM2M_ATTR_FLAG_STEP) { watcherP->parameters->step = attrP->step; } } LOG_ARG("Final toSet: %08X, minPeriod: %d, maxPeriod: %d, greaterThan: %f, lessThan: %f, step: %f", watcherP->parameters->toSet, watcherP->parameters->minPeriod, watcherP->parameters->maxPeriod, watcherP->parameters->greaterThan, watcherP->parameters->lessThan, watcherP->parameters->step); return COAP_204_CHANGED; } lwm2m_observed_t *observe_findByUri(lwm2m_context_t *contextP, lwm2m_uri_t *uriP) { lwm2m_observed_t *targetP; LOG_URI(uriP); targetP = contextP->observedList; while (targetP != NULL) { if (targetP->uri.objectId == uriP->objectId) { if ((!LWM2M_URI_IS_SET_INSTANCE(uriP) && !LWM2M_URI_IS_SET_INSTANCE(&(targetP->uri))) || (LWM2M_URI_IS_SET_INSTANCE(uriP) && LWM2M_URI_IS_SET_INSTANCE(&(targetP->uri)) && (uriP->instanceId == targetP->uri.instanceId))) { if ((!LWM2M_URI_IS_SET_RESOURCE(uriP) && !LWM2M_URI_IS_SET_RESOURCE(&(targetP->uri))) || (LWM2M_URI_IS_SET_RESOURCE(uriP) && LWM2M_URI_IS_SET_RESOURCE(&(targetP->uri)) && (uriP->resourceId == targetP->uri.resourceId))) { LOG_ARG("Found one with%s observers.", targetP->watcherList ? "" : " no"); LOG_URI(&(targetP->uri)); return targetP; } } } targetP = targetP->next; } LOG("Found nothing"); return NULL; } void lwm2m_resource_value_changed(lwm2m_context_t *contextP, lwm2m_uri_t *uriP) { lwm2m_observed_t *targetP; LOG_URI(uriP); targetP = contextP->observedList; while (targetP != NULL) { if (targetP->uri.objectId == uriP->objectId) { if (!LWM2M_URI_IS_SET_INSTANCE(uriP) || (targetP->uri.flag & LWM2M_URI_FLAG_INSTANCE_ID) == 0 || uriP->instanceId == targetP->uri.instanceId) { if (!LWM2M_URI_IS_SET_RESOURCE(uriP) || (targetP->uri.flag & LWM2M_URI_FLAG_RESOURCE_ID) == 0 || uriP->resourceId == targetP->uri.resourceId) { lwm2m_watcher_t *watcherP; LOG("Found an observation"); LOG_URI(&(targetP->uri)); for (watcherP = targetP->watcherList ; watcherP != NULL ; watcherP = watcherP->next) { if (watcherP->active == true) { LOG("Tagging a watcher"); watcherP->update = true; } } } } } targetP = targetP->next; } } int observe_send_transaction(lwm2m_context_t *contextP, lwm2m_data_cfg_t *cfg, lwm2m_watcher_t *watcherP, uint8_t *buffer, size_t length) { lwm2m_transaction_t *transaction; int ret; transaction = transaction_new(watcherP->server->sessionH, COAP_205_CONTENT, NULL, NULL, watcherP->lastMid, watcherP->tokenLen, watcherP->token); if(NULL == transaction) { LOG("transaction_new null"); return COAP_500_INTERNAL_SERVER_ERROR; } transaction->cfg.callback = cfg->callback; transaction->cfg.cookie = cfg->cookie; transaction->cfg.type = cfg->type; transaction->callback = observe_call_back; coap_set_header_content_type(transaction->message, watcherP->format); coap_set_header_observe(transaction->message, watcherP->counter++); coap_set_payload(transaction->message, buffer, length); contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transaction); ret = transaction_send(contextP, transaction); LOG_ARG("notify con msg, cookie:%d type:%d,ret:%d", transaction->cfg.cookie, transaction->cfg.type, ret); return ret; } void observe_app_step(lwm2m_context_t *contextP, lwm2m_observed_t *targetP, time_t currentTime, time_t *timeoutP) { LOG("Entering"); lwm2m_watcher_t *watcherP; uint8_t *buffer = NULL; size_t length = 0; lwm2m_data_t *dataP = NULL; lwm2m_data_cfg_t cfg = {0, 0, NULL}; int size = 0; while (COAP_205_CONTENT == object_readData(contextP, &targetP->uri, &size, &dataP, &cfg, 0)) { for (watcherP = targetP->watcherList ; watcherP != NULL ; watcherP = watcherP->next) { int res; if (buffer == NULL) { res = lwm2m_data_serialize(&targetP->uri, size, dataP, &(watcherP->format), &buffer); if (res < 0) { if (dataP != NULL) { lwm2m_data_free(size, dataP); dataP = NULL; } if (buffer != NULL) { lwm2m_free(buffer); } break; } else { length = (size_t)res; } } if (watcherP->active == true) { watcherP->lastTime = currentTime; watcherP->lastMid = contextP->nextMID++; if (cfg.callback == NULL) { coap_packet_t message[1]; coap_init_message(message, COAP_TYPE_NON, COAP_205_CONTENT, 0); coap_set_header_content_type(message, watcherP->format); coap_set_payload(message, buffer, length); message->mid = watcherP->lastMid; coap_set_header_token(message, watcherP->token, watcherP->tokenLen); coap_set_header_observe(message, watcherP->counter++); (void)message_send(contextP, message, watcherP->server->sessionH); LOG_ARG("notify no con msg, msgid:", message->mid); } else { (void)observe_send_transaction(contextP, &cfg, watcherP, buffer, length); } } } if (dataP != NULL) { lwm2m_data_free(size, dataP); dataP = NULL; } if (buffer != NULL) { lwm2m_free(buffer); buffer = NULL; } } if (dataP != NULL) { lwm2m_data_free(size, dataP); } } void observe_step(lwm2m_context_t *contextP, time_t currentTime, time_t *timeoutP) { lwm2m_observed_t *targetP; LOG("Entering"); for (targetP = contextP->observedList ; targetP != NULL ; targetP = targetP->next) { lwm2m_watcher_t *watcherP; uint8_t *buffer = NULL; size_t length = 0; lwm2m_data_t *dataP = NULL; lwm2m_data_cfg_t cfg = {0, 0, NULL}; int size = 0; double floatValue = 0; int64_t integerValue = 0; bool storeValue = false; coap_packet_t message[1]; time_t interval; LOG_URI(&(targetP->uri)); if (dm_isUriOpaqueHandle(&(targetP->uri))) { observe_app_step(contextP, targetP, currentTime, timeoutP); continue; } cfg.callback = NULL; if (LWM2M_URI_IS_SET_RESOURCE(&targetP->uri)) { if (COAP_205_CONTENT != object_readData(contextP, &targetP->uri, &size, &dataP, &cfg, 0)) continue; switch (dataP->type) { case LWM2M_TYPE_INTEGER: if (1 != lwm2m_data_decode_int(dataP, &integerValue)) { lwm2m_data_free(size, dataP); continue; } storeValue = true; break; case LWM2M_TYPE_FLOAT: if (1 != lwm2m_data_decode_float(dataP, &floatValue)) { lwm2m_data_free(size, dataP); continue; } storeValue = true; break; default: break; } } for (watcherP = targetP->watcherList ; watcherP != NULL ; watcherP = watcherP->next) { if (watcherP->active == true) { bool notify = false; if (watcherP->update == true) { // value changed, should we notify the server ? if (watcherP->parameters == NULL || watcherP->parameters->toSet == 0) { // no conditions notify = true; LOG("Notify with no conditions"); LOG_URI(&(targetP->uri)); } if (notify == false && watcherP->parameters != NULL && (watcherP->parameters->toSet & ATTR_FLAG_NUMERIC) != 0) { if ((watcherP->parameters->toSet & LWM2M_ATTR_FLAG_LESS_THAN) != 0) { LOG("Checking lower threshold"); // Did we cross the lower threshold ? switch (dataP->type) { case LWM2M_TYPE_INTEGER: if ((integerValue <= watcherP->parameters->lessThan && watcherP->lastValue.asInteger > watcherP->parameters->lessThan) || (integerValue >= watcherP->parameters->lessThan && watcherP->lastValue.asInteger < watcherP->parameters->lessThan)) { LOG("Notify on lower threshold crossing"); notify = true; } break; case LWM2M_TYPE_FLOAT: if ((floatValue <= watcherP->parameters->lessThan && watcherP->lastValue.asFloat > watcherP->parameters->lessThan) || (floatValue >= watcherP->parameters->lessThan && watcherP->lastValue.asFloat < watcherP->parameters->lessThan)) { LOG("Notify on lower threshold crossing"); notify = true; } break; default: break; } } if ((watcherP->parameters->toSet & LWM2M_ATTR_FLAG_GREATER_THAN) != 0) { LOG("Checking upper threshold"); // Did we cross the upper threshold ? switch (dataP->type) { case LWM2M_TYPE_INTEGER: if ((integerValue <= watcherP->parameters->greaterThan && watcherP->lastValue.asInteger > watcherP->parameters->greaterThan) || (integerValue >= watcherP->parameters->greaterThan && watcherP->lastValue.asInteger < watcherP->parameters->greaterThan)) { LOG("Notify on lower upper crossing"); notify = true; } break; case LWM2M_TYPE_FLOAT: if ((floatValue <= watcherP->parameters->greaterThan && watcherP->lastValue.asFloat > watcherP->parameters->greaterThan) || (floatValue >= watcherP->parameters->greaterThan && watcherP->lastValue.asFloat < watcherP->parameters->greaterThan)) { LOG("Notify on lower upper crossing"); notify = true; } break; default: break; } } if ((watcherP->parameters->toSet & LWM2M_ATTR_FLAG_STEP) != 0) { LOG("Checking step"); switch (dataP->type) { case LWM2M_TYPE_INTEGER: { int64_t diff; diff = integerValue - watcherP->lastValue.asInteger; if ((diff < 0 && (0 - diff) >= watcherP->parameters->step) || (diff >= 0 && diff >= watcherP->parameters->step)) { LOG("Notify on step condition"); notify = true; } } break; case LWM2M_TYPE_FLOAT: { double diff; diff = floatValue - watcherP->lastValue.asFloat; if ((diff < 0 && (0 - diff) >= watcherP->parameters->step) || (diff >= 0 && diff >= watcherP->parameters->step)) { LOG("Notify on step condition"); notify = true; } } break; default: break; } } } if (watcherP->parameters != NULL && (watcherP->parameters->toSet & LWM2M_ATTR_FLAG_MIN_PERIOD) != 0) { LOG_ARG("Checking minimal period (%d s)", watcherP->parameters->minPeriod); if (watcherP->lastTime + watcherP->parameters->minPeriod > currentTime) { // Minimum Period did not elapse yet interval = watcherP->lastTime + watcherP->parameters->minPeriod - currentTime; if (*timeoutP > interval) *timeoutP = interval; notify = false; } else { LOG("Notify on minimal period"); notify = true; } } } // Is the Maximum Period reached ? if (notify == false && watcherP->parameters != NULL && (watcherP->parameters->toSet & LWM2M_ATTR_FLAG_MAX_PERIOD) != 0) { LOG_ARG("Checking maximal period (%d s)", watcherP->parameters->maxPeriod); if (watcherP->lastTime + watcherP->parameters->maxPeriod <= currentTime) { LOG("Notify on maximal period"); notify = true; } } if (notify == true) { if (buffer == NULL) { if (dataP != NULL) { int res; res = lwm2m_data_serialize(&targetP->uri, size, dataP, &(watcherP->format), &buffer); if (res < 0) { break; } else { length = (size_t)res; } } else { if (COAP_205_CONTENT != object_read(contextP, &targetP->uri, &(watcherP->format), &buffer, &length, 0)) { buffer = NULL; break; } } if(NULL == cfg.callback) { coap_init_message(message, COAP_TYPE_NON, COAP_205_CONTENT, 0); coap_set_header_content_type(message, watcherP->format); coap_set_payload(message, buffer, length); LOG_ARG("non observe, msgid:", message->mid); } } watcherP->lastTime = currentTime; watcherP->lastMid = contextP->nextMID++; if(NULL == cfg.callback) { message->mid = watcherP->lastMid; coap_set_header_token(message, watcherP->token, watcherP->tokenLen); coap_set_header_observe(message, watcherP->counter++); (void)message_send(contextP, message, watcherP->server->sessionH); } else { (void)observe_send_transaction(contextP, &cfg, watcherP, buffer, length); } atiny_mutex_lock(contextP->observe_mutex); watcherP->update = false; atiny_mutex_unlock(contextP->observe_mutex); } // Store this value if (notify == true && storeValue == true) { switch (dataP->type) { case LWM2M_TYPE_INTEGER: watcherP->lastValue.asInteger = integerValue; break; case LWM2M_TYPE_FLOAT: watcherP->lastValue.asFloat = floatValue; break; default: break; } } if (watcherP->parameters != NULL && (watcherP->parameters->toSet & LWM2M_ATTR_FLAG_MAX_PERIOD) != 0) { // update timers interval = watcherP->lastTime + watcherP->parameters->maxPeriod - currentTime; if (*timeoutP > interval) *timeoutP = interval; } } } if (dataP != NULL) lwm2m_data_free(size, dataP); if (buffer != NULL) lwm2m_free(buffer); } } uint8_t lwm2m_get_observe_info(lwm2m_context_t *contextP, lwm2m_observe_info_t *observe_info) { lwm2m_observed_t *targetP; lwm2m_watcher_t *watcherP; if((NULL == observe_info) || (NULL == contextP)) { LOG("null pointer\n"); return COAP_500_INTERNAL_SERVER_ERROR; } for (targetP = contextP->observedList ; targetP != NULL ; targetP = targetP->next) { if((!LWM2M_URI_IS_SET_RESOURCE(&targetP->uri)) || (targetP->uri.objectId != LWM2M_FIRMWARE_UPDATE_OBJECT_ID) || (targetP->uri.instanceId != 0) || (targetP->uri.resourceId != RES_M_STATE)) { continue; } watcherP = targetP->watcherList; observe_info->counter = watcherP->counter; memcpy(observe_info->token, watcherP->token, sizeof(observe_info->token)); observe_info->tokenLen = watcherP->tokenLen; observe_info->format = watcherP->format; return COAP_NO_ERROR; } return COAP_500_INTERNAL_SERVER_ERROR; } uint8_t lwm2m_send_notify(lwm2m_context_t *contextP, lwm2m_observe_info_t *observe_info, int firmware_update_state, lwm2m_data_cfg_t *cfg) { lwm2m_uri_t uri; int res; lwm2m_data_t data; lwm2m_media_type_t format; uint8_t *buffer = NULL; lwm2m_server_t *server; lwm2m_watcher_t watcherP; if((NULL == observe_info) || (NULL == contextP) || (NULL == cfg)) { LOG("null pointer\n"); return COAP_500_INTERNAL_SERVER_ERROR; } server = registration_get_registered_server(contextP); if(NULL == server) { LOG("registration_get_registered_server fail\n"); return COAP_500_INTERNAL_SERVER_ERROR; } uri.objectId = LWM2M_FIRMWARE_UPDATE_OBJECT_ID; uri.instanceId = 0; uri.resourceId = RES_M_STATE; uri.flag = (LWM2M_URI_FLAG_OBJECT_ID | LWM2M_URI_FLAG_INSTANCE_ID | LWM2M_URI_FLAG_RESOURCE_ID); format = (lwm2m_media_type_t)observe_info->format; memset(&data, 0, sizeof(data)); data.id = uri.resourceId; lwm2m_data_encode_int(firmware_update_state, &data); res = lwm2m_data_serialize(&uri, 1, &data, &format, &buffer); if (res < 0) { LOG("lwm2m_data_serialize fail\n"); if (buffer != NULL) { lwm2m_free(buffer); } return COAP_500_INTERNAL_SERVER_ERROR; } memset(&watcherP, 0, sizeof(watcherP)); watcherP.lastMid = contextP->nextMID++; watcherP.tokenLen = observe_info->tokenLen; memcpy(watcherP.token, observe_info->token, sizeof(watcherP.token)); watcherP.format = format; watcherP.counter = observe_info->counter; watcherP.server = server; return (uint8_t)observe_send_transaction(contextP, cfg, &watcherP, buffer, res); } #endif #ifdef LWM2M_SERVER_MODE typedef struct { lwm2m_observation_t *observationP; lwm2m_result_callback_t callbackP; void *userDataP; } cancellation_data_t; static lwm2m_observation_t *prv_findObservationByURI(lwm2m_client_t *clientP, lwm2m_uri_t *uriP) { lwm2m_observation_t *targetP; targetP = clientP->observationList; while (targetP != NULL) { if (targetP->uri.objectId == uriP->objectId && targetP->uri.flag == uriP->flag && targetP->uri.instanceId == uriP->instanceId && targetP->uri.resourceId == uriP->resourceId) { return targetP; } targetP = targetP->next; } return targetP; } void observe_remove(lwm2m_observation_t *observationP) { LOG("Entering"); observationP->clientP->observationList = (lwm2m_observation_t *) LWM2M_LIST_RM(observationP->clientP->observationList, observationP->id, NULL); lwm2m_free(observationP); } static void prv_obsRequestCallback(lwm2m_transaction_t *transacP, void *message) { lwm2m_observation_t *observationP = (lwm2m_observation_t *)transacP->userData; coap_packet_t *packet = (coap_packet_t *)message; uint8_t code; switch (observationP->status) { case STATE_DEREG_PENDING: // Observation was canceled by the user. observe_remove(observationP); return; case STATE_REG_PENDING: observationP->status = STATE_REGISTERED; break; default: break; } if (message == NULL) { code = COAP_503_SERVICE_UNAVAILABLE; } else if (packet->code == COAP_205_CONTENT && !IS_OPTION(packet, COAP_OPTION_OBSERVE)) { code = COAP_405_METHOD_NOT_ALLOWED; } else { code = packet->code; } if (code != COAP_205_CONTENT) { observationP->callback(observationP->clientP->internalID, &observationP->uri, code, LWM2M_CONTENT_TEXT, NULL, 0, observationP->userData); observe_remove(observationP); } else { observationP->callback(observationP->clientP->internalID, &observationP->uri, 0, packet->content_type, packet->payload, packet->payload_len, observationP->userData); } } static void prv_obsCancelRequestCallback(lwm2m_transaction_t *transacP, void *message) { cancellation_data_t *cancelP = (cancellation_data_t *)transacP->userData; coap_packet_t *packet = (coap_packet_t *)message; uint8_t code; if (message == NULL) { code = COAP_503_SERVICE_UNAVAILABLE; } else { code = packet->code; } if (code != COAP_205_CONTENT) { cancelP->callbackP(cancelP->observationP->clientP->internalID, &cancelP->observationP->uri, code, LWM2M_CONTENT_TEXT, NULL, 0, cancelP->userDataP); } else { cancelP->callbackP(cancelP->observationP->clientP->internalID, &cancelP->observationP->uri, 0, packet->content_type, packet->payload, packet->payload_len, cancelP->userDataP); } observe_remove(cancelP->observationP); lwm2m_free(cancelP); } int lwm2m_observe(lwm2m_context_t *contextP, uint16_t clientID, lwm2m_uri_t *uriP, lwm2m_result_callback_t callback, void *userData) { lwm2m_client_t *clientP; lwm2m_transaction_t *transactionP; lwm2m_observation_t *observationP; uint8_t token[4]; LOG_ARG("clientID: %d", clientID); LOG_URI(uriP); if (!LWM2M_URI_IS_SET_INSTANCE(uriP) && LWM2M_URI_IS_SET_RESOURCE(uriP)) return COAP_400_BAD_REQUEST; clientP = (lwm2m_client_t *)lwm2m_list_find((lwm2m_list_t *)contextP->clientList, clientID); if (clientP == NULL) return COAP_404_NOT_FOUND; for (observationP = clientP->observationList; observationP != NULL; observationP = observationP->next) { if (uriP->objectId == observationP->uri.objectId && (LWM2M_URI_IS_SET_INSTANCE(uriP) == false || observationP->uri.instanceId == uriP->instanceId) && (LWM2M_URI_IS_SET_RESOURCE(uriP) == false || observationP->uri.resourceId == uriP->resourceId)) { break; } } if (observationP == NULL) { observationP = (lwm2m_observation_t *)lwm2m_malloc(sizeof(lwm2m_observation_t)); if (observationP == NULL) return COAP_500_INTERNAL_SERVER_ERROR; memset(observationP, 0, sizeof(lwm2m_observation_t)); observationP->id = lwm2m_list_newId((lwm2m_list_t *)clientP->observationList); memcpy(&observationP->uri, uriP, sizeof(lwm2m_uri_t)); observationP->clientP = clientP; observationP->clientP->observationList = (lwm2m_observation_t *)LWM2M_LIST_ADD(observationP->clientP->observationList, observationP); } observationP->status = STATE_REG_PENDING; observationP->callback = callback; observationP->userData = userData; token[0] = clientP->internalID >> 8; token[1] = clientP->internalID & 0xFF; token[2] = observationP->id >> 8; token[3] = observationP->id & 0xFF; transactionP = transaction_new(clientP->sessionH, COAP_GET, clientP->altPath, uriP, contextP->nextMID++, 4, token); if (transactionP == NULL) { observationP->clientP->observationList = (lwm2m_observation_t *)LWM2M_LIST_RM(observationP->clientP->observationList, observationP->id, NULL); lwm2m_free(observationP); return COAP_500_INTERNAL_SERVER_ERROR; } coap_set_header_observe(transactionP->message, 0); if (clientP->supportJSON == true) { coap_set_header_accept(transactionP->message, LWM2M_CONTENT_JSON); } else { coap_set_header_accept(transactionP->message, LWM2M_CONTENT_TLV); } transactionP->callback = prv_obsRequestCallback; transactionP->userData = (void *)observationP; contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transactionP); return transaction_send(contextP, transactionP); } int lwm2m_observe_cancel(lwm2m_context_t *contextP, uint16_t clientID, lwm2m_uri_t *uriP, lwm2m_result_callback_t callback, void *userData) { lwm2m_client_t *clientP; lwm2m_observation_t *observationP; LOG_ARG("clientID: %d", clientID); LOG_URI(uriP); clientP = (lwm2m_client_t *)lwm2m_list_find((lwm2m_list_t *)contextP->clientList, clientID); if (clientP == NULL) return COAP_404_NOT_FOUND; observationP = prv_findObservationByURI(clientP, uriP); if (observationP == NULL) return COAP_404_NOT_FOUND; switch (observationP->status) { case STATE_REGISTERED: { lwm2m_transaction_t *transactionP; cancellation_data_t *cancelP; uint8_t token[4]; token[0] = clientP->internalID >> 8; token[1] = clientP->internalID & 0xFF; token[2] = observationP->id >> 8; token[3] = observationP->id & 0xFF; transactionP = transaction_new(clientP->sessionH, COAP_GET, clientP->altPath, uriP, contextP->nextMID++, 4, token); if (transactionP == NULL) { return COAP_500_INTERNAL_SERVER_ERROR; } cancelP = (cancellation_data_t *)lwm2m_malloc(sizeof(cancellation_data_t)); if (cancelP == NULL) { lwm2m_free(transactionP); return COAP_500_INTERNAL_SERVER_ERROR; } coap_set_header_observe(transactionP->message, 1); cancelP->observationP = observationP; cancelP->callbackP = callback; cancelP->userDataP = userData; transactionP->callback = prv_obsCancelRequestCallback; transactionP->userData = (void *)cancelP; contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transactionP); return transaction_send(contextP, transactionP); } case STATE_REG_PENDING: observationP->status = STATE_DEREG_PENDING; break; default: // Should not happen break; } return COAP_NO_ERROR; } bool observe_handleNotify(lwm2m_context_t *contextP, void *fromSessionH, coap_packet_t *message, coap_packet_t *response) { uint8_t *tokenP; int token_len; uint16_t clientID; uint16_t obsID; lwm2m_client_t *clientP; lwm2m_observation_t *observationP; uint32_t count; LOG("Entering"); token_len = coap_get_header_token(message, (const uint8_t **)&tokenP); if (token_len != sizeof(uint32_t)) return false; if (1 != coap_get_header_observe(message, &count)) return false; clientID = (tokenP[0] << 8) | tokenP[1]; obsID = (tokenP[2] << 8) | tokenP[3]; clientP = (lwm2m_client_t *)lwm2m_list_find((lwm2m_list_t *)contextP->clientList, clientID); if (clientP == NULL) return false; observationP = (lwm2m_observation_t *)lwm2m_list_find((lwm2m_list_t *)clientP->observationList, obsID); if (observationP == NULL) { coap_init_message(response, COAP_TYPE_RST, 0, message->mid); message_send(contextP, response, fromSessionH); } else { if (message->type == COAP_TYPE_CON ) { coap_init_message(response, COAP_TYPE_ACK, 0, message->mid); message_send(contextP, response, fromSessionH); } observationP->callback(clientID, &observationP->uri, (int)count, message->content_type, message->payload, message->payload_len, observationP->userData); } return true; } #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/packet.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * domedambrosio - Please refer to git log * Fabien Fleutot - Please refer to git log * Fabien Fleutot - Please refer to git log * Simon Bernard - Please refer to git log * Toby Jaffey - Please refer to git log * Pascal Rieux - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * *******************************************************************************/ /* Copyright (c) 2013, 2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. David Navarro */ /* Contains code snippets which are: * Copyright (c) 2013, Institute for Pervasive Computing, ETH Zurich * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the Institute nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "internals.h" #include #include #include #include "commandline.h" static void handle_reset(lwm2m_context_t *contextP, void *fromSessionH, coap_packet_t *message) { #ifdef LWM2M_CLIENT_MODE LOG("Entering"); observe_cancel(contextP, message->mid, fromSessionH); #endif } static uint8_t handle_request(lwm2m_context_t *contextP, void *fromSessionH, coap_packet_t *message, coap_packet_t *response) { lwm2m_uri_t *uriP; uint8_t result = COAP_IGNORE; LOG("Entering"); #ifdef LWM2M_CLIENT_MODE uriP = uri_decode(contextP->altPath, message->uri_path); #else uriP = uri_decode(NULL, message->uri_path); #endif if (uriP == NULL) return COAP_400_BAD_REQUEST; switch(uriP->flag & LWM2M_URI_MASK_TYPE) { #ifdef LWM2M_CLIENT_MODE case LWM2M_URI_FLAG_DM: { lwm2m_server_t *serverP; serverP = utils_findServer(contextP, fromSessionH); if (serverP != NULL) { result = dm_handleRequest(contextP, uriP, serverP, message, response); } #ifdef LWM2M_BOOTSTRAP else { serverP = utils_findBootstrapServer(contextP, fromSessionH); if (serverP != NULL) { result = bootstrap_handleCommand(contextP, uriP, serverP, message, response); } } #endif } break; #ifdef LWM2M_BOOTSTRAP case LWM2M_URI_FLAG_DELETE_ALL: if (COAP_DELETE != message->code) { result = COAP_400_BAD_REQUEST; } else { result = bootstrap_handleDeleteAll(contextP, fromSessionH); } break; case LWM2M_URI_FLAG_BOOTSTRAP: if (message->code == COAP_POST) { result = bootstrap_handleFinish(contextP, fromSessionH); } break; #endif #endif #ifdef LWM2M_SERVER_MODE case LWM2M_URI_FLAG_REGISTRATION: result = registration_handleRequest(contextP, uriP, fromSessionH, message, response); break; #endif #ifdef LWM2M_BOOTSTRAP_SERVER_MODE case LWM2M_URI_FLAG_BOOTSTRAP: result = bootstrap_handleRequest(contextP, uriP, fromSessionH, message, response); break; #endif default: result = COAP_IGNORE; break; } coap_set_status_code(response, result); if (COAP_IGNORE < result && result < COAP_400_BAD_REQUEST) { result = NO_ERROR; } lwm2m_free(uriP); return result; } /* This function is an adaptation of function coap_receive() from Erbium's er-coap-13-engine.c. * Erbium is Copyright (c) 2013, Institute for Pervasive Computing, ETH Zurich * All rights reserved. */ void lwm2m_handle_packet(lwm2m_context_t *contextP, uint8_t *buffer, int length, void *fromSessionH) { uint8_t coap_error_code = NO_ERROR; static coap_packet_t message[1]; static coap_packet_t response[1]; LOG("Entering"); coap_error_code = coap_parse_message(message, buffer, (uint16_t)length); if (coap_error_code == NO_ERROR) { LOG_ARG("Parsed: ver %u, type %u, tkl %u, code %u.%.2u, mid %u, Content type: %d", message->version, message->type, message->token_len, message->code >> 5, message->code & 0x1F, message->mid, message->content_type); //LOG_ARG("Payload: %.*s", message->payload_len, message->payload); //%s can not used for binary data. if (message->code >= COAP_GET && message->code <= COAP_DELETE) { uint32_t block_num = 0; uint16_t block_size = REST_MAX_CHUNK_SIZE; uint32_t block_offset = 0; int64_t new_offset = 0; /* prepare response */ if (message->type == COAP_TYPE_CON) { /* Reliable CON requests are answered with an ACK. */ coap_init_message(response, COAP_TYPE_ACK, COAP_205_CONTENT, message->mid); } else { /* Unreliable NON requests are answered with a NON as well. */ coap_init_message(response, COAP_TYPE_NON, COAP_205_CONTENT, contextP->nextMID++); } /* mirror token */ if (message->token_len) { coap_set_header_token(response, message->token, message->token_len); } /* get offset for blockwise transfers */ if (coap_get_header_block2(message, &block_num, NULL, &block_size, &block_offset)) { LOG_ARG("Blockwise: block request %u (%u/%u) @ %u bytes", block_num, block_size, REST_MAX_CHUNK_SIZE, block_offset); block_size = MIN(block_size, REST_MAX_CHUNK_SIZE); new_offset = block_offset; } /* handle block1 option */ if (IS_OPTION(message, COAP_OPTION_BLOCK1)) { #ifdef LWM2M_CLIENT_MODE // get server lwm2m_server_t *serverP; serverP = utils_findServer(contextP, fromSessionH); #ifdef LWM2M_BOOTSTRAP if (serverP == NULL) { serverP = utils_findBootstrapServer(contextP, fromSessionH); } #endif if (serverP == NULL) { coap_error_code = COAP_500_INTERNAL_SERVER_ERROR; } else { uint32_t block1_num; uint8_t block1_more; uint16_t block1_size; uint8_t *complete_buffer = NULL; size_t complete_buffer_size; // parse block1 header coap_get_header_block1(message, &block1_num, &block1_more, &block1_size, NULL); LOG_ARG("Blockwise: block1 request NUM %u (SZX %u/ SZX Max%u) MORE %u", block1_num, block1_size, REST_MAX_CHUNK_SIZE, block1_more); // handle block 1 coap_error_code = coap_block1_handler(&serverP->block1Data, message->mid, message->payload, message->payload_len, block1_size, block1_num, block1_more, &complete_buffer, &complete_buffer_size); // if payload is complete, replace it in the coap message. if (coap_error_code == NO_ERROR) { message->payload = complete_buffer; message->payload_len = complete_buffer_size; } else if (coap_error_code == COAP_231_CONTINUE) { block1_size = MIN(block1_size, REST_MAX_CHUNK_SIZE); coap_set_header_block1(response, block1_num, block1_more, block1_size); } } #else coap_error_code = COAP_501_NOT_IMPLEMENTED; #endif } if (coap_error_code == NO_ERROR) { coap_error_code = handle_request(contextP, fromSessionH, message, response); } if (coap_error_code == NO_ERROR) { if ( IS_OPTION(message, COAP_OPTION_BLOCK2) ) { /* unchanged new_offset indicates that resource is unaware of blockwise transfer */ if (new_offset == block_offset) { LOG_ARG("Blockwise: unaware resource with payload length %u/%u", response->payload_len, block_size); if (block_offset >= message->payload_len) { LOG("handle_incoming_data(): block_offset >= response->payload_len"); response->code = COAP_402_BAD_OPTION; coap_set_payload(response, "BlockOutOfScope", 15); /* a const char str[] and sizeof(str) produces larger code size */ } else { coap_set_header_block2(response, block_num, response->payload_len - block_offset > block_size, block_size); coap_set_payload(response, response->payload + block_offset, MIN(response->payload_len - block_offset, block_size)); } /* if (valid offset) */ } else { /* resource provides chunk-wise data */ LOG_ARG("Blockwise: blockwise resource, new offset %d", (int) new_offset); coap_set_header_block2(response, block_num, new_offset != -1 || response->payload_len > block_size, block_size); if (response->payload_len > block_size) coap_set_payload(response, response->payload, block_size); } /* if (resource aware of blockwise) */ } else if (new_offset != 0) { LOG_ARG("Blockwise: no block option for blockwise resource, using block size %u", REST_MAX_CHUNK_SIZE); coap_set_header_block2(response, 0, new_offset != -1, REST_MAX_CHUNK_SIZE); coap_set_payload(response, response->payload, MIN(response->payload_len, REST_MAX_CHUNK_SIZE)); } /* if (blockwise request) */ coap_error_code = message_send(contextP, response, fromSessionH); lwm2m_free(response->payload); response->payload = NULL; response->payload_len = 0; } else if (coap_error_code != COAP_IGNORE) { if (1 == coap_set_status_code(response, coap_error_code)) { coap_error_code = message_send(contextP, response, fromSessionH); } } } else { /* Responses */ switch (message->type) { case COAP_TYPE_NON: case COAP_TYPE_CON: { bool done = transaction_handleResponse(contextP, fromSessionH, message, response); #ifdef LWM2M_SERVER_MODE if (!done && IS_OPTION(message, COAP_OPTION_OBSERVE) && ((message->code == COAP_204_CHANGED) || (message->code == COAP_205_CONTENT))) { done = observe_handleNotify(contextP, fromSessionH, message, response); } #endif if (!done && message->type == COAP_TYPE_CON ) { coap_init_message(response, COAP_TYPE_ACK, 0, message->mid); coap_error_code = message_send(contextP, response, fromSessionH); } } break; case COAP_TYPE_RST: /* Cancel possible subscriptions. */ handle_reset(contextP, fromSessionH, message); transaction_handleResponse(contextP, fromSessionH, message, NULL); break; case COAP_TYPE_ACK: transaction_handleResponse(contextP, fromSessionH, message, NULL); break; default: break; } } /* Request or Response */ coap_free_header(message); } /* if (parsed correctly) */ else { LOG_ARG("Message parsing failed %u.%2u", coap_error_code >> 5, coap_error_code & 0x1F); } if (coap_error_code != NO_ERROR && coap_error_code != COAP_IGNORE) { LOG_ARG("ERROR %u: %s", coap_error_code, coap_error_message); /* Set to sendable error code. */ if (coap_error_code >= 192) { coap_error_code = COAP_500_INTERNAL_SERVER_ERROR; } /* Reuse input buffer for error message. */ coap_init_message(message, COAP_TYPE_ACK, coap_error_code, message->mid); coap_set_payload(message, coap_error_message, strlen(coap_error_message)); message_send(contextP, message, fromSessionH); } } uint8_t message_send(lwm2m_context_t *contextP, coap_packet_t *message, void *sessionH) { uint8_t result = COAP_500_INTERNAL_SERVER_ERROR; uint8_t *pktBuffer; size_t pktBufferLen = 0; size_t allocLen; LOG("Entering"); allocLen = coap_serialize_get_size(message); LOG_ARG("Size to allocate: %d", allocLen); if (allocLen == 0) return COAP_500_INTERNAL_SERVER_ERROR; pktBuffer = (uint8_t *)lwm2m_malloc(allocLen); if (pktBuffer != NULL) { pktBufferLen = coap_serialize_message(message, pktBuffer); LOG_ARG("coap_serialize_message() returned %d", pktBufferLen); if (0 != pktBufferLen) { result = lwm2m_buffer_send(sessionH, pktBuffer, pktBufferLen, contextP->userData); output_buffer(stderr, (uint8_t *)pktBuffer, pktBufferLen, 0); } lwm2m_free(pktBuffer); } return result; } ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/registration.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * domedambrosio - Please refer to git log * Fabien Fleutot - Please refer to git log * Simon Bernard - Please refer to git log * Toby Jaffey - Please refer to git log * Manuel Sangoi - Please refer to git log * Julien Vermillard - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - Please refer to git log * Scott Bertin - Please refer to git log * *******************************************************************************/ /* Copyright (c) 2013, 2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. David Navarro */ #include "internals.h" #include #include #include #define MAX_LOCATION_LENGTH 10 // strlen("/rd/65534") + 1 #ifdef LWM2M_CLIENT_MODE static int prv_getRegistrationQueryLength(lwm2m_context_t *contextP, lwm2m_server_t *server) { int index; int res; char buffer[21]; index = strlen(QUERY_STARTER QUERY_VERSION_FULL QUERY_DELIMITER QUERY_NAME);//?1.0&ep= index += strlen(contextP->endpointName); if (NULL != contextP->msisdn) { index += strlen(QUERY_DELIMITER QUERY_SMS); index += strlen(contextP->msisdn); } switch (server->binding) { case BINDING_U: index += strlen("&b=U"); break; case BINDING_UQ: index += strlen("&b=UQ"); break; case BINDING_S: index += strlen("&b=S"); break; case BINDING_SQ: index += strlen("&b=SQ"); break; case BINDING_US: index += strlen("&b=US"); break; case BINDING_UQS: index += strlen("&b=UQS"); break; default: return 0; } if (0 != server->lifetime) { index += strlen(QUERY_DELIMITER QUERY_LIFETIME);//<= res = utils_intToText(server->lifetime, (uint8_t *)buffer, sizeof(buffer)); if (res == 0) return 0; index += res; } return index + 1; } static int prv_getRegistrationQuery(lwm2m_context_t *contextP, lwm2m_server_t *server, char *buffer, size_t length) { int index; int res; index = utils_stringCopy(buffer, length, QUERY_STARTER QUERY_VERSION_FULL QUERY_DELIMITER QUERY_NAME); if (index < 0) return 0; res = utils_stringCopy(buffer + index, length - index, contextP->endpointName); if (res < 0) return 0; index += res; if (NULL != contextP->msisdn) { res = utils_stringCopy(buffer + index, length - index, QUERY_DELIMITER QUERY_SMS); if (res < 0) return 0; index += res; res = utils_stringCopy(buffer + index, length - index, contextP->msisdn); if (res < 0) return 0; index += res; } switch (server->binding) { case BINDING_U: res = utils_stringCopy(buffer + index, length - index, "&b=U"); break; case BINDING_UQ: res = utils_stringCopy(buffer + index, length - index, "&b=UQ"); break; case BINDING_S: res = utils_stringCopy(buffer + index, length - index, "&b=S"); break; case BINDING_SQ: res = utils_stringCopy(buffer + index, length - index, "&b=SQ"); break; case BINDING_US: res = utils_stringCopy(buffer + index, length - index, "&b=US"); break; case BINDING_UQS: res = utils_stringCopy(buffer + index, length - index, "&b=UQS"); break; default: res = -1; } if (res < 0) return 0; index += res; if (0 != server->lifetime) { res = utils_stringCopy(buffer + index, length - index, QUERY_DELIMITER QUERY_LIFETIME); if (res < 0) return 0; index += res; res = utils_intToText(server->lifetime, (uint8_t *)buffer + index, length - index); if (res == 0) return 0; index += res; } if(index < (int)length) { buffer[index++] = '\0'; } else { return 0; } return index; } static void prv_handleRegistrationReply(lwm2m_transaction_t *transacP, void *message) { coap_packet_t *packet = (coap_packet_t *)message; lwm2m_server_t *targetP = (lwm2m_server_t *)(transacP->userData); LOG("come into prv_handleRegistrationReply!!"); if (targetP->status == STATE_REG_PENDING) { time_t tv_sec = lwm2m_gettime(); if (tv_sec) { targetP->registration = tv_sec; } if (packet != NULL && packet->code == COAP_201_CREATED) { targetP->status = STATE_REGISTERED; if (NULL != targetP->location) { lwm2m_free(targetP->location); } targetP->location = coap_get_multi_option_as_string(packet->location_path); LOG("Registration successful"); } else { targetP->status = STATE_REG_FAILED; LOG("Registration failed"); } } } // send the registration for a single server static uint8_t prv_register(lwm2m_context_t *contextP, lwm2m_server_t *server) { char *query; int query_length; uint8_t *payload; int payload_length; lwm2m_transaction_t *transaction; payload_length = object_getRegisterPayloadBufferLength(contextP); if(payload_length == 0) return COAP_500_INTERNAL_SERVER_ERROR; payload = lwm2m_malloc(payload_length); if(!payload) return COAP_500_INTERNAL_SERVER_ERROR; payload_length = object_getRegisterPayload(contextP, payload, payload_length); if(payload_length == 0) { lwm2m_free(payload); return COAP_500_INTERNAL_SERVER_ERROR; } query_length = prv_getRegistrationQueryLength(contextP, server); if(query_length == 0) { lwm2m_free(payload); return COAP_500_INTERNAL_SERVER_ERROR; } query = lwm2m_malloc(query_length); if(!query) { lwm2m_free(payload); return COAP_500_INTERNAL_SERVER_ERROR; } if(prv_getRegistrationQuery(contextP, server, query, query_length) != query_length) { lwm2m_free(payload); lwm2m_free(query); return COAP_500_INTERNAL_SERVER_ERROR; } if (server->sessionH == NULL) { server->sessionH = lwm2m_connect_server(server->secObjInstID, contextP->userData, false); } if (NULL == server->sessionH) { lwm2m_free(payload); lwm2m_free(query); return COAP_503_SERVICE_UNAVAILABLE; } transaction = transaction_new(server->sessionH, COAP_POST, NULL, NULL, contextP->nextMID++, 4, NULL); if (transaction == NULL) { lwm2m_free(payload); lwm2m_free(query); return COAP_503_SERVICE_UNAVAILABLE; } // coap_pdu_t *pdu = (coap_pdu_t *)(transaction->message); coap_set_header_uri_path(transaction->message, "/"URI_REGISTRATION_SEGMENT); coap_set_header_uri_query(transaction->message, query); coap_set_header_content_type(transaction->message, LWM2M_CONTENT_LINK); coap_set_payload(transaction->message, payload, payload_length); transaction->callback = prv_handleRegistrationReply; transaction->userData = (void *) server; contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transaction); if (transaction_send(contextP, transaction) != 0) { lwm2m_free(payload); lwm2m_free(query); return COAP_503_SERVICE_UNAVAILABLE; } lwm2m_free(payload); lwm2m_free(query); server->status = STATE_REG_PENDING; return COAP_NO_ERROR; } static void prv_handleRegistrationUpdateReply(lwm2m_transaction_t *transacP, void *message) { coap_packet_t *packet = (coap_packet_t *)message; lwm2m_server_t *targetP = (lwm2m_server_t *)(transacP->userData); if (targetP->status == STATE_REG_UPDATE_PENDING) { time_t tv_sec = lwm2m_gettime(); if (tv_sec ) { targetP->registration = tv_sec; } if (packet != NULL && packet->code == COAP_204_CHANGED) { targetP->status = STATE_REGISTERED; LOG("Registration update successful"); } else { targetP->status = STATE_REG_FAILED; LOG("Registration update failed"); } } } static int prv_updateRegistration(lwm2m_context_t *contextP, lwm2m_server_t *server, bool withObjects) { lwm2m_transaction_t *transaction; uint8_t *payload = NULL; int payload_length; transaction = transaction_new(server->sessionH, COAP_POST, NULL, NULL, contextP->nextMID++, 4, NULL); if (transaction == NULL) return COAP_500_INTERNAL_SERVER_ERROR; coap_set_header_uri_path(transaction->message, server->location); if (withObjects == true) { payload_length = object_getRegisterPayloadBufferLength(contextP); if(payload_length == 0) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } payload = lwm2m_malloc(payload_length); if(!payload) { transaction_free(transaction); return COAP_500_INTERNAL_SERVER_ERROR; } payload_length = object_getRegisterPayload(contextP, payload, payload_length); if(payload_length == 0) { transaction_free(transaction); lwm2m_free(payload); return COAP_500_INTERNAL_SERVER_ERROR; } coap_set_payload(transaction->message, payload, payload_length); } transaction->callback = prv_handleRegistrationUpdateReply; transaction->userData = (void *) server; contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transaction); if (transaction_send(contextP, transaction) == 0) { server->status = STATE_REG_UPDATE_PENDING; } if (withObjects == true) { lwm2m_free(payload); } return COAP_NO_ERROR; } // update the registration of a given server int lwm2m_update_registration(lwm2m_context_t *contextP, uint16_t shortServerID, bool withObjects) { lwm2m_server_t *targetP; uint8_t result; LOG_ARG("State: %s, shortServerID: %d", STR_STATE(contextP->state), shortServerID); result = COAP_NO_ERROR; targetP = contextP->serverList; if (targetP == NULL) { if (object_getServers(contextP, false) == -1) { LOG("No server found"); return COAP_404_NOT_FOUND; } } while (targetP != NULL && result == COAP_NO_ERROR) { if (shortServerID != 0) { if (targetP->shortID == shortServerID) { // found the server, trigger the update transaction if (targetP->status == STATE_REGISTERED || targetP->status == STATE_REG_UPDATE_PENDING) { if (withObjects == true) { targetP->status = STATE_REG_FULL_UPDATE_NEEDED; } else { targetP->status = STATE_REG_UPDATE_NEEDED; } return COAP_NO_ERROR; } else if ((targetP->status == STATE_REG_FULL_UPDATE_NEEDED) || (targetP->status == STATE_REG_UPDATE_NEEDED)) { // if REG (FULL) UPDATE is already set, returns COAP_NO_ERROR if (withObjects == true) { targetP->status = STATE_REG_FULL_UPDATE_NEEDED; } return COAP_NO_ERROR; } else { return COAP_400_BAD_REQUEST; } } } else { if (targetP->status == STATE_REGISTERED || targetP->status == STATE_REG_UPDATE_PENDING) { if (withObjects == true) { targetP->status = STATE_REG_FULL_UPDATE_NEEDED; } else { targetP->status = STATE_REG_UPDATE_NEEDED; } } } targetP = targetP->next; } if (shortServerID != 0 && targetP == NULL) { // no server found result = COAP_404_NOT_FOUND; } return result; } //serverlistobjectlistѾֵ uint8_t registration_start(lwm2m_context_t *contextP) { lwm2m_server_t *targetP; uint8_t result; LOG_ARG("State: %s", STR_STATE(contextP->state)); result = COAP_NO_ERROR; targetP = contextP->serverList; while (targetP != NULL && result == COAP_NO_ERROR) { if (targetP->status == STATE_DEREGISTERED || targetP->status == STATE_REG_FAILED) { result = prv_register(contextP, targetP); } targetP = targetP->next; } return result; } /* * Returns STATE_REG_PENDING if at least one registration is still pending * Returns STATE_REGISTERED if no registration is pending and there is at least one server the client is registered to * Returns STATE_REG_FAILED if all registration failed. */ lwm2m_status_t registration_getStatus(lwm2m_context_t *contextP) { lwm2m_server_t *targetP; lwm2m_status_t reg_status; LOG_ARG("State: %s", STR_STATE(contextP->state)); targetP = contextP->serverList; reg_status = STATE_REG_FAILED; while (targetP != NULL) { LOG_ARG("targetP->status: %s", STR_STATUS(targetP->status)); switch (targetP->status) { case STATE_REGISTERED: case STATE_REG_UPDATE_NEEDED: case STATE_REG_FULL_UPDATE_NEEDED: case STATE_REG_UPDATE_PENDING: if (reg_status == STATE_REG_FAILED) { reg_status = STATE_REGISTERED; } break; case STATE_REG_PENDING: reg_status = STATE_REG_PENDING; break; case STATE_REG_FAILED: case STATE_DEREG_PENDING: case STATE_DEREGISTERED: default: break; } LOG_ARG("reg_status: %s", STR_STATUS(reg_status)); targetP = targetP->next; } return reg_status; } static void prv_handleDeregistrationReply(lwm2m_transaction_t *transacP, void *message) { lwm2m_server_t *targetP; targetP = (lwm2m_server_t *)(transacP->userData); if (NULL != targetP) { if (targetP->status == STATE_DEREG_PENDING) { targetP->status = STATE_DEREGISTERED; } } } void registration_deregister(lwm2m_context_t *contextP, lwm2m_server_t *serverP) { lwm2m_transaction_t *transaction; LOG_ARG("State: %s, serverP->status: %s", STR_STATE(contextP->state), STR_STATUS(serverP->status)); if (serverP->status == STATE_DEREGISTERED || serverP->status == STATE_REG_PENDING || serverP->status == STATE_DEREG_PENDING || serverP->status == STATE_REG_FAILED || serverP->location == NULL) { return; } transaction = transaction_new(serverP->sessionH, COAP_DELETE, NULL, NULL, contextP->nextMID++, 4, NULL); if (transaction == NULL) return; coap_set_header_uri_path(transaction->message, serverP->location); transaction->callback = prv_handleDeregistrationReply; transaction->userData = (void *) serverP; contextP->transactionList = (lwm2m_transaction_t *)LWM2M_LIST_ADD(contextP->transactionList, transaction); if (transaction_send(contextP, transaction) == 0) { serverP->status = STATE_DEREG_PENDING; } } void registration_reset(lwm2m_context_t *contextP, lwm2m_server_t *serverP) { //registration_deregister(contextP, serverP); if (serverP->sessionH != NULL) { lwm2m_close_connection(serverP->sessionH, contextP->userData); serverP->sessionH = NULL; } serverP->status = STATE_DEREGISTERED; } lwm2m_server_t *registration_get_registered_server(lwm2m_context_t *contextP) { lwm2m_server_t *targetP; if(NULL == contextP) { LOG("null pointer"); return NULL; } targetP = contextP->serverList; while (targetP != NULL) { if ((STATE_REGISTERED == targetP->status) || (STATE_REG_UPDATE_PENDING == targetP->status) || (STATE_REG_UPDATE_NEEDED == targetP->status) || (STATE_REG_FULL_UPDATE_NEEDED == targetP->status)) { return targetP; } targetP = targetP->next; } return NULL; } #endif #ifdef LWM2M_SERVER_MODE static void prv_freeClientObjectList(lwm2m_client_object_t *objects) { while (objects != NULL) { lwm2m_client_object_t *objP; while (objects->instanceList != NULL) { lwm2m_list_t *target; target = objects->instanceList; objects->instanceList = objects->instanceList->next; lwm2m_free(target); } objP = objects; objects = objects->next; lwm2m_free(objP); } } static int prv_getParameters(multi_option_t *query, char **nameP, uint32_t *lifetimeP, char **msisdnP, lwm2m_binding_t *bindingP, char **versionP) { *nameP = NULL; *lifetimeP = 0; *msisdnP = NULL; *bindingP = BINDING_UNKNOWN; *versionP = NULL; while (query != NULL) { if (lwm2m_strncmp((char *)query->data, QUERY_NAME, QUERY_NAME_LEN) == 0) { if (*nameP != NULL) goto error; if (query->len == QUERY_NAME_LEN) goto error; *nameP = (char *)lwm2m_malloc(query->len - QUERY_NAME_LEN + 1); if (*nameP != NULL) { memcpy(*nameP, query->data + QUERY_NAME_LEN, query->len - QUERY_NAME_LEN); (*nameP)[query->len - QUERY_NAME_LEN] = 0; } } else if (lwm2m_strncmp((char *)query->data, QUERY_SMS, QUERY_SMS_LEN) == 0) { if (*msisdnP != NULL) goto error; if (query->len == QUERY_SMS_LEN) goto error; *msisdnP = (char *)lwm2m_malloc(query->len - QUERY_SMS_LEN + 1); if (*msisdnP != NULL) { memcpy(*msisdnP, query->data + QUERY_SMS_LEN, query->len - QUERY_SMS_LEN); (*msisdnP)[query->len - QUERY_SMS_LEN] = 0; } } else if (lwm2m_strncmp((char *)query->data, QUERY_LIFETIME, QUERY_LIFETIME_LEN) == 0) { int i; if (*lifetimeP != 0) goto error; if (query->len == QUERY_LIFETIME_LEN) goto error; for (i = QUERY_LIFETIME_LEN ; i < query->len ; i++) { if (query->data[i] < '0' || query->data[i] > '9') goto error; *lifetimeP = (*lifetimeP * 10) + (query->data[i] - '0'); } } else if (lwm2m_strncmp((char *)query->data, QUERY_VERSION, QUERY_VERSION_LEN) == 0) { if (*versionP != NULL) goto error; if (query->len == QUERY_VERSION_LEN) goto error; *versionP = (char *)lwm2m_malloc(query->len - QUERY_VERSION_LEN + 1); if (*versionP != NULL) { memcpy(*versionP, query->data + QUERY_VERSION_LEN, query->len - QUERY_VERSION_LEN); (*versionP)[query->len - QUERY_VERSION_LEN] = 0; } } else if (lwm2m_strncmp((char *)query->data, QUERY_BINDING, QUERY_BINDING_LEN) == 0) { if (*bindingP != BINDING_UNKNOWN) goto error; if (query->len == QUERY_BINDING_LEN) goto error; *bindingP = utils_stringToBinding(query->data + QUERY_BINDING_LEN, query->len - QUERY_BINDING_LEN); } query = query->next; } return 0; error: if (*nameP != NULL) lwm2m_free(*nameP); if (*msisdnP != NULL) lwm2m_free(*msisdnP); if (*versionP != NULL) lwm2m_free(*versionP); return -1; } static uint16_t prv_splitLinkAttribute(uint8_t *data, uint16_t length, uint16_t *keyStart, uint16_t *keyLength, uint16_t *valueStart, uint16_t *valueLength) { uint16_t index; uint16_t end; index = 0; while (index < length && data[index] == ' ') index++; if (index == length) return 0; if (data[index] == REG_ATTR_SEPARATOR) { index++; } if (index == length) return 0; *keyStart = index; while (index < length && data[index] != REG_ATTR_EQUALS) index++; if (index == *keyStart || index == length) return 0; *keyLength = index - *keyStart; index++; while (index < length && data[index] == ' ') index++; if (index == length) return 0; *valueStart = index; while (index < length && data[index] != REG_ATTR_SEPARATOR) index++; end = index; index--; while (index > *valueStart && data[index] == ' ') index--; if (index == *valueStart) return 0; *valueLength = index - *valueStart + 1; return end; } static int prv_parseLinkAttributes(uint8_t *data, uint16_t length, bool *supportJSON, char **altPath) { uint16_t index; uint16_t pathStart; uint16_t pathLength; bool isValid; isValid = false; // Expecting application/link-format (RFC6690) // leading space were removed before. Remove trailing spaces. while (length > 0 && data[length - 1] == ' ') length--; // strip open tag if (length >= 2 && data[0] == REG_URI_START) { data += 1; length -= 1; } else { return 0; } pathStart = 0; index = length - 1; while (index > 0 && data[index] != REG_URI_END) index--; // link attributes are required if (index == 0 || index == length - 1) return 0; // If there is a preceding /, remove it if (data[pathStart] == '/') { pathStart += 1; } pathLength = index - pathStart; index++; if (index >= length || data[index] != REG_ATTR_SEPARATOR) return 0; index++; while (index < length) { uint16_t result; uint16_t keyStart; uint16_t keyLength; uint16_t valueStart; uint16_t valueLength; result = prv_splitLinkAttribute(data + index, length - index, &keyStart, &keyLength, &valueStart, &valueLength); if (result == 0) return 0; if (keyLength == REG_ATTR_TYPE_KEY_LEN && 0 == lwm2m_strncmp(REG_ATTR_TYPE_KEY, (char *)data + index + keyStart, keyLength)) { if (isValid == true) return 0; // declared twice if (valueLength != REG_ATTR_TYPE_VALUE_LEN || 0 != lwm2m_strncmp(REG_ATTR_TYPE_VALUE, (char *)data + index + valueStart, valueLength)) { return 0; } isValid = true; } else if (keyLength == REG_ATTR_CONTENT_KEY_LEN && 0 == lwm2m_strncmp(REG_ATTR_CONTENT_KEY, (char *)data + index + keyStart, keyLength)) { if (*supportJSON == true) return 0; // declared twice if (valueLength == REG_ATTR_CONTENT_JSON_LEN && 0 == lwm2m_strncmp(REG_ATTR_CONTENT_JSON, (char *)data + index + valueStart, valueLength)) { *supportJSON = true; } else { return 0; } } // else ignore this one index += result; } if (isValid == false) return 0; if (pathLength != 0) { *altPath = (char *)lwm2m_malloc(pathLength + 1); if (*altPath == NULL) return 0; memcpy(*altPath, data + pathStart, pathLength); (*altPath)[pathLength] = 0; } return 1; } static int prv_getId(uint8_t *data, uint16_t length, uint16_t *objId, uint16_t *instanceId) { int value; uint16_t limit; // Expecting application/link-format (RFC6690) // leading space were removed before. Remove trailing spaces. while (length > 0 && data[length - 1] == ' ') length--; // strip open and close tags if (length >= 1 && data[0] == REG_URI_START && data[length - 1] == REG_URI_END) { data += 1; length -= 2; } else { return 0; } // If there is a preceding /, remove it if (length >= 1 && data[0] == '/') { data += 1; length -= 1; } limit = 0; while (limit < length && data[limit] != '/') limit++; value = uri_getNumber(data, limit); if (value < 0 || value >= LWM2M_MAX_ID) return 0; *objId = value; if (limit < length) { limit += 1; data += limit; length -= limit; if (length > 0) { value = uri_getNumber(data, length); if (value >= 0 && value < LWM2M_MAX_ID) { *instanceId = value; return 2; } else { return 0; } } } return 1; } static lwm2m_client_object_t *prv_decodeRegisterPayload(uint8_t *payload, uint16_t payloadLength, bool *supportJSON, char **altPath) { uint16_t index; lwm2m_client_object_t *objList; bool linkAttrFound; *altPath = NULL; *supportJSON = false; objList = NULL; linkAttrFound = false; index = 0; while (index <= payloadLength) { uint16_t start; uint16_t length; int result; uint16_t id; uint16_t instance; while (index < payloadLength && payload[index] == ' ') index++; if (index == payloadLength) break; start = index; while (index < payloadLength && payload[index] != REG_DELIMITER) index++; length = index - start; result = prv_getId(payload + start, length, &id, &instance); if (result != 0) { lwm2m_client_object_t *objectP; objectP = (lwm2m_client_object_t *)lwm2m_list_find((lwm2m_list_t *)objList, id); if (objectP == NULL) { objectP = (lwm2m_client_object_t *)lwm2m_malloc(sizeof(lwm2m_client_object_t)); if (objectP == NULL) goto error; memset(objectP, 0, sizeof(lwm2m_client_object_t)); objectP->id = id; objList = (lwm2m_client_object_t *)LWM2M_LIST_ADD(objList, objectP); } if (result == 2) { lwm2m_list_t *instanceP; instanceP = lwm2m_list_find(objectP->instanceList, instance); if (instanceP == NULL) { instanceP = (lwm2m_list_t *)lwm2m_malloc(sizeof(lwm2m_list_t)); if(instanceP == NULL) goto error; memset(instanceP, 0, sizeof(lwm2m_list_t)); instanceP->id = instance; objectP->instanceList = LWM2M_LIST_ADD(objectP->instanceList, instanceP); } } } else if (linkAttrFound == false) { result = prv_parseLinkAttributes(payload + start, length, supportJSON, altPath); if (result == 0) goto error; linkAttrFound = true; } else goto error; index++; } return objList; error: if (*altPath != NULL) { lwm2m_free(*altPath); *altPath = NULL; } prv_freeClientObjectList(objList); return NULL; } static lwm2m_client_t *prv_getClientByName(lwm2m_context_t *contextP, char *name) { lwm2m_client_t *targetP; targetP = contextP->clientList; while (targetP != NULL && strcmp(name, targetP->name) != 0) { targetP = targetP->next; } return targetP; } void registration_freeClient(lwm2m_client_t *clientP) { LOG("Entering"); if (clientP->name != NULL) lwm2m_free(clientP->name); if (clientP->msisdn != NULL) lwm2m_free(clientP->msisdn); if (clientP->altPath != NULL) lwm2m_free(clientP->altPath); prv_freeClientObjectList(clientP->objectList); while(clientP->observationList != NULL) { lwm2m_observation_t *targetP; targetP = clientP->observationList; clientP->observationList = clientP->observationList->next; lwm2m_free(targetP); } lwm2m_free(clientP); } static int prv_getLocationString(uint16_t id, char location[MAX_LOCATION_LENGTH]) { int index; int result; memset(location, 0, MAX_LOCATION_LENGTH); result = utils_stringCopy(location, MAX_LOCATION_LENGTH, "/"URI_REGISTRATION_SEGMENT"/"); if (result < 0) return 0; index = result; result = utils_intToText(id, (uint8_t *)location + index, MAX_LOCATION_LENGTH - index); if (result == 0) return 0; return index + result; } uint8_t registration_handleRequest(lwm2m_context_t *contextP, lwm2m_uri_t *uriP, void *fromSessionH, coap_packet_t *message, coap_packet_t *response) { uint8_t result; time_t tv_sec; LOG_URI(uriP); tv_sec = lwm2m_gettime(); if (tv_sec < 0) return COAP_500_INTERNAL_SERVER_ERROR; switch(message->code) { case COAP_POST: { char *name = NULL; uint32_t lifetime; char *msisdn; char *altPath; char *version; lwm2m_binding_t binding; lwm2m_client_object_t *objects; bool supportJSON; lwm2m_client_t *clientP; char location[MAX_LOCATION_LENGTH]; if (0 != prv_getParameters(message->uri_query, &name, &lifetime, &msisdn, &binding, &version)) { return COAP_400_BAD_REQUEST; } if (message->content_type != (coap_content_type_t)LWM2M_CONTENT_LINK && message->content_type != (coap_content_type_t)LWM2M_CONTENT_TEXT) { return COAP_400_BAD_REQUEST; } objects = prv_decodeRegisterPayload(message->payload, message->payload_len, &supportJSON, &altPath); switch (uriP->flag & LWM2M_URI_MASK_ID) { case 0: // Register operation // Version is mandatory if (version == NULL) { if (name != NULL) lwm2m_free(name); if (msisdn != NULL) lwm2m_free(msisdn); return COAP_400_BAD_REQUEST; } // Endpoint client name is mandatory if (name == NULL) { lwm2m_free(version); if (msisdn != NULL) lwm2m_free(msisdn); return COAP_400_BAD_REQUEST; } // Object list is mandatory if (objects == NULL) { lwm2m_free(version); lwm2m_free(name); if (msisdn != NULL) lwm2m_free(msisdn); return COAP_400_BAD_REQUEST; } // version must be 1.0 if (strlen(version) != LWM2M_VERSION_LEN || lwm2m_strncmp(version, LWM2M_VERSION, LWM2M_VERSION_LEN)) { lwm2m_free(version); lwm2m_free(name); if (msisdn != NULL) lwm2m_free(msisdn); return COAP_412_PRECONDITION_FAILED; } if (lifetime == 0) { lifetime = LWM2M_DEFAULT_LIFETIME; } clientP = prv_getClientByName(contextP, name); if (clientP != NULL) { // we reset this registration lwm2m_free(clientP->name); if (clientP->msisdn != NULL) lwm2m_free(clientP->msisdn); if (clientP->altPath != NULL) lwm2m_free(clientP->altPath); prv_freeClientObjectList(clientP->objectList); clientP->objectList = NULL; } else { clientP = (lwm2m_client_t *)lwm2m_malloc(sizeof(lwm2m_client_t)); if (clientP == NULL) { lwm2m_free(name); lwm2m_free(altPath); if (msisdn != NULL) lwm2m_free(msisdn); prv_freeClientObjectList(objects); return COAP_500_INTERNAL_SERVER_ERROR; } memset(clientP, 0, sizeof(lwm2m_client_t)); clientP->internalID = lwm2m_list_newId((lwm2m_list_t *)contextP->clientList); contextP->clientList = (lwm2m_client_t *)LWM2M_LIST_ADD(contextP->clientList, clientP); } clientP->name = name; clientP->binding = binding; clientP->msisdn = msisdn; clientP->altPath = altPath; clientP->supportJSON = supportJSON; clientP->lifetime = lifetime; clientP->endOfLife = tv_sec + lifetime; clientP->objectList = objects; clientP->sessionH = fromSessionH; if (prv_getLocationString(clientP->internalID, location) == 0) { registration_freeClient(clientP); return COAP_500_INTERNAL_SERVER_ERROR; } if (coap_set_header_location_path(response, location) == 0) { registration_freeClient(clientP); return COAP_500_INTERNAL_SERVER_ERROR; } if (contextP->monitorCallback != NULL) { contextP->monitorCallback(clientP->internalID, NULL, COAP_201_CREATED, LWM2M_CONTENT_TEXT, NULL, 0, contextP->monitorUserData); } result = COAP_201_CREATED; break; case LWM2M_URI_FLAG_OBJECT_ID: clientP = (lwm2m_client_t *)lwm2m_list_find((lwm2m_list_t *)contextP->clientList, uriP->objectId); if (clientP == NULL) return COAP_404_NOT_FOUND; // Endpoint client name MUST NOT be present if (name != NULL) { lwm2m_free(name); if (msisdn != NULL) lwm2m_free(msisdn); return COAP_400_BAD_REQUEST; } if (binding != BINDING_UNKNOWN) { clientP->binding = binding; } if (msisdn != NULL) { if (clientP->msisdn != NULL) lwm2m_free(clientP->msisdn); clientP->msisdn = msisdn; } if (lifetime != 0) { clientP->lifetime = lifetime; } // client IP address, port or MSISDN may have changed clientP->sessionH = fromSessionH; if (objects != NULL) { lwm2m_observation_t *observationP; // remove observations on object/instance no longer existing observationP = clientP->observationList; while (observationP != NULL) { lwm2m_client_object_t *objP; lwm2m_observation_t *nextP; nextP = observationP->next; objP = (lwm2m_client_object_t *)lwm2m_list_find((lwm2m_list_t *)objects, observationP->uri.objectId); if (objP == NULL) { observationP->callback(clientP->internalID, &observationP->uri, COAP_202_DELETED, LWM2M_CONTENT_TEXT, NULL, 0, observationP->userData); observe_remove(observationP); } else { if ((observationP->uri.flag & LWM2M_URI_FLAG_INSTANCE_ID) != 0) { if (lwm2m_list_find((lwm2m_list_t *)objP->instanceList, observationP->uri.instanceId) == NULL) { observationP->callback(clientP->internalID, &observationP->uri, COAP_202_DELETED, LWM2M_CONTENT_TEXT, NULL, 0, observationP->userData); observe_remove(observationP); } } } observationP = nextP; } prv_freeClientObjectList(clientP->objectList); clientP->objectList = objects; } clientP->endOfLife = tv_sec + clientP->lifetime; if (contextP->monitorCallback != NULL) { contextP->monitorCallback(clientP->internalID, NULL, COAP_204_CHANGED, LWM2M_CONTENT_TEXT, NULL, 0, contextP->monitorUserData); } result = COAP_204_CHANGED; break; default: return COAP_400_BAD_REQUEST; } } break; case COAP_DELETE: { lwm2m_client_t *clientP; if ((uriP->flag & LWM2M_URI_MASK_ID) != LWM2M_URI_FLAG_OBJECT_ID) return COAP_400_BAD_REQUEST; contextP->clientList = (lwm2m_client_t *)LWM2M_LIST_RM(contextP->clientList, uriP->objectId, &clientP); if (clientP == NULL) return COAP_400_BAD_REQUEST; if (contextP->monitorCallback != NULL) { contextP->monitorCallback(clientP->internalID, NULL, COAP_202_DELETED, LWM2M_CONTENT_TEXT, NULL, 0, contextP->monitorUserData); } registration_freeClient(clientP); result = COAP_202_DELETED; } break; default: return COAP_400_BAD_REQUEST; } return result; } void lwm2m_set_monitoring_callback(lwm2m_context_t *contextP, lwm2m_result_callback_t callback, void *userData) { LOG("Entering"); contextP->monitorCallback = callback; contextP->monitorUserData = userData; } #endif // for each server update the registration if needed // for each client check if the registration expired void registration_step(lwm2m_context_t *contextP, time_t currentTime, time_t *timeoutP) { #ifdef LWM2M_CLIENT_MODE lwm2m_server_t *targetP = contextP->serverList; LOG_ARG("contextP State: %s", STR_STATE(contextP->state)); targetP = contextP->serverList; while (targetP != NULL) { LOG_ARG("targetP Status: %s", STR_STATUS(targetP->status)); switch (targetP->status) { case STATE_REGISTERED: { time_t nextUpdate; int32_t interval; nextUpdate = targetP->lifetime; if (COAP_MAX_TRANSMIT_WAIT < nextUpdate) { nextUpdate -= COAP_MAX_TRANSMIT_WAIT; } else { nextUpdate = nextUpdate >> 1; } interval = (int32_t)(targetP->registration + nextUpdate) - (int32_t)currentTime; if (0 >= interval) { LOG("Updating registration"); prv_updateRegistration(contextP, targetP, false); } else if (interval < *timeoutP) { *timeoutP = interval; } } break; case STATE_REG_UPDATE_NEEDED: prv_updateRegistration(contextP, targetP, false); break; case STATE_REG_FULL_UPDATE_NEEDED: prv_updateRegistration(contextP, targetP, true); break; case STATE_REG_FAILED: if (targetP->sessionH != NULL) { lwm2m_close_connection(targetP->sessionH, contextP->userData); targetP->sessionH = NULL; } break; default: break; } targetP = targetP->next; } #endif #ifdef LWM2M_SERVER_MODE lwm2m_client_t *clientP; LOG("Entering"); // monitor clients lifetime clientP = contextP->clientList; while (clientP != NULL) { lwm2m_client_t *nextP = clientP->next; if (clientP->endOfLife <= currentTime) { contextP->clientList = (lwm2m_client_t *)LWM2M_LIST_RM(contextP->clientList, clientP->internalID, NULL); if (contextP->monitorCallback != NULL) { contextP->monitorCallback(clientP->internalID, NULL, COAP_202_DELETED, LWM2M_CONTENT_TEXT, NULL, 0, contextP->monitorUserData); } registration_freeClient(clientP); } else { time_t interval; interval = clientP->endOfLife - currentTime; if (*timeoutP > interval) { *timeoutP = interval; } } clientP = nextP; } #endif } ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/tlv.c ================================================ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Fabien Fleutot - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * *******************************************************************************/ #include "internals.h" #include #include #include #include #include #ifndef LWM2M_BIG_ENDIAN #ifndef LWM2M_LITTLE_ENDIAN #error Please define LWM2M_BIG_ENDIAN or LWM2M_LITTLE_ENDIAN #endif #endif #define _PRV_TLV_TYPE_MASK 0xC0 #define _PRV_TLV_HEADER_MAX_LENGTH 6 #define _PRV_TLV_TYPE_UNKNOWN (uint8_t)0xFF #define _PRV_TLV_TYPE_OBJECT (uint8_t)0x10 #define _PRV_TLV_TYPE_OBJECT_INSTANCE (uint8_t)0x00 #define _PRV_TLV_TYPE_RESOURCE (uint8_t)0xC0 #define _PRV_TLV_TYPE_MULTIPLE_RESOURCE (uint8_t)0x80 #define _PRV_TLV_TYPE_RESOURCE_INSTANCE (uint8_t)0x40 static size_t prv_encodeFloat(double data, uint8_t *data_buffer) { size_t length = 0; if ((data < 0.0 - (double)FLT_MAX) || (data > (double)FLT_MAX)) { length = 8; utils_copyValue(data_buffer, &data, 8); } else { float value; length = 4; value = (float)data; utils_copyValue(data_buffer, &value, 4); } return length; } static size_t prv_encodeInt(int64_t data, uint8_t *data_buffer) { size_t length = 0; if (data >= INT8_MIN && data <= INT8_MAX) { length = 1; data_buffer[0] = data; } else if (data >= INT16_MIN && data <= INT16_MAX) { int16_t value; value = data; length = 2; data_buffer[0] = (value >> 8) & 0xFF; data_buffer[1] = value & 0xFF; } else if (data >= INT32_MIN && data <= INT32_MAX) { int32_t value; value = data; length = 4; utils_copyValue(data_buffer, &value, length); } else if (data >= INT64_MIN && data <= INT64_MAX) { length = 8; utils_copyValue(data_buffer, &data, length); } return length; } static uint8_t prv_getHeaderType(lwm2m_data_type_t type) { switch (type) { case LWM2M_TYPE_OBJECT: return _PRV_TLV_TYPE_OBJECT; case LWM2M_TYPE_OBJECT_INSTANCE: return _PRV_TLV_TYPE_OBJECT_INSTANCE; case LWM2M_TYPE_MULTIPLE_RESOURCE: return _PRV_TLV_TYPE_MULTIPLE_RESOURCE; case LWM2M_TYPE_STRING: case LWM2M_TYPE_INTEGER: case LWM2M_TYPE_FLOAT: case LWM2M_TYPE_BOOLEAN: case LWM2M_TYPE_OPAQUE: case LWM2M_TYPE_OBJECT_LINK: return _PRV_TLV_TYPE_RESOURCE; case LWM2M_TYPE_UNDEFINED: default: return _PRV_TLV_TYPE_UNKNOWN; } } static lwm2m_data_type_t prv_getDataType(uint8_t type) { switch (type) { case _PRV_TLV_TYPE_OBJECT: return LWM2M_TYPE_OBJECT; case _PRV_TLV_TYPE_OBJECT_INSTANCE: return LWM2M_TYPE_OBJECT_INSTANCE; case _PRV_TLV_TYPE_MULTIPLE_RESOURCE: return LWM2M_TYPE_MULTIPLE_RESOURCE; case _PRV_TLV_TYPE_RESOURCE: case _PRV_TLV_TYPE_RESOURCE_INSTANCE: return LWM2M_TYPE_OPAQUE; default: return LWM2M_TYPE_UNDEFINED; } } static int prv_getHeaderLength(uint16_t id, size_t dataLen) { int length; length = 2; if (id > 0xFF) { length += 1; } if (dataLen > 0xFFFF) { length += 3; } else if (dataLen > 0xFF) { length += 2; } else if (dataLen > 7) { length += 1; } return length; } static int prv_createHeader(uint8_t *header, bool isInstance, lwm2m_data_type_t type, uint16_t id, size_t data_len) { int header_len; int offset; uint8_t hdrType; header_len = prv_getHeaderLength(id, data_len); if (isInstance == true) { hdrType = _PRV_TLV_TYPE_RESOURCE_INSTANCE; } else { hdrType = prv_getHeaderType(type); } header[0] = 0; header[0] |= hdrType & _PRV_TLV_TYPE_MASK; if (id > 0xFF) { header[0] |= 0x20; header[1] = (id >> 8) & 0XFF; header[2] = id & 0XFF; offset = 3; } else { header[1] = id; offset = 2; } if (data_len <= 7) { header[0] += data_len; } else if (data_len <= 0xFF) { header[0] |= 0x08; header[offset] = data_len; } else if (data_len <= 0xFFFF) { header[0] |= 0x10; header[offset] = (data_len >> 8) & 0XFF; header[offset + 1] = data_len & 0XFF; } else if (data_len <= 0xFFFFFF) { header[0] |= 0x18; header[offset] = (data_len >> 16) & 0XFF; header[offset + 1] = (data_len >> 8) & 0XFF; header[offset + 2] = data_len & 0XFF; } return header_len; } int lwm2m_decode_TLV(const uint8_t *buffer, size_t buffer_len, lwm2m_data_type_t *oType, uint16_t *oID, size_t *oDataIndex, size_t *oDataLen) { LOG_ARG("buffer_len: %d", buffer_len); ; if (buffer_len < 2) return 0; *oDataIndex = 2; *oType = prv_getDataType(buffer[0] & _PRV_TLV_TYPE_MASK); if ((buffer[0] & 0x20) == 0x20) { // id is 16 bits long if (buffer_len < 3) return 0; *oDataIndex += 1; *oID = (buffer[1] << 8) + buffer[2]; } else { // id is 8 bits long *oID = buffer[1]; } switch (buffer[0] & 0x18) { case 0x00: // no length field *oDataLen = buffer[0] & 0x07; break; case 0x08: // length field is 8 bits long if (buffer_len < *oDataIndex + 1) return 0; *oDataLen = buffer[*oDataIndex]; *oDataIndex += 1; break; case 0x10: // length field is 16 bits long if (buffer_len < *oDataIndex + 2) return 0; *oDataLen = (buffer[*oDataIndex] << 8) + buffer[*oDataIndex + 1]; *oDataIndex += 2; break; case 0x18: // length field is 24 bits long if (buffer_len < *oDataIndex + 3) return 0; *oDataLen = (buffer[*oDataIndex] << 16) + (buffer[*oDataIndex + 1] << 8) + buffer[*oDataIndex + 2]; *oDataIndex += 3; break; default: // can't happen return 0; } if (*oDataIndex + *oDataLen > buffer_len) return 0; return *oDataIndex + *oDataLen; } int tlv_parse(uint8_t *buffer, size_t bufferLen, lwm2m_data_t **dataP) { lwm2m_data_type_t type; uint16_t id; size_t dataIndex; size_t dataLen; int index = 0; int result; int size = 0; LOG_ARG("bufferLen: %d", bufferLen); *dataP = NULL; while (0 != (result = lwm2m_decode_TLV((uint8_t *)buffer + index, bufferLen - index, &type, &id, &dataIndex, &dataLen))) { lwm2m_data_t *newTlvP; newTlvP = lwm2m_data_new(size + 1); if (size >= 1) { if (newTlvP == NULL) { lwm2m_data_free(size, *dataP); return 0; } else { memcpy(newTlvP, *dataP, size * sizeof(lwm2m_data_t)); lwm2m_free(*dataP); } } *dataP = newTlvP; (*dataP)[size].type = type; (*dataP)[size].id = id; if (type == LWM2M_TYPE_OBJECT_INSTANCE || type == LWM2M_TYPE_MULTIPLE_RESOURCE) { (*dataP)[size].value.asChildren.count = tlv_parse(buffer + index + dataIndex, dataLen, &((*dataP)[size].value.asChildren.array)); if ((*dataP)[size].value.asChildren.count == 0) { lwm2m_data_free(size + 1, *dataP); return 0; } } else { lwm2m_data_encode_opaque(buffer + index + dataIndex, dataLen, (*dataP) + size); } size++; index += result; } return size; } static int prv_getLength(int size, lwm2m_data_t *dataP) { int length; int i; length = 0; for (i = 0 ; i < size && length != -1 ; i++) { switch (dataP[i].type) { case LWM2M_TYPE_OBJECT_INSTANCE: case LWM2M_TYPE_MULTIPLE_RESOURCE: { int subLength; subLength = prv_getLength(dataP[i].value.asChildren.count, dataP[i].value.asChildren.array); if (subLength == -1) { length = -1; } else { length += prv_getHeaderLength(dataP[i].id, subLength) + subLength; } } break; case LWM2M_TYPE_STRING: case LWM2M_TYPE_OPAQUE: length += prv_getHeaderLength(dataP[i].id, dataP[i].value.asBuffer.length) + dataP[i].value.asBuffer.length; break; case LWM2M_TYPE_INTEGER: { size_t data_len; uint8_t unused_buffer[_PRV_64BIT_BUFFER_SIZE]; data_len = prv_encodeInt(dataP[i].value.asInteger, unused_buffer); length += prv_getHeaderLength(dataP[i].id, data_len) + data_len; } break; case LWM2M_TYPE_FLOAT: { size_t data_len; if ((dataP[i].value.asFloat < 0.0 - (double)FLT_MAX) || (dataP[i].value.asFloat > (double)FLT_MAX)) { data_len = 8; } else { data_len = 4; } length += prv_getHeaderLength(dataP[i].id, data_len) + data_len; } break; case LWM2M_TYPE_BOOLEAN: // Booleans are always encoded on one byte length += prv_getHeaderLength(dataP[i].id, 1) + 1; break; case LWM2M_TYPE_OBJECT_LINK: // Object Link are always encoded on four bytes length += prv_getHeaderLength(dataP[i].id, 4) + 4; break; default: length = -1; break; } } return length; } int tlv_serialize(bool isResourceInstance, int size, lwm2m_data_t *dataP, uint8_t **bufferP) { int length; int index; int i; LOG_ARG("isResourceInstance: %s, size: %d", isResourceInstance ? "true" : "false", size); *bufferP = NULL; length = prv_getLength(size, dataP); if (length <= 0) return length; *bufferP = (uint8_t *)lwm2m_malloc(length); if (*bufferP == NULL) return 0; index = 0; for (i = 0 ; i < size && length != 0 ; i++) { int headerLen; bool isInstance; isInstance = isResourceInstance; switch (dataP[i].type) { case LWM2M_TYPE_MULTIPLE_RESOURCE: isInstance = true; // fall through case LWM2M_TYPE_OBJECT_INSTANCE: { uint8_t *tmpBuffer; int res; res = tlv_serialize(isInstance, dataP[i].value.asChildren.count, dataP[i].value.asChildren.array, &tmpBuffer); if (res < 0) { length = -1; } else { size_t tmpLength; tmpLength = (size_t)res; headerLen = prv_createHeader(*bufferP + index, false, dataP[i].type, dataP[i].id, tmpLength); index += headerLen; if (tmpLength > 0) { memcpy(*bufferP + index, tmpBuffer, tmpLength); index += tmpLength; lwm2m_free(tmpBuffer); } } } break; case LWM2M_TYPE_OBJECT_LINK: { int k; uint8_t buf[4]; uint32_t v = dataP[i].value.asObjLink.objectId; v <<= 16; v |= dataP[i].value.asObjLink.objectInstanceId; for (k = 3; k >= 0; --k) { buf[k] = (uint8_t)(v & 0xFF); v >>= 8; } // keep encoding as buffer headerLen = prv_createHeader(*bufferP + index, isInstance, dataP[i].type, dataP[i].id, 4); index += headerLen; memcpy(*bufferP + index, buf, 4); index += 4; } break; case LWM2M_TYPE_STRING: case LWM2M_TYPE_OPAQUE: headerLen = prv_createHeader(*bufferP + index, isInstance, dataP[i].type, dataP[i].id, dataP[i].value.asBuffer.length); index += headerLen; memcpy(*bufferP + index, dataP[i].value.asBuffer.buffer, dataP[i].value.asBuffer.length); index += dataP[i].value.asBuffer.length; break; case LWM2M_TYPE_INTEGER: { size_t data_len; uint8_t data_buffer[_PRV_64BIT_BUFFER_SIZE]; data_len = prv_encodeInt(dataP[i].value.asInteger, data_buffer); headerLen = prv_createHeader(*bufferP + index, isInstance, dataP[i].type, dataP[i].id, data_len); index += headerLen; memcpy(*bufferP + index, data_buffer, data_len); index += data_len; } break; case LWM2M_TYPE_FLOAT: { size_t data_len; uint8_t data_buffer[_PRV_64BIT_BUFFER_SIZE]; data_len = prv_encodeFloat(dataP[i].value.asFloat, data_buffer); headerLen = prv_createHeader(*bufferP + index, isInstance, dataP[i].type, dataP[i].id, data_len); index += headerLen; memcpy(*bufferP + index, data_buffer, data_len); index += data_len; } break; case LWM2M_TYPE_BOOLEAN: headerLen = prv_createHeader(*bufferP + index, isInstance, dataP[i].type, dataP[i].id, 1); index += headerLen; (*bufferP)[index] = dataP[i].value.asBoolean ? 1 : 0; index += 1; break; default: length = -1; break; } } if (length < 0) { lwm2m_free(*bufferP); *bufferP = NULL; } LOG_ARG("returning %u", length); return length; } ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/transaction.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Simon Bernard - Please refer to git log * Toby Jaffey - Please refer to git log * Pascal Rieux - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * *******************************************************************************/ /* Copyright (c) 2013, 2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. David Navarro */ /* Contains code snippets which are: * Copyright (c) 2013, Institute for Pervasive Computing, ETH Zurich * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the Institute nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /************************************************************************ * Function for communications transactions. * * Basic specification: rfc7252 * * Transaction implements processing of piggybacked and separate response communication * dialogs specified in section 2.2 of the above specification. * The caller registers a callback function, which is called, when either the result is * received or a timeout occurs. * * Supported dialogs: * Requests (GET - DELETE): * - CON with mid, without token => regular finished with corresponding ACK.MID * - CON with mid, with token => regular finished with corresponding ACK.MID and response containing * the token. Supports both versions, with piggybacked ACK and separate ACK/response. * Though the ACK.MID may be lost in the separate version, a matching response may * finish the transaction even without the ACK.MID. * - NON without token => no transaction, no result expected! * - NON with token => regular finished with response containing the token. * Responses (COAP_201_CREATED - ?): * - CON with mid => regular finished with corresponding ACK.MID */ #include "internals.h" //#include "pdu.h" #include "commandline.h" /* * Modulo mask (+1 and +0.5 for rounding) for a random number to get the tick number for the random * retransmission time between COAP_RESPONSE_TIMEOUT and COAP_RESPONSE_TIMEOUT*COAP_RESPONSE_RANDOM_FACTOR. */ #define COAP_RESPONSE_TIMEOUT_TICKS (CLOCK_SECOND * COAP_RESPONSE_TIMEOUT) #define COAP_RESPONSE_TIMEOUT_BACKOFF_MASK ((CLOCK_SECOND * COAP_RESPONSE_TIMEOUT * (COAP_RESPONSE_RANDOM_FACTOR - 1)) + 1.5) static int prv_checkFinished(lwm2m_transaction_t *transacP, coap_packet_t *receivedMessage) { int len; const uint8_t *token; coap_packet_t *transactionMessage = transacP->message; if (COAP_DELETE < transactionMessage->code) { // response return transacP->ack_received ? 1 : 0; } if (!IS_OPTION(transactionMessage, COAP_OPTION_TOKEN)) { // request without token return transacP->ack_received ? 1 : 0; } len = coap_get_header_token(receivedMessage, &token); if (transactionMessage->token_len == len) { if (memcmp(transactionMessage->token, token, len) == 0) return 1; } LOG_ARG("transactionMessage->token_len is %d, len is %d\n", transactionMessage->token_len, len); int i = 0; for(i = 0; i < transactionMessage->token_len; i++ ) LOG_ARG("%d\n", transactionMessage->token[i]); LOG("\n\n"); for(i = 0; i < len; i++) LOG_ARG("%d\n", token[i]); LOG("prv_checkFinished not finish!!!\n"); return 0; } //transaction_new(server->sessionH, COAP_POST, NULL, NULL, contextP->nextMID++, 4, NULL) lwm2m_transaction_t *transaction_new(void *sessionH, unsigned char method, char *altPath, lwm2m_uri_t *uriP, uint16_t mID, uint8_t token_len, uint8_t *token) { lwm2m_transaction_t *transacP; int result; if(altPath != NULL){ LOG_ARG("method: %d, altPath: \"%s\", mID: %d, token_len: %d", method, altPath, mID, token_len); } else { LOG_ARG("method: %d, altPath: NULL, mID: %d, token_len: %d", method, mID, token_len); } LOG_URI(uriP); // no transactions without peer if (NULL == sessionH) return NULL; transacP = (lwm2m_transaction_t *)lwm2m_malloc(sizeof(lwm2m_transaction_t)); if (NULL == transacP) return NULL; memset(transacP, 0, sizeof(lwm2m_transaction_t)); transacP->message = lwm2m_malloc(sizeof(coap_packet_t)); if (NULL == transacP->message) goto error; coap_init_message(transacP->message, COAP_TYPE_CON, method, mID); transacP->peerH = sessionH; transacP->mID = mID; if (altPath != NULL) { // TODO: Support multi-segment alternative path coap_set_header_uri_path_segment(transacP->message, altPath + 1); } if (NULL != uriP) { char stringID[LWM2M_STRING_ID_MAX_LEN]; result = utils_intToText(uriP->objectId, (uint8_t *)stringID, LWM2M_STRING_ID_MAX_LEN); if (result == 0) goto error; stringID[result] = 0; coap_set_header_uri_path_segment(transacP->message, stringID); if (LWM2M_URI_IS_SET_INSTANCE(uriP)) { result = utils_intToText(uriP->instanceId, (uint8_t *)stringID, LWM2M_STRING_ID_MAX_LEN); if (result == 0) goto error; stringID[result] = 0; coap_set_header_uri_path_segment(transacP->message, stringID); } else { if (LWM2M_URI_IS_SET_RESOURCE(uriP)) { coap_set_header_uri_path_segment(transacP->message, NULL); } } if (LWM2M_URI_IS_SET_RESOURCE(uriP)) { result = utils_intToText(uriP->resourceId, (uint8_t *)stringID, LWM2M_STRING_ID_MAX_LEN); if (result == 0) goto error; stringID[result] = 0; coap_set_header_uri_path_segment(transacP->message, stringID); } } if (0 < token_len) { if (NULL != token) { coap_set_header_token(transacP->message, token, token_len); } else { // generate a token uint8_t temp_token[COAP_TOKEN_LEN]; time_t tv_sec = lwm2m_gettime(); // initialize first 6 bytes, leave the last 2 random temp_token[0] = mID; temp_token[1] = mID >> 8; temp_token[2] = tv_sec; temp_token[3] = tv_sec >> 8; temp_token[4] = tv_sec >> 16; temp_token[5] = tv_sec >> 24; // use just the provided amount of bytes coap_set_header_token(transacP->message, temp_token, token_len); int i; for(i = 0; i < token_len; i++) LOG_ARG("send token is %d\n", temp_token[i]); } } LOG("Exiting on success"); return transacP; error: LOG("Exiting on failure"); lwm2m_free(transacP); return NULL; } void transaction_free(lwm2m_transaction_t *transacP) { LOG("Entering"); if (transacP->message) { coap_free_header(transacP->message); lwm2m_free(transacP->message); } if (transacP->buffer) lwm2m_free(transacP->buffer); lwm2m_free(transacP); } void transaction_remove(lwm2m_context_t *contextP, lwm2m_transaction_t *transacP) { LOG("Entering"); contextP->transactionList = (lwm2m_transaction_t *) LWM2M_LIST_RM(contextP->transactionList, transacP->mID, NULL); transaction_free(transacP); } bool transaction_handleResponse(lwm2m_context_t *contextP, void *fromSessionH, coap_packet_t *message, coap_packet_t *response) { bool found = false; bool reset = false; lwm2m_transaction_t *transacP; LOG_ARG("Entering,message->code: %d", message->code); transacP = contextP->transactionList; while (NULL != transacP) { if (lwm2m_session_is_equal(fromSessionH, transacP->peerH, contextP->userData) == true) { if (!transacP->ack_received) { if ((COAP_TYPE_ACK == message->type) || (COAP_TYPE_RST == message->type)) { if (transacP->mID == message->mid) { found = true; transacP->ack_received = true; reset = COAP_TYPE_RST == message->type; } } } if (reset || prv_checkFinished(transacP, message)) { // HACK: If a message is sent from the monitor callback, // it will arrive before the registration ACK. // So we resend transaction that were denied for authentication reason. if (!reset) { if (COAP_TYPE_CON == message->type && NULL != response) { coap_init_message(response, COAP_TYPE_ACK, 0, message->mid); message_send(contextP, response, fromSessionH); } if ((COAP_401_UNAUTHORIZED == message->code) && (COAP_MAX_RETRANSMIT > transacP->retrans_counter)) { transacP->ack_received = false; transacP->retrans_time += COAP_RESPONSE_TIMEOUT; LOG("timeout in transaction_handleResponse\n"); return true; } } if (transacP->callback != NULL) { transacP->callback(transacP, message); } transaction_remove(contextP, transacP); return true; } // if we found our guy, exit if (found) { time_t tv_sec = lwm2m_gettime(); if (tv_sec) { transacP->retrans_time = tv_sec; } if (transacP->response_timeout) { transacP->retrans_time += transacP->response_timeout; } else { transacP->retrans_time += COAP_RESPONSE_TIMEOUT * transacP->retrans_counter; } LOG_ARG("only true25,fromSessionH is %p, transacP->peerH is %p\n", fromSessionH, transacP->peerH); return true; } } else { LOG_ARG("error25,fromSessionH is %p, transacP->peerH is %p\n", fromSessionH, transacP->peerH); } transacP = transacP->next; } LOG("error25,return false in transaction_handleResponse\n"); return false; } //transacPж󣬳bufferѾֵ int transaction_send(lwm2m_context_t *contextP, lwm2m_transaction_t *transacP) { bool maxRetriesReached = false; coap_packet_t *message = transacP->message; int ret; LOG("Entering"); LOG_ARG("transaction_send: ver %u, type %u, tkl %u, code %u.%.2u, mid %u, Content type: %d", message->version, message->type, message->token_len, message->code >> 5, message->code & 0x1F, message->mid, message->content_type); LOG_ARG("time:%llu", atiny_gettime_ms()); if (transacP->buffer == NULL) { transacP->buffer_len = coap_serialize_get_size(message); if (transacP->buffer_len == 0) { transaction_remove(contextP, transacP); LOG("remove"); return COAP_500_INTERNAL_SERVER_ERROR; } transacP->buffer = (uint8_t *)lwm2m_malloc(transacP->buffer_len); if (transacP->buffer == NULL) { transaction_remove(contextP, transacP); LOG("remove"); return COAP_500_INTERNAL_SERVER_ERROR; } transacP->buffer_len = coap_serialize_message(message, transacP->buffer); if (transacP->buffer_len == 0) { lwm2m_free(transacP->buffer); transacP->buffer = NULL; transaction_remove(contextP, transacP); LOG("remove"); return COAP_500_INTERNAL_SERVER_ERROR; } } if (!transacP->ack_received) { long unsigned timeout = 0; if (0 == transacP->retrans_counter) { time_t tv_sec = lwm2m_gettime(); if (tv_sec) { transacP->retrans_time = tv_sec + COAP_RESPONSE_TIMEOUT; transacP->retrans_counter = 1; timeout = 0; } else { maxRetriesReached = true; } } else { if(transacP->retrans_counter <= 4 ) timeout = COAP_RESPONSE_TIMEOUT << (transacP->retrans_counter - 1); else timeout = COAP_RESPONSE_TIMEOUT << (4 - 1); } if (COAP_MAX_RETRANSMIT + 1 >= transacP->retrans_counter) { ret = lwm2m_buffer_send(transacP->peerH, transacP->buffer, transacP->buffer_len, contextP->userData); output_buffer(stderr, (uint8_t *)(transacP->buffer), transacP->buffer_len, 0); transacP->retrans_time += timeout; LOG_ARG("send result is %d, retrans_counter:%d", ret, transacP->retrans_counter); transacP->retrans_counter += 1; UNUSEX(ret); } else { maxRetriesReached = true; } } if (transacP->ack_received || maxRetriesReached) { if (transacP->callback) { transacP->callback(transacP, NULL); } transaction_remove(contextP, transacP); LOG_ARG("remove, ACK:%d, timeout: %d", transacP->ack_received, maxRetriesReached); return -1; } return 0; } void transaction_step(lwm2m_context_t *contextP, time_t currentTime, time_t *timeoutP) { lwm2m_transaction_t *transacP; LOG("Entering"); transacP = contextP->transactionList; while (transacP != NULL) { // transaction_send() may remove transaction from the linked list lwm2m_transaction_t *nextP = transacP->next; int removed = 0; if (transacP->retrans_time <= currentTime) { removed = transaction_send(contextP, transacP); } if (0 == removed) { time_t interval; if (transacP->retrans_time > currentTime) { interval = transacP->retrans_time - currentTime; } else { interval = 1; } if (*timeoutP > interval) { *timeoutP = interval; } } else { *timeoutP = 1; } transacP = nextP; } } ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/uri.c ================================================ /******************************************************************************* * * Copyright (c) 2013, 2014 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Fabien Fleutot - Please refer to git log * Toby Jaffey - Please refer to git log * Bosch Software Innovations GmbH - Please refer to git log * Pascal Rieux - Please refer to git log * *******************************************************************************/ /* Copyright (c) 2013, 2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. David Navarro */ #include "internals.h" #include #include #include static int prv_parseNumber(uint8_t *uriString, size_t uriLength, size_t *headP) { int result = 0; if (uriString[*headP] == '/') { // empty Object Instance ID with resource ID is not allowed return -1; } while (*headP < uriLength && uriString[*headP] != '/') { if ('0' <= uriString[*headP] && uriString[*headP] <= '9') { result += uriString[*headP] - '0'; result *= 10; } else { return -1; } *headP += 1; } result /= 10; return result; } int uri_getNumber(uint8_t *uriString, size_t uriLength) { size_t index = 0; return prv_parseNumber(uriString, uriLength, &index); } lwm2m_uri_t *uri_decode(char *altPath, multi_option_t *uriPath) { lwm2m_uri_t *uriP; int readNum; if(altPath != NULL) { LOG_ARG("altPath: \"%s\"", altPath); } else { LOG("altPath: NULL"); } uriP = (lwm2m_uri_t *)lwm2m_malloc(sizeof(lwm2m_uri_t)); if (NULL == uriP) return NULL; memset(uriP, 0, sizeof(lwm2m_uri_t)); // Read object ID if (NULL != uriPath && URI_REGISTRATION_SEGMENT_LEN == uriPath->len && 0 == strncmp(URI_REGISTRATION_SEGMENT, (char *)uriPath->data, uriPath->len)) { uriP->flag |= LWM2M_URI_FLAG_REGISTRATION; uriPath = uriPath->next; if (uriPath == NULL) return uriP; } else if (NULL != uriPath && URI_BOOTSTRAP_SEGMENT_LEN == uriPath->len && 0 == strncmp(URI_BOOTSTRAP_SEGMENT, (char *)uriPath->data, uriPath->len)) { uriP->flag |= LWM2M_URI_FLAG_BOOTSTRAP; uriPath = uriPath->next; if (uriPath != NULL) goto error; return uriP; } if ((uriP->flag & LWM2M_URI_MASK_TYPE) != LWM2M_URI_FLAG_REGISTRATION) { // Read altPath if any if (altPath != NULL) { int i; if (NULL == uriPath) { lwm2m_free(uriP); return NULL; } for (i = 0 ; i < uriPath->len ; i++) { if (uriPath->data[i] != altPath[i + 1]) { lwm2m_free(uriP); return NULL; } } uriPath = uriPath->next; } if (NULL == uriPath || uriPath->len == 0) { uriP->flag |= LWM2M_URI_FLAG_DELETE_ALL; return uriP; } } readNum = uri_getNumber(uriPath->data, uriPath->len); if (readNum < 0 || readNum > LWM2M_MAX_ID) goto error; uriP->objectId = (uint16_t)readNum; uriP->flag |= LWM2M_URI_FLAG_OBJECT_ID; uriPath = uriPath->next; if ((uriP->flag & LWM2M_URI_MASK_TYPE) == LWM2M_URI_FLAG_REGISTRATION) { if (uriPath != NULL) goto error; return uriP; } uriP->flag |= LWM2M_URI_FLAG_DM; if (uriPath == NULL) return uriP; // Read object instance if (uriPath->len != 0) { readNum = uri_getNumber(uriPath->data, uriPath->len); if (readNum < 0 || readNum >= LWM2M_MAX_ID) goto error; uriP->instanceId = (uint16_t)readNum; uriP->flag |= LWM2M_URI_FLAG_INSTANCE_ID; } uriPath = uriPath->next; if (uriPath == NULL) return uriP; // Read resource ID if (uriPath->len != 0) { // resource ID without an instance ID is not allowed if ((uriP->flag & LWM2M_URI_FLAG_INSTANCE_ID) == 0) goto error; readNum = uri_getNumber(uriPath->data, uriPath->len); if (readNum < 0 || readNum > LWM2M_MAX_ID) goto error; uriP->resourceId = (uint16_t)readNum; uriP->flag |= LWM2M_URI_FLAG_RESOURCE_ID; } // must be the last segment if (NULL == uriPath->next) { LOG_URI(uriP); return uriP; } error: LOG("Exiting on error"); lwm2m_free(uriP); return NULL; } int lwm2m_stringToUri(const char *buffer, size_t buffer_len, lwm2m_uri_t *uriP) { size_t head; int readNum; LOG_ARG("buffer_len: %u, buffer: \"%.*s\"", buffer_len, buffer_len, buffer); if (buffer == NULL || buffer_len == 0 || uriP == NULL) return 0; memset(uriP, 0, sizeof(lwm2m_uri_t)); // Skip any white space head = 0; while (head < buffer_len && isspace(buffer[head] & 0xFF)) { head++; } if (head == buffer_len) return 0; // Check the URI start with a '/' if (buffer[head] != '/') return 0; head++; if (head == buffer_len) return 0; // Read object ID readNum = prv_parseNumber((uint8_t *)buffer, buffer_len, &head); if (readNum < 0 || readNum > LWM2M_MAX_ID) return 0; uriP->objectId = (uint16_t)readNum; uriP->flag |= LWM2M_URI_FLAG_OBJECT_ID; if (buffer[head] == '/') head += 1; if (head >= buffer_len) { LOG_ARG("Parsed characters: %u", head); LOG_URI(uriP); return head; } readNum = prv_parseNumber((uint8_t *)buffer, buffer_len, &head); if (readNum < 0 || readNum >= LWM2M_MAX_ID) return 0; uriP->instanceId = (uint16_t)readNum; uriP->flag |= LWM2M_URI_FLAG_INSTANCE_ID; if (buffer[head] == '/') head += 1; if (head >= buffer_len) { LOG_ARG("Parsed characters: %u", head); LOG_URI(uriP); return head; } readNum = prv_parseNumber((uint8_t *)buffer, buffer_len, &head); if (readNum < 0 || readNum >= LWM2M_MAX_ID) return 0; uriP->resourceId = (uint16_t)readNum; uriP->flag |= LWM2M_URI_FLAG_RESOURCE_ID; if (head != buffer_len) return 0; LOG_ARG("Parsed characters: %u", head); LOG_URI(uriP); return head; } int uri_toString(lwm2m_uri_t *uriP, uint8_t *buffer, size_t bufferLen, uri_depth_t *depthP) { size_t head; int res; LOG_ARG("bufferLen: %u", bufferLen); LOG_URI(uriP); buffer[0] = '/'; if (uriP == NULL) { if (depthP) *depthP = URI_DEPTH_OBJECT; return 1; } head = 1; res = utils_intToText(uriP->objectId, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; if (head >= bufferLen - 1) return -1; if (depthP) *depthP = URI_DEPTH_OBJECT_INSTANCE; if (LWM2M_URI_IS_SET_INSTANCE(uriP)) { buffer[head] = '/'; head++; res = utils_intToText(uriP->instanceId, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; if (head >= bufferLen - 1) return -1; if (depthP) *depthP = URI_DEPTH_RESOURCE; if (LWM2M_URI_IS_SET_RESOURCE(uriP)) { buffer[head] = '/'; head++; res = utils_intToText(uriP->resourceId, buffer + head, bufferLen - head); if (res <= 0) return -1; head += res; if (head >= bufferLen - 1) return -1; if (depthP) *depthP = URI_DEPTH_RESOURCE_INSTANCE; } } buffer[head] = '/'; head++; LOG_ARG("length: %u, buffer: \"%.*s\"", head, head, buffer); return head; } ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/core/wakaama.cmake ================================================ # Provides WAKAAMA_SOURCES_DIR and WAKAAMA_SOURCES and WAKAAMA_DEFINITIONS variables. # Add LWM2M_WITH_LOGS to compile definitions to enable logging. # Set LWM2M_LITTLE_ENDIAN to FALSE or TRUE according to your destination platform or leave # it unset to determine endianess automatically. set(WAKAAMA_SOURCES_DIR ${CMAKE_CURRENT_LIST_DIR}) set(EXT_SOURCES ${WAKAAMA_SOURCES_DIR}/er-coap-13/er-coap-13.c ${WAKAAMA_SOURCES_DIR}/er-coap-13/er-coap-13.h) set(CORE_HEADERS ${WAKAAMA_SOURCES_DIR}/liblwm2m.h) set(WAKAAMA_SOURCES ${WAKAAMA_SOURCES_DIR}/liblwm2m.c ${WAKAAMA_SOURCES_DIR}/uri.c ${WAKAAMA_SOURCES_DIR}/utils.c ${WAKAAMA_SOURCES_DIR}/objects.c ${WAKAAMA_SOURCES_DIR}/tlv.c ${WAKAAMA_SOURCES_DIR}/data.c ${WAKAAMA_SOURCES_DIR}/list.c ${WAKAAMA_SOURCES_DIR}/packet.c ${WAKAAMA_SOURCES_DIR}/transaction.c ${WAKAAMA_SOURCES_DIR}/registration.c ${WAKAAMA_SOURCES_DIR}/bootstrap.c ${WAKAAMA_SOURCES_DIR}/management.c ${WAKAAMA_SOURCES_DIR}/observe.c ${WAKAAMA_SOURCES_DIR}/json.c ${WAKAAMA_SOURCES_DIR}/discover.c ${WAKAAMA_SOURCES_DIR}/block1.c ${WAKAAMA_SOURCES_DIR}/internals.h ${CORE_HEADERS} ${EXT_SOURCES}) # This will not work for multi project cmake generators like the Visual Studio Generator if(CMAKE_BUILD_TYPE MATCHES Debug) set(WAKAAMA_DEFINITIONS ${WAKAAMA_DEFINITIONS} -DLWM2M_WITH_LOGS) endif() # Automatically determine endianess. This can be overwritten by setting LWM2M_LITTLE_ENDIAN # accordingly in a cross compile toolchain file. if(NOT DEFINED LWM2M_LITTLE_ENDIAN) include(TestBigEndian) TEST_BIG_ENDIAN(LWM2M_BIG_ENDIAN) if (LWM2M_BIG_ENDIAN) set(LWM2M_LITTLE_ENDIAN FALSE) else() set(LWM2M_LITTLE_ENDIAN TRUE) endif() endif() if (LWM2M_LITTLE_ENDIAN) set(WAKAAMA_DEFINITIONS ${WAKAAMA_DEFINITIONS} -DLWM2M_LITTLE_ENDIAN) endif() ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/examples/shared/commandline.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013, 2014, 2015 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * Fabien Fleutot - Please refer to git log * *******************************************************************************/ #include #include #include #include #include #include "liblwm2m.h" #include "internals.h" #include "commandline.h" #define HELP_COMMAND "help" #define HELP_DESC "Type '"HELP_COMMAND" [COMMAND]' for more details on a command." #define UNKNOWN_CMD_MSG "Unknown command. Type '"HELP_COMMAND"' for help." static command_desc_t *prv_find_command(command_desc_t *commandArray, char *buffer, size_t length) { int i; if (length == 0) return NULL; i = 0; while (commandArray[i].name != NULL && (strlen(commandArray[i].name) != length || strncmp(buffer, commandArray[i].name, length))) { i++; } if (commandArray[i].name == NULL) { return NULL; } else { return &commandArray[i]; } } static void prv_displayHelp(command_desc_t *commandArray, char *buffer) { command_desc_t *cmdP; int length; // find end of first argument length = 0; while (buffer[length] != 0 && !isspace(buffer[length] & 0xff)) length++; cmdP = prv_find_command(commandArray, buffer, length); if (cmdP == NULL) { int i; fprintf(stdout, HELP_COMMAND"\t"HELP_DESC"\r\n"); for (i = 0 ; commandArray[i].name != NULL ; i++) { fprintf(stdout, "%s\t%s\r\n", commandArray[i].name, commandArray[i].shortDesc); } } else { fprintf(stdout, "%s\r\n", cmdP->longDesc ? cmdP->longDesc : cmdP->shortDesc); } } void handle_command(command_desc_t *commandArray, char *buffer) { command_desc_t *cmdP; int length; // find end of command name length = 0; while (buffer[length] != 0 && !isspace(buffer[length] & 0xFF)) length++; cmdP = prv_find_command(commandArray, buffer, length); if (cmdP != NULL) { while (buffer[length] != 0 && isspace(buffer[length] & 0xFF)) length++; cmdP->callback(buffer + length, cmdP->userData); } else { if (!strncmp(buffer, HELP_COMMAND, length)) { while (buffer[length] != 0 && isspace(buffer[length] & 0xFF)) length++; prv_displayHelp(commandArray, buffer + length); } else { fprintf(stdout, UNKNOWN_CMD_MSG"\r\n"); } } } static char *prv_end_of_space(char *buffer) { while (isspace(buffer[0] & 0xff)) { buffer++; } return buffer; } char *get_end_of_arg(char *buffer) { while (buffer[0] != 0 && !isspace(buffer[0] & 0xFF)) { buffer++; } return buffer; } char *get_next_arg(char *buffer, char **end) { // skip arg buffer = get_end_of_arg(buffer); // skip space buffer = prv_end_of_space(buffer); if (NULL != end) { *end = get_end_of_arg(buffer); } return buffer; } int check_end_of_args(char *buffer) { buffer = prv_end_of_space(buffer); return (0 == buffer[0]); } /********************************************************** * Display Functions */ static void print_indent(FILE *stream, int num) { int i; for ( i = 0 ; i < num ; i++) fprintf(stream, " "); } #ifdef ATING_DEBUG void output_buffer(FILE *stream, uint8_t *buffer, int length, int indent) { int i; if (length == 0) fprintf(stream, "\n"); if (buffer == NULL) return; i = 0; while (i < length) { uint8_t array[16]; int j; print_indent(stream, indent); memcpy(array, buffer + i, 16); for (j = 0 ; j < 16 && i + j < length; j++) { fprintf(stream, "%02X ", array[j]); if (j % 4 == 3) fprintf(stream, " "); } if (length > 16) { while (j < 16) { fprintf(stream, " "); if (j % 4 == 3) fprintf(stream, " "); j++; } } fprintf(stream, " "); for (j = 0 ; j < 16 && i + j < length; j++) { if (isprint(array[j])) fprintf(stream, "%c", array[j]); else fprintf(stream, "."); } fprintf(stream, "\n"); i += 16; } } #else void output_buffer(FILE *stream, uint8_t *buffer, int length, int indent) { } #endif void output_tlv(FILE *stream, uint8_t *buffer, size_t buffer_len, int indent) { lwm2m_data_type_t type; uint16_t id; size_t dataIndex; size_t dataLen; int length = 0; int result; while (0 != (result = lwm2m_decode_TLV((uint8_t *)buffer + length, buffer_len - length, &type, &id, &dataIndex, &dataLen))) { print_indent(stream, indent); fprintf(stream, "{\r\n"); print_indent(stream, indent + 1); fprintf(stream, "ID: %d", id); fprintf(stream, " type: "); switch (type) { case LWM2M_TYPE_OBJECT_INSTANCE: fprintf(stream, "Object Instance"); break; case LWM2M_TYPE_MULTIPLE_RESOURCE: fprintf(stream, "Multiple Instances"); break; case LWM2M_TYPE_OPAQUE: fprintf(stream, "Resource Value"); break; default: printf("unknown (%d)", (int)type); break; } fprintf(stream, "\n"); print_indent(stream, indent + 1); fprintf(stream, "{\n"); if (type == LWM2M_TYPE_OBJECT_INSTANCE || type == LWM2M_TYPE_MULTIPLE_RESOURCE) { output_tlv(stream, buffer + length + dataIndex, dataLen, indent + 1); } else { int64_t intValue; double floatValue; uint8_t tmp; print_indent(stream, indent + 2); fprintf(stream, "data (%d bytes):\r\n", dataLen); output_buffer(stream, (uint8_t *)buffer + length + dataIndex, dataLen, indent + 2); tmp = buffer[length + dataIndex + dataLen]; buffer[length + dataIndex + dataLen] = 0; if (0 < sscanf((const char *)buffer + length + dataIndex, "%"PRId64, &intValue)) { print_indent(stream, indent + 2); fprintf(stream, "data as Integer: %" PRId64 "\r\n", intValue); } if (0 < sscanf((const char *)buffer + length + dataIndex, "%lg", &floatValue)) { print_indent(stream, indent + 2); fprintf(stream, "data as Float: %.16g\r\n", floatValue); } buffer[length + dataIndex + dataLen] = tmp; } print_indent(stream, indent + 1); fprintf(stream, "}\r\n"); length += result; print_indent(stream, indent); fprintf(stream, "}\r\n"); } } void output_data(FILE *stream, lwm2m_media_type_t format, uint8_t *data, int dataLength, int indent) { int i; print_indent(stream, indent); fprintf(stream, "%d bytes received of type ", dataLength); switch (format) { case LWM2M_CONTENT_TEXT: fprintf(stream, "text/plain:\r\n"); output_buffer(stream, data, dataLength, indent); break; case LWM2M_CONTENT_OPAQUE: fprintf(stream, "application/octet-stream:\r\n"); output_buffer(stream, data, dataLength, indent); break; case LWM2M_CONTENT_TLV: fprintf(stream, "application/vnd.oma.lwm2m+tlv:\r\n"); output_tlv(stream, data, dataLength, indent); break; case LWM2M_CONTENT_JSON: fprintf(stream, "application/vnd.oma.lwm2m+json:\r\n"); print_indent(stream, indent); for (i = 0 ; i < dataLength ; i++) { fprintf(stream, "%c", data[i]); } fprintf(stream, "\n"); break; case LWM2M_CONTENT_LINK: fprintf(stream, "application/link-format:\r\n"); print_indent(stream, indent); for (i = 0 ; i < dataLength ; i++) { fprintf(stream, "%c", data[i]); } fprintf(stream, "\n"); break; default: fprintf(stream, "Unknown (%d):\r\n", format); output_buffer(stream, data, dataLength, indent); break; } } void dump_tlv(FILE *stream, int size, lwm2m_data_t *dataP, int indent) { int i; for(i = 0 ; i < size ; i++) { print_indent(stream, indent); fprintf(stream, "{\r\n"); print_indent(stream, indent + 1); fprintf(stream, "id: %d\r\n", dataP[i].id); print_indent(stream, indent + 1); fprintf(stream, "type: "); switch (dataP[i].type) { case LWM2M_TYPE_OBJECT: fprintf(stream, "LWM2M_TYPE_OBJECT\r\n"); dump_tlv(stream, dataP[i].value.asChildren.count, dataP[i].value.asChildren.array, indent + 1); break; case LWM2M_TYPE_OBJECT_INSTANCE: fprintf(stream, "LWM2M_TYPE_OBJECT_INSTANCE\r\n"); dump_tlv(stream, dataP[i].value.asChildren.count, dataP[i].value.asChildren.array, indent + 1); break; case LWM2M_TYPE_MULTIPLE_RESOURCE: fprintf(stream, "LWM2M_TYPE_MULTIPLE_RESOURCE\r\n"); dump_tlv(stream, dataP[i].value.asChildren.count, dataP[i].value.asChildren.array, indent + 1); break; case LWM2M_TYPE_UNDEFINED: fprintf(stream, "LWM2M_TYPE_UNDEFINED\r\n"); break; case LWM2M_TYPE_STRING: fprintf(stream, "LWM2M_TYPE_STRING\r\n"); print_indent(stream, indent + 1); fprintf(stream, "\"%.*s\"\r\n", (int)dataP[i].value.asBuffer.length, dataP[i].value.asBuffer.buffer); break; case LWM2M_TYPE_OPAQUE: fprintf(stream, "LWM2M_TYPE_OPAQUE\r\n"); output_buffer(stream, dataP[i].value.asBuffer.buffer, dataP[i].value.asBuffer.length, indent + 1); break; case LWM2M_TYPE_INTEGER: fprintf(stream, "LWM2M_TYPE_INTEGER: "); print_indent(stream, indent + 1); fprintf(stream, "%" PRId64, dataP[i].value.asInteger); fprintf(stream, "\r\n"); break; case LWM2M_TYPE_FLOAT: fprintf(stream, "LWM2M_TYPE_FLOAT: "); print_indent(stream, indent + 1); fprintf(stream, "%" PRId64, dataP[i].value.asInteger); fprintf(stream, "\r\n"); break; case LWM2M_TYPE_BOOLEAN: fprintf(stream, "LWM2M_TYPE_BOOLEAN: "); fprintf(stream, "%s", dataP[i].value.asBoolean ? "true" : "false"); fprintf(stream, "\r\n"); break; case LWM2M_TYPE_OBJECT_LINK: fprintf(stream, "LWM2M_TYPE_OBJECT_LINK\r\n"); break; default: fprintf(stream, "unknown (%d)\r\n", (int)dataP[i].type); break; } print_indent(stream, indent); fprintf(stream, "}\r\n"); } } #define CODE_TO_STRING(X) case X : return #X static const char *prv_status_to_string(int status) { switch(status) { CODE_TO_STRING(COAP_NO_ERROR); CODE_TO_STRING(COAP_IGNORE); CODE_TO_STRING(COAP_201_CREATED); CODE_TO_STRING(COAP_202_DELETED); CODE_TO_STRING(COAP_204_CHANGED); CODE_TO_STRING(COAP_205_CONTENT); CODE_TO_STRING(COAP_400_BAD_REQUEST); CODE_TO_STRING(COAP_401_UNAUTHORIZED); CODE_TO_STRING(COAP_404_NOT_FOUND); CODE_TO_STRING(COAP_405_METHOD_NOT_ALLOWED); CODE_TO_STRING(COAP_406_NOT_ACCEPTABLE); CODE_TO_STRING(COAP_500_INTERNAL_SERVER_ERROR); CODE_TO_STRING(COAP_501_NOT_IMPLEMENTED); CODE_TO_STRING(COAP_503_SERVICE_UNAVAILABLE); default: return ""; } } void print_status(FILE *stream, uint8_t status) { fprintf(stream, "%d.%02d (%s)", (status & 0xE0) >> 5, status & 0x1F, prv_status_to_string(status)); } /********************************************************** * Base64 decoding function * * WARNING: Bugged for input strings with length < 4 * */ #define PRV_B64_PADDING '=' static uint8_t prv_b64Revert(uint8_t value) { if (value >= 'A' && value <= 'Z') { return (value - 'A'); } if (value >= 'a' && value <= 'z') { return (26 + value - 'a'); } if (value >= '0' && value <= '9') { return (52 + value - '0'); } switch (value) { case '+': return 62; case '/': return 63; default: return 0; } } static void prv_decodeBlock(uint8_t input[4], uint8_t output[3]) { uint8_t tmp[4]; int i; memset(output, 0, 3); for (i = 0; i < 4; i++) { tmp[i] = prv_b64Revert(input[i]); } output[0] = (tmp[0] << 2) | (tmp[1] >> 4); output[1] = (tmp[1] << 4) | (tmp[2] >> 2); output[2] = (tmp[2] << 6) | tmp[3]; } size_t base64_decode(uint8_t *dataP, size_t dataLen, uint8_t **bufferP) { size_t data_index; size_t result_index; size_t result_len; if (dataLen % 4) return 0; result_len = (dataLen >> 2) * 3; *bufferP = (uint8_t *)lwm2m_malloc(result_len); if (NULL == *bufferP) return 0; memset(*bufferP, 0, result_len); // remove padding while (dataP[dataLen - 1] == PRV_B64_PADDING) { dataLen--; } data_index = 0; result_index = 0; while (data_index < dataLen) { prv_decodeBlock(dataP + data_index, *bufferP + result_index); data_index += 4; result_index += 3; } switch (data_index - dataLen) { case 0: break; case 2: { uint8_t tmp[2]; tmp[0] = prv_b64Revert(dataP[dataLen - 2]); tmp[1] = prv_b64Revert(dataP[dataLen - 1]); *bufferP[result_index - 3] = (tmp[0] << 2) | (tmp[1] >> 4); *bufferP[result_index - 2] = (tmp[1] << 4); result_len -= 2; } break; case 3: { uint8_t tmp[3]; tmp[0] = prv_b64Revert(dataP[dataLen - 3]); tmp[1] = prv_b64Revert(dataP[dataLen - 2]); tmp[2] = prv_b64Revert(dataP[dataLen - 1]); *bufferP[result_index - 3] = (tmp[0] << 2) | (tmp[1] >> 4); *bufferP[result_index - 2] = (tmp[1] << 4) | (tmp[2] >> 2); *bufferP[result_index - 1] = (tmp[2] << 6); result_len -= 1; } break; default: // error lwm2m_free(*bufferP); *bufferP = NULL; result_len = 0; break; } return result_len; } ================================================ FILE: Huawei_LiteOS/components/connectivity/lwm2m/examples/shared/commandline.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /******************************************************************************* * * Copyright (c) 2013 Intel Corporation and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * The Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * David Navarro, Intel Corporation - initial API and implementation * *******************************************************************************/ #include #define COMMAND_END_LIST {NULL, NULL, NULL, NULL, NULL} typedef void (*command_handler_t) (char * args, void * user_data); typedef struct { char * name; char * shortDesc; char * longDesc; command_handler_t callback; void * userData; } command_desc_t; void handle_command(command_desc_t * commandArray, char * buffer); char* get_end_of_arg(char* buffer); char * get_next_arg(char * buffer, char **end); int check_end_of_args(char* buffer); void output_buffer(FILE * stream, uint8_t * buffer, int length, int indent); void output_tlv(FILE * stream, uint8_t * buffer, size_t buffer_len, int indent); void dump_tlv(FILE * stream, int size, lwm2m_data_t * dataP, int indent); void output_data(FILE * stream, lwm2m_media_type_t format, uint8_t * buffer, int length, int indent); void print_status(FILE * stream, uint8_t status); size_t base64_decode(uint8_t * dataP, size_t dataLen, uint8_t ** bufferP); ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/.cproject ================================================ ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/.gitignore ================================================ /dep/ /build/ /build.paho/ *.swp *.pyc /doc/MQTTClient/ /doc/MQTTPacket/ /doc/MQTTClient-C/ ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/.project 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org.eclipse.cdt.core.formatter.keep_else_statement_on_same_line=false org.eclipse.cdt.core.formatter.keep_empty_array_initializer_on_one_line=false org.eclipse.cdt.core.formatter.keep_imple_if_on_one_line=false org.eclipse.cdt.core.formatter.keep_then_statement_on_same_line=false org.eclipse.cdt.core.formatter.lineSplit=80 org.eclipse.cdt.core.formatter.number_of_empty_lines_to_preserve=1 org.eclipse.cdt.core.formatter.put_empty_statement_on_new_line=true org.eclipse.cdt.core.formatter.tabulation.char=tab org.eclipse.cdt.core.formatter.tabulation.size=4 org.eclipse.cdt.core.formatter.use_tabs_only_for_leading_indentations=false ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/.settings/org.eclipse.cdt.ui.prefs ================================================ eclipse.preferences.version=1 formatter_profile=org.eclipse.cdt.ui.default.allman_profile formatter_settings_version=1 ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/.travis.yml ================================================ sudo: true language: c compiler: - gcc os: - linux sudo: required before_install: - ./travis-install.sh script: - if [[ "$COVERITY_SCAN_BRANCH" != 1 ]]; then ./travis-build.sh; fi addons: apt: sources: - george-edison55-precise-backports # cmake 3.2.3 / doxygen 1.8.3 - sourceline: 'ppa:mosquitto-dev/mosquitto-ppa' packages: - cmake - cmake-data - mosquitto - doxygen ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/CMakeLists.txt ================================================ #******************************************************************************* # Copyright (c) 2017 IBM Corp. # # All rights reserved. This program and the accompanying materials # are made available under the terms of the Eclipse Public License v1.0 # and Eclipse Distribution License v1.0 which accompany this distribution. # # The Eclipse Public License is available at # http://www.eclipse.org/legal/epl-v10.html # and the Eclipse Distribution License is available at # http://www.eclipse.org/org/documents/edl-v10.php. # # Contributors: # Ian Craggs - initial version #*******************************************************************************/ cmake_minimum_required(VERSION 2.8) project (embedded-mqtt) set(CMAKE_BUILD_TYPE Debug) message(STATUS "CMake version: " ${CMAKE_VERSION}) message(STATUS "CMake system name: " ${CMAKE_SYSTEM_NAME}) set(CMAKE_SCRIPTS "${CMAKE_SOURCE_DIR}/cmake") set(CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake/modules") ## build settings set(PAHO_VERSION_MAJOR 1) set(PAHO_VERSION_MINOR 0) set(PAHO_VERSION_PATCH 0) set(CLIENT_VERSION ${PAHO_VERSION_MAJOR}.${PAHO_VERSION_MINOR}.${PAHO_VERSION_PATCH}) string(TIMESTAMP BUILD_TIMESTAMP UTC) message(STATUS "Timestamp is ${BUILD_TIMESTAMP}") set(CPACK_PACKAGE_VERSION_MAJOR ${PAHO_VERSION_MAJOR}) set(CPACK_PACKAGE_VERSION_MINOR ${PAHO_VERSION_MINOR}) set(CPACK_PACKAGE_VERSION_PATCH ${PAHO_VERSION_PATCH}) include(CPack) include_directories(MQTTPacket/src) enable_testing() ADD_SUBDIRECTORY(MQTTPacket) ADD_SUBDIRECTORY(MQTTClient) ADD_SUBDIRECTORY(MQTTClient-C) ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/CONTRIBUTING.md ================================================ # Contributing to Paho Thanks for your interest in this project! You can contribute bugfixes and new features by sending pull requests through GitHub. ## Legal In order for your contribution to be accepted, it must comply with the Eclipse Foundation IP policy. Please read the [Eclipse Foundation policy on accepting contributions via Git](http://wiki.eclipse.org/Development_Resources/Contributing_via_Git). 1. Sign the [Eclipse CLA](http://www.eclipse.org/legal/CLA.php) 1. Register for an Eclipse Foundation User ID. You can register [here](https://dev.eclipse.org/site_login/createaccount.php). 2. Log into the [Projects Portal](https://projects.eclipse.org/), and click on the '[Eclipse CLA](https://projects.eclipse.org/user/sign/cla)' link. 2. Go to your [account settings](https://dev.eclipse.org/site_login/myaccount.php#open_tab_accountsettings) and add your GitHub username to your account. 3. Make sure that you _sign-off_ your Git commits in the following format: ``` Signed-off-by: John Smith ``` This is usually at the bottom of the commit message. You can automate this by adding the '-s' flag when you make the commits. e.g. ```git commit -s -m "Adding a cool feature"``` 4. Ensure that the email address that you make your commits with is the same one you used to sign up to the Eclipse Foundation website with. ## Contributing a change 1. [Fork the repository on GitHub](https://github.com/eclipse/paho.mqtt.embedded-c/fork) 2. Clone the forked repository onto your computer: ``` git clone https://github.com//paho.mqtt.embedded-c.git ``` 3. Create a new branch from the latest ```develop``` branch with ```git checkout -b YOUR_BRANCH_NAME origin/develop``` 4. Make your changes 5. If developing a new feature, make sure to include JUnit tests. 6. Ensure that all new and existing tests pass. 7. Commit the changes into the branch: ``` git commit -s ``` Make sure that your commit message is meaningful and describes your changes correctly. 8. If you have a lot of commits for the change, squash them into a single / few commits. 9. Push the changes in your branch to your forked repository. 10. Finally, go to [https://github.com/eclipse/paho.mqtt.embedded-c](https://github.com/eclipse/paho.mqtt.embedded-c) and create a pull request from your "YOUR_BRANCH_NAME" branch to the ```develop``` one to request review and merge of the commits in your pushed branch. What happens next depends on the content of the patch. If it is 100% authored by the contributor and is less than 1000 lines (and meets the needs of the project), then it can be pulled into the main repository. If not, more steps are required. These are detailed in the [legal process poster](http://www.eclipse.org/legal/EclipseLegalProcessPoster.pdf). ## Developer resources: Information regarding source code management, builds, coding standards, and more. - [https://projects.eclipse.org/projects/iot.paho/developer](https://projects.eclipse.org/projects/iot.paho/developer) Contact: -------- Contact the project developers via the project's development [mailing list](https://dev.eclipse.org/mailman/listinfo/paho-dev). Search for bugs: ---------------- This project uses GitHub Issues here: [github.com/eclipse/paho.mqtt.embedded-c/issues](https://github.com/eclipse/paho.mqtt.embedded-c/issues) to track ongoing development and issues. Create a new bug: ----------------- Be sure to search for existing bugs before you create another one. Remember that contributions are always welcome! - [Create new Paho bug](https://github.com/eclipse/paho.mqtt.embedded-c/issues) ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/CMakeLists.txt ================================================ #******************************************************************************* # Copyright (c) 2017 IBM Corp. # # All rights reserved. This program and the accompanying materials # are made available under the terms of the Eclipse Public License v1.0 # and Eclipse Distribution License v1.0 which accompany this distribution. # # The Eclipse Public License is available at # http://www.eclipse.org/legal/epl-v10.html # and the Eclipse Distribution License is available at # http://www.eclipse.org/org/documents/edl-v10.php. # # Contributors: # Ian Craggs - initial version #*******************************************************************************/ project("paho-mqttclient" C) ADD_SUBDIRECTORY(src) ADD_SUBDIRECTORY(samples) ADD_SUBDIRECTORY(test) ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/samples/CMakeLists.txt ================================================ #******************************************************************************* # Copyright (c) 2017 IBM Corp. # # All rights reserved. This program and the accompanying materials # are made available under the terms of the Eclipse Public License v1.0 # and Eclipse Distribution License v1.0 which accompany this distribution. # # The Eclipse Public License is available at # http://www.eclipse.org/legal/epl-v10.html # and the Eclipse Distribution License is available at # http://www.eclipse.org/org/documents/edl-v10.php. # # Contributors: # Ian Craggs - initial version #*******************************************************************************/ add_subdirectory(linux) ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/samples/FreeRTOS/MQTTEcho.c ================================================ /* Standard includes. */ #include #include #include /* FreeRTOS includes. */ #include "FreeRTOS.h" #include "task.h" #include "queue.h" /* FreeRTOS+TCP includes. */ #include "FreeRTOS_IP.h" #include "FreeRTOS_Sockets.h" #define MQTT_TASK 1 #include "MQTTClient.h" void messageArrived(MessageData *data) { printf("Message arrived on topic %.*s: %.*s\n", data->topicName->lenstring.len, data->topicName->lenstring.data, data->message->payloadlen, data->message->payload); } static void prvMQTTEchoTask(void *pvParameters) { /* connect to m2m.eclipse.org, subscribe to a topic, send and receive messages regularly every 1 sec */ MQTTClient client; Network network; unsigned char sendbuf[80], readbuf[80]; int rc = 0, count = 0; MQTTPacket_connectData connectData = MQTTPacket_connectData_initializer; pvParameters = 0; NetworkInit(&network); MQTTClientInit(&client, &network, 30000, sendbuf, sizeof(sendbuf), readbuf, sizeof(readbuf)); char *address = "iot.eclipse.org"; if ((rc = NetworkConnect(&network, address, 1883)) != 0) printf("Return code from network connect is %d\n", rc); #if defined(MQTT_TASK) if ((rc = MQTTStartTask(&client)) != pdPASS) printf("Return code from start tasks is %d\n", rc); #endif connectData.MQTTVersion = 3; connectData.clientID.cstring = "FreeRTOS_sample"; if ((rc = MQTTConnect(&client, &connectData)) != 0) printf("Return code from MQTT connect is %d\n", rc); else printf("MQTT Connected\n"); if ((rc = MQTTSubscribe(&client, "FreeRTOS/sample/#", 2, messageArrived)) != 0) printf("Return code from MQTT subscribe is %d\n", rc); while (++count) { MQTTMessage message; char payload[30]; message.qos = 1; message.retained = 0; message.payload = payload; sprintf(payload, "message number %d", count); message.payloadlen = strlen(payload); if ((rc = MQTTPublish(&client, "FreeRTOS/sample/a", &message)) != 0) printf("Return code from MQTT publish is %d\n", rc); #if !defined(MQTT_TASK) if ((rc = MQTTYield(&client, 1000)) != 0) printf("Return code from yield is %d\n", rc); #endif } /* do not return */ } void vStartMQTTTasks(uint16_t usTaskStackSize, UBaseType_t uxTaskPriority) { BaseType_t x = 0L; xTaskCreate(prvMQTTEchoTask, /* The function that implements the task. */ "MQTTEcho0", /* Just a text name for the task to aid debugging. */ usTaskStackSize, /* The stack size is defined in FreeRTOSIPConfig.h. */ (void *)x, /* The task parameter, not used in this case. */ uxTaskPriority, /* The priority assigned to the task is defined in FreeRTOSConfig.h. */ NULL); /* The task handle is not used. */ } /*-----------------------------------------------------------*/ ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/samples/linux/CMakeLists.txt ================================================ #******************************************************************************* # Copyright (c) 2017 IBM Corp. # # All rights reserved. This program and the accompanying materials # are made available under the terms of the Eclipse Public License v1.0 # and Eclipse Distribution License v1.0 which accompany this distribution. # # The Eclipse Public License is available at # http://www.eclipse.org/legal/epl-v10.html # and the Eclipse Distribution License is available at # http://www.eclipse.org/org/documents/edl-v10.php. # # Contributors: # Ian Craggs - initial version #*******************************************************************************/ add_executable( stdoutsubc stdoutsub.c ) target_link_libraries(stdoutsubc paho-embed-mqtt3cc paho-embed-mqtt3c) target_include_directories(stdoutsubc PRIVATE "../../src" "../../src/linux") target_compile_definitions(stdoutsubc PRIVATE MQTTCLIENT_PLATFORM_HEADER=MQTTLinux.h) ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/samples/linux/build.sh ================================================ cp ../../src/MQTTClient.c . sed -e 's/""/"MQTTLinux.h"/g' ../../src/MQTTClient.h > MQTTClient.h gcc stdoutsub.c -I ../../src -I ../../src/linux -I ../../../MQTTPacket/src MQTTClient.c ../../src/linux/MQTTLinux.c ../../../MQTTPacket/src/MQTTFormat.c ../../../MQTTPacket/src/MQTTPacket.c ../../../MQTTPacket/src/MQTTDeserializePublish.c ../../../MQTTPacket/src/MQTTConnectClient.c ../../../MQTTPacket/src/MQTTSubscribeClient.c ../../../MQTTPacket/src/MQTTSerializePublish.c -o stdoutsub ../../../MQTTPacket/src/MQTTConnectServer.c ../../../MQTTPacket/src/MQTTSubscribeServer.c ../../../MQTTPacket/src/MQTTUnsubscribeServer.c ../../../MQTTPacket/src/MQTTUnsubscribeClient.c -DMQTTCLIENT_PLATFORM_HEADER=MQTTLinux.h ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/samples/linux/stdoutsub.c ================================================ /******************************************************************************* * Copyright (c) 2012, 2016 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial contribution * Ian Craggs - change delimiter option from char to string * Al Stockdill-Mander - Version using the embedded C client * Ian Craggs - update MQTTClient function names *******************************************************************************/ /* stdout subscriber compulsory parameters: topic to subscribe to defaulted parameters: --host localhost --port 1883 --qos 2 --delimiter \n --clientid stdout_subscriber --userid none --password none for example: stdoutsub topic/of/interest --host iot.eclipse.org */ #include #include #include "MQTTClient.h" #include #include #include volatile int toStop = 0; void usage() { printf("MQTT stdout subscriber\n"); printf("Usage: stdoutsub topicname , where options are:\n"); printf(" --host (default is localhost)\n"); printf(" --port (default is 1883)\n"); printf(" --qos (default is 2)\n"); printf(" --delimiter (default is \\n)\n"); printf(" --clientid (default is hostname+timestamp)\n"); printf(" --username none\n"); printf(" --password none\n"); printf(" --showtopics (default is on if the topic has a wildcard, else off)\n"); exit(-1); } void cfinish(int sig) { signal(SIGINT, NULL); toStop = 1; } struct opts_struct { char *clientid; int nodelimiter; char *delimiter; enum QoS qos; char *username; char *password; char *host; int port; int showtopics; } opts = { (char *)"stdout-subscriber", 0, (char *)"\n", QOS2, NULL, NULL, (char *)"localhost", 1883, 0 }; void getopts(int argc, char **argv) { int count = 2; while (count < argc) { if (strcmp(argv[count], "--qos") == 0) { if (++count < argc) { if (strcmp(argv[count], "0") == 0) opts.qos = QOS0; else if (strcmp(argv[count], "1") == 0) opts.qos = QOS1; else if (strcmp(argv[count], "2") == 0) opts.qos = QOS2; else usage(); } else usage(); } else if (strcmp(argv[count], "--host") == 0) { if (++count < argc) opts.host = argv[count]; else usage(); } else if (strcmp(argv[count], "--port") == 0) { if (++count < argc) opts.port = atoi(argv[count]); else usage(); } else if (strcmp(argv[count], "--clientid") == 0) { if (++count < argc) opts.clientid = argv[count]; else usage(); } else if (strcmp(argv[count], "--username") == 0) { if (++count < argc) opts.username = argv[count]; else usage(); } else if (strcmp(argv[count], "--password") == 0) { if (++count < argc) opts.password = argv[count]; else usage(); } else if (strcmp(argv[count], "--delimiter") == 0) { if (++count < argc) opts.delimiter = argv[count]; else opts.nodelimiter = 1; } else if (strcmp(argv[count], "--showtopics") == 0) { if (++count < argc) { if (strcmp(argv[count], "on") == 0) opts.showtopics = 1; else if (strcmp(argv[count], "off") == 0) opts.showtopics = 0; else usage(); } else usage(); } count++; } } void messageArrived(MessageData *md) { MQTTMessage *message = md->message; if (opts.showtopics) printf("%.*s\t", md->topicName->lenstring.len, md->topicName->lenstring.data); if (opts.nodelimiter) printf("%.*s", (int)message->payloadlen, (char *)message->payload); else printf("%.*s%s", (int)message->payloadlen, (char *)message->payload, opts.delimiter); //fflush(stdout); } int main(int argc, char **argv) { int rc = 0; unsigned char buf[100]; unsigned char readbuf[100]; if (argc < 2) usage(); char *topic = argv[1]; if (strchr(topic, '#') || strchr(topic, '+')) opts.showtopics = 1; if (opts.showtopics) printf("topic is %s\n", topic); getopts(argc, argv); Network n; MQTTClient c; signal(SIGINT, cfinish); signal(SIGTERM, cfinish); NetworkInit(&n); NetworkConnect(&n, opts.host, opts.port); MQTTClientInit(&c, &n, 1000, buf, 100, readbuf, 100); MQTTPacket_connectData data = MQTTPacket_connectData_initializer; data.willFlag = 0; data.MQTTVersion = 3; data.clientID.cstring = opts.clientid; data.username.cstring = opts.username; data.password.cstring = opts.password; data.keepAliveInterval = 10; data.cleansession = 1; printf("Connecting to %s %d\n", opts.host, opts.port); rc = MQTTConnect(&c, &data); printf("Connected %d\n", rc); printf("Subscribing to %s\n", topic); rc = MQTTSubscribe(&c, topic, opts.qos, messageArrived); printf("Subscribed %d\n", rc); while (!toStop) { MQTTYield(&c, 1000); } printf("Stopping\n"); MQTTDisconnect(&c); NetworkDisconnect(&n); return 0; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/src/CMakeLists.txt ================================================ #******************************************************************************* # Copyright (c) 2017 IBM Corp. # # All rights reserved. This program and the accompanying materials # are made available under the terms of the Eclipse Public License v1.0 # and Eclipse Distribution License v1.0 which accompany this distribution. # # The Eclipse Public License is available at # http://www.eclipse.org/legal/epl-v10.html # and the Eclipse Distribution License is available at # http://www.eclipse.org/org/documents/edl-v10.php. # # Contributors: # Ian Craggs - initial version #*******************************************************************************/ # MQTTClient Library - C file(GLOB SOURCES "*.c" "linux/*.c") add_library( paho-embed-mqtt3cc SHARED ${SOURCES} ) install(TARGETS paho-embed-mqtt3cc DESTINATION /usr/lib) target_include_directories(paho-embed-mqtt3cc PRIVATE "linux") target_link_libraries(paho-embed-mqtt3cc paho-embed-mqtt3c) target_compile_definitions(paho-embed-mqtt3cc PRIVATE MQTTCLIENT_PLATFORM_HEADER=MQTTLinux.h MQTTCLIENT_QOS2=1) ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/src/FreeRTOS/MQTTFreeRTOS.c ================================================ /******************************************************************************* * Copyright (c) 2014, 2015 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Allan Stockdill-Mander - initial API and implementation and/or initial documentation * Ian Craggs - convert to FreeRTOS *******************************************************************************/ #include "MQTTFreeRTOS.h" int ThreadStart(Thread *thread, void (*fn)(void *), void *arg) { int rc = 0; uint16_t usTaskStackSize = (configMINIMAL_STACK_SIZE * 5); UBaseType_t uxTaskPriority = uxTaskPriorityGet(NULL); /* set the priority as the same as the calling task*/ rc = xTaskCreate(fn, /* The function that implements the task. */ "MQTTTask", /* Just a text name for the task to aid debugging. */ usTaskStackSize, /* The stack size is defined in FreeRTOSIPConfig.h. */ arg, /* The task parameter, not used in this case. */ uxTaskPriority, /* The priority assigned to the task is defined in FreeRTOSConfig.h. */ &thread->task); /* The task handle is not used. */ return rc; } void MutexInit(Mutex *mutex) { mutex->sem = xSemaphoreCreateMutex(); } int MutexLock(Mutex *mutex) { return xSemaphoreTake(mutex->sem, portMAX_DELAY); } int MutexUnlock(Mutex *mutex) { return xSemaphoreGive(mutex->sem); } void TimerCountdownMS(Timer *timer, unsigned int timeout_ms) { timer->xTicksToWait = timeout_ms / portTICK_PERIOD_MS; /* convert milliseconds to ticks */ vTaskSetTimeOutState(&timer->xTimeOut); /* Record the time at which this function was entered. */ } void TimerCountdown(Timer *timer, unsigned int timeout) { TimerCountdownMS(timer, timeout * 1000); } int TimerLeftMS(Timer *timer) { xTaskCheckForTimeOut(&timer->xTimeOut, &timer->xTicksToWait); /* updates xTicksToWait to the number left */ return (timer->xTicksToWait < 0) ? 0 : (timer->xTicksToWait * portTICK_PERIOD_MS); } char TimerIsExpired(Timer *timer) { return xTaskCheckForTimeOut(&timer->xTimeOut, &timer->xTicksToWait) == pdTRUE; } void TimerInit(Timer *timer) { timer->xTicksToWait = 0; memset(&timer->xTimeOut, '\0', sizeof(timer->xTimeOut)); } int FreeRTOS_read(Network *n, unsigned char *buffer, int len, int timeout_ms) { TickType_t xTicksToWait = timeout_ms / portTICK_PERIOD_MS; /* convert milliseconds to ticks */ TimeOut_t xTimeOut; int recvLen = 0; vTaskSetTimeOutState(&xTimeOut); /* Record the time at which this function was entered. */ do { int rc = 0; FreeRTOS_setsockopt(n->my_socket, 0, FREERTOS_SO_RCVTIMEO, &xTicksToWait, sizeof(xTicksToWait)); rc = FreeRTOS_recv(n->my_socket, buffer + recvLen, len - recvLen, 0); if (rc > 0) recvLen += rc; else if (rc < 0) { recvLen = rc; break; } } while (recvLen < len && xTaskCheckForTimeOut(&xTimeOut, &xTicksToWait) == pdFALSE); return recvLen; } int FreeRTOS_write(Network *n, unsigned char *buffer, int len, int timeout_ms) { TickType_t xTicksToWait = timeout_ms / portTICK_PERIOD_MS; /* convert milliseconds to ticks */ TimeOut_t xTimeOut; int sentLen = 0; vTaskSetTimeOutState(&xTimeOut); /* Record the time at which this function was entered. */ do { int rc = 0; FreeRTOS_setsockopt(n->my_socket, 0, FREERTOS_SO_RCVTIMEO, &xTicksToWait, sizeof(xTicksToWait)); rc = FreeRTOS_send(n->my_socket, buffer + sentLen, len - sentLen, 0); if (rc > 0) sentLen += rc; else if (rc < 0) { sentLen = rc; break; } } while (sentLen < len && xTaskCheckForTimeOut(&xTimeOut, &xTicksToWait) == pdFALSE); return sentLen; } void FreeRTOS_disconnect(Network *n) { FreeRTOS_closesocket(n->my_socket); } void NetworkInit(Network *n) { n->my_socket = 0; n->mqttread = FreeRTOS_read; n->mqttwrite = FreeRTOS_write; n->disconnect = FreeRTOS_disconnect; } int NetworkConnect(Network *n, char *addr, int port) { struct freertos_sockaddr sAddr; int retVal = -1; uint32_t ipAddress; if ((ipAddress = FreeRTOS_gethostbyname(addr)) == 0) goto exit; sAddr.sin_port = FreeRTOS_htons(port); sAddr.sin_addr = ipAddress; if ((n->my_socket = FreeRTOS_socket(FREERTOS_AF_INET, FREERTOS_SOCK_STREAM, FREERTOS_IPPROTO_TCP)) < 0) goto exit; if ((retVal = FreeRTOS_connect(n->my_socket, &sAddr, sizeof(sAddr))) < 0) { FreeRTOS_closesocket(n->my_socket); goto exit; } exit: return retVal; } #if 0 int NetworkConnectTLS(Network *n, char *addr, int port, SlSockSecureFiles_t *certificates, unsigned char sec_method, unsigned int cipher, char server_verify) { SlSockAddrIn_t sAddr; int addrSize; int retVal; unsigned long ipAddress; retVal = sl_NetAppDnsGetHostByName(addr, strlen(addr), &ipAddress, AF_INET); if (retVal < 0) { return -1; } sAddr.sin_family = AF_INET; sAddr.sin_port = sl_Htons((unsigned short)port); sAddr.sin_addr.s_addr = sl_Htonl(ipAddress); addrSize = sizeof(SlSockAddrIn_t); n->my_socket = sl_Socket(SL_AF_INET, SL_SOCK_STREAM, SL_SEC_SOCKET); if (n->my_socket < 0) { return -1; } SlSockSecureMethod method; method.secureMethod = sec_method; retVal = sl_SetSockOpt(n->my_socket, SL_SOL_SOCKET, SL_SO_SECMETHOD, &method, sizeof(method)); if (retVal < 0) { return retVal; } SlSockSecureMask mask; mask.secureMask = cipher; retVal = sl_SetSockOpt(n->my_socket, SL_SOL_SOCKET, SL_SO_SECURE_MASK, &mask, sizeof(mask)); if (retVal < 0) { return retVal; } if (certificates != NULL) { retVal = sl_SetSockOpt(n->my_socket, SL_SOL_SOCKET, SL_SO_SECURE_FILES, certificates->secureFiles, sizeof(SlSockSecureFiles_t)); if (retVal < 0) { return retVal; } } retVal = sl_Connect(n->my_socket, (SlSockAddr_t *)&sAddr, addrSize); if (retVal < 0) { if (server_verify || retVal != -453) { sl_Close(n->my_socket); return retVal; } } SysTickIntRegister(SysTickIntHandler); SysTickPeriodSet(80000); SysTickEnable(); return retVal; } #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/src/FreeRTOS/MQTTFreeRTOS.h ================================================ /******************************************************************************* * Copyright (c) 2014, 2015 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Allan Stockdill-Mander - initial API and implementation and/or initial documentation *******************************************************************************/ #if !defined(MQTTFreeRTOS_H) #define MQTTFreeRTOS_H #include "FreeRTOS.h" #include "FreeRTOS_Sockets.h" #include "FreeRTOS_IP.h" #include "semphr.h" #include "task.h" typedef struct Timer { TickType_t xTicksToWait; TimeOut_t xTimeOut; } Timer; typedef struct Network Network; struct Network { xSocket_t my_socket; int (*mqttread) (Network*, unsigned char*, int, int); int (*mqttwrite) (Network*, unsigned char*, int, int); void (*disconnect) (Network*); }; void TimerInit(Timer*); char TimerIsExpired(Timer*); void TimerCountdownMS(Timer*, unsigned int); void TimerCountdown(Timer*, unsigned int); int TimerLeftMS(Timer*); typedef struct Mutex { SemaphoreHandle_t sem; } Mutex; void MutexInit(Mutex*); int MutexLock(Mutex*); int MutexUnlock(Mutex*); typedef struct Thread { TaskHandle_t task; } Thread; int ThreadStart(Thread*, void (*fn)(void*), void* arg); int FreeRTOS_read(Network*, unsigned char*, int, int); int FreeRTOS_write(Network*, unsigned char*, int, int); void FreeRTOS_disconnect(Network*); void NetworkInit(Network*); int NetworkConnect(Network*, char*, int); /*int NetworkConnectTLS(Network*, char*, int, SlSockSecureFiles_t*, unsigned char, unsigned int, char);*/ #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/src/MQTTClient.c ================================================ /******************************************************************************* * Copyright (c) 2014, 2017 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Allan Stockdill-Mander/Ian Craggs - initial API and implementation and/or initial documentation * Ian Craggs - fix for #96 - check rem_len in readPacket * Ian Craggs - add ability to set message handler separately #6 *******************************************************************************/ #include "MQTTClient.h" static void NewMessageData(MessageData *md, MQTTString *aTopicName, MQTTMessage *aMessage, const char *topic_sub) { md->topicName = aTopicName; md->message = aMessage; } static int getNextPacketId(MQTTClient *c) { return c->next_packetid = (c->next_packetid == MAX_PACKET_ID) ? 1 : c->next_packetid + 1; } static int sendPacket(MQTTClient* c, int length, Timer* timer) { int rc = FAILURE, sent = 0; while (sent < length && !TimerIsExpired(timer)) { rc = c->ipstack->mqttwrite(c->ipstack, &c->buf[sent], length, TimerLeftMS(timer)); if (rc < 0) // there was an error writing the data break; sent += rc; } if (sent == length) { TimerCountdown(&c->last_sent, c->keepAliveInterval); // record the fact that we have successfully sent the packet rc = MQTT_SUCCESS; } else rc = FAILURE; return rc; } int MQTTClientInit(MQTTClient *c, Network *network, unsigned int command_timeout_ms, unsigned char *sendbuf, size_t sendbuf_size, unsigned char *readbuf, size_t readbuf_size) { int i; c->ipstack = network; for (i = 0; i < MAX_MESSAGE_HANDLERS; ++i) c->messageHandlers[i].topicFilter = 0; c->command_timeout_ms = command_timeout_ms; c->buf = sendbuf; c->buf_size = sendbuf_size; c->readbuf = readbuf; c->readbuf_size = readbuf_size; c->isconnected = 0; c->cleansession = 0; c->ping_outstanding = 0; c->defaultMessageHandler = NULL; c->next_packetid = 1; TimerInit(&c->last_sent); TimerInit(&c->last_received); #if defined(MQTT_TASK) if (MutexInit(&c->mutex) != 0) { return FAILURE; } #endif return MQTT_SUCCESS; } void MQTTClientDeInit(MQTTClient *c) { if(!c) return; #if defined(MQTT_TASK) MutexDestory(&c->mutex); #endif return; } static int decodePacket(MQTTClient* c, int* value, int timeout) { unsigned char i; int multiplier = 1; int len = 0; const int MAX_NO_OF_REMAINING_LENGTH_BYTES = 4; *value = 0; do { int rc = MQTTPACKET_READ_ERROR; if (++len > MAX_NO_OF_REMAINING_LENGTH_BYTES) { rc = MQTTPACKET_READ_ERROR; /* bad data */ goto exit; } rc = c->ipstack->mqttread(c->ipstack, &i, 1, timeout); if (rc != 1) goto exit; *value += (i & 127) * multiplier; multiplier *= 128; } while ((i & 128) != 0); exit: return len; } static int readPacket(MQTTClient* c, Timer* timer) { MQTTHeader header = {0}; int len = 0; int rem_len = 0; /* 1. read the header byte. This has the packet type in it */ int rc = c->ipstack->mqttread(c->ipstack, c->readbuf, 1, TimerLeftMS(timer)); if (rc != 1) goto exit; len = 1; /* 2. read the remaining length. This is variable in itself */ decodePacket(c, &rem_len, TimerLeftMS(timer)); len += MQTTPacket_encode(c->readbuf + 1, rem_len); /* put the original remaining length back into the buffer */ if (rem_len > (c->readbuf_size - len)) { rc = BUFFER_OVERFLOW; goto exit; } /* 3. read the rest of the buffer using a callback to supply the rest of the data */ if (rem_len > 0 && (rc = c->ipstack->mqttread(c->ipstack, c->readbuf + len, rem_len, TimerLeftMS(timer)) != rem_len)) { rc = 0; goto exit; } header.byte = c->readbuf[0]; rc = header.bits.type; if (c->keepAliveInterval > 0) TimerCountdown(&c->last_received, c->keepAliveInterval); // record the fact that we have successfully received a packet exit: return rc; } /** * Copyright (c) 2009-2018 Roger Light * licensed under the Eclipse Public License 1.0 and the Eclipse Distribution License 1.0 */ static int MQTTTopicMatched(const char *sub, MQTTString *topic_name, char *result) { int sublen, topiclen; int spos, tpos; char multilevel_wildcard = 0; char *topic; if(!result) return -1; *result = 0; if(!sub || !topic_name) { return -1; } sublen = strlen(sub); if(topic_name->cstring) { topic = topic_name->cstring; topiclen = strlen(topic_name->cstring); } else { topic = topic_name->lenstring.data; topiclen = topic_name->lenstring.len; } if(!sublen || !topiclen) { *result = 0; return -1; } if(sublen && topiclen) { if((sub[0] == '$' && topic[0] != '$') || (topic[0] == '$' && sub[0] != '$')) { return 0; } } spos = 0; tpos = 0; while(spos < sublen && tpos <= topiclen) { if(sub[spos] == topic[tpos]) { if(tpos == topiclen - 1) { /* Check for e.g. foo matching foo/# */ if(spos == sublen - 3 && sub[spos + 1] == '/' && sub[spos + 2] == '#') { *result = 1; multilevel_wildcard = 1; return 0; } } spos++; tpos++; if(spos == sublen && tpos == topiclen) { *result = 1; return 0; } else if(tpos == topiclen && spos == sublen - 1 && sub[spos] == '+') { if(spos > 0 && sub[spos - 1] != '/') { return -1; } spos++; *result = 1; return 0; } } else { if(sub[spos] == '+') { /* Check for bad "+foo" or "a/+foo" subscription */ if(spos > 0 && sub[spos - 1] != '/') { return -1; } /* Check for bad "foo+" or "foo+/a" subscription */ if(spos < sublen - 1 && sub[spos + 1] != '/') { return -1; } spos++; while(tpos < topiclen && topic[tpos] != '/') { tpos++; } if(tpos == topiclen && spos == sublen) { *result = 1; return 0; } } else if(sub[spos] == '#') { if(spos > 0 && sub[spos - 1] != '/') { return -1; } multilevel_wildcard = 1; if(spos + 1 != sublen) { return -1; } else { *result = 1; return 0; } } else { /* Check for e.g. foo/bar matching foo/+/# */ if(spos > 0 && spos + 2 == sublen && tpos == topiclen && sub[spos - 1] == '+' && sub[spos] == '/' && sub[spos + 1] == '#') { *result = 1; multilevel_wildcard = 1; return 0; } return 0; } } } if(multilevel_wildcard == 0 && (tpos < topiclen || spos < sublen)) { *result = 0; } return 0; } int deliverMessage(MQTTClient* c, MQTTString* topicName, MQTTMessage* message) { int i; int rc = FAILURE; char match_rst = 0; // we have to find the right message handler - indexed by topic for (i = 0; i < MAX_MESSAGE_HANDLERS; ++i) { if (c->messageHandlers[i].topicFilter != 0) { (void)MQTTTopicMatched((const char *)c->messageHandlers[i].topicFilter, topicName, &match_rst); if (1 == match_rst && c->messageHandlers[i].fp != NULL) { MessageData md; NewMessageData(&md, topicName, message, (const char *)c->messageHandlers[i].topicFilter); c->messageHandlers[i].fp(&md); rc = MQTT_SUCCESS; } } } if (rc == FAILURE && c->defaultMessageHandler != NULL) { MessageData md; NewMessageData(&md, topicName, message, NULL); c->defaultMessageHandler(&md); rc = MQTT_SUCCESS; } return rc; } int keepalive(MQTTClient* c) { int rc = MQTT_SUCCESS; if (c->keepAliveInterval == 0) goto exit; if (TimerIsExpired(&c->last_sent) && TimerIsExpired(&c->last_received)) { if (c->ping_outstanding) rc = FAILURE; /* PINGRESP not received in keepalive interval */ else { Timer timer; TimerInit(&timer); TimerCountdownMS(&timer, 1000); int len = MQTTSerialize_pingreq(c->buf, c->buf_size); if (len > 0 && (rc = sendPacket(c, len, &timer)) == MQTT_SUCCESS) // send the ping packet c->ping_outstanding = 1; } } exit: return rc; } void MQTTCleanSession(MQTTClient* c) { int i = 0; for (i = 0; i < MAX_MESSAGE_HANDLERS; ++i) c->messageHandlers[i].topicFilter = NULL; } void MQTTCloseSession(MQTTClient* c) { c->ping_outstanding = 0; c->isconnected = 0; if (c->cleansession) MQTTCleanSession(c); } int cycle(MQTTClient* c, Timer* timer) { int len = 0, rc = MQTT_SUCCESS; Timer send_timer; int packet_type = readPacket(c, timer); /* read the socket, see what work is due */ switch (packet_type) { default: /* no more data to read, unrecoverable. Or read packet fails due to unexpected network error */ rc = packet_type; goto exit; case 0: /* timed out reading packet */ break; case CONNACK: case PUBACK: case SUBACK: case UNSUBACK: break; case PUBLISH: { MQTTString topicName; MQTTMessage msg; int intQoS; msg.payloadlen = 0; /* this is a size_t, but deserialize publish sets this as int */ if (MQTTDeserialize_publish(&msg.dup, &intQoS, &msg.retained, &msg.id, &topicName, (unsigned char **)&msg.payload, (int *)&msg.payloadlen, c->readbuf, c->readbuf_size) != 1) goto exit; msg.qos = (enum QoS)intQoS; deliverMessage(c, &topicName, &msg); if (msg.qos != QOS0) { if (msg.qos == QOS1) len = MQTTSerialize_ack(c->buf, c->buf_size, PUBACK, 0, msg.id); else if (msg.qos == QOS2) len = MQTTSerialize_ack(c->buf, c->buf_size, PUBREC, 0, msg.id); if (len <= 0) rc = FAILURE; else { TimerInit(&send_timer); TimerCountdownMS(&send_timer, 1000); rc = sendPacket(c, len, &send_timer); } if (rc == FAILURE) goto exit; // there was a problem } break; } case PUBREC: case PUBREL: { unsigned short mypacketid; unsigned char dup, type; if (MQTTDeserialize_ack(&type, &dup, &mypacketid, c->readbuf, c->readbuf_size) != 1) rc = FAILURE; else if ((len = MQTTSerialize_ack(c->buf, c->buf_size, (packet_type == PUBREC) ? PUBREL : PUBCOMP, 0, mypacketid)) <= 0) rc = FAILURE; else { TimerInit(&send_timer); TimerCountdownMS(&send_timer, 1000); rc = sendPacket(c, len, &send_timer); if(rc != MQTT_SUCCESS) rc = FAILURE; // there was a problem } if (rc == FAILURE) goto exit; // there was a problem break; } case PUBCOMP: break; case PINGRESP: c->ping_outstanding = 0; break; } if (keepalive(c) != MQTT_SUCCESS) { //check only keepalive FAILURE status so that previous FAILURE status can be considered as FAULT rc = FAILURE; } exit: if (rc == MQTT_SUCCESS) rc = packet_type; else if (c->isconnected) MQTTCloseSession(c); return rc; } int MQTTYield(MQTTClient* c, int timeout_ms) { int rc = MQTT_SUCCESS; Timer timer; TimerInit(&timer); TimerCountdownMS(&timer, timeout_ms); do { #if defined(MQTT_TASK) (void)MutexLock(&c->mutex); #endif if ( (rc = cycle(c, &timer) ) < 0) { rc = FAILURE; #if defined(MQTT_TASK) (void)MutexUnlock(&c->mutex); #endif break; } #if defined(MQTT_TASK) (void)MutexUnlock(&c->mutex); #endif } while (!TimerIsExpired(&timer)); return rc; } void MQTTRun(void* parm) { Timer timer; MQTTClient* c = (MQTTClient*)parm; TimerInit(&timer); while (1) { #if defined(MQTT_TASK) MutexLock(&c->mutex); #endif TimerCountdownMS(&timer, 500); /* Don't wait too long if no traffic is incoming */ cycle(c, &timer); #if defined(MQTT_TASK) MutexUnlock(&c->mutex); #endif } } #if defined(MQTT_TASK) int MQTTStartTask(MQTTClient* client) { return ThreadStart(&client->thread, &MQTTRun, client); } #endif int waitfor(MQTTClient* c, int packet_type, Timer* timer) { int rc = FAILURE; do { if (TimerIsExpired(timer)) break; // we timed out rc = cycle(c, timer); } while (rc != packet_type && rc >= 0); return rc; } int MQTTConnectWithResults(MQTTClient* c, MQTTPacket_connectData* options, MQTTConnackData* data) { Timer connect_timer; int rc = FAILURE; MQTTPacket_connectData default_options = MQTTPacket_connectData_initializer; int len = 0; #if defined(MQTT_TASK) MutexLock(&c->mutex); #endif if (c->isconnected) /* don't send connect packet again if we are already connected */ goto exit; TimerInit(&connect_timer); TimerCountdownMS(&connect_timer, c->command_timeout_ms); if (options == 0) options = &default_options; /* set default options if none were supplied */ c->keepAliveInterval = options->keepAliveInterval; c->cleansession = options->cleansession; TimerCountdown(&c->last_received, c->keepAliveInterval); if ((len = MQTTSerialize_connect(c->buf, c->buf_size, options)) <= 0) goto exit; if ((rc = sendPacket(c, len, &connect_timer)) != MQTT_SUCCESS) // send the connect packet goto exit; // there was a problem // this will be a blocking call, wait for the connack if (waitfor(c, CONNACK, &connect_timer) == CONNACK) { data->rc = 0; data->sessionPresent = 0; if (MQTTDeserialize_connack(&data->sessionPresent, &data->rc, c->readbuf, c->readbuf_size) == 1) rc = data->rc; else rc = FAILURE; } else rc = FAILURE; exit: if (rc == MQTT_SUCCESS) { c->isconnected = 1; c->ping_outstanding = 0; } #if defined(MQTT_TASK) MutexUnlock(&c->mutex); #endif return rc; } int MQTTConnect(MQTTClient* c, MQTTPacket_connectData* options) { MQTTConnackData data; return MQTTConnectWithResults(c, options, &data); } int MQTTSetMessageHandler(MQTTClient* c, const char* topicFilter, messageHandler messageHandler) { int rc = FAILURE; int i = -1; /* first check for an existing matching slot */ for (i = 0; i < MAX_MESSAGE_HANDLERS; ++i) { if (c->messageHandlers[i].topicFilter != NULL && strcmp(c->messageHandlers[i].topicFilter, topicFilter) == 0) { if (messageHandler == NULL) /* remove existing */ { c->messageHandlers[i].topicFilter = NULL; c->messageHandlers[i].fp = NULL; } rc = MQTT_SUCCESS; /* return i when adding new subscription */ break; } } /* if no existing, look for empty slot (unless we are removing) */ if (messageHandler != NULL) { if (rc == FAILURE) { for (i = 0; i < MAX_MESSAGE_HANDLERS; ++i) { if (c->messageHandlers[i].topicFilter == NULL) { rc = MQTT_SUCCESS; break; } } } if (i < MAX_MESSAGE_HANDLERS) { c->messageHandlers[i].topicFilter = topicFilter; c->messageHandlers[i].fp = messageHandler; } } return rc; } int MQTTSubscribeWithResults(MQTTClient *c, const char *topicFilter, enum QoS qos, messageHandler messageHandler, MQTTSubackData *data) { int rc = FAILURE; Timer timer; int len = 0; MQTTString topic = MQTTString_initializer; topic.cstring = (char *)topicFilter; #if defined(MQTT_TASK) MutexLock(&c->mutex); #endif if (!c->isconnected) goto exit; TimerInit(&timer); TimerCountdownMS(&timer, c->command_timeout_ms); len = MQTTSerialize_subscribe(c->buf, c->buf_size, 0, getNextPacketId(c), 1, &topic, (int *)&qos); if (len <= 0) goto exit; if ((rc = sendPacket(c, len, &timer)) != MQTT_SUCCESS) // send the subscribe packet goto exit; // there was a problem if (waitfor(c, SUBACK, &timer) == SUBACK) // wait for suback { int count = 0; unsigned short mypacketid; data->grantedQoS = QOS0; if (MQTTDeserialize_suback(&mypacketid, 1, &count, (int *)&data->grantedQoS, c->readbuf, c->readbuf_size) == 1) { if (data->grantedQoS != 0x80) rc = MQTTSetMessageHandler(c, topicFilter, messageHandler); } } else rc = FAILURE; exit: if (rc == FAILURE) MQTTCloseSession(c); #if defined(MQTT_TASK) MutexUnlock(&c->mutex); #endif return rc; } int MQTTSubscribe(MQTTClient* c, const char* topicFilter, enum QoS qos, messageHandler messageHandler) { MQTTSubackData data; return MQTTSubscribeWithResults(c, topicFilter, qos, messageHandler, &data); } int MQTTUnsubscribe(MQTTClient* c, const char* topicFilter) { int rc = FAILURE; Timer timer; MQTTString topic = MQTTString_initializer; topic.cstring = (char *)topicFilter; int len = 0; #if defined(MQTT_TASK) MutexLock(&c->mutex); #endif if (!c->isconnected) goto exit; TimerInit(&timer); TimerCountdownMS(&timer, c->command_timeout_ms); if ((len = MQTTSerialize_unsubscribe(c->buf, c->buf_size, 0, getNextPacketId(c), 1, &topic)) <= 0) goto exit; if ((rc = sendPacket(c, len, &timer)) != MQTT_SUCCESS) // send the subscribe packet goto exit; // there was a problem if (waitfor(c, UNSUBACK, &timer) == UNSUBACK) { unsigned short mypacketid; // should be the same as the packetid above if (MQTTDeserialize_unsuback(&mypacketid, c->readbuf, c->readbuf_size) == 1) { /* remove the subscription message handler associated with this topic, if there is one */ MQTTSetMessageHandler(c, topicFilter, NULL); } } else rc = FAILURE; exit: if (rc == FAILURE) MQTTCloseSession(c); #if defined(MQTT_TASK) MutexUnlock(&c->mutex); #endif return rc; } int MQTTPublish(MQTTClient* c, const char* topicName, MQTTMessage* message) { int rc = FAILURE; Timer timer; MQTTString topic = MQTTString_initializer; topic.cstring = (char *)topicName; int len = 0; #if defined(MQTT_TASK) MutexLock(&c->mutex); #endif if (!c->isconnected) goto exit; TimerInit(&timer); if(message->qos == QOS2) TimerCountdownMS(&timer, c->command_timeout_ms * 2); else TimerCountdownMS(&timer, c->command_timeout_ms); if (message->qos == QOS1 || message->qos == QOS2) message->id = getNextPacketId(c); len = MQTTSerialize_publish(c->buf, c->buf_size, 0, message->qos, message->retained, message->id, topic, (unsigned char*)message->payload, message->payloadlen); if (len <= 0) goto exit; if ((rc = sendPacket(c, len, &timer)) != MQTT_SUCCESS) // send the subscribe packet goto exit; // there was a problem if (message->qos == QOS1) { if (waitfor(c, PUBACK, &timer) == PUBACK) { unsigned short mypacketid; unsigned char dup, type; if (MQTTDeserialize_ack(&type, &dup, &mypacketid, c->readbuf, c->readbuf_size) != 1) rc = FAILURE; } else rc = FAILURE; } else if (message->qos == QOS2) { if (waitfor(c, PUBCOMP, &timer) == PUBCOMP) { unsigned short mypacketid; unsigned char dup, type; if (MQTTDeserialize_ack(&type, &dup, &mypacketid, c->readbuf, c->readbuf_size) != 1) rc = FAILURE; } else rc = FAILURE; } exit: if (rc == FAILURE) MQTTCloseSession(c); #if defined(MQTT_TASK) MutexUnlock(&c->mutex); #endif return rc; } int MQTTDisconnect(MQTTClient* c) { int rc = FAILURE; Timer timer; // we might wait for incomplete incoming publishes to complete int len = 0; #if defined(MQTT_TASK) MutexLock(&c->mutex); #endif TimerInit(&timer); TimerCountdownMS(&timer, c->command_timeout_ms); len = MQTTSerialize_disconnect(c->buf, c->buf_size); if (len > 0) rc = sendPacket(c, len, &timer); // send the disconnect packet MQTTCloseSession(c); #if defined(MQTT_TASK) MutexUnlock(&c->mutex); #endif return rc; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/src/MQTTClient.h ================================================ /******************************************************************************* * Copyright (c) 2014, 2017 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Allan Stockdill-Mander/Ian Craggs - initial API and implementation and/or initial documentation * Ian Craggs - documentation and platform specific header * Ian Craggs - add setMessageHandler function *******************************************************************************/ #if !defined(MQTT_CLIENT_H) #define MQTT_CLIENT_H #if defined(__cplusplus) extern "C" { #endif #if defined(WIN32_DLL) || defined(WIN64_DLL) #define DLLImport __declspec(dllimport) #define DLLExport __declspec(dllexport) #elif defined(LINUX_SO) #define DLLImport extern #define DLLExport __attribute__ ((visibility ("default"))) #else #define DLLImport #define DLLExport #endif #include "MQTTPacket.h" #include "stdio.h" #define __MQTT_LITE_OS__ #ifdef __MQTT_LITE_OS__ #include "MQTTliteos.h" #endif #if defined(MQTTCLIENT_PLATFORM_HEADER) /* The following sequence of macros converts the MQTTCLIENT_PLATFORM_HEADER value * into a string constant suitable for use with include. */ #define xstr(s) str(s) #define str(s) #s #include xstr(MQTTCLIENT_PLATFORM_HEADER) #endif #define MAX_PACKET_ID 65535 /* according to the MQTT specification - do not change! */ #if !defined(MAX_MESSAGE_HANDLERS) #define MAX_MESSAGE_HANDLERS 5 /* redefinable - how many subscriptions do you want? */ #endif enum QoS { QOS0, QOS1, QOS2, SUBFAIL=0x80 }; /* all failure return codes must be negative */ enum returnCode { BUFFER_OVERFLOW = -2, FAILURE = -1, MQTT_SUCCESS = 0 }; /* The Platform specific header must define the Network and Timer structures and functions * which operate on them. * typedef struct Network { int (*mqttread)(Network*, unsigned char* read_buffer, int, int); int (*mqttwrite)(Network*, unsigned char* send_buffer, int, int); } Network;*/ /* The Timer structure must be defined in the platform specific header, * and have the following functions to operate on it. */ extern void TimerInit(Timer*); extern char TimerIsExpired(Timer*); extern void TimerCountdownMS(Timer*, unsigned int); extern void TimerCountdown(Timer*, unsigned int); extern int TimerLeftMS(Timer*); typedef struct MQTTMessage { enum QoS qos; unsigned char retained; unsigned char dup; unsigned short id; void *payload; size_t payloadlen; } MQTTMessage; typedef struct MessageData { MQTTMessage* message; MQTTString* topicName; } MessageData; typedef struct MQTTConnackData { unsigned char rc; unsigned char sessionPresent; } MQTTConnackData; typedef struct MQTTSubackData { enum QoS grantedQoS; } MQTTSubackData; typedef void (*messageHandler)(MessageData*); typedef struct MQTTClient { unsigned int next_packetid, command_timeout_ms; size_t buf_size, readbuf_size; unsigned char *buf, *readbuf; unsigned int keepAliveInterval; char ping_outstanding; int isconnected; int cleansession; struct MessageHandlers { const char* topicFilter; void (*fp) (MessageData*); } messageHandlers[MAX_MESSAGE_HANDLERS]; /* Message handlers are indexed by subscription topic */ void (*defaultMessageHandler) (MessageData*); Network* ipstack; Timer last_sent, last_received; #if defined(MQTT_TASK) Mutex mutex; Thread thread; #endif } MQTTClient; #define DefaultClient {0, 0, 0, 0, NULL, NULL, 0, 0, 0} /** * Create an MQTT client object * @param client * @param network * @param command_timeout_ms * @param */ DLLExport int MQTTClientInit(MQTTClient* client, Network* network, unsigned int command_timeout_ms, unsigned char* sendbuf, size_t sendbuf_size, unsigned char* readbuf, size_t readbuf_size); DLLExport void MQTTClientDeInit(MQTTClient* c); /** MQTT Connect - send an MQTT connect packet down the network and wait for a Connack * The nework object must be connected to the network endpoint before calling this * @param options - connect options * @return success code */ DLLExport int MQTTConnectWithResults(MQTTClient* client, MQTTPacket_connectData* options, MQTTConnackData* data); /** MQTT Connect - send an MQTT connect packet down the network and wait for a Connack * The nework object must be connected to the network endpoint before calling this * @param options - connect options * @return success code */ DLLExport int MQTTConnect(MQTTClient* client, MQTTPacket_connectData* options); /** MQTT Publish - send an MQTT publish packet and wait for all acks to complete for all QoSs * @param client - the client object to use * @param topic - the topic to publish to * @param message - the message to send * @return success code */ DLLExport int MQTTPublish(MQTTClient* client, const char*, MQTTMessage*); /** MQTT SetMessageHandler - set or remove a per topic message handler * @param client - the client object to use * @param topicFilter - the topic filter set the message handler for * @param messageHandler - pointer to the message handler function or NULL to remove * @return success code */ DLLExport int MQTTSetMessageHandler(MQTTClient* c, const char* topicFilter, messageHandler messageHandler); /** MQTT Subscribe - send an MQTT subscribe packet and wait for suback before returning. * @param client - the client object to use * @param topicFilter - the topic filter to subscribe to * @param message - the message to send * @return success code */ DLLExport int MQTTSubscribe(MQTTClient* client, const char* topicFilter, enum QoS, messageHandler); /** MQTT Subscribe - send an MQTT subscribe packet and wait for suback before returning. * @param client - the client object to use * @param topicFilter - the topic filter to subscribe to * @param message - the message to send * @param data - suback granted QoS returned * @return success code */ DLLExport int MQTTSubscribeWithResults(MQTTClient* client, const char* topicFilter, enum QoS, messageHandler, MQTTSubackData* data); /** MQTT Subscribe - send an MQTT unsubscribe packet and wait for unsuback before returning. * @param client - the client object to use * @param topicFilter - the topic filter to unsubscribe from * @return success code */ DLLExport int MQTTUnsubscribe(MQTTClient* client, const char* topicFilter); /** MQTT Disconnect - send an MQTT disconnect packet and close the connection * @param client - the client object to use * @return success code */ DLLExport int MQTTDisconnect(MQTTClient* client); /** MQTT Yield - MQTT background * @param client - the client object to use * @param time - the time, in milliseconds, to yield for * @return success code */ DLLExport int MQTTYield(MQTTClient* client, int time); /** MQTT isConnected * @param client - the client object to use * @return truth value indicating whether the client is connected to the server */ static inline DLLExport int MQTTIsConnected(MQTTClient* client) { return client->isconnected; } #if defined(MQTT_TASK) /** MQTT start background thread for a client. After this, MQTTYield should not be called. * @param client - the client object to use * @return success code */ DLLExport int MQTTStartTask(MQTTClient* client); #endif #if defined(__cplusplus) } #endif #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/src/cc3200/MQTTCC3200.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Allan Stockdill-Mander - initial API and implementation and/or initial documentation *******************************************************************************/ #include "MQTTCC3200.h" unsigned long MilliTimer; void SysTickIntHandler(void) { MilliTimer++; } char expired(Timer *timer) { long left = timer->end_time - MilliTimer; return (left < 0); } void countdown_ms(Timer *timer, unsigned int timeout) { timer->end_time = MilliTimer + timeout; } void countdown(Timer *timer, unsigned int timeout) { timer->end_time = MilliTimer + (timeout * 1000); } int left_ms(Timer *timer) { long left = timer->end_time - MilliTimer; return (left < 0) ? 0 : left; } void InitTimer(Timer *timer) { timer->end_time = 0; } int cc3200_read(Network *n, unsigned char *buffer, int len, int timeout_ms) { SlTimeval_t timeVal; SlFdSet_t fdset; int rc = 0; int recvLen = 0; SL_FD_ZERO(&fdset); SL_FD_SET(n->my_socket, &fdset); timeVal.tv_sec = 0; timeVal.tv_usec = timeout_ms * 1000; if (sl_Select(n->my_socket + 1, &fdset, NULL, NULL, &timeVal) == 1) { do { rc = sl_Recv(n->my_socket, buffer + recvLen, len - recvLen, 0); recvLen += rc; } while(recvLen < len); } return recvLen; } int cc3200_write(Network *n, unsigned char *buffer, int len, int timeout_ms) { SlTimeval_t timeVal; SlFdSet_t fdset; int rc = 0; int readySock; SL_FD_ZERO(&fdset); SL_FD_SET(n->my_socket, &fdset); timeVal.tv_sec = 0; timeVal.tv_usec = timeout_ms * 1000; do { readySock = sl_Select(n->my_socket + 1, NULL, &fdset, NULL, &timeVal); } while(readySock != 1); rc = sl_Send(n->my_socket, buffer, len, 0); return rc; } void cc3200_disconnect(Network *n) { sl_Close(n->my_socket); } void NewNetwork(Network *n) { n->my_socket = 0; n->mqttread = cc3200_read; n->mqttwrite = cc3200_write; n->disconnect = cc3200_disconnect; } int TLSConnectNetwork(Network *n, char *addr, int port, SlSockSecureFiles_t *certificates, unsigned char sec_method, unsigned int cipher, char server_verify) { SlSockAddrIn_t sAddr; int addrSize; int retVal; unsigned long ipAddress; retVal = sl_NetAppDnsGetHostByName(addr, strlen(addr), &ipAddress, AF_INET); if (retVal < 0) { return -1; } sAddr.sin_family = AF_INET; sAddr.sin_port = sl_Htons((unsigned short)port); sAddr.sin_addr.s_addr = sl_Htonl(ipAddress); addrSize = sizeof(SlSockAddrIn_t); n->my_socket = sl_Socket(SL_AF_INET, SL_SOCK_STREAM, SL_SEC_SOCKET); if (n->my_socket < 0) { return -1; } SlSockSecureMethod method; method.secureMethod = sec_method; retVal = sl_SetSockOpt(n->my_socket, SL_SOL_SOCKET, SL_SO_SECMETHOD, &method, sizeof(method)); if (retVal < 0) { return retVal; } SlSockSecureMask mask; mask.secureMask = cipher; retVal = sl_SetSockOpt(n->my_socket, SL_SOL_SOCKET, SL_SO_SECURE_MASK, &mask, sizeof(mask)); if (retVal < 0) { return retVal; } if (certificates != NULL) { retVal = sl_SetSockOpt(n->my_socket, SL_SOL_SOCKET, SL_SO_SECURE_FILES, certificates->secureFiles, sizeof(SlSockSecureFiles_t)); if(retVal < 0) { return retVal; } } retVal = sl_Connect(n->my_socket, ( SlSockAddr_t *)&sAddr, addrSize); if( retVal < 0 ) { if (server_verify || retVal != -453) { sl_Close(n->my_socket); return retVal; } } SysTickIntRegister(SysTickIntHandler); SysTickPeriodSet(80000); SysTickEnable(); return retVal; } int ConnectNetwork(Network *n, char *addr, int port) { SlSockAddrIn_t sAddr; int addrSize; int retVal; unsigned long ipAddress; sl_NetAppDnsGetHostByName(addr, strlen(addr), &ipAddress, AF_INET); sAddr.sin_family = AF_INET; sAddr.sin_port = sl_Htons((unsigned short)port); sAddr.sin_addr.s_addr = sl_Htonl(ipAddress); addrSize = sizeof(SlSockAddrIn_t); n->my_socket = sl_Socket(SL_AF_INET, SL_SOCK_STREAM, 0); if( n->my_socket < 0 ) { // error return -1; } retVal = sl_Connect(n->my_socket, ( SlSockAddr_t *)&sAddr, addrSize); if( retVal < 0 ) { // error sl_Close(n->my_socket); return retVal; } SysTickIntRegister(SysTickIntHandler); SysTickPeriodSet(80000); SysTickEnable(); return retVal; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/src/cc3200/MQTTCC3200.h ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Allan Stockdill-Mander - initial API and implementation and/or initial documentation *******************************************************************************/ #ifndef __MQTT_CC3200_ #define __MQTT_CC3200_ #include "simplelink.h" #include "netapp.h" #include "socket.h" #include "hw_types.h" #include "systick.h" typedef struct Timer Timer; struct Timer { unsigned long systick_period; unsigned long end_time; }; typedef struct Network Network; struct Network { int my_socket; int (*mqttread) (Network*, unsigned char*, int, int); int (*mqttwrite) (Network*, unsigned char*, int, int); void (*disconnect) (Network*); }; char expired(Timer*); void countdown_ms(Timer*, unsigned int); void countdown(Timer*, unsigned int); int left_ms(Timer*); void InitTimer(Timer*); int cc3200_read(Network*, unsigned char*, int, int); int cc3200_write(Network*, unsigned char*, int, int); void cc3200_disconnect(Network*); void NewNetwork(Network*); int ConnectNetwork(Network*, char*, int); int TLSConnectNetwork(Network*, char*, int, SlSockSecureFiles_t*, unsigned char, unsigned int, char); #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/src/linux/MQTTLinux.c ================================================ /******************************************************************************* * Copyright (c) 2014, 2017 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Allan Stockdill-Mander - initial API and implementation and/or initial documentation * Ian Craggs - return codes from linux_read *******************************************************************************/ #include "MQTTLinux.h" void TimerInit(Timer *timer) { timer->end_time = (struct timeval) { 0, 0 }; } char TimerIsExpired(Timer *timer) { struct timeval now, res; gettimeofday(&now, NULL); timersub(&timer->end_time, &now, &res); return res.tv_sec < 0 || (res.tv_sec == 0 && res.tv_usec <= 0); } void TimerCountdownMS(Timer *timer, unsigned int timeout) { struct timeval now; gettimeofday(&now, NULL); struct timeval interval = {timeout / 1000, (timeout % 1000) * 1000}; timeradd(&now, &interval, &timer->end_time); } void TimerCountdown(Timer *timer, unsigned int timeout) { struct timeval now; gettimeofday(&now, NULL); struct timeval interval = {timeout, 0}; timeradd(&now, &interval, &timer->end_time); } int TimerLeftMS(Timer *timer) { struct timeval now, res; gettimeofday(&now, NULL); timersub(&timer->end_time, &now, &res); //printf("left %d ms\n", (res.tv_sec < 0) ? 0 : res.tv_sec * 1000 + res.tv_usec / 1000); return (res.tv_sec < 0) ? 0 : res.tv_sec * 1000 + res.tv_usec / 1000; } int linux_read(Network *n, unsigned char *buffer, int len, int timeout_ms) { struct timeval interval = {timeout_ms / 1000, (timeout_ms % 1000) * 1000}; if (interval.tv_sec < 0 || (interval.tv_sec == 0 && interval.tv_usec <= 0)) { interval.tv_sec = 0; interval.tv_usec = 100; } setsockopt(n->my_socket, SOL_SOCKET, SO_RCVTIMEO, (char *)&interval, sizeof(struct timeval)); int bytes = 0; while (bytes < len) { int rc = recv(n->my_socket, &buffer[bytes], (size_t)(len - bytes), 0); if (rc == -1) { if (errno != EAGAIN && errno != EWOULDBLOCK) bytes = -1; break; } else if (rc == 0) { bytes = 0; break; } else bytes += rc; } return bytes; } int linux_write(Network *n, unsigned char *buffer, int len, int timeout_ms) { struct timeval tv; tv.tv_sec = 0; /* 30 Secs Timeout */ tv.tv_usec = timeout_ms * 1000; // Not init'ing this can cause strange errors setsockopt(n->my_socket, SOL_SOCKET, SO_SNDTIMEO, (char *)&tv, sizeof(struct timeval)); int rc = write(n->my_socket, buffer, len); return rc; } void NetworkInit(Network *n) { n->my_socket = 0; n->mqttread = linux_read; n->mqttwrite = linux_write; } int NetworkConnect(Network *n, char *addr, int port) { int type = SOCK_STREAM; struct sockaddr_in address; int rc = -1; sa_family_t family = AF_INET; struct addrinfo *result = NULL; struct addrinfo hints = {0, AF_UNSPEC, SOCK_STREAM, IPPROTO_TCP, 0, NULL, NULL, NULL}; if ((rc = getaddrinfo(addr, NULL, &hints, &result)) == 0) { struct addrinfo *res = result; /* prefer ip4 addresses */ while (res) { if (res->ai_family == AF_INET) { result = res; break; } res = res->ai_next; } if (result->ai_family == AF_INET) { address.sin_port = htons(port); address.sin_family = family = AF_INET; address.sin_addr = ((struct sockaddr_in *)(result->ai_addr))->sin_addr; } else rc = -1; freeaddrinfo(result); } if (rc == 0) { n->my_socket = socket(family, type, 0); if (n->my_socket != -1) rc = connect(n->my_socket, (struct sockaddr *)&address, sizeof(address)); } return rc; } void NetworkDisconnect(Network *n) { close(n->my_socket); } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/src/linux/MQTTLinux.h ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Allan Stockdill-Mander - initial API and implementation and/or initial documentation *******************************************************************************/ #if !defined(__MQTT_LINUX_) #define __MQTT_LINUX_ #if defined(WIN32_DLL) || defined(WIN64_DLL) #define DLLImport __declspec(dllimport) #define DLLExport __declspec(dllexport) #elif defined(LINUX_SO) #define DLLImport extern #define DLLExport __attribute__ ((visibility ("default"))) #else #define DLLImport #define DLLExport #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include typedef struct Timer { struct timeval end_time; } Timer; void TimerInit(Timer*); char TimerIsExpired(Timer*); void TimerCountdownMS(Timer*, unsigned int); void TimerCountdown(Timer*, unsigned int); int TimerLeftMS(Timer*); typedef struct Network { int my_socket; int (*mqttread) (struct Network*, unsigned char*, int, int); int (*mqttwrite) (struct Network*, unsigned char*, int, int); } Network; int linux_read(Network*, unsigned char*, int, int); int linux_write(Network*, unsigned char*, int, int); DLLExport void NetworkInit(Network*); DLLExport int NetworkConnect(Network*, char*, int); DLLExport void NetworkDisconnect(Network*); #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/src/liteOS/MQTTliteos.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "MQTTliteos.h" #include "mbedtls/net_sockets.h" #include "mbedtls/ssl.h" #include "mbedtls/entropy.h" #include "mbedtls/ctr_drbg.h" #include "mbedtls/platform.h" #include "dtls_interface.h" #if defined(WITH_LINUX) #include #include #include #include #include #include #include #include #include #elif defined(WITH_LWIP) //#include "lwip/sockets.h" #include "lwip/netdb.h" #include "lwip/errno.h" #endif #include "osdepends/atiny_osdep.h" #define get_time_ms atiny_gettime_ms void TimerInit(Timer *timer) { timer->end_time = get_time_ms(); } char TimerIsExpired(Timer *timer) { unsigned long long now = get_time_ms(); return now >= timer->end_time; } void TimerCountdownMS(Timer *timer, unsigned int timeout) { unsigned long long now = get_time_ms(); timer->end_time = now + timeout; } void TimerCountdown(Timer *timer, unsigned int timeout) { unsigned long long now = get_time_ms(); timer->end_time = now + timeout * 1000; } int TimerLeftMS(Timer *timer) { UINT64 now = get_time_ms(); return timer->end_time <= now ? 0 : timer->end_time - now; } int MutexInit(Mutex* mutex) { int ret = atiny_task_mutex_create(mutex); if (ret != LOS_OK) { ATINY_LOG(LOG_ERR, "create mutex fail, ret %d.", ret); } return ret; } int MutexLock(Mutex* mutex) { int ret = atiny_task_mutex_lock(mutex); if (ret != LOS_OK) { ATINY_LOG(LOG_ERR, "lock mutex fail,mutex %d,ret %d.", mutex->mutex, ret); } return ret; } int MutexUnlock(Mutex* mutex) { int ret = atiny_task_mutex_unlock(mutex); if (ret != LOS_OK) { ATINY_LOG(LOG_ERR, "unlock mutex fail,mutex %d,ret %d.", mutex->mutex, ret); } return ret; } void MutexDestory(Mutex* mutex) { int ret = atiny_task_mutex_delete(mutex); if (ret != LOS_OK) { ATINY_LOG(LOG_ERR, "delete mutex fail,mutex %d,ret %d.", mutex->mutex, ret); } } int ThreadStart(Thread *thread, void (*fn)(void *), void *arg) { (void)thread; (void)fn; (void)arg; return -1; } static int los_mqtt_read(void *ctx, unsigned char *buffer, int len, int timeout_ms) { int ret = atiny_net_recv_timeout(ctx, buffer, len, timeout_ms); /* 0 is timeout for mqtt for normal select */ if (ret == ATINY_NET_TIMEOUT) { ret = 0; } return ret; } static int los_mqtt_tls_read(mbedtls_ssl_context *ssl, unsigned char *buffer, int len, int timeout_ms) { int ret; if(NULL == ssl || NULL == buffer) { ATINY_LOG(LOG_FATAL, "invalid params."); return -1; } mbedtls_ssl_conf_read_timeout(ssl->conf, timeout_ms); ret = mbedtls_ssl_read(ssl, buffer, len); if(ret == MBEDTLS_ERR_SSL_WANT_READ || ret == MBEDTLS_ERR_SSL_WANT_WRITE || ret == MBEDTLS_ERR_SSL_TIMEOUT) ret = 0; return ret; } static int los_read(Network *n, unsigned char *buffer, int len, int timeout_ms) { int ret = -1; mqtt_security_info_s *info; if(NULL == n || NULL == buffer) { ATINY_LOG(LOG_FATAL, "invalid params."); return -1; } info = n->get_security_info(); switch(info->security_type) { case MQTT_SECURITY_TYPE_NONE : ret = los_mqtt_read(n->ctx, buffer, len, timeout_ms); break; case MQTT_SECURITY_TYPE_PSK: case MQTT_SECURITY_TYPE_CA: ret = los_mqtt_tls_read(n->ctx, buffer, len, timeout_ms); break; default : ATINY_LOG(LOG_WARNING, "unknow proto : %d", info->security_type); break; } return ret; } static int los_write(Network *n, unsigned char *buffer, int len, int timeout_ms) { int ret = -1; mqtt_security_info_s *info; if(NULL == n || NULL == buffer) { ATINY_LOG(LOG_FATAL, "invalid params."); return -1; } info = n->get_security_info(); switch(info->security_type) { case MQTT_SECURITY_TYPE_NONE : ret = atiny_net_send_timeout(n->ctx, buffer, len, timeout_ms); break; case MQTT_SECURITY_TYPE_PSK: case MQTT_SECURITY_TYPE_CA: ret = dtls_write(n->ctx, buffer, len); break; default : ATINY_LOG(LOG_WARNING, "unknow proto : %d", info->security_type); break; } return ret; } void NetworkInit(Network *n, mqtt_security_info_s *(*get_security_info)(void)) { if((NULL == n) || (NULL == get_security_info)) { ATINY_LOG(LOG_FATAL, "invalid params."); return; } memset(n, 0x0, sizeof(Network)); n->mqttread = los_read; n->mqttwrite = los_write; n->get_security_info = get_security_info; return; } static int los_mqtt_connect(Network *n, char *addr, int port) { char port_str[16]; (void)snprintf(port_str, sizeof(port_str), "%u", port); port_str[sizeof(port_str) - 1] = '\0'; n->ctx = atiny_net_connect(addr, port_str, ATINY_PROTO_TCP); if (n->ctx == NULL) { ATINY_LOG(LOG_FATAL, "atiny_net_connect fail"); return ATINY_NET_ERR; } return ATINY_OK; } #define PORT_BUF_LEN 16 static int los_mqtt_tls_connect(Network *n, char *addr, int port) { int ret; mbedtls_ssl_context *ssl; dtls_shakehand_info_s shakehand_info; dtls_establish_info_s establish_info; mqtt_security_info_s *security_info; char port_buf[PORT_BUF_LEN]; security_info = n->get_security_info(); if (security_info->security_type == MQTT_SECURITY_TYPE_PSK) { establish_info.psk_or_cert = VERIFY_WITH_PSK; establish_info.v.p.psk = (unsigned char *)security_info->u.psk.psk; establish_info.v.p.psk_len = security_info->u.psk.psk_len; establish_info.v.p.psk_identity = (unsigned char *)security_info->u.psk.psk_id; } else { establish_info.psk_or_cert = VERIFY_WITH_CERT; establish_info.v.c.ca_cert = (const unsigned char *)security_info->u.ca.ca_crt; establish_info.v.c.cert_len = security_info->u.ca.ca_len; } establish_info.udp_or_tcp = MBEDTLS_NET_PROTO_TCP; ssl = (void *)dtls_ssl_new(&establish_info, MBEDTLS_SSL_IS_CLIENT); if (NULL == ssl) { ATINY_LOG(LOG_ERR, "create ssl context failed"); goto exit; } memset(&shakehand_info, 0, sizeof(dtls_shakehand_info_s)); if (security_info->security_type == MQTT_SECURITY_TYPE_PSK) { shakehand_info.psk_or_cert = VERIFY_WITH_PSK; } else { shakehand_info.psk_or_cert = VERIFY_WITH_CERT; } shakehand_info.client_or_server = MBEDTLS_SSL_IS_CLIENT; shakehand_info.udp_or_tcp = MBEDTLS_NET_PROTO_TCP; shakehand_info.u.c.host = addr; atiny_snprintf(port_buf, PORT_BUF_LEN, "%d", port); shakehand_info.u.c.port = port_buf; ret = dtls_shakehand(ssl, &shakehand_info); if (ret != 0) { ATINY_LOG(LOG_ERR, "ssl shake hand failed"); goto exit; } n->ctx = ssl; return 0; exit: dtls_ssl_destroy(ssl); return -1; } int NetworkConnect(Network *n, char *addr, int port) { int ret = -1; mqtt_security_info_s *info; if(NULL == n || NULL == addr) { ATINY_LOG(LOG_FATAL, "invalid params.\n"); return -1; } info = n->get_security_info(); switch(info->security_type) { case MQTT_SECURITY_TYPE_NONE : ret = los_mqtt_connect(n, addr, port); break; case MQTT_SECURITY_TYPE_PSK: case MQTT_SECURITY_TYPE_CA: ret = los_mqtt_tls_connect(n, addr, port); break; default : ATINY_LOG(LOG_WARNING, "unknow proto : %d\n", info->security_type); break; } return ret; } static void los_mqtt_disconnect(void *ctx) { if(NULL == ctx) { ATINY_LOG(LOG_FATAL, "invalid params.\n"); return; } atiny_net_close(ctx); return; } void NetworkDisconnect(Network *n) { mqtt_security_info_s *info; if(NULL == n) { ATINY_LOG(LOG_FATAL, "invalid params.\n"); return; } info = n->get_security_info(); switch(info->security_type) { case MQTT_SECURITY_TYPE_NONE : los_mqtt_disconnect(n->ctx); break; case MQTT_SECURITY_TYPE_PSK: case MQTT_SECURITY_TYPE_CA: dtls_ssl_destroy(n->ctx); break; default : ATINY_LOG(LOG_WARNING, "unknow proto : %d\n", info->security_type); break; } n->ctx = NULL; return; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/src/liteOS/MQTTliteos.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef MQTT_LITE_OS_H #define MQTT_LITE_OS_H #include #include #include #include #include #include #include "sal/atiny_socket.h" #include "log/atiny_log.h" #include "atiny_mqtt/mqtt_client.h" #define MQTT_TASK 1 typedef struct Timer { unsigned long long end_time; } Timer; void TimerInit(Timer*); char TimerIsExpired(Timer*); void TimerCountdownMS(Timer*, unsigned int); void TimerCountdown(Timer*, unsigned int); int TimerLeftMS(Timer*); typedef struct atiny_task_mutex_tag_s Mutex; int MutexInit(Mutex* mutex); int MutexLock(Mutex* mutex); int MutexUnlock(Mutex* mutex); void MutexDestory(Mutex* mutex); typedef struct { void * no_used; } Thread; int ThreadStart(Thread *thread, void (*fn)(void *), void *arg); typedef struct mqtt_context { int fd; }mqtt_context_t; typedef struct Network { void *ctx; int (*mqttread) (struct Network*, unsigned char*, int, int); int (*mqttwrite) (struct Network*, unsigned char*, int, int); mqtt_security_info_s *(*get_security_info)(void); } Network; void NetworkInit(Network* n, mqtt_security_info_s *(*get_security_info)(void)); int NetworkConnect(Network*, char*, int); void NetworkDisconnect(Network*); #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/test/CMakeLists.txt ================================================ PROJECT(mqtt-tests) SET(MQTT_TEST_BROKER_HOST "localhost" CACHE STRING "Hostname of a test MQTT broker to use") SET(MQTT_TEST_PROXY_PORT "1884" CACHE STRING "Port of the test proxy to use") SET(MQTT_SSL_HOSTNAME "localhost" CACHE STRING "Hostname of a test SSL MQTT broker to use") SET(CERTDIR $ENV{TRAVIS_BUILD_DIR}/test/ssl) ADD_EXECUTABLE( testc1 test1.c ) target_link_libraries(testc1 paho-embed-mqtt3cc paho-embed-mqtt3c) target_include_directories(testc1 PRIVATE "../src" "../src/linux") target_compile_definitions(testc1 PRIVATE MQTTCLIENT_PLATFORM_HEADER=MQTTLinux.h) ADD_TEST( NAME testc1 COMMAND "testc1" "--host" ${MQTT_TEST_BROKER_HOST} ) ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTClient-C/test/test1.c ================================================ /******************************************************************************* * Copyright (c) 2009, 2017 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial implementation for embedded C client *******************************************************************************/ /** * @file * Tests for the Paho embedded C "high" level client */ #include "MQTTClient.h" #include #include #if !defined(_WINDOWS) #include #include #include #include #else #include #define setenv(a, b, c) _putenv_s(a, b) #endif #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) void usage(void) { printf("help!!\n"); exit(EXIT_FAILURE); } struct Options { char *host; /**< connection to system under test. */ int port; char *proxy_host; int proxy_port; int verbose; int test_no; int MQTTVersion; int iterations; } options = { "localhost", 1883, "localhost", 1885, 0, //verbose 0, //test_no 4, 1, }; void getopts(int argc, char **argv) { int count = 1; while (count < argc) { if (strcmp(argv[count], "--test_no") == 0) { if (++count < argc) options.test_no = atoi(argv[count]); else usage(); } else if (strcmp(argv[count], "--host") == 0) { if (++count < argc) { options.host = argv[count]; printf("\nSetting host to %s\n", options.host); } else usage(); } else if (strcmp(argv[count], "--port") == 0) { if (++count < argc) { options.port = atoi(argv[count]); printf("\nSetting port to %d\n", options.port); } else usage(); } else if (strcmp(argv[count], "--proxy_host") == 0) { if (++count < argc) { options.proxy_host = argv[count]; printf("\nSetting proxy_host to %s\n", options.proxy_host); } else usage(); } else if (strcmp(argv[count], "--proxy_port") == 0) { if (++count < argc) { options.proxy_port = atoi(argv[count]); printf("\nSetting proxy_port to %d\n", options.proxy_port); } else usage(); } else if (strcmp(argv[count], "--MQTTversion") == 0) { if (++count < argc) { options.MQTTVersion = atoi(argv[count]); printf("setting MQTT version to %d\n", options.MQTTVersion); } else usage(); } else if (strcmp(argv[count], "--iterations") == 0) { if (++count < argc) options.iterations = atoi(argv[count]); else usage(); } else if (strcmp(argv[count], "--verbose") == 0) { options.verbose = 1; printf("\nSetting verbose on\n"); } count++; } } #define LOGA_DEBUG 0 #define LOGA_INFO 1 #include #include #include void MyLog(int LOGA_level, char *format, ...) { static char msg_buf[256]; va_list args; struct timeb ts; struct tm *timeinfo; if (LOGA_level == LOGA_DEBUG && options.verbose == 0) return; ftime(&ts); timeinfo = localtime(&ts.time); strftime(msg_buf, 80, "%Y%m%d %H%M%S", timeinfo); sprintf(&msg_buf[strlen(msg_buf)], ".%.3hu ", ts.millitm); va_start(args, format); vsnprintf(&msg_buf[strlen(msg_buf)], sizeof(msg_buf) - strlen(msg_buf), format, args); va_end(args); printf("%s\n", msg_buf); fflush(stdout); } #if defined(WIN32) || defined(_WINDOWS) #define mqsleep(A) Sleep(1000*A) #define START_TIME_TYPE DWORD static DWORD start_time = 0; START_TIME_TYPE start_clock(void) { return GetTickCount(); } #elif defined(AIX) #define mqsleep sleep #define START_TIME_TYPE struct timespec START_TIME_TYPE start_clock(void) { static struct timespec start; clock_gettime(CLOCK_REALTIME, &start); return start; } #else #define mqsleep sleep #define START_TIME_TYPE struct timeval /* TODO - unused - remove? static struct timeval start_time; */ START_TIME_TYPE start_clock(void) { struct timeval start_time; gettimeofday(&start_time, NULL); return start_time; } #endif #if defined(WIN32) long elapsed(START_TIME_TYPE start_time) { return GetTickCount() - start_time; } #elif defined(AIX) #define assert(a) long elapsed(struct timespec start) { struct timespec now, res; clock_gettime(CLOCK_REALTIME, &now); ntimersub(now, start, res); return (res.tv_sec) * 1000L + (res.tv_nsec) / 1000000L; } #else long elapsed(START_TIME_TYPE start_time) { struct timeval now, res; gettimeofday(&now, NULL); timersub(&now, &start_time, &res); return (res.tv_sec) * 1000 + (res.tv_usec) / 1000; } #endif #define assert(a, b, c, d) myassert(__FILE__, __LINE__, a, b, c, d) #define assert1(a, b, c, d, e) myassert(__FILE__, __LINE__, a, b, c, d, e) int tests = 0; int failures = 0; FILE *xml; START_TIME_TYPE global_start_time; char output[3000]; char *cur_output = output; void write_test_result(void) { long duration = elapsed(global_start_time); fprintf(xml, " time=\"%ld.%.3ld\" >\n", duration / 1000, duration % 1000); if (cur_output != output) { fprintf(xml, "%s", output); cur_output = output; } fprintf(xml, "\n"); } void myassert(char *filename, int lineno, char *description, int value, char *format, ...) { ++tests; if (!value) { va_list args; ++failures; MyLog(LOGA_INFO, "Assertion failed, file %s, line %d, description: %s\n", filename, lineno, description); va_start(args, format); vprintf(format, args); va_end(args); cur_output += sprintf(cur_output, "file %s, line %d \n", description, filename, lineno); } else MyLog(LOGA_DEBUG, "Assertion succeeded, file %s, line %d, description: %s", filename, lineno, description); } static volatile MessageData *test1_message_data = NULL; static MQTTMessage pubmsg; void messageArrived(MessageData *md) { test1_message_data = md; MQTTMessage *m = md->message; assert("Good message lengths", pubmsg.payloadlen == m->payloadlen, "payloadlen was %d", m->payloadlen); if (pubmsg.payloadlen == m->payloadlen) assert("Good message contents", memcmp(m->payload, pubmsg.payload, m->payloadlen) == 0, "payload was %s", m->payload); } /********************************************************************* Test1: single-threaded client *********************************************************************/ void test1_sendAndReceive(MQTTClient *c, int qos, char *test_topic) { char *topicName = NULL; int topicLen; int i = 0; int iterations = 50; int rc; int wait_seconds; MyLog(LOGA_DEBUG, "%d messages at QoS %d", iterations, qos); memset(&pubmsg, '\0', sizeof(pubmsg)); pubmsg.payload = "a much longer message that we can shorten to the extent that we need to payload up to 11"; pubmsg.payloadlen = 11; pubmsg.qos = qos; pubmsg.retained = 0; pubmsg.dup = 0; for (i = 0; i < iterations; ++i) { test1_message_data = NULL; rc = MQTTPublish(c, test_topic, &pubmsg); assert("Good rc from publish", rc == MQTT_SUCCESS, "rc was %d", rc); /* wait for the message to be received */ wait_seconds = 10; while ((test1_message_data == NULL) && (wait_seconds-- > 0)) { MQTTYield(c, 100); } assert("Message Arrived", wait_seconds > 0, "Time out waiting for message %d\n", i); if (!test1_message_data) printf("No message received within timeout period\n"); } /* wait to receive any outstanding messages */ wait_seconds = 2; while (wait_seconds-- > 0) { MQTTYield(c, 1000); } } int test1(struct Options options) { int subsqos = 2; Network n; MQTTClient c; int rc = 0; char *test_topic = "C client test1"; MQTTPacket_willOptions wopts; unsigned char buf[100]; unsigned char readbuf[100]; printf("test1\n"); fprintf(xml, "message; assert("Good message lengths", pubmsg.payloadlen == m->payloadlen, "payloadlen was %d", m->payloadlen); if (pubmsg.payloadlen == m->payloadlen) assert("Good message contents", memcmp(m->payload, pubmsg.payload, m->payloadlen) == 0, "payload was %s", m->payload); } int check_subs_exist(MQTTClient *c, const char *test_topic, int which) { int rc = FAILURE; int wait_seconds = 0; memset(&pubmsg, '\0', sizeof(pubmsg)); pubmsg.payload = (void *)"a much longer message that we can shorten to the extent that we need to payload up to 11"; pubmsg.payloadlen = 11; pubmsg.qos = QOS2; pubmsg.retained = 0; pubmsg.dup = 0; test1_message_data = test2_message_data = NULL; rc = MQTTPublish(c, test_topic, &pubmsg); assert("Good rc from publish", rc == MQTT_SUCCESS, "rc was %d", rc); /* wait for the message to be received */ wait_seconds = 10; while (wait_seconds-- > 0) { MQTTYield(c, 100); } rc = (((which == 1 || which == 3) && test1_message_data) || (which == 2 && test1_message_data == NULL)) ? MQTT_SUCCESS : FAILURE; assert("test1 subscription", rc == MQTT_SUCCESS, "test1_message_data %p\n", test1_message_data); rc = (((which == 2 || which == 3) && test2_message_data) || (which == 1 && test2_message_data == NULL)) ? MQTT_SUCCESS : FAILURE; assert("test2 subscription", rc == MQTT_SUCCESS, "test2_message_data %p\n", test2_message_data); return rc; } int test3(struct Options options) { enum QoS subsqos = QOS2; Network n; MQTTClient c; int rc; const char *test_topic = "C client test3"; int wait_seconds = 0; unsigned char buf[100]; unsigned char readbuf[100]; MQTTConnackData connack; MQTTSubackData suback; fprintf(xml, " 0)) { MQTTYield(&c, 1000); } assert("Disconnected", !MQTTIsConnected(&c), "isConnected was %d", MQTTIsConnected(&c)); NetworkDisconnect(&n); /* reconnect with cleansession false */ data.cleansession = 0; rc = NetworkConnect(&n, options.host, options.port); assert("TCP connect successful", rc == MQTT_SUCCESS, "rc was %d", rc); rc = MQTTConnectWithResults(&c, &data, &connack); assert("Connect successful", rc == MQTT_SUCCESS, "rc was %d", rc); assert("Good rc in connack", connack.rc == 0, "rc was %d", connack.rc); assert("Session present is 1", connack.sessionPresent == 1, "sessionPresent was %d", connack.sessionPresent); check_subs_exist(&c, test_topic, 1); rc = MQTTSubscribeWithResults(&c, test_topic, subsqos, messageArrived2, &suback); assert("Good rc from subscribe", rc == MQTT_SUCCESS, "rc was %d", rc); assert("Granted QoS rc from subscribe", suback.grantedQoS == QOS2, "rc was %d", suback.grantedQoS); check_subs_exist(&c, test_topic, 2); rc = MQTTDisconnect(&c); assert("Disconnect successful", rc == MQTT_SUCCESS, "rc was %d", rc); NetworkDisconnect(&n); /* reconnect with cleansession true to clean up both server and client state */ data.cleansession = 1; rc = NetworkConnect(&n, options.host, options.port); assert("TCP connect successful", rc == MQTT_SUCCESS, "rc was %d", rc); rc = MQTTConnectWithResults(&c, &data, &connack); assert("Connect successful", rc == MQTT_SUCCESS, "rc was %d", rc); assert("Good rc in connack", connack.rc == 0, "rc was %d", connack.rc); assert("Session present is 0", connack.sessionPresent == 0, "sessionPresent was %d", connack.sessionPresent); rc = MQTTSubscribeWithResults(&c, test_topic, subsqos, messageArrived2, &suback); assert("Good rc from subscribe", rc == MQTT_SUCCESS, "rc was %d", rc); assert("Granted QoS rc from subscribe", suback.grantedQoS == QOS2, "rc was %d", suback.grantedQoS); check_subs_exist(&c, test_topic, 2); rc = MQTTDisconnect(&c); assert("Disconnect successful", rc == MQTT_SUCCESS, "rc was %d", rc); NetworkDisconnect(&n); exit: MyLog(LOGA_INFO, "TEST2: test %s. %d tests run, %d failures.", (failures == 0) ? "passed" : "failed", tests, failures); write_test_result(); return failures; } #if 0 /********************************************************************* Test 4: connectionLost and will message *********************************************************************/ MQTTClient test6_c1, test6_c2; volatile int test6_will_message_arrived = 0; volatile int test6_connection_lost_called = 0; void test6_connectionLost(void *context, char *cause) { MQTTClient c = (MQTTClient)context; printf("%s -> Callback: connection lost\n", (c == test6_c1) ? "Client-1" : "Client-2"); test6_connection_lost_called = 1; } void test6_deliveryComplete(void *context, MQTTClient_deliveryToken token) { printf("Client-2 -> Callback: publish complete for token %d\n", token); } char *test6_will_topic = "C Test 2: will topic"; char *test6_will_message = "will message from Client-1"; int test6_messageArrived(void *context, char *topicName, int topicLen, MQTTClient_message *m) { MQTTClient c = (MQTTClient)context; printf("%s -> Callback: message received on topic '%s' is '%.*s'.\n", (c == test6_c1) ? "Client-1" : "Client-2", topicName, m->payloadlen, (char *)(m->payload)); if (c == test6_c2 && strcmp(topicName, test6_will_topic) == 0 && memcmp(m->payload, test6_will_message, m->payloadlen) == 0) test6_will_message_arrived = 1; MQTTClient_free(topicName); MQTTClient_freeMessage(&m); return 1; } int test6(struct Options options) { char *testname = "test6"; MQTTClient_connectOptions opts = MQTTClient_connectOptions_initializer; MQTTClient_willOptions wopts = MQTTClient_willOptions_initializer; MQTTClient_connectOptions opts2 = MQTTClient_connectOptions_initializer; int rc, count; char *mqttsas_topic = "MQTTSAS topic"; failures = 0; MyLog(LOGA_INFO, "Starting test 6 - connectionLost and will messages"); fprintf(xml, "message = test6_will_message; opts.will->qos = 1; opts.will->retained = 0; opts.will->topicName = test6_will_topic; if (options.haconnections != NULL) { opts.serverURIs = options.haconnections; opts.serverURIcount = options.hacount; } /* Client-1 with Will options */ rc = MQTTClient_create(&test6_c1, options.proxy_connection, "Client_1", MQTTCLIENT_PERSISTENCE_DEFAULT, NULL); assert("good rc from create", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); if (rc != MQTTCLIENT_SUCCESS) goto exit; rc = MQTTClient_setCallbacks(test6_c1, (void *)test6_c1, test6_connectionLost, test6_messageArrived, test6_deliveryComplete); assert("good rc from setCallbacks", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); if (rc != MQTTCLIENT_SUCCESS) goto exit; /* Connect to the broker */ rc = MQTTClient_connect(test6_c1, &opts); assert("good rc from connect", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); if (rc != MQTTCLIENT_SUCCESS) goto exit; /* Client - 2 (multi-threaded) */ rc = MQTTClient_create(&test6_c2, options.connection, "Client_2", MQTTCLIENT_PERSISTENCE_DEFAULT, NULL); assert("good rc from create", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); /* Set the callback functions for the client */ rc = MQTTClient_setCallbacks(test6_c2, (void *)test6_c2, test6_connectionLost, test6_messageArrived, test6_deliveryComplete); assert("good rc from setCallbacks", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); /* Connect to the broker */ opts2.keepAliveInterval = 20; opts2.cleansession = 1; MyLog(LOGA_INFO, "Connecting Client_2 ..."); rc = MQTTClient_connect(test6_c2, &opts2); assert("Good rc from connect", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); rc = MQTTClient_subscribe(test6_c2, test6_will_topic, 2); assert("Good rc from subscribe", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); /* now send the command which will break the connection and cause the will message to be sent */ rc = MQTTClient_publish(test6_c1, mqttsas_topic, (int)strlen("TERMINATE"), "TERMINATE", 0, 0, NULL); assert("Good rc from publish", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); MyLog(LOGA_INFO, "Waiting to receive the will message"); count = 0; while (++count < 40) { #if defined(WIN32) Sleep(1000L); #else sleep(1); #endif if (test6_will_message_arrived == 1 && test6_connection_lost_called == 1) break; } assert("will message arrived", test6_will_message_arrived == 1, "will_message_arrived was %d\n", test6_will_message_arrived); assert("connection lost called", test6_connection_lost_called == 1, "connection_lost_called %d\n", test6_connection_lost_called); rc = MQTTClient_unsubscribe(test6_c2, test6_will_topic); assert("Good rc from unsubscribe", rc == MQTTCLIENT_SUCCESS, "rc was %d", rc); rc = MQTTClient_isConnected(test6_c2); assert("Client-2 still connected", rc == 1, "isconnected is %d", rc); rc = MQTTClient_isConnected(test6_c1); assert("Client-1 not connected", rc == 0, "isconnected is %d", rc); rc = MQTTClient_disconnect(test6_c2, 100L); assert("Good rc from disconnect", rc == MQTTCLIENT_SUCCESS, "rc was %d", rc); MQTTClient_destroy(&test6_c1); MQTTClient_destroy(&test6_c2); exit: MyLog(LOGA_INFO, "%s: test %s. %d tests run, %d failures.\n", (failures == 0) ? "passed" : "failed", testname, tests, failures); write_test_result(); return failures; } int test6a(struct Options options) { char *testname = "test6a"; MQTTClient_connectOptions opts = MQTTClient_connectOptions_initializer; MQTTClient_willOptions wopts = MQTTClient_willOptions_initializer; MQTTClient_connectOptions opts2 = MQTTClient_connectOptions_initializer; int rc, count; char *mqttsas_topic = "MQTTSAS topic"; failures = 0; MyLog(LOGA_INFO, "Starting test 6 - connectionLost and binary will messages"); fprintf(xml, "payload.data = test6_will_message; opts.will->payload.len = strlen(test6_will_message) + 1; opts.will->qos = 1; opts.will->retained = 0; opts.will->topicName = test6_will_topic; if (options.haconnections != NULL) { opts.serverURIs = options.haconnections; opts.serverURIcount = options.hacount; } /* Client-1 with Will options */ rc = MQTTClient_create(&test6_c1, options.proxy_connection, "Client_1", MQTTCLIENT_PERSISTENCE_DEFAULT, NULL); assert("good rc from create", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); if (rc != MQTTCLIENT_SUCCESS) goto exit; rc = MQTTClient_setCallbacks(test6_c1, (void *)test6_c1, test6_connectionLost, test6_messageArrived, test6_deliveryComplete); assert("good rc from setCallbacks", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); if (rc != MQTTCLIENT_SUCCESS) goto exit; /* Connect to the broker */ rc = MQTTClient_connect(test6_c1, &opts); assert("good rc from connect", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); if (rc != MQTTCLIENT_SUCCESS) goto exit; /* Client - 2 (multi-threaded) */ rc = MQTTClient_create(&test6_c2, options.connection, "Client_2", MQTTCLIENT_PERSISTENCE_DEFAULT, NULL); assert("good rc from create", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); /* Set the callback functions for the client */ rc = MQTTClient_setCallbacks(test6_c2, (void *)test6_c2, test6_connectionLost, test6_messageArrived, test6_deliveryComplete); assert("good rc from setCallbacks", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); /* Connect to the broker */ opts2.keepAliveInterval = 20; opts2.cleansession = 1; MyLog(LOGA_INFO, "Connecting Client_2 ..."); rc = MQTTClient_connect(test6_c2, &opts2); assert("Good rc from connect", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); rc = MQTTClient_subscribe(test6_c2, test6_will_topic, 2); assert("Good rc from subscribe", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); /* now send the command which will break the connection and cause the will message to be sent */ rc = MQTTClient_publish(test6_c1, mqttsas_topic, (int)strlen("TERMINATE"), "TERMINATE", 0, 0, NULL); assert("Good rc from publish", rc == MQTTCLIENT_SUCCESS, "rc was %d\n", rc); MyLog(LOGA_INFO, "Waiting to receive the will message"); count = 0; while (++count < 40) { #if defined(WIN32) Sleep(1000L); #else sleep(1); #endif if (test6_will_message_arrived == 1 && test6_connection_lost_called == 1) break; } assert("will message arrived", test6_will_message_arrived == 1, "will_message_arrived was %d\n", test6_will_message_arrived); assert("connection lost called", test6_connection_lost_called == 1, "connection_lost_called %d\n", test6_connection_lost_called); rc = MQTTClient_unsubscribe(test6_c2, test6_will_topic); assert("Good rc from unsubscribe", rc == MQTTCLIENT_SUCCESS, "rc was %d", rc); rc = MQTTClient_isConnected(test6_c2); assert("Client-2 still connected", rc == 1, "isconnected is %d", rc); rc = MQTTClient_isConnected(test6_c1); assert("Client-1 not connected", rc == 0, "isconnected is %d", rc); rc = MQTTClient_disconnect(test6_c2, 100L); assert("Good rc from disconnect", rc == MQTTCLIENT_SUCCESS, "rc was %d", rc); MQTTClient_destroy(&test6_c1); MQTTClient_destroy(&test6_c2); exit: MyLog(LOGA_INFO, "%s: test %s. %d tests run, %d failures.\n", (failures == 0) ? "passed" : "failed", testname, tests, failures); write_test_result(); return failures; } #endif int main(int argc, char **argv) { int rc = 0; int (*tests[])() = {NULL, test1, test2, test3}; int i; xml = fopen("TEST-test1.xml", "w"); fprintf(xml, "\n", (int)(ARRAY_SIZE(tests) - 1)); getopts(argc, argv); for (i = 0; i < options.iterations; ++i) { if (options.test_no == 0) { /* run all the tests */ for (options.test_no = 1; options.test_no < ARRAY_SIZE(tests); ++options.test_no) rc += tests[options.test_no](options); /* return number of failures. 0 = test succeeded */ } else rc = tests[options.test_no](options); /* run just the selected test */ } if (rc == 0) MyLog(LOGA_INFO, "verdict pass"); else MyLog(LOGA_INFO, "verdict fail"); fprintf(xml, "\n"); fclose(xml); return rc; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/CMakeLists.txt ================================================ #******************************************************************************* # Copyright (c) 2017 IBM Corp. # # All rights reserved. This program and the accompanying materials # are made available under the terms of the Eclipse Public License v1.0 # and Eclipse Distribution License v1.0 which accompany this distribution. # # The Eclipse Public License is available at # http://www.eclipse.org/legal/epl-v10.html # and the Eclipse Distribution License is available at # http://www.eclipse.org/org/documents/edl-v10.php. # # Contributors: # Ian Craggs - initial version #*******************************************************************************/ project("paho-mqttpacket" C) ADD_SUBDIRECTORY(src) ADD_SUBDIRECTORY(samples) ADD_SUBDIRECTORY(test) ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/CMakeLists.txt ================================================ #******************************************************************************* # Copyright (c) 2017 IBM Corp. # # All rights reserved. This program and the accompanying materials # are made available under the terms of the Eclipse Public License v1.0 # and Eclipse Distribution License v1.0 which accompany this distribution. # # The Eclipse Public License is available at # http://www.eclipse.org/legal/epl-v10.html # and the Eclipse Distribution License is available at # http://www.eclipse.org/org/documents/edl-v10.php. # # Contributors: # Ian Craggs - initial version #*******************************************************************************/ # Samples include_directories(../src) add_executable( pub0sub1 pub0sub1.c transport.c ) target_link_libraries(pub0sub1 paho-embed-mqtt3c) add_executable( pub0sub1_nb pub0sub1_nb.c transport.c ) target_link_libraries(pub0sub1_nb paho-embed-mqtt3c) add_executable( qos0pub qos0pub.c transport.c ) target_link_libraries(qos0pub paho-embed-mqtt3c) ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/baremetalserial/build ================================================ gcc -g -Wall pub0sub1_nb.c transport.c -I ../../src ../../src/MQTTConnectClient.c ../../src/MQTTSerializePublish.c ../../src/MQTTPacket.c ../../src/MQTTSubscribeClient.c -o pub0sub1_nb ../../src/MQTTDeserializePublish.c ../../src/MQTTConnectServer.c ../../src/MQTTSubscribeServer.c ../../src/MQTTUnsubscribeServer.c ../../src/MQTTUnsubscribeClient.c gcc -g -Wall ping_nb.c transport.c -I ../../src ../../src/MQTTConnectClient.c ../../src/MQTTPacket.c -o ping_nb ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/baremetalserial/ping_nb.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Sergio R. Caprile *******************************************************************************/ #include #include #include #include "MQTTPacket.h" #include "transport.h" #define KEEPALIVE_INTERVAL 20 /* This is to get a timebase in seconds to test the sample */ #include time_t old_t; void start_ping_timer(void) { time(&old_t); old_t += KEEPALIVE_INTERVAL / 2 + 1; } int time_to_ping(void) { time_t t; time(&t); if(t >= old_t) return 1; return 0; } /* This is in order to get an asynchronous signal to stop the sample, as the code loops waiting for msgs on the subscribed topic. Your actual code will depend on your hw and approach, but this sample can be run on Linux so debugging of the non-hardware specific bare metal code is easier. See at bottom of file for details */ #include int toStop = 0; void stop_init(void); /* */ /* Same as above, we provide a set of functions to test/debug on a friendlier system; the init() and close() actions on the serial are just for this, you will probably handle this on whatever handles your media in your application */ void sampleserial_init(void); void sampleserial_close(void); int samplesend(unsigned char *address, unsigned int bytes); int samplerecv(unsigned char *address, unsigned int maxbytes); /* */ /* You will use your hardware specifics here, see transport.h. */ static transport_iofunctions_t iof = {samplesend, samplerecv}; enum states { IDLE, SENDPING, GETPONG }; int main(int argc, char *argv[]) { MQTTPacket_connectData data = MQTTPacket_connectData_initializer; int rc = 0; int mysock = 0; unsigned char buf[200]; int buflen = sizeof(buf); int len = 0; MQTTTransport mytransport; int state; stop_init(); sampleserial_init(); mysock = transport_open(&iof); if(mysock < 0) return mysock; /* You will (or already are) 'somehow' connect(ed) to host:port via your hardware specifics. E.g.: you have a serial (RS-232/UART) link you have a cell modem and you issue your AT+ magic you have some TCP/IP which is not lwIP (nor a full-fledged socket compliant one) and you TCP connect */ mytransport.sck = &mysock; mytransport.getfn = transport_getdatanb; mytransport.state = 0; data.clientID.cstring = "me"; data.keepAliveInterval = KEEPALIVE_INTERVAL; data.cleansession = 1; data.username.cstring = "testuser"; data.password.cstring = "testpassword"; len = MQTTSerialize_connect(buf, buflen, &data); /* This one blocks until it finishes sending, you will probably not want this in real life, in such a case replace this call by a scheme similar to the one you'll see in the main loop */ rc = transport_sendPacketBuffer(mysock, buf, len); printf("Sent MQTT connect\n"); /* wait for connack */ do { int frc; if ((frc = MQTTPacket_readnb(buf, buflen, &mytransport)) == CONNACK) { unsigned char sessionPresent, connack_rc; if (MQTTDeserialize_connack(&sessionPresent, &connack_rc, buf, buflen) != 1 || connack_rc != 0) { printf("Unable to connect, return code %d\n", connack_rc); goto exit; } break; } else if (frc == -1) goto exit; } while (1); /* handle timeouts here */ printf("MQTT connected\n"); start_ping_timer(); state = IDLE; while (!toStop) { switch(state) { case IDLE: if(time_to_ping()) { len = MQTTSerialize_pingreq(buf, buflen); transport_sendPacketBuffernb_start(mysock, buf, len); state = SENDPING; } break; case SENDPING: switch(transport_sendPacketBuffernb(mysock)) { case TRANSPORT_DONE: printf("Ping..."); start_ping_timer(); state = GETPONG; break; case TRANSPORT_ERROR: /* handle any I/O errors here */ goto exit; break; case TRANSPORT_AGAIN: default: /* handle timeouts here, not probable unless there is a hardware problem */ break; } break; case GETPONG: if((rc = MQTTPacket_readnb(buf, buflen, &mytransport)) == PINGRESP) { printf("Pong\n"); start_ping_timer(); state = IDLE; } else if(rc == -1) { /* handle I/O errors here */ printf("OOPS\n"); goto exit; } /* handle timeouts here */ break; } } printf("disconnecting\n"); len = MQTTSerialize_disconnect(buf, buflen); /* Same blocking related stuff here */ rc = transport_sendPacketBuffer(mysock, buf, len); exit: transport_close(mysock); sampleserial_close(); return 0; } /* To stop the sample */ void cfinish(int sig) { signal(SIGINT, NULL); toStop = 1; } void stop_init(void) { signal(SIGINT, cfinish); signal(SIGTERM, cfinish); } /* Serial hack: Simulate serial transfers on an established TCP connection */ #include #include #include #include #include #include #include static int sockfd; void sampleserial_init(void) { struct sockaddr_in serv_addr; if ((sockfd = socket(AF_INET, SOCK_STREAM, 0)) < 0) { perror(NULL); exit(2); } serv_addr.sin_family = AF_INET; serv_addr.sin_addr.s_addr = inet_addr("198.41.30.241"); serv_addr.sin_port = htons(1883); if (connect(sockfd, (struct sockaddr *)&serv_addr, sizeof(serv_addr)) < 0) { printf("ERROR connecting\n"); exit(-1); } printf("- TCP Connected to Eclipse\n"); /* set to non-blocking */ fcntl(sockfd, F_SETFL, fcntl(sockfd, F_GETFL) | O_NONBLOCK); } void sampleserial_close(void) { close(sockfd); } int samplesend(unsigned char *address, unsigned int bytes) { int len; if(rand() > (RAND_MAX / 2)) // 50% probability of being busy return 0; if(rand() > (RAND_MAX / 2)) // 50% probability of sending half the requested data (no room in buffer) { if(bytes > 1) bytes /= 2; } if((len = write(sockfd, address, bytes)) >= 0) return len; if(errno == EAGAIN) return 0; return -1; } int samplerecv(unsigned char *address, unsigned int maxbytes) { int len; if(rand() > (RAND_MAX / 2)) // 50% probability of no data return 0; if(rand() > (RAND_MAX / 2)) // 50% probability of getting half the requested data (not arrived yet) { if(maxbytes > 1) { maxbytes /= 2; } } if((len = read(sockfd, address, maxbytes)) >= 0) return len; if(errno == EAGAIN) return 0; return -1; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/baremetalserial/pub0sub1_nb.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Sergio R. Caprile - port to the bare metal environment *******************************************************************************/ #include #include #include #include "MQTTPacket.h" #include "transport.h" /* This is in order to get an asynchronous signal to stop the sample, as the code loops waiting for msgs on the subscribed topic. Your actual code will depend on your hw and approach, but this sample can be run on Linux so debugging of the non-hardware specific bare metal code is easier. See at bottom of file for details */ #include int toStop = 0; void stop_init(void); /* */ /* Same as above, we provide a set of functions to test/debug on a friendlier system; the init() and close() actions on the serial are just for this, you will probably handle this on whatever handles your media in your application */ void sampleserial_init(void); void sampleserial_close(void); int samplesend(unsigned char *address, unsigned int bytes); int samplerecv(unsigned char *address, unsigned int maxbytes); /* */ /* You will use your hardware specifics here, see transport.h. */ static transport_iofunctions_t iof = {samplesend, samplerecv}; enum states { READING, PUBLISHING }; int main(int argc, char *argv[]) { MQTTPacket_connectData data = MQTTPacket_connectData_initializer; int rc = 0; int mysock = 0; unsigned char buf[200]; int buflen = sizeof(buf); int msgid = 1; MQTTString topicString = MQTTString_initializer; int req_qos = 0; char *payload = "mypayload"; int payloadlen = strlen(payload); int len = 0; MQTTTransport mytransport; int state = READING; stop_init(); sampleserial_init(); mysock = transport_open(&iof); if(mysock < 0) return mysock; /* You will (or already are) 'somehow' connect(ed) to host:port via your hardware specifics. E.g.: you have a serial (RS-232/UART) link you have a cell modem and you issue your AT+ magic you have some TCP/IP which is not lwIP (nor a full-fledged socket compliant one) and you TCP connect */ mytransport.sck = &mysock; mytransport.getfn = transport_getdatanb; mytransport.state = 0; data.clientID.cstring = "me"; data.keepAliveInterval = 20; data.cleansession = 1; data.username.cstring = "testuser"; data.password.cstring = "testpassword"; len = MQTTSerialize_connect(buf, buflen, &data); /* This one blocks until it finishes sending, you will probably not want this in real life, in such a case replace this call by a scheme similar to the one you'll see in the main loop */ rc = transport_sendPacketBuffer(mysock, buf, len); printf("Sent MQTT connect\n"); /* wait for connack */ do { int frc; if ((frc = MQTTPacket_readnb(buf, buflen, &mytransport)) == CONNACK) { unsigned char sessionPresent, connack_rc; if (MQTTDeserialize_connack(&sessionPresent, &connack_rc, buf, buflen) != 1 || connack_rc != 0) { printf("Unable to connect, return code %d\n", connack_rc); goto exit; } break; } else if (frc == -1) goto exit; } while (1); /* handle timeouts here */ printf("MQTT connected\n"); /* subscribe */ topicString.cstring = "substopic"; len = MQTTSerialize_subscribe(buf, buflen, 0, msgid, 1, &topicString, &req_qos); /* This is equivalent to the one above, but using the non-blocking functions. You will probably not want this in real life, in such a case replace this call by a scheme similar to the one you'll see in the main loop */ transport_sendPacketBuffernb_start(mysock, buf, len); while((rc = transport_sendPacketBuffernb(mysock)) != TRANSPORT_DONE); do { int frc; if ((frc = MQTTPacket_readnb(buf, buflen, &mytransport)) == SUBACK) /* wait for suback */ { unsigned short submsgid; int subcount; int granted_qos; rc = MQTTDeserialize_suback(&submsgid, 1, &subcount, &granted_qos, buf, buflen); if (granted_qos != 0) { printf("granted qos != 0, %d\n", granted_qos); goto exit; } break; } else if (frc == -1) goto exit; } while (1); /* handle timeouts here */ printf("Subscribed\n"); /* loop getting msgs on subscribed topic */ topicString.cstring = "pubtopic"; state = READING; while (!toStop) { /* do other stuff here */ switch(state) { case READING: if((rc = MQTTPacket_readnb(buf, buflen, &mytransport)) == PUBLISH) { unsigned char dup; int qos; unsigned char retained; unsigned short msgid; int payloadlen_in; unsigned char *payload_in; int rc; MQTTString receivedTopic; rc = MQTTDeserialize_publish(&dup, &qos, &retained, &msgid, &receivedTopic, &payload_in, &payloadlen_in, buf, buflen); printf("message arrived %.*s\n", payloadlen_in, payload_in); printf("publishing reading\n"); state = PUBLISHING; len = MQTTSerialize_publish(buf, buflen, 0, 0, 0, 0, topicString, (unsigned char *)payload, payloadlen); transport_sendPacketBuffernb_start(mysock, buf, len); } else if(rc == -1) { /* handle I/O errors here */ goto exit; } /* handle timeouts here */ break; case PUBLISHING: switch(transport_sendPacketBuffernb(mysock)) { case TRANSPORT_DONE: printf("Published\n"); state = READING; break; case TRANSPORT_ERROR: /* handle any I/O errors here */ goto exit; break; case TRANSPORT_AGAIN: default: /* handle timeouts here, not probable unless there is a hardware problem */ break; } break; } } printf("disconnecting\n"); len = MQTTSerialize_disconnect(buf, buflen); /* Same blocking related stuff here */ rc = transport_sendPacketBuffer(mysock, buf, len); exit: transport_close(mysock); sampleserial_close(); return 0; } /* To stop the sample */ void cfinish(int sig) { signal(SIGINT, NULL); toStop = 1; } void stop_init(void) { signal(SIGINT, cfinish); signal(SIGTERM, cfinish); } /* Serial hack: Simulate serial transfers on an established TCP connection */ #include #include #include #include #include #include #include static int sockfd; void sampleserial_init(void) { struct sockaddr_in serv_addr; if ((sockfd = socket(AF_INET, SOCK_STREAM, 0)) < 0) { perror(NULL); exit(2); } serv_addr.sin_family = AF_INET; serv_addr.sin_addr.s_addr = inet_addr("198.41.30.241"); serv_addr.sin_port = htons(1883); if (connect(sockfd, (struct sockaddr *)&serv_addr, sizeof(serv_addr)) < 0) { printf("ERROR connecting\n"); exit(-1); } printf("- TCP Connected to Eclipse\n"); /* set to non-blocking */ fcntl(sockfd, F_SETFL, fcntl(sockfd, F_GETFL) | O_NONBLOCK); } void sampleserial_close(void) { close(sockfd); } int samplesend(unsigned char *address, unsigned int bytes) { int len; if(rand() > (RAND_MAX / 2)) // 50% probability of being busy return 0; if(rand() > (RAND_MAX / 2)) // 50% probability of sending half the requested data (no room in buffer) { if(bytes > 1) bytes /= 2; } if((len = write(sockfd, address, bytes)) >= 0) return len; if(errno == EAGAIN) return 0; return -1; } int samplerecv(unsigned char *address, unsigned int maxbytes) { int len; if(rand() > (RAND_MAX / 2)) // 50% probability of no data return 0; if(rand() > (RAND_MAX / 2)) // 50% probability of getting half the requested data (not arrived yet) { if(maxbytes > 1) { maxbytes /= 2; } } if((len = read(sockfd, address, maxbytes)) >= 0) return len; if(errno == EAGAIN) return 0; return -1; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/baremetalserial/transport.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Sergio R. Caprile - port to the bare metal environment and serial media specifics *******************************************************************************/ /** By the way, this is a nice bare bones example, easier to expand to whatever non-OS media you might have */ #include #include #include #include #include #include "transport.h" /** This simple low-level implementation assumes a single connection for a single thread. Thus, single static variables are used for that connection. On other scenarios, you might want to put all these variables into a structure and index via the 'sock' parameter, as some functions show in the comments The blocking rx function is not supported. If you plan on writing one, take into account that the current implementation of MQTTPacket_read() has a function pointer for a function call to get the data to a buffer, but no provisions to know the caller or other indicator (the socket id): int (*getfn)(unsigned char*, int) */ static transport_iofunctions_t *io = NULL; static unsigned char *from = NULL; // to keep track of data sending static int howmany; // ditto void transport_sendPacketBuffernb_start(int sock, unsigned char *buf, int buflen) { from = buf; // from[sock] or mystruct[sock].from howmany = buflen; // myhowmany[sock] or mystruct[sock].howmany } int transport_sendPacketBuffernb(int sock) { transport_iofunctions_t *myio = io; // io[sock] or mystruct[sock].io int len; /* you should have called open() with a valid pointer to a valid struct and called sendPacketBuffernb_start with a valid buffer, before calling this */ assert((myio != NULL) && (myio->send != NULL) && (from != NULL)); if((len = myio->send(from, howmany)) > 0) { from += len; if((howmany -= len) <= 0) { return TRANSPORT_DONE; } } else if(len < 0) { return TRANSPORT_ERROR; } return TRANSPORT_AGAIN; } int transport_sendPacketBuffer(int sock, unsigned char *buf, int buflen) { int rc; transport_sendPacketBuffernb_start(sock, buf, buflen); while((rc = transport_sendPacketBuffernb(sock)) == TRANSPORT_AGAIN) { /* this is unlikely to loop forever unless there is a hardware problem */ } if(rc == TRANSPORT_DONE) { return buflen; } return TRANSPORT_ERROR; } int transport_getdata(unsigned char *buf, int count) { assert(0); /* This function is NOT supported, it is just here to tease you */ return TRANSPORT_ERROR; /* nah, it is here for similarity with other transport examples */ } int transport_getdatanb(void *sck, unsigned char *buf, int count) { //int sock = *((int *)sck); /* sck: pointer to whatever the system may use to identify the transport */ transport_iofunctions_t *myio = io; // io[sock] or mystruct[sock].io int len; /* you should have called open() with a valid pointer to a valid struct before calling this */ assert((myio != NULL) && (myio->recv != NULL)); /* this call will return immediately if no bytes, or return whatever outstanding bytes we have, upto count */ if((len = myio->recv(buf, count)) >= 0) return len; return TRANSPORT_ERROR; } /** return >=0 for a connection descriptor, <0 for an error code */ int transport_open(transport_iofunctions_t *thisio) { int idx = 0; // for multiple connections, you might, basically turn myio into myio[MAX_CONNECTIONS], //if((idx=assignidx()) >= MAX_CONNECTIONS) // somehow assign an index, // return TRANSPORT_ERROR; io = thisio; // store myio[idx] = thisio, or mystruct[idx].io = thisio, return idx; // and return the index used } int transport_close(int sock) { int rc = TRANSPORT_DONE; return rc; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/baremetalserial/transport.h ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Sergio R. Caprile - media specifics, nice api doc :^) *******************************************************************************/ typedef struct { int (*send)(unsigned char *address, unsigned int bytes); ///< pointer to function to send 'bytes' bytes, returns the actual number of bytes sent int (*recv)(unsigned char *address, unsigned int maxbytes); ///< pointer to function to receive upto 'maxbytes' bytes, returns the actual number of bytes copied } transport_iofunctions_t; #define TRANSPORT_DONE 1 #define TRANSPORT_AGAIN 0 #define TRANSPORT_ERROR -1 /** @note Blocks until requested buflen is sent */ int transport_sendPacketBuffer(int sock, unsigned char* buf, int buflen); /** @note Blocks until requested count is received, as MQTTPacket_read() expects @warning This function is not supported (not implemented) @warning unless you provide a timeout, this function can block forever. Socket based systems do have a built in timeout, if your system can provide this, do modify this function, otherwise use getdatanb() instead @returns number of bytes read */ int transport_getdata(unsigned char* buf, int count); /** This is a bare metal implementation, so we must have non-blocking functions, the process of pumping to serial lines can result a bit slow and we don't want to busy wait. This function starts the process, you will call sendPacketBuffernb() until it reports success (or error) */ void transport_sendPacketBuffernb_start(int sock, unsigned char* buf, int buflen); /** This is a bare metal implementation, so we must have non-blocking functions, the process of pumping to serial lines can result a bit slow and we don't want to busy wait @returns TRANSPORT_DONE if finished, TRANSPORT_AGAIN for call again, or TRANSPORT_ERROR on error @note you will call again until it finishes (this is stream) */ int transport_sendPacketBuffernb(int sock); /** This is a bare metal implementation, so we must have non-blocking functions, the process of sucking from serial lines can result a bit slow and we don't want to busy wait @return the actual number of bytes read, 0 for none, or TRANSPORT_ERROR on error @note you will call again until total number of expected bytes is read (this is stream) */ int transport_getdatanb(void *sck, unsigned char* buf, int count); /** We assume whatever connection needs to be done, it is externally established by the specifics of the hardware E.g.: A cell modem: you will call AT+whatever and put the modem in transparent mode, OR, you will embed the AT+xSENDx / AT+xRECVx commands into the former sendPacketBuffer() and getdatanb() functions @param thisio pointer to a structure containing all necessary stuff to handle direct serial I/O @returns whatever indicator the system assigns to this link, if any. (a.k.a. : 'sock'), or TRANSPORT_ERROR for error */ int transport_open(transport_iofunctions_t *thisio); int transport_close(int sock); ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/build ================================================ gcc -Wall -c transport.c -Os -s gcc qos0pub.c transport.o -I ../src ../src/MQTTConnectClient.c ../src/MQTTSerializePublish.c ../src/MQTTPacket.c -o qos0pub -Os -s gcc pub0sub1.c transport.o -I ../src ../src/MQTTConnectClient.c ../src/MQTTSerializePublish.c ../src/MQTTPacket.c ../src/MQTTSubscribeClient.c -o pub0sub1 ../src/MQTTDeserializePublish.c -Os -s ../src/MQTTConnectServer.c ../src/MQTTSubscribeServer.c ../src/MQTTUnsubscribeServer.c ../src/MQTTUnsubscribeClient.c -ggdb gcc pub0sub1_nb.c transport.o -I ../src ../src/MQTTConnectClient.c ../src/MQTTSerializePublish.c ../src/MQTTPacket.c ../src/MQTTSubscribeClient.c -o pub0sub1_nb ../src/MQTTDeserializePublish.c -Os -s ../src/MQTTConnectServer.c ../src/MQTTSubscribeServer.c ../src/MQTTUnsubscribeServer.c ../src/MQTTUnsubscribeClient.c -ggdb ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/null.c ================================================ int main(int argc, char **argv) { return 0; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/ping.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Sergio R. Caprile - port *******************************************************************************/ #include #include #include #include "MQTTPacket.h" #include "transport.h" #define KEEPALIVE_INTERVAL 20 /* This is to get a timebase in seconds to test the sample */ #include time_t old_t; void start_ping_timer(void) { time(&old_t); old_t += KEEPALIVE_INTERVAL / 2 + 1; } int time_to_ping(void) { time_t t; time(&t); if(t >= old_t) return 1; return 0; } /* This is in order to get an asynchronous signal to stop the sample, as the code loops waiting for msgs on the subscribed topic. Your actual code will depend on your hw and approach*/ #include int toStop = 0; void cfinish(int sig) { signal(SIGINT, NULL); toStop = 1; } void stop_init(void) { signal(SIGINT, cfinish); signal(SIGTERM, cfinish); } /* */ int main(int argc, char *argv[]) { MQTTPacket_connectData data = MQTTPacket_connectData_initializer; int rc = 0; int mysock = 0; unsigned char buf[200]; int buflen = sizeof(buf); int len = 0; char *host = "m2m.eclipse.org"; int port = 1883; stop_init(); if (argc > 1) host = argv[1]; if (argc > 2) port = atoi(argv[2]); mysock = transport_open(host, port); if(mysock < 0) return mysock; printf("Sending to hostname %s port %d\n", host, port); data.clientID.cstring = "me"; data.keepAliveInterval = KEEPALIVE_INTERVAL; data.cleansession = 1; data.username.cstring = "testuser"; data.password.cstring = "testpassword"; len = MQTTSerialize_connect(buf, buflen, &data); rc = transport_sendPacketBuffer(mysock, buf, len); printf("Sent MQTT connect\n"); /* wait for connack */ if (MQTTPacket_read(buf, buflen, transport_getdata) == CONNACK) { unsigned char sessionPresent, connack_rc; if (MQTTDeserialize_connack(&sessionPresent, &connack_rc, buf, buflen) != 1 || connack_rc != 0) { printf("Unable to connect, return code %d\n", connack_rc); goto exit; } } else goto exit; printf("MQTT connected\n"); start_ping_timer(); while (!toStop) { while(!time_to_ping()); len = MQTTSerialize_pingreq(buf, buflen); transport_sendPacketBuffer(mysock, buf, len); printf("Ping..."); if (MQTTPacket_read(buf, buflen, transport_getdata) == PINGRESP) { printf("Pong\n"); start_ping_timer(); } else { printf("OOPS\n"); goto exit; } } printf("disconnecting\n"); len = MQTTSerialize_disconnect(buf, buflen); rc = transport_sendPacketBuffer(mysock, buf, len); exit: transport_close(mysock); return 0; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/ping_nb.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Sergio R. Caprile - port and nonblocking *******************************************************************************/ #include #include #include #include "MQTTPacket.h" #include "transport.h" #define KEEPALIVE_INTERVAL 20 /* This is to get a timebase in seconds to test the sample */ #include time_t old_t; void start_ping_timer(void) { time(&old_t); old_t += KEEPALIVE_INTERVAL / 2 + 1; } int time_to_ping(void) { time_t t; time(&t); if(t >= old_t) return 1; return 0; } /* This is in order to get an asynchronous signal to stop the sample, as the code loops waiting for msgs on the subscribed topic. Your actual code will depend on your hw and approach*/ #include int toStop = 0; void cfinish(int sig) { signal(SIGINT, NULL); toStop = 1; } void stop_init(void) { signal(SIGINT, cfinish); signal(SIGTERM, cfinish); } /* */ enum states { IDLE, GETPONG }; int main(int argc, char *argv[]) { MQTTPacket_connectData data = MQTTPacket_connectData_initializer; int rc = 0; int mysock = 0; unsigned char buf[200]; int buflen = sizeof(buf); int len = 0; char *host = "m2m.eclipse.org"; int port = 1883; MQTTTransport mytransport; int state; stop_init(); if (argc > 1) host = argv[1]; if (argc > 2) port = atoi(argv[2]); mysock = transport_open(host, port); if(mysock < 0) return mysock; printf("Sending to hostname %s port %d\n", host, port); mytransport.sck = &mysock; mytransport.getfn = transport_getdatanb; mytransport.state = 0; data.clientID.cstring = "me"; data.keepAliveInterval = KEEPALIVE_INTERVAL; data.cleansession = 1; data.username.cstring = "testuser"; data.password.cstring = "testpassword"; len = MQTTSerialize_connect(buf, buflen, &data); rc = transport_sendPacketBuffer(mysock, buf, len); printf("Sent MQTT connect\n"); /* wait for connack */ do { int frc; if ((frc = MQTTPacket_readnb(buf, buflen, &mytransport)) == CONNACK) { unsigned char sessionPresent, connack_rc; if (MQTTDeserialize_connack(&sessionPresent, &connack_rc, buf, buflen) != 1 || connack_rc != 0) { printf("Unable to connect, return code %d\n", connack_rc); goto exit; } break; } else if (frc == -1) goto exit; } while (1); /* handle timeouts here */ printf("MQTT connected\n"); start_ping_timer(); state = IDLE; while (!toStop) { switch(state) { case IDLE: if(time_to_ping()) { len = MQTTSerialize_pingreq(buf, buflen); transport_sendPacketBuffer(mysock, buf, len); printf("Ping..."); state = GETPONG; } break; case GETPONG: if((rc = MQTTPacket_readnb(buf, buflen, &mytransport)) == PINGRESP) { printf("Pong\n"); start_ping_timer(); state = IDLE; } else if(rc == -1) { printf("OOPS\n"); goto exit; } break; } } printf("disconnecting\n"); len = MQTTSerialize_disconnect(buf, buflen); rc = transport_sendPacketBuffer(mysock, buf, len); exit: transport_close(mysock); return 0; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/pub0sub1.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Sergio R. Caprile - clarifications and/or documentation extension *******************************************************************************/ #include #include #include #include "MQTTPacket.h" #include "transport.h" /* This is in order to get an asynchronous signal to stop the sample, as the code loops waiting for msgs on the subscribed topic. Your actual code will depend on your hw and approach*/ #include int toStop = 0; void cfinish(int sig) { signal(SIGINT, NULL); toStop = 1; } void stop_init(void) { signal(SIGINT, cfinish); signal(SIGTERM, cfinish); } /* */ int main(int argc, char *argv[]) { MQTTPacket_connectData data = MQTTPacket_connectData_initializer; int rc = 0; int mysock = 0; unsigned char buf[200]; int buflen = sizeof(buf); int msgid = 1; MQTTString topicString = MQTTString_initializer; int req_qos = 0; char *payload = "mypayload"; int payloadlen = strlen(payload); int len = 0; char *host = "m2m.eclipse.org"; int port = 1883; stop_init(); if (argc > 1) host = argv[1]; if (argc > 2) port = atoi(argv[2]); mysock = transport_open(host, port); if(mysock < 0) return mysock; printf("Sending to hostname %s port %d\n", host, port); data.clientID.cstring = "me"; data.keepAliveInterval = 20; data.cleansession = 1; data.username.cstring = "testuser"; data.password.cstring = "testpassword"; len = MQTTSerialize_connect(buf, buflen, &data); rc = transport_sendPacketBuffer(mysock, buf, len); /* wait for connack */ if (MQTTPacket_read(buf, buflen, transport_getdata) == CONNACK) { unsigned char sessionPresent, connack_rc; if (MQTTDeserialize_connack(&sessionPresent, &connack_rc, buf, buflen) != 1 || connack_rc != 0) { printf("Unable to connect, return code %d\n", connack_rc); goto exit; } } else goto exit; /* subscribe */ topicString.cstring = "substopic"; len = MQTTSerialize_subscribe(buf, buflen, 0, msgid, 1, &topicString, &req_qos); rc = transport_sendPacketBuffer(mysock, buf, len); if (MQTTPacket_read(buf, buflen, transport_getdata) == SUBACK) /* wait for suback */ { unsigned short submsgid; int subcount; int granted_qos; rc = MQTTDeserialize_suback(&submsgid, 1, &subcount, &granted_qos, buf, buflen); if (granted_qos != 0) { printf("granted qos != 0, %d\n", granted_qos); goto exit; } } else goto exit; /* loop getting msgs on subscribed topic */ topicString.cstring = "pubtopic"; while (!toStop) { /* transport_getdata() has a built-in 1 second timeout, your mileage will vary */ if (MQTTPacket_read(buf, buflen, transport_getdata) == PUBLISH) { unsigned char dup; int qos; unsigned char retained; unsigned short msgid; int payloadlen_in; unsigned char *payload_in; int rc; MQTTString receivedTopic; rc = MQTTDeserialize_publish(&dup, &qos, &retained, &msgid, &receivedTopic, &payload_in, &payloadlen_in, buf, buflen); printf("message arrived %.*s\n", payloadlen_in, payload_in); } printf("publishing reading\n"); len = MQTTSerialize_publish(buf, buflen, 0, 0, 0, 0, topicString, (unsigned char *)payload, payloadlen); rc = transport_sendPacketBuffer(mysock, buf, len); } printf("disconnecting\n"); len = MQTTSerialize_disconnect(buf, buflen); rc = transport_sendPacketBuffer(mysock, buf, len); exit: transport_close(mysock); return 0; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/pub0sub1_nb.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Sergio R. Caprile - clarifications and/or documentation extension *******************************************************************************/ #include #include #include #include "MQTTPacket.h" #include "transport.h" /* This is in order to get an asynchronous signal to stop the sample, as the code loops waiting for msgs on the subscribed topic. Your actual code will depend on your hw and approach*/ #include int toStop = 0; void cfinish(int sig) { signal(SIGINT, NULL); toStop = 1; } void stop_init(void) { signal(SIGINT, cfinish); signal(SIGTERM, cfinish); } /* */ int main(int argc, char *argv[]) { MQTTPacket_connectData data = MQTTPacket_connectData_initializer; int rc = 0; int mysock = 0; unsigned char buf[200]; int buflen = sizeof(buf); int msgid = 1; MQTTString topicString = MQTTString_initializer; int req_qos = 0; char *payload = "mypayload"; int payloadlen = strlen(payload); int len = 0; char *host = "m2m.eclipse.org"; int port = 1883; MQTTTransport mytransport; stop_init(); if (argc > 1) host = argv[1]; if (argc > 2) port = atoi(argv[2]); mysock = transport_open(host, port); if(mysock < 0) return mysock; printf("Sending to hostname %s port %d\n", host, port); mytransport.sck = &mysock; mytransport.getfn = transport_getdatanb; mytransport.state = 0; data.clientID.cstring = "me"; data.keepAliveInterval = 20; data.cleansession = 1; data.username.cstring = "testuser"; data.password.cstring = "testpassword"; len = MQTTSerialize_connect(buf, buflen, &data); rc = transport_sendPacketBuffer(mysock, buf, len); /* wait for connack */ if (MQTTPacket_read(buf, buflen, transport_getdata) == CONNACK) { unsigned char sessionPresent, connack_rc; if (MQTTDeserialize_connack(&sessionPresent, &connack_rc, buf, buflen) != 1 || connack_rc != 0) { printf("Unable to connect, return code %d\n", connack_rc); goto exit; } } else goto exit; /* subscribe */ topicString.cstring = "substopic"; len = MQTTSerialize_subscribe(buf, buflen, 0, msgid, 1, &topicString, &req_qos); rc = transport_sendPacketBuffer(mysock, buf, len); do { int frc; if ((frc = MQTTPacket_readnb(buf, buflen, &mytransport)) == SUBACK) /* wait for suback */ { unsigned short submsgid; int subcount; int granted_qos; rc = MQTTDeserialize_suback(&submsgid, 1, &subcount, &granted_qos, buf, buflen); if (granted_qos != 0) { printf("granted qos != 0, %d\n", granted_qos); goto exit; } break; } else if (frc == -1) goto exit; } while (1); /* handle timeouts here */ /* loop getting msgs on subscribed topic */ topicString.cstring = "pubtopic"; while (!toStop) { /* handle timeouts */ if (MQTTPacket_readnb(buf, buflen, &mytransport) == PUBLISH) { unsigned char dup; int qos; unsigned char retained; unsigned short msgid; int payloadlen_in; unsigned char *payload_in; int rc; MQTTString receivedTopic; rc = MQTTDeserialize_publish(&dup, &qos, &retained, &msgid, &receivedTopic, &payload_in, &payloadlen_in, buf, buflen); printf("message arrived %.*s\n", payloadlen_in, payload_in); printf("publishing reading\n"); len = MQTTSerialize_publish(buf, buflen, 0, 0, 0, 0, topicString, (unsigned char *)payload, payloadlen); rc = transport_sendPacketBuffer(mysock, buf, len); } } printf("disconnecting\n"); len = MQTTSerialize_disconnect(buf, buflen); rc = transport_sendPacketBuffer(mysock, buf, len); exit: transport_close(mysock); return 0; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/qos0pub.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Sergio R. Caprile - clarifications and/or documentation extension *******************************************************************************/ #include #include #include #include "MQTTPacket.h" #include "transport.h" int main(int argc, char *argv[]) { MQTTPacket_connectData data = MQTTPacket_connectData_initializer; int rc = 0; char buf[200]; int buflen = sizeof(buf); int mysock = 0; MQTTString topicString = MQTTString_initializer; char *payload = "mypayload"; int payloadlen = strlen(payload); int len = 0; char *host = "m2m.eclipse.org"; int port = 1883; if (argc > 1) host = argv[1]; if (argc > 2) port = atoi(argv[2]); mysock = transport_open(host, port); if(mysock < 0) return mysock; printf("Sending to hostname %s port %d\n", host, port); data.clientID.cstring = "me"; data.keepAliveInterval = 20; data.cleansession = 1; data.username.cstring = "testuser"; data.password.cstring = "testpassword"; data.MQTTVersion = 4; len = MQTTSerialize_connect((unsigned char *)buf, buflen, &data); topicString.cstring = "mytopic"; len += MQTTSerialize_publish((unsigned char *)(buf + len), buflen - len, 0, 0, 0, 0, topicString, (unsigned char *)payload, payloadlen); len += MQTTSerialize_disconnect((unsigned char *)(buf + len), buflen - len); rc = transport_sendPacketBuffer(mysock, (unsigned char *)buf, len); if (rc == len) printf("Successfully published\n"); else printf("Publish failed\n"); exit: transport_close(mysock); return 0; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/transport.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Sergio R. Caprile - "commonalization" from prior samples and/or documentation extension *******************************************************************************/ #include #if !defined(SOCKET_ERROR) /** error in socket operation */ #define SOCKET_ERROR -1 #endif #if defined(WIN32) /* default on Windows is 64 - increase to make Linux and Windows the same */ #define FD_SETSIZE 1024 #include #include #define MAXHOSTNAMELEN 256 #define EAGAIN WSAEWOULDBLOCK #define EINTR WSAEINTR #define EINVAL WSAEINVAL #define EINPROGRESS WSAEINPROGRESS #define EWOULDBLOCK WSAEWOULDBLOCK #define ENOTCONN WSAENOTCONN #define ECONNRESET WSAECONNRESET #define ioctl ioctlsocket #define socklen_t int #else #define INVALID_SOCKET SOCKET_ERROR #include #include #include #include #include #include #include #include #include #include #include #include #include #endif #if defined(WIN32) #include #else #include #include #endif /** This simple low-level implementation assumes a single connection for a single thread. Thus, a static variable is used for that connection. On other scenarios, the user must solve this by taking into account that the current implementation of MQTTPacket_read() has a function pointer for a function call to get the data to a buffer, but no provisions to know the caller or other indicator (the socket id): int (*getfn)(unsigned char*, int) */ static int mysock = INVALID_SOCKET; int transport_sendPacketBuffer(int sock, unsigned char *buf, int buflen) { int rc = 0; rc = write(sock, buf, buflen); return rc; } int transport_getdata(unsigned char *buf, int count) { int rc = recv(mysock, buf, count, 0); //printf("received %d bytes count %d\n", rc, (int)count); return rc; } int transport_getdatanb(void *sck, unsigned char *buf, int count) { int sock = *((int *)sck); /* sck: pointer to whatever the system may use to identify the transport */ /* this call will return after the timeout set on initialization if no bytes; in your system you will use whatever you use to get whichever outstanding bytes your socket equivalent has ready to be extracted right now, if any, or return immediately */ int rc = recv(sock, buf, count, 0); if (rc == -1) { /* check error conditions from your system here, and return -1 */ return 0; } return rc; } /** return >=0 for a socket descriptor, <0 for an error code @todo Basically moved from the sample without changes, should accomodate same usage for 'sock' for clarity, removing indirections */ int transport_open(char *addr, int port) { int *sock = &mysock; int type = SOCK_STREAM; struct sockaddr_in address; #if defined(AF_INET6) struct sockaddr_in6 address6; #endif int rc = -1; #if defined(WIN32) short family; #else sa_family_t family = AF_INET; #endif struct addrinfo *result = NULL; struct addrinfo hints = {0, AF_UNSPEC, SOCK_STREAM, IPPROTO_TCP, 0, NULL, NULL, NULL}; static struct timeval tv; *sock = -1; if (addr[0] == '[') ++addr; if ((rc = getaddrinfo(addr, NULL, &hints, &result)) == 0) { struct addrinfo *res = result; /* prefer ip4 addresses */ while (res) { if (res->ai_family == AF_INET) { result = res; break; } res = res->ai_next; } #if defined(AF_INET6) if (result->ai_family == AF_INET6) { address6.sin6_port = htons(port); address6.sin6_family = family = AF_INET6; address6.sin6_addr = ((struct sockaddr_in6 *)(result->ai_addr))->sin6_addr; } else #endif if (result->ai_family == AF_INET) { address.sin_port = htons(port); address.sin_family = family = AF_INET; address.sin_addr = ((struct sockaddr_in *)(result->ai_addr))->sin_addr; } else rc = -1; freeaddrinfo(result); } if (rc == 0) { *sock = socket(family, type, 0); if (*sock != -1) { #if defined(NOSIGPIPE) int opt = 1; if (setsockopt(*sock, SOL_SOCKET, SO_NOSIGPIPE, (void *)&opt, sizeof(opt)) != 0) Log(TRACE_MIN, -1, "Could not set SO_NOSIGPIPE for socket %d", *sock); #endif if (family == AF_INET) rc = connect(*sock, (struct sockaddr *)&address, sizeof(address)); #if defined(AF_INET6) else rc = connect(*sock, (struct sockaddr *)&address6, sizeof(address6)); #endif } } if (mysock == INVALID_SOCKET) return rc; tv.tv_sec = 1; /* 1 second Timeout */ tv.tv_usec = 0; setsockopt(mysock, SOL_SOCKET, SO_RCVTIMEO, (char *)&tv, sizeof(struct timeval)); return mysock; } int transport_close(int sock) { int rc; rc = shutdown(sock, SHUT_WR); rc = recv(sock, NULL, (size_t)0, 0); rc = close(sock); return rc; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/samples/transport.h ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Sergio R. Caprile - "commonalization" from prior samples and/or documentation extension *******************************************************************************/ int transport_sendPacketBuffer(int sock, unsigned char* buf, int buflen); int transport_getdata(unsigned char* buf, int count); int transport_getdatanb(void *sck, unsigned char* buf, int count); int transport_open(char* host, int port); int transport_close(int sock); ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/CMakeLists.txt ================================================ #******************************************************************************* # Copyright (c) 2017 IBM Corp. # # All rights reserved. This program and the accompanying materials # are made available under the terms of the Eclipse Public License v1.0 # and Eclipse Distribution License v1.0 which accompany this distribution. # # The Eclipse Public License is available at # http://www.eclipse.org/legal/epl-v10.html # and the Eclipse Distribution License is available at # http://www.eclipse.org/org/documents/edl-v10.php. # # Contributors: # Ian Craggs - initial version #*******************************************************************************/ # MQTTPacket Library file(GLOB SOURCES "*.c") add_library(paho-embed-mqtt3c SHARED ${SOURCES}) install(TARGETS paho-embed-mqtt3c DESTINATION /usr/lib) target_compile_definitions(paho-embed-mqtt3c PRIVATE MQTT_SERVER MQTT_CLIENT) add_library(MQTTPacketClient SHARED MQTTFormat MQTTPacket MQTTSerializePublish MQTTDeserializePublish MQTTConnectClient MQTTSubscribeClient MQTTUnsubscribeClient) target_compile_definitions(MQTTPacketClient PRIVATE MQTT_CLIENT) add_library(MQTTPacketServer SHARED MQTTFormat MQTTPacket MQTTSerializePublish MQTTDeserializePublish MQTTConnectServer MQTTSubscribeServer MQTTUnsubscribeServer) target_compile_definitions(MQTTPacketServer PRIVATE MQTT_SERVER) ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTConnect.h ================================================ /******************************************************************************* * Copyright (c) 2014, 2017 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Xiang Rong - 442039 Add makefile to Embedded C client * Ian Craggs - fix for issue #64, bit order in connack response *******************************************************************************/ #ifndef MQTTCONNECT_H_ #define MQTTCONNECT_H_ #if !defined(DLLImport) #define DLLImport #endif #if !defined(DLLExport) #define DLLExport #endif typedef union { unsigned char all; /**< all connect flags */ #if defined(REVERSED) struct { unsigned int username : 1; /**< 3.1 user name */ unsigned int password : 1; /**< 3.1 password */ unsigned int willRetain : 1; /**< will retain setting */ unsigned int willQoS : 2; /**< will QoS value */ unsigned int will : 1; /**< will flag */ unsigned int cleansession : 1; /**< clean session flag */ unsigned int : 1; /**< unused */ } bits; #else struct { unsigned int : 1; /**< unused */ unsigned int cleansession : 1; /**< cleansession flag */ unsigned int will : 1; /**< will flag */ unsigned int willQoS : 2; /**< will QoS value */ unsigned int willRetain : 1; /**< will retain setting */ unsigned int password : 1; /**< 3.1 password */ unsigned int username : 1; /**< 3.1 user name */ } bits; #endif } MQTTConnectFlags; /**< connect flags byte */ /** * Defines the MQTT "Last Will and Testament" (LWT) settings for * the connect packet. */ typedef struct { /** The eyecatcher for this structure. must be MQTW. */ char struct_id[4]; /** The version number of this structure. Must be 0 */ int struct_version; /** The LWT topic to which the LWT message will be published. */ MQTTString topicName; /** The LWT payload. */ MQTTString message; /** * The retained flag for the LWT message (see MQTTAsync_message.retained). */ unsigned char retained; /** * The quality of service setting for the LWT message (see * MQTTAsync_message.qos and @ref qos). */ char qos; } MQTTPacket_willOptions; #define MQTTPacket_willOptions_initializer { {'M', 'Q', 'T', 'W'}, 0, {NULL, {0, NULL}}, {NULL, {0, NULL}}, 0, 0 } typedef struct { /** The eyecatcher for this structure. must be MQTC. */ char struct_id[4]; /** The version number of this structure. Must be 0 */ int struct_version; /** Version of MQTT to be used. 3 = 3.1 4 = 3.1.1 */ unsigned char MQTTVersion; MQTTString clientID; unsigned short keepAliveInterval; unsigned char cleansession; unsigned char willFlag; MQTTPacket_willOptions will; MQTTString username; MQTTString password; } MQTTPacket_connectData; typedef union { unsigned char all; /**< all connack flags */ #if defined(REVERSED) struct { unsigned int reserved : 7; /**< unused */ unsigned int sessionpresent : 1; /**< session present flag */ } bits; #else struct { unsigned int sessionpresent : 1; /**< session present flag */ unsigned int reserved: 7; /**< unused */ } bits; #endif } MQTTConnackFlags; /**< connack flags byte */ #define MQTTPacket_connectData_initializer { {'M', 'Q', 'T', 'C'}, 0, 4, {NULL, {0, NULL}}, 60, 1, 0, \ MQTTPacket_willOptions_initializer, {NULL, {0, NULL}}, {NULL, {0, NULL}} } DLLExport int MQTTSerialize_connect(unsigned char* buf, int buflen, MQTTPacket_connectData* options); DLLExport int MQTTDeserialize_connect(MQTTPacket_connectData* data, unsigned char* buf, int len); DLLExport int MQTTSerialize_connack(unsigned char* buf, int buflen, unsigned char connack_rc, unsigned char sessionPresent); DLLExport int MQTTDeserialize_connack(unsigned char* sessionPresent, unsigned char* connack_rc, unsigned char* buf, int buflen); DLLExport int MQTTSerialize_disconnect(unsigned char* buf, int buflen); DLLExport int MQTTSerialize_pingreq(unsigned char* buf, int buflen); #endif /* MQTTCONNECT_H_ */ ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTConnectClient.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation *******************************************************************************/ #include "MQTTPacket.h" #include "StackTrace.h" #include /** * Determines the length of the MQTT connect packet that would be produced using the supplied connect options. * @param options the options to be used to build the connect packet * @return the length of buffer needed to contain the serialized version of the packet */ int MQTTSerialize_connectLength(MQTTPacket_connectData *options) { int len = 0; FUNC_ENTRY; if (options->MQTTVersion == 3) len = 12; /* variable depending on MQTT or MQIsdp */ else if (options->MQTTVersion == 4) len = 10; len += MQTTstrlen(options->clientID) + 2; if (options->willFlag) len += MQTTstrlen(options->will.topicName) + 2 + MQTTstrlen(options->will.message) + 2; if (options->username.cstring || options->username.lenstring.data) len += MQTTstrlen(options->username) + 2; if (options->password.cstring || options->password.lenstring.data) len += MQTTstrlen(options->password) + 2; FUNC_EXIT_RC(len); return len; } /** * Serializes the connect options into the buffer. * @param buf the buffer into which the packet will be serialized * @param len the length in bytes of the supplied buffer * @param options the options to be used to build the connect packet * @return serialized length, or error if 0 */ int MQTTSerialize_connect(unsigned char *buf, int buflen, MQTTPacket_connectData *options) { unsigned char *ptr = buf; MQTTHeader header = {0}; MQTTConnectFlags flags = {0}; int len = 0; int rc = -1; FUNC_ENTRY; if (MQTTPacket_len(len = MQTTSerialize_connectLength(options)) > buflen) { rc = MQTTPACKET_BUFFER_TOO_SHORT; goto exit; } header.byte = 0; header.bits.type = CONNECT; writeChar(&ptr, header.byte); /* write header */ ptr += MQTTPacket_encode(ptr, len); /* write remaining length */ if (options->MQTTVersion == 4) { writeCString(&ptr, "MQTT"); writeChar(&ptr, (char) 4); } else { writeCString(&ptr, "MQIsdp"); writeChar(&ptr, (char) 3); } flags.all = 0; flags.bits.cleansession = options->cleansession; flags.bits.will = (options->willFlag) ? 1 : 0; if (flags.bits.will) { flags.bits.willQoS = options->will.qos; flags.bits.willRetain = options->will.retained; } if (options->username.cstring || options->username.lenstring.data) flags.bits.username = 1; if (options->password.cstring || options->password.lenstring.data) flags.bits.password = 1; writeChar(&ptr, flags.all); writeInt(&ptr, options->keepAliveInterval); writeMQTTString(&ptr, options->clientID); if (options->willFlag) { writeMQTTString(&ptr, options->will.topicName); writeMQTTString(&ptr, options->will.message); } if (flags.bits.username) writeMQTTString(&ptr, options->username); if (flags.bits.password) writeMQTTString(&ptr, options->password); rc = ptr - buf; exit: FUNC_EXIT_RC(rc); return rc; } /** * Deserializes the supplied (wire) buffer into connack data - return code * @param sessionPresent the session present flag returned (only for MQTT 3.1.1) * @param connack_rc returned integer value of the connack return code * @param buf the raw buffer data, of the correct length determined by the remaining length field * @param len the length in bytes of the data in the supplied buffer * @return error code. 1 is success, 0 is failure */ int MQTTDeserialize_connack(unsigned char *sessionPresent, unsigned char *connack_rc, unsigned char *buf, int buflen) { MQTTHeader header = {0}; unsigned char *curdata = buf; unsigned char *enddata = NULL; int rc = 0; int mylen; MQTTConnackFlags flags = {0}; FUNC_ENTRY; header.byte = readChar(&curdata); if (header.bits.type != CONNACK) goto exit; curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ enddata = curdata + mylen; if (enddata - curdata < 2) goto exit; flags.all = readChar(&curdata); *sessionPresent = flags.bits.sessionpresent; *connack_rc = readChar(&curdata); rc = 1; exit: FUNC_EXIT_RC(rc); return rc; } /** * Serializes a 0-length packet into the supplied buffer, ready for writing to a socket * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer, to avoid overruns * @param packettype the message type * @return serialized length, or error if 0 */ int MQTTSerialize_zero(unsigned char *buf, int buflen, unsigned char packettype) { MQTTHeader header = {0}; int rc = -1; unsigned char *ptr = buf; FUNC_ENTRY; if (buflen < 2) { rc = MQTTPACKET_BUFFER_TOO_SHORT; goto exit; } header.byte = 0; header.bits.type = packettype; writeChar(&ptr, header.byte); /* write header */ ptr += MQTTPacket_encode(ptr, 0); /* write remaining length */ rc = ptr - buf; exit: FUNC_EXIT_RC(rc); return rc; } /** * Serializes a disconnect packet into the supplied buffer, ready for writing to a socket * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer, to avoid overruns * @return serialized length, or error if 0 */ int MQTTSerialize_disconnect(unsigned char *buf, int buflen) { return MQTTSerialize_zero(buf, buflen, DISCONNECT); } /** * Serializes a disconnect packet into the supplied buffer, ready for writing to a socket * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer, to avoid overruns * @return serialized length, or error if 0 */ int MQTTSerialize_pingreq(unsigned char *buf, int buflen) { return MQTTSerialize_zero(buf, buflen, PINGREQ); } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTConnectServer.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation *******************************************************************************/ #include "StackTrace.h" #include "MQTTPacket.h" #include #define min(a, b) ((a < b) ? a : b) /** * Validates MQTT protocol name and version combinations * @param protocol the MQTT protocol name as an MQTTString * @param version the MQTT protocol version number, as in the connect packet * @return correct MQTT combination? 1 is true, 0 is false */ int MQTTPacket_checkVersion(MQTTString *protocol, int version) { int rc = 0; if (version == 3 && memcmp(protocol->lenstring.data, "MQIsdp", min(6, protocol->lenstring.len)) == 0) rc = 1; else if (version == 4 && memcmp(protocol->lenstring.data, "MQTT", min(4, protocol->lenstring.len)) == 0) rc = 1; return rc; } /** * Deserializes the supplied (wire) buffer into connect data structure * @param data the connect data structure to be filled out * @param buf the raw buffer data, of the correct length determined by the remaining length field * @param len the length in bytes of the data in the supplied buffer * @return error code. 1 is success, 0 is failure */ int MQTTDeserialize_connect(MQTTPacket_connectData *data, unsigned char *buf, int len) { MQTTHeader header = {0}; MQTTConnectFlags flags = {0}; unsigned char *curdata = buf; unsigned char *enddata = &buf[len]; int rc = 0; MQTTString Protocol; int version; int mylen = 0; FUNC_ENTRY; header.byte = readChar(&curdata); if (header.bits.type != CONNECT) goto exit; curdata += MQTTPacket_decodeBuf(curdata, &mylen); /* read remaining length */ if (!readMQTTLenString(&Protocol, &curdata, enddata) || enddata - curdata < 0) /* do we have enough data to read the protocol version byte? */ goto exit; version = (int)readChar(&curdata); /* Protocol version */ /* If we don't recognize the protocol version, we don't parse the connect packet on the * basis that we don't know what the format will be. */ if (MQTTPacket_checkVersion(&Protocol, version)) { flags.all = readChar(&curdata); data->cleansession = flags.bits.cleansession; data->keepAliveInterval = readInt(&curdata); if (!readMQTTLenString(&data->clientID, &curdata, enddata)) goto exit; data->willFlag = flags.bits.will; if (flags.bits.will) { data->will.qos = flags.bits.willQoS; data->will.retained = flags.bits.willRetain; if (!readMQTTLenString(&data->will.topicName, &curdata, enddata) || !readMQTTLenString(&data->will.message, &curdata, enddata)) goto exit; } if (flags.bits.username) { if (enddata - curdata < 3 || !readMQTTLenString(&data->username, &curdata, enddata)) goto exit; /* username flag set, but no username supplied - invalid */ if (flags.bits.password && (enddata - curdata < 3 || !readMQTTLenString(&data->password, &curdata, enddata))) goto exit; /* password flag set, but no password supplied - invalid */ } else if (flags.bits.password) goto exit; /* password flag set without username - invalid */ rc = 1; } exit: FUNC_EXIT_RC(rc); return rc; } /** * Serializes the connack packet into the supplied buffer. * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer * @param connack_rc the integer connack return code to be used * @param sessionPresent the MQTT 3.1.1 sessionPresent flag * @return serialized length, or error if 0 */ int MQTTSerialize_connack(unsigned char *buf, int buflen, unsigned char connack_rc, unsigned char sessionPresent) { MQTTHeader header = {0}; int rc = 0; unsigned char *ptr = buf; MQTTConnackFlags flags = {0}; FUNC_ENTRY; if (buflen < 2) { rc = MQTTPACKET_BUFFER_TOO_SHORT; goto exit; } header.byte = 0; header.bits.type = CONNACK; writeChar(&ptr, header.byte); /* write header */ ptr += MQTTPacket_encode(ptr, 2); /* write remaining length */ flags.all = 0; flags.bits.sessionpresent = sessionPresent; writeChar(&ptr, flags.all); writeChar(&ptr, connack_rc); rc = ptr - buf; exit: FUNC_EXIT_RC(rc); return rc; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTDeserializePublish.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation *******************************************************************************/ #include "StackTrace.h" #include "MQTTPacket.h" #include #define min(a, b) ((a < b) ? 1 : 0) /** * Deserializes the supplied (wire) buffer into publish data * @param dup returned integer - the MQTT dup flag * @param qos returned integer - the MQTT QoS value * @param retained returned integer - the MQTT retained flag * @param packetid returned integer - the MQTT packet identifier * @param topicName returned MQTTString - the MQTT topic in the publish * @param payload returned byte buffer - the MQTT publish payload * @param payloadlen returned integer - the length of the MQTT payload * @param buf the raw buffer data, of the correct length determined by the remaining length field * @param buflen the length in bytes of the data in the supplied buffer * @return error code. 1 is success */ int MQTTDeserialize_publish(unsigned char *dup, int *qos, unsigned char *retained, unsigned short *packetid, MQTTString *topicName, unsigned char **payload, int *payloadlen, unsigned char *buf, int buflen) { MQTTHeader header = {0}; unsigned char *curdata = buf; unsigned char *enddata = NULL; int rc = 0; int mylen = 0; FUNC_ENTRY; header.byte = readChar(&curdata); if (header.bits.type != PUBLISH) goto exit; *dup = header.bits.dup; *qos = header.bits.qos; *retained = header.bits.retain; curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ enddata = curdata + mylen; if (!readMQTTLenString(topicName, &curdata, enddata) || enddata - curdata < 0) /* do we have enough data to read the protocol version byte? */ goto exit; if (*qos > 0) *packetid = readInt(&curdata); *payloadlen = enddata - curdata; *payload = curdata; rc = 1; exit: FUNC_EXIT_RC(rc); return rc; } /** * Deserializes the supplied (wire) buffer into an ack * @param packettype returned integer - the MQTT packet type * @param dup returned integer - the MQTT dup flag * @param packetid returned integer - the MQTT packet identifier * @param buf the raw buffer data, of the correct length determined by the remaining length field * @param buflen the length in bytes of the data in the supplied buffer * @return error code. 1 is success, 0 is failure */ int MQTTDeserialize_ack(unsigned char *packettype, unsigned char *dup, unsigned short *packetid, unsigned char *buf, int buflen) { MQTTHeader header = {0}; unsigned char *curdata = buf; unsigned char *enddata = NULL; int rc = 0; int mylen; FUNC_ENTRY; header.byte = readChar(&curdata); *dup = header.bits.dup; *packettype = header.bits.type; curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ enddata = curdata + mylen; if (enddata - curdata < 2) goto exit; *packetid = readInt(&curdata); rc = 1; exit: FUNC_EXIT_RC(rc); return rc; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTFormat.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation *******************************************************************************/ #include "StackTrace.h" #include "MQTTPacket.h" #include const char *MQTTPacket_names[] = { "RESERVED", "CONNECT", "CONNACK", "PUBLISH", "PUBACK", "PUBREC", "PUBREL", "PUBCOMP", "SUBSCRIBE", "SUBACK", "UNSUBSCRIBE", "UNSUBACK", "PINGREQ", "PINGRESP", "DISCONNECT" }; const char *MQTTPacket_getName(unsigned short packetid) { return MQTTPacket_names[packetid]; } int MQTTStringFormat_connect(char *strbuf, int strbuflen, MQTTPacket_connectData *data) { int strindex = 0; strindex = snprintf(strbuf, strbuflen, "CONNECT MQTT version %d, client id %.*s, clean session %d, keep alive %d", (int)data->MQTTVersion, data->clientID.lenstring.len, data->clientID.lenstring.data, (int)data->cleansession, data->keepAliveInterval); if (data->willFlag) strindex += snprintf(&strbuf[strindex], strbuflen - strindex, ", will QoS %d, will retain %d, will topic %.*s, will message %.*s", data->will.qos, data->will.retained, data->will.topicName.lenstring.len, data->will.topicName.lenstring.data, data->will.message.lenstring.len, data->will.message.lenstring.data); if (data->username.lenstring.data && data->username.lenstring.len > 0) strindex += snprintf(&strbuf[strindex], strbuflen - strindex, ", user name %.*s", data->username.lenstring.len, data->username.lenstring.data); if (data->password.lenstring.data && data->password.lenstring.len > 0) strindex += snprintf(&strbuf[strindex], strbuflen - strindex, ", password %.*s", data->password.lenstring.len, data->password.lenstring.data); return strindex; } int MQTTStringFormat_connack(char *strbuf, int strbuflen, unsigned char connack_rc, unsigned char sessionPresent) { int strindex = snprintf(strbuf, strbuflen, "CONNACK session present %d, rc %d", sessionPresent, connack_rc); return strindex; } int MQTTStringFormat_publish(char *strbuf, int strbuflen, unsigned char dup, int qos, unsigned char retained, unsigned short packetid, MQTTString topicName, unsigned char *payload, int payloadlen) { int strindex = snprintf(strbuf, strbuflen, "PUBLISH dup %d, QoS %d, retained %d, packet id %d, topic %.*s, payload length %d, payload %.*s", dup, qos, retained, packetid, (topicName.lenstring.len < 20) ? topicName.lenstring.len : 20, topicName.lenstring.data, payloadlen, (payloadlen < 20) ? payloadlen : 20, payload); return strindex; } int MQTTStringFormat_ack(char *strbuf, int strbuflen, unsigned char packettype, unsigned char dup, unsigned short packetid) { int strindex = snprintf(strbuf, strbuflen, "%s, packet id %d", MQTTPacket_names[packettype], packetid); if (dup) strindex += snprintf(strbuf + strindex, strbuflen - strindex, ", dup %d", dup); return strindex; } int MQTTStringFormat_subscribe(char *strbuf, int strbuflen, unsigned char dup, unsigned short packetid, int count, MQTTString topicFilters[], int requestedQoSs[]) { return snprintf(strbuf, strbuflen, "SUBSCRIBE dup %d, packet id %d count %d topic %.*s qos %d", dup, packetid, count, topicFilters[0].lenstring.len, topicFilters[0].lenstring.data, requestedQoSs[0]); } int MQTTStringFormat_suback(char *strbuf, int strbuflen, unsigned short packetid, int count, int *grantedQoSs) { return snprintf(strbuf, strbuflen, "SUBACK packet id %d count %d granted qos %d", packetid, count, grantedQoSs[0]); } int MQTTStringFormat_unsubscribe(char *strbuf, int strbuflen, unsigned char dup, unsigned short packetid, int count, MQTTString topicFilters[]) { return snprintf(strbuf, strbuflen, "UNSUBSCRIBE dup %d, packet id %d count %d topic %.*s", dup, packetid, count, topicFilters[0].lenstring.len, topicFilters[0].lenstring.data); } #if defined(MQTT_CLIENT) char *MQTTFormat_toClientString(char *strbuf, int strbuflen, unsigned char *buf, int buflen) { int index = 0; int rem_length = 0; MQTTHeader header = {0}; int strindex = 0; header.byte = buf[index++]; index += MQTTPacket_decodeBuf(&buf[index], &rem_length); switch (header.bits.type) { case CONNACK: { unsigned char sessionPresent, connack_rc; if (MQTTDeserialize_connack(&sessionPresent, &connack_rc, buf, buflen) == 1) strindex = MQTTStringFormat_connack(strbuf, strbuflen, connack_rc, sessionPresent); } break; case PUBLISH: { unsigned char dup, retained, *payload; unsigned short packetid; int qos, payloadlen; MQTTString topicName = MQTTString_initializer; if (MQTTDeserialize_publish(&dup, &qos, &retained, &packetid, &topicName, &payload, &payloadlen, buf, buflen) == 1) strindex = MQTTStringFormat_publish(strbuf, strbuflen, dup, qos, retained, packetid, topicName, payload, payloadlen); } break; case PUBACK: case PUBREC: case PUBREL: case PUBCOMP: { unsigned char packettype, dup; unsigned short packetid; if (MQTTDeserialize_ack(&packettype, &dup, &packetid, buf, buflen) == 1) strindex = MQTTStringFormat_ack(strbuf, strbuflen, packettype, dup, packetid); } break; case SUBACK: { unsigned short packetid; int maxcount = 1, count = 0; int grantedQoSs[1]; if (MQTTDeserialize_suback(&packetid, maxcount, &count, grantedQoSs, buf, buflen) == 1) strindex = MQTTStringFormat_suback(strbuf, strbuflen, packetid, count, grantedQoSs); } break; case UNSUBACK: { unsigned short packetid; if (MQTTDeserialize_unsuback(&packetid, buf, buflen) == 1) strindex = MQTTStringFormat_ack(strbuf, strbuflen, UNSUBACK, 0, packetid); } break; case PINGREQ: case PINGRESP: case DISCONNECT: strindex = snprintf(strbuf, strbuflen, "%s", MQTTPacket_names[header.bits.type]); break; } return strbuf; } #endif #if defined(MQTT_SERVER) char *MQTTFormat_toServerString(char *strbuf, int strbuflen, unsigned char *buf, int buflen) { int index = 0; int rem_length = 0; MQTTHeader header = {0}; int strindex = 0; header.byte = buf[index++]; index += MQTTPacket_decodeBuf(&buf[index], &rem_length); switch (header.bits.type) { case CONNECT: { MQTTPacket_connectData data; int rc; if ((rc = MQTTDeserialize_connect(&data, buf, buflen)) == 1) strindex = MQTTStringFormat_connect(strbuf, strbuflen, &data); } break; case PUBLISH: { unsigned char dup, retained, *payload; unsigned short packetid; int qos, payloadlen; MQTTString topicName = MQTTString_initializer; if (MQTTDeserialize_publish(&dup, &qos, &retained, &packetid, &topicName, &payload, &payloadlen, buf, buflen) == 1) strindex = MQTTStringFormat_publish(strbuf, strbuflen, dup, qos, retained, packetid, topicName, payload, payloadlen); } break; case PUBACK: case PUBREC: case PUBREL: case PUBCOMP: { unsigned char packettype, dup; unsigned short packetid; if (MQTTDeserialize_ack(&packettype, &dup, &packetid, buf, buflen) == 1) strindex = MQTTStringFormat_ack(strbuf, strbuflen, packettype, dup, packetid); } break; case SUBSCRIBE: { unsigned char dup; unsigned short packetid; int maxcount = 1, count = 0; MQTTString topicFilters[1]; int requestedQoSs[1]; if (MQTTDeserialize_subscribe(&dup, &packetid, maxcount, &count, topicFilters, requestedQoSs, buf, buflen) == 1) strindex = MQTTStringFormat_subscribe(strbuf, strbuflen, dup, packetid, count, topicFilters, requestedQoSs);; } break; case UNSUBSCRIBE: { unsigned char dup; unsigned short packetid; int maxcount = 1, count = 0; MQTTString topicFilters[1]; if (MQTTDeserialize_unsubscribe(&dup, &packetid, maxcount, &count, topicFilters, buf, buflen) == 1) strindex = MQTTStringFormat_unsubscribe(strbuf, strbuflen, dup, packetid, count, topicFilters); } break; case PINGREQ: case PINGRESP: case DISCONNECT: strindex = snprintf(strbuf, strbuflen, "%s", MQTTPacket_names[header.bits.type]); break; } strbuf[strbuflen] = '\0'; return strbuf; } #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTFormat.h ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation *******************************************************************************/ #if !defined(MQTTFORMAT_H) #define MQTTFORMAT_H #include "StackTrace.h" #include "MQTTPacket.h" const char* MQTTPacket_getName(unsigned short packetid); int MQTTStringFormat_connect(char* strbuf, int strbuflen, MQTTPacket_connectData* data); int MQTTStringFormat_connack(char* strbuf, int strbuflen, unsigned char connack_rc, unsigned char sessionPresent); int MQTTStringFormat_publish(char* strbuf, int strbuflen, unsigned char dup, int qos, unsigned char retained, unsigned short packetid, MQTTString topicName, unsigned char* payload, int payloadlen); int MQTTStringFormat_ack(char* strbuf, int strbuflen, unsigned char packettype, unsigned char dup, unsigned short packetid); int MQTTStringFormat_subscribe(char* strbuf, int strbuflen, unsigned char dup, unsigned short packetid, int count, MQTTString topicFilters[], int requestedQoSs[]); int MQTTStringFormat_suback(char* strbuf, int strbuflen, unsigned short packetid, int count, int* grantedQoSs); int MQTTStringFormat_unsubscribe(char* strbuf, int strbuflen, unsigned char dup, unsigned short packetid, int count, MQTTString topicFilters[]); char* MQTTFormat_toClientString(char* strbuf, int strbuflen, unsigned char* buf, int buflen); char* MQTTFormat_toServerString(char* strbuf, int strbuflen, unsigned char* buf, int buflen); #endif ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTPacket.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Sergio R. Caprile - non-blocking packet read functions for stream transport *******************************************************************************/ #include "StackTrace.h" #include "MQTTPacket.h" #include /** * Encodes the message length according to the MQTT algorithm * @param buf the buffer into which the encoded data is written * @param length the length to be encoded * @return the number of bytes written to buffer */ int MQTTPacket_encode(unsigned char *buf, int length) { int rc = 0; FUNC_ENTRY; do { char d = length % 128; length /= 128; /* if there are more digits to encode, set the top bit of this digit */ if (length > 0) d |= 0x80; buf[rc++] = d; } while (length > 0); FUNC_EXIT_RC(rc); return rc; } /** * Decodes the message length according to the MQTT algorithm * @param getcharfn pointer to function to read the next character from the data source * @param value the decoded length returned * @return the number of bytes read from the socket */ int MQTTPacket_decode(int (*getcharfn)(unsigned char *, int), int *value) { unsigned char c; int multiplier = 1; int len = 0; #define MAX_NO_OF_REMAINING_LENGTH_BYTES 4 FUNC_ENTRY; *value = 0; do { int rc = MQTTPACKET_READ_ERROR; if (++len > MAX_NO_OF_REMAINING_LENGTH_BYTES) { rc = MQTTPACKET_READ_ERROR; /* bad data */ goto exit; } rc = (*getcharfn)(&c, 1); if (rc != 1) goto exit; *value += (c & 127) * multiplier; multiplier *= 128; } while ((c & 128) != 0); exit: FUNC_EXIT_RC(len); return len; } int MQTTPacket_len(int rem_len) { rem_len += 1; /* header byte */ /* now remaining_length field */ if (rem_len < 128) rem_len += 1; else if (rem_len < 16384) rem_len += 2; else if (rem_len < 2097151) rem_len += 3; else rem_len += 4; return rem_len; } static unsigned char *bufptr; int bufchar(unsigned char *c, int count) { int i; for (i = 0; i < count; ++i) *c = *bufptr++; return count; } int MQTTPacket_decodeBuf(unsigned char *buf, int *value) { bufptr = buf; return MQTTPacket_decode(bufchar, value); } /** * Calculates an integer from two bytes read from the input buffer * @param pptr pointer to the input buffer - incremented by the number of bytes used & returned * @return the integer value calculated */ int readInt(unsigned char **pptr) { unsigned char *ptr = *pptr; int len = 256 * (*ptr) + (*(ptr + 1)); *pptr += 2; return len; } /** * Reads one character from the input buffer. * @param pptr pointer to the input buffer - incremented by the number of bytes used & returned * @return the character read */ char readChar(unsigned char **pptr) { char c = **pptr; (*pptr)++; return c; } /** * Writes one character to an output buffer. * @param pptr pointer to the output buffer - incremented by the number of bytes used & returned * @param c the character to write */ void writeChar(unsigned char **pptr, char c) { **pptr = c; (*pptr)++; } /** * Writes an integer as 2 bytes to an output buffer. * @param pptr pointer to the output buffer - incremented by the number of bytes used & returned * @param anInt the integer to write */ void writeInt(unsigned char **pptr, int anInt) { **pptr = (unsigned char)(anInt / 256); (*pptr)++; **pptr = (unsigned char)(anInt % 256); (*pptr)++; } /** * Writes a "UTF" string to an output buffer. Converts C string to length-delimited. * @param pptr pointer to the output buffer - incremented by the number of bytes used & returned * @param string the C string to write */ void writeCString(unsigned char **pptr, const char *string) { int len = strlen(string); writeInt(pptr, len); memcpy(*pptr, string, len); *pptr += len; } int getLenStringLen(char *ptr) { int len = 256 * ((unsigned char)(*ptr)) + (unsigned char)(*(ptr + 1)); return len; } void writeMQTTString(unsigned char **pptr, MQTTString mqttstring) { if (mqttstring.lenstring.len > 0) { writeInt(pptr, mqttstring.lenstring.len); memcpy(*pptr, mqttstring.lenstring.data, mqttstring.lenstring.len); *pptr += mqttstring.lenstring.len; } else if (mqttstring.cstring) writeCString(pptr, mqttstring.cstring); else writeInt(pptr, 0); } /** * @param mqttstring the MQTTString structure into which the data is to be read * @param pptr pointer to the output buffer - incremented by the number of bytes used & returned * @param enddata pointer to the end of the data: do not read beyond * @return 1 if successful, 0 if not */ int readMQTTLenString(MQTTString *mqttstring, unsigned char **pptr, unsigned char *enddata) { int rc = 0; FUNC_ENTRY; /* the first two bytes are the length of the string */ if (enddata - (*pptr) > 1) /* enough length to read the integer? */ { mqttstring->lenstring.len = readInt(pptr); /* increments pptr to point past length */ if (&(*pptr)[mqttstring->lenstring.len] <= enddata) { mqttstring->lenstring.data = (char *)*pptr; *pptr += mqttstring->lenstring.len; rc = 1; } } mqttstring->cstring = NULL; FUNC_EXIT_RC(rc); return rc; } /** * Return the length of the MQTTstring - C string if there is one, otherwise the length delimited string * @param mqttstring the string to return the length of * @return the length of the string */ int MQTTstrlen(MQTTString mqttstring) { int rc = 0; if (mqttstring.cstring) rc = strlen(mqttstring.cstring); else rc = mqttstring.lenstring.len; return rc; } /** * Compares an MQTTString to a C string * @param a the MQTTString to compare * @param bptr the C string to compare * @return boolean - equal or not */ int MQTTPacket_equals(MQTTString *a, char *bptr) { int alen = 0, blen = 0; char *aptr; if (a->cstring) { aptr = a->cstring; alen = strlen(a->cstring); } else { aptr = a->lenstring.data; alen = a->lenstring.len; } blen = strlen(bptr); return (alen == blen) && (strncmp(aptr, bptr, alen) == 0); } /** * Helper function to read packet data from some source into a buffer * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer * @param getfn pointer to a function which will read any number of bytes from the needed source * @return integer MQTT packet type, or -1 on error * @note the whole message must fit into the caller's buffer */ int MQTTPacket_read(unsigned char *buf, int buflen, int (*getfn)(unsigned char *, int)) { int rc = -1; MQTTHeader header = {0}; int len = 0; int rem_len = 0; /* 1. read the header byte. This has the packet type in it */ if ((*getfn)(buf, 1) != 1) goto exit; len = 1; /* 2. read the remaining length. This is variable in itself */ MQTTPacket_decode(getfn, &rem_len); len += MQTTPacket_encode(buf + 1, rem_len); /* put the original remaining length back into the buffer */ /* 3. read the rest of the buffer using a callback to supply the rest of the data */ if((rem_len + len) > buflen) goto exit; if (rem_len && ((*getfn)(buf + len, rem_len) != rem_len)) goto exit; header.byte = buf[0]; rc = header.bits.type; exit: return rc; } /** * Decodes the message length according to the MQTT algorithm, non-blocking * @param trp pointer to a transport structure holding what is needed to solve getting data from it * @param value the decoded length returned * @return integer the number of bytes read from the socket, 0 for call again, or -1 on error */ static int MQTTPacket_decodenb(MQTTTransport *trp) { unsigned char c; int rc = MQTTPACKET_READ_ERROR; FUNC_ENTRY; if(trp->len == 0) /* initialize on first call */ { trp->multiplier = 1; trp->rem_len = 0; } do { int frc; if (trp->len >= MAX_NO_OF_REMAINING_LENGTH_BYTES) goto exit; if ((frc = (*trp->getfn)(trp->sck, &c, 1)) == -1) goto exit; if (frc == 0) { rc = 0; goto exit; } ++(trp->len); trp->rem_len += (c & 127) * trp->multiplier; trp->multiplier *= 128; } while ((c & 128) != 0); rc = trp->len; exit: FUNC_EXIT_RC(rc); return rc; } /** * Helper function to read packet data from some source into a buffer, non-blocking * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer * @param trp pointer to a transport structure holding what is needed to solve getting data from it * @return integer MQTT packet type, 0 for call again, or -1 on error * @note the whole message must fit into the caller's buffer */ int MQTTPacket_readnb(unsigned char *buf, int buflen, MQTTTransport *trp) { int rc = -1, frc; MQTTHeader header = {0}; switch(trp->state) { default: trp->state = 0; /*FALLTHROUGH*/ case 0: /* read the header byte. This has the packet type in it */ if ((frc = (*trp->getfn)(trp->sck, buf, 1)) == -1) goto exit; if (frc == 0) return 0; trp->len = 0; ++trp->state; /*FALLTHROUGH*/ /* read the remaining length. This is variable in itself */ case 1: if((frc = MQTTPacket_decodenb(trp)) == MQTTPACKET_READ_ERROR) goto exit; if(frc == 0) return 0; trp->len = 1 + MQTTPacket_encode(buf + 1, trp->rem_len); /* put the original remaining length back into the buffer */ if((trp->rem_len + trp->len) > buflen) goto exit; ++trp->state; /*FALLTHROUGH*/ case 2: if(trp->rem_len) { /* read the rest of the buffer using a callback to supply the rest of the data */ if ((frc = (*trp->getfn)(trp->sck, buf + trp->len, trp->rem_len)) == -1) goto exit; if (frc == 0) return 0; trp->rem_len -= frc; trp->len += frc; if(trp->rem_len) return 0; } header.byte = buf[0]; rc = header.bits.type; break; } exit: trp->state = 0; return rc; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTPacket.h ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Xiang Rong - 442039 Add makefile to Embedded C client *******************************************************************************/ #ifndef MQTTPACKET_H_ #define MQTTPACKET_H_ #if defined(__cplusplus) /* If this is a C++ compiler, use C linkage */ extern "C" { #endif #if defined(WIN32_DLL) || defined(WIN64_DLL) #define DLLImport __declspec(dllimport) #define DLLExport __declspec(dllexport) #elif defined(LINUX_SO) #define DLLImport extern #define DLLExport __attribute__ ((visibility ("default"))) #else #define DLLImport #define DLLExport #endif enum errors { MQTTPACKET_BUFFER_TOO_SHORT = -2, MQTTPACKET_READ_ERROR = -1, MQTTPACKET_READ_COMPLETE }; enum msgTypes { CONNECT = 1, CONNACK, PUBLISH, PUBACK, PUBREC, PUBREL, PUBCOMP, SUBSCRIBE, SUBACK, UNSUBSCRIBE, UNSUBACK, PINGREQ, PINGRESP, DISCONNECT }; /** * Bitfields for the MQTT header byte. */ typedef union { unsigned char byte; /**< the whole byte */ #if defined(REVERSED) struct { unsigned int type : 4; /**< message type nibble */ unsigned int dup : 1; /**< DUP flag bit */ unsigned int qos : 2; /**< QoS value, 0, 1 or 2 */ unsigned int retain : 1; /**< retained flag bit */ } bits; #else struct { unsigned int retain : 1; /**< retained flag bit */ unsigned int qos : 2; /**< QoS value, 0, 1 or 2 */ unsigned int dup : 1; /**< DUP flag bit */ unsigned int type : 4; /**< message type nibble */ } bits; #endif } MQTTHeader; typedef struct { int len; char* data; } MQTTLenString; typedef struct { char* cstring; MQTTLenString lenstring; } MQTTString; #define MQTTString_initializer {NULL, {0, NULL}} int MQTTstrlen(MQTTString mqttstring); #include "MQTTConnect.h" #include "MQTTPublish.h" #include "MQTTSubscribe.h" #include "MQTTUnsubscribe.h" #include "MQTTFormat.h" DLLExport int MQTTSerialize_ack(unsigned char* buf, int buflen, unsigned char type, unsigned char dup, unsigned short packetid); DLLExport int MQTTDeserialize_ack(unsigned char* packettype, unsigned char* dup, unsigned short* packetid, unsigned char* buf, int buflen); int MQTTPacket_len(int rem_len); DLLExport int MQTTPacket_equals(MQTTString* a, char* b); DLLExport int MQTTPacket_encode(unsigned char* buf, int length); int MQTTPacket_decode(int (*getcharfn)(unsigned char*, int), int* value); int MQTTPacket_decodeBuf(unsigned char* buf, int* value); int readInt(unsigned char** pptr); char readChar(unsigned char** pptr); void writeChar(unsigned char** pptr, char c); void writeInt(unsigned char** pptr, int anInt); int readMQTTLenString(MQTTString* mqttstring, unsigned char** pptr, unsigned char* enddata); void writeCString(unsigned char** pptr, const char* string); void writeMQTTString(unsigned char** pptr, MQTTString mqttstring); DLLExport int MQTTPacket_read(unsigned char* buf, int buflen, int (*getfn)(unsigned char*, int)); typedef struct { int (*getfn)(void *, unsigned char*, int); /* must return -1 for error, 0 for call again, or the number of bytes read */ void *sck; /* pointer to whatever the system may use to identify the transport */ int multiplier; int rem_len; int len; char state; }MQTTTransport; int MQTTPacket_readnb(unsigned char* buf, int buflen, MQTTTransport *trp); #ifdef __cplusplus /* If this is a C++ compiler, use C linkage */ } #endif #endif /* MQTTPACKET_H_ */ ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTPublish.h ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Xiang Rong - 442039 Add makefile to Embedded C client *******************************************************************************/ #ifndef MQTTPUBLISH_H_ #define MQTTPUBLISH_H_ #if !defined(DLLImport) #define DLLImport #endif #if !defined(DLLExport) #define DLLExport #endif DLLExport int MQTTSerialize_publish(unsigned char* buf, int buflen, unsigned char dup, int qos, unsigned char retained, unsigned short packetid, MQTTString topicName, unsigned char* payload, int payloadlen); DLLExport int MQTTDeserialize_publish(unsigned char* dup, int* qos, unsigned char* retained, unsigned short* packetid, MQTTString* topicName, unsigned char** payload, int* payloadlen, unsigned char* buf, int len); DLLExport int MQTTSerialize_puback(unsigned char* buf, int buflen, unsigned short packetid); DLLExport int MQTTSerialize_pubrel(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid); DLLExport int MQTTSerialize_pubcomp(unsigned char* buf, int buflen, unsigned short packetid); #endif /* MQTTPUBLISH_H_ */ ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTSerializePublish.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Ian Craggs - fix for https://bugs.eclipse.org/bugs/show_bug.cgi?id=453144 *******************************************************************************/ #include "MQTTPacket.h" #include "StackTrace.h" #include /** * Determines the length of the MQTT publish packet that would be produced using the supplied parameters * @param qos the MQTT QoS of the publish (packetid is omitted for QoS 0) * @param topicName the topic name to be used in the publish * @param payloadlen the length of the payload to be sent * @return the length of buffer needed to contain the serialized version of the packet */ int MQTTSerialize_publishLength(int qos, MQTTString topicName, int payloadlen) { int len = 0; len += 2 + MQTTstrlen(topicName) + payloadlen; if (qos > 0) len += 2; /* packetid */ return len; } /** * Serializes the supplied publish data into the supplied buffer, ready for sending * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer * @param dup integer - the MQTT dup flag * @param qos integer - the MQTT QoS value * @param retained integer - the MQTT retained flag * @param packetid integer - the MQTT packet identifier * @param topicName MQTTString - the MQTT topic in the publish * @param payload byte buffer - the MQTT publish payload * @param payloadlen integer - the length of the MQTT payload * @return the length of the serialized data. <= 0 indicates error */ int MQTTSerialize_publish(unsigned char *buf, int buflen, unsigned char dup, int qos, unsigned char retained, unsigned short packetid, MQTTString topicName, unsigned char *payload, int payloadlen) { unsigned char *ptr = buf; MQTTHeader header = {0}; int rem_len = 0; int rc = 0; FUNC_ENTRY; if (MQTTPacket_len(rem_len = MQTTSerialize_publishLength(qos, topicName, payloadlen)) > buflen) { rc = MQTTPACKET_BUFFER_TOO_SHORT; goto exit; } header.bits.type = PUBLISH; header.bits.dup = dup; header.bits.qos = qos; header.bits.retain = retained; writeChar(&ptr, header.byte); /* write header */ ptr += MQTTPacket_encode(ptr, rem_len); /* write remaining length */; writeMQTTString(&ptr, topicName); if (qos > 0) writeInt(&ptr, packetid); memcpy(ptr, payload, payloadlen); ptr += payloadlen; rc = ptr - buf; exit: FUNC_EXIT_RC(rc); return rc; } /** * Serializes the ack packet into the supplied buffer. * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer * @param type the MQTT packet type * @param dup the MQTT dup flag * @param packetid the MQTT packet identifier * @return serialized length, or error if 0 */ int MQTTSerialize_ack(unsigned char *buf, int buflen, unsigned char packettype, unsigned char dup, unsigned short packetid) { MQTTHeader header = {0}; int rc = 0; unsigned char *ptr = buf; FUNC_ENTRY; if (buflen < 4) { rc = MQTTPACKET_BUFFER_TOO_SHORT; goto exit; } header.bits.type = packettype; header.bits.dup = dup; header.bits.qos = (packettype == PUBREL) ? 1 : 0; writeChar(&ptr, header.byte); /* write header */ ptr += MQTTPacket_encode(ptr, 2); /* write remaining length */ writeInt(&ptr, packetid); rc = ptr - buf; exit: FUNC_EXIT_RC(rc); return rc; } /** * Serializes a puback packet into the supplied buffer. * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer * @param packetid integer - the MQTT packet identifier * @return serialized length, or error if 0 */ int MQTTSerialize_puback(unsigned char *buf, int buflen, unsigned short packetid) { return MQTTSerialize_ack(buf, buflen, PUBACK, 0, packetid); } /** * Serializes a pubrel packet into the supplied buffer. * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer * @param dup integer - the MQTT dup flag * @param packetid integer - the MQTT packet identifier * @return serialized length, or error if 0 */ int MQTTSerialize_pubrel(unsigned char *buf, int buflen, unsigned char dup, unsigned short packetid) { return MQTTSerialize_ack(buf, buflen, PUBREL, dup, packetid); } /** * Serializes a pubrel packet into the supplied buffer. * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer * @param packetid integer - the MQTT packet identifier * @return serialized length, or error if 0 */ int MQTTSerialize_pubcomp(unsigned char *buf, int buflen, unsigned short packetid) { return MQTTSerialize_ack(buf, buflen, PUBCOMP, 0, packetid); } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTSubscribe.h ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Xiang Rong - 442039 Add makefile to Embedded C client *******************************************************************************/ #ifndef MQTTSUBSCRIBE_H_ #define MQTTSUBSCRIBE_H_ #if !defined(DLLImport) #define DLLImport #endif #if !defined(DLLExport) #define DLLExport #endif DLLExport int MQTTSerialize_subscribe(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid, int count, MQTTString topicFilters[], int requestedQoSs[]); DLLExport int MQTTDeserialize_subscribe(unsigned char* dup, unsigned short* packetid, int maxcount, int* count, MQTTString topicFilters[], int requestedQoSs[], unsigned char* buf, int len); DLLExport int MQTTSerialize_suback(unsigned char* buf, int buflen, unsigned short packetid, int count, int* grantedQoSs); DLLExport int MQTTDeserialize_suback(unsigned short* packetid, int maxcount, int* count, int grantedQoSs[], unsigned char* buf, int len); #endif /* MQTTSUBSCRIBE_H_ */ ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTSubscribeClient.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation *******************************************************************************/ #include "MQTTPacket.h" #include "StackTrace.h" #include /** * Determines the length of the MQTT subscribe packet that would be produced using the supplied parameters * @param count the number of topic filter strings in topicFilters * @param topicFilters the array of topic filter strings to be used in the publish * @return the length of buffer needed to contain the serialized version of the packet */ int MQTTSerialize_subscribeLength(int count, MQTTString topicFilters[]) { int i; int len = 2; /* packetid */ for (i = 0; i < count; ++i) len += 2 + MQTTstrlen(topicFilters[i]) + 1; /* length + topic + req_qos */ return len; } /** * Serializes the supplied subscribe data into the supplied buffer, ready for sending * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied bufferr * @param dup integer - the MQTT dup flag * @param packetid integer - the MQTT packet identifier * @param count - number of members in the topicFilters and reqQos arrays * @param topicFilters - array of topic filter names * @param requestedQoSs - array of requested QoS * @return the length of the serialized data. <= 0 indicates error */ int MQTTSerialize_subscribe(unsigned char *buf, int buflen, unsigned char dup, unsigned short packetid, int count, MQTTString topicFilters[], int requestedQoSs[]) { unsigned char *ptr = buf; MQTTHeader header = {0}; int rem_len = 0; int rc = 0; int i = 0; FUNC_ENTRY; if (MQTTPacket_len(rem_len = MQTTSerialize_subscribeLength(count, topicFilters)) > buflen) { rc = MQTTPACKET_BUFFER_TOO_SHORT; goto exit; } header.byte = 0; header.bits.type = SUBSCRIBE; header.bits.dup = dup; header.bits.qos = 1; writeChar(&ptr, header.byte); /* write header */ ptr += MQTTPacket_encode(ptr, rem_len); /* write remaining length */; writeInt(&ptr, packetid); for (i = 0; i < count; ++i) { writeMQTTString(&ptr, topicFilters[i]); writeChar(&ptr, requestedQoSs[i]); } rc = ptr - buf; exit: FUNC_EXIT_RC(rc); return rc; } /** * Deserializes the supplied (wire) buffer into suback data * @param packetid returned integer - the MQTT packet identifier * @param maxcount - the maximum number of members allowed in the grantedQoSs array * @param count returned integer - number of members in the grantedQoSs array * @param grantedQoSs returned array of integers - the granted qualities of service * @param buf the raw buffer data, of the correct length determined by the remaining length field * @param buflen the length in bytes of the data in the supplied buffer * @return error code. 1 is success, 0 is failure */ int MQTTDeserialize_suback(unsigned short *packetid, int maxcount, int *count, int grantedQoSs[], unsigned char *buf, int buflen) { MQTTHeader header = {0}; unsigned char *curdata = buf; unsigned char *enddata = NULL; int rc = 0; int mylen; FUNC_ENTRY; header.byte = readChar(&curdata); if (header.bits.type != SUBACK) goto exit; curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ enddata = curdata + mylen; if (enddata - curdata < 2) goto exit; *packetid = readInt(&curdata); *count = 0; while (curdata < enddata) { if (*count > maxcount) { rc = -1; goto exit; } grantedQoSs[(*count)++] = readChar(&curdata); } rc = 1; exit: FUNC_EXIT_RC(rc); return rc; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTSubscribeServer.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation *******************************************************************************/ #include "MQTTPacket.h" #include "StackTrace.h" #include /** * Deserializes the supplied (wire) buffer into subscribe data * @param dup integer returned - the MQTT dup flag * @param packetid integer returned - the MQTT packet identifier * @param maxcount - the maximum number of members allowed in the topicFilters and requestedQoSs arrays * @param count - number of members in the topicFilters and requestedQoSs arrays * @param topicFilters - array of topic filter names * @param requestedQoSs - array of requested QoS * @param buf the raw buffer data, of the correct length determined by the remaining length field * @param buflen the length in bytes of the data in the supplied buffer * @return the length of the serialized data. <= 0 indicates error */ int MQTTDeserialize_subscribe(unsigned char *dup, unsigned short *packetid, int maxcount, int *count, MQTTString topicFilters[], int requestedQoSs[], unsigned char *buf, int buflen) { MQTTHeader header = {0}; unsigned char *curdata = buf; unsigned char *enddata = NULL; int rc = -1; int mylen = 0; FUNC_ENTRY; header.byte = readChar(&curdata); if (header.bits.type != SUBSCRIBE) goto exit; *dup = header.bits.dup; curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ enddata = curdata + mylen; *packetid = readInt(&curdata); *count = 0; while (curdata < enddata) { if (!readMQTTLenString(&topicFilters[*count], &curdata, enddata)) goto exit; if (curdata >= enddata) /* do we have enough data to read the req_qos version byte? */ goto exit; requestedQoSs[*count] = readChar(&curdata); (*count)++; } rc = 1; exit: FUNC_EXIT_RC(rc); return rc; } /** * Serializes the supplied suback data into the supplied buffer, ready for sending * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer * @param packetid integer - the MQTT packet identifier * @param count - number of members in the grantedQoSs array * @param grantedQoSs - array of granted QoS * @return the length of the serialized data. <= 0 indicates error */ int MQTTSerialize_suback(unsigned char *buf, int buflen, unsigned short packetid, int count, int *grantedQoSs) { MQTTHeader header = {0}; int rc = -1; unsigned char *ptr = buf; int i; FUNC_ENTRY; if (buflen < 2 + count) { rc = MQTTPACKET_BUFFER_TOO_SHORT; goto exit; } header.byte = 0; header.bits.type = SUBACK; writeChar(&ptr, header.byte); /* write header */ ptr += MQTTPacket_encode(ptr, 2 + count); /* write remaining length */ writeInt(&ptr, packetid); for (i = 0; i < count; ++i) writeChar(&ptr, grantedQoSs[i]); rc = ptr - buf; exit: FUNC_EXIT_RC(rc); return rc; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTUnsubscribe.h ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Xiang Rong - 442039 Add makefile to Embedded C client *******************************************************************************/ #ifndef MQTTUNSUBSCRIBE_H_ #define MQTTUNSUBSCRIBE_H_ #if !defined(DLLImport) #define DLLImport #endif #if !defined(DLLExport) #define DLLExport #endif DLLExport int MQTTSerialize_unsubscribe(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid, int count, MQTTString topicFilters[]); DLLExport int MQTTDeserialize_unsubscribe(unsigned char* dup, unsigned short* packetid, int max_count, int* count, MQTTString topicFilters[], unsigned char* buf, int len); DLLExport int MQTTSerialize_unsuback(unsigned char* buf, int buflen, unsigned short packetid); DLLExport int MQTTDeserialize_unsuback(unsigned short* packetid, unsigned char* buf, int len); #endif /* MQTTUNSUBSCRIBE_H_ */ ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTUnsubscribeClient.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation *******************************************************************************/ #include "MQTTPacket.h" #include "StackTrace.h" #include /** * Determines the length of the MQTT unsubscribe packet that would be produced using the supplied parameters * @param count the number of topic filter strings in topicFilters * @param topicFilters the array of topic filter strings to be used in the publish * @return the length of buffer needed to contain the serialized version of the packet */ int MQTTSerialize_unsubscribeLength(int count, MQTTString topicFilters[]) { int i; int len = 2; /* packetid */ for (i = 0; i < count; ++i) len += 2 + MQTTstrlen(topicFilters[i]); /* length + topic*/ return len; } /** * Serializes the supplied unsubscribe data into the supplied buffer, ready for sending * @param buf the raw buffer data, of the correct length determined by the remaining length field * @param buflen the length in bytes of the data in the supplied buffer * @param dup integer - the MQTT dup flag * @param packetid integer - the MQTT packet identifier * @param count - number of members in the topicFilters array * @param topicFilters - array of topic filter names * @return the length of the serialized data. <= 0 indicates error */ int MQTTSerialize_unsubscribe(unsigned char *buf, int buflen, unsigned char dup, unsigned short packetid, int count, MQTTString topicFilters[]) { unsigned char *ptr = buf; MQTTHeader header = {0}; int rem_len = 0; int rc = -1; int i = 0; FUNC_ENTRY; if (MQTTPacket_len(rem_len = MQTTSerialize_unsubscribeLength(count, topicFilters)) > buflen) { rc = MQTTPACKET_BUFFER_TOO_SHORT; goto exit; } header.byte = 0; header.bits.type = UNSUBSCRIBE; header.bits.dup = dup; header.bits.qos = 1; writeChar(&ptr, header.byte); /* write header */ ptr += MQTTPacket_encode(ptr, rem_len); /* write remaining length */; writeInt(&ptr, packetid); for (i = 0; i < count; ++i) writeMQTTString(&ptr, topicFilters[i]); rc = ptr - buf; exit: FUNC_EXIT_RC(rc); return rc; } /** * Deserializes the supplied (wire) buffer into unsuback data * @param packetid returned integer - the MQTT packet identifier * @param buf the raw buffer data, of the correct length determined by the remaining length field * @param buflen the length in bytes of the data in the supplied buffer * @return error code. 1 is success, 0 is failure */ int MQTTDeserialize_unsuback(unsigned short *packetid, unsigned char *buf, int buflen) { unsigned char type = 0; unsigned char dup = 0; int rc = 0; FUNC_ENTRY; rc = MQTTDeserialize_ack(&type, &dup, packetid, buf, buflen); if (type == UNSUBACK) rc = 1; FUNC_EXIT_RC(rc); return rc; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/MQTTUnsubscribeServer.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation *******************************************************************************/ #include "MQTTPacket.h" #include "StackTrace.h" #include /** * Deserializes the supplied (wire) buffer into unsubscribe data * @param dup integer returned - the MQTT dup flag * @param packetid integer returned - the MQTT packet identifier * @param maxcount - the maximum number of members allowed in the topicFilters and requestedQoSs arrays * @param count - number of members in the topicFilters and requestedQoSs arrays * @param topicFilters - array of topic filter names * @param buf the raw buffer data, of the correct length determined by the remaining length field * @param buflen the length in bytes of the data in the supplied buffer * @return the length of the serialized data. <= 0 indicates error */ int MQTTDeserialize_unsubscribe(unsigned char *dup, unsigned short *packetid, int maxcount, int *count, MQTTString topicFilters[], unsigned char *buf, int len) { MQTTHeader header = {0}; unsigned char *curdata = buf; unsigned char *enddata = NULL; int rc = 0; int mylen = 0; FUNC_ENTRY; header.byte = readChar(&curdata); if (header.bits.type != UNSUBSCRIBE) goto exit; *dup = header.bits.dup; curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ enddata = curdata + mylen; *packetid = readInt(&curdata); *count = 0; while (curdata < enddata) { if (!readMQTTLenString(&topicFilters[*count], &curdata, enddata)) goto exit; (*count)++; } rc = 1; exit: FUNC_EXIT_RC(rc); return rc; } /** * Serializes the supplied unsuback data into the supplied buffer, ready for sending * @param buf the buffer into which the packet will be serialized * @param buflen the length in bytes of the supplied buffer * @param packetid integer - the MQTT packet identifier * @return the length of the serialized data. <= 0 indicates error */ int MQTTSerialize_unsuback(unsigned char *buf, int buflen, unsigned short packetid) { MQTTHeader header = {0}; int rc = 0; unsigned char *ptr = buf; FUNC_ENTRY; if (buflen < 2) { rc = MQTTPACKET_BUFFER_TOO_SHORT; goto exit; } header.byte = 0; header.bits.type = UNSUBACK; writeChar(&ptr, header.byte); /* write header */ ptr += MQTTPacket_encode(ptr, 2); /* write remaining length */ writeInt(&ptr, packetid); rc = ptr - buf; exit: FUNC_EXIT_RC(rc); return rc; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/src/StackTrace.h ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation * Ian Craggs - fix for bug #434081 *******************************************************************************/ #ifndef STACKTRACE_H_ #define STACKTRACE_H_ #include #define NOSTACKTRACE 1 #if defined(NOSTACKTRACE) #define FUNC_ENTRY #define FUNC_ENTRY_NOLOG #define FUNC_ENTRY_MED #define FUNC_ENTRY_MAX #define FUNC_EXIT #define FUNC_EXIT_NOLOG #define FUNC_EXIT_MED #define FUNC_EXIT_MAX #define FUNC_EXIT_RC(x) #define FUNC_EXIT_MED_RC(x) #define FUNC_EXIT_MAX_RC(x) #else #if defined(WIN32) #define inline __inline #define FUNC_ENTRY StackTrace_entry(__FUNCTION__, __LINE__, TRACE_MINIMUM) #define FUNC_ENTRY_NOLOG StackTrace_entry(__FUNCTION__, __LINE__, -1) #define FUNC_ENTRY_MED StackTrace_entry(__FUNCTION__, __LINE__, TRACE_MEDIUM) #define FUNC_ENTRY_MAX StackTrace_entry(__FUNCTION__, __LINE__, TRACE_MAXIMUM) #define FUNC_EXIT StackTrace_exit(__FUNCTION__, __LINE__, NULL, TRACE_MINIMUM) #define FUNC_EXIT_NOLOG StackTrace_exit(__FUNCTION__, __LINE__, -1) #define FUNC_EXIT_MED StackTrace_exit(__FUNCTION__, __LINE__, NULL, TRACE_MEDIUM) #define FUNC_EXIT_MAX StackTrace_exit(__FUNCTION__, __LINE__, NULL, TRACE_MAXIMUM) #define FUNC_EXIT_RC(x) StackTrace_exit(__FUNCTION__, __LINE__, &x, TRACE_MINIMUM) #define FUNC_EXIT_MED_RC(x) StackTrace_exit(__FUNCTION__, __LINE__, &x, TRACE_MEDIUM) #define FUNC_EXIT_MAX_RC(x) StackTrace_exit(__FUNCTION__, __LINE__, &x, TRACE_MAXIMUM) #else #define FUNC_ENTRY StackTrace_entry(__func__, __LINE__, TRACE_MINIMUM) #define FUNC_ENTRY_NOLOG StackTrace_entry(__func__, __LINE__, -1) #define FUNC_ENTRY_MED StackTrace_entry(__func__, __LINE__, TRACE_MEDIUM) #define FUNC_ENTRY_MAX StackTrace_entry(__func__, __LINE__, TRACE_MAXIMUM) #define FUNC_EXIT StackTrace_exit(__func__, __LINE__, NULL, TRACE_MINIMUM) #define FUNC_EXIT_NOLOG StackTrace_exit(__func__, __LINE__, NULL, -1) #define FUNC_EXIT_MED StackTrace_exit(__func__, __LINE__, NULL, TRACE_MEDIUM) #define FUNC_EXIT_MAX StackTrace_exit(__func__, __LINE__, NULL, TRACE_MAXIMUM) #define FUNC_EXIT_RC(x) StackTrace_exit(__func__, __LINE__, &x, TRACE_MINIMUM) #define FUNC_EXIT_MED_RC(x) StackTrace_exit(__func__, __LINE__, &x, TRACE_MEDIUM) #define FUNC_EXIT_MAX_RC(x) StackTrace_exit(__func__, __LINE__, &x, TRACE_MAXIMUM) void StackTrace_entry(const char* name, int line, int trace); void StackTrace_exit(const char* name, int line, void* return_value, int trace); void StackTrace_printStack(FILE* dest); char* StackTrace_get(unsigned long); #endif #endif #endif /* STACKTRACE_H_ */ ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/test/CMakeLists.txt ================================================ PROJECT(mqttpacket-tests) IF (WIN32) SET(MQTT_TEST_BROKER "tcp://mqtt.iotree.co.uk:1883" CACHE STRING "Hostname of a test MQTT broker to use") SET(MQTT_TEST_PROXY "tcp://localhost:1883" CACHE STRING "Hostname of the test proxy to use") SET(MQTT_SSL_HOSTNAME "mqtt.iotree.co.uk" CACHE STRING "Hostname of a test SSL MQTT broker to use") SET(CERTDIR $ENV{APPVEYOR_BUILD_FOLDER}/test/ssl) ELSE () SET(MQTT_TEST_BROKER "tcp://localhost:1883" CACHE STRING "Hostname of a test MQTT broker to use") SET(MQTT_TEST_PROXY "tcp://localhost:1884" CACHE STRING "Hostname of the test proxy to use") SET(MQTT_SSL_HOSTNAME "localhost" CACHE STRING "Hostname of a test SSL MQTT broker to use") SET(CERTDIR $ENV{TRAVIS_BUILD_DIR}/test/ssl) ENDIF () include_directories(../src) ADD_EXECUTABLE( test1 test1.c ) TARGET_LINK_LIBRARIES( test1 paho-embed-mqtt3c ) ADD_TEST( NAME test1 COMMAND "test1" "--connection" ${MQTT_TEST_BROKER} ) SET_TESTS_PROPERTIES( test1 PROPERTIES TIMEOUT 540 ) ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/test/build_test ================================================ gcc -Wall test1.c -o test1 -I../src ../src/MQTTConnectClient.c ../src/MQTTConnectServer.c ../src/MQTTPacket.c ../src/MQTTSerializePublish.c ../src/MQTTDeserializePublish.c ../src/MQTTSubscribeServer.c ../src/MQTTSubscribeClient.c ../src/MQTTUnsubscribeServer.c ../src/MQTTUnsubscribeClient.c ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/MQTTPacket/test/test1.c ================================================ /******************************************************************************* * Copyright (c) 2014 IBM Corp. * * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * and Eclipse Distribution License v1.0 which accompany this distribution. * * The Eclipse Public License is available at * http://www.eclipse.org/legal/epl-v10.html * and the Eclipse Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Ian Craggs - initial API and implementation and/or initial documentation *******************************************************************************/ #include "MQTTPacket.h" #include #include #include #if !defined(_WINDOWS) #include #include #include #include #else #include #include #define MAXHOSTNAMELEN 256 #define EAGAIN WSAEWOULDBLOCK #define EINTR WSAEINTR #define EINPROGRESS WSAEINPROGRESS #define EWOULDBLOCK WSAEWOULDBLOCK #define ENOTCONN WSAENOTCONN #define ECONNRESET WSAECONNRESET #endif #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) struct Options { char *connection; /**< connection to system under test. */ char **haconnections; int hacount; int verbose; int test_no; } options = { "tcp://m2m.eclipse.org:1883", NULL, 0, 0, 0, }; void usage() { } void getopts(int argc, char **argv) { int count = 1; while (count < argc) { if (strcmp(argv[count], "--test_no") == 0) { if (++count < argc) options.test_no = atoi(argv[count]); else usage(); } else if (strcmp(argv[count], "--connection") == 0) { if (++count < argc) { options.connection = argv[count]; printf("\nSetting connection to %s\n", options.connection); } else usage(); } else if (strcmp(argv[count], "--haconnections") == 0) { if (++count < argc) { char *tok = strtok(argv[count], " "); options.hacount = 0; options.haconnections = malloc(sizeof(char *) * 5); while (tok) { options.haconnections[options.hacount] = malloc(strlen(tok) + 1); strcpy(options.haconnections[options.hacount], tok); options.hacount++; tok = strtok(NULL, " "); } } else usage(); } else if (strcmp(argv[count], "--verbose") == 0) { options.verbose = 1; printf("\nSetting verbose on\n"); } count++; } } #define LOGA_DEBUG 0 #define LOGA_INFO 1 #include #include #include void MyLog(int LOGA_level, char *format, ...) { static char msg_buf[256]; va_list args; struct timeb ts; struct tm *timeinfo; if (LOGA_level == LOGA_DEBUG && options.verbose == 0) return; ftime(&ts); timeinfo = localtime(&ts.time); strftime(msg_buf, 80, "%Y%m%d %H%M%S", timeinfo); sprintf(&msg_buf[strlen(msg_buf)], ".%.3hu ", ts.millitm); va_start(args, format); vsnprintf(&msg_buf[strlen(msg_buf)], sizeof(msg_buf) - strlen(msg_buf), format, args); va_end(args); printf("%s\n", msg_buf); fflush(stdout); } #if defined(WIN32) || defined(_WINDOWS) #define mqsleep(A) Sleep(1000*A) #define START_TIME_TYPE DWORD static DWORD start_time = 0; START_TIME_TYPE start_clock(void) { return GetTickCount(); } #elif defined(AIX) #define mqsleep sleep #define START_TIME_TYPE struct timespec START_TIME_TYPE start_clock(void) { static struct timespec start; clock_gettime(CLOCK_REALTIME, &start); return start; } #else #define mqsleep sleep #define START_TIME_TYPE struct timeval /* TODO - unused - remove? static struct timeval start_time; */ START_TIME_TYPE start_clock(void) { struct timeval start_time; gettimeofday(&start_time, NULL); return start_time; } #endif #if defined(WIN32) long elapsed(START_TIME_TYPE start_time) { return GetTickCount() - start_time; } #elif defined(AIX) #define assert(a) long elapsed(struct timespec start) { struct timespec now, res; clock_gettime(CLOCK_REALTIME, &now); ntimersub(now, start, res); return (res.tv_sec) * 1000L + (res.tv_nsec) / 1000000L; } #else long elapsed(START_TIME_TYPE start_time) { struct timeval now, res; gettimeofday(&now, NULL); timersub(&now, &start_time, &res); return (res.tv_sec) * 1000 + (res.tv_usec) / 1000; } #endif #define assert(a, b, c, d) myassert(__FILE__, __LINE__, a, b, c, d) #define assert1(a, b, c, d, e) myassert(__FILE__, __LINE__, a, b, c, d, e) int tests = 0; int failures = 0; FILE *xml; START_TIME_TYPE global_start_time; char output[3000]; char *cur_output = output; void write_test_result() { long duration = elapsed(global_start_time); fprintf(xml, " time=\"%ld.%.3ld\" >\n", duration / 1000, duration % 1000); if (cur_output != output) { fprintf(xml, "%s", output); cur_output = output; } fprintf(xml, "\n"); } void myassert(char *filename, int lineno, char *description, int value, char *format, ...) { ++tests; if (!value) { va_list args; ++failures; printf("Assertion failed, file %s, line %d, description: %s\n", filename, lineno, description); va_start(args, format); vprintf(format, args); va_end(args); cur_output += sprintf(cur_output, "file %s, line %d \n", description, filename, lineno); } else MyLog(LOGA_DEBUG, "Assertion succeeded, file %s, line %d, description: %s", filename, lineno, description); } #define min(a, b) ((a < b) ? a : b) int checkMQTTStrings(MQTTString a, MQTTString b) { if (!a.lenstring.data) { a.lenstring.data = a.cstring; if (a.cstring) a.lenstring.len = strlen(a.cstring); } if (!b.lenstring.data) { b.lenstring.data = b.cstring; if (b.cstring) b.lenstring.len = strlen(b.cstring); } return memcmp(a.lenstring.data, b.lenstring.data, min(a.lenstring.len, b.lenstring.len)) == 0; } int checkConnectPackets(MQTTPacket_connectData *before, MQTTPacket_connectData *after) { int rc = 0; int start_failures = failures; assert("struct_ids should be the same", memcmp(before->struct_id, after->struct_id, 4) == 0, "struct_ids were different %.4s\n", after->struct_id); assert("struct_versions should be the same", before->struct_version == after->struct_version, "struct_versions were different\n", rc); assert("MQTT versions should be the same", before->MQTTVersion == after->MQTTVersion, "MQTT versions were different\n", rc); assert("ClientIDs should be the same", checkMQTTStrings(before->clientID, after->clientID), "ClientIDs were different\n", rc); assert("keepAliveIntervals should be the same", before->keepAliveInterval == after->keepAliveInterval, "keepAliveIntervals were different %d\n", after->keepAliveInterval); assert("cleansessions should be the same", before->cleansession == after->cleansession, "cleansessions were different\n", rc); assert("willFlags should be the same", before->willFlag == after->willFlag, "willFlags were different\n", rc); if (before->willFlag) { assert("will struct_ids should be the same", memcmp(before->will.struct_id, after->will.struct_id, 4) == 0, "will struct_ids were different %.4s\n", after->struct_id); assert("will struct_versions should be the same", before->will.struct_version == after->will.struct_version, "will struct_versions were different\n", rc); assert("topic names should be the same", checkMQTTStrings(before->will.topicName, after->will.topicName), "topic names were different\n", rc); assert("messages should be the same", checkMQTTStrings(before->will.message, after->will.message), "messages were different\n", rc); assert("retained flags should be the same", before->will.retained == after->will.retained, "retained flags were different\n", rc); assert("will qos should be the same", before->will.qos == after->will.qos, "will qos were different\n", rc); } assert("usernames should be the same", checkMQTTStrings(before->clientID, after->clientID), "usernames were different\n", rc); assert("passwords should be the same", checkMQTTStrings(before->password, after->password), "passwords were different\n", rc); return failures == start_failures; } int test1(struct Options options) { MQTTPacket_connectData data = MQTTPacket_connectData_initializer; MQTTPacket_connectData data_after = MQTTPacket_connectData_initializer; int rc = 0; unsigned char buf[100]; int buflen = sizeof(buf); fprintf(xml, " 0, "rc was %d\n", rc); rc = MQTTDeserialize_connect(&data_after, buf, buflen); assert("good rc from deserialize connect", rc == 1, "rc was %d\n", rc); /* data after should be the same as data before */ rc = checkConnectPackets(&data, &data_after); assert("packets should be the same", rc == 1, "packets were different\n", rc); /* exit: */ MyLog(LOGA_INFO, "TEST1: test %s. %d tests run, %d failures.", (failures == 0) ? "passed" : "failed", tests, failures); write_test_result(); return failures; } int test2(struct Options options) { int rc = 0; unsigned char buf[100]; int buflen = sizeof(buf); unsigned char dup = 0; int qos = 2; unsigned char retained = 0; unsigned short msgid = 23; MQTTString topicString = MQTTString_initializer; unsigned char *payload = (unsigned char *)"kkhkhkjkj jkjjk jk jk "; int payloadlen = strlen((char *)payload); unsigned char dup2 = 1; int qos2 = 1; unsigned char retained2 = 1; unsigned short msgid2 = 3243; MQTTString topicString2 = MQTTString_initializer; unsigned char *payload2 = NULL; int payloadlen2 = 0; fprintf(xml, " 0, "rc was %d\n", rc); rc = MQTTDeserialize_publish(&dup2, &qos2, &retained2, &msgid2, &topicString2, &payload2, &payloadlen2, buf, buflen); assert("good rc from deserialize publish", rc == 1, "rc was %d\n", rc); /* data after should be the same as data before */ assert("dups should be the same", dup == dup2, "dups were different %d\n", dup2); assert("qoss should be the same", qos == qos2, "qoss were different %d\n", qos2); assert("retaineds should be the same", retained == retained2, "retaineds were different %d\n", retained2); assert("msgids should be the same", msgid == msgid2, "msgids were different %d\n", msgid2); assert("topics should be the same", checkMQTTStrings(topicString, topicString2), "topics were different %s\n", ""); //topicString2); assert("payload lengths should be the same", payloadlen == payloadlen2, "payload lengths were different %d\n", payloadlen2); assert("payloads should be the same", memcmp(payload, payload2, payloadlen) == 0, "payloads were different %s\n", ""); /*exit:*/ MyLog(LOGA_INFO, "TEST2: test %s. %d tests run, %d failures.", (failures == 0) ? "passed" : "failed", tests, failures); write_test_result(); return failures; } int test3(struct Options options) { int i = 0; int rc = 0; unsigned char buf[100]; int buflen = sizeof(buf); #define TOPIC_COUNT 2 unsigned char dup = 0; unsigned short msgid = 23; int count = TOPIC_COUNT; MQTTString topicStrings[TOPIC_COUNT] = { MQTTString_initializer, MQTTString_initializer }; int req_qoss[TOPIC_COUNT] = {2, 1}; unsigned char dup2 = 1; unsigned short msgid2 = 2223; int count2 = 0; MQTTString topicStrings2[TOPIC_COUNT] = { MQTTString_initializer, MQTTString_initializer }; int req_qoss2[TOPIC_COUNT] = {0, 0}; fprintf(xml, " 0, "rc was %d\n", rc); rc = MQTTDeserialize_subscribe(&dup2, &msgid2, 2, &count2, topicStrings2, req_qoss2, buf, buflen); assert("good rc from deserialize subscribe", rc == 1, "rc was %d\n", rc); /* data after should be the same as data before */ assert("dups should be the same", dup == dup2, "dups were different %d\n", dup2); assert("msgids should be the same", msgid == msgid2, "msgids were different %d\n", msgid2); assert("count should be the same", count == count2, "counts were different %d\n", count2); for (i = 0; i < count2; ++i) { assert("topics should be the same", checkMQTTStrings(topicStrings[i], topicStrings2[i]), "topics were different %s\n", ""); assert("qoss should be the same", req_qoss[i] == req_qoss2[i], "qoss were different %d\n", req_qoss2[i]); } /*exit:*/ MyLog(LOGA_INFO, "TEST3: test %s. %d tests run, %d failures.", (failures == 0) ? "passed" : "failed", tests, failures); write_test_result(); return failures; } int test4(struct Options options) { int i = 0; int rc = 0; unsigned char buf[100]; int buflen = sizeof(buf); #define TOPIC_COUNT 2 int msgid = 23; int count = TOPIC_COUNT; int granted_qoss[TOPIC_COUNT] = {2, 1}; unsigned short msgid2 = 2223; int count2 = 0; int granted_qoss2[TOPIC_COUNT] = {0, 0}; fprintf(xml, " 0, "rc was %d\n", rc); rc = MQTTDeserialize_suback(&msgid2, 2, &count2, granted_qoss2, buf, buflen); assert("good rc from deserialize suback", rc == 1, "rc was %d\n", rc); /* data after should be the same as data before */ assert("msgids should be the same", msgid == msgid2, "msgids were different %d\n", msgid2); assert("count should be the same", count == count2, "counts were different %d\n", count2); for (i = 0; i < count2; ++i) assert("qoss should be the same", granted_qoss[i] == granted_qoss2[i], "qoss were different %d\n", granted_qoss2[i]); /* exit: */ MyLog(LOGA_INFO, "TEST4: test %s. %d tests run, %d failures.", (failures == 0) ? "passed" : "failed", tests, failures); write_test_result(); return failures; } int test5(struct Options options) { int i = 0; int rc = 0; unsigned char buf[100]; int buflen = sizeof(buf); #define TOPIC_COUNT 2 unsigned char dup = 0; unsigned short msgid = 23; int count = TOPIC_COUNT; MQTTString topicStrings[TOPIC_COUNT] = { MQTTString_initializer, MQTTString_initializer }; unsigned char dup2 = 1; unsigned short msgid2 = 2223; int count2 = 0; MQTTString topicStrings2[TOPIC_COUNT] = { MQTTString_initializer, MQTTString_initializer }; fprintf(xml, " 0, "rc was %d\n", rc); rc = MQTTDeserialize_unsubscribe(&dup2, &msgid2, 2, &count2, topicStrings2, buf, buflen); assert("good rc from deserialize unsubscribe", rc == 1, "rc was %d\n", rc); /* data after should be the same as data before */ assert("dups should be the same", dup == dup2, "dups were different %d\n", dup2); assert("msgids should be the same", msgid == msgid2, "msgids were different %d\n", msgid2); assert("count should be the same", count == count2, "counts were different %d\n", count2); for (i = 0; i < count2; ++i) assert("topics should be the same", checkMQTTStrings(topicStrings[i], topicStrings2[i]), "topics were different %s\n", ""); /* exit: */ MyLog(LOGA_INFO, "TEST5: test %s. %d tests run, %d failures.", (failures == 0) ? "passed" : "failed", tests, failures); write_test_result(); return failures; } int test6(struct Options options) { int rc = 0; unsigned char buf[100]; int buflen = sizeof(buf); unsigned char sessionPresent = 1; unsigned char connack_rc = 77; unsigned char sessionPresent2 = 0; unsigned char connack_rc2 = 0; fprintf(xml, " 0, "rc was %d\n", rc); rc = MQTTDeserialize_connack(&sessionPresent2, &connack_rc2, buf, buflen); assert("good rc from deserialize connack", rc == 1, "rc was %d\n", rc); /* data after should be the same as data before */ assert("connack rcs should be the same", connack_rc == connack_rc2, "connack rcs were different %d\n", connack_rc2); assert("session present flags should be the same", sessionPresent == sessionPresent2, "session present flags were different %d\n", sessionPresent2); /* exit: */ MyLog(LOGA_INFO, "TEST6: test %s. %d tests run, %d failures.", (failures == 0) ? "passed" : "failed", tests, failures); write_test_result(); return failures; } int main(int argc, char **argv) { int rc = 0; int (*tests[])() = {NULL, test1, test2, test3, test4, test5, test6}; xml = fopen("TEST-test1.xml", "w"); fprintf(xml, "\n", (int)(ARRAY_SIZE(tests) - 1)); getopts(argc, argv); if (options.test_no == 0) { /* run all the tests */ for (options.test_no = 1; options.test_no < ARRAY_SIZE(tests); ++options.test_no) rc += tests[options.test_no](options); /* return number of failures. 0 = test succeeded */ } else rc = tests[options.test_no](options); /* run just the selected test */ if (rc == 0) MyLog(LOGA_INFO, "verdict pass"); else MyLog(LOGA_INFO, "verdict fail"); fprintf(xml, "\n"); fclose(xml); return rc; } ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/Makefile ================================================ #******************************************************************************* # Copyright (c) 2009, 2014 IBM Corp. # # All rights reserved. This program and the accompanying materials # are made available under the terms of the Eclipse Public License v1.0 # and Eclipse Distribution License v1.0 which accompany this distribution. # # The Eclipse Public License is available at # http://www.eclipse.org/legal/epl-v10.html # and the Eclipse Distribution License is available at # http://www.eclipse.org/org/documents/edl-v10.php. # # Contributors: # Xiang Rong - 442039 Add makefile to Embedded C client #*******************************************************************************/ # Note: on OS X you should install XCode and the associated command-line tools SHELL = /bin/sh .PHONY: clean, mkdir, install, uninstall, html # assume this is normally run in the main Paho directory ifndef srcdir srcdir = MQTTPacket/src endif ifndef blddir blddir = build/output endif ifndef prefix prefix = /usr/local endif ifndef exec_prefix exec_prefix = ${prefix} endif bindir = $(exec_prefix)/bin includedir = $(prefix)/include libdir = $(exec_prefix)/lib SOURCE_FILES_C = $(srcdir)/*.c HEADERS = $(srcdir)/*.h SAMPLE_FILES_C = pub0sub1 qos0pub SYNC_SAMPLES = ${addprefix ${blddir}/samples/,${SAMPLE_FILES_C}} TEST_FILES_C = test1 SYNC_TESTS = ${addprefix ${blddir}/test/,${TEST_FILES_C}} # The names of libraries to be built MQTT_EMBED_LIB_C = paho-embed-mqtt3c # determine current platform ifeq ($(OS),Windows_NT) OSTYPE = $(OS) else OSTYPE = $(shell uname -s) MACHINETYPE = $(shell uname -m) endif ifeq ($(OSTYPE),Linux) CC ?= gcc ifndef INSTALL INSTALL = install endif INSTALL_PROGRAM = $(INSTALL) INSTALL_DATA = $(INSTALL) -m 644 MAJOR_VERSION = 1 MINOR_VERSION = 0 VERSION = ${MAJOR_VERSION}.${MINOR_VERSION} EMBED_MQTTLIB_C_TARGET = ${blddir}/lib${MQTT_EMBED_LIB_C}.so.${VERSION} CCFLAGS_SO = -g -fPIC -Os -Wall -fvisibility=hidden -DLINUX_SO FLAGS_EXE = -I ${srcdir} -L ${blddir} LDFLAGS_C = -shared -Wl,-soname,lib$(MQTT_EMBED_LIB_C).so.${MAJOR_VERSION} all: build build: | mkdir ${EMBED_MQTTLIB_C_TARGET} ${SYNC_SAMPLES} ${SYNC_TESTS} clean: rm -rf ${blddir}/* mkdir: -mkdir -p ${blddir}/samples -mkdir -p ${blddir}/test ${SYNC_TESTS}: ${blddir}/test/%: ${srcdir}/../test/%.c ${CC} -g -o ${blddir}/test/${basename ${+F}} $< -l${MQTT_EMBED_LIB_C} ${FLAGS_EXE} ${SYNC_SAMPLES}: ${blddir}/samples/%: ${srcdir}/../samples/%.c ${srcdir}/../samples/transport.o ${CC} -o $@ $^ -l${MQTT_EMBED_LIB_C} ${FLAGS_EXE} ${EMBED_MQTTLIB_C_TARGET}: ${SOURCE_FILES_C} ${HEADERS_C} ${CC} ${CCFLAGS_SO} -o $@ ${SOURCE_FILES_C} ${LDFLAGS_C} -ln -s lib$(MQTT_EMBED_LIB_C).so.${VERSION} ${blddir}/lib$(MQTT_EMBED_LIB_C).so.${MAJOR_VERSION} -ln -s lib$(MQTT_EMBED_LIB_C).so.${MAJOR_VERSION} ${blddir}/lib$(MQTT_EMBED_LIB_C).so strip_options: $(eval INSTALL_OPTS := -s) install-strip: build strip_options install install: build $(INSTALL_DATA) ${INSTALL_OPTS} ${EMBED_MQTTLIB_C_TARGET} $(DESTDIR)${libdir} /sbin/ldconfig $(DESTDIR)${libdir} ln -s lib$(MQTT_EMBED_LIB_C).so.${MAJOR_VERSION} $(DESTDIR)${libdir}/lib$(MQTT_EMBED_LIB_C).so uninstall: rm $(DESTDIR)${libdir}/lib$(MQTT_EMBED_LIB_C).so.${VERSION} /sbin/ldconfig $(DESTDIR)${libdir} rm $(DESTDIR)${libdir}/lib$(MQTT_EMBED_LIB_C).so html: ARDUINO_LIB_FILES = MQTTClient/src/*.h MQTTClient/src/arduino/*.h $(srcdir)/* ARDUINO_SAMPLES = MQTTClient/samples/arduino/* LEGAL_FILES = edl-v10 epl-v10 notice.html about.html CONTRIBUTING.md README.md library.properties arduino: mkdir -mkdir -p ${blddir}/arduino/MQTTClient/examples -mkdir -p ${blddir}/arduino/MQTTClient/src cp $(ARDUINO_LIB_FILES) ${blddir}/arduino/MQTTClient/src cp $(LEGAL_FILES) ${blddir}/arduino/MQTTClient cp -R $(ARDUINO_SAMPLES) ${blddir}/arduino/MQTTClient/examples cd ${blddir}/arduino && zip -r arduino MQTTClient endif ifeq ($(OSTYPE),Darwin) CC ?= gcc ifndef INSTALL INSTALL = install endif INSTALL_PROGRAM = $(INSTALL) INSTALL_DATA = $(INSTALL) -m 644 MAJOR_VERSION = 1 MINOR_VERSION = 0 VERSION = ${MAJOR_VERSION}.${MINOR_VERSION} EMBED_MQTTLIB_C_TARGET = ${blddir}/lib${MQTT_EMBED_LIB_C}.so.${VERSION} CCFLAGS_SO = -g -fPIC -Os -Wall -fvisibility=hidden -Wno-deprecated-declarations -DUSE_NAMED_SEMAPHORES FLAGS_EXE = -I ${srcdir} -L ${blddir} LDFLAGS_C = -shared -Wl,-install_name,lib$(MQTT_EMBED_LIB_C).so.${MAJOR_VERSION} all: build build: | mkdir ${EMBED_MQTTLIB_C_TARGET} ${SYNC_SAMPLES} ${SYNC_TESTS} clean: rm -rf ${blddir}/* mkdir: -mkdir -p ${blddir}/samples -mkdir -p ${blddir}/test ${SYNC_TESTS}: ${blddir}/test/%: ${srcdir}/../test/%.c ${CC} -g -o ${blddir}/test/${basename ${+F}} $< -l${MQTT_EMBED_LIB_C} ${FLAGS_EXE} ${SYNC_SAMPLES}: ${blddir}/samples/%: ${srcdir}/../samples/%.c ${CC} -o ${blddir}/samples/${basename ${+F}} $< ${FLAGS_EXE} -l${MQTT_EMBED_LIB_C} ${EMBED_MQTTLIB_C_TARGET}: ${SOURCE_FILES_C} ${HEADERS_C} ${CC} ${CCFLAGS_SO} -o $@ ${SOURCE_FILES_C} ${LDFLAGS_C} -ln -s lib$(MQTT_EMBED_LIB_C).so.${VERSION} ${blddir}/lib$(MQTT_EMBED_LIB_C).so.${MAJOR_VERSION} -ln -s lib$(MQTT_EMBED_LIB_C).so.${MAJOR_VERSION} ${blddir}/lib$(MQTT_EMBED_LIB_C).so strip_options: $(eval INSTALL_OPTS := -s) install-strip: build strip_options install install: build $(INSTALL_DATA) ${INSTALL_OPTS} ${EMBED_MQTTLIB_C_TARGET} $(DESTDIR)${libdir} /sbin/ldconfig $(DESTDIR)${libdir} ln -s lib$(MQTT_EMBED_LIB_C).so.${MAJOR_VERSION} $(DESTDIR)${libdir}/lib$(MQTT_EMBED_LIB_C).so uninstall: rm $(DESTDIR)${libdir}/lib$(MQTT_EMBED_LIB_C).so.${VERSION} /sbin/ldconfig $(DESTDIR)${libdir} rm $(DESTDIR)${libdir}/lib$(MQTT_EMBED_LIB_C).so html: endif ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/README.md ================================================ # Eclipse Paho MQTT C/C++ client for Embedded platforms This repository contains the source code for the [Eclipse Paho](http://eclipse.org/paho) MQTT C/C++ client library for Embedded platorms. It is dual licensed under the EPL and EDL (see about.html and notice.html for more details). You can choose which of these licenses you want to use the code under. The EDL allows you to embed the code into your application, and distribute your application in binary or source form without contributing any of your code, or any changes you make back to Paho. See the EDL for the exact conditions. There are three sub-projects: 1. MQTTPacket - simple de/serialization of MQTT packets, plus helper functions 2. MQTTClient - high(er) level C++ client, plus 3. MQTTClient-C - high(er) level C client (pretty much a clone of the C++ client) The *MQTTPacket* directory contains the lowest level C library with the smallest requirements. This supplies simple serialization and deserialization routines. They serve as a base for the higher level libraries, but can also be used on their own It is mainly up to you to write and read to and from the network. The *MQTTClient* directory contains the next level C++ library. This networking code is contained in separate classes so that you can plugin the network of your choice. Currently there are implementations for Linux, Arduino and mbed. ARM mbed was the first platform for which this was written, where the conventional language choice is C++, which explains the language choice. I have written a starter [Porting Guide](http://modelbasedtesting.co.uk/2014/08/25/porting-a-paho-embedded-c-client/). The *MQTTClient-C* directory contains a C equivalent of MQTTClient, for those platforms where C++ is not supported or the convention. As far as possible it is a direct translation from *MQTTClient*. ## Build requirements / compilation CMake builds for the various packages have been introduced, along with Travis-CI configuration for automated build & testing. The basic method of building on Linux is: ``` mkdir build.paho cd build.paho cmake .. make ``` The travis-build.sh file has the full build and test sequence for Linux. ## Usage and API See the samples directories for examples of intended use. Doxygen config files for each package are available in the doc directory. ## Runtime tracing The *MQTTClient* API has debug tracing for MQTT packets sent and received - turn this on by setting the MQTT_DEBUG preprocessor definition. ## Reporting bugs This project uses GitHub Issues here: [github.com/eclipse/paho.mqtt.embedded-c/issues](https://github.com/eclipse/paho.mqtt.embedded-c/issues) to track ongoing development and issues. ## More information Discussion of the Paho clients takes place on the [Eclipse Mattermost Paho channel](https://mattermost.eclipse.org/eclipse/channels/paho) and the [Eclipse paho-dev mailing list](https://dev.eclipse.org/mailman/listinfo/paho-dev). General questions about the MQTT protocol are discussed in the [MQTT Google Group](https://groups.google.com/forum/?hl=en-US&fromgroups#!forum/mqtt). More information is available via the [MQTT community](http://mqtt.org). ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/about.html ================================================ About

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    December 9, 2013

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    ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/edl-v10 ================================================ Eclipse Distribution License - v 1.0 Copyright (c) 2007, Eclipse Foundation, Inc. and its licensors. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of the Eclipse Foundation, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. 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Everyone is permitted to copy and distribute copies of this Agreement, but in order to avoid inconsistency the Agreement is copyrighted and may only be modified in the following manner. The Agreement Steward reserves the right to publish new versions (including revisions) of this Agreement from time to time. No one other than the Agreement Steward has the right to modify this Agreement. The Eclipse Foundation is the initial Agreement Steward. The Eclipse Foundation may assign the responsibility to serve as the Agreement Steward to a suitable separate entity. Each new version of the Agreement will be given a distinguishing version number. The Program (including Contributions) may always be distributed subject to the version of the Agreement under which it was received. In addition, after a new version of the Agreement is published, Contributor may elect to distribute the Program (including its Contributions) under the new version. Except as expressly stated in Sections 2(a) and 2(b) above, Recipient receives no rights or licenses to the intellectual property of any Contributor under this Agreement, whether expressly, by implication, estoppel or otherwise. All rights in the Program not expressly granted under this Agreement are reserved. This Agreement is governed by the laws of the State of New York and the intellectual property laws of the United States of America. No party to this Agreement will bring a legal action under this Agreement more than one year after the cause of action arose. Each party waives its rights to a jury trial in any resulting litigation. ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/library.properties ================================================ name=MQTTClient version=1.0.0 author=Ian Craggs maintainer=Ian Craggs https://github.com/icraggs sentence=This is the lowest level library, the simplest and smallest, but hardest to use. It simply deals with serialization and deserialization of MQTT packets. paragraph=... category=Communication url=https://github.com/eclipse/paho.mqtt.embedded-c architectures=* ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/notice.html ================================================ Eclipse Foundation Software User Agreement

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    ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/travis-build.sh ================================================ #!/bin/bash set -e rm -rf build.paho mkdir build.paho cd build.paho echo "travis build dir $TRAVIS_BUILD_DIR pwd $PWD" cmake .. make python ../test/mqttsas2.py localhost 1883 1885 & ctest -VV --timeout 600 kill %1 killall mosquitto ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/travis-env-vars ================================================ export TRAVIS_OS_NAME=linux export TRAVIS_BUILD_DIR=/home/icraggs/git/paho.mqtt.embedded-c ================================================ FILE: Huawei_LiteOS/components/connectivity/mqtt/travis-install.sh ================================================ #!/bin/bash if [ "$TRAVIS_OS_NAME" == "linux" ]; then pwd sudo service mosquitto stop # Stop any mosquitto instance which may be still running from previous runs killall mosquitto mosquitto -h mosquitto & fi if [ "$TRAVIS_OS_NAME" == "osx" ]; then pwd brew update brew install openssl mosquitto brew services stop mosquitto /usr/local/sbin/mosquitto -h /usr/local/sbin/mosquitto & fi ================================================ FILE: Huawei_LiteOS/components/connectivity/nb_iot/los_nb_api.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #if defined(WITH_AT_FRAMEWORK) #include "nb_iot/los_nb_api.h" #include "at_frame/at_api.h" //#include "atiny_socket.h" #include "at_device/bc95.h" int los_nb_init(const int8_t* host, const int8_t* port, sec_param_s* psk) { int ret; int timecnt = 0; //if(port == NULL) //return -1; /*when used nb with agenttiny*/ /*the following para is replaced by call nb_int()*/ at_config at_user_conf = { .name = AT_MODU_NAME, .usart_port = AT_USART_PORT, .buardrate = AT_BUARDRATE, .linkid_num = AT_MAX_LINK_NUM, .user_buf_len = MAX_AT_USERDATA_LEN, .cmd_begin = AT_CMD_BEGIN, .line_end = AT_LINE_END, .mux_mode = 1, //support multi connection mode .timeout = AT_CMD_TIMEOUT, // ms }; at.init(&at_user_conf); nb_reboot(); //LOS_TaskDelay(2000); if(psk != NULL)//encryption v1.9 { if(psk->setpsk) nb_send_psk(psk->pskid, psk->psk); else nb_set_no_encrypt(); } while(1) { ret = nb_hw_detect(); printf("call nb_hw_detect,ret is %d\n",ret); if(ret == AT_OK) break; //LOS_TaskDelay(1000); } //nb_get_auto_connect(); //nb_connect(NULL, NULL, NULL); while(timecnt < 120) { ret = nb_get_netstat(); nb_check_csq(); if(ret != AT_FAILED) { ret = nb_query_ip(); break; } //LOS_TaskDelay(1000); timecnt++; } if(ret != AT_FAILED) { nb_query_ip(); } ret = nb_set_cdpserver((char *)host, (char *)port); return ret; } int los_nb_report(const char* buf, int len) { if(buf == NULL || len <= 0) return -1; return nb_send_payload(buf, len); } int los_nb_notify(char* featurestr,int cmdlen, oob_callback callback, oob_cmd_match cmd_match) { if(featurestr == NULL ||cmdlen <= 0 || cmdlen >= OOB_CMD_LEN - 1) return -1; return at.oob_register(featurestr,cmdlen, callback,cmd_match); } int los_nb_deinit(void) { nb_reboot(); at.deinit(); return 0; } #endif ================================================ FILE: Huawei_LiteOS/components/fs/devfs/los_devfs.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include #include #if (LOSCFG_ENABLE_DEVFS == YES) static void *devfs_root = NULL; UINT32 los_devfs_init (void) { if (devfs_root != NULL) { return LOS_OK; } if (los_kifs_init () != LOS_OK) { return LOS_NOK; } devfs_root = los_kifs_mount ("/dev/"); return (devfs_root == NULL) ? LOS_NOK : LOS_OK; } UINT32 los_devfs_create (const char *name, uint32_t flags, struct devfs_ops *devops, void *arg) { int ret; if (devfs_root == NULL) { return LOS_NOK; } ret = los_kifs_create (devfs_root, name, flags, &devops->kiops, arg); return ret == 0 ? LOS_OK : LOS_NOK; } UINT32 los_devfs_link (const char *path_in_mp, uint32_t flags, void *buff, size_t size) { int ret; if (devfs_root == NULL) { return LOS_NOK; } ret = los_kifs_link (devfs_root, path_in_mp, flags, buff, size); return ret == 0 ? LOS_OK : LOS_NOK; } #endif ================================================ FILE: Huawei_LiteOS/components/fs/fatfs/ff13b/LICENSE.txt ================================================ FatFs License FatFs has being developped as a personal project of the author, ChaN. It is free from the code anyone else wrote at current release. Following code block shows a copy of the FatFs license document that heading the source files. /*----------------------------------------------------------------------------/ / FatFs - Generic FAT Filesystem Module Rx.xx / /-----------------------------------------------------------------------------/ / / Copyright (C) 20xx, ChaN, all right reserved. / / FatFs module is an open source software. Redistribution and use of FatFs in / source and binary forms, with or without modification, are permitted provided / that the following condition is met: / / 1. Redistributions of source code must retain the above copyright notice, / this condition and the following disclaimer. / / This software is provided by the copyright holder and contributors "AS IS" / and any warranties related to this software are DISCLAIMED. / The copyright owner or contributors be NOT LIABLE for any damages caused / by use of this software. /----------------------------------------------------------------------------*/ Therefore FatFs license is one of the BSD-style licenses but there is a significant feature. FatFs is mainly intended for embedded systems. In order to extend the usability for commercial products, the redistributions of FatFs in binary form, such as embedded code, binary library and any forms without source code, does not need to include about FatFs in the documentations. This is equivalent to the 1-clause BSD license. Of course FatFs is compatible with the most of open source software licenses including GNU GPL. When you redistribute the FatFs source code with any changes or create a fork, the license can also be changed to GNU GPL, BSD-style license or any open source software license that not conflict with FatFs license. ================================================ FILE: Huawei_LiteOS/components/fs/fatfs/ff13b/source/00history.txt ================================================ ---------------------------------------------------------------------------- Revision history of FatFs module ---------------------------------------------------------------------------- R0.00 (February 26, 2006) Prototype. R0.01 (April 29, 2006) The first release. R0.02 (June 01, 2006) Added FAT12 support. Removed unbuffered mode. Fixed a problem on small (<32M) partition. R0.02a (June 10, 2006) Added a configuration option (_FS_MINIMUM). R0.03 (September 22, 2006) Added f_rename(). Changed option _FS_MINIMUM to _FS_MINIMIZE. R0.03a (December 11, 2006) Improved cluster scan algorithm to write files fast. Fixed f_mkdir() creates incorrect directory on FAT32. R0.04 (February 04, 2007) Added f_mkfs(). Supported multiple drive system. Changed some interfaces for multiple drive system. Changed f_mountdrv() to f_mount(). R0.04a (April 01, 2007) Supported multiple partitions on a physical drive. Added a capability of extending file size to f_lseek(). Added minimization level 3. Fixed an endian sensitive code in f_mkfs(). R0.04b (May 05, 2007) Added a configuration option _USE_NTFLAG. Added FSINFO support. Fixed DBCS name can result FR_INVALID_NAME. Fixed short seek (<= csize) collapses the file object. R0.05 (August 25, 2007) Changed arguments of f_read(), f_write() and f_mkfs(). Fixed f_mkfs() on FAT32 creates incorrect FSINFO. Fixed f_mkdir() on FAT32 creates incorrect directory. R0.05a (February 03, 2008) Added f_truncate() and f_utime(). Fixed off by one error at FAT sub-type determination. Fixed btr in f_read() can be mistruncated. Fixed cached sector is not flushed when create and close without write. R0.06 (April 01, 2008) Added fputc(), fputs(), fprintf() and fgets(). Improved performance of f_lseek() on moving to the same or following cluster. R0.07 (April 01, 2009) Merged Tiny-FatFs as a configuration option. (_FS_TINY) Added long file name feature. (_USE_LFN) Added multiple code page feature. (_CODE_PAGE) Added re-entrancy for multitask operation. (_FS_REENTRANT) Added auto cluster size selection to f_mkfs(). Added rewind option to f_readdir(). Changed result code of critical errors. Renamed string functions to avoid name collision. R0.07a (April 14, 2009) Septemberarated out OS dependent code on reentrant cfg. Added multiple sector size feature. R0.07c (June 21, 2009) Fixed f_unlink() can return FR_OK on error. Fixed wrong cache control in f_lseek(). Added relative path feature. Added f_chdir() and f_chdrive(). Added proper case conversion to extended character. R0.07e (November 03, 2009) Septemberarated out configuration options from ff.h to ffconf.h. Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH. Fixed name matching error on the 13 character boundary. Added a configuration option, _LFN_UNICODE. Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. R0.08 (May 15, 2010) Added a memory configuration option. (_USE_LFN = 3) Added file lock feature. (_FS_SHARE) Added fast seek feature. (_USE_FASTSEEK) Changed some types on the API, XCHAR->TCHAR. Changed .fname in the FILINFO structure on Unicode cfg. String functions support UTF-8 encoding files on Unicode cfg. R0.08a (August 16, 2010) Added f_getcwd(). (_FS_RPATH = 2) Added sector erase feature. (_USE_ERASE) Moved file lock semaphore table from fs object to the bss. Fixed f_mkfs() creates wrong FAT32 volume. R0.08b (January 15, 2011) Fast seek feature is also applied to f_read() and f_write(). f_lseek() reports required table size on creating CLMP. Extended format syntax of f_printf(). Ignores duplicated directory separators in given path name. R0.09 (September 06, 2011) f_mkfs() supports multiple partition to complete the multiple partition feature. Added f_fdisk(). R0.09a (August 27, 2012) Changed f_open() and f_opendir() reject null object pointer to avoid crash. Changed option name _FS_SHARE to _FS_LOCK. Fixed assertion failure due to OS/2 EA on FAT12/16 volume. R0.09b (January 24, 2013) Added f_setlabel() and f_getlabel(). R0.10 (October 02, 2013) Added selection of character encoding on the file. (_STRF_ENCODE) Added f_closedir(). Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO) Added forced mount feature with changes of f_mount(). Improved behavior of volume auto detection. Improved write throughput of f_puts() and f_printf(). Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write(). Fixed f_write() can be truncated when the file size is close to 4GB. Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect value on error. R0.10a (January 15, 2014) Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID) Added a configuration option of minimum sector size. (_MIN_SS) 2nd argument of f_rename() can have a drive number and it will be ignored. Fixed f_mount() with forced mount fails when drive number is >= 1. (appeared at R0.10) Fixed f_close() invalidates the file object without volume lock. Fixed f_closedir() returns but the volume lock is left acquired. (appeared at R0.10) Fixed creation of an entry with LFN fails on too many SFN collisions. (appeared at R0.07) R0.10b (May 19, 2014) Fixed a hard error in the disk I/O layer can collapse the directory entry. Fixed LFN entry is not deleted when delete/rename an object with lossy converted SFN. (appeared at R0.07) R0.10c (November 09, 2014) Added a configuration option for the platforms without RTC. (_FS_NORTC) Changed option name _USE_ERASE to _USE_TRIM. Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b) Fixed a potential problem of FAT access that can appear on disk error. Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08) R0.11 (February 09, 2015) Added f_findfirst(), f_findnext() and f_findclose(). (_USE_FIND) Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c) Fixed _FS_NORTC option does not work properly. (appeared at R0.10c) R0.11a (September 05, 2015) Fixed wrong media change can lead a deadlock at thread-safe configuration. Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE) Removed some code pages actually not exist on the standard systems. (_CODE_PAGE) Fixed errors in the case conversion teble of code page 437 and 850 (ff.c). Fixed errors in the case conversion teble of Unicode (cc*.c). R0.12 (April 12, 2016) Added support for exFAT file system. (_FS_EXFAT) Added f_expand(). (_USE_EXPAND) Changed some members in FINFO structure and behavior of f_readdir(). Added an option _USE_CHMOD. Removed an option _WORD_ACCESS. Fixed errors in the case conversion table of Unicode (cc*.c). R0.12a (July 10, 2016) Added support for creating exFAT volume with some changes of f_mkfs(). Added a file open method FA_OPEN_APPEND. An f_lseek() following f_open() is no longer needed. f_forward() is available regardless of _FS_TINY. Fixed f_mkfs() creates wrong volume. (appeared at R0.12) Fixed wrong memory read in create_name(). (appeared at R0.12) Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD. R0.12b (September 04, 2016) Made f_rename() be able to rename objects with the same name but case. Fixed an error in the case conversion teble of code page 866. (ff.c) Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12) Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12) Fixed f_mkfs() creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12) Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12) Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12) Fixed some internal errors in f_expand() and f_lseek(). (appeared at R0.12) R0.12c (March 04, 2017) Improved write throughput at the fragmented file on the exFAT volume. Made memory usage for exFAT be able to be reduced as decreasing _MAX_LFN. Fixed successive f_getfree() can return wrong count on the FAT12/16 volume. (appeared at R0.12) Fixed configuration option _VOLUMES cannot be set 10. (appeared at R0.10c) R0.13 (May 21, 2017) Changed heading character of configuration keywords "_" to "FF_". Removed ASCII-only configuration, FF_CODE_PAGE = 1. Use FF_CODE_PAGE = 437 instead. Added f_setcp(), run-time code page configuration. (FF_CODE_PAGE = 0) Improved cluster allocation time on stretch a deep buried cluster chain. Improved processing time of f_mkdir() with large cluster size by using FF_USE_LFN = 3. Improved NoFatChain flag of the fragmented file to be set after it is truncated and got contiguous. Fixed archive attribute is left not set when a file on the exFAT volume is renamed. (appeared at R0.12) Fixed exFAT FAT entry can be collapsed when write or lseek operation to the existing file is done. (appeared at R0.12c) Fixed creating a file can fail when a new cluster allocation to the exFAT directory occures. (appeared at R0.12c) R0.13a (October 14, 2017) Added support for UTF-8 encoding on the API. (FF_LFN_UNICODE = 2) Added options for file name output buffer. (FF_LFN_BUF, FF_SFN_BUF). Added dynamic memory allocation option for working buffer of f_mkfs() and f_fdisk(). Fixed f_fdisk() and f_mkfs() create the partition table with wrong CHS parameters. (appeared at R0.09) Fixed f_unlink() can cause lost clusters at fragmented file on the exFAT volume. (appeared at R0.12c) Fixed f_setlabel() rejects some valid characters for exFAT volume. (appeared at R0.12) R0.13b (April 07, 2018) Added support for UTF-32 encoding on the API. (FF_LFN_UNICODE = 3) Added support for Unix style volume ID. (FF_STR_VOLUME_ID = 2) Fixed accesing any object on the exFAT root directory beyond the cluster boundary can fail. (appeared at R0.12c) Fixed f_setlabel() does not reject some invalid characters. (appeared at R0.09b) ================================================ FILE: Huawei_LiteOS/components/fs/fatfs/ff13b/source/00readme.txt ================================================ FatFs Module Source Files R0.13b FILES 00readme.txt This file. 00history.txt Revision history. ff.c FatFs module. ffconf.h Configuration file of FatFs module. ff.h Common include file for FatFs and application module. diskio.h Common include file for FatFs and disk I/O module. diskio.c An example of glue function to attach existing disk I/O module to FatFs. integer.h Integer type definitions for FatFs. ffunicode.c Optional Unicode utility functions. ffsystem.c An example of optional O/S related functions. Low level disk I/O module is not included in this archive because the FatFs module is only a generic file system layer and it does not depend on any specific storage device. You need to provide a low level disk I/O module written to control the storage device that attached to the target system. ================================================ FILE: Huawei_LiteOS/components/fs/fatfs/ff13b/source/default/ffconf.h ================================================ /*---------------------------------------------------------------------------/ / FatFs - Configuration file /---------------------------------------------------------------------------*/ #include "fs/los_vfs.h" #define FFCONF_DEF 63463 /* Revision ID */ /*---------------------------------------------------------------------------/ / Function Configurations /---------------------------------------------------------------------------*/ #define FF_FS_READONLY 0 /* This option switches read-only configuration. (0:Read/Write or 1:Read-only) / Read-only configuration removes writing API functions, f_write(), f_sync(), / f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() / and optional writing functions as well. */ #define FF_FS_MINIMIZE 0 /* This option defines minimization level to remove some basic API functions. / / 0: Basic functions are fully enabled. / 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() / are removed. / 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. / 3: f_lseek() function is removed in addition to 2. */ #define FF_USE_STRFUNC 2 /* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf(). / / 0: Disable string functions. / 1: Enable without LF-CRLF conversion. / 2: Enable with LF-CRLF conversion. */ #define FF_USE_FIND 0 /* This option switches filtered directory read functions, f_findfirst() and / f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ #define FF_USE_MKFS 1 /* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ #define FF_USE_FASTSEEK 1 /* This option switches fast seek function. (0:Disable or 1:Enable) */ #define FF_USE_EXPAND 0 /* This option switches f_expand function. (0:Disable or 1:Enable) */ #define FF_USE_CHMOD 0 /* This option switches attribute manipulation functions, f_chmod() and f_utime(). / (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ #define FF_USE_LABEL 0 /* This option switches volume label functions, f_getlabel() and f_setlabel(). / (0:Disable or 1:Enable) */ #define FF_USE_FORWARD 0 /* This option switches f_forward() function. (0:Disable or 1:Enable) */ /*---------------------------------------------------------------------------/ / Locale and Namespace Configurations /---------------------------------------------------------------------------*/ #define FF_CODE_PAGE 936 /* This option specifies the OEM code page to be used on the target system. / Incorrect code page setting can cause a file open failure. / / 437 - U.S. / 720 - Arabic / 737 - Greek / 771 - KBL / 775 - Baltic / 850 - Latin 1 / 852 - Latin 2 / 855 - Cyrillic / 857 - Turkish / 860 - Portuguese / 861 - Icelandic / 862 - Hebrew / 863 - Canadian French / 864 - Arabic / 865 - Nordic / 866 - Russian / 869 - Greek 2 / 932 - Japanese (DBCS) / 936 - Simplified Chinese (DBCS) / 949 - Korean (DBCS) / 950 - Traditional Chinese (DBCS) / 0 - Include all code pages above and configured by f_setcp() */ #define FF_USE_LFN 2 #define FF_MAX_LFN LOS_MAX_DIR_NAME_LEN /* The FF_USE_LFN switches the support for LFN (long file name). / / 0: Disable LFN. FF_MAX_LFN has no effect. / 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. / 2: Enable LFN with dynamic working buffer on the STACK. / 3: Enable LFN with dynamic working buffer on the HEAP. / / To enable the LFN, ffunicode.c needs to be added to the project. The LFN function / requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and / additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled. / The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can / be in range of 12 to 255. It is recommended to be set 255 to fully support LFN / specification. / When use stack for the working buffer, take care on stack overflow. When use heap / memory for the working buffer, memory management functions, ff_memalloc() and / ff_memfree() in ffsystem.c, need to be added to the project. */ #define FF_LFN_UNICODE 0 /* This option switches the character encoding on the API when LFN is enabled. / / 0: ANSI/OEM in current CP (TCHAR = char) / 1: Unicode in UTF-16 (TCHAR = WCHAR) / 2: Unicode in UTF-8 (TCHAR = char) / 3: Unicode in UTF-32 (TCHAR = DWORD) / / Also behavior of string I/O functions will be affected by this option. / When LFN is not enabled, this option has no effect. */ #define FF_LFN_BUF 255 #define FF_SFN_BUF 12 /* This set of options defines size of file name members in the FILINFO structure / which is used to read out directory items. These values should be suffcient for / the file names to read. The maximum possible length of the read file name depends / on character encoding. When LFN is not enabled, these options have no effect. */ #define FF_STRF_ENCODE 3 /* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(), / f_putc(), f_puts and f_printf() convert the character encoding in it. / This option selects assumption of character encoding ON THE FILE to be / read/written via those functions. / / 0: ANSI/OEM in current CP / 1: Unicode in UTF-16LE / 2: Unicode in UTF-16BE / 3: Unicode in UTF-8 */ #define FF_FS_RPATH 0 /* This option configures support for relative path. / / 0: Disable relative path and remove related functions. / 1: Enable relative path. f_chdir() and f_chdrive() are available. / 2: f_getcwd() function is available in addition to 1. */ /*---------------------------------------------------------------------------/ / Drive/Volume Configurations /---------------------------------------------------------------------------*/ #define FF_VOLUMES 1 /* Number of volumes (logical drives) to be used. (1-10) */ #define FF_STR_VOLUME_ID 0 #define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3" /* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings. / When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive / number in the path name. FF_VOLUME_STRS defines the volume ID strings for each / logical drives. Number of items must not be less than FF_VOLUMES. Valid / characters for the volume ID strings are A-Z, a-z and 0-9, however, they are / compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is / not defined, a user defined volume string table needs to be defined as: / / const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",... */ #define FF_MULTI_PARTITION 0 /* This option switches support for multiple volumes on the physical drive. / By default (0), each logical drive number is bound to the same physical drive / number and only an FAT volume found on the physical drive will be mounted. / When this function is enabled (1), each logical drive number can be bound to / arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() / funciton will be available. */ #define FF_MIN_SS 512 #define FF_MAX_SS 4096 /* This set of options configures the range of sector size to be supported. (512, / 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and / harddisk. But a larger value may be required for on-board flash memory and some / type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured / for variable sector size mode and disk_ioctl() function needs to implement / GET_SECTOR_SIZE command. */ #define FF_USE_TRIM 0 /* This option switches support for ATA-TRIM. (0:Disable or 1:Enable) / To enable Trim function, also CTRL_TRIM command should be implemented to the / disk_ioctl() function. */ #define FF_FS_NOFSINFO 0 /* If you need to know correct free space on the FAT32 volume, set bit 0 of this / option, and f_getfree() function at first time after volume mount will force / a full FAT scan. Bit 1 controls the use of last allocated cluster number. / / bit0=0: Use free cluster count in the FSINFO if available. / bit0=1: Do not trust free cluster count in the FSINFO. / bit1=0: Use last allocated cluster number in the FSINFO if available. / bit1=1: Do not trust last allocated cluster number in the FSINFO. */ /*---------------------------------------------------------------------------/ / System Configurations /---------------------------------------------------------------------------*/ #define FF_FS_TINY 0 /* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) / At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes. / Instead of private sector buffer eliminated from the file object, common sector / buffer in the filesystem object (FATFS) is used for the file data transfer. */ #define FF_FS_EXFAT 0 /* This option switches support for exFAT filesystem. (0:Disable or 1:Enable) / To enable exFAT, also LFN needs to be enabled. / Note that enabling exFAT discards ANSI C (C89) compatibility. */ #define FF_FS_NORTC 0 #define FF_NORTC_MON 1 #define FF_NORTC_MDAY 1 #define FF_NORTC_YEAR 2018 /* The option FF_FS_NORTC switches timestamp functiton. If the system does not have / any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable / the timestamp function. Every object modified by FatFs will have a fixed timestamp / defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time. / To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be / added to the project to read current time form real-time clock. FF_NORTC_MON, / FF_NORTC_MDAY and FF_NORTC_YEAR have no effect. / These options have no effect at read-only configuration (FF_FS_READONLY = 1). */ #define FF_FS_LOCK LOS_MAX_FILES /* The option FF_FS_LOCK switches file lock function to control duplicated file open / and illegal operation to open objects. This option must be 0 when FF_FS_READONLY / is 1. / / 0: Disable file lock function. To avoid volume corruption, application program / should avoid illegal open, remove and rename to the open objects. / >0: Enable file lock function. The value defines how many files/sub-directories / can be opened simultaneously under file lock control. Note that the file / lock control is independent of re-entrancy. / This value should be no more than LOS_MAX_FILES in los_vfs.h */ #define FF_FS_REENTRANT 0 #define FF_FS_TIMEOUT 1000 #define FF_SYNC_t HANDLE /* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs / module itself. Note that regardless of this option, file access to different / volume is always re-entrant and volume control functions, f_mount(), f_mkfs() / and f_fdisk() function, are always not re-entrant. Only file/directory access / to the same volume is under control of this function. / / 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect. / 1: Enable re-entrancy. Also user provided synchronization handlers, / ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() / function, must be added to the project. Samples are available in / option/syscall.c. / / The FF_FS_TIMEOUT defines timeout period in unit of time tick. / The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, / SemaphoreHandle_t and etc. A header file for O/S definitions needs to be / included somewhere in the scope of ff.h. */ #define FF_PHYS_ADDR 0 /* Physical offset(in bytes) in spi flash used for FatFs / Must be on 4k boundary */ #define FF_PHYS_SIZE 0x100000 /* Physical size(in bytes) of the spi flash used for FatFs / Must be on 4k boundary */ /*--- End of configuration options ---*/ ================================================ FILE: Huawei_LiteOS/components/fs/fatfs/ff13b/source/diskio.c ================================================ /*-----------------------------------------------------------------------*/ /* Low level disk I/O module skeleton for FatFs (C)ChaN, 2016 */ /*-----------------------------------------------------------------------*/ /* If a working storage control module is available, it should be */ /* attached to the FatFs via a glue function rather than modifying it. */ /* This is an example of glue functions to attach various exsisting */ /* storage control modules to the FatFs module with a defined API. */ /*-----------------------------------------------------------------------*/ #include "diskio.h" /* FatFs lower layer API */ #include "fs/los_fatfs.h" extern struct disk_mnt disk; /** * @brief Gets Disk Status * @param pdrv: Physical drive number (0..) * @retval DSTATUS: Operation status */ DSTATUS disk_status ( BYTE pdrv /* Physical drive nmuber to identify the drive */ ) { DSTATUS stat; struct disk_dev *pdev = &disk.dev[pdrv]; stat = pdev->drv->status(pdev->lun); return stat; } /** * @brief Initializes a Drive * @param pdrv: Physical drive number (0..) * @retval DSTATUS: Operation status */ DSTATUS disk_initialize ( BYTE pdrv /* Physical drive nmuber to identify the drive */ ) { DSTATUS stat = RES_OK; struct disk_dev *pdev = &disk.dev[pdrv]; if(pdev->state == 0) { pdev->state = 1; stat = pdev->drv->initialize(pdev->lun); } return stat; } /** * @brief Reads Sector(s) * @param pdrv: Physical drive number (0..) * @param *buff: Data buffer to store read data * @param sector: Sector address (LBA) * @param count: Number of sectors to read (1..128) * @retval DRESULT: Operation result */ DRESULT disk_read ( BYTE pdrv, /* Physical drive nmuber to identify the drive */ BYTE *buff, /* Data buffer to store read data */ DWORD sector, /* Start sector in LBA */ UINT count /* Number of sectors to read */ ) { DRESULT res; struct disk_dev *pdev = &disk.dev[pdrv]; res = pdev->drv->read(pdev->lun, buff, sector, count); return res; } /** * @brief Writes Sector(s) * @param pdrv: Physical drive number (0..) * @param *buff: Data to be written * @param sector: Sector address (LBA) * @param count: Number of sectors to write (1..128) * @retval DRESULT: Operation result */ DRESULT disk_write ( BYTE pdrv, /* Physical drive nmuber to identify the drive */ const BYTE *buff, /* Data to be written */ DWORD sector, /* Start sector in LBA */ UINT count /* Number of sectors to write */ ) { DRESULT res; struct disk_dev *pdev = &disk.dev[pdrv]; res = pdev->drv->write(pdev->lun, buff, sector, count); return res; } /** * @brief I/O control operation * @param pdrv: Physical drive number (0..) * @param cmd: Control code * @param *buff: Buffer to send/receive control data * @retval DRESULT: Operation result */ DRESULT disk_ioctl ( BYTE pdrv, /* Physical drive nmuber (0..) */ BYTE cmd, /* Control code */ void *buff /* Buffer to send/receive control data */ ) { DRESULT res; struct disk_dev *pdev = &disk.dev[pdrv]; res = pdev->drv->ioctl(pdev->lun, cmd, buff); return res; } ================================================ FILE: Huawei_LiteOS/components/fs/fatfs/ff13b/source/diskio.h ================================================ /*-----------------------------------------------------------------------/ / Low level disk interface modlue include file (C)ChaN, 2014 / /-----------------------------------------------------------------------*/ #ifndef _DISKIO_DEFINED #define _DISKIO_DEFINED #ifdef __cplusplus extern "C" { #endif #include "integer.h" /* Status of Disk Functions */ typedef BYTE DSTATUS; /* Results of Disk Functions */ typedef enum { RES_OK = 0, /* 0: Successful */ RES_ERROR, /* 1: R/W Error */ RES_WRPRT, /* 2: Write Protected */ RES_NOTRDY, /* 3: Not Ready */ RES_PARERR /* 4: Invalid Parameter */ } DRESULT; /*---------------------------------------*/ /* Prototypes for disk control functions */ DSTATUS disk_initialize (BYTE pdrv); DSTATUS disk_status (BYTE pdrv); DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count); DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count); DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff); /* Disk Status Bits (DSTATUS) */ #define STA_NOINIT 0x01 /* Drive not initialized */ #define STA_NODISK 0x02 /* No medium in the drive */ #define STA_PROTECT 0x04 /* Write protected */ /* Command code for disk_ioctrl fucntion */ /* Generic command (Used by FatFs) */ #define CTRL_SYNC 0 /* Complete pending write process (needed at FF_FS_READONLY == 0) */ #define GET_SECTOR_COUNT 1 /* Get media size (needed at FF_USE_MKFS == 1) */ #define GET_SECTOR_SIZE 2 /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */ #define GET_BLOCK_SIZE 3 /* Get erase block size (needed at FF_USE_MKFS == 1) */ #define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */ /* Generic command (Not used by FatFs) */ #define CTRL_POWER 5 /* Get/Set power status */ #define CTRL_LOCK 6 /* Lock/Unlock media removal */ #define CTRL_EJECT 7 /* Eject media */ #define CTRL_FORMAT 8 /* Create physical format on the media */ /* MMC/SDC specific ioctl command */ #define MMC_GET_TYPE 10 /* Get card type */ #define MMC_GET_CSD 11 /* Get CSD */ #define MMC_GET_CID 12 /* Get CID */ #define MMC_GET_OCR 13 /* Get OCR */ #define MMC_GET_SDSTAT 14 /* Get SD status */ #define ISDIO_READ 55 /* Read data form SD iSDIO register */ #define ISDIO_WRITE 56 /* Write data to SD iSDIO register */ #define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */ /* ATA/CF specific ioctl command */ #define ATA_GET_REV 20 /* Get F/W revision */ #define ATA_GET_MODEL 21 /* Get model name */ #define ATA_GET_SN 22 /* Get serial number */ #ifdef __cplusplus } #endif #endif ================================================ FILE: Huawei_LiteOS/components/fs/fatfs/ff13b/source/ff.c ================================================ /*----------------------------------------------------------------------------/ / FatFs - Generic FAT Filesystem Module R0.13b / /-----------------------------------------------------------------------------/ / / Copyright (C) 2018, ChaN, all right reserved. / / FatFs module is an open source software. Redistribution and use of FatFs in / source and binary forms, with or without modification, are permitted provided / that the following condition is met: / / 1. Redistributions of source code must retain the above copyright notice, / this condition and the following disclaimer. / / This software is provided by the copyright holder and contributors "AS IS" / and any warranties related to this software are DISCLAIMED. / The copyright owner or contributors be NOT LIABLE for any damages caused / by use of this software. / /----------------------------------------------------------------------------*/ #include "ff.h" /* Declarations of FatFs API */ #include "diskio.h" /* Declarations of device I/O functions */ /*-------------------------------------------------------------------------- Module Private Definitions ---------------------------------------------------------------------------*/ #if FF_DEFINED != 63463 /* Revision ID */ #error Wrong include file (ff.h). #endif /* Character code support macros */ #define IsUpper(c) ((c) >= 'A' && (c) <= 'Z') #define IsLower(c) ((c) >= 'a' && (c) <= 'z') #define IsDigit(c) ((c) >= '0' && (c) <= '9') #define IsSurrogate(c) ((c) >= 0xD800 && (c) <= 0xDFFF) #define IsSurrogateH(c) ((c) >= 0xD800 && (c) <= 0xDBFF) #define IsSurrogateL(c) ((c) >= 0xDC00 && (c) <= 0xDFFF) /* Additional file attribute bits for internal use */ #define AM_VOL 0x08 /* Volume label */ #define AM_LFN 0x0F /* LFN entry */ #define AM_MASK 0x3F /* Mask of defined bits */ /* Additional file access control and file status flags for internal use */ #define FA_SEEKEND 0x20 /* Seek to end of the file on file open */ #define FA_MODIFIED 0x40 /* File has been modified */ #define FA_DIRTY 0x80 /* FIL.buf[] needs to be written-back */ /* Name status flags in fn[11] */ #define NSFLAG 11 /* Index of the name status byte */ #define NS_LOSS 0x01 /* Out of 8.3 format */ #define NS_LFN 0x02 /* Force to create LFN entry */ #define NS_LAST 0x04 /* Last segment */ #define NS_BODY 0x08 /* Lower case flag (body) */ #define NS_EXT 0x10 /* Lower case flag (ext) */ #define NS_DOT 0x20 /* Dot entry */ #define NS_NOLFN 0x40 /* Do not find LFN */ #define NS_NONAME 0x80 /* Not followed */ /* Limits and boundaries */ #define MAX_DIR 0x200000 /* Max size of FAT directory */ #define MAX_DIR_EX 0x10000000 /* Max size of exFAT directory */ #define MAX_FAT12 0xFF5 /* Max FAT12 clusters (differs from specs, but right for real DOS/Windows behavior) */ #define MAX_FAT16 0xFFF5 /* Max FAT16 clusters (differs from specs, but right for real DOS/Windows behavior) */ #define MAX_FAT32 0x0FFFFFF5 /* Max FAT32 clusters (not specified, practical limit) */ #define MAX_EXFAT 0x7FFFFFFD /* Max exFAT clusters (differs from specs, implementation limit) */ /* FatFs refers the FAT structure as simple byte array instead of structure member / because the C structure is not binary compatible between different platforms */ #define BS_JmpBoot 0 /* x86 jump instruction (3-byte) */ #define BS_OEMName 3 /* OEM name (8-byte) */ #define BPB_BytsPerSec 11 /* Sector size [byte] (WORD) */ #define BPB_SecPerClus 13 /* Cluster size [sector] (BYTE) */ #define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (WORD) */ #define BPB_NumFATs 16 /* Number of FATs (BYTE) */ #define BPB_RootEntCnt 17 /* Size of root directory area for FAT [entry] (WORD) */ #define BPB_TotSec16 19 /* Volume size (16-bit) [sector] (WORD) */ #define BPB_Media 21 /* Media descriptor byte (BYTE) */ #define BPB_FATSz16 22 /* FAT size (16-bit) [sector] (WORD) */ #define BPB_SecPerTrk 24 /* Number of sectors per track for int13h [sector] (WORD) */ #define BPB_NumHeads 26 /* Number of heads for int13h (WORD) */ #define BPB_HiddSec 28 /* Volume offset from top of the drive (DWORD) */ #define BPB_TotSec32 32 /* Volume size (32-bit) [sector] (DWORD) */ #define BS_DrvNum 36 /* Physical drive number for int13h (BYTE) */ #define BS_NTres 37 /* WindowsNT error flag (BYTE) */ #define BS_BootSig 38 /* Extended boot signature (BYTE) */ #define BS_VolID 39 /* Volume serial number (DWORD) */ #define BS_VolLab 43 /* Volume label string (8-byte) */ #define BS_FilSysType 54 /* Filesystem type string (8-byte) */ #define BS_BootCode 62 /* Boot code (448-byte) */ #define BS_55AA 510 /* Signature word (WORD) */ #define BPB_FATSz32 36 /* FAT32: FAT size [sector] (DWORD) */ #define BPB_ExtFlags32 40 /* FAT32: Extended flags (WORD) */ #define BPB_FSVer32 42 /* FAT32: Filesystem version (WORD) */ #define BPB_RootClus32 44 /* FAT32: Root directory cluster (DWORD) */ #define BPB_FSInfo32 48 /* FAT32: Offset of FSINFO sector (WORD) */ #define BPB_BkBootSec32 50 /* FAT32: Offset of backup boot sector (WORD) */ #define BS_DrvNum32 64 /* FAT32: Physical drive number for int13h (BYTE) */ #define BS_NTres32 65 /* FAT32: Error flag (BYTE) */ #define BS_BootSig32 66 /* FAT32: Extended boot signature (BYTE) */ #define BS_VolID32 67 /* FAT32: Volume serial number (DWORD) */ #define BS_VolLab32 71 /* FAT32: Volume label string (8-byte) */ #define BS_FilSysType32 82 /* FAT32: Filesystem type string (8-byte) */ #define BS_BootCode32 90 /* FAT32: Boot code (420-byte) */ #define BPB_ZeroedEx 11 /* exFAT: MBZ field (53-byte) */ #define BPB_VolOfsEx 64 /* exFAT: Volume offset from top of the drive [sector] (QWORD) */ #define BPB_TotSecEx 72 /* exFAT: Volume size [sector] (QWORD) */ #define BPB_FatOfsEx 80 /* exFAT: FAT offset from top of the volume [sector] (DWORD) */ #define BPB_FatSzEx 84 /* exFAT: FAT size [sector] (DWORD) */ #define BPB_DataOfsEx 88 /* exFAT: Data offset from top of the volume [sector] (DWORD) */ #define BPB_NumClusEx 92 /* exFAT: Number of clusters (DWORD) */ #define BPB_RootClusEx 96 /* exFAT: Root directory start cluster (DWORD) */ #define BPB_VolIDEx 100 /* exFAT: Volume serial number (DWORD) */ #define BPB_FSVerEx 104 /* exFAT: Filesystem version (WORD) */ #define BPB_VolFlagEx 106 /* exFAT: Volume flags (WORD) */ #define BPB_BytsPerSecEx 108 /* exFAT: Log2 of sector size in unit of byte (BYTE) */ #define BPB_SecPerClusEx 109 /* exFAT: Log2 of cluster size in unit of sector (BYTE) */ #define BPB_NumFATsEx 110 /* exFAT: Number of FATs (BYTE) */ #define BPB_DrvNumEx 111 /* exFAT: Physical drive number for int13h (BYTE) */ #define BPB_PercInUseEx 112 /* exFAT: Percent in use (BYTE) */ #define BPB_RsvdEx 113 /* exFAT: Reserved (7-byte) */ #define BS_BootCodeEx 120 /* exFAT: Boot code (390-byte) */ #define DIR_Name 0 /* Short file name (11-byte) */ #define DIR_Attr 11 /* Attribute (BYTE) */ #define DIR_NTres 12 /* Lower case flag (BYTE) */ #define DIR_CrtTime10 13 /* Created time sub-second (BYTE) */ #define DIR_CrtTime 14 /* Created time (DWORD) */ #define DIR_LstAccDate 18 /* Last accessed date (WORD) */ #define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (WORD) */ #define DIR_ModTime 22 /* Modified time (DWORD) */ #define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (WORD) */ #define DIR_FileSize 28 /* File size (DWORD) */ #define LDIR_Ord 0 /* LFN: LFN order and LLE flag (BYTE) */ #define LDIR_Attr 11 /* LFN: LFN attribute (BYTE) */ #define LDIR_Type 12 /* LFN: Entry type (BYTE) */ #define LDIR_Chksum 13 /* LFN: Checksum of the SFN (BYTE) */ #define LDIR_FstClusLO 26 /* LFN: MBZ field (WORD) */ #define XDIR_Type 0 /* exFAT: Type of exFAT directory entry (BYTE) */ #define XDIR_NumLabel 1 /* exFAT: Number of volume label characters (BYTE) */ #define XDIR_Label 2 /* exFAT: Volume label (11-WORD) */ #define XDIR_CaseSum 4 /* exFAT: Sum of case conversion table (DWORD) */ #define XDIR_NumSec 1 /* exFAT: Number of secondary entries (BYTE) */ #define XDIR_SetSum 2 /* exFAT: Sum of the set of directory entries (WORD) */ #define XDIR_Attr 4 /* exFAT: File attribute (WORD) */ #define XDIR_CrtTime 8 /* exFAT: Created time (DWORD) */ #define XDIR_ModTime 12 /* exFAT: Modified time (DWORD) */ #define XDIR_AccTime 16 /* exFAT: Last accessed time (DWORD) */ #define XDIR_CrtTime10 20 /* exFAT: Created time subsecond (BYTE) */ #define XDIR_ModTime10 21 /* exFAT: Modified time subsecond (BYTE) */ #define XDIR_CrtTZ 22 /* exFAT: Created timezone (BYTE) */ #define XDIR_ModTZ 23 /* exFAT: Modified timezone (BYTE) */ #define XDIR_AccTZ 24 /* exFAT: Last accessed timezone (BYTE) */ #define XDIR_GenFlags 33 /* exFAT: General secondary flags (BYTE) */ #define XDIR_NumName 35 /* exFAT: Number of file name characters (BYTE) */ #define XDIR_NameHash 36 /* exFAT: Hash of file name (WORD) */ #define XDIR_ValidFileSize 40 /* exFAT: Valid file size (QWORD) */ #define XDIR_FstClus 52 /* exFAT: First cluster of the file data (DWORD) */ #define XDIR_FileSize 56 /* exFAT: File/Directory size (QWORD) */ #define SZDIRE 32 /* Size of a directory entry */ #define DDEM 0xE5 /* Deleted directory entry mark set to DIR_Name[0] */ #define RDDEM 0x05 /* Replacement of the character collides with DDEM */ #define LLEF 0x40 /* Last long entry flag in LDIR_Ord */ #define FSI_LeadSig 0 /* FAT32 FSI: Leading signature (DWORD) */ #define FSI_StrucSig 484 /* FAT32 FSI: Structure signature (DWORD) */ #define FSI_Free_Count 488 /* FAT32 FSI: Number of free clusters (DWORD) */ #define FSI_Nxt_Free 492 /* FAT32 FSI: Last allocated cluster (DWORD) */ #define MBR_Table 446 /* MBR: Offset of partition table in the MBR */ #define SZ_PTE 16 /* MBR: Size of a partition table entry */ #define PTE_Boot 0 /* MBR PTE: Boot indicator */ #define PTE_StHead 1 /* MBR PTE: Start head */ #define PTE_StSec 2 /* MBR PTE: Start sector */ #define PTE_StCyl 3 /* MBR PTE: Start cylinder */ #define PTE_System 4 /* MBR PTE: System ID */ #define PTE_EdHead 5 /* MBR PTE: End head */ #define PTE_EdSec 6 /* MBR PTE: End sector */ #define PTE_EdCyl 7 /* MBR PTE: End cylinder */ #define PTE_StLba 8 /* MBR PTE: Start in LBA */ #define PTE_SizLba 12 /* MBR PTE: Size in LBA */ /* Post process on fatal error in the file operations */ #define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); } /* Re-entrancy related */ #if FF_FS_REENTRANT #if FF_USE_LFN == 1 #error Static LFN work area cannot be used at thread-safe configuration #endif #define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } #else #define LEAVE_FF(fs, res) return res #endif /* Definitions of volume - physical location conversion */ #if FF_MULTI_PARTITION #define LD2PD(vol) VolToPart[vol].pd /* Get physical drive number */ #define LD2PT(vol) VolToPart[vol].pt /* Get partition index */ #else #define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */ #define LD2PT(vol) 0 /* Find first valid partition or in SFD */ #endif /* Definitions of sector size */ #if (FF_MAX_SS < FF_MIN_SS) || (FF_MAX_SS != 512 && FF_MAX_SS != 1024 && FF_MAX_SS != 2048 && FF_MAX_SS != 4096) || (FF_MIN_SS != 512 && FF_MIN_SS != 1024 && FF_MIN_SS != 2048 && FF_MIN_SS != 4096) #error Wrong sector size configuration #endif #if FF_MAX_SS == FF_MIN_SS #define SS(fs) ((UINT)FF_MAX_SS) /* Fixed sector size */ #else #define SS(fs) ((fs)->ssize) /* Variable sector size */ #endif /* Timestamp */ #if FF_FS_NORTC == 1 #if FF_NORTC_YEAR < 1980 || FF_NORTC_YEAR > 2107 || FF_NORTC_MON < 1 || FF_NORTC_MON > 12 || FF_NORTC_MDAY < 1 || FF_NORTC_MDAY > 31 #error Invalid FF_FS_NORTC settings #endif #define GET_FATTIME() ((DWORD)(FF_NORTC_YEAR - 1980) << 25 | (DWORD)FF_NORTC_MON << 21 | (DWORD)FF_NORTC_MDAY << 16) #else #define GET_FATTIME() get_fattime() #endif /* File lock controls */ #if FF_FS_LOCK != 0 #if FF_FS_READONLY #error FF_FS_LOCK must be 0 at read-only configuration #endif typedef struct { FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */ DWORD clu; /* Object ID 2, containing directory (0:root) */ DWORD ofs; /* Object ID 3, offset in the directory */ WORD ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */ } FILESEM; #endif /* SBCS up-case tables (\x80-\xFF) */ #define TBL_CT437 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT720 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT737 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ 0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT771 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF} #define TBL_CT775 {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \ 0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT850 {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \ 0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \ 0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT852 {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \ 0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \ 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} #define TBL_CT855 {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \ 0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \ 0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} #define TBL_CT857 {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \ 0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT860 {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \ 0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ 0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT861 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \ 0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ 0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT862 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT863 {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \ 0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \ 0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT864 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT865 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT866 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} #define TBL_CT869 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \ 0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \ 0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \ 0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF} /* DBCS code range |----- 1st byte -----| |----------- 2nd byte -----------| */ #define TBL_DC932 {0x81, 0x9F, 0xE0, 0xFC, 0x40, 0x7E, 0x80, 0xFC, 0x00, 0x00} #define TBL_DC936 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0x80, 0xFE, 0x00, 0x00} #define TBL_DC949 {0x81, 0xFE, 0x00, 0x00, 0x41, 0x5A, 0x61, 0x7A, 0x81, 0xFE} #define TBL_DC950 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0xA1, 0xFE, 0x00, 0x00} /* Macros for table definitions */ #define MERGE_2STR(a, b) a ## b #define MKCVTBL(hd, cp) MERGE_2STR(hd, cp) /*-------------------------------------------------------------------------- Module Private Work Area ---------------------------------------------------------------------------*/ /* Remark: Variables defined here without initial value shall be guaranteed / zero/null at start-up. If not, the linker option or start-up routine is / not compliance with C standard. */ /*--------------------------------*/ /* File/Volume controls */ /*--------------------------------*/ #if FF_VOLUMES < 1 || FF_VOLUMES > 10 #error Wrong FF_VOLUMES setting #endif static FATFS* FatFs[FF_VOLUMES]; /* Pointer to the filesystem objects (logical drives) */ static WORD Fsid; /* Filesystem mount ID */ #if FF_FS_RPATH != 0 static BYTE CurrVol; /* Current drive */ #endif #if FF_FS_LOCK != 0 static FILESEM Files[FF_FS_LOCK]; /* Open object lock semaphores */ #endif #if FF_STR_VOLUME_ID #ifdef FF_VOLUME_STRS static const char* const VolumeStr[FF_VOLUMES] = {FF_VOLUME_STRS}; /* Pre-defined volume ID */ #endif #endif /*--------------------------------*/ /* LFN/Directory working buffer */ /*--------------------------------*/ #if FF_USE_LFN == 0 /* Non-LFN configuration */ #if FF_FS_EXFAT #error LFN must be enabled when enable exFAT #endif #define DEF_NAMBUF #define INIT_NAMBUF(fs) #define FREE_NAMBUF() #define LEAVE_MKFS(res) return res #else /* LFN configurations */ #if FF_MAX_LFN < 12 || FF_MAX_LFN > 255 #error Wrong setting of FF_MAX_LFN #endif #if FF_LFN_BUF < FF_SFN_BUF || FF_SFN_BUF < 12 #error Wrong setting of FF_LFN_BUF or FF_SFN_BUF #endif #if FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3 #error Wrong setting of FF_LFN_UNICODE #endif static const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* FAT: Offset of LFN characters in the directory entry */ #define MAXDIRB(nc) ((nc + 44U) / 15 * SZDIRE) /* exFAT: Size of directory entry block scratchpad buffer needed for the name length */ #if FF_USE_LFN == 1 /* LFN enabled with static working buffer */ #if FF_FS_EXFAT static BYTE DirBuf[MAXDIRB(FF_MAX_LFN)]; /* Directory entry block scratchpad buffer */ #endif static WCHAR LfnBuf[FF_MAX_LFN + 1]; /* LFN working buffer */ #define DEF_NAMBUF #define INIT_NAMBUF(fs) #define FREE_NAMBUF() #define LEAVE_MKFS(res) return res #elif FF_USE_LFN == 2 /* LFN enabled with dynamic working buffer on the stack */ #if FF_FS_EXFAT #define DEF_NAMBUF WCHAR lbuf[FF_MAX_LFN+1]; BYTE dbuf[MAXDIRB(FF_MAX_LFN)]; /* LFN working buffer and directory entry block scratchpad buffer */ #define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; } #define FREE_NAMBUF() #else #define DEF_NAMBUF WCHAR lbuf[FF_MAX_LFN+1]; /* LFN working buffer */ #define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; } #define FREE_NAMBUF() #endif #define LEAVE_MKFS(res) return res #elif FF_USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */ #if FF_FS_EXFAT #define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer and directory entry block scratchpad buffer */ #define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); } #define FREE_NAMBUF() ff_memfree(lfn) #else #define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer */ #define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; } #define FREE_NAMBUF() ff_memfree(lfn) #endif #define LEAVE_MKFS(res) { if (!work) ff_memfree(buf); return res; } #define MAX_MALLOC 0x8000 /* Must be >=FF_MAX_SS */ #else #error Wrong setting of FF_USE_LFN #endif /* FF_USE_LFN == 1 */ #endif /* FF_USE_LFN == 0 */ /*--------------------------------*/ /* Code conversion tables */ /*--------------------------------*/ #if FF_CODE_PAGE == 0 /* Run-time code page configuration */ #define CODEPAGE CodePage static WORD CodePage; /* Current code page */ static const BYTE *ExCvt, *DbcTbl; /* Pointer to current SBCS up-case table and DBCS code range table below */ static const BYTE Ct437[] = TBL_CT437; static const BYTE Ct720[] = TBL_CT720; static const BYTE Ct737[] = TBL_CT737; static const BYTE Ct771[] = TBL_CT771; static const BYTE Ct775[] = TBL_CT775; static const BYTE Ct850[] = TBL_CT850; static const BYTE Ct852[] = TBL_CT852; static const BYTE Ct855[] = TBL_CT855; static const BYTE Ct857[] = TBL_CT857; static const BYTE Ct860[] = TBL_CT860; static const BYTE Ct861[] = TBL_CT861; static const BYTE Ct862[] = TBL_CT862; static const BYTE Ct863[] = TBL_CT863; static const BYTE Ct864[] = TBL_CT864; static const BYTE Ct865[] = TBL_CT865; static const BYTE Ct866[] = TBL_CT866; static const BYTE Ct869[] = TBL_CT869; static const BYTE Dc932[] = TBL_DC932; static const BYTE Dc936[] = TBL_DC936; static const BYTE Dc949[] = TBL_DC949; static const BYTE Dc950[] = TBL_DC950; #elif FF_CODE_PAGE < 900 /* Static code page configuration (SBCS) */ #define CODEPAGE FF_CODE_PAGE static const BYTE ExCvt[] = MKCVTBL(TBL_CT, FF_CODE_PAGE); #else /* Static code page configuration (DBCS) */ #define CODEPAGE FF_CODE_PAGE static const BYTE DbcTbl[] = MKCVTBL(TBL_DC, FF_CODE_PAGE); #endif /*-------------------------------------------------------------------------- Module Private Functions ---------------------------------------------------------------------------*/ /*-----------------------------------------------------------------------*/ /* Load/Store multi-byte word in the FAT structure */ /*-----------------------------------------------------------------------*/ static WORD ld_word (const BYTE* ptr) /* Load a 2-byte little-endian word */ { WORD rv; rv = ptr[1]; rv = rv << 8 | ptr[0]; return rv; } static DWORD ld_dword (const BYTE* ptr) /* Load a 4-byte little-endian word */ { DWORD rv; rv = ptr[3]; rv = rv << 8 | ptr[2]; rv = rv << 8 | ptr[1]; rv = rv << 8 | ptr[0]; return rv; } #if FF_FS_EXFAT static QWORD ld_qword (const BYTE* ptr) /* Load an 8-byte little-endian word */ { QWORD rv; rv = ptr[7]; rv = rv << 8 | ptr[6]; rv = rv << 8 | ptr[5]; rv = rv << 8 | ptr[4]; rv = rv << 8 | ptr[3]; rv = rv << 8 | ptr[2]; rv = rv << 8 | ptr[1]; rv = rv << 8 | ptr[0]; return rv; } #endif #if !FF_FS_READONLY static void st_word (BYTE* ptr, WORD val) /* Store a 2-byte word in little-endian */ { *ptr++ = (BYTE)val; val >>= 8; *ptr++ = (BYTE)val; } static void st_dword (BYTE* ptr, DWORD val) /* Store a 4-byte word in little-endian */ { *ptr++ = (BYTE)val; val >>= 8; *ptr++ = (BYTE)val; val >>= 8; *ptr++ = (BYTE)val; val >>= 8; *ptr++ = (BYTE)val; } #if FF_FS_EXFAT static void st_qword (BYTE* ptr, QWORD val) /* Store an 8-byte word in little-endian */ { *ptr++ = (BYTE)val; val >>= 8; *ptr++ = (BYTE)val; val >>= 8; *ptr++ = (BYTE)val; val >>= 8; *ptr++ = (BYTE)val; val >>= 8; *ptr++ = (BYTE)val; val >>= 8; *ptr++ = (BYTE)val; val >>= 8; *ptr++ = (BYTE)val; val >>= 8; *ptr++ = (BYTE)val; } #endif #endif /* !FF_FS_READONLY */ /*-----------------------------------------------------------------------*/ /* String functions */ /*-----------------------------------------------------------------------*/ /* Copy memory to memory */ static void mem_cpy (void* dst, const void* src, UINT cnt) { BYTE *d = (BYTE*)dst; const BYTE *s = (const BYTE*)src; if (cnt != 0) { do { *d++ = *s++; } while (--cnt); } } /* Fill memory block */ static void mem_set (void* dst, int val, UINT cnt) { BYTE *d = (BYTE*)dst; do { *d++ = (BYTE)val; } while (--cnt); } /* Compare memory block */ static int mem_cmp (const void* dst, const void* src, UINT cnt) /* ZR:same, NZ:different */ { const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; int r = 0; do { r = *d++ - *s++; } while (--cnt && r == 0); return r; } /* Check if chr is contained in the string */ static int chk_chr (const char* str, int chr) /* NZ:contained, ZR:not contained */ { while (*str && *str != chr) str++; return *str; } /* Test if the character is DBC 1st byte */ static int dbc_1st (BYTE c) { #if FF_CODE_PAGE == 0 /* Variable code page */ if (DbcTbl && c >= DbcTbl[0]) { if (c <= DbcTbl[1]) return 1; /* 1st byte range 1 */ if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1; /* 1st byte range 2 */ } #elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */ if (c >= DbcTbl[0]) { if (c <= DbcTbl[1]) return 1; if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1; } #else /* SBCS fixed code page */ if (c != 0) return 0; /* Always false */ #endif return 0; } /* Test if the character is DBC 2nd byte */ static int dbc_2nd (BYTE c) { #if FF_CODE_PAGE == 0 /* Variable code page */ if (DbcTbl && c >= DbcTbl[4]) { if (c <= DbcTbl[5]) return 1; /* 2nd byte range 1 */ if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1; /* 2nd byte range 2 */ if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1; /* 2nd byte range 3 */ } #elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */ if (c >= DbcTbl[4]) { if (c <= DbcTbl[5]) return 1; if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1; if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1; } #else /* SBCS fixed code page */ if (c != 0) return 0; /* Always false */ #endif return 0; } #if FF_USE_LFN /* Get a character from TCHAR string in defined API encodeing */ static DWORD tchar2uni ( /* Returns character in UTF-16 encoding (>=0x10000 on double encoding unit, 0xFFFFFFFF on decode error) */ const TCHAR** str /* Pointer to pointer to TCHAR string in configured encoding */ ) { DWORD uc; const TCHAR *p = *str; #if FF_LFN_UNICODE == 1 /* UTF-16 input */ WCHAR wc; uc = *p++; /* Get a unit */ if (IsSurrogate(uc)) { /* Surrogate? */ wc = *p++; /* Get low surrogate */ if (!IsSurrogateH(uc) || !IsSurrogateL(wc)) return 0xFFFFFFFF; /* Wrong surrogate? */ uc = uc << 16 | wc; } #elif FF_LFN_UNICODE == 2 /* UTF-8 input */ BYTE b; int nf; uc = (BYTE)*p++; /* Get a unit */ if (uc & 0x80) { /* Multiple byte code? */ if ((uc & 0xE0) == 0xC0) { /* 2-byte sequence? */ uc &= 0x1F; nf = 1; } else { if ((uc & 0xF0) == 0xE0) { /* 3-byte sequence? */ uc &= 0x0F; nf = 2; } else { if ((uc & 0xF8) == 0xF0) { /* 4-byte sequence? */ uc &= 0x07; nf = 3; } else { /* Wrong sequence */ return 0xFFFFFFFF; } } } do { /* Get trailing bytes */ b = (BYTE)*p++; if ((b & 0xC0) != 0x80) return 0xFFFFFFFF; /* Wrong sequence? */ uc = uc << 6 | (b & 0x3F); } while (--nf != 0); if (uc < 0x80 || IsSurrogate(uc) || uc >= 0x110000) return 0xFFFFFFFF; /* Wrong code? */ if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */ } #elif FF_LFN_UNICODE == 3 /* UTF-32 input */ uc = (TCHAR)*p++; /* Get a unit */ if (uc >= 0x110000) return 0xFFFFFFFF; /* Wrong code? */ if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */ #else /* ANSI/OEM input */ BYTE b; WCHAR wc; wc = (BYTE)*p++; /* Get a byte */ if (dbc_1st((BYTE)wc)) { /* Is it a DBC 1st byte? */ b = (BYTE)*p++; /* Get 2nd byte */ if (!dbc_2nd(b)) return 0xFFFFFFFF; /* Invalid code? */ wc = (wc << 8) + b; /* Make a DBC */ } if (wc != 0) { wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM ==> Unicode */ if (wc == 0) return 0xFFFFFFFF; /* Invalid code? */ } uc = wc; #endif *str = p; /* Next read pointer */ return uc; } /* Output a TCHAR string in defined API encoding */ static BYTE put_utf ( /* Returns number of encoding units written (0:buffer overflow or wrong encoding) */ DWORD chr, /* UTF-16 encoded character (Double encoding unit char if >=0x10000) */ TCHAR* buf, /* Output buffer */ UINT szb /* Size of the buffer */ ) { #if FF_LFN_UNICODE == 1 /* UTF-16 output */ WCHAR hs, wc; hs = (WCHAR)(chr >> 16); wc = (WCHAR)chr; if (hs == 0) { /* Single encoding unit? */ if (szb < 1 || IsSurrogate(wc)) return 0; /* Buffer overflow or wrong code? */ *buf = wc; return 1; } if (szb < 2 || !IsSurrogateH(hs) || !IsSurrogateL(wc)) return 0; /* Buffer overflow or wrong surrogate? */ *buf++ = hs; *buf++ = wc; return 2; #elif FF_LFN_UNICODE == 2 /* UTF-8 output */ DWORD hc; if (chr < 0x80) { /* Single byte code? */ if (szb < 1) return 0; /* Buffer overflow? */ *buf = (TCHAR)chr; return 1; } if (chr < 0x800) { /* 2-byte sequence? */ if (szb < 2) return 0; /* Buffer overflow? */ *buf++ = (TCHAR)(0xC0 | (chr >> 6 & 0x1F)); *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); return 2; } if (chr < 0x10000) { /* 3-byte sequence? */ if (szb < 3 || IsSurrogate(chr)) return 0; /* Buffer overflow or wrong code? */ *buf++ = (TCHAR)(0xE0 | (chr >> 12 & 0x0F)); *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F)); *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); return 3; } /* 4-byte sequence */ if (szb < 4) return 0; /* Buffer overflow? */ hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */ chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */ if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */ chr = (hc | chr) + 0x10000; *buf++ = (TCHAR)(0xF0 | (chr >> 18 & 0x07)); *buf++ = (TCHAR)(0x80 | (chr >> 12 & 0x3F)); *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F)); *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); return 4; #elif FF_LFN_UNICODE == 3 /* UTF-32 output */ DWORD hc; if (szb < 1) return 0; /* Buffer overflow? */ if (chr >= 0x10000) { /* Out of BMP? */ hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */ chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */ if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */ chr = (hc | chr) + 0x10000; } *buf++ = (TCHAR)chr; return 1; #else /* ANSI/OEM output */ WCHAR wc; wc = ff_uni2oem(chr, CODEPAGE); if (wc >= 0x100) { /* Is this a DBC? */ if (szb < 2) return 0; *buf++ = (char)(wc >> 8); /* Store DBC 1st byte */ *buf++ = (TCHAR)wc; /* Store DBC 2nd byte */ return 2; } if (wc == 0 || szb < 1) return 0; /* Invalid char or buffer overflow? */ *buf++ = (TCHAR)wc; /* Store the character */ return 1; #endif } #endif /* FF_USE_LFN */ #if FF_FS_REENTRANT /*-----------------------------------------------------------------------*/ /* Request/Release grant to access the volume */ /*-----------------------------------------------------------------------*/ static int lock_fs ( /* 1:Ok, 0:timeout */ FATFS* fs /* Filesystem object */ ) { return ff_req_grant(fs->sobj); } static void unlock_fs ( FATFS* fs, /* Filesystem object */ FRESULT res /* Result code to be returned */ ) { if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) { ff_rel_grant(fs->sobj); } } #endif #if FF_FS_LOCK != 0 /*-----------------------------------------------------------------------*/ /* File lock control functions */ /*-----------------------------------------------------------------------*/ static FRESULT chk_lock ( /* Check if the file can be accessed */ DIR* dp, /* Directory object pointing the file to be checked */ int acc /* Desired access type (0:Read mode open, 1:Write mode open, 2:Delete or rename) */ ) { UINT i, be; /* Search open object table for the object */ be = 0; for (i = 0; i < FF_FS_LOCK; i++) { if (Files[i].fs) { /* Existing entry */ if (Files[i].fs == dp->obj.fs && /* Check if the object matches with an open object */ Files[i].clu == dp->obj.sclust && Files[i].ofs == dp->dptr) break; } else { /* Blank entry */ be = 1; } } if (i == FF_FS_LOCK) { /* The object has not been opened */ return (!be && acc != 2) ? FR_TOO_MANY_OPEN_FILES : FR_OK; /* Is there a blank entry for new object? */ } /* The object was opened. Reject any open against writing file and all write mode open */ return (acc != 0 || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; } static int enq_lock (void) /* Check if an entry is available for a new object */ { UINT i; for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ; return (i == FF_FS_LOCK) ? 0 : 1; } static UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */ DIR* dp, /* Directory object pointing the file to register or increment */ int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ ) { UINT i; for (i = 0; i < FF_FS_LOCK; i++) { /* Find the object */ if (Files[i].fs == dp->obj.fs && Files[i].clu == dp->obj.sclust && Files[i].ofs == dp->dptr) break; } if (i == FF_FS_LOCK) { /* Not opened. Register it as new. */ for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ; if (i == FF_FS_LOCK) return 0; /* No free entry to register (int err) */ Files[i].fs = dp->obj.fs; Files[i].clu = dp->obj.sclust; Files[i].ofs = dp->dptr; Files[i].ctr = 0; } if (acc >= 1 && Files[i].ctr) return 0; /* Access violation (int err) */ Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ return i + 1; /* Index number origin from 1 */ } static FRESULT dec_lock ( /* Decrement object open counter */ UINT i /* Semaphore index (1..) */ ) { WORD n; FRESULT res; if (--i < FF_FS_LOCK) { /* Index number origin from 0 */ n = Files[i].ctr; if (n == 0x100) n = 0; /* If write mode open, delete the entry */ if (n > 0) n--; /* Decrement read mode open count */ Files[i].ctr = n; if (n == 0) Files[i].fs = 0; /* Delete the entry if open count gets zero */ res = FR_OK; } else { res = FR_INT_ERR; /* Invalid index nunber */ } return res; } static void clear_lock ( /* Clear lock entries of the volume */ FATFS *fs ) { UINT i; for (i = 0; i < FF_FS_LOCK; i++) { if (Files[i].fs == fs) Files[i].fs = 0; } } #endif /* FF_FS_LOCK != 0 */ /*-----------------------------------------------------------------------*/ /* Move/Flush disk access window in the filesystem object */ /*-----------------------------------------------------------------------*/ #if !FF_FS_READONLY static FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERR */ FATFS* fs /* Filesystem object */ ) { FRESULT res = FR_OK; if (fs->wflag) { /* Is the disk access window dirty */ if (disk_write(fs->pdrv, fs->win, fs->winsect, 1) == RES_OK) { /* Write back the window */ fs->wflag = 0; /* Clear window dirty flag */ if (fs->winsect - fs->fatbase < fs->fsize) { /* Is it in the 1st FAT? */ if (fs->n_fats == 2) disk_write(fs->pdrv, fs->win, fs->winsect + fs->fsize, 1); /* Reflect it to 2nd FAT if needed */ } } else { res = FR_DISK_ERR; } } return res; } #endif static FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERR */ FATFS* fs, /* Filesystem object */ DWORD sector /* Sector number to make appearance in the fs->win[] */ ) { FRESULT res = FR_OK; if (sector != fs->winsect) { /* Window offset changed? */ #if !FF_FS_READONLY res = sync_window(fs); /* Write-back changes */ #endif if (res == FR_OK) { /* Fill sector window with new data */ if (disk_read(fs->pdrv, fs->win, sector, 1) != RES_OK) { sector = 0xFFFFFFFF; /* Invalidate window if read data is not valid */ res = FR_DISK_ERR; } fs->winsect = sector; } } return res; } #if !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* Synchronize filesystem and data on the storage */ /*-----------------------------------------------------------------------*/ static FRESULT sync_fs ( /* Returns FR_OK or FR_DISK_ERR */ FATFS* fs /* Filesystem object */ ) { FRESULT res; res = sync_window(fs); if (res == FR_OK) { if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { /* FAT32: Update FSInfo sector if needed */ /* Create FSInfo structure */ mem_set(fs->win, 0, SS(fs)); st_word(fs->win + BS_55AA, 0xAA55); st_dword(fs->win + FSI_LeadSig, 0x41615252); st_dword(fs->win + FSI_StrucSig, 0x61417272); st_dword(fs->win + FSI_Free_Count, fs->free_clst); st_dword(fs->win + FSI_Nxt_Free, fs->last_clst); /* Write it into the FSInfo sector */ fs->winsect = fs->volbase + 1; disk_write(fs->pdrv, fs->win, fs->winsect, 1); fs->fsi_flag = 0; } /* Make sure that no pending write process in the lower layer */ if (disk_ioctl(fs->pdrv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR; } return res; } #endif /*-----------------------------------------------------------------------*/ /* Get physical sector number from cluster number */ /*-----------------------------------------------------------------------*/ static DWORD clst2sect ( /* !=0:Sector number, 0:Failed (invalid cluster#) */ FATFS* fs, /* Filesystem object */ DWORD clst /* Cluster# to be converted */ ) { clst -= 2; /* Cluster number is origin from 2 */ if (clst >= fs->n_fatent - 2) return 0; /* Is it invalid cluster number? */ return fs->database + fs->csize * clst; /* Start sector number of the cluster */ } /*-----------------------------------------------------------------------*/ /* FAT access - Read value of a FAT entry */ /*-----------------------------------------------------------------------*/ static DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */ FFOBJID* obj, /* Corresponding object */ DWORD clst /* Cluster number to get the value */ ) { UINT wc, bc; DWORD val; FATFS *fs = obj->fs; if (clst < 2 || clst >= fs->n_fatent) { /* Check if in valid range */ val = 1; /* Internal error */ } else { val = 0xFFFFFFFF; /* Default value falls on disk error */ switch (fs->fs_type) { case FS_FAT12 : bc = (UINT)clst; bc += bc / 2; if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; wc = fs->win[bc++ % SS(fs)]; /* Get 1st byte of the entry */ if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; wc |= fs->win[bc % SS(fs)] << 8; /* Merge 2nd byte of the entry */ val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); /* Adjust bit position */ break; case FS_FAT16 : if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break; val = ld_word(fs->win + clst * 2 % SS(fs)); /* Simple WORD array */ break; case FS_FAT32 : if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; /* Simple DWORD array but mask out upper 4 bits */ break; #if FF_FS_EXFAT case FS_EXFAT : if ((obj->objsize != 0 && obj->sclust != 0) || obj->stat == 0) { /* Object except root dir must have valid data length */ DWORD cofs = clst - obj->sclust; /* Offset from start cluster */ DWORD clen = (DWORD)((obj->objsize - 1) / SS(fs)) / fs->csize; /* Number of clusters - 1 */ if (obj->stat == 2 && cofs <= clen) { /* Is it a contiguous chain? */ val = (cofs == clen) ? 0x7FFFFFFF : clst + 1; /* No data on the FAT, generate the value */ break; } if (obj->stat == 3 && cofs < obj->n_cont) { /* Is it in the 1st fragment? */ val = clst + 1; /* Generate the value */ break; } if (obj->stat != 2) { /* Get value from FAT if FAT chain is valid */ if (obj->n_frag != 0) { /* Is it on the growing edge? */ val = 0x7FFFFFFF; /* Generate EOC */ } else { if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF; } break; } } /* go to default */ #endif default: val = 1; /* Internal error */ } } return val; } #if !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* FAT access - Change value of a FAT entry */ /*-----------------------------------------------------------------------*/ static FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */ FATFS* fs, /* Corresponding filesystem object */ DWORD clst, /* FAT index number (cluster number) to be changed */ DWORD val /* New value to be set to the entry */ ) { UINT bc; BYTE *p; FRESULT res = FR_INT_ERR; if (clst >= 2 && clst < fs->n_fatent) { /* Check if in valid range */ switch (fs->fs_type) { case FS_FAT12 : bc = (UINT)clst; bc += bc / 2; /* bc: byte offset of the entry */ res = move_window(fs, fs->fatbase + (bc / SS(fs))); if (res != FR_OK) break; p = fs->win + bc++ % SS(fs); *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; /* Put 1st byte */ fs->wflag = 1; res = move_window(fs, fs->fatbase + (bc / SS(fs))); if (res != FR_OK) break; p = fs->win + bc % SS(fs); *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); /* Put 2nd byte */ fs->wflag = 1; break; case FS_FAT16 : res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); if (res != FR_OK) break; st_word(fs->win + clst * 2 % SS(fs), (WORD)val); /* Simple WORD array */ fs->wflag = 1; break; case FS_FAT32 : #if FF_FS_EXFAT case FS_EXFAT : #endif res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); if (res != FR_OK) break; if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000); } st_dword(fs->win + clst * 4 % SS(fs), val); fs->wflag = 1; break; } } return res; } #endif /* !FF_FS_READONLY */ #if FF_FS_EXFAT && !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* exFAT: Accessing FAT and Allocation Bitmap */ /*-----------------------------------------------------------------------*/ /*--------------------------------------*/ /* Find a contiguous free cluster block */ /*--------------------------------------*/ static DWORD find_bitmap ( /* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */ FATFS* fs, /* Filesystem object */ DWORD clst, /* Cluster number to scan from */ DWORD ncl /* Number of contiguous clusters to find (1..) */ ) { BYTE bm, bv; UINT i; DWORD val, scl, ctr; clst -= 2; /* The first bit in the bitmap corresponds to cluster #2 */ if (clst >= fs->n_fatent - 2) clst = 0; scl = val = clst; ctr = 0; for (;;) { if (move_window(fs, fs->database + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF; /* (assuming bitmap is located top of the cluster heap) */ i = val / 8 % SS(fs); bm = 1 << (val % 8); do { do { bv = fs->win[i] & bm; bm <<= 1; /* Get bit value */ if (++val >= fs->n_fatent - 2) { /* Next cluster (with wrap-around) */ val = 0; bm = 0; i = SS(fs); } if (bv == 0) { /* Is it a free cluster? */ if (++ctr == ncl) return scl + 2; /* Check if run length is sufficient for required */ } else { scl = val; ctr = 0; /* Encountered a cluster in-use, restart to scan */ } if (val == clst) return 0; /* All cluster scanned? */ } while (bm != 0); bm = 1; } while (++i < SS(fs)); } } /*----------------------------------------*/ /* Set/Clear a block of allocation bitmap */ /*----------------------------------------*/ static FRESULT change_bitmap ( FATFS* fs, /* Filesystem object */ DWORD clst, /* Cluster number to change from */ DWORD ncl, /* Number of clusters to be changed */ int bv /* bit value to be set (0 or 1) */ ) { BYTE bm; UINT i; DWORD sect; clst -= 2; /* The first bit corresponds to cluster #2 */ sect = fs->database + clst / 8 / SS(fs); /* Sector address (assuming bitmap is located top of the cluster heap) */ i = clst / 8 % SS(fs); /* Byte offset in the sector */ bm = 1 << (clst % 8); /* Bit mask in the byte */ for (;;) { if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR; do { do { if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR; /* Is the bit expected value? */ fs->win[i] ^= bm; /* Flip the bit */ fs->wflag = 1; if (--ncl == 0) return FR_OK; /* All bits processed? */ } while (bm <<= 1); /* Next bit */ bm = 1; } while (++i < SS(fs)); /* Next byte */ i = 0; } } /*---------------------------------------------*/ /* Fill the first fragment of the FAT chain */ /*---------------------------------------------*/ static FRESULT fill_first_frag ( FFOBJID* obj /* Pointer to the corresponding object */ ) { FRESULT res; DWORD cl, n; if (obj->stat == 3) { /* Has the object been changed 'fragmented' in this session? */ for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) { /* Create cluster chain on the FAT */ res = put_fat(obj->fs, cl, cl + 1); if (res != FR_OK) return res; } obj->stat = 0; /* Change status 'FAT chain is valid' */ } return FR_OK; } /*---------------------------------------------*/ /* Fill the last fragment of the FAT chain */ /*---------------------------------------------*/ static FRESULT fill_last_frag ( FFOBJID* obj, /* Pointer to the corresponding object */ DWORD lcl, /* Last cluster of the fragment */ DWORD term /* Value to set the last FAT entry */ ) { FRESULT res; while (obj->n_frag > 0) { /* Create the chain of last fragment */ res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term); if (res != FR_OK) return res; obj->n_frag--; } return FR_OK; } #endif /* FF_FS_EXFAT && !FF_FS_READONLY */ #if !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* FAT handling - Remove a cluster chain */ /*-----------------------------------------------------------------------*/ static FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */ FFOBJID* obj, /* Corresponding object */ DWORD clst, /* Cluster to remove a chain from */ DWORD pclst /* Previous cluster of clst (0:entire chain) */ ) { FRESULT res = FR_OK; DWORD nxt; FATFS *fs = obj->fs; #if FF_FS_EXFAT || FF_USE_TRIM DWORD scl = clst, ecl = clst; #endif #if FF_USE_TRIM DWORD rt[2]; #endif if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Check if in valid range */ /* Mark the previous cluster 'EOC' on the FAT if it exists */ if (pclst != 0 && (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) { res = put_fat(fs, pclst, 0xFFFFFFFF); if (res != FR_OK) return res; } /* Remove the chain */ do { nxt = get_fat(obj, clst); /* Get cluster status */ if (nxt == 0) break; /* Empty cluster? */ if (nxt == 1) return FR_INT_ERR; /* Internal error? */ if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */ if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { res = put_fat(fs, clst, 0); /* Mark the cluster 'free' on the FAT */ if (res != FR_OK) return res; } if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */ fs->free_clst++; fs->fsi_flag |= 1; } #if FF_FS_EXFAT || FF_USE_TRIM if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ ecl = nxt; } else { /* End of contiguous cluster block */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { res = change_bitmap(fs, scl, ecl - scl + 1, 0); /* Mark the cluster block 'free' on the bitmap */ if (res != FR_OK) return res; } #endif #if FF_USE_TRIM rt[0] = clst2sect(fs, scl); /* Start of data area freed */ rt[1] = clst2sect(fs, ecl) + fs->csize - 1; /* End of data area freed */ disk_ioctl(fs->pdrv, CTRL_TRIM, rt); /* Inform device the data in the block is no longer needed */ #endif scl = ecl = nxt; } #endif clst = nxt; /* Next cluster */ } while (clst < fs->n_fatent); /* Repeat while not the last link */ #if FF_FS_EXFAT /* Some post processes for chain status */ if (fs->fs_type == FS_EXFAT) { if (pclst == 0) { /* Has the entire chain been removed? */ obj->stat = 0; /* Change the chain status 'initial' */ } else { if (obj->stat == 0) { /* Is it a fragmented chain from the beginning of this session? */ clst = obj->sclust; /* Follow the chain to check if it gets contiguous */ while (clst != pclst) { nxt = get_fat(obj, clst); if (nxt < 2) return FR_INT_ERR; if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; if (nxt != clst + 1) break; /* Not contiguous? */ clst++; } if (clst == pclst) { /* Has the chain got contiguous again? */ obj->stat = 2; /* Change the chain status 'contiguous' */ } } else { if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) { /* Was the chain fragmented in this session and got contiguous again? */ obj->stat = 2; /* Change the chain status 'contiguous' */ } } } } #endif return FR_OK; } /*-----------------------------------------------------------------------*/ /* FAT handling - Stretch a chain or Create a new chain */ /*-----------------------------------------------------------------------*/ static DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ FFOBJID* obj, /* Corresponding object */ DWORD clst /* Cluster# to stretch, 0:Create a new chain */ ) { DWORD cs, ncl, scl; FRESULT res; FATFS *fs = obj->fs; if (clst == 0) { /* Create a new chain */ scl = fs->last_clst; /* Suggested cluster to start to find */ if (scl == 0 || scl >= fs->n_fatent) scl = 1; } else { /* Stretch a chain */ cs = get_fat(obj, clst); /* Check the cluster status */ if (cs < 2) return 1; /* Test for insanity */ if (cs == 0xFFFFFFFF) return cs; /* Test for disk error */ if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ scl = clst; /* Cluster to start to find */ } if (fs->free_clst == 0) return 0; /* No free cluster */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ ncl = find_bitmap(fs, scl, 1); /* Find a free cluster */ if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl; /* No free cluster or hard error? */ res = change_bitmap(fs, ncl, 1, 1); /* Mark the cluster 'in use' */ if (res == FR_INT_ERR) return 1; if (res == FR_DISK_ERR) return 0xFFFFFFFF; if (clst == 0) { /* Is it a new chain? */ obj->stat = 2; /* Set status 'contiguous' */ } else { /* It is a stretched chain */ if (obj->stat == 2 && ncl != scl + 1) { /* Is the chain got fragmented? */ obj->n_cont = scl - obj->sclust; /* Set size of the contiguous part */ obj->stat = 3; /* Change status 'just fragmented' */ } } if (obj->stat != 2) { /* Is the file non-contiguous? */ if (ncl == clst + 1) { /* Is the cluster next to previous one? */ obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2; /* Increment size of last framgent */ } else { /* New fragment */ if (obj->n_frag == 0) obj->n_frag = 1; res = fill_last_frag(obj, clst, ncl); /* Fill last fragment on the FAT and link it to new one */ if (res == FR_OK) obj->n_frag = 1; } } } else #endif { /* On the FAT/FAT32 volume */ ncl = 0; if (scl == clst) { /* Stretching an existing chain? */ ncl = scl + 1; /* Test if next cluster is free */ if (ncl >= fs->n_fatent) ncl = 2; cs = get_fat(obj, ncl); /* Get next cluster status */ if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */ if (cs != 0) { /* Not free? */ cs = fs->last_clst; /* Start at suggested cluster if it is valid */ if (cs >= 2 && cs < fs->n_fatent) scl = cs; ncl = 0; } } if (ncl == 0) { /* The new cluster cannot be contiguous and find another fragment */ ncl = scl; /* Start cluster */ for (;;) { ncl++; /* Next cluster */ if (ncl >= fs->n_fatent) { /* Check wrap-around */ ncl = 2; if (ncl > scl) return 0; /* No free cluster found? */ } cs = get_fat(obj, ncl); /* Get the cluster status */ if (cs == 0) break; /* Found a free cluster? */ if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */ if (ncl == scl) return 0; /* No free cluster found? */ } } res = put_fat(fs, ncl, 0xFFFFFFFF); /* Mark the new cluster 'EOC' */ if (res == FR_OK && clst != 0) { res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */ } } if (res == FR_OK) { /* Update FSINFO if function succeeded. */ fs->last_clst = ncl; if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--; fs->fsi_flag |= 1; } else { ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; /* Failed. Generate error status */ } return ncl; /* Return new cluster number or error status */ } #endif /* !FF_FS_READONLY */ #if FF_USE_FASTSEEK /*-----------------------------------------------------------------------*/ /* FAT handling - Convert offset into cluster with link map table */ /*-----------------------------------------------------------------------*/ static DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ FIL* fp, /* Pointer to the file object */ FSIZE_t ofs /* File offset to be converted to cluster# */ ) { DWORD cl, ncl, *tbl; FATFS *fs = fp->obj.fs; tbl = fp->cltbl + 1; /* Top of CLMT */ cl = (DWORD)(ofs / SS(fs) / fs->csize); /* Cluster order from top of the file */ for (;;) { ncl = *tbl++; /* Number of cluters in the fragment */ if (ncl == 0) return 0; /* End of table? (error) */ if (cl < ncl) break; /* In this fragment? */ cl -= ncl; tbl++; /* Next fragment */ } return cl + *tbl; /* Return the cluster number */ } #endif /* FF_USE_FASTSEEK */ /*-----------------------------------------------------------------------*/ /* Directory handling - Fill a cluster with zeros */ /*-----------------------------------------------------------------------*/ #if !FF_FS_READONLY static FRESULT dir_clear ( /* Returns FR_OK or FR_DISK_ERR */ FATFS *fs, /* Filesystem object */ DWORD clst /* Directory table to clear */ ) { DWORD sect; UINT n, szb; BYTE *ibuf; if (sync_window(fs) != FR_OK) return FR_DISK_ERR; /* Flush disk access window */ sect = clst2sect(fs, clst); /* Top of the cluster */ fs->winsect = sect; /* Set window to top of the cluster */ mem_set(fs->win, 0, SS(fs)); /* Clear window buffer */ #if FF_USE_LFN == 3 /* Quick table clear by using multi-secter write */ /* Allocate a temporary buffer */ for (szb = ((DWORD)fs->csize * SS(fs) >= MAX_MALLOC) ? MAX_MALLOC : fs->csize * SS(fs), ibuf = 0; szb > SS(fs) && (ibuf = ff_memalloc(szb)) == 0; szb /= 2) ; if (szb > SS(fs)) { /* Buffer allocated? */ mem_set(ibuf, 0, szb); szb /= SS(fs); /* Bytes -> Sectors */ for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */ ff_memfree(ibuf); } else #endif { ibuf = fs->win; szb = 1; /* Use window buffer (many single-sector writes may take a time) */ for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */ } return (n == fs->csize) ? FR_OK : FR_DISK_ERR; } #endif /* !FF_FS_READONLY */ /*-----------------------------------------------------------------------*/ /* Directory handling - Set directory index */ /*-----------------------------------------------------------------------*/ static FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */ DIR* dp, /* Pointer to directory object */ DWORD ofs /* Offset of directory table */ ) { DWORD csz, clst; FATFS *fs = dp->obj.fs; if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) { /* Check range of offset and alignment */ return FR_INT_ERR; } dp->dptr = ofs; /* Set current offset */ clst = dp->obj.sclust; /* Table start cluster (0:root) */ if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */ clst = fs->dirbase; if (FF_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */ } if (clst == 0) { /* Static table (root-directory on the FAT volume) */ if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */ dp->sect = fs->dirbase; } else { /* Dynamic table (sub-directory or root-directory on the FAT32/exFAT volume) */ csz = (DWORD)fs->csize * SS(fs); /* Bytes per cluster */ while (ofs >= csz) { /* Follow cluster chain */ clst = get_fat(&dp->obj, clst); /* Get next cluster */ if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal error */ ofs -= csz; } dp->sect = clst2sect(fs, clst); } dp->clust = clst; /* Current cluster# */ if (dp->sect == 0) return FR_INT_ERR; dp->sect += ofs / SS(fs); /* Sector# of the directory entry */ dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */ return FR_OK; } /*-----------------------------------------------------------------------*/ /* Directory handling - Move directory table index next */ /*-----------------------------------------------------------------------*/ static FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ DIR* dp, /* Pointer to the directory object */ int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ ) { DWORD ofs, clst; FATFS *fs = dp->obj.fs; ofs = dp->dptr + SZDIRE; /* Next entry */ if (dp->sect == 0 || ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) return FR_NO_FILE; /* Report EOT when offset has reached max value */ if (ofs % SS(fs) == 0) { /* Sector changed? */ dp->sect++; /* Next sector */ if (dp->clust == 0) { /* Static table */ if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */ dp->sect = 0; return FR_NO_FILE; } } else { /* Dynamic table */ if ((ofs / SS(fs) & (fs->csize - 1)) == 0) { /* Cluster changed? */ clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ if (clst <= 1) return FR_INT_ERR; /* Internal error */ if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ if (clst >= fs->n_fatent) { /* It reached end of dynamic table */ #if !FF_FS_READONLY if (!stretch) { /* If no stretch, report EOT */ dp->sect = 0; return FR_NO_FILE; } clst = create_chain(&dp->obj, dp->clust); /* Allocate a cluster */ if (clst == 0) return FR_DENIED; /* No free cluster */ if (clst == 1) return FR_INT_ERR; /* Internal error */ if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ if (dir_clear(fs, clst) != FR_OK) return FR_DISK_ERR; /* Clean up the stretched table */ if (FF_FS_EXFAT) dp->obj.stat |= 4; /* exFAT: The directory has been stretched */ #else if (!stretch) dp->sect = 0; /* (this line is to suppress compiler warning) */ dp->sect = 0; return FR_NO_FILE; /* Report EOT */ #endif } dp->clust = clst; /* Initialize data for new cluster */ dp->sect = clst2sect(fs, clst); } } } dp->dptr = ofs; /* Current entry */ dp->dir = fs->win + ofs % SS(fs); /* Pointer to the entry in the win[] */ return FR_OK; } #if !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* Directory handling - Reserve a block of directory entries */ /*-----------------------------------------------------------------------*/ static FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */ DIR* dp, /* Pointer to the directory object */ UINT nent /* Number of contiguous entries to allocate */ ) { FRESULT res; UINT n; FATFS *fs = dp->obj.fs; res = dir_sdi(dp, 0); if (res == FR_OK) { n = 0; do { res = move_window(fs, dp->sect); if (res != FR_OK) break; #if FF_FS_EXFAT if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) { #else if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) { #endif if (++n == nent) break; /* A block of contiguous free entries is found */ } else { n = 0; /* Not a blank entry. Restart to search */ } res = dir_next(dp, 1); } while (res == FR_OK); /* Next entry with table stretch enabled */ } if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */ return res; } #endif /* !FF_FS_READONLY */ /*-----------------------------------------------------------------------*/ /* FAT: Directory handling - Load/Store start cluster number */ /*-----------------------------------------------------------------------*/ static DWORD ld_clust ( /* Returns the top cluster value of the SFN entry */ FATFS* fs, /* Pointer to the fs object */ const BYTE* dir /* Pointer to the key entry */ ) { DWORD cl; cl = ld_word(dir + DIR_FstClusLO); if (fs->fs_type == FS_FAT32) { cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16; } return cl; } #if !FF_FS_READONLY static void st_clust ( FATFS* fs, /* Pointer to the fs object */ BYTE* dir, /* Pointer to the key entry */ DWORD cl /* Value to be set */ ) { st_word(dir + DIR_FstClusLO, (WORD)cl); if (fs->fs_type == FS_FAT32) { st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16)); } } #endif #if FF_USE_LFN /*--------------------------------------------------------*/ /* FAT-LFN: Compare a part of file name with an LFN entry */ /*--------------------------------------------------------*/ static int cmp_lfn ( /* 1:matched, 0:not matched */ const WCHAR* lfnbuf, /* Pointer to the LFN working buffer to be compared */ BYTE* dir /* Pointer to the directory entry containing the part of LFN */ ) { UINT i, s; WCHAR wc, uc; if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */ i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ if (wc != 0) { if (i >= FF_MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) { /* Compare it */ return 0; /* Not matched */ } wc = uc; } else { if (uc != 0xFFFF) return 0; /* Check filler */ } } if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0; /* Last segment matched but different length */ return 1; /* The part of LFN matched */ } #if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT /*-----------------------------------------------------*/ /* FAT-LFN: Pick a part of file name from an LFN entry */ /*-----------------------------------------------------*/ static int pick_lfn ( /* 1:succeeded, 0:buffer overflow or invalid LFN entry */ WCHAR* lfnbuf, /* Pointer to the LFN working buffer */ BYTE* dir /* Pointer to the LFN entry */ ) { UINT i, s; WCHAR wc, uc; if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO is 0 */ i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13; /* Offset in the LFN buffer */ for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ if (wc != 0) { if (i >= FF_MAX_LFN) return 0; /* Buffer overflow? */ lfnbuf[i++] = wc = uc; /* Store it */ } else { if (uc != 0xFFFF) return 0; /* Check filler */ } } if (dir[LDIR_Ord] & LLEF) { /* Put terminator if it is the last LFN part */ if (i >= FF_MAX_LFN) return 0; /* Buffer overflow? */ lfnbuf[i] = 0; } return 1; /* The part of LFN is valid */ } #endif #if !FF_FS_READONLY /*-----------------------------------------*/ /* FAT-LFN: Create an entry of LFN entries */ /*-----------------------------------------*/ static void put_lfn ( const WCHAR* lfn, /* Pointer to the LFN */ BYTE* dir, /* Pointer to the LFN entry to be created */ BYTE ord, /* LFN order (1-20) */ BYTE sum /* Checksum of the corresponding SFN */ ) { UINT i, s; WCHAR wc; dir[LDIR_Chksum] = sum; /* Set checksum */ dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ dir[LDIR_Type] = 0; st_word(dir + LDIR_FstClusLO, 0); i = (ord - 1) * 13; /* Get offset in the LFN working buffer */ s = wc = 0; do { if (wc != 0xFFFF) wc = lfn[i++]; /* Get an effective character */ st_word(dir + LfnOfs[s], wc); /* Put it */ if (wc == 0) wc = 0xFFFF; /* Padding characters for left locations */ } while (++s < 13); if (wc == 0xFFFF || !lfn[i]) ord |= LLEF; /* Last LFN part is the start of LFN sequence */ dir[LDIR_Ord] = ord; /* Set the LFN order */ } #endif /* !FF_FS_READONLY */ #endif /* FF_USE_LFN */ #if FF_USE_LFN && !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* FAT-LFN: Create a Numbered SFN */ /*-----------------------------------------------------------------------*/ static void gen_numname ( BYTE* dst, /* Pointer to the buffer to store numbered SFN */ const BYTE* src, /* Pointer to SFN */ const WCHAR* lfn, /* Pointer to LFN */ UINT seq /* Sequence number */ ) { BYTE ns[8], c; UINT i, j; WCHAR wc; DWORD sr; mem_cpy(dst, src, 11); if (seq > 5) { /* In case of many collisions, generate a hash number instead of sequential number */ sr = seq; while (*lfn) { /* Create a CRC as hash value */ wc = *lfn++; for (i = 0; i < 16; i++) { sr = (sr << 1) + (wc & 1); wc >>= 1; if (sr & 0x10000) sr ^= 0x11021; } } seq = (UINT)sr; } /* itoa (hexdecimal) */ i = 7; do { c = (BYTE)((seq % 16) + '0'); if (c > '9') c += 7; ns[i--] = c; seq /= 16; } while (seq); ns[i] = '~'; /* Append the number to the SFN body */ for (j = 0; j < i && dst[j] != ' '; j++) { if (dbc_1st(dst[j])) { if (j == i - 1) break; j++; } } do { dst[j++] = (i < 8) ? ns[i++] : ' '; } while (j < 8); } #endif /* FF_USE_LFN && !FF_FS_READONLY */ #if FF_USE_LFN /*-----------------------------------------------------------------------*/ /* FAT-LFN: Calculate checksum of an SFN entry */ /*-----------------------------------------------------------------------*/ static BYTE sum_sfn ( const BYTE* dir /* Pointer to the SFN entry */ ) { BYTE sum = 0; UINT n = 11; do { sum = (sum >> 1) + (sum << 7) + *dir++; } while (--n); return sum; } #endif /* FF_USE_LFN */ #if FF_FS_EXFAT /*-----------------------------------------------------------------------*/ /* exFAT: Checksum */ /*-----------------------------------------------------------------------*/ static WORD xdir_sum ( /* Get checksum of the directoly entry block */ const BYTE* dir /* Directory entry block to be calculated */ ) { UINT i, szblk; WORD sum; szblk = (dir[XDIR_NumSec] + 1) * SZDIRE; /* Number of bytes of the entry block */ for (i = sum = 0; i < szblk; i++) { if (i == XDIR_SetSum) { /* Skip 2-byte sum field */ i++; } else { sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i]; } } return sum; } static WORD xname_sum ( /* Get check sum (to be used as hash) of the file name */ const WCHAR* name /* File name to be calculated */ ) { WCHAR chr; WORD sum = 0; while ((chr = *name++) != 0) { chr = (WCHAR)ff_wtoupper(chr); /* File name needs to be up-case converted */ sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF); sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8); } return sum; } #if !FF_FS_READONLY && FF_USE_MKFS static DWORD xsum32 ( /* Returns 32-bit checksum */ BYTE dat, /* Byte to be calculated (byte-by-byte processing) */ DWORD sum /* Previous sum value */ ) { sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat; return sum; } #endif #if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 /*------------------------------------------------------*/ /* exFAT: Get object information from a directory block */ /*------------------------------------------------------*/ static void get_xfileinfo ( BYTE* dirb, /* Pointer to the direcotry entry block 85+C0+C1s */ FILINFO* fno /* Buffer to store the extracted file information */ ) { WCHAR wc, hs; UINT di, si, nc; /* Get file name from the entry block */ si = SZDIRE * 2; /* 1st C1 entry */ nc = 0; hs = 0; di = 0; while (nc < dirb[XDIR_NumName]) { if (si >= MAXDIRB(FF_MAX_LFN)) { di = 0; break; } /* Truncated directory block? */ if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */ wc = ld_word(dirb + si); si += 2; nc++; /* Get a character */ if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */ hs = wc; continue; /* Get low surrogate */ } wc = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in API encoding */ if (wc == 0) { di = 0; break; } /* Buffer overflow or wrong encoding? */ di += wc; hs = 0; } if (hs != 0) di = 0; /* Broken surrogate pair? */ if (di == 0) fno->fname[di++] = '?'; /* Inaccessible object name? */ fno->fname[di] = 0; /* Terminate the name */ fno->altname[0] = 0; /* exFAT does not support SFN */ fno->fattrib = dirb[XDIR_Attr]; /* Attribute */ fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(dirb + XDIR_FileSize); /* Size */ fno->ftime = ld_word(dirb + XDIR_ModTime + 0); /* Time */ fno->fdate = ld_word(dirb + XDIR_ModTime + 2); /* Date */ } #endif /* FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 */ /*-----------------------------------*/ /* exFAT: Get a directry entry block */ /*-----------------------------------*/ static FRESULT load_xdir ( /* FR_INT_ERR: invalid entry block */ DIR* dp /* Reading direcotry object pointing top of the entry block to load */ ) { FRESULT res; UINT i, sz_ent; BYTE* dirb = dp->obj.fs->dirbuf; /* Pointer to the on-memory direcotry entry block 85+C0+C1s */ /* Load 85 entry */ res = move_window(dp->obj.fs, dp->sect); if (res != FR_OK) return res; if (dp->dir[XDIR_Type] != 0x85) return FR_INT_ERR; /* Invalid order */ mem_cpy(dirb + 0 * SZDIRE, dp->dir, SZDIRE); sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE; if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR; /* Load C0 entry */ res = dir_next(dp, 0); if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */ if (res != FR_OK) return res; res = move_window(dp->obj.fs, dp->sect); if (res != FR_OK) return res; if (dp->dir[XDIR_Type] != 0xC0) return FR_INT_ERR; /* Invalid order */ mem_cpy(dirb + 1 * SZDIRE, dp->dir, SZDIRE); if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR; /* Load C1 entries */ i = 2 * SZDIRE; /* C1 offset to load */ do { res = dir_next(dp, 0); if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */ if (res != FR_OK) return res; res = move_window(dp->obj.fs, dp->sect); if (res != FR_OK) return res; if (dp->dir[XDIR_Type] != 0xC1) return FR_INT_ERR; /* Invalid order */ if (i < MAXDIRB(FF_MAX_LFN)) mem_cpy(dirb + i, dp->dir, SZDIRE); } while ((i += SZDIRE) < sz_ent); /* Sanity check (do it for only accessible object) */ if (i <= MAXDIRB(FF_MAX_LFN)) { if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR; } return FR_OK; } /*------------------------------------------------------------------*/ /* exFAT: Initialize object allocation info with loaded entry block */ /*------------------------------------------------------------------*/ static void init_alloc_info ( FATFS* fs, /* Filesystem object */ FFOBJID* obj /* Object allocation information to be initialized */ ) { obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Start cluster */ obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize); /* Size */ obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; /* Allocation status */ obj->n_frag = 0; /* No last fragment info */ } #if !FF_FS_READONLY || FF_FS_RPATH != 0 /*------------------------------------------------*/ /* exFAT: Load the object's directory entry block */ /*------------------------------------------------*/ static FRESULT load_obj_xdir ( DIR* dp, /* Blank directory object to be used to access containing direcotry */ const FFOBJID* obj /* Object with its containing directory information */ ) { FRESULT res; /* Open object containing directory */ dp->obj.fs = obj->fs; dp->obj.sclust = obj->c_scl; dp->obj.stat = (BYTE)obj->c_size; dp->obj.objsize = obj->c_size & 0xFFFFFF00; dp->obj.n_frag = 0; dp->blk_ofs = obj->c_ofs; res = dir_sdi(dp, dp->blk_ofs); /* Goto object's entry block */ if (res == FR_OK) { res = load_xdir(dp); /* Load the object's entry block */ } return res; } #endif #if !FF_FS_READONLY /*----------------------------------------*/ /* exFAT: Store the directory entry block */ /*----------------------------------------*/ static FRESULT store_xdir ( DIR* dp /* Pointer to the direcotry object */ ) { FRESULT res; UINT nent; BYTE* dirb = dp->obj.fs->dirbuf; /* Pointer to the direcotry entry block 85+C0+C1s */ /* Create set sum */ st_word(dirb + XDIR_SetSum, xdir_sum(dirb)); nent = dirb[XDIR_NumSec] + 1; /* Store the direcotry entry block to the directory */ res = dir_sdi(dp, dp->blk_ofs); while (res == FR_OK) { res = move_window(dp->obj.fs, dp->sect); if (res != FR_OK) break; mem_cpy(dp->dir, dirb, SZDIRE); dp->obj.fs->wflag = 1; if (--nent == 0) break; dirb += SZDIRE; res = dir_next(dp, 0); } return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR; } /*-------------------------------------------*/ /* exFAT: Create a new directory enrty block */ /*-------------------------------------------*/ static void create_xdir ( BYTE* dirb, /* Pointer to the direcotry entry block buffer */ const WCHAR* lfn /* Pointer to the object name */ ) { UINT i; BYTE nc1, nlen; WCHAR wc; /* Create 85,C0 entry */ mem_set(dirb, 0, 2 * SZDIRE); dirb[0 * SZDIRE + XDIR_Type] = 0x85; /* 85 entry */ dirb[1 * SZDIRE + XDIR_Type] = 0xC0; /* C0 entry */ /* Create C1 entries */ i = SZDIRE * 2; /* Top of C1 entries */ nlen = nc1 = 0; wc = 1; do { dirb[i++] = 0xC1; dirb[i++] = 0; /* Entry type C1 */ do { /* Fill name field */ if (wc != 0 && (wc = lfn[nlen]) != 0) nlen++; /* Get a character if exist */ st_word(dirb + i, wc); /* Store it */ i += 2; } while (i % SZDIRE != 0); nc1++; } while (lfn[nlen]); /* Fill next entry if any char follows */ dirb[XDIR_NumName] = nlen; /* Set name length */ dirb[XDIR_NumSec] = 1 + nc1; /* Set secondary count (C0 + C1s) */ st_word(dirb + XDIR_NameHash, xname_sum(lfn)); /* Set name hash */ } #endif /* !FF_FS_READONLY */ #endif /* FF_FS_EXFAT */ #if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT /*-----------------------------------------------------------------------*/ /* Read an object from the directory */ /*-----------------------------------------------------------------------*/ #define dir_read_file(dp) dir_read(dp, 0) #define dir_read_label(dp) dir_read(dp, 1) static FRESULT dir_read ( DIR* dp, /* Pointer to the directory object */ int vol /* Filtered by 0:file/directory or 1:volume label */ ) { FRESULT res = FR_NO_FILE; FATFS *fs = dp->obj.fs; BYTE a, c; #if FF_USE_LFN BYTE ord = 0xFF, sum = 0xFF; #endif while (dp->sect) { res = move_window(fs, dp->sect); if (res != FR_OK) break; c = dp->dir[DIR_Name]; /* Test for the entry type */ if (c == 0) { res = FR_NO_FILE; break; /* Reached to end of the directory */ } #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ if (FF_USE_LABEL && vol) { if (c == 0x83) break; /* Volume label entry? */ } else { if (c == 0x85) { /* Start of the file entry block? */ dp->blk_ofs = dp->dptr; /* Get location of the block */ res = load_xdir(dp); /* Load the entry block */ if (res == FR_OK) { dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK; /* Get attribute */ } break; } } } else #endif { /* On the FAT/FAT32 volume */ dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; /* Get attribute */ #if FF_USE_LFN /* LFN configuration */ if (c == DDEM || c == '.' || (int)((a & ~AM_ARC) == AM_VOL) != vol) { /* An entry without valid data */ ord = 0xFF; } else { if (a == AM_LFN) { /* An LFN entry is found */ if (c & LLEF) { /* Is it start of an LFN sequence? */ sum = dp->dir[LDIR_Chksum]; c &= (BYTE)~LLEF; ord = c; dp->blk_ofs = dp->dptr; } /* Check LFN validity and capture it */ ord = (c == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; } else { /* An SFN entry is found */ if (ord != 0 || sum != sum_sfn(dp->dir)) { /* Is there a valid LFN? */ dp->blk_ofs = 0xFFFFFFFF; /* It has no LFN. */ } break; } } #else /* Non LFN configuration */ if (c != DDEM && c != '.' && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol) { /* Is it a valid entry? */ break; } #endif } res = dir_next(dp, 0); /* Next entry */ if (res != FR_OK) break; } if (res != FR_OK) dp->sect = 0; /* Terminate the read operation on error or EOT */ return res; } #endif /* FF_FS_MINIMIZE <= 1 || FF_USE_LABEL || FF_FS_RPATH >= 2 */ /*-----------------------------------------------------------------------*/ /* Directory handling - Find an object in the directory */ /*-----------------------------------------------------------------------*/ static FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */ DIR* dp /* Pointer to the directory object with the file name */ ) { FRESULT res; FATFS *fs = dp->obj.fs; BYTE c; #if FF_USE_LFN BYTE a, ord, sum; #endif res = dir_sdi(dp, 0); /* Rewind directory object */ if (res != FR_OK) return res; #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ BYTE nc; UINT di, ni; WORD hash = xname_sum(fs->lfnbuf); /* Hash value of the name to find */ while ((res = dir_read_file(dp)) == FR_OK) { /* Read an item */ #if FF_MAX_LFN < 255 if (fs->dirbuf[XDIR_NumName] > FF_MAX_LFN) continue; /* Skip comparison if inaccessible object name */ #endif if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue; /* Skip comparison if hash mismatched */ for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) { /* Compare the name */ if ((di % SZDIRE) == 0) di += 2; if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break; } if (nc == 0 && !fs->lfnbuf[ni]) break; /* Name matched? */ } return res; } #endif /* On the FAT/FAT32 volume */ #if FF_USE_LFN ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ #endif do { res = move_window(fs, dp->sect); if (res != FR_OK) break; c = dp->dir[DIR_Name]; if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ #if FF_USE_LFN /* LFN configuration */ dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ } else { if (a == AM_LFN) { /* An LFN entry is found */ if (!(dp->fn[NSFLAG] & NS_NOLFN)) { if (c & LLEF) { /* Is it start of LFN sequence? */ sum = dp->dir[LDIR_Chksum]; c &= (BYTE)~LLEF; ord = c; /* LFN start order */ dp->blk_ofs = dp->dptr; /* Start offset of LFN */ } /* Check validity of the LFN entry and compare it with given name */ ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; } } else { /* An SFN entry is found */ if (ord == 0 && sum == sum_sfn(dp->dir)) break; /* LFN matched? */ if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* SFN matched? */ ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ } } #else /* Non LFN configuration */ dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK; if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry? */ #endif res = dir_next(dp, 0); /* Next entry */ } while (res == FR_OK); return res; } #if !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* Register an object to the directory */ /*-----------------------------------------------------------------------*/ static FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */ DIR* dp /* Target directory with object name to be created */ ) { FRESULT res; FATFS *fs = dp->obj.fs; #if FF_USE_LFN /* LFN configuration */ UINT n, nlen, nent; BYTE sn[12], sum; if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME; /* Check name validity */ for (nlen = 0; fs->lfnbuf[nlen]; nlen++) ; /* Get lfn length */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ nent = (nlen + 14) / 15 + 2; /* Number of entries to allocate (85+C0+C1s) */ res = dir_alloc(dp, nent); /* Allocate entries */ if (res != FR_OK) return res; dp->blk_ofs = dp->dptr - SZDIRE * (nent - 1); /* Set the allocated entry block offset */ if (dp->obj.stat & 4) { /* Has the directory been stretched? */ dp->obj.stat &= ~4; res = fill_first_frag(&dp->obj); /* Fill the first fragment on the FAT if needed */ if (res != FR_OK) return res; res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF); /* Fill the last fragment on the FAT if needed */ if (res != FR_OK) return res; if (dp->obj.sclust != 0) { /* Is it a sub directory? */ DIR dj; res = load_obj_xdir(&dj, &dp->obj); /* Load the object status */ if (res != FR_OK) return res; dp->obj.objsize += (DWORD)fs->csize * SS(fs); /* Increase the directory size by cluster size */ st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize); /* Update the allocation status */ st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize); fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1; res = store_xdir(&dj); /* Store the object status */ if (res != FR_OK) return res; } } create_xdir(fs->dirbuf, fs->lfnbuf); /* Create on-memory directory block to be written later */ return FR_OK; } #endif /* On the FAT/FAT32 volume */ mem_cpy(sn, dp->fn, 12); if (sn[NSFLAG] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ dp->fn[NSFLAG] = NS_NOLFN; /* Find only SFN */ for (n = 1; n < 100; n++) { gen_numname(dp->fn, sn, fs->lfnbuf, n); /* Generate a numbered name */ res = dir_find(dp); /* Check if the name collides with existing SFN */ if (res != FR_OK) break; } if (n == 100) return FR_DENIED; /* Abort if too many collisions */ if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ dp->fn[NSFLAG] = sn[NSFLAG]; } /* Create an SFN with/without LFNs. */ nent = (sn[NSFLAG] & NS_LFN) ? (nlen + 12) / 13 + 1 : 1; /* Number of entries to allocate */ res = dir_alloc(dp, nent); /* Allocate entries */ if (res == FR_OK && --nent) { /* Set LFN entry if needed */ res = dir_sdi(dp, dp->dptr - nent * SZDIRE); if (res == FR_OK) { sum = sum_sfn(dp->fn); /* Checksum value of the SFN tied to the LFN */ do { /* Store LFN entries in bottom first */ res = move_window(fs, dp->sect); if (res != FR_OK) break; put_lfn(fs->lfnbuf, dp->dir, (BYTE)nent, sum); fs->wflag = 1; res = dir_next(dp, 0); /* Next entry */ } while (res == FR_OK && --nent); } } #else /* Non LFN configuration */ res = dir_alloc(dp, 1); /* Allocate an entry for SFN */ #endif /* Set SFN entry */ if (res == FR_OK) { res = move_window(fs, dp->sect); if (res == FR_OK) { mem_set(dp->dir, 0, SZDIRE); /* Clean the entry */ mem_cpy(dp->dir + DIR_Name, dp->fn, 11); /* Put SFN */ #if FF_USE_LFN dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT); /* Put NT flag */ #endif fs->wflag = 1; } } return res; } #endif /* !FF_FS_READONLY */ #if !FF_FS_READONLY && FF_FS_MINIMIZE == 0 /*-----------------------------------------------------------------------*/ /* Remove an object from the directory */ /*-----------------------------------------------------------------------*/ static FRESULT dir_remove ( /* FR_OK:Succeeded, FR_DISK_ERR:A disk error */ DIR* dp /* Directory object pointing the entry to be removed */ ) { FRESULT res; FATFS *fs = dp->obj.fs; #if FF_USE_LFN /* LFN configuration */ DWORD last = dp->dptr; res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs); /* Goto top of the entry block if LFN is exist */ if (res == FR_OK) { do { res = move_window(fs, dp->sect); if (res != FR_OK) break; if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ dp->dir[XDIR_Type] &= 0x7F; /* Clear the entry InUse flag. */ } else { /* On the FAT/FAT32 volume */ dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'. */ } fs->wflag = 1; if (dp->dptr >= last) break; /* If reached last entry then all entries of the object has been deleted. */ res = dir_next(dp, 0); /* Next entry */ } while (res == FR_OK); if (res == FR_NO_FILE) res = FR_INT_ERR; } #else /* Non LFN configuration */ res = move_window(fs, dp->sect); if (res == FR_OK) { dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'.*/ fs->wflag = 1; } #endif return res; } #endif /* !FF_FS_READONLY && FF_FS_MINIMIZE == 0 */ #if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 /*-----------------------------------------------------------------------*/ /* Get file information from directory entry */ /*-----------------------------------------------------------------------*/ static void get_fileinfo ( DIR* dp, /* Pointer to the directory object */ FILINFO* fno /* Pointer to the file information to be filled */ ) { UINT si, di; #if FF_USE_LFN WCHAR wc, hs; FATFS *fs = dp->obj.fs; #else TCHAR c; #endif fno->fname[0] = 0; /* Invaidate file info */ if (dp->sect == 0) return; /* Exit if read pointer has reached end of directory */ #if FF_USE_LFN /* LFN configuration */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ get_xfileinfo(fs->dirbuf, fno); return; } else #endif { /* On the FAT/FAT32 volume */ if (dp->blk_ofs != 0xFFFFFFFF) { /* Get LFN if available */ si = di = hs = 0; while (fs->lfnbuf[si] != 0) { wc = fs->lfnbuf[si++]; /* Get an LFN character (UTF-16) */ if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */ hs = wc; continue; /* Get low surrogate */ } wc = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in UTF-16 or UTF-8 encoding */ if (wc == 0) { di = 0; break; } /* Invalid char or buffer overflow? */ di += wc; hs = 0; } if (hs != 0) di = 0; /* Broken surrogate pair? */ fno->fname[di] = 0; /* Terminate the LFN (null string means LFN is invalid) */ } } si = di = 0; while (si < 11) { /* Get SFN from SFN entry */ wc = dp->dir[si++]; /* Get a char */ if (wc == ' ') continue; /* Skip padding spaces */ if (wc == RDDEM) wc = DDEM; /* Restore replaced DDEM character */ if (si == 9 && di < FF_SFN_BUF) fno->altname[di++] = '.'; /* Insert a . if extension is exist */ #if FF_LFN_UNICODE >= 1 /* Unicode output */ if (dbc_1st((BYTE)wc) && si != 8 && si != 11 && dbc_2nd(dp->dir[si])) { /* Make a DBC if needed */ wc = wc << 8 | dp->dir[si++]; } wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM -> Unicode */ if (wc == 0) { di = 0; break; } /* Wrong char in the current code page? */ wc = put_utf(wc, &fno->altname[di], FF_SFN_BUF - di); /* Store it in Unicode */ if (wc == 0) { di = 0; break; } /* Buffer overflow? */ di += wc; #else /* ANSI/OEM output */ fno->altname[di++] = (TCHAR)wc; /* Store it without any conversion */ #endif } fno->altname[di] = 0; /* Terminate the SFN (null string means SFN is invalid) */ if (fno->fname[0] == 0) { /* If LFN is invalid, altname[] needs to be copied to fname[] */ if (di == 0) { /* If LFN and SFN both are invalid, this object is inaccesible */ fno->fname[di++] = '?'; } else { for (si = di = 0; fno->altname[si]; si++, di++) { /* Copy altname[] to fname[] with case information */ wc = (WCHAR)fno->altname[si]; if (IsUpper(wc) && (dp->dir[DIR_NTres] & ((si >= 9) ? NS_EXT : NS_BODY))) wc += 0x20; fno->fname[di] = (TCHAR)wc; } } fno->fname[di] = 0; /* Terminate the LFN */ if (!dp->dir[DIR_NTres]) fno->altname[0] = 0; /* Altname is not needed if neither LFN nor case info is exist. */ } #else /* Non-LFN configuration */ si = di = 0; while (si < 11) { /* Copy name body and extension */ c = (TCHAR)dp->dir[si++]; if (c == ' ') continue; /* Skip padding spaces */ if (c == RDDEM) c = DDEM; /* Restore replaced DDEM character */ if (si == 9) fno->fname[di++] = '.';/* Insert a . if extension is exist */ fno->fname[di++] = c; } fno->fname[di] = 0; #endif fno->fattrib = dp->dir[DIR_Attr]; /* Attribute */ fno->fsize = ld_dword(dp->dir + DIR_FileSize); /* Size */ fno->ftime = ld_word(dp->dir + DIR_ModTime + 0); /* Time */ fno->fdate = ld_word(dp->dir + DIR_ModTime + 2); /* Date */ } #endif /* FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 */ #if FF_USE_FIND && FF_FS_MINIMIZE <= 1 /*-----------------------------------------------------------------------*/ /* Pattern matching */ /*-----------------------------------------------------------------------*/ static DWORD get_achar ( /* Get a character and advances ptr */ const TCHAR** ptr /* Pointer to pointer to the ANSI/OEM or Unicode string */ ) { DWORD chr; #if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode input */ chr = tchar2uni(ptr); if (chr == 0xFFFFFFFF) chr = 0; /* Wrong UTF encoding is recognized as end of the string */ chr = ff_wtoupper(chr); #else /* ANSI/OEM input */ chr = (BYTE)*(*ptr)++; /* Get a byte */ if (IsLower(chr)) chr -= 0x20; /* To upper ASCII char */ #if FF_CODE_PAGE == 0 if (ExCvt && chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ #elif FF_CODE_PAGE < 900 if (chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ #endif #if FF_CODE_PAGE == 0 || FF_CODE_PAGE >= 900 if (dbc_1st((BYTE)chr)) { /* Get DBC 2nd byte if needed */ chr = dbc_2nd((BYTE)**ptr) ? chr << 8 | (BYTE)*(*ptr)++ : 0; } #endif #endif return chr; } static int pattern_matching ( /* 0:not matched, 1:matched */ const TCHAR* pat, /* Matching pattern */ const TCHAR* nam, /* String to be tested */ int skip, /* Number of pre-skip chars (number of ?s) */ int inf /* Infinite search (* specified) */ ) { const TCHAR *pp, *np; DWORD pc, nc; int nm, nx; while (skip--) { /* Pre-skip name chars */ if (!get_achar(&nam)) return 0; /* Branch mismatched if less name chars */ } if (*pat == 0 && inf) return 1; /* (short circuit) */ do { pp = pat; np = nam; /* Top of pattern and name to match */ for (;;) { if (*pp == '?' || *pp == '*') { /* Wildcard? */ nm = nx = 0; do { /* Analyze the wildcard block */ if (*pp++ == '?') nm++; else nx = 1; } while (*pp == '?' || *pp == '*'); if (pattern_matching(pp, np, nm, nx)) return 1; /* Test new branch (recurs upto number of wildcard blocks in the pattern) */ nc = *np; break; /* Branch mismatched */ } pc = get_achar(&pp); /* Get a pattern char */ nc = get_achar(&np); /* Get a name char */ if (pc != nc) break; /* Branch mismatched? */ if (pc == 0) return 1; /* Branch matched? (matched at end of both strings) */ } get_achar(&nam); /* nam++ */ } while (inf && nc); /* Retry until end of name if infinite search is specified */ return 0; } #endif /* FF_USE_FIND && FF_FS_MINIMIZE <= 1 */ /*-----------------------------------------------------------------------*/ /* Pick a top segment and create the object name in directory form */ /*-----------------------------------------------------------------------*/ static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not create */ DIR* dp, /* Pointer to the directory object */ const TCHAR** path /* Pointer to pointer to the segment in the path string */ ) { #if FF_USE_LFN /* LFN configuration */ BYTE b, cf; WCHAR wc, *lfn; DWORD uc; UINT i, ni, si, di; const TCHAR *p; /* Create LFN into LFN working buffer */ p = *path; lfn = dp->obj.fs->lfnbuf; di = 0; for (;;) { uc = tchar2uni(&p); /* Get a character */ if (uc == 0xFFFFFFFF) return FR_INVALID_NAME; /* Invalid code or UTF decode error */ if (uc >= 0x10000) lfn[di++] = (WCHAR)(uc >> 16); /* Store high surrogate if needed */ wc = (WCHAR)uc; if (wc < ' ' || wc == '/' || wc == '\\') break; /* Break if end of the path or a separator is found */ if (wc < 0x80 && chk_chr("\"*:<>\?|\x7F", wc)) return FR_INVALID_NAME; /* Reject illegal characters for LFN */ if (di >= FF_MAX_LFN) return FR_INVALID_NAME; /* Reject too long name */ lfn[di++] = wc; /* Store the Unicode character */ } while (*p == '/' || *p == '\\') p++; /* Skip duplicated separators if exist */ *path = p; /* Return pointer to the next segment */ cf = (wc < ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ #if FF_FS_RPATH != 0 if ((di == 1 && lfn[di - 1] == '.') || (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { /* Is this segment a dot name? */ lfn[di] = 0; for (i = 0; i < 11; i++) { /* Create dot name for SFN entry */ dp->fn[i] = (i < di) ? '.' : ' '; } dp->fn[i] = cf | NS_DOT; /* This is a dot entry */ return FR_OK; } #endif while (di) { /* Snip off trailing spaces and dots if exist */ wc = lfn[di - 1]; if (wc != ' ' && wc != '.') break; di--; } lfn[di] = 0; /* LFN is created into the working buffer */ if (di == 0) return FR_INVALID_NAME; /* Reject null name */ /* Create SFN in directory form */ for (si = 0; lfn[si] == ' '; si++) ; /* Remove leading spaces */ if (si > 0 || lfn[si] == '.') cf |= NS_LOSS | NS_LFN; /* Is there any leading space or dot? */ while (di > 0 && lfn[di - 1] != '.') di--; /* Find last dot (di<=si: no extension) */ mem_set(dp->fn, ' ', 11); i = b = 0; ni = 8; for (;;) { wc = lfn[si++]; /* Get an LFN character */ if (wc == 0) break; /* Break on end of the LFN */ if (wc == ' ' || (wc == '.' && si != di)) { /* Remove embedded spaces and dots */ cf |= NS_LOSS | NS_LFN; continue; } if (i >= ni || si == di) { /* End of field? */ if (ni == 11) { /* Name extension overflow? */ cf |= NS_LOSS | NS_LFN; break; } if (si != di) cf |= NS_LOSS | NS_LFN; /* Name body overflow? */ if (si > di) break; /* No name extension? */ si = di; i = 8; ni = 11; b <<= 2; /* Enter name extension */ continue; } if (wc >= 0x80) { /* Is this a non-ASCII character? */ cf |= NS_LFN; /* LFN entry needs to be created */ #if FF_CODE_PAGE == 0 if (ExCvt) { /* At SBCS */ wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */ if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */ } else { /* At DBCS */ wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Upper convert ==> ANSI/OEM code */ } #elif FF_CODE_PAGE < 900 /* SBCS cfg */ wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */ if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */ #else /* DBCS cfg */ wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Upper convert ==> ANSI/OEM code */ #endif } if (wc >= 0x100) { /* Is this a DBC? */ if (i >= ni - 1) { /* Field overflow? */ cf |= NS_LOSS | NS_LFN; i = ni; continue; /* Next field */ } dp->fn[i++] = (BYTE)(wc >> 8); /* Put 1st byte */ } else { /* SBC */ if (wc == 0 || chk_chr("+,;=[]", wc)) { /* Replace illegal characters for SFN if needed */ wc = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ } else { if (IsUpper(wc)) { /* ASCII upper case? */ b |= 2; } if (IsLower(wc)) { /* ASCII lower case? */ b |= 1; wc -= 0x20; } } } dp->fn[i++] = (BYTE)wc; } if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ if (ni == 8) b <<= 2; /* Shift capital flags if no extension */ if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN; /* LFN entry needs to be created if composite capitals */ if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */ if (b & 0x01) cf |= NS_EXT; /* NT flag (Extension has small capital letters only) */ if (b & 0x04) cf |= NS_BODY; /* NT flag (Body has small capital letters only) */ } dp->fn[NSFLAG] = cf; /* SFN is created into dp->fn[] */ return FR_OK; #else /* FF_USE_LFN : Non-LFN configuration */ BYTE c, d, *sfn; UINT ni, si, i; const char *p; /* Create file name in directory form */ p = *path; sfn = dp->fn; mem_set(sfn, ' ', 11); si = i = 0; ni = 8; #if FF_FS_RPATH != 0 if (p[si] == '.') { /* Is this a dot entry? */ for (;;) { c = (BYTE)p[si++]; if (c != '.' || si >= 3) break; sfn[i++] = c; } if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; *path = p + si; /* Return pointer to the next segment */ sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of the path */ return FR_OK; } #endif for (;;) { c = (BYTE)p[si++]; /* Get a byte */ if (c <= ' ') break; /* Break if end of the path name */ if (c == '/' || c == '\\') { /* Break if a separator is found */ while (p[si] == '/' || p[si] == '\\') si++; /* Skip duplicated separator if exist */ break; } if (c == '.' || i >= ni) { /* End of body or field overflow? */ if (ni == 11 || c != '.') return FR_INVALID_NAME; /* Field overflow or invalid dot? */ i = 8; ni = 11; /* Enter file extension field */ continue; } #if FF_CODE_PAGE == 0 if (ExCvt && c >= 0x80) { /* Is SBC extended character? */ c = ExCvt[c & 0x7F]; /* To upper SBC extended character */ } #elif FF_CODE_PAGE < 900 if (c >= 0x80) { /* Is SBC extended character? */ c = ExCvt[c & 0x7F]; /* To upper SBC extended character */ } #endif if (dbc_1st(c)) { /* Check if it is a DBC 1st byte */ d = (BYTE)p[si++]; /* Get 2nd byte */ if (!dbc_2nd(d) || i >= ni - 1) return FR_INVALID_NAME; /* Reject invalid DBC */ sfn[i++] = c; sfn[i++] = d; } else { /* SBC */ if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) return FR_INVALID_NAME; /* Reject illegal chrs for SFN */ if (IsLower(c)) c -= 0x20; /* To upper */ sfn[i++] = c; } } *path = p + si; /* Return pointer to the next segment */ if (i == 0) return FR_INVALID_NAME; /* Reject nul string */ if (sfn[0] == DDEM) sfn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ return FR_OK; #endif /* FF_USE_LFN */ } /*-----------------------------------------------------------------------*/ /* Follow a file path */ /*-----------------------------------------------------------------------*/ static FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ DIR* dp, /* Directory object to return last directory and found object */ const TCHAR* path /* Full-path string to find a file or directory */ ) { FRESULT res; BYTE ns; FATFS *fs = dp->obj.fs; #if FF_FS_RPATH != 0 if (*path != '/' && *path != '\\') { /* Without heading separator */ dp->obj.sclust = fs->cdir; /* Start from current directory */ } else #endif { /* With heading separator */ while (*path == '/' || *path == '\\') path++; /* Strip heading separator */ dp->obj.sclust = 0; /* Start from root directory */ } #if FF_FS_EXFAT dp->obj.n_frag = 0; /* Invalidate last fragment counter of the object */ #if FF_FS_RPATH != 0 if (fs->fs_type == FS_EXFAT && dp->obj.sclust) { /* exFAT: Retrieve the sub-directory's status */ DIR dj; dp->obj.c_scl = fs->cdc_scl; dp->obj.c_size = fs->cdc_size; dp->obj.c_ofs = fs->cdc_ofs; res = load_obj_xdir(&dj, &dp->obj); if (res != FR_OK) return res; dp->obj.objsize = ld_dword(fs->dirbuf + XDIR_FileSize); dp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; } #endif #endif if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */ dp->fn[NSFLAG] = NS_NONAME; res = dir_sdi(dp, 0); } else { /* Follow path */ for (;;) { res = create_name(dp, &path); /* Get a segment name of the path */ if (res != FR_OK) break; res = dir_find(dp); /* Find an object with the segment name */ ns = dp->fn[NSFLAG]; if (res != FR_OK) { /* Failed to find the object */ if (res == FR_NO_FILE) { /* Object is not found */ if (FF_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */ if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ dp->fn[NSFLAG] = NS_NONAME; res = FR_OK; } else { /* Could not find the object */ if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */ } } break; } if (ns & NS_LAST) break; /* Last segment matched. Function completed. */ /* Get into the sub-directory */ if (!(dp->obj.attr & AM_DIR)) { /* It is not a sub-directory and cannot follow */ res = FR_NO_PATH; break; } #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* Save containing directory information for next dir */ dp->obj.c_scl = dp->obj.sclust; dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat; dp->obj.c_ofs = dp->blk_ofs; init_alloc_info(fs, &dp->obj); /* Open next directory */ } else #endif { dp->obj.sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs)); /* Open next directory */ } } } return res; } /*-----------------------------------------------------------------------*/ /* Get logical drive number from path name */ /*-----------------------------------------------------------------------*/ static int get_ldnumber ( /* Returns logical drive number (-1:invalid drive number or null pointer) */ const TCHAR** path /* Pointer to pointer to the path name */ ) { const TCHAR *tp, *tt; TCHAR tc; int i, vol = -1; #if FF_STR_VOLUME_ID /* Find string volume ID */ const char *sp; char c; #endif tt = tp = *path; if (!tp) return vol; /* Invalid path name? */ do tc = *tt++; while ((UINT)tc >= (FF_USE_LFN ? ' ' : '!') && tc != ':'); /* Find a colon in the path */ if (tc == ':') { /* DOS/Windows style volume ID? */ i = FF_VOLUMES; if (IsDigit(*tp) && tp + 2 == tt) { /* Is there a numeric volume ID + colon? */ i = (int)*tp - '0'; /* Get the LD number */ } #if FF_STR_VOLUME_ID == 1 /* Arbitrary string is enabled */ else { i = 0; do { sp = VolumeStr[i]; tp = *path; /* This string volume ID and path name */ do { /* Compare the volume ID with path name */ c = *sp++; tc = *tp++; if (IsLower(c)) c -= 0x20; if (IsLower(tc)) tc -= 0x20; } while (c && (TCHAR)c == tc); } while ((c || tp != tt) && ++i < FF_VOLUMES); /* Repeat for each id until pattern match */ } #endif if (i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */ vol = i; /* Drive number */ *path = tt; /* Snip the drive prefix off */ } return vol; } #if FF_STR_VOLUME_ID == 2 /* Unix style volume ID is enabled */ if (*tp == '/') { i = 0; do { sp = VolumeStr[i]; tp = *path; /* This string volume ID and path name */ do { /* Compare the volume ID with path name */ c = *sp++; tc = *(++tp); if (IsLower(c)) c -= 0x20; if (IsLower(tc)) tc -= 0x20; } while (c && (TCHAR)c == tc); } while ((c || (tc != '/' && (UINT)tc >= (FF_USE_LFN ? ' ' : '!'))) && ++i < FF_VOLUMES); /* Repeat for each ID until pattern match */ if (i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */ vol = i; /* Drive number */ *path = tp; /* Snip the drive prefix off */ return vol; } } #endif /* No drive prefix is found */ #if FF_FS_RPATH != 0 vol = CurrVol; /* Default drive is current drive */ #else vol = 0; /* Default drive is 0 */ #endif return vol; /* Return the default drive */ } /*-----------------------------------------------------------------------*/ /* Load a sector and check if it is an FAT VBR */ /*-----------------------------------------------------------------------*/ static BYTE check_fs ( /* 0:FAT, 1:exFAT, 2:Valid BS but not FAT, 3:Not a BS, 4:Disk error */ FATFS* fs, /* Filesystem object */ DWORD sect /* Sector# (lba) to load and check if it is an FAT-VBR or not */ ) { fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */ if (move_window(fs, sect) != FR_OK) return 4; /* Load boot record */ if (ld_word(fs->win + BS_55AA) != 0xAA55) return 3; /* Check boot record signature (always here regardless of the sector size) */ #if FF_FS_EXFAT if (!mem_cmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11)) return 1; /* Check if exFAT VBR */ #endif if (fs->win[BS_JmpBoot] == 0xE9 || fs->win[BS_JmpBoot] == 0xEB || fs->win[BS_JmpBoot] == 0xE8) { /* Valid JumpBoot code? */ if (!mem_cmp(fs->win + BS_FilSysType, "FAT", 3)) return 0; /* Is it an FAT VBR? */ if (!mem_cmp(fs->win + BS_FilSysType32, "FAT32", 5)) return 0; /* Is it an FAT32 VBR? */ } return 2; /* Valid BS but not FAT */ } /*-----------------------------------------------------------------------*/ /* Determine logical drive number and mount the volume if needed */ /*-----------------------------------------------------------------------*/ static FRESULT find_volume ( /* FR_OK(0): successful, !=0: an error occurred */ const TCHAR** path, /* Pointer to pointer to the path name (drive number) */ FATFS** rfs, /* Pointer to pointer to the found filesystem object */ BYTE mode /* !=0: Check write protection for write access */ ) { BYTE fmt, *pt; int vol; DSTATUS stat; DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4]; WORD nrsv; FATFS *fs; UINT i; /* Get logical drive number */ *rfs = 0; vol = get_ldnumber(path); if (vol < 0) return FR_INVALID_DRIVE; /* Check if the filesystem object is valid or not */ fs = FatFs[vol]; /* Get pointer to the filesystem object */ if (!fs) return FR_NOT_ENABLED; /* Is the filesystem object available? */ #if FF_FS_REENTRANT if (!lock_fs(fs)) return FR_TIMEOUT; /* Lock the volume */ #endif *rfs = fs; /* Return pointer to the filesystem object */ mode &= (BYTE)~FA_READ; /* Desired access mode, write access or not */ if (fs->fs_type != 0) { /* If the volume has been mounted */ stat = disk_status(fs->pdrv); if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */ return FR_WRITE_PROTECTED; } return FR_OK; /* The filesystem object is valid */ } } /* The filesystem object is not valid. */ /* Following code attempts to mount the volume. (analyze BPB and initialize the filesystem object) */ fs->fs_type = 0; /* Clear the filesystem object */ fs->pdrv = LD2PD(vol); /* Bind the logical drive and a physical drive */ stat = disk_initialize(fs->pdrv); /* Initialize the physical drive */ if (stat & STA_NOINIT) { /* Check if the initialization succeeded */ return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ } if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */ return FR_WRITE_PROTECTED; } #if FF_MAX_SS != FF_MIN_SS /* Get sector size (multiple sector size cfg only) */ if (disk_ioctl(fs->pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR; if (SS(fs) > FF_MAX_SS || SS(fs) < FF_MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; #endif /* Find an FAT partition on the drive. Supports only generic partitioning rules, FDISK and SFD. */ bsect = 0; fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT-VBR as SFD */ if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) { /* Not an FAT-VBR or forced partition number */ for (i = 0; i < 4; i++) { /* Get partition offset */ pt = fs->win + (MBR_Table + i * SZ_PTE); br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0; } i = LD2PT(vol); /* Partition number: 0:auto, 1-4:forced */ if (i != 0) i--; do { /* Find an FAT volume */ bsect = br[i]; fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */ } while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4); } if (fmt == 4) return FR_DISK_ERR; /* An error occured in the disk I/O layer */ if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ /* An FAT volume is found (bsect). Following code initializes the filesystem object */ #if FF_FS_EXFAT if (fmt == 1) { QWORD maxlba; for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ; /* Check zero filler */ if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM; if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM; /* Check exFAT version (must be version 1.0) */ if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) { /* (BPB_BytsPerSecEx must be equal to the physical sector size) */ return FR_NO_FILESYSTEM; } maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect; /* Last LBA + 1 of the volume */ if (maxlba >= 0x100000000) return FR_NO_FILESYSTEM; /* (It cannot be handled in 32-bit LBA) */ fs->fsize = ld_dword(fs->win + BPB_FatSzEx); /* Number of sectors per FAT */ fs->n_fats = fs->win[BPB_NumFATsEx]; /* Number of FATs */ if (fs->n_fats != 1) return FR_NO_FILESYSTEM; /* (Supports only 1 FAT) */ fs->csize = 1 << fs->win[BPB_SecPerClusEx]; /* Cluster size */ if (fs->csize == 0) return FR_NO_FILESYSTEM; /* (Must be 1..32768) */ nclst = ld_dword(fs->win + BPB_NumClusEx); /* Number of clusters */ if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM; /* (Too many clusters) */ fs->n_fatent = nclst + 2; /* Boundaries and Limits */ fs->volbase = bsect; fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx); fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx); if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM; /* (Volume size must not be smaller than the size requiered) */ fs->dirbase = ld_dword(fs->win + BPB_RootClusEx); /* Check if bitmap location is in assumption (at the first cluster) */ if (move_window(fs, clst2sect(fs, fs->dirbase)) != FR_OK) return FR_DISK_ERR; for (i = 0; i < SS(fs); i += SZDIRE) { if (fs->win[i] == 0x81 && ld_dword(fs->win + i + 20) == 2) break; /* 81 entry with cluster #2? */ } if (i == SS(fs)) return FR_NO_FILESYSTEM; #if !FF_FS_READONLY fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ #endif fmt = FS_EXFAT; /* FAT sub-type */ } else #endif /* FF_FS_EXFAT */ { if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_BytsPerSec must be equal to the physical sector size) */ fasize = ld_word(fs->win + BPB_FATSz16); /* Number of sectors per FAT */ if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32); fs->fsize = fasize; fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FATs */ if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ fasize *= fs->n_fats; /* Number of sectors for FAT area */ fs->csize = fs->win[BPB_SecPerClus]; /* Cluster size */ if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt); /* Number of root directory entries */ if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */ tsect = ld_word(fs->win + BPB_TotSec16); /* Number of sectors on the volume */ if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32); nrsv = ld_word(fs->win + BPB_RsvdSecCnt); /* Number of reserved sectors */ if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */ /* Determine the FAT sub type */ sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE); /* RSV + FAT + DIR */ if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ fmt = 0; if (nclst <= MAX_FAT32) fmt = FS_FAT32; if (nclst <= MAX_FAT16) fmt = FS_FAT16; if (nclst <= MAX_FAT12) fmt = FS_FAT12; if (fmt == 0) return FR_NO_FILESYSTEM; /* Boundaries and Limits */ fs->n_fatent = nclst + 2; /* Number of FAT entries */ fs->volbase = bsect; /* Volume start sector */ fs->fatbase = bsect + nrsv; /* FAT start sector */ fs->database = bsect + sysect; /* Data start sector */ if (fmt == FS_FAT32) { if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0) */ if (fs->n_rootdir != 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */ szbfat = fs->n_fatent * 4; /* (Needed FAT size) */ } else { if (fs->n_rootdir == 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */ fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); } if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_FATSz must not be less than the size needed) */ #if !FF_FS_READONLY /* Get FSInfo if available */ fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ fs->fsi_flag = 0x80; #if (FF_FS_NOFSINFO & 3) != 3 if (fmt == FS_FAT32 /* Allow to update FSInfo only if BPB_FSInfo32 == 1 */ && ld_word(fs->win + BPB_FSInfo32) == 1 && move_window(fs, bsect + 1) == FR_OK) { fs->fsi_flag = 0; if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSInfo data if available */ && ld_dword(fs->win + FSI_LeadSig) == 0x41615252 && ld_dword(fs->win + FSI_StrucSig) == 0x61417272) { #if (FF_FS_NOFSINFO & 1) == 0 fs->free_clst = ld_dword(fs->win + FSI_Free_Count); #endif #if (FF_FS_NOFSINFO & 2) == 0 fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free); #endif } } #endif /* (FF_FS_NOFSINFO & 3) != 3 */ #endif /* !FF_FS_READONLY */ } fs->fs_type = fmt; /* FAT sub-type */ fs->id = ++Fsid; /* Volume mount ID */ #if FF_USE_LFN == 1 fs->lfnbuf = LfnBuf; /* Static LFN working buffer */ #if FF_FS_EXFAT fs->dirbuf = DirBuf; /* Static directory block scratchpad buuffer */ #endif #endif #if FF_FS_RPATH != 0 fs->cdir = 0; /* Initialize current directory */ #endif #if FF_FS_LOCK != 0 /* Clear file lock semaphores */ clear_lock(fs); #endif return FR_OK; } /*-----------------------------------------------------------------------*/ /* Check if the file/directory object is valid or not */ /*-----------------------------------------------------------------------*/ static FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */ FFOBJID* obj, /* Pointer to the FFOBJID, the 1st member in the FIL/DIR object, to check validity */ FATFS** rfs /* Pointer to pointer to the owner filesystem object to return */ ) { FRESULT res = FR_INVALID_OBJECT; if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) { /* Test if the object is valid */ #if FF_FS_REENTRANT if (lock_fs(obj->fs)) { /* Obtain the filesystem object */ if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */ res = FR_OK; } else { unlock_fs(obj->fs, FR_OK); } } else { res = FR_TIMEOUT; } #else if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */ res = FR_OK; } #endif } *rfs = (res == FR_OK) ? obj->fs : 0; /* Corresponding filesystem object */ return res; } /*--------------------------------------------------------------------------- Public Functions (FatFs API) ----------------------------------------------------------------------------*/ /*-----------------------------------------------------------------------*/ /* Mount/Unmount a Logical Drive */ /*-----------------------------------------------------------------------*/ FRESULT f_mount ( FATFS* fs, /* Pointer to the filesystem object (NULL:unmount)*/ const TCHAR* path, /* Logical drive number to be mounted/unmounted */ BYTE opt /* Mode option 0:Do not mount (delayed mount), 1:Mount immediately */ ) { FATFS *cfs; int vol; FRESULT res; const TCHAR *rp = path; /* Get logical drive number */ vol = get_ldnumber(&rp); if (vol < 0) return FR_INVALID_DRIVE; cfs = FatFs[vol]; /* Pointer to fs object */ if (cfs) { #if FF_FS_LOCK != 0 clear_lock(cfs); #endif #if FF_FS_REENTRANT /* Discard sync object of the current volume */ if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR; #endif cfs->fs_type = 0; /* Clear old fs object */ } if (fs) { fs->fs_type = 0; /* Clear new fs object */ #if FF_FS_REENTRANT /* Create sync object for the new volume */ if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR; #endif } FatFs[vol] = fs; /* Register new fs object */ if (opt == 0) return FR_OK; /* Do not mount now, it will be mounted later */ res = find_volume(&path, &fs, 0); /* Force mounted the volume */ LEAVE_FF(fs, res); } /*-----------------------------------------------------------------------*/ /* Open or Create a File */ /*-----------------------------------------------------------------------*/ FRESULT f_open ( FIL* fp, /* Pointer to the blank file object */ const TCHAR* path, /* Pointer to the file name */ BYTE mode /* Access mode and file open mode flags */ ) { FRESULT res; DIR dj; FATFS *fs; #if !FF_FS_READONLY DWORD dw, cl, bcs, clst, sc; FSIZE_t ofs; #endif DEF_NAMBUF if (!fp) return FR_INVALID_OBJECT; /* Get logical drive number */ mode &= FF_FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND; res = find_volume(&path, &fs, mode); if (res == FR_OK) { dj.obj.fs = fs; INIT_NAMBUF(fs); res = follow_path(&dj, path); /* Follow the file path */ #if !FF_FS_READONLY /* Read/Write configuration */ if (res == FR_OK) { if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */ res = FR_INVALID_NAME; } #if FF_FS_LOCK != 0 else { res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); /* Check if the file can be used */ } #endif } /* Create or Open a file */ if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { if (res != FR_OK) { /* No file, create new */ if (res == FR_NO_FILE) { /* There is no file to open, create a new entry */ #if FF_FS_LOCK != 0 res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; #else res = dir_register(&dj); #endif } mode |= FA_CREATE_ALWAYS; /* File is created */ } else { /* Any object with the same name is already existing */ if (dj.obj.attr & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ res = FR_DENIED; } else { if (mode & FA_CREATE_NEW) res = FR_EXIST; /* Cannot create as new file */ } } if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate the file if overwrite mode */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* Get current allocation info */ fp->obj.fs = fs; init_alloc_info(fs, &fp->obj); /* Set directory entry block initial state */ mem_set(fs->dirbuf + 2, 0, 30); /* Clear 85 entry except for NumSec */ mem_set(fs->dirbuf + 38, 0, 26); /* Clear C0 entry except for NumName and NameHash */ fs->dirbuf[XDIR_Attr] = AM_ARC; st_dword(fs->dirbuf + XDIR_CrtTime, GET_FATTIME()); fs->dirbuf[XDIR_GenFlags] = 1; res = store_xdir(&dj); if (res == FR_OK && fp->obj.sclust != 0) { /* Remove the cluster chain if exist */ res = remove_chain(&fp->obj, fp->obj.sclust, 0); fs->last_clst = fp->obj.sclust - 1; /* Reuse the cluster hole */ } } else #endif { /* Set directory entry initial state */ cl = ld_clust(fs, dj.dir); /* Get current cluster chain */ st_dword(dj.dir + DIR_CrtTime, GET_FATTIME()); /* Set created time */ dj.dir[DIR_Attr] = AM_ARC; /* Reset attribute */ st_clust(fs, dj.dir, 0); /* Reset file allocation info */ st_dword(dj.dir + DIR_FileSize, 0); fs->wflag = 1; if (cl != 0) { /* Remove the cluster chain if exist */ dw = fs->winsect; res = remove_chain(&dj.obj, cl, 0); if (res == FR_OK) { res = move_window(fs, dw); fs->last_clst = cl - 1; /* Reuse the cluster hole */ } } } } } else { /* Open an existing file */ if (res == FR_OK) { /* Is the object exsiting? */ if (dj.obj.attr & AM_DIR) { /* File open against a directory */ res = FR_NO_FILE; } else { if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* Write mode open against R/O file */ res = FR_DENIED; } } } } if (res == FR_OK) { if (mode & FA_CREATE_ALWAYS) mode |= FA_MODIFIED; /* Set file change flag if created or overwritten */ fp->dir_sect = fs->winsect; /* Pointer to the directory entry */ fp->dir_ptr = dj.dir; #if FF_FS_LOCK != 0 fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); /* Lock the file for this session */ if (fp->obj.lockid == 0) res = FR_INT_ERR; #endif } #else /* R/O configuration */ if (res == FR_OK) { if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it origin directory itself? */ res = FR_INVALID_NAME; } else { if (dj.obj.attr & AM_DIR) { /* Is it a directory? */ res = FR_NO_FILE; } } } #endif if (res == FR_OK) { #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { fp->obj.c_scl = dj.obj.sclust; /* Get containing directory info */ fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; fp->obj.c_ofs = dj.blk_ofs; init_alloc_info(fs, &fp->obj); } else #endif { fp->obj.sclust = ld_clust(fs, dj.dir); /* Get object allocation info */ fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize); } #if FF_USE_FASTSEEK fp->cltbl = 0; /* Disable fast seek mode */ #endif fp->obj.fs = fs; /* Validate the file object */ fp->obj.id = fs->id; fp->flag = mode; /* Set file access mode */ fp->err = 0; /* Clear error flag */ fp->sect = 0; /* Invalidate current data sector */ fp->fptr = 0; /* Set file pointer top of the file */ #if !FF_FS_READONLY #if !FF_FS_TINY mem_set(fp->buf, 0, FF_MAX_SS); /* Clear sector buffer */ #endif if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) { /* Seek to end of file if FA_OPEN_APPEND is specified */ fp->fptr = fp->obj.objsize; /* Offset to seek */ bcs = (DWORD)fs->csize * SS(fs); /* Cluster size in byte */ clst = fp->obj.sclust; /* Follow the cluster chain */ for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) { clst = get_fat(&fp->obj, clst); if (clst <= 1) res = FR_INT_ERR; if (clst == 0xFFFFFFFF) res = FR_DISK_ERR; } fp->clust = clst; if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */ if ((sc = clst2sect(fs, clst)) == 0) { res = FR_INT_ERR; } else { fp->sect = sc + (DWORD)(ofs / SS(fs)); #if !FF_FS_TINY if (disk_read(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR; #endif } } } #endif } FREE_NAMBUF(); } if (res != FR_OK) fp->obj.fs = 0; /* Invalidate file object on error */ LEAVE_FF(fs, res); } /*-----------------------------------------------------------------------*/ /* Read File */ /*-----------------------------------------------------------------------*/ FRESULT f_read ( FIL* fp, /* Pointer to the file object */ void* buff, /* Pointer to data buffer */ UINT btr, /* Number of bytes to read */ UINT* br /* Pointer to number of bytes read */ ) { FRESULT res; FATFS *fs; DWORD clst, sect; FSIZE_t remain; UINT rcnt, cc, csect; BYTE *rbuff = (BYTE*)buff; *br = 0; /* Clear read byte counter */ res = validate(&fp->obj, &fs); /* Check validity of the file object */ if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ remain = fp->obj.objsize - fp->fptr; if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ for ( ; btr; /* Repeat until btr bytes read */ btr -= rcnt, *br += rcnt, rbuff += rcnt, fp->fptr += rcnt) { if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ if (csect == 0) { /* On the cluster boundary? */ if (fp->fptr == 0) { /* On the top of the file? */ clst = fp->obj.sclust; /* Follow cluster chain from the origin */ } else { /* Middle or end of the file */ #if FF_USE_FASTSEEK if (fp->cltbl) { clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ } else #endif { clst = get_fat(&fp->obj, fp->clust); /* Follow cluster chain on the FAT */ } } if (clst < 2) ABORT(fs, FR_INT_ERR); if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); fp->clust = clst; /* Update current cluster */ } sect = clst2sect(fs, fp->clust); /* Get current sector */ if (sect == 0) ABORT(fs, FR_INT_ERR); sect += csect; cc = btr / SS(fs); /* When remaining bytes >= sector size, */ if (cc > 0) { /* Read maximum contiguous sectors directly */ if (csect + cc > fs->csize) { /* Clip at cluster boundary */ cc = fs->csize - csect; } if (disk_read(fs->pdrv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); #if !FF_FS_READONLY && FF_FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ #if FF_FS_TINY if (fs->wflag && fs->winsect - sect < cc) { mem_cpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs)); } #else if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) { mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); } #endif #endif rcnt = SS(fs) * cc; /* Number of bytes transferred */ continue; } #if !FF_FS_TINY if (fp->sect != sect) { /* Load data sector if not in cache */ #if !FF_FS_READONLY if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); fp->flag &= (BYTE)~FA_DIRTY; } #endif if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ } #endif fp->sect = sect; } rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */ if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ #if FF_FS_TINY if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ mem_cpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ #else mem_cpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ #endif } LEAVE_FF(fs, FR_OK); } #if !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* Write File */ /*-----------------------------------------------------------------------*/ FRESULT f_write ( FIL* fp, /* Pointer to the file object */ const void* buff, /* Pointer to the data to be written */ UINT btw, /* Number of bytes to write */ UINT* bw /* Pointer to number of bytes written */ ) { FRESULT res; FATFS *fs; DWORD clst, sect; UINT wcnt, cc, csect; const BYTE *wbuff = (const BYTE*)buff; *bw = 0; /* Clear write byte counter */ res = validate(&fp->obj, &fs); /* Check validity of the file object */ if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ /* Check fptr wrap-around (file size cannot reach 4 GiB at FAT volume) */ if ((!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) { btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr); } for ( ; btw; /* Repeat until all data written */ btw -= wcnt, *bw += wcnt, wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize) { if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ if (csect == 0) { /* On the cluster boundary? */ if (fp->fptr == 0) { /* On the top of the file? */ clst = fp->obj.sclust; /* Follow from the origin */ if (clst == 0) { /* If no cluster is allocated, */ clst = create_chain(&fp->obj, 0); /* create a new cluster chain */ } } else { /* On the middle or end of the file */ #if FF_USE_FASTSEEK if (fp->cltbl) { clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ } else #endif { clst = create_chain(&fp->obj, fp->clust); /* Follow or stretch cluster chain on the FAT */ } } if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ if (clst == 1) ABORT(fs, FR_INT_ERR); if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); fp->clust = clst; /* Update current cluster */ if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */ } #if FF_FS_TINY if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Write-back sector cache */ #else if (fp->flag & FA_DIRTY) { /* Write-back sector cache */ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); fp->flag &= (BYTE)~FA_DIRTY; } #endif sect = clst2sect(fs, fp->clust); /* Get current sector */ if (sect == 0) ABORT(fs, FR_INT_ERR); sect += csect; cc = btw / SS(fs); /* When remaining bytes >= sector size, */ if (cc > 0) { /* Write maximum contiguous sectors directly */ if (csect + cc > fs->csize) { /* Clip at cluster boundary */ cc = fs->csize - csect; } if (disk_write(fs->pdrv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); #if FF_FS_MINIMIZE <= 2 #if FF_FS_TINY if (fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ mem_cpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs)); fs->wflag = 0; } #else if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs)); fp->flag &= (BYTE)~FA_DIRTY; } #endif #endif wcnt = SS(fs) * cc; /* Number of bytes transferred */ continue; } #if FF_FS_TINY if (fp->fptr >= fp->obj.objsize) { /* Avoid silly cache filling on the growing edge */ if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); fs->winsect = sect; } #else if (fp->sect != sect && /* Fill sector cache with file data */ fp->fptr < fp->obj.objsize && disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) { ABORT(fs, FR_DISK_ERR); } #endif fp->sect = sect; } wcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */ if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ #if FF_FS_TINY if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ mem_cpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ fs->wflag = 1; #else mem_cpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ fp->flag |= FA_DIRTY; #endif } fp->flag |= FA_MODIFIED; /* Set file change flag */ LEAVE_FF(fs, FR_OK); } /*-----------------------------------------------------------------------*/ /* Synchronize the File */ /*-----------------------------------------------------------------------*/ FRESULT f_sync ( FIL* fp /* Pointer to the file object */ ) { FRESULT res; FATFS *fs; DWORD tm; BYTE *dir; res = validate(&fp->obj, &fs); /* Check validity of the file object */ if (res == FR_OK) { if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */ #if !FF_FS_TINY if (fp->flag & FA_DIRTY) { /* Write-back cached data if needed */ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR); fp->flag &= (BYTE)~FA_DIRTY; } #endif /* Update the directory entry */ tm = GET_FATTIME(); /* Modified time */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { res = fill_first_frag(&fp->obj); /* Fill first fragment on the FAT if needed */ if (res == FR_OK) { res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */ } if (res == FR_OK) { DIR dj; DEF_NAMBUF INIT_NAMBUF(fs); res = load_obj_xdir(&dj, &fp->obj); /* Load directory entry block */ if (res == FR_OK) { fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute to indicate that the file has been changed */ fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1; /* Update file allocation information */ st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust); st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize); st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize); st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Update modified time */ fs->dirbuf[XDIR_ModTime10] = 0; st_dword(fs->dirbuf + XDIR_AccTime, 0); res = store_xdir(&dj); /* Restore it to the directory */ if (res == FR_OK) { res = sync_fs(fs); fp->flag &= (BYTE)~FA_MODIFIED; } } FREE_NAMBUF(); } } else #endif { res = move_window(fs, fp->dir_sect); if (res == FR_OK) { dir = fp->dir_ptr; dir[DIR_Attr] |= AM_ARC; /* Set archive attribute to indicate that the file has been changed */ st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation information */ st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize); /* Update file size */ st_dword(dir + DIR_ModTime, tm); /* Update modified time */ st_word(dir + DIR_LstAccDate, 0); fs->wflag = 1; res = sync_fs(fs); /* Restore it to the directory */ fp->flag &= (BYTE)~FA_MODIFIED; } } } } LEAVE_FF(fs, res); } #endif /* !FF_FS_READONLY */ /*-----------------------------------------------------------------------*/ /* Close File */ /*-----------------------------------------------------------------------*/ FRESULT f_close ( FIL* fp /* Pointer to the file object to be closed */ ) { FRESULT res; FATFS *fs; #if !FF_FS_READONLY res = f_sync(fp); /* Flush cached data */ if (res == FR_OK) #endif { res = validate(&fp->obj, &fs); /* Lock volume */ if (res == FR_OK) { #if FF_FS_LOCK != 0 res = dec_lock(fp->obj.lockid); /* Decrement file open counter */ if (res == FR_OK) fp->obj.fs = 0; /* Invalidate file object */ #else fp->obj.fs = 0; /* Invalidate file object */ #endif #if FF_FS_REENTRANT unlock_fs(fs, FR_OK); /* Unlock volume */ #endif } } return res; } #if FF_FS_RPATH >= 1 /*-----------------------------------------------------------------------*/ /* Change Current Directory or Current Drive, Get Current Directory */ /*-----------------------------------------------------------------------*/ FRESULT f_chdrive ( const TCHAR* path /* Drive number to set */ ) { int vol; /* Get logical drive number */ vol = get_ldnumber(&path); if (vol < 0) return FR_INVALID_DRIVE; CurrVol = (BYTE)vol; /* Set it as current volume */ return FR_OK; } FRESULT f_chdir ( const TCHAR* path /* Pointer to the directory path */ ) { #if FF_STR_VOLUME_ID == 2 UINT i; #endif FRESULT res; DIR dj; FATFS *fs; DEF_NAMBUF /* Get logical drive */ res = find_volume(&path, &fs, 0); if (res == FR_OK) { dj.obj.fs = fs; INIT_NAMBUF(fs); res = follow_path(&dj, path); /* Follow the path */ if (res == FR_OK) { /* Follow completed */ if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it the start directory itself? */ fs->cdir = dj.obj.sclust; #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { fs->cdc_scl = dj.obj.c_scl; fs->cdc_size = dj.obj.c_size; fs->cdc_ofs = dj.obj.c_ofs; } #endif } else { if (dj.obj.attr & AM_DIR) { /* It is a sub-directory */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus); /* Sub-directory cluster */ fs->cdc_scl = dj.obj.sclust; /* Save containing directory information */ fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; fs->cdc_ofs = dj.blk_ofs; } else #endif { fs->cdir = ld_clust(fs, dj.dir); /* Sub-directory cluster */ } } else { res = FR_NO_PATH; /* Reached but a file */ } } } FREE_NAMBUF(); if (res == FR_NO_FILE) res = FR_NO_PATH; #if FF_STR_VOLUME_ID == 2 /* Also current drive is changed at Unix style volume ID */ if (res == FR_OK) { for (i = FF_VOLUMES - 1; i && fs != FatFs[i]; i--) ; /* Set current drive */ CurrVol = (BYTE)i; } #endif } LEAVE_FF(fs, res); } #if FF_FS_RPATH >= 2 FRESULT f_getcwd ( TCHAR* buff, /* Pointer to the directory path */ UINT len /* Size of buff in unit of TCHAR */ ) { FRESULT res; DIR dj; FATFS *fs; UINT i, n; DWORD ccl; TCHAR *tp = buff; #if FF_VOLUMES >= 2 UINT vl; #endif #if FF_STR_VOLUME_ID const char *vp; #endif FILINFO fno; DEF_NAMBUF /* Get logical drive */ res = find_volume((const TCHAR**)&buff, &fs, 0); /* Get current volume */ if (res == FR_OK) { dj.obj.fs = fs; INIT_NAMBUF(fs); /* Follow parent directories and create the path */ i = len; /* Bottom of buffer (directory stack base) */ if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { /* (Cannot do getcwd on exFAT and returns root path) */ dj.obj.sclust = fs->cdir; /* Start to follow upper directory from current directory */ while ((ccl = dj.obj.sclust) != 0) { /* Repeat while current directory is a sub-directory */ res = dir_sdi(&dj, 1 * SZDIRE); /* Get parent directory */ if (res != FR_OK) break; res = move_window(fs, dj.sect); if (res != FR_OK) break; dj.obj.sclust = ld_clust(fs, dj.dir); /* Goto parent directory */ res = dir_sdi(&dj, 0); if (res != FR_OK) break; do { /* Find the entry links to the child directory */ res = dir_read_file(&dj); if (res != FR_OK) break; if (ccl == ld_clust(fs, dj.dir)) break; /* Found the entry */ res = dir_next(&dj, 0); } while (res == FR_OK); if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ if (res != FR_OK) break; get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */ for (n = 0; fno.fname[n]; n++) ; /* Name length */ if (i < n + 1) { /* Insufficient space to store the path name? */ res = FR_NOT_ENOUGH_CORE; break; } while (n) buff[--i] = fno.fname[--n]; /* Stack the name */ buff[--i] = '/'; } } if (res == FR_OK) { if (i == len) buff[--i] = '/'; /* Is it the root-directory? */ #if FF_VOLUMES >= 2 /* Put drive prefix */ vl = 0; #if FF_STR_VOLUME_ID >= 1 /* String volume ID */ for (n = 0, vp = (const char*)VolumeStr[CurrVol]; vp[n]; n++) ; if (i >= n + 2) { if (FF_STR_VOLUME_ID == 2) *tp++ = (TCHAR)'/'; for (vl = 0; vl < n; *tp++ = (TCHAR)vp[vl], vl++) ; if (FF_STR_VOLUME_ID == 1) *tp++ = (TCHAR)':'; vl++; } #else /* Numeric volume ID */ if (i >= 3) { *tp++ = (TCHAR)'0' + CurrVol; *tp++ = (TCHAR)':'; vl = 2; } #endif if (vl == 0) res = FR_NOT_ENOUGH_CORE; #endif /* Add current directory path */ if (res == FR_OK) { do *tp++ = buff[i++]; while (i < len); /* Copy stacked path string */ } } FREE_NAMBUF(); } *tp = 0; LEAVE_FF(fs, res); } #endif /* FF_FS_RPATH >= 2 */ #endif /* FF_FS_RPATH >= 1 */ #if FF_FS_MINIMIZE <= 2 /*-----------------------------------------------------------------------*/ /* Seek File Read/Write Pointer */ /*-----------------------------------------------------------------------*/ FRESULT f_lseek ( FIL* fp, /* Pointer to the file object */ FSIZE_t ofs /* File pointer from top of file */ ) { FRESULT res; FATFS *fs; DWORD clst, bcs, nsect; FSIZE_t ifptr; #if FF_USE_FASTSEEK DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl; #endif res = validate(&fp->obj, &fs); /* Check validity of the file object */ if (res == FR_OK) res = (FRESULT)fp->err; #if FF_FS_EXFAT && !FF_FS_READONLY if (res == FR_OK && fs->fs_type == FS_EXFAT) { res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */ } #endif if (res != FR_OK) LEAVE_FF(fs, res); #if FF_USE_FASTSEEK if (fp->cltbl) { /* Fast seek */ if (ofs == CREATE_LINKMAP) { /* Create CLMT */ tbl = fp->cltbl; tlen = *tbl++; ulen = 2; /* Given table size and required table size */ cl = fp->obj.sclust; /* Origin of the chain */ if (cl != 0) { do { /* Get a fragment */ tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ do { pcl = cl; ncl++; cl = get_fat(&fp->obj, cl); if (cl <= 1) ABORT(fs, FR_INT_ERR); if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); } while (cl == pcl + 1); if (ulen <= tlen) { /* Store the length and top of the fragment */ *tbl++ = ncl; *tbl++ = tcl; } } while (cl < fs->n_fatent); /* Repeat until end of chain */ } *fp->cltbl = ulen; /* Number of items used */ if (ulen <= tlen) { *tbl = 0; /* Terminate table */ } else { res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ } } else { /* Fast seek */ if (ofs > fp->obj.objsize) ofs = fp->obj.objsize; /* Clip offset at the file size */ fp->fptr = ofs; /* Set file pointer */ if (ofs > 0) { fp->clust = clmt_clust(fp, ofs - 1); dsc = clst2sect(fs, fp->clust); if (dsc == 0) ABORT(fs, FR_INT_ERR); dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ #if !FF_FS_TINY #if !FF_FS_READONLY if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); fp->flag &= (BYTE)~FA_DIRTY; } #endif if (disk_read(fs->pdrv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Load current sector */ #endif fp->sect = dsc; } } } } else #endif /* Normal Seek */ { #if FF_FS_EXFAT if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF; /* Clip at 4 GiB - 1 if at FATxx */ #endif if (ofs > fp->obj.objsize && (FF_FS_READONLY || !(fp->flag & FA_WRITE))) { /* In read-only mode, clip offset with the file size */ ofs = fp->obj.objsize; } ifptr = fp->fptr; fp->fptr = nsect = 0; if (ofs > 0) { bcs = (DWORD)fs->csize * SS(fs); /* Cluster size (byte) */ if (ifptr > 0 && (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */ ofs -= fp->fptr; clst = fp->clust; } else { /* When seek to back cluster, */ clst = fp->obj.sclust; /* start from the first cluster */ #if !FF_FS_READONLY if (clst == 0) { /* If no cluster chain, create a new chain */ clst = create_chain(&fp->obj, 0); if (clst == 1) ABORT(fs, FR_INT_ERR); if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); fp->obj.sclust = clst; } #endif fp->clust = clst; } if (clst != 0) { while (ofs > bcs) { /* Cluster following loop */ ofs -= bcs; fp->fptr += bcs; #if !FF_FS_READONLY if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ if (FF_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize to generate FAT value */ fp->obj.objsize = fp->fptr; fp->flag |= FA_MODIFIED; } clst = create_chain(&fp->obj, clst); /* Follow chain with forceed stretch */ if (clst == 0) { /* Clip file size in case of disk full */ ofs = 0; break; } } else #endif { clst = get_fat(&fp->obj, clst); /* Follow cluster chain if not in write mode */ } if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); fp->clust = clst; } fp->fptr += ofs; if (ofs % SS(fs)) { nsect = clst2sect(fs, clst); /* Current sector */ if (nsect == 0) ABORT(fs, FR_INT_ERR); nsect += (DWORD)(ofs / SS(fs)); } } } if (!FF_FS_READONLY && fp->fptr > fp->obj.objsize) { /* Set file change flag if the file size is extended */ fp->obj.objsize = fp->fptr; fp->flag |= FA_MODIFIED; } if (fp->fptr % SS(fs) && nsect != fp->sect) { /* Fill sector cache if needed */ #if !FF_FS_TINY #if !FF_FS_READONLY if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); fp->flag &= (BYTE)~FA_DIRTY; } #endif if (disk_read(fs->pdrv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ #endif fp->sect = nsect; } } LEAVE_FF(fs, res); } #if FF_FS_MINIMIZE <= 1 /*-----------------------------------------------------------------------*/ /* Create a Directory Object */ /*-----------------------------------------------------------------------*/ FRESULT f_opendir ( DIR* dp, /* Pointer to directory object to create */ const TCHAR* path /* Pointer to the directory path */ ) { FRESULT res; FATFS *fs; DEF_NAMBUF if (!dp) return FR_INVALID_OBJECT; /* Get logical drive */ res = find_volume(&path, &fs, 0); if (res == FR_OK) { dp->obj.fs = fs; INIT_NAMBUF(fs); res = follow_path(dp, path); /* Follow the path to the directory */ if (res == FR_OK) { /* Follow completed */ if (!(dp->fn[NSFLAG] & NS_NONAME)) { /* It is not the origin directory itself */ if (dp->obj.attr & AM_DIR) { /* This object is a sub-directory */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { dp->obj.c_scl = dp->obj.sclust; /* Get containing directory inforamation */ dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat; dp->obj.c_ofs = dp->blk_ofs; init_alloc_info(fs, &dp->obj); /* Get object allocation info */ } else #endif { dp->obj.sclust = ld_clust(fs, dp->dir); /* Get object allocation info */ } } else { /* This object is a file */ res = FR_NO_PATH; } } if (res == FR_OK) { dp->obj.id = fs->id; res = dir_sdi(dp, 0); /* Rewind directory */ #if FF_FS_LOCK != 0 if (res == FR_OK) { if (dp->obj.sclust != 0) { dp->obj.lockid = inc_lock(dp, 0); /* Lock the sub directory */ if (!dp->obj.lockid) res = FR_TOO_MANY_OPEN_FILES; } else { dp->obj.lockid = 0; /* Root directory need not to be locked */ } } #endif } } FREE_NAMBUF(); if (res == FR_NO_FILE) res = FR_NO_PATH; } if (res != FR_OK) dp->obj.fs = 0; /* Invalidate the directory object if function faild */ LEAVE_FF(fs, res); } /*-----------------------------------------------------------------------*/ /* Close Directory */ /*-----------------------------------------------------------------------*/ FRESULT f_closedir ( DIR *dp /* Pointer to the directory object to be closed */ ) { FRESULT res; FATFS *fs; res = validate(&dp->obj, &fs); /* Check validity of the file object */ if (res == FR_OK) { #if FF_FS_LOCK != 0 if (dp->obj.lockid) res = dec_lock(dp->obj.lockid); /* Decrement sub-directory open counter */ if (res == FR_OK) dp->obj.fs = 0; /* Invalidate directory object */ #else dp->obj.fs = 0; /* Invalidate directory object */ #endif #if FF_FS_REENTRANT unlock_fs(fs, FR_OK); /* Unlock volume */ #endif } return res; } /*-----------------------------------------------------------------------*/ /* Read Directory Entries in Sequence */ /*-----------------------------------------------------------------------*/ FRESULT f_readdir ( DIR* dp, /* Pointer to the open directory object */ FILINFO* fno /* Pointer to file information to return */ ) { FRESULT res; FATFS *fs; DEF_NAMBUF res = validate(&dp->obj, &fs); /* Check validity of the directory object */ if (res == FR_OK) { if (!fno) { res = dir_sdi(dp, 0); /* Rewind the directory object */ } else { INIT_NAMBUF(fs); res = dir_read_file(dp); /* Read an item */ if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */ if (res == FR_OK) { /* A valid entry is found */ get_fileinfo(dp, fno); /* Get the object information */ res = dir_next(dp, 0); /* Increment index for next */ if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */ } FREE_NAMBUF(); } } LEAVE_FF(fs, res); } #if FF_USE_FIND /*-----------------------------------------------------------------------*/ /* Find Next File */ /*-----------------------------------------------------------------------*/ FRESULT f_findnext ( DIR* dp, /* Pointer to the open directory object */ FILINFO* fno /* Pointer to the file information structure */ ) { FRESULT res; for (;;) { res = f_readdir(dp, fno); /* Get a directory item */ if (res != FR_OK || !fno || !fno->fname[0]) break; /* Terminate if any error or end of directory */ if (pattern_matching(dp->pat, fno->fname, 0, 0)) break; /* Test for the file name */ #if FF_USE_LFN && FF_USE_FIND == 2 if (pattern_matching(dp->pat, fno->altname, 0, 0)) break; /* Test for alternative name if exist */ #endif } return res; } /*-----------------------------------------------------------------------*/ /* Find First File */ /*-----------------------------------------------------------------------*/ FRESULT f_findfirst ( DIR* dp, /* Pointer to the blank directory object */ FILINFO* fno, /* Pointer to the file information structure */ const TCHAR* path, /* Pointer to the directory to open */ const TCHAR* pattern /* Pointer to the matching pattern */ ) { FRESULT res; dp->pat = pattern; /* Save pointer to pattern string */ res = f_opendir(dp, path); /* Open the target directory */ if (res == FR_OK) { res = f_findnext(dp, fno); /* Find the first item */ } return res; } #endif /* FF_USE_FIND */ #if FF_FS_MINIMIZE == 0 /*-----------------------------------------------------------------------*/ /* Get File Status */ /*-----------------------------------------------------------------------*/ FRESULT f_stat ( const TCHAR* path, /* Pointer to the file path */ FILINFO* fno /* Pointer to file information to return */ ) { FRESULT res; DIR dj; DEF_NAMBUF /* Get logical drive */ res = find_volume(&path, &dj.obj.fs, 0); if (res == FR_OK) { INIT_NAMBUF(dj.obj.fs); res = follow_path(&dj, path); /* Follow the file path */ if (res == FR_OK) { /* Follow completed */ if (dj.fn[NSFLAG] & NS_NONAME) { /* It is origin directory */ res = FR_INVALID_NAME; } else { /* Found an object */ if (fno) get_fileinfo(&dj, fno); } } FREE_NAMBUF(); } LEAVE_FF(dj.obj.fs, res); } #if !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* Get Number of Free Clusters */ /*-----------------------------------------------------------------------*/ FRESULT f_getfree ( const TCHAR* path, /* Logical drive number */ DWORD* nclst, /* Pointer to a variable to return number of free clusters */ FATFS** fatfs /* Pointer to return pointer to corresponding filesystem object */ ) { FRESULT res; FATFS *fs; DWORD nfree, clst, sect, stat; UINT i; FFOBJID obj; /* Get logical drive */ res = find_volume(&path, &fs, 0); if (res == FR_OK) { *fatfs = fs; /* Return ptr to the fs object */ /* If free_clst is valid, return it without full FAT scan */ if (fs->free_clst <= fs->n_fatent - 2) { *nclst = fs->free_clst; } else { /* Scan FAT to obtain number of free clusters */ nfree = 0; if (fs->fs_type == FS_FAT12) { /* FAT12: Scan bit field FAT entries */ clst = 2; obj.fs = fs; do { stat = get_fat(&obj, clst); if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } if (stat == 1) { res = FR_INT_ERR; break; } if (stat == 0) nfree++; } while (++clst < fs->n_fatent); } else { #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* exFAT: Scan allocation bitmap */ BYTE bm; UINT b; clst = fs->n_fatent - 2; /* Number of clusters */ sect = fs->database; /* Assuming bitmap starts at cluster 2 */ i = 0; /* Offset in the sector */ do { /* Counts numbuer of bits with zero in the bitmap */ if (i == 0) { res = move_window(fs, sect++); if (res != FR_OK) break; } for (b = 8, bm = fs->win[i]; b && clst; b--, clst--) { if (!(bm & 1)) nfree++; bm >>= 1; } i = (i + 1) % SS(fs); } while (clst); } else #endif { /* FAT16/32: Scan WORD/DWORD FAT entries */ clst = fs->n_fatent; /* Number of entries */ sect = fs->fatbase; /* Top of the FAT */ i = 0; /* Offset in the sector */ do { /* Counts numbuer of entries with zero in the FAT */ if (i == 0) { res = move_window(fs, sect++); if (res != FR_OK) break; } if (fs->fs_type == FS_FAT16) { if (ld_word(fs->win + i) == 0) nfree++; i += 2; } else { if ((ld_dword(fs->win + i) & 0x0FFFFFFF) == 0) nfree++; i += 4; } i %= SS(fs); } while (--clst); } } *nclst = nfree; /* Return the free clusters */ fs->free_clst = nfree; /* Now free_clst is valid */ fs->fsi_flag |= 1; /* FAT32: FSInfo is to be updated */ } } LEAVE_FF(fs, res); } /*-----------------------------------------------------------------------*/ /* Truncate File */ /*-----------------------------------------------------------------------*/ FRESULT f_truncate ( FIL* fp /* Pointer to the file object */ ) { FRESULT res; FATFS *fs; DWORD ncl; res = validate(&fp->obj, &fs); /* Check validity of the file object */ if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ if (fp->fptr < fp->obj.objsize) { /* Process when fptr is not on the eof */ if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ res = remove_chain(&fp->obj, fp->obj.sclust, 0); fp->obj.sclust = 0; } else { /* When truncate a part of the file, remove remaining clusters */ ncl = get_fat(&fp->obj, fp->clust); res = FR_OK; if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; if (ncl == 1) res = FR_INT_ERR; if (res == FR_OK && ncl < fs->n_fatent) { res = remove_chain(&fp->obj, ncl, fp->clust); } } fp->obj.objsize = fp->fptr; /* Set file size to current read/write point */ fp->flag |= FA_MODIFIED; #if !FF_FS_TINY if (res == FR_OK && (fp->flag & FA_DIRTY)) { if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) { res = FR_DISK_ERR; } else { fp->flag &= (BYTE)~FA_DIRTY; } } #endif if (res != FR_OK) ABORT(fs, res); } LEAVE_FF(fs, res); } /*-----------------------------------------------------------------------*/ /* Delete a File/Directory */ /*-----------------------------------------------------------------------*/ FRESULT f_unlink ( const TCHAR* path /* Pointer to the file or directory path */ ) { FRESULT res; DIR dj, sdj; DWORD dclst = 0; FATFS *fs; #if FF_FS_EXFAT FFOBJID obj; #endif DEF_NAMBUF /* Get logical drive */ res = find_volume(&path, &fs, FA_WRITE); if (res == FR_OK) { dj.obj.fs = fs; INIT_NAMBUF(fs); res = follow_path(&dj, path); /* Follow the file path */ if (FF_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) { res = FR_INVALID_NAME; /* Cannot remove dot entry */ } #if FF_FS_LOCK != 0 if (res == FR_OK) res = chk_lock(&dj, 2); /* Check if it is an open object */ #endif if (res == FR_OK) { /* The object is accessible */ if (dj.fn[NSFLAG] & NS_NONAME) { res = FR_INVALID_NAME; /* Cannot remove the origin directory */ } else { if (dj.obj.attr & AM_RDO) { res = FR_DENIED; /* Cannot remove R/O object */ } } if (res == FR_OK) { #if FF_FS_EXFAT obj.fs = fs; if (fs->fs_type == FS_EXFAT) { init_alloc_info(fs, &obj); dclst = obj.sclust; } else #endif { dclst = ld_clust(fs, dj.dir); } if (dj.obj.attr & AM_DIR) { /* Is it a sub-directory? */ #if FF_FS_RPATH != 0 if (dclst == fs->cdir) { /* Is it the current directory? */ res = FR_DENIED; } else #endif { sdj.obj.fs = fs; /* Open the sub-directory */ sdj.obj.sclust = dclst; #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { sdj.obj.objsize = obj.objsize; sdj.obj.stat = obj.stat; } #endif res = dir_sdi(&sdj, 0); if (res == FR_OK) { res = dir_read_file(&sdj); /* Test if the directory is empty */ if (res == FR_OK) res = FR_DENIED; /* Not empty? */ if (res == FR_NO_FILE) res = FR_OK; /* Empty? */ } } } } if (res == FR_OK) { res = dir_remove(&dj); /* Remove the directory entry */ if (res == FR_OK && dclst != 0) { /* Remove the cluster chain if exist */ #if FF_FS_EXFAT res = remove_chain(&obj, dclst, 0); #else res = remove_chain(&dj.obj, dclst, 0); #endif } if (res == FR_OK) res = sync_fs(fs); } } FREE_NAMBUF(); } LEAVE_FF(fs, res); } /*-----------------------------------------------------------------------*/ /* Create a Directory */ /*-----------------------------------------------------------------------*/ FRESULT f_mkdir ( const TCHAR* path /* Pointer to the directory path */ ) { FRESULT res; DIR dj; FATFS *fs; BYTE *dir; DWORD dcl, pcl, tm; DEF_NAMBUF /* Get logical drive */ res = find_volume(&path, &fs, FA_WRITE); if (res == FR_OK) { dj.obj.fs = fs; INIT_NAMBUF(fs); res = follow_path(&dj, path); /* Follow the file path */ if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ if (FF_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) { res = FR_INVALID_NAME; } if (res == FR_NO_FILE) { /* Can create a new directory */ dcl = create_chain(&dj.obj, 0); /* Allocate a cluster for the new directory table */ dj.obj.objsize = (DWORD)fs->csize * SS(fs); res = FR_OK; if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ if (dcl == 1) res = FR_INT_ERR; if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; if (res == FR_OK) res = sync_window(fs); /* Flush FAT */ tm = GET_FATTIME(); if (res == FR_OK) { /* Initialize the new directory table */ res = dir_clear(fs, dcl); /* Clean up the new table */ if (res == FR_OK && (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT)) { /* Create dot entries (FAT only) */ dir = fs->win; mem_set(dir + DIR_Name, ' ', 11); /* Create "." entry */ dir[DIR_Name] = '.'; dir[DIR_Attr] = AM_DIR; st_dword(dir + DIR_ModTime, tm); st_clust(fs, dir, dcl); mem_cpy(dir + SZDIRE, dir, SZDIRE); /* Create ".." entry */ dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust; st_clust(fs, dir + SZDIRE, pcl); fs->wflag = 1; } } if (res == FR_OK) { res = dir_register(&dj); /* Register the object to the directoy */ } if (res == FR_OK) { #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* Initialize directory entry block */ st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Created time */ st_dword(fs->dirbuf + XDIR_FstClus, dcl); /* Table start cluster */ st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)dj.obj.objsize); /* File size needs to be valid */ st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)dj.obj.objsize); fs->dirbuf[XDIR_GenFlags] = 3; /* Initialize the object flag */ fs->dirbuf[XDIR_Attr] = AM_DIR; /* Attribute */ res = store_xdir(&dj); } else #endif { dir = dj.dir; st_dword(dir + DIR_ModTime, tm); /* Created time */ st_clust(fs, dir, dcl); /* Table start cluster */ dir[DIR_Attr] = AM_DIR; /* Attribute */ fs->wflag = 1; } if (res == FR_OK) { res = sync_fs(fs); } } else { remove_chain(&dj.obj, dcl, 0); /* Could not register, remove cluster chain */ } } FREE_NAMBUF(); } LEAVE_FF(fs, res); } /*-----------------------------------------------------------------------*/ /* Rename a File/Directory */ /*-----------------------------------------------------------------------*/ FRESULT f_rename ( const TCHAR* path_old, /* Pointer to the object name to be renamed */ const TCHAR* path_new /* Pointer to the new name */ ) { FRESULT res; DIR djo, djn; FATFS *fs; BYTE buf[FF_FS_EXFAT ? SZDIRE * 2 : SZDIRE], *dir; DWORD dw; DEF_NAMBUF get_ldnumber(&path_new); /* Snip the drive number of new name off */ res = find_volume(&path_old, &fs, FA_WRITE); /* Get logical drive of the old object */ if (res == FR_OK) { djo.obj.fs = fs; INIT_NAMBUF(fs); res = follow_path(&djo, path_old); /* Check old object */ if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check validity of name */ #if FF_FS_LOCK != 0 if (res == FR_OK) { res = chk_lock(&djo, 2); } #endif if (res == FR_OK) { /* Object to be renamed is found */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* At exFAT volume */ BYTE nf, nn; WORD nh; mem_cpy(buf, fs->dirbuf, SZDIRE * 2); /* Save 85+C0 entry of old object */ mem_cpy(&djn, &djo, sizeof djo); res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ if (res == FR_OK) { /* Is new name already in use by any other object? */ res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; } if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ res = dir_register(&djn); /* Register the new entry */ if (res == FR_OK) { nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName]; nh = ld_word(fs->dirbuf + XDIR_NameHash); mem_cpy(fs->dirbuf, buf, SZDIRE * 2); /* Restore 85+C0 entry */ fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn; st_word(fs->dirbuf + XDIR_NameHash, nh); if (!(fs->dirbuf[XDIR_Attr] & AM_DIR)) fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */ /* Start of critical section where an interruption can cause a cross-link */ res = store_xdir(&djn); } } } else #endif { /* At FAT/FAT32 volume */ mem_cpy(buf, djo.dir, SZDIRE); /* Save directory entry of the object */ mem_cpy(&djn, &djo, sizeof (DIR)); /* Duplicate the directory object */ res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ if (res == FR_OK) { /* Is new name already in use by any other object? */ res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; } if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ res = dir_register(&djn); /* Register the new entry */ if (res == FR_OK) { dir = djn.dir; /* Copy directory entry of the object except name */ mem_cpy(dir + 13, buf + 13, SZDIRE - 13); dir[DIR_Attr] = buf[DIR_Attr]; if (!(dir[DIR_Attr] & AM_DIR)) dir[DIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */ fs->wflag = 1; if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) { /* Update .. entry in the sub-directory if needed */ dw = clst2sect(fs, ld_clust(fs, dir)); if (dw == 0) { res = FR_INT_ERR; } else { /* Start of critical section where an interruption can cause a cross-link */ res = move_window(fs, dw); dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */ if (res == FR_OK && dir[1] == '.') { st_clust(fs, dir, djn.obj.sclust); fs->wflag = 1; } } } } } } if (res == FR_OK) { res = dir_remove(&djo); /* Remove old entry */ if (res == FR_OK) { res = sync_fs(fs); } } /* End of the critical section */ } FREE_NAMBUF(); } LEAVE_FF(fs, res); } #endif /* !FF_FS_READONLY */ #endif /* FF_FS_MINIMIZE == 0 */ #endif /* FF_FS_MINIMIZE <= 1 */ #endif /* FF_FS_MINIMIZE <= 2 */ #if FF_USE_CHMOD && !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* Change Attribute */ /*-----------------------------------------------------------------------*/ FRESULT f_chmod ( const TCHAR* path, /* Pointer to the file path */ BYTE attr, /* Attribute bits */ BYTE mask /* Attribute mask to change */ ) { FRESULT res; DIR dj; FATFS *fs; DEF_NAMBUF res = find_volume(&path, &fs, FA_WRITE); /* Get logical drive */ if (res == FR_OK) { dj.obj.fs = fs; INIT_NAMBUF(fs); res = follow_path(&dj, path); /* Follow the file path */ if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ if (res == FR_OK) { mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask); /* Apply attribute change */ res = store_xdir(&dj); } else #endif { dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ fs->wflag = 1; } if (res == FR_OK) { res = sync_fs(fs); } } FREE_NAMBUF(); } LEAVE_FF(fs, res); } /*-----------------------------------------------------------------------*/ /* Change Timestamp */ /*-----------------------------------------------------------------------*/ FRESULT f_utime ( const TCHAR* path, /* Pointer to the file/directory name */ const FILINFO* fno /* Pointer to the timestamp to be set */ ) { FRESULT res; DIR dj; FATFS *fs; DEF_NAMBUF res = find_volume(&path, &fs, FA_WRITE); /* Get logical drive */ if (res == FR_OK) { dj.obj.fs = fs; INIT_NAMBUF(fs); res = follow_path(&dj, path); /* Follow the file path */ if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ if (res == FR_OK) { #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); res = store_xdir(&dj); } else #endif { st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); fs->wflag = 1; } if (res == FR_OK) { res = sync_fs(fs); } } FREE_NAMBUF(); } LEAVE_FF(fs, res); } #endif /* FF_USE_CHMOD && !FF_FS_READONLY */ #if FF_USE_LABEL /*-----------------------------------------------------------------------*/ /* Get Volume Label */ /*-----------------------------------------------------------------------*/ FRESULT f_getlabel ( const TCHAR* path, /* Logical drive number */ TCHAR* label, /* Buffer to store the volume label */ DWORD* vsn /* Variable to store the volume serial number */ ) { FRESULT res; DIR dj; FATFS *fs; UINT si, di; WCHAR wc; /* Get logical drive */ res = find_volume(&path, &fs, 0); /* Get volume label */ if (res == FR_OK && label) { dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ res = dir_sdi(&dj, 0); if (res == FR_OK) { res = dir_read_label(&dj); /* Find a volume label entry */ if (res == FR_OK) { #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { WCHAR hs; for (si = di = hs = 0; si < dj.dir[XDIR_NumLabel]; si++) { /* Extract volume label from 83 entry */ wc = ld_word(dj.dir + XDIR_Label + si * 2); if (hs == 0 && IsSurrogate(wc)) { /* Is the code a surrogate? */ hs = wc; continue; } wc = put_utf((DWORD)hs << 16 | wc, &label[di], 4); if (wc == 0) { di = 0; break; } di += wc; hs = 0; } if (hs != 0) di = 0; /* Broken surrogate pair? */ label[di] = 0; } else #endif { si = di = 0; /* Extract volume label from AM_VOL entry */ while (si < 11) { wc = dj.dir[si++]; #if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode output */ if (dbc_1st((BYTE)wc) && si < 11) wc = wc << 8 | dj.dir[si++]; /* Is it a DBC? */ wc = ff_oem2uni(wc, CODEPAGE); /* Convert it into Unicode */ if (wc != 0) wc = put_utf(wc, &label[di], 4); /* Put it in Unicode */ if (wc == 0) { di = 0; break; } di += wc; #else /* ANSI/OEM output */ label[di++] = (TCHAR)wc; #endif } do { /* Truncate trailing spaces */ label[di] = 0; if (di == 0) break; } while (label[--di] == ' '); } } } if (res == FR_NO_FILE) { /* No label entry and return nul string */ label[0] = 0; res = FR_OK; } } /* Get volume serial number */ if (res == FR_OK && vsn) { res = move_window(fs, fs->volbase); if (res == FR_OK) { switch (fs->fs_type) { case FS_EXFAT: di = BPB_VolIDEx; break; case FS_FAT32: di = BS_VolID32; break; default: di = BS_VolID; } *vsn = ld_dword(fs->win + di); } } LEAVE_FF(fs, res); } #if !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* Set Volume Label */ /*-----------------------------------------------------------------------*/ FRESULT f_setlabel ( const TCHAR* label /* Volume label to set with heading logical drive number */ ) { FRESULT res; DIR dj; FATFS *fs; BYTE dirvn[22]; UINT di; WCHAR wc; static const char badchr[] = "+.,;=[]/\\\"*:<>\?|\x7F"; /* [0..] for FAT, [7..] for exFAT */ #if FF_USE_LFN DWORD dc; #endif /* Get logical drive */ res = find_volume(&label, &fs, FA_WRITE); if (res != FR_OK) LEAVE_FF(fs, res); #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ mem_set(dirvn, 0, 22); di = 0; while ((UINT)*label >= ' ') { /* Create volume label */ dc = tchar2uni(&label); /* Get a Unicode character */ if (dc >= 0x10000) { if (dc == 0xFFFFFFFF || di >= 10) { /* Wrong surrogate or buffer overflow */ dc = 0; } else { st_word(dirvn + di * 2, (WCHAR)(dc >> 16)); di++; } } if (dc == 0 || chk_chr(badchr + 7, (int)dc) || di >= 11) { /* Check validity of the volume label */ LEAVE_FF(fs, FR_INVALID_NAME); } st_word(dirvn + di * 2, (WCHAR)dc); di++; } } else #endif { /* On the FAT/FAT32 volume */ mem_set(dirvn, ' ', 11); di = 0; while ((UINT)*label >= ' ') { /* Create volume label */ #if FF_USE_LFN dc = tchar2uni(&label); wc = (dc < 0x10000) ? ff_uni2oem(ff_wtoupper(dc), CODEPAGE) : 0; #else /* ANSI/OEM input */ wc = (BYTE)*label++; if (dbc_1st((BYTE)wc)) wc = dbc_2nd((BYTE)*label) ? wc << 8 | (BYTE)*label++ : 0; if (IsLower(wc)) wc -= 0x20; /* To upper ASCII characters */ #if FF_CODE_PAGE == 0 if (ExCvt && wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */ #elif FF_CODE_PAGE < 900 if (wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */ #endif #endif if (wc == 0 || chk_chr(badchr + 0, (int)wc) || di >= (UINT)((wc >= 0x100) ? 10 : 11)) { /* Reject invalid characters for volume label */ LEAVE_FF(fs, FR_INVALID_NAME); } if (wc >= 0x100) dirvn[di++] = (BYTE)(wc >> 8); dirvn[di++] = (BYTE)wc; } if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME); /* Reject illegal name (heading DDEM) */ while (di && dirvn[di - 1] == ' ') di--; /* Snip trailing spaces */ } /* Set volume label */ dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ res = dir_sdi(&dj, 0); if (res == FR_OK) { res = dir_read_label(&dj); /* Get volume label entry */ if (res == FR_OK) { if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { dj.dir[XDIR_NumLabel] = (BYTE)di; /* Change the volume label */ mem_cpy(dj.dir + XDIR_Label, dirvn, 22); } else { if (di != 0) { mem_cpy(dj.dir, dirvn, 11); /* Change the volume label */ } else { dj.dir[DIR_Name] = DDEM; /* Remove the volume label */ } } fs->wflag = 1; res = sync_fs(fs); } else { /* No volume label entry or an error */ if (res == FR_NO_FILE) { res = FR_OK; if (di != 0) { /* Create a volume label entry */ res = dir_alloc(&dj, 1); /* Allocate an entry */ if (res == FR_OK) { mem_set(dj.dir, 0, SZDIRE); /* Clean the entry */ if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { dj.dir[XDIR_Type] = 0x83; /* Create 83 entry */ dj.dir[XDIR_NumLabel] = (BYTE)di; mem_cpy(dj.dir + XDIR_Label, dirvn, 22); } else { dj.dir[DIR_Attr] = AM_VOL; /* Create volume label entry */ mem_cpy(dj.dir, dirvn, 11); } fs->wflag = 1; res = sync_fs(fs); } } } } } LEAVE_FF(fs, res); } #endif /* !FF_FS_READONLY */ #endif /* FF_USE_LABEL */ #if FF_USE_EXPAND && !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* Allocate a Contiguous Blocks to the File */ /*-----------------------------------------------------------------------*/ FRESULT f_expand ( FIL* fp, /* Pointer to the file object */ FSIZE_t fsz, /* File size to be expanded to */ BYTE opt /* Operation mode 0:Find and prepare or 1:Find and allocate */ ) { FRESULT res; FATFS *fs; DWORD n, clst, stcl, scl, ncl, tcl, lclst; res = validate(&fp->obj, &fs); /* Check validity of the file object */ if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); #if FF_FS_EXFAT if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED); /* Check if in size limit */ #endif n = (DWORD)fs->csize * SS(fs); /* Cluster size */ tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0); /* Number of clusters required */ stcl = fs->last_clst; lclst = 0; if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2; #if FF_FS_EXFAT if (fs->fs_type == FS_EXFAT) { scl = find_bitmap(fs, stcl, tcl); /* Find a contiguous cluster block */ if (scl == 0) res = FR_DENIED; /* No contiguous cluster block was found */ if (scl == 0xFFFFFFFF) res = FR_DISK_ERR; if (res == FR_OK) { /* A contiguous free area is found */ if (opt) { /* Allocate it now */ res = change_bitmap(fs, scl, tcl, 1); /* Mark the cluster block 'in use' */ lclst = scl + tcl - 1; } else { /* Set it as suggested point for next allocation */ lclst = scl - 1; } } } else #endif { scl = clst = stcl; ncl = 0; for (;;) { /* Find a contiguous cluster block */ n = get_fat(&fp->obj, clst); if (++clst >= fs->n_fatent) clst = 2; if (n == 1) { res = FR_INT_ERR; break; } if (n == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } if (n == 0) { /* Is it a free cluster? */ if (++ncl == tcl) break; /* Break if a contiguous cluster block is found */ } else { scl = clst; ncl = 0; /* Not a free cluster */ } if (clst == stcl) { res = FR_DENIED; break; } /* No contiguous cluster? */ } if (res == FR_OK) { /* A contiguous free area is found */ if (opt) { /* Allocate it now */ for (clst = scl, n = tcl; n; clst++, n--) { /* Create a cluster chain on the FAT */ res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1); if (res != FR_OK) break; lclst = clst; } } else { /* Set it as suggested point for next allocation */ lclst = scl - 1; } } } if (res == FR_OK) { fs->last_clst = lclst; /* Set suggested start cluster to start next */ if (opt) { /* Is it allocated now? */ fp->obj.sclust = scl; /* Update object allocation information */ fp->obj.objsize = fsz; if (FF_FS_EXFAT) fp->obj.stat = 2; /* Set status 'contiguous chain' */ fp->flag |= FA_MODIFIED; if (fs->free_clst <= fs->n_fatent - 2) { /* Update FSINFO */ fs->free_clst -= tcl; fs->fsi_flag |= 1; } } } LEAVE_FF(fs, res); } #endif /* FF_USE_EXPAND && !FF_FS_READONLY */ #if FF_USE_FORWARD /*-----------------------------------------------------------------------*/ /* Forward Data to the Stream Directly */ /*-----------------------------------------------------------------------*/ FRESULT f_forward ( FIL* fp, /* Pointer to the file object */ UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ UINT btf, /* Number of bytes to forward */ UINT* bf /* Pointer to number of bytes forwarded */ ) { FRESULT res; FATFS *fs; DWORD clst, sect; FSIZE_t remain; UINT rcnt, csect; BYTE *dbuf; *bf = 0; /* Clear transfer byte counter */ res = validate(&fp->obj, &fs); /* Check validity of the file object */ if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ remain = fp->obj.objsize - fp->fptr; if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ for ( ; btf && (*func)(0, 0); /* Repeat until all data transferred or stream goes busy */ fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ if (csect == 0) { /* On the cluster boundary? */ clst = (fp->fptr == 0) ? /* On the top of the file? */ fp->obj.sclust : get_fat(&fp->obj, fp->clust); if (clst <= 1) ABORT(fs, FR_INT_ERR); if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); fp->clust = clst; /* Update current cluster */ } } sect = clst2sect(fs, fp->clust); /* Get current data sector */ if (sect == 0) ABORT(fs, FR_INT_ERR); sect += csect; #if FF_FS_TINY if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window to the file data */ dbuf = fs->win; #else if (fp->sect != sect) { /* Fill sector cache with file data */ #if !FF_FS_READONLY if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); fp->flag &= (BYTE)~FA_DIRTY; } #endif if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); } dbuf = fp->buf; #endif fp->sect = sect; rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */ if (rcnt > btf) rcnt = btf; /* Clip it by btr if needed */ rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt); /* Forward the file data */ if (rcnt == 0) ABORT(fs, FR_INT_ERR); } LEAVE_FF(fs, FR_OK); } #endif /* FF_USE_FORWARD */ #if FF_USE_MKFS && !FF_FS_READONLY /*-----------------------------------------------------------------------*/ /* Create an FAT/exFAT volume */ /*-----------------------------------------------------------------------*/ FRESULT f_mkfs ( const TCHAR* path, /* Logical drive number */ BYTE opt, /* Format option */ DWORD au, /* Size of allocation unit (cluster) [byte] */ void* work, /* Pointer to working buffer (null: use heap memory) */ UINT len /* Size of working buffer [byte] */ ) { const UINT n_fats = 1; /* Number of FATs for FAT/FAT32 volume (1 or 2) */ const UINT n_rootdir = 512; /* Number of root directory entries for FAT volume */ static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0}; /* Cluster size boundary for FAT volume (4Ks unit) */ static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0}; /* Cluster size boundary for FAT32 volume (128Ks unit) */ BYTE fmt, sys, *buf, *pte, pdrv, part; WORD ss; /* Sector size */ DWORD szb_buf, sz_buf, sz_blk, n_clst, pau, sect, nsect, n; DWORD b_vol, b_fat, b_data; /* Base LBA for volume, fat, data */ DWORD sz_vol, sz_rsv, sz_fat, sz_dir; /* Size for volume, fat, dir, data */ UINT i; int vol; DSTATUS stat; #if FF_USE_TRIM || FF_FS_EXFAT DWORD tbl[3]; #endif /* Check mounted drive and clear work area */ vol = get_ldnumber(&path); /* Get target logical drive */ if (vol < 0) return FR_INVALID_DRIVE; if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the volume if mounted */ pdrv = LD2PD(vol); /* Physical drive */ part = LD2PT(vol); /* Partition (0:create as new, 1-4:get from partition table) */ /* Check physical drive status */ stat = disk_initialize(pdrv); if (stat & STA_NOINIT) return FR_NOT_READY; if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & (sz_blk - 1))) sz_blk = 1; /* Erase block to align data area */ #if FF_MAX_SS != FF_MIN_SS /* Get sector size of the medium if variable sector size cfg. */ if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; #else ss = FF_MAX_SS; #endif if ((au != 0 && au < ss) || au > 0x1000000 || (au & (au - 1))) return FR_INVALID_PARAMETER; /* Check if au is valid */ au /= ss; /* Cluster size in unit of sector */ /* Get working buffer */ #if FF_USE_LFN == 3 if (!work) { /* Use heap memory for working buffer */ for (szb_buf = MAX_MALLOC, buf = 0; szb_buf >= ss && (buf = ff_memalloc(szb_buf)) == 0; szb_buf /= 2) ; sz_buf = szb_buf / ss; /* Size of working buffer (sector) */ } else #endif { buf = (BYTE*)work; /* Working buffer */ sz_buf = len / ss; /* Size of working buffer (sector) */ szb_buf = sz_buf * ss; /* Size of working buffer (byte) */ } if (!buf || sz_buf == 0) return FR_NOT_ENOUGH_CORE; /* Determine where the volume to be located (b_vol, sz_vol) */ if (FF_MULTI_PARTITION && part != 0) { /* Get partition information from partition table in the MBR */ if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Load MBR */ if (ld_word(buf + BS_55AA) != 0xAA55) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if MBR is valid */ pte = buf + (MBR_Table + (part - 1) * SZ_PTE); if (pte[PTE_System] == 0) LEAVE_MKFS(FR_MKFS_ABORTED); /* No partition? */ b_vol = ld_dword(pte + PTE_StLba); /* Get volume start sector */ sz_vol = ld_dword(pte + PTE_SizLba); /* Get volume size */ } else { /* Create a single-partition in this function */ if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); b_vol = (opt & FM_SFD) ? 0 : 63; /* Volume start sector */ if (sz_vol < b_vol) LEAVE_MKFS(FR_MKFS_ABORTED); sz_vol -= b_vol; /* Volume size */ } if (sz_vol < 128) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >=128s */ /* Pre-determine the FAT type */ do { if (FF_FS_EXFAT && (opt & FM_EXFAT)) { /* exFAT possible? */ if ((opt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || au > 128) { /* exFAT only, vol >= 64Ms or au > 128s ? */ fmt = FS_EXFAT; break; } } if (au > 128) LEAVE_MKFS(FR_INVALID_PARAMETER); /* Too large au for FAT/FAT32 */ if (opt & FM_FAT32) { /* FAT32 possible? */ if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) { /* FAT32 only or no-FAT? */ fmt = FS_FAT32; break; } } if (!(opt & FM_FAT)) LEAVE_MKFS(FR_INVALID_PARAMETER); /* no-FAT? */ fmt = FS_FAT16; } while (0); #if FF_FS_EXFAT if (fmt == FS_EXFAT) { /* Create an exFAT volume */ DWORD szb_bit, szb_case, sum, nb, cl; WCHAR ch, si; UINT j, st; BYTE b; if (sz_vol < 0x1000) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ #if FF_USE_TRIM tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1; /* Inform the device the volume area may be erased */ disk_ioctl(pdrv, CTRL_TRIM, tbl); #endif /* Determine FAT location, data location and number of clusters */ if (au == 0) { /* au auto-selection */ au = 8; if (sz_vol >= 0x80000) au = 64; /* >= 512Ks */ if (sz_vol >= 0x4000000) au = 256; /* >= 64Ms */ } b_fat = b_vol + 32; /* FAT start at offset 32 */ sz_fat = ((sz_vol / au + 2) * 4 + ss - 1) / ss; /* Number of FAT sectors */ b_data = (b_fat + sz_fat + sz_blk - 1) & ~(sz_blk - 1); /* Align data area to the erase block boundary */ if (b_data >= sz_vol / 2) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ n_clst = (sz_vol - (b_data - b_vol)) / au; /* Number of clusters */ if (n_clst <16) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too few clusters? */ if (n_clst > MAX_EXFAT) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters? */ szb_bit = (n_clst + 7) / 8; /* Size of allocation bitmap */ tbl[0] = (szb_bit + au * ss - 1) / (au * ss); /* Number of allocation bitmap clusters */ /* Create a compressed up-case table */ sect = b_data + au * tbl[0]; /* Table start sector */ sum = 0; /* Table checksum to be stored in the 82 entry */ st = 0; si = 0; i = 0; j = 0; szb_case = 0; do { switch (st) { case 0: ch = (WCHAR)ff_wtoupper(si); /* Get an up-case char */ if (ch != si) { si++; break; /* Store the up-case char if exist */ } for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ; /* Get run length of no-case block */ if (j >= 128) { ch = 0xFFFF; st = 2; break; /* Compress the no-case block if run is >= 128 */ } st = 1; /* Do not compress short run */ /* go to next case */ case 1: ch = si++; /* Fill the short run */ if (--j == 0) st = 0; break; default: ch = (WCHAR)j; si += (WCHAR)j; /* Number of chars to skip */ st = 0; } sum = xsum32(buf[i + 0] = (BYTE)ch, sum); /* Put it into the write buffer */ sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum); i += 2; szb_case += 2; if (si == 0 || i == szb_buf) { /* Write buffered data when buffer full or end of process */ n = (i + ss - 1) / ss; if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); sect += n; i = 0; } } while (si); tbl[1] = (szb_case + au * ss - 1) / (au * ss); /* Number of up-case table clusters */ tbl[2] = 1; /* Number of root dir clusters */ /* Initialize the allocation bitmap */ sect = b_data; nsect = (szb_bit + ss - 1) / ss; /* Start of bitmap and number of sectors */ nb = tbl[0] + tbl[1] + tbl[2]; /* Number of clusters in-use by system */ do { mem_set(buf, 0, szb_buf); for (i = 0; nb >= 8 && i < szb_buf; buf[i++] = 0xFF, nb -= 8) ; for (b = 1; nb != 0 && i < szb_buf; buf[i] |= b, b <<= 1, nb--) ; n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); sect += n; nsect -= n; } while (nsect); /* Initialize the FAT */ sect = b_fat; nsect = sz_fat; /* Start of FAT and number of FAT sectors */ j = nb = cl = 0; do { mem_set(buf, 0, szb_buf); i = 0; /* Clear work area and reset write index */ if (cl == 0) { /* Set entry 0 and 1 */ st_dword(buf + i, 0xFFFFFFF8); i += 4; cl++; st_dword(buf + i, 0xFFFFFFFF); i += 4; cl++; } do { /* Create chains of bitmap, up-case and root dir */ while (nb != 0 && i < szb_buf) { /* Create a chain */ st_dword(buf + i, (nb > 1) ? cl + 1 : 0xFFFFFFFF); i += 4; cl++; nb--; } if (nb == 0 && j < 3) nb = tbl[j++]; /* Next chain */ } while (nb != 0 && i < szb_buf); n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); sect += n; nsect -= n; } while (nsect); /* Initialize the root directory */ mem_set(buf, 0, szb_buf); buf[SZDIRE * 0 + 0] = 0x83; /* 83 entry (volume label) */ buf[SZDIRE * 1 + 0] = 0x81; /* 81 entry (allocation bitmap) */ st_dword(buf + SZDIRE * 1 + 20, 2); /* cluster */ st_dword(buf + SZDIRE * 1 + 24, szb_bit); /* size */ buf[SZDIRE * 2 + 0] = 0x82; /* 82 entry (up-case table) */ st_dword(buf + SZDIRE * 2 + 4, sum); /* sum */ st_dword(buf + SZDIRE * 2 + 20, 2 + tbl[0]); /* cluster */ st_dword(buf + SZDIRE * 2 + 24, szb_case); /* size */ sect = b_data + au * (tbl[0] + tbl[1]); nsect = au; /* Start of the root directory and number of sectors */ do { /* Fill root directory sectors */ n = (nsect > sz_buf) ? sz_buf : nsect; if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); mem_set(buf, 0, ss); sect += n; nsect -= n; } while (nsect); /* Create two set of the exFAT VBR blocks */ sect = b_vol; for (n = 0; n < 2; n++) { /* Main record (+0) */ mem_set(buf, 0, ss); mem_cpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11); /* Boot jump code (x86), OEM name */ st_dword(buf + BPB_VolOfsEx, b_vol); /* Volume offset in the physical drive [sector] */ st_dword(buf + BPB_TotSecEx, sz_vol); /* Volume size [sector] */ st_dword(buf + BPB_FatOfsEx, b_fat - b_vol); /* FAT offset [sector] */ st_dword(buf + BPB_FatSzEx, sz_fat); /* FAT size [sector] */ st_dword(buf + BPB_DataOfsEx, b_data - b_vol); /* Data offset [sector] */ st_dword(buf + BPB_NumClusEx, n_clst); /* Number of clusters */ st_dword(buf + BPB_RootClusEx, 2 + tbl[0] + tbl[1]); /* Root dir cluster # */ st_dword(buf + BPB_VolIDEx, GET_FATTIME()); /* VSN */ st_word(buf + BPB_FSVerEx, 0x100); /* Filesystem version (1.00) */ for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ; /* Log2 of sector size [byte] */ for (buf[BPB_SecPerClusEx] = 0, i = au; i >>= 1; buf[BPB_SecPerClusEx]++) ; /* Log2 of cluster size [sector] */ buf[BPB_NumFATsEx] = 1; /* Number of FATs */ buf[BPB_DrvNumEx] = 0x80; /* Drive number (for int13) */ st_word(buf + BS_BootCodeEx, 0xFEEB); /* Boot code (x86) */ st_word(buf + BS_55AA, 0xAA55); /* Signature (placed here regardless of sector size) */ for (i = sum = 0; i < ss; i++) { /* VBR checksum */ if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum); } if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Extended bootstrap record (+1..+8) */ mem_set(buf, 0, ss); st_word(buf + ss - 2, 0xAA55); /* Signature (placed at end of sector) */ for (j = 1; j < 9; j++) { for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); } /* OEM/Reserved record (+9..+10) */ mem_set(buf, 0, ss); for ( ; j < 11; j++) { for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); } /* Sum record (+11) */ for (i = 0; i < ss; i += 4) st_dword(buf + i, sum); /* Fill with checksum value */ if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); } } else #endif /* FF_FS_EXFAT */ { /* Create an FAT/FAT32 volume */ do { pau = au; /* Pre-determine number of clusters and FAT sub-type */ if (fmt == FS_FAT32) { /* FAT32 volume */ if (pau == 0) { /* au auto-selection */ n = sz_vol / 0x20000; /* Volume size in unit of 128KS */ for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ; /* Get from table */ } n_clst = sz_vol / pau; /* Number of clusters */ sz_fat = (n_clst * 4 + 8 + ss - 1) / ss; /* FAT size [sector] */ sz_rsv = 32; /* Number of reserved sectors */ sz_dir = 0; /* No static directory */ if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) LEAVE_MKFS(FR_MKFS_ABORTED); } else { /* FAT volume */ if (pau == 0) { /* au auto-selection */ n = sz_vol / 0x1000; /* Volume size in unit of 4KS */ for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ; /* Get from table */ } n_clst = sz_vol / pau; if (n_clst > MAX_FAT12) { n = n_clst * 2 + 4; /* FAT size [byte] */ } else { fmt = FS_FAT12; n = (n_clst * 3 + 1) / 2 + 3; /* FAT size [byte] */ } sz_fat = (n + ss - 1) / ss; /* FAT size [sector] */ sz_rsv = 1; /* Number of reserved sectors */ sz_dir = (DWORD)n_rootdir * SZDIRE / ss; /* Rootdir size [sector] */ } b_fat = b_vol + sz_rsv; /* FAT base */ b_data = b_fat + sz_fat * n_fats + sz_dir; /* Data base */ /* Align data base to erase block boundary (for flash memory media) */ n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data; /* Next nearest erase block from current data base */ if (fmt == FS_FAT32) { /* FAT32: Move FAT base */ sz_rsv += n; b_fat += n; } else { /* FAT: Expand FAT size */ sz_fat += n / n_fats; } /* Determine number of clusters and final check of validity of the FAT sub-type */ if (sz_vol < b_data + pau * 16 - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume */ n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau; if (fmt == FS_FAT32) { if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32 */ if (au == 0 && (au = pau / 2) != 0) continue; /* Adjust cluster size and retry */ LEAVE_MKFS(FR_MKFS_ABORTED); } } if (fmt == FS_FAT16) { if (n_clst > MAX_FAT16) { /* Too many clusters for FAT16 */ if (au == 0 && (pau * 2) <= 64) { au = pau * 2; continue; /* Adjust cluster size and retry */ } if ((opt & FM_FAT32)) { fmt = FS_FAT32; continue; /* Switch type to FAT32 and retry */ } if (au == 0 && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ LEAVE_MKFS(FR_MKFS_ABORTED); } if (n_clst <= MAX_FAT12) { /* Too few clusters for FAT16 */ if (au == 0 && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ LEAVE_MKFS(FR_MKFS_ABORTED); } } if (fmt == FS_FAT12 && n_clst > MAX_FAT12) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters for FAT12 */ /* Ok, it is the valid cluster configuration */ break; } while (1); #if FF_USE_TRIM tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1; /* Inform the device the volume area can be erased */ disk_ioctl(pdrv, CTRL_TRIM, tbl); #endif /* Create FAT VBR */ mem_set(buf, 0, ss); mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */ st_word(buf + BPB_BytsPerSec, ss); /* Sector size [byte] */ buf[BPB_SecPerClus] = (BYTE)pau; /* Cluster size [sector] */ st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv); /* Size of reserved area */ buf[BPB_NumFATs] = (BYTE)n_fats; /* Number of FATs */ st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir)); /* Number of root directory entries */ if (sz_vol < 0x10000) { st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */ } else { st_dword(buf + BPB_TotSec32, sz_vol); /* Volume size in 32-bit LBA */ } buf[BPB_Media] = 0xF8; /* Media descriptor byte */ st_word(buf + BPB_SecPerTrk, 63); /* Number of sectors per track (for int13) */ st_word(buf + BPB_NumHeads, 255); /* Number of heads (for int13) */ st_dword(buf + BPB_HiddSec, b_vol); /* Volume offset in the physical drive [sector] */ if (fmt == FS_FAT32) { st_dword(buf + BS_VolID32, GET_FATTIME()); /* VSN */ st_dword(buf + BPB_FATSz32, sz_fat); /* FAT size [sector] */ st_dword(buf + BPB_RootClus32, 2); /* Root directory cluster # (2) */ st_word(buf + BPB_FSInfo32, 1); /* Offset of FSINFO sector (VBR + 1) */ st_word(buf + BPB_BkBootSec32, 6); /* Offset of backup VBR (VBR + 6) */ buf[BS_DrvNum32] = 0x80; /* Drive number (for int13) */ buf[BS_BootSig32] = 0x29; /* Extended boot signature */ mem_cpy(buf + BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ } else { st_dword(buf + BS_VolID, GET_FATTIME()); /* VSN */ st_word(buf + BPB_FATSz16, (WORD)sz_fat); /* FAT size [sector] */ buf[BS_DrvNum] = 0x80; /* Drive number (for int13) */ buf[BS_BootSig] = 0x29; /* Extended boot signature */ mem_cpy(buf + BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ } st_word(buf + BS_55AA, 0xAA55); /* Signature (offset is fixed here regardless of sector size) */ if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it to the VBR sector */ /* Create FSINFO record if needed */ if (fmt == FS_FAT32) { disk_write(pdrv, buf, b_vol + 6, 1); /* Write backup VBR (VBR + 6) */ mem_set(buf, 0, ss); st_dword(buf + FSI_LeadSig, 0x41615252); st_dword(buf + FSI_StrucSig, 0x61417272); st_dword(buf + FSI_Free_Count, n_clst - 1); /* Number of free clusters */ st_dword(buf + FSI_Nxt_Free, 2); /* Last allocated cluster# */ st_word(buf + BS_55AA, 0xAA55); disk_write(pdrv, buf, b_vol + 7, 1); /* Write backup FSINFO (VBR + 7) */ disk_write(pdrv, buf, b_vol + 1, 1); /* Write original FSINFO (VBR + 1) */ } /* Initialize FAT area */ mem_set(buf, 0, (UINT)szb_buf); sect = b_fat; /* FAT start sector */ for (i = 0; i < n_fats; i++) { /* Initialize FATs each */ if (fmt == FS_FAT32) { st_dword(buf + 0, 0xFFFFFFF8); /* Entry 0 */ st_dword(buf + 4, 0xFFFFFFFF); /* Entry 1 */ st_dword(buf + 8, 0x0FFFFFFF); /* Entry 2 (root directory) */ } else { st_dword(buf + 0, (fmt == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8); /* Entry 0 and 1 */ } nsect = sz_fat; /* Number of FAT sectors */ do { /* Fill FAT sectors */ n = (nsect > sz_buf) ? sz_buf : nsect; if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); mem_set(buf, 0, ss); sect += n; nsect -= n; } while (nsect); } /* Initialize root directory (fill with zero) */ nsect = (fmt == FS_FAT32) ? pau : sz_dir; /* Number of root directory sectors */ do { n = (nsect > sz_buf) ? sz_buf : nsect; if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); sect += n; nsect -= n; } while (nsect); } /* Determine system ID in the partition table */ if (FF_FS_EXFAT && fmt == FS_EXFAT) { sys = 0x07; /* HPFS/NTFS/exFAT */ } else { if (fmt == FS_FAT32) { sys = 0x0C; /* FAT32X */ } else { if (sz_vol >= 0x10000) { sys = 0x06; /* FAT12/16 (large) */ } else { sys = (fmt == FS_FAT16) ? 0x04 : 0x01; /* FAT16 : FAT12 */ } } } /* Update partition information */ if (FF_MULTI_PARTITION && part != 0) { /* Created in the existing partition */ /* Update system ID in the partition table */ if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Read the MBR */ buf[MBR_Table + (part - 1) * SZ_PTE + PTE_System] = sys; /* Set system ID */ if (disk_write(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it back to the MBR */ } else { /* Created as a new single partition */ if (!(opt & FM_SFD)) { /* Create partition table if in FDISK format */ mem_set(buf, 0, ss); st_word(buf + BS_55AA, 0xAA55); /* MBR signature */ pte = buf + MBR_Table; /* Create partition table for single partition in the drive */ pte[PTE_Boot] = 0; /* Boot indicator */ pte[PTE_StHead] = 1; /* Start head */ pte[PTE_StSec] = 1; /* Start sector */ pte[PTE_StCyl] = 0; /* Start cylinder */ pte[PTE_System] = sys; /* System type */ n = (b_vol + sz_vol) / (63 * 255); /* (End CHS may be invalid) */ pte[PTE_EdHead] = 254; /* End head */ pte[PTE_EdSec] = (BYTE)(((n >> 2) & 0xC0) | 63); /* End sector */ pte[PTE_EdCyl] = (BYTE)n; /* End cylinder */ st_dword(pte + PTE_StLba, b_vol); /* Start offset in LBA */ st_dword(pte + PTE_SizLba, sz_vol); /* Size in sectors */ if (disk_write(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it to the MBR */ } } if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); LEAVE_MKFS(FR_OK); } #if FF_MULTI_PARTITION /*-----------------------------------------------------------------------*/ /* Create Partition Table on the Physical Drive */ /*-----------------------------------------------------------------------*/ FRESULT f_fdisk ( BYTE pdrv, /* Physical drive number */ const DWORD* szt, /* Pointer to the size table for each partitions */ void* work /* Pointer to the working buffer (null: use heap memory) */ ) { UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl; BYTE s_hd, e_hd, *p, *buf = (BYTE*)work; DSTATUS stat; DWORD sz_disk, sz_part, s_part; FRESULT res; stat = disk_initialize(pdrv); if (stat & STA_NOINIT) return FR_NOT_READY; if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR; buf = (BYTE*)work; #if FF_USE_LFN == 3 if (!buf) buf = ff_memalloc(FF_MAX_SS); /* Use heap memory for working buffer */ #endif if (!buf) return FR_NOT_ENOUGH_CORE; /* Determine the CHS without any consideration of the drive geometry */ for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ; if (n == 256) n--; e_hd = (BYTE)(n - 1); sz_cyl = 63 * n; tot_cyl = sz_disk / sz_cyl; /* Create partition table */ mem_set(buf, 0, FF_MAX_SS); p = buf + MBR_Table; b_cyl = 0; for (i = 0; i < 4; i++, p += SZ_PTE) { p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; /* Number of cylinders */ if (p_cyl == 0) continue; s_part = (DWORD)sz_cyl * b_cyl; sz_part = (DWORD)sz_cyl * p_cyl; if (i == 0) { /* Exclude first track of cylinder 0 */ s_hd = 1; s_part += 63; sz_part -= 63; } else { s_hd = 0; } e_cyl = b_cyl + p_cyl - 1; /* End cylinder */ if (e_cyl >= tot_cyl) LEAVE_MKFS(FR_INVALID_PARAMETER); /* Set partition table */ p[1] = s_hd; /* Start head */ p[2] = (BYTE)(((b_cyl >> 2) & 0xC0) | 1); /* Start sector */ p[3] = (BYTE)b_cyl; /* Start cylinder */ p[4] = 0x07; /* System type (temporary setting) */ p[5] = e_hd; /* End head */ p[6] = (BYTE)(((e_cyl >> 2) & 0xC0) | 63); /* End sector */ p[7] = (BYTE)e_cyl; /* End cylinder */ st_dword(p + 8, s_part); /* Start sector in LBA */ st_dword(p + 12, sz_part); /* Number of sectors */ /* Next partition */ b_cyl += p_cyl; } st_word(p, 0xAA55); /* MBR signature (always at offset 510) */ /* Write it to the MBR */ res = (disk_write(pdrv, buf, 0, 1) == RES_OK && disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR; LEAVE_MKFS(res); } #endif /* FF_MULTI_PARTITION */ #endif /* FF_USE_MKFS && !FF_FS_READONLY */ #if FF_USE_STRFUNC #if FF_USE_LFN && FF_LFN_UNICODE && (FF_STRF_ENCODE < 0 || FF_STRF_ENCODE > 3) #error Wrong FF_STRF_ENCODE setting #endif /*-----------------------------------------------------------------------*/ /* Get a String from the File */ /*-----------------------------------------------------------------------*/ TCHAR* f_gets ( TCHAR* buff, /* Pointer to the string buffer to read */ int len, /* Size of string buffer (items) */ FIL* fp /* Pointer to the file object */ ) { int nc = 0; TCHAR *p = buff; BYTE s[4]; UINT rc; DWORD dc; #if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE <= 2 WCHAR wc; #endif #if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE == 3 UINT ct; #endif #if FF_USE_LFN && FF_LFN_UNICODE /* With code conversion (Unicode API) */ /* Make a room for the character and terminator */ if (FF_LFN_UNICODE == 1) len -= (FF_STRF_ENCODE == 0) ? 1 : 2; if (FF_LFN_UNICODE == 2) len -= (FF_STRF_ENCODE == 0) ? 3 : 4; if (FF_LFN_UNICODE == 3) len -= 1; while (nc < len) { #if FF_STRF_ENCODE == 0 /* Read a character in ANSI/OEM */ f_read(fp, s, 1, &rc); if (rc != 1) break; wc = s[0]; if (dbc_1st((BYTE)wc)) { f_read(fp, s, 1, &rc); if (rc != 1 || !dbc_2nd(s[0])) continue; wc = wc << 8 | s[0]; } dc = ff_oem2uni(wc, CODEPAGE); if (dc == 0) continue; #elif FF_STRF_ENCODE == 1 || FF_STRF_ENCODE == 2 /* Read a character in UTF-16LE/BE */ f_read(fp, s, 2, &rc); if (rc != 2) break; dc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1]; if (IsSurrogateL(dc)) continue; if (IsSurrogateH(dc)) { f_read(fp, s, 2, &rc); if (rc != 2) break; wc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1]; if (!IsSurrogateL(wc)) continue; dc = ((dc & 0x3FF) + 0x40) << 10 | (wc & 0x3FF); } #else /* Read a character in UTF-8 */ f_read(fp, s, 1, &rc); if (rc != 1) break; dc = s[0]; if (dc >= 0x80) { /* Multi-byte character? */ ct = 0; if ((dc & 0xE0) == 0xC0) { dc &= 0x1F; ct = 1; } /* 2-byte? */ if ((dc & 0xF0) == 0xE0) { dc &= 0x0F; ct = 2; } /* 3-byte? */ if ((dc & 0xF8) == 0xF0) { dc &= 0x07; ct = 3; } /* 4-byte? */ if (ct == 0) continue; f_read(fp, s, ct, &rc); /* Get trailing bytes */ if (rc != ct) break; rc = 0; do { /* Merge trailing bytes */ if ((s[rc] & 0xC0) != 0x80) break; dc = dc << 6 | (s[rc] & 0x3F); } while (++rc < ct); if (rc != ct || dc < 0x80 || IsSurrogate(dc) || dc >= 0x110000) continue; /* Wrong encoding? */ } #endif if (FF_USE_STRFUNC == 2 && dc == '\r') continue; /* Strip \r off if needed */ #if FF_LFN_UNICODE == 1 || FF_LFN_UNICODE == 3 /* Output it in UTF-16/32 encoding */ if (FF_LFN_UNICODE == 1 && dc >= 0x10000) { /* Out of BMP at UTF-16? */ *p++ = (TCHAR)(0xD800 | ((dc >> 10) - 0x40)); nc++; /* Make and output high surrogate */ dc = 0xDC00 | (dc & 0x3FF); /* Make low surrogate */ } *p++ = (TCHAR)dc; nc++; if (dc == '\n') break; /* End of line? */ #elif FF_LFN_UNICODE == 2 /* Output it in UTF-8 encoding */ if (dc < 0x80) { /* 1-byte */ *p++ = (TCHAR)dc; nc++; if (dc == '\n') break; /* End of line? */ } else { if (dc < 0x800) { /* 2-byte */ *p++ = (TCHAR)(0xC0 | (dc >> 6 & 0x1F)); *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); nc += 2; } else { if (dc < 0x10000) { /* 3-byte */ *p++ = (TCHAR)(0xE0 | (dc >> 12 & 0x0F)); *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F)); *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); nc += 3; } else { /* 4-byte */ *p++ = (TCHAR)(0xF0 | (dc >> 18 & 0x07)); *p++ = (TCHAR)(0x80 | (dc >> 12 & 0x3F)); *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F)); *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); nc += 4; } } } #endif } #else /* Byte-by-byte without any conversion (ANSI/OEM API) */ len -= 1; /* Make a room for the terminator */ while (nc < len) { f_read(fp, s, 1, &rc); if (rc != 1) break; dc = s[0]; if (FF_USE_STRFUNC == 2 && dc == '\r') continue; *p++ = (TCHAR)dc; nc++; if (dc == '\n') break; } #endif *p = 0; /* Terminate the string */ return nc ? buff : 0; /* When no data read due to EOF or error, return with error. */ } #if !FF_FS_READONLY #include /*-----------------------------------------------------------------------*/ /* Put a Character to the File */ /*-----------------------------------------------------------------------*/ typedef struct { /* Putchar output buffer and work area */ FIL *fp; /* Ptr to the writing file */ int idx, nchr; /* Write index of buf[] (-1:error), number of encoding units written */ #if FF_USE_LFN && FF_LFN_UNICODE == 1 WCHAR hs; #elif FF_USE_LFN && FF_LFN_UNICODE == 2 BYTE bs[4]; UINT wi, ct; #endif BYTE buf[64]; /* Write buffer */ } putbuff; static void putc_bfd ( /* Buffered write with code conversion */ putbuff* pb, TCHAR c ) { UINT n; int i, nc; #if FF_USE_LFN && FF_LFN_UNICODE WCHAR hs, wc; #if FF_LFN_UNICODE == 2 DWORD dc; TCHAR *tp; #endif #endif if (FF_USE_STRFUNC == 2 && c == '\n') { /* LF -> CRLF conversion */ putc_bfd(pb, '\r'); } i = pb->idx; /* Write index of pb->buf[] */ if (i < 0) return; nc = pb->nchr; /* Write unit counter */ #if FF_USE_LFN && FF_LFN_UNICODE #if FF_LFN_UNICODE == 1 /* UTF-16 input */ if (IsSurrogateH(c)) { pb->hs = c; return; } hs = pb->hs; pb->hs = 0; if (hs != 0) { if (!IsSurrogateL(c)) hs = 0; } else { if (IsSurrogateL(c)) return; } wc = c; #elif FF_LFN_UNICODE == 2 /* UTF-8 input */ for (;;) { if (pb->ct == 0) { /* Out of multi-byte sequence? */ pb->bs[pb->wi = 0] = (BYTE)c; /* Save 1st byte */ if ((BYTE)c < 0x80) break; /* 1-byte? */ if (((BYTE)c & 0xE0) == 0xC0) pb->ct = 1; /* 2-byte? */ if (((BYTE)c & 0xF0) == 0xE0) pb->ct = 2; /* 3-byte? */ if (((BYTE)c & 0xF1) == 0xF0) pb->ct = 3; /* 4-byte? */ return; } else { /* In the multi-byte sequence */ if (((BYTE)c & 0xC0) != 0x80) { /* Broken sequence? */ pb->ct = 0; continue; } pb->bs[++pb->wi] = (BYTE)c; /* Save the trailing byte */ if (--pb->ct == 0) break; /* End of multi-byte sequence? */ return; } } tp = (TCHAR*)pb->bs; dc = tchar2uni(&tp); /* UTF-8 ==> UTF-16 */ if (dc == 0xFFFFFFFF) return; wc = (WCHAR)dc; hs = (WCHAR)(dc >> 16); #elif FF_LFN_UNICODE == 3 /* UTF-32 input */ if (IsSurrogate(c) || c >= 0x110000) return; if (c >= 0x10000) { hs = (WCHAR)(0xD800 | ((c >> 10) - 0x40)); /* Make high surrogate */ wc = 0xDC00 | (c & 0x3FF); /* Make low surrogate */ } else { hs = 0; wc = (WCHAR)c; } #endif #if FF_STRF_ENCODE == 1 /* Write a character in UTF-16LE */ if (hs != 0) { st_word(&pb->buf[i], hs); i += 2; nc++; } st_word(&pb->buf[i], wc); i += 2; #elif FF_STRF_ENCODE == 2 /* Write a character in UTF-16BE */ if (hs != 0) { pb->buf[i++] = (BYTE)(hs >> 8); pb->buf[i++] = (BYTE)hs; nc++; } pb->buf[i++] = (BYTE)(wc >> 8); pb->buf[i++] = (BYTE)wc; #elif FF_STRF_ENCODE == 3 /* Write it in UTF-8 */ if (hs != 0) { /* 4-byte */ nc += 3; hs = (hs & 0x3FF) + 0x40; pb->buf[i++] = (BYTE)(0xF0 | hs >> 8); pb->buf[i++] = (BYTE)(0x80 | (hs >> 2 & 0x3F)); pb->buf[i++] = (BYTE)(0x80 | (hs & 3) << 4 | (wc >> 6 & 0x0F)); pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F)); } else { if (wc < 0x80) { /* 1-byte */ pb->buf[i++] = (BYTE)wc; } else { if (wc < 0x800) { /* 2-byte */ nc += 1; pb->buf[i++] = (BYTE)(0xC0 | wc >> 6); } else { /* 3-byte */ nc += 2; pb->buf[i++] = (BYTE)(0xE0 | wc >> 12); pb->buf[i++] = (BYTE)(0x80 | (wc >> 6 & 0x3F)); } pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F)); } } #else /* Write it in ANSI/OEM */ if (hs != 0) return; wc = ff_uni2oem(wc, CODEPAGE); /* UTF-16 ==> ANSI/OEM */ if (wc == 0) return;; if (wc >= 0x100) { pb->buf[i++] = (BYTE)(wc >> 8); nc++; } pb->buf[i++] = (BYTE)wc; #endif #else /* ANSI/OEM input (without re-encode) */ pb->buf[i++] = (BYTE)c; #endif if (i >= (int)(sizeof pb->buf) - 4) { /* Write buffered characters to the file */ f_write(pb->fp, pb->buf, (UINT)i, &n); i = (n == (UINT)i) ? 0 : -1; } pb->idx = i; pb->nchr = nc + 1; } static int putc_flush ( /* Flush left characters in the buffer */ putbuff* pb ) { UINT nw; if ( pb->idx >= 0 /* Flush buffered characters to the file */ && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK && (UINT)pb->idx == nw) return pb->nchr; return EOF; } static void putc_init ( /* Initialize write buffer */ putbuff* pb, FIL* fp ) { mem_set(pb, 0, sizeof (putbuff)); pb->fp = fp; } int f_putc ( TCHAR c, /* A character to be output */ FIL* fp /* Pointer to the file object */ ) { putbuff pb; putc_init(&pb, fp); putc_bfd(&pb, c); /* Put the character */ return putc_flush(&pb); } /*-----------------------------------------------------------------------*/ /* Put a String to the File */ /*-----------------------------------------------------------------------*/ int f_puts ( const TCHAR* str, /* Pointer to the string to be output */ FIL* fp /* Pointer to the file object */ ) { putbuff pb; putc_init(&pb, fp); while (*str) putc_bfd(&pb, *str++); /* Put the string */ return putc_flush(&pb); } /*-----------------------------------------------------------------------*/ /* Put a Formatted String to the File */ /*-----------------------------------------------------------------------*/ int f_printf ( FIL* fp, /* Pointer to the file object */ const TCHAR* fmt, /* Pointer to the format string */ ... /* Optional arguments... */ ) { va_list arp; putbuff pb; BYTE f, r; UINT i, j, w; DWORD v; TCHAR c, d, str[32], *p; putc_init(&pb, fp); va_start(arp, fmt); for (;;) { c = *fmt++; if (c == 0) break; /* End of string */ if (c != '%') { /* Non escape character */ putc_bfd(&pb, c); continue; } w = f = 0; c = *fmt++; if (c == '0') { /* Flag: '0' padding */ f = 1; c = *fmt++; } else { if (c == '-') { /* Flag: left justified */ f = 2; c = *fmt++; } } if (c == '*') { /* Minimum width by argument */ w = va_arg(arp, int); c = *fmt++; } else { while (IsDigit(c)) { /* Minimum width */ w = w * 10 + c - '0'; c = *fmt++; } } if (c == 'l' || c == 'L') { /* Type prefix: Size is long int */ f |= 4; c = *fmt++; } if (c == 0) break; d = c; if (IsLower(d)) d -= 0x20; switch (d) { /* Atgument type is... */ case 'S' : /* String */ p = va_arg(arp, TCHAR*); for (j = 0; p[j]; j++) ; if (!(f & 2)) { /* Right padded */ while (j++ < w) putc_bfd(&pb, ' ') ; } while (*p) putc_bfd(&pb, *p++) ; /* String body */ while (j++ < w) putc_bfd(&pb, ' ') ; /* Left padded */ continue; case 'C' : /* Character */ putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue; case 'B' : /* Unsigned binary */ r = 2; break; case 'O' : /* Unsigned octal */ r = 8; break; case 'D' : /* Signed decimal */ case 'U' : /* Unsigned decimal */ r = 10; break; case 'X' : /* Unsigned hexdecimal */ r = 16; break; default: /* Unknown type (pass-through) */ putc_bfd(&pb, c); continue; } /* Get an argument and put it in numeral */ v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int)); if (d == 'D' && (v & 0x80000000)) { v = 0 - v; f |= 8; } i = 0; do { d = (TCHAR)(v % r); v /= r; if (d > 9) d += (c == 'x') ? 0x27 : 0x07; str[i++] = d + '0'; } while (v && i < sizeof str / sizeof *str); if (f & 8) str[i++] = '-'; j = i; d = (f & 1) ? '0' : ' '; if (!(f & 2)) { while (j++ < w) putc_bfd(&pb, d); /* Right pad */ } do { putc_bfd(&pb, str[--i]); /* Number body */ } while (i); while (j++ < w) putc_bfd(&pb, d); /* Left pad */ } va_end(arp); return putc_flush(&pb); } #endif /* !FF_FS_READONLY */ #endif /* FF_USE_STRFUNC */ #if FF_CODE_PAGE == 0 /*-----------------------------------------------------------------------*/ /* Set Active Codepage for the Path Name */ /*-----------------------------------------------------------------------*/ FRESULT f_setcp ( WORD cp /* Value to be set as active code page */ ) { static const WORD validcp[] = { 437, 720, 737, 771, 775, 850, 852, 857, 860, 861, 862, 863, 864, 865, 866, 869, 932, 936, 949, 950, 0}; static const BYTE* const tables[] = {Ct437, Ct720, Ct737, Ct771, Ct775, Ct850, Ct852, Ct857, Ct860, Ct861, Ct862, Ct863, Ct864, Ct865, Ct866, Ct869, Dc932, Dc936, Dc949, Dc950, 0}; UINT i; for (i = 0; validcp[i] != 0 && validcp[i] != cp; i++) ; /* Find the code page */ if (validcp[i] != cp) return FR_INVALID_PARAMETER; /* Not found? */ CodePage = cp; if (cp >= 900) { /* DBCS */ ExCvt = 0; DbcTbl = tables[i]; } else { /* SBCS */ ExCvt = tables[i]; DbcTbl = 0; } return FR_OK; } #endif /* FF_CODE_PAGE == 0 */ ================================================ FILE: Huawei_LiteOS/components/fs/fatfs/ff13b/source/ff.h ================================================ /*----------------------------------------------------------------------------/ / FatFs - Generic FAT Filesystem module R0.13b / /-----------------------------------------------------------------------------/ / / Copyright (C) 2018, ChaN, all right reserved. / / FatFs module is an open source software. Redistribution and use of FatFs in / source and binary forms, with or without modification, are permitted provided / that the following condition is met: / 1. Redistributions of source code must retain the above copyright notice, / this condition and the following disclaimer. / / This software is provided by the copyright holder and contributors "AS IS" / and any warranties related to this software are DISCLAIMED. / The copyright owner or contributors be NOT LIABLE for any damages caused / by use of this software. / /----------------------------------------------------------------------------*/ #ifndef FF_DEFINED #define FF_DEFINED 63463 /* Revision ID */ #ifdef __cplusplus extern "C" { #endif #include "integer.h" /* Basic integer types */ #include "ffconf.h" /* FatFs configuration options */ #if FF_DEFINED != FFCONF_DEF #error Wrong configuration file (ffconf.h). #endif /* Definitions of volume management */ #if FF_MULTI_PARTITION /* Multiple partition configuration */ typedef struct { BYTE pd; /* Physical drive number */ BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */ } PARTITION; extern PARTITION VolToPart[]; /* Volume - Partition resolution table */ #endif #if FF_STR_VOLUME_ID #ifndef FF_VOLUME_STRS extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */ #endif #endif /* Type of path name strings on FatFs API */ #ifndef _INC_TCHAR #define _INC_TCHAR #if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */ typedef WCHAR TCHAR; #define _T(x) L ## x #define _TEXT(x) L ## x #elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */ typedef char TCHAR; #define _T(x) u8 ## x #define _TEXT(x) u8 ## x #elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */ typedef DWORD TCHAR; #define _T(x) U ## x #define _TEXT(x) U ## x #elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3) #error Wrong FF_LFN_UNICODE setting #else /* ANSI/OEM code in SBCS/DBCS */ typedef char TCHAR; #define _T(x) x #define _TEXT(x) x #endif #endif /* Type of file size variables */ #if FF_FS_EXFAT typedef QWORD FSIZE_t; #else typedef DWORD FSIZE_t; #endif /* Filesystem object structure (FATFS) */ typedef struct { BYTE fs_type; /* Filesystem type (0:N/A) */ BYTE pdrv; /* Physical drive number */ BYTE n_fats; /* Number of FATs (1 or 2) */ BYTE wflag; /* win[] flag (b0:dirty) */ BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */ WORD id; /* Volume mount ID */ WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ WORD csize; /* Cluster size [sectors] */ #if FF_MAX_SS != FF_MIN_SS WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */ #endif #if FF_USE_LFN WCHAR* lfnbuf; /* LFN working buffer */ #endif #if FF_FS_EXFAT BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */ #endif #if FF_FS_REENTRANT FF_SYNC_t sobj; /* Identifier of sync object */ #endif #if !FF_FS_READONLY DWORD last_clst; /* Last allocated cluster */ DWORD free_clst; /* Number of free clusters */ #endif #if FF_FS_RPATH DWORD cdir; /* Current directory start cluster (0:root) */ #if FF_FS_EXFAT DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */ DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */ DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */ #endif #endif DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */ DWORD fsize; /* Size of an FAT [sectors] */ DWORD volbase; /* Volume base sector */ DWORD fatbase; /* FAT base sector */ DWORD dirbase; /* Root directory base sector/cluster */ DWORD database; /* Data base sector */ DWORD winsect; /* Current sector appearing in the win[] */ BYTE win[FF_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */ } FATFS; /* Object ID and allocation information (FFOBJID) */ typedef struct { FATFS* fs; /* Pointer to the hosting volume of this object */ WORD id; /* Hosting volume mount ID */ BYTE attr; /* Object attribute */ BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:flagmented in this session, b2:sub-directory stretched) */ DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */ FSIZE_t objsize; /* Object size (valid when sclust != 0) */ #if FF_FS_EXFAT DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */ DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */ DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */ DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */ DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */ #endif #if FF_FS_LOCK UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */ #endif } FFOBJID; /* File object structure (FIL) */ typedef struct { FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */ BYTE flag; /* File status flags */ BYTE err; /* Abort flag (error code) */ FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */ DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */ DWORD sect; /* Sector number appearing in buf[] (0:invalid) */ #if !FF_FS_READONLY DWORD dir_sect; /* Sector number containing the directory entry (not used at exFAT) */ BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */ #endif #if FF_USE_FASTSEEK DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */ #endif #if !FF_FS_TINY BYTE buf[FF_MAX_SS]; /* File private data read/write window */ #endif } FIL; /* Directory object structure (DIR) */ typedef struct { FFOBJID obj; /* Object identifier */ DWORD dptr; /* Current read/write offset */ DWORD clust; /* Current cluster */ DWORD sect; /* Current sector (0:Read operation has terminated) */ BYTE* dir; /* Pointer to the directory item in the win[] */ BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */ #if FF_USE_LFN DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */ #endif #if FF_USE_FIND const TCHAR* pat; /* Pointer to the name matching pattern */ #endif } DIR; /* File information structure (FILINFO) */ typedef struct { FSIZE_t fsize; /* File size */ WORD fdate; /* Modified date */ WORD ftime; /* Modified time */ BYTE fattrib; /* File attribute */ #if FF_USE_LFN TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */ TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */ #else TCHAR fname[12 + 1]; /* File name */ #endif } FILINFO; /* File function return code (FRESULT) */ typedef enum { FR_OK = 0, /* (0) Succeeded */ FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */ FR_INT_ERR, /* (2) Assertion failed */ FR_NOT_READY, /* (3) The physical drive cannot work */ FR_NO_FILE, /* (4) Could not find the file */ FR_NO_PATH, /* (5) Could not find the path */ FR_INVALID_NAME, /* (6) The path name format is invalid */ FR_DENIED, /* (7) Access denied due to prohibited access or directory full */ FR_EXIST, /* (8) Access denied due to prohibited access */ FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */ FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */ FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */ FR_NOT_ENABLED, /* (12) The volume has no work area */ FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */ FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */ FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */ FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */ FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */ FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */ FR_INVALID_PARAMETER /* (19) Given parameter is invalid */ } FRESULT; /*--------------------------------------------------------------*/ /* FatFs module application interface */ FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */ FRESULT f_close (FIL* fp); /* Close an open file object */ FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */ FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */ FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */ FRESULT f_truncate (FIL* fp); /* Truncate the file */ FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */ FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */ FRESULT f_closedir (DIR* dp); /* Close an open directory */ FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */ FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */ FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */ FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */ FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */ FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */ FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */ FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */ FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */ FRESULT f_chdir (const TCHAR* path); /* Change current directory */ FRESULT f_chdrive (const TCHAR* path); /* Change current drive */ FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */ FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */ FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */ FRESULT f_setlabel (const TCHAR* label); /* Set volume label */ FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */ FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt); /* Allocate a contiguous block to the file */ FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */ FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len); /* Create a FAT volume */ FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work); /* Divide a physical drive into some partitions */ FRESULT f_setcp (WORD cp); /* Set current code page */ int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */ int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ #define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize)) #define f_error(fp) ((fp)->err) #define f_tell(fp) ((fp)->fptr) #define f_size(fp) ((fp)->obj.objsize) #define f_rewind(fp) f_lseek((fp), 0) #define f_rewinddir(dp) f_readdir((dp), 0) #define f_rmdir(path) f_unlink(path) #define f_unmount(path) f_mount(0, path, 0) #ifndef EOF #define EOF (-1) #endif /*--------------------------------------------------------------*/ /* Additional user defined functions */ /* RTC function */ #if !FF_FS_READONLY && !FF_FS_NORTC DWORD get_fattime (void); #endif /* LFN support functions */ #if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */ WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */ WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */ DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */ #endif #if FF_USE_LFN == 3 /* Dynamic memory allocation */ void* ff_memalloc (UINT msize); /* Allocate memory block */ void ff_memfree (void* mblock); /* Free memory block */ #endif /* Sync functions */ #if FF_FS_REENTRANT int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */ int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */ void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */ int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */ #endif /*--------------------------------------------------------------*/ /* Flags and offset address */ /* File access mode and open method flags (3rd argument of f_open) */ #define FA_READ 0x01 #define FA_WRITE 0x02 #define FA_OPEN_EXISTING 0x00 #define FA_CREATE_NEW 0x04 #define FA_CREATE_ALWAYS 0x08 #define FA_OPEN_ALWAYS 0x10 #define FA_OPEN_APPEND 0x30 /* Fast seek controls (2nd argument of f_lseek) */ #define CREATE_LINKMAP ((FSIZE_t)0 - 1) /* Format options (2nd argument of f_mkfs) */ #define FM_FAT 0x01 #define FM_FAT32 0x02 #define FM_EXFAT 0x04 #define FM_ANY 0x07 #define FM_SFD 0x08 /* Filesystem type (FATFS.fs_type) */ #define FS_FAT12 1 #define FS_FAT16 2 #define FS_FAT32 3 #define FS_EXFAT 4 /* File attribute bits for directory entry (FILINFO.fattrib) */ #define AM_RDO 0x01 /* Read only */ #define AM_HID 0x02 /* Hidden */ #define AM_SYS 0x04 /* System */ #define AM_DIR 0x10 /* Directory */ #define AM_ARC 0x20 /* Archive */ #ifdef __cplusplus } #endif #endif /* FF_DEFINED */ ================================================ FILE: Huawei_LiteOS/components/fs/fatfs/ff13b/source/ffsystem.c ================================================ /*------------------------------------------------------------------------*/ /* Sample Code of OS Dependent Functions for FatFs */ /* (C)ChaN, 2017 */ /*------------------------------------------------------------------------*/ #include "ff.h" #if FF_USE_LFN == 3 /* Dynamic memory allocation */ /*------------------------------------------------------------------------*/ /* Allocate a memory block */ /*------------------------------------------------------------------------*/ void* ff_memalloc ( /* Returns pointer to the allocated memory block (null on not enough core) */ UINT msize /* Number of bytes to allocate */ ) { return malloc(msize); /* Allocate a new memory block with POSIX API */ } /*------------------------------------------------------------------------*/ /* Free a memory block */ /*------------------------------------------------------------------------*/ void ff_memfree ( void* mblock /* Pointer to the memory block to free (nothing to do for null) */ ) { free(mblock); /* Free the memory block with POSIX API */ } #endif #if FF_FS_REENTRANT /* Mutal exclusion */ /*------------------------------------------------------------------------*/ /* Create a Synchronization Object */ /*------------------------------------------------------------------------*/ /* This function is called in f_mount() function to create a new / synchronization object for the volume, such as semaphore and mutex. / When a 0 is returned, the f_mount() function fails with FR_INT_ERR. */ //const osMutexDef_t Mutex[FF_VOLUMES]; /* CMSIS-RTOS */ int ff_cre_syncobj ( /* 1:Function succeeded, 0:Could not create the sync object */ BYTE vol, /* Corresponding volume (logical drive number) */ FF_SYNC_t* sobj /* Pointer to return the created sync object */ ) { /* Win32 */ *sobj = CreateMutex(NULL, FALSE, NULL); return (int)(*sobj != INVALID_HANDLE_VALUE); /* uITRON */ // T_CSEM csem = {TA_TPRI,1,1}; // *sobj = acre_sem(&csem); // return (int)(*sobj > 0); /* uC/OS-II */ // OS_ERR err; // *sobj = OSMutexCreate(0, &err); // return (int)(err == OS_NO_ERR); /* FreeRTOS */ // *sobj = xSemaphoreCreateMutex(); // return (int)(*sobj != NULL); /* CMSIS-RTOS */ // *sobj = osMutexCreate(Mutex + vol); // return (int)(*sobj != NULL); } /*------------------------------------------------------------------------*/ /* Delete a Synchronization Object */ /*------------------------------------------------------------------------*/ /* This function is called in f_mount() function to delete a synchronization / object that created with ff_cre_syncobj() function. When a 0 is returned, / the f_mount() function fails with FR_INT_ERR. */ int ff_del_syncobj ( /* 1:Function succeeded, 0:Could not delete due to an error */ FF_SYNC_t sobj /* Sync object tied to the logical drive to be deleted */ ) { /* Win32 */ return (int)CloseHandle(sobj); /* uITRON */ // return (int)(del_sem(sobj) == E_OK); /* uC/OS-II */ // OS_ERR err; // OSMutexDel(sobj, OS_DEL_ALWAYS, &err); // return (int)(err == OS_NO_ERR); /* FreeRTOS */ // vSemaphoreDelete(sobj); // return 1; /* CMSIS-RTOS */ // return (int)(osMutexDelete(sobj) == osOK); } /*------------------------------------------------------------------------*/ /* Request Grant to Access the Volume */ /*------------------------------------------------------------------------*/ /* This function is called on entering file functions to lock the volume. / When a 0 is returned, the file function fails with FR_TIMEOUT. */ int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a grant */ FF_SYNC_t sobj /* Sync object to wait */ ) { /* Win32 */ return (int)(WaitForSingleObject(sobj, FF_FS_TIMEOUT) == WAIT_OBJECT_0); /* uITRON */ // return (int)(wai_sem(sobj) == E_OK); /* uC/OS-II */ // OS_ERR err; // OSMutexPend(sobj, FF_FS_TIMEOUT, &err)); // return (int)(err == OS_NO_ERR); /* FreeRTOS */ // return (int)(xSemaphoreTake(sobj, FF_FS_TIMEOUT) == pdTRUE); /* CMSIS-RTOS */ // return (int)(osMutexWait(sobj, FF_FS_TIMEOUT) == osOK); } /*------------------------------------------------------------------------*/ /* Release Grant to Access the Volume */ /*------------------------------------------------------------------------*/ /* This function is called on leaving file functions to unlock the volume. */ void ff_rel_grant ( FF_SYNC_t sobj /* Sync object to be signaled */ ) { /* Win32 */ ReleaseMutex(sobj); /* uITRON */ // sig_sem(sobj); /* uC/OS-II */ // OSMutexPost(sobj); /* FreeRTOS */ // xSemaphoreGive(sobj); /* CMSIS-RTOS */ // osMutexRelease(sobj); } #endif ================================================ FILE: Huawei_LiteOS/components/fs/fatfs/ff13b/source/ffunicode.c ================================================ /*------------------------------------------------------------------------*/ /* Unicode handling functions for FatFs R0.13b */ /*------------------------------------------------------------------------*/ /* This module will occupy a huge memory in the .const section when the / / FatFs is configured for LFN with DBCS. If the system has any Unicode / / utilitiy for the code conversion, this module should be modified to use / / that function to avoid silly memory consumption. / /-------------------------------------------------------------------------*/ /* / Copyright (C) 2018, ChaN, all right reserved. / / FatFs module is an open source software. Redistribution and use of FatFs in / source and binary forms, with or without modification, are permitted provided / that the following condition is met: / / 1. Redistributions of source code must retain the above copyright notice, / this condition and the following disclaimer. / / This software is provided by the copyright holder and contributors "AS IS" / and any warranties related to this software are DISCLAIMED. / The copyright owner or contributors be NOT LIABLE for any damages caused / by use of this software. */ #include "ff.h" #if FF_USE_LFN /* This module is blanked when non-LFN configuration */ #if FF_DEFINED != 63463 /* Revision ID */ #error Wrong include file (ff.h). #endif #define MERGE2(a, b) a ## b #define CVTBL(tbl, cp) MERGE2(tbl, cp) /*------------------------------------------------------------------------*/ /* Code Conversion Tables */ /*------------------------------------------------------------------------*/ #if FF_CODE_PAGE == 932 || FF_CODE_PAGE == 0 /* Japanese */ static const WCHAR uni2oem932[] = { /* Unicode --> Shift_JIS pairs */ 0x00A7, 0x8198, 0x00A8, 0x814E, 0x00B0, 0x818B, 0x00B1, 0x817D, 0x00B4, 0x814C, 0x00B6, 0x81F7, 0x00D7, 0x817E, 0x00F7, 0x8180, 0x0391, 0x839F, 0x0392, 0x83A0, 0x0393, 0x83A1, 0x0394, 0x83A2, 0x0395, 0x83A3, 0x0396, 0x83A4, 0x0397, 0x83A5, 0x0398, 0x83A6, 0x0399, 0x83A7, 0x039A, 0x83A8, 0x039B, 0x83A9, 0x039C, 0x83AA, 0x039D, 0x83AB, 0x039E, 0x83AC, 0x039F, 0x83AD, 0x03A0, 0x83AE, 0x03A1, 0x83AF, 0x03A3, 0x83B0, 0x03A4, 0x83B1, 0x03A5, 0x83B2, 0x03A6, 0x83B3, 0x03A7, 0x83B4, 0x03A8, 0x83B5, 0x03A9, 0x83B6, 0x03B1, 0x83BF, 0x03B2, 0x83C0, 0x03B3, 0x83C1, 0x03B4, 0x83C2, 0x03B5, 0x83C3, 0x03B6, 0x83C4, 0x03B7, 0x83C5, 0x03B8, 0x83C6, 0x03B9, 0x83C7, 0x03BA, 0x83C8, 0x03BB, 0x83C9, 0x03BC, 0x83CA, 0x03BD, 0x83CB, 0x03BE, 0x83CC, 0x03BF, 0x83CD, 0x03C0, 0x83CE, 0x03C1, 0x83CF, 0x03C3, 0x83D0, 0x03C4, 0x83D1, 0x03C5, 0x83D2, 0x03C6, 0x83D3, 0x03C7, 0x83D4, 0x03C8, 0x83D5, 0x03C9, 0x83D6, 0x0401, 0x8446, 0x0410, 0x8440, 0x0411, 0x8441, 0x0412, 0x8442, 0x0413, 0x8443, 0x0414, 0x8444, 0x0415, 0x8445, 0x0416, 0x8447, 0x0417, 0x8448, 0x0418, 0x8449, 0x0419, 0x844A, 0x041A, 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0xE9B2, 0x9B4F, 0xE9B0, 0x9B51, 0xE9B3, 0x9B54, 0x9682, 0x9B58, 0xE9B4, 0x9B5A, 0x8B9B, 0x9B6F, 0x9844, 0x9B72, 0xFC42, 0x9B74, 0xE9B5, 0x9B75, 0xFC41, 0x9B83, 0xE9B7, 0x9B8E, 0x88BC, 0x9B8F, 0xFC43, 0x9B91, 0xE9B8, 0x9B92, 0x95A9, 0x9B93, 0xE9B6, 0x9B96, 0xE9B9, 0x9B97, 0xE9BA, 0x9B9F, 0xE9BB, 0x9BA0, 0xE9BC, 0x9BA8, 0xE9BD, 0x9BAA, 0x968E, 0x9BAB, 0x8E4C, 0x9BAD, 0x8DF8, 0x9BAE, 0x914E, 0x9BB1, 0xFC44, 0x9BB4, 0xE9BE, 0x9BB9, 0xE9C1, 0x9BBB, 0xFC45, 0x9BC0, 0xE9BF, 0x9BC6, 0xE9C2, 0x9BC9, 0x8CEF, 0x9BCA, 0xE9C0, 0x9BCF, 0xE9C3, 0x9BD1, 0xE9C4, 0x9BD2, 0xE9C5, 0x9BD4, 0xE9C9, 0x9BD6, 0x8E49, 0x9BDB, 0x91E2, 0x9BE1, 0xE9CA, 0x9BE2, 0xE9C7, 0x9BE3, 0xE9C6, 0x9BE4, 0xE9C8, 0x9BE8, 0x8C7E, 0x9BF0, 0xE9CE, 0x9BF1, 0xE9CD, 0x9BF2, 0xE9CC, 0x9BF5, 0x88B1, 0x9C00, 0xFC46, 0x9C04, 0xE9D8, 0x9C06, 0xE9D4, 0x9C08, 0xE9D5, 0x9C09, 0xE9D1, 0x9C0A, 0xE9D7, 0x9C0C, 0xE9D3, 0x9C0D, 0x8A82, 0x9C10, 0x986B, 0x9C12, 0xE9D6, 0x9C13, 0xE9D2, 0x9C14, 0xE9D0, 0x9C15, 0xE9CF, 0x9C1B, 0xE9DA, 0x9C21, 0xE9DD, 0x9C24, 0xE9DC, 0x9C25, 0xE9DB, 0x9C2D, 0x9568, 0x9C2E, 0xE9D9, 0x9C2F, 0x88F1, 0x9C30, 0xE9DE, 0x9C32, 0xE9E0, 0x9C39, 0x8A8F, 0x9C3A, 0xE9CB, 0x9C3B, 0x8956, 0x9C3E, 0xE9E2, 0x9C46, 0xE9E1, 0x9C47, 0xE9DF, 0x9C48, 0x924C, 0x9C52, 0x9690, 0x9C57, 0x97D8, 0x9C5A, 0xE9E3, 0x9C60, 0xE9E4, 0x9C67, 0xE9E5, 0x9C76, 0xE9E6, 0x9C78, 0xE9E7, 0x9CE5, 0x92B9, 0x9CE7, 0xE9E8, 0x9CE9, 0x94B5, 0x9CEB, 0xE9ED, 0x9CEC, 0xE9E9, 0x9CF0, 0xE9EA, 0x9CF3, 0x9650, 0x9CF4, 0x96C2, 0x9CF6, 0x93CE, 0x9D03, 0xE9EE, 0x9D06, 0xE9EF, 0x9D07, 0x93BC, 0x9D08, 0xE9EC, 0x9D09, 0xE9EB, 0x9D0E, 0x89A8, 0x9D12, 0xE9F7, 0x9D15, 0xE9F6, 0x9D1B, 0x8995, 0x9D1F, 0xE9F4, 0x9D23, 0xE9F3, 0x9D26, 0xE9F1, 0x9D28, 0x8A9B, 0x9D2A, 0xE9F0, 0x9D2B, 0x8EB0, 0x9D2C, 0x89A7, 0x9D3B, 0x8D83, 0x9D3E, 0xE9FA, 0x9D3F, 0xE9F9, 0x9D41, 0xE9F8, 0x9D44, 0xE9F5, 0x9D46, 0xE9FB, 0x9D48, 0xE9FC, 0x9D50, 0xEA44, 0x9D51, 0xEA43, 0x9D59, 0xEA45, 0x9D5C, 0x894C, 0x9D5D, 0xEA40, 0x9D5E, 0xEA41, 0x9D60, 0x8D94, 0x9D61, 0x96B7, 0x9D64, 0xEA42, 0x9D6B, 0xFC48, 0x9D6C, 0x9651, 0x9D6F, 0xEA4A, 0x9D70, 0xFC47, 0x9D72, 0xEA46, 0x9D7A, 0xEA4B, 0x9D87, 0xEA48, 0x9D89, 0xEA47, 0x9D8F, 0x8C7B, 0x9D9A, 0xEA4C, 0x9DA4, 0xEA4D, 0x9DA9, 0xEA4E, 0x9DAB, 0xEA49, 0x9DAF, 0xE9F2, 0x9DB2, 0xEA4F, 0x9DB4, 0x92DF, 0x9DB8, 0xEA53, 0x9DBA, 0xEA54, 0x9DBB, 0xEA52, 0x9DC1, 0xEA51, 0x9DC2, 0xEA57, 0x9DC4, 0xEA50, 0x9DC6, 0xEA55, 0x9DCF, 0xEA56, 0x9DD3, 0xEA59, 0x9DD9, 0xEA58, 0x9DE6, 0xEA5B, 0x9DED, 0xEA5C, 0x9DEF, 0xEA5D, 0x9DF2, 0x9868, 0x9DF8, 0xEA5A, 0x9DF9, 0x91E9, 0x9DFA, 0x8DEB, 0x9DFD, 0xEA5E, 0x9E19, 0xFC4A, 0x9E1A, 0xEA5F, 0x9E1B, 0xEA60, 0x9E1E, 0xEA61, 0x9E75, 0xEA62, 0x9E78, 0x8CB2, 0x9E79, 0xEA63, 0x9E7D, 0xEA64, 0x9E7F, 0x8EAD, 0x9E81, 0xEA65, 0x9E88, 0xEA66, 0x9E8B, 0xEA67, 0x9E8C, 0xEA68, 0x9E91, 0xEA6B, 0x9E92, 0xEA69, 0x9E93, 0x985B, 0x9E95, 0xEA6A, 0x9E97, 0x97ED, 0x9E9D, 0xEA6C, 0x9E9F, 0x97D9, 0x9EA5, 0xEA6D, 0x9EA6, 0x949E, 0x9EA9, 0xEA6E, 0x9EAA, 0xEA70, 0x9EAD, 0xEA71, 0x9EB8, 0xEA6F, 0x9EB9, 0x8D8D, 0x9EBA, 0x96CB, 0x9EBB, 0x9683, 0x9EBC, 0x9BF5, 0x9EBE, 0x9F80, 0x9EBF, 0x969B, 0x9EC4, 0x89A9, 0x9ECC, 0xEA73, 0x9ECD, 0x8B6F, 0x9ECE, 0xEA74, 0x9ECF, 0xEA75, 0x9ED0, 0xEA76, 0x9ED1, 0xFC4B, 0x9ED2, 0x8D95, 0x9ED4, 0xEA77, 0x9ED8, 0xE0D2, 0x9ED9, 0x96D9, 0x9EDB, 0x91E1, 0x9EDC, 0xEA78, 0x9EDD, 0xEA7A, 0x9EDE, 0xEA79, 0x9EE0, 0xEA7B, 0x9EE5, 0xEA7C, 0x9EE8, 0xEA7D, 0x9EEF, 0xEA7E, 0x9EF4, 0xEA80, 0x9EF6, 0xEA81, 0x9EF7, 0xEA82, 0x9EF9, 0xEA83, 0x9EFB, 0xEA84, 0x9EFC, 0xEA85, 0x9EFD, 0xEA86, 0x9F07, 0xEA87, 0x9F08, 0xEA88, 0x9F0E, 0x9343, 0x9F13, 0x8CDB, 0x9F15, 0xEA8A, 0x9F20, 0x916C, 0x9F21, 0xEA8B, 0x9F2C, 0xEA8C, 0x9F3B, 0x9540, 0x9F3E, 0xEA8D, 0x9F4A, 0xEA8E, 0x9F4B, 0xE256, 0x9F4E, 0xE6D8, 0x9F4F, 0xE8EB, 0x9F52, 0xEA8F, 0x9F54, 0xEA90, 0x9F5F, 0xEA92, 0x9F60, 0xEA93, 0x9F61, 0xEA94, 0x9F62, 0x97EE, 0x9F63, 0xEA91, 0x9F66, 0xEA95, 0x9F67, 0xEA96, 0x9F6A, 0xEA98, 0x9F6C, 0xEA97, 0x9F72, 0xEA9A, 0x9F76, 0xEA9B, 0x9F77, 0xEA99, 0x9F8D, 0x97B4, 0x9F95, 0xEA9C, 0x9F9C, 0xEA9D, 0x9F9D, 0xE273, 0x9FA0, 0xEA9E, 0xF929, 0xFAE0, 0xF9DC, 0xFBE9, 0xFA0E, 0xFA90, 0xFA0F, 0xFA9B, 0xFA10, 0xFA9C, 0xFA11, 0xFAB1, 0xFA12, 0xFAD8, 0xFA13, 0xFAE8, 0xFA14, 0xFAEA, 0xFA15, 0xFB58, 0xFA16, 0xFB5E, 0xFA17, 0xFB75, 0xFA18, 0xFB7D, 0xFA19, 0xFB7E, 0xFA1A, 0xFB80, 0xFA1B, 0xFB82, 0xFA1C, 0xFB86, 0xFA1D, 0xFB89, 0xFA1E, 0xFB92, 0xFA1F, 0xFB9D, 0xFA20, 0xFB9F, 0xFA21, 0xFBA0, 0xFA22, 0xFBA9, 0xFA23, 0xFBB1, 0xFA24, 0xFBB3, 0xFA25, 0xFBB4, 0xFA26, 0xFBB7, 0xFA27, 0xFBD3, 0xFA28, 0xFBDA, 0xFA29, 0xFBEA, 0xFA2A, 0xFBF6, 0xFA2B, 0xFBF7, 0xFA2C, 0xFBF9, 0xFA2D, 0xFC49, 0xFF01, 0x8149, 0xFF02, 0xFA57, 0xFF03, 0x8194, 0xFF04, 0x8190, 0xFF05, 0x8193, 0xFF06, 0x8195, 0xFF07, 0xFA56, 0xFF08, 0x8169, 0xFF09, 0x816A, 0xFF0A, 0x8196, 0xFF0B, 0x817B, 0xFF0C, 0x8143, 0xFF0D, 0x817C, 0xFF0E, 0x8144, 0xFF0F, 0x815E, 0xFF10, 0x824F, 0xFF11, 0x8250, 0xFF12, 0x8251, 0xFF13, 0x8252, 0xFF14, 0x8253, 0xFF15, 0x8254, 0xFF16, 0x8255, 0xFF17, 0x8256, 0xFF18, 0x8257, 0xFF19, 0x8258, 0xFF1A, 0x8146, 0xFF1B, 0x8147, 0xFF1C, 0x8183, 0xFF1D, 0x8181, 0xFF1E, 0x8184, 0xFF1F, 0x8148, 0xFF20, 0x8197, 0xFF21, 0x8260, 0xFF22, 0x8261, 0xFF23, 0x8262, 0xFF24, 0x8263, 0xFF25, 0x8264, 0xFF26, 0x8265, 0xFF27, 0x8266, 0xFF28, 0x8267, 0xFF29, 0x8268, 0xFF2A, 0x8269, 0xFF2B, 0x826A, 0xFF2C, 0x826B, 0xFF2D, 0x826C, 0xFF2E, 0x826D, 0xFF2F, 0x826E, 0xFF30, 0x826F, 0xFF31, 0x8270, 0xFF32, 0x8271, 0xFF33, 0x8272, 0xFF34, 0x8273, 0xFF35, 0x8274, 0xFF36, 0x8275, 0xFF37, 0x8276, 0xFF38, 0x8277, 0xFF39, 0x8278, 0xFF3A, 0x8279, 0xFF3B, 0x816D, 0xFF3C, 0x815F, 0xFF3D, 0x816E, 0xFF3E, 0x814F, 0xFF3F, 0x8151, 0xFF40, 0x814D, 0xFF41, 0x8281, 0xFF42, 0x8282, 0xFF43, 0x8283, 0xFF44, 0x8284, 0xFF45, 0x8285, 0xFF46, 0x8286, 0xFF47, 0x8287, 0xFF48, 0x8288, 0xFF49, 0x8289, 0xFF4A, 0x828A, 0xFF4B, 0x828B, 0xFF4C, 0x828C, 0xFF4D, 0x828D, 0xFF4E, 0x828E, 0xFF4F, 0x828F, 0xFF50, 0x8290, 0xFF51, 0x8291, 0xFF52, 0x8292, 0xFF53, 0x8293, 0xFF54, 0x8294, 0xFF55, 0x8295, 0xFF56, 0x8296, 0xFF57, 0x8297, 0xFF58, 0x8298, 0xFF59, 0x8299, 0xFF5A, 0x829A, 0xFF5B, 0x816F, 0xFF5C, 0x8162, 0xFF5D, 0x8170, 0xFF5E, 0x8160, 0xFF61, 0x00A1, 0xFF62, 0x00A2, 0xFF63, 0x00A3, 0xFF64, 0x00A4, 0xFF65, 0x00A5, 0xFF66, 0x00A6, 0xFF67, 0x00A7, 0xFF68, 0x00A8, 0xFF69, 0x00A9, 0xFF6A, 0x00AA, 0xFF6B, 0x00AB, 0xFF6C, 0x00AC, 0xFF6D, 0x00AD, 0xFF6E, 0x00AE, 0xFF6F, 0x00AF, 0xFF70, 0x00B0, 0xFF71, 0x00B1, 0xFF72, 0x00B2, 0xFF73, 0x00B3, 0xFF74, 0x00B4, 0xFF75, 0x00B5, 0xFF76, 0x00B6, 0xFF77, 0x00B7, 0xFF78, 0x00B8, 0xFF79, 0x00B9, 0xFF7A, 0x00BA, 0xFF7B, 0x00BB, 0xFF7C, 0x00BC, 0xFF7D, 0x00BD, 0xFF7E, 0x00BE, 0xFF7F, 0x00BF, 0xFF80, 0x00C0, 0xFF81, 0x00C1, 0xFF82, 0x00C2, 0xFF83, 0x00C3, 0xFF84, 0x00C4, 0xFF85, 0x00C5, 0xFF86, 0x00C6, 0xFF87, 0x00C7, 0xFF88, 0x00C8, 0xFF89, 0x00C9, 0xFF8A, 0x00CA, 0xFF8B, 0x00CB, 0xFF8C, 0x00CC, 0xFF8D, 0x00CD, 0xFF8E, 0x00CE, 0xFF8F, 0x00CF, 0xFF90, 0x00D0, 0xFF91, 0x00D1, 0xFF92, 0x00D2, 0xFF93, 0x00D3, 0xFF94, 0x00D4, 0xFF95, 0x00D5, 0xFF96, 0x00D6, 0xFF97, 0x00D7, 0xFF98, 0x00D8, 0xFF99, 0x00D9, 0xFF9A, 0x00DA, 0xFF9B, 0x00DB, 0xFF9C, 0x00DC, 0xFF9D, 0x00DD, 0xFF9E, 0x00DE, 0xFF9F, 0x00DF, 0xFFE0, 0x8191, 0xFFE1, 0x8192, 0xFFE2, 0x81CA, 0xFFE3, 0x8150, 0xFFE4, 0xFA55, 0xFFE5, 0x818F, 0, 0 }; static const WCHAR oem2uni932[] = { /* Shift_JIS --> Unicode pairs */ 0x00A1, 0xFF61, 0x00A2, 0xFF62, 0x00A3, 0xFF63, 0x00A4, 0xFF64, 0x00A5, 0xFF65, 0x00A6, 0xFF66, 0x00A7, 0xFF67, 0x00A8, 0xFF68, 0x00A9, 0xFF69, 0x00AA, 0xFF6A, 0x00AB, 0xFF6B, 0x00AC, 0xFF6C, 0x00AD, 0xFF6D, 0x00AE, 0xFF6E, 0x00AF, 0xFF6F, 0x00B0, 0xFF70, 0x00B1, 0xFF71, 0x00B2, 0xFF72, 0x00B3, 0xFF73, 0x00B4, 0xFF74, 0x00B5, 0xFF75, 0x00B6, 0xFF76, 0x00B7, 0xFF77, 0x00B8, 0xFF78, 0x00B9, 0xFF79, 0x00BA, 0xFF7A, 0x00BB, 0xFF7B, 0x00BC, 0xFF7C, 0x00BD, 0xFF7D, 0x00BE, 0xFF7E, 0x00BF, 0xFF7F, 0x00C0, 0xFF80, 0x00C1, 0xFF81, 0x00C2, 0xFF82, 0x00C3, 0xFF83, 0x00C4, 0xFF84, 0x00C5, 0xFF85, 0x00C6, 0xFF86, 0x00C7, 0xFF87, 0x00C8, 0xFF88, 0x00C9, 0xFF89, 0x00CA, 0xFF8A, 0x00CB, 0xFF8B, 0x00CC, 0xFF8C, 0x00CD, 0xFF8D, 0x00CE, 0xFF8E, 0x00CF, 0xFF8F, 0x00D0, 0xFF90, 0x00D1, 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0x6A30, 0xFAEE, 0x6A6B, 0xFAEF, 0x6A46, 0xFAF0, 0x6A73, 0xFAF1, 0x6A7E, 0xFAF2, 0x6AE2, 0xFAF3, 0x6AE4, 0xFAF4, 0x6BD6, 0xFAF5, 0x6C3F, 0xFAF6, 0x6C5C, 0xFAF7, 0x6C86, 0xFAF8, 0x6C6F, 0xFAF9, 0x6CDA, 0xFAFA, 0x6D04, 0xFAFB, 0x6D87, 0xFAFC, 0x6D6F, 0xFB40, 0x6D96, 0xFB41, 0x6DAC, 0xFB42, 0x6DCF, 0xFB43, 0x6DF8, 0xFB44, 0x6DF2, 0xFB45, 0x6DFC, 0xFB46, 0x6E39, 0xFB47, 0x6E5C, 0xFB48, 0x6E27, 0xFB49, 0x6E3C, 0xFB4A, 0x6EBF, 0xFB4B, 0x6F88, 0xFB4C, 0x6FB5, 0xFB4D, 0x6FF5, 0xFB4E, 0x7005, 0xFB4F, 0x7007, 0xFB50, 0x7028, 0xFB51, 0x7085, 0xFB52, 0x70AB, 0xFB53, 0x710F, 0xFB54, 0x7104, 0xFB55, 0x715C, 0xFB56, 0x7146, 0xFB57, 0x7147, 0xFB58, 0xFA15, 0xFB59, 0x71C1, 0xFB5A, 0x71FE, 0xFB5B, 0x72B1, 0xFB5C, 0x72BE, 0xFB5D, 0x7324, 0xFB5E, 0xFA16, 0xFB5F, 0x7377, 0xFB60, 0x73BD, 0xFB61, 0x73C9, 0xFB62, 0x73D6, 0xFB63, 0x73E3, 0xFB64, 0x73D2, 0xFB65, 0x7407, 0xFB66, 0x73F5, 0xFB67, 0x7426, 0xFB68, 0x742A, 0xFB69, 0x7429, 0xFB6A, 0x742E, 0xFB6B, 0x7462, 0xFB6C, 0x7489, 0xFB6D, 0x749F, 0xFB6E, 0x7501, 0xFB6F, 0x756F, 0xFB70, 0x7682, 0xFB71, 0x769C, 0xFB72, 0x769E, 0xFB73, 0x769B, 0xFB74, 0x76A6, 0xFB75, 0xFA17, 0xFB76, 0x7746, 0xFB77, 0x52AF, 0xFB78, 0x7821, 0xFB79, 0x784E, 0xFB7A, 0x7864, 0xFB7B, 0x787A, 0xFB7C, 0x7930, 0xFB7D, 0xFA18, 0xFB7E, 0xFA19, 0xFB80, 0xFA1A, 0xFB81, 0x7994, 0xFB82, 0xFA1B, 0xFB83, 0x799B, 0xFB84, 0x7AD1, 0xFB85, 0x7AE7, 0xFB86, 0xFA1C, 0xFB87, 0x7AEB, 0xFB88, 0x7B9E, 0xFB89, 0xFA1D, 0xFB8A, 0x7D48, 0xFB8B, 0x7D5C, 0xFB8C, 0x7DB7, 0xFB8D, 0x7DA0, 0xFB8E, 0x7DD6, 0xFB8F, 0x7E52, 0xFB90, 0x7F47, 0xFB91, 0x7FA1, 0xFB92, 0xFA1E, 0xFB93, 0x8301, 0xFB94, 0x8362, 0xFB95, 0x837F, 0xFB96, 0x83C7, 0xFB97, 0x83F6, 0xFB98, 0x8448, 0xFB99, 0x84B4, 0xFB9A, 0x8553, 0xFB9B, 0x8559, 0xFB9C, 0x856B, 0xFB9D, 0xFA1F, 0xFB9E, 0x85B0, 0xFB9F, 0xFA20, 0xFBA0, 0xFA21, 0xFBA1, 0x8807, 0xFBA2, 0x88F5, 0xFBA3, 0x8A12, 0xFBA4, 0x8A37, 0xFBA5, 0x8A79, 0xFBA6, 0x8AA7, 0xFBA7, 0x8ABE, 0xFBA8, 0x8ADF, 0xFBA9, 0xFA22, 0xFBAA, 0x8AF6, 0xFBAB, 0x8B53, 0xFBAC, 0x8B7F, 0xFBAD, 0x8CF0, 0xFBAE, 0x8CF4, 0xFBAF, 0x8D12, 0xFBB0, 0x8D76, 0xFBB1, 0xFA23, 0xFBB2, 0x8ECF, 0xFBB3, 0xFA24, 0xFBB4, 0xFA25, 0xFBB5, 0x9067, 0xFBB6, 0x90DE, 0xFBB7, 0xFA26, 0xFBB8, 0x9115, 0xFBB9, 0x9127, 0xFBBA, 0x91DA, 0xFBBB, 0x91D7, 0xFBBC, 0x91DE, 0xFBBD, 0x91ED, 0xFBBE, 0x91EE, 0xFBBF, 0x91E4, 0xFBC0, 0x91E5, 0xFBC1, 0x9206, 0xFBC2, 0x9210, 0xFBC3, 0x920A, 0xFBC4, 0x923A, 0xFBC5, 0x9240, 0xFBC6, 0x923C, 0xFBC7, 0x924E, 0xFBC8, 0x9259, 0xFBC9, 0x9251, 0xFBCA, 0x9239, 0xFBCB, 0x9267, 0xFBCC, 0x92A7, 0xFBCD, 0x9277, 0xFBCE, 0x9278, 0xFBCF, 0x92E7, 0xFBD0, 0x92D7, 0xFBD1, 0x92D9, 0xFBD2, 0x92D0, 0xFBD3, 0xFA27, 0xFBD4, 0x92D5, 0xFBD5, 0x92E0, 0xFBD6, 0x92D3, 0xFBD7, 0x9325, 0xFBD8, 0x9321, 0xFBD9, 0x92FB, 0xFBDA, 0xFA28, 0xFBDB, 0x931E, 0xFBDC, 0x92FF, 0xFBDD, 0x931D, 0xFBDE, 0x9302, 0xFBDF, 0x9370, 0xFBE0, 0x9357, 0xFBE1, 0x93A4, 0xFBE2, 0x93C6, 0xFBE3, 0x93DE, 0xFBE4, 0x93F8, 0xFBE5, 0x9431, 0xFBE6, 0x9445, 0xFBE7, 0x9448, 0xFBE8, 0x9592, 0xFBE9, 0xF9DC, 0xFBEA, 0xFA29, 0xFBEB, 0x969D, 0xFBEC, 0x96AF, 0xFBED, 0x9733, 0xFBEE, 0x973B, 0xFBEF, 0x9743, 0xFBF0, 0x974D, 0xFBF1, 0x974F, 0xFBF2, 0x9751, 0xFBF3, 0x9755, 0xFBF4, 0x9857, 0xFBF5, 0x9865, 0xFBF6, 0xFA2A, 0xFBF7, 0xFA2B, 0xFBF8, 0x9927, 0xFBF9, 0xFA2C, 0xFBFA, 0x999E, 0xFBFB, 0x9A4E, 0xFBFC, 0x9AD9, 0xFC40, 0x9ADC, 0xFC41, 0x9B75, 0xFC42, 0x9B72, 0xFC43, 0x9B8F, 0xFC44, 0x9BB1, 0xFC45, 0x9BBB, 0xFC46, 0x9C00, 0xFC47, 0x9D70, 0xFC48, 0x9D6B, 0xFC49, 0xFA2D, 0xFC4A, 0x9E19, 0xFC4B, 0x9ED1, 0, 0 }; #endif #if FF_CODE_PAGE == 936 || FF_CODE_PAGE == 0 /* Simplified Chinese */ static const WCHAR uni2oem936[] = { /* Unicode --> GBK pairs */ 0x00A4, 0xA1E8, 0x00A7, 0xA1EC, 0x00A8, 0xA1A7, 0x00B0, 0xA1E3, 0x00B1, 0xA1C0, 0x00B7, 0xA1A4, 0x00D7, 0xA1C1, 0x00E0, 0xA8A4, 0x00E1, 0xA8A2, 0x00E8, 0xA8A8, 0x00E9, 0xA8A6, 0x00EA, 0xA8BA, 0x00EC, 0xA8AC, 0x00ED, 0xA8AA, 0x00F2, 0xA8B0, 0x00F3, 0xA8AE, 0x00F7, 0xA1C2, 0x00F9, 0xA8B4, 0x00FA, 0xA8B2, 0x00FC, 0xA8B9, 0x0101, 0xA8A1, 0x0113, 0xA8A5, 0x011B, 0xA8A7, 0x012B, 0xA8A9, 0x0144, 0xA8BD, 0x0148, 0xA8BE, 0x014D, 0xA8AD, 0x016B, 0xA8B1, 0x01CE, 0xA8A3, 0x01D0, 0xA8AB, 0x01D2, 0xA8AF, 0x01D4, 0xA8B3, 0x01D6, 0xA8B5, 0x01D8, 0xA8B6, 0x01DA, 0xA8B7, 0x01DC, 0xA8B8, 0x0251, 0xA8BB, 0x0261, 0xA8C0, 0x02C7, 0xA1A6, 0x02C9, 0xA1A5, 0x02CA, 0xA840, 0x02CB, 0xA841, 0x02D9, 0xA842, 0x0391, 0xA6A1, 0x0392, 0xA6A2, 0x0393, 0xA6A3, 0x0394, 0xA6A4, 0x0395, 0xA6A5, 0x0396, 0xA6A6, 0x0397, 0xA6A7, 0x0398, 0xA6A8, 0x0399, 0xA6A9, 0x039A, 0xA6AA, 0x039B, 0xA6AB, 0x039C, 0xA6AC, 0x039D, 0xA6AD, 0x039E, 0xA6AE, 0x039F, 0xA6AF, 0x03A0, 0xA6B0, 0x03A1, 0xA6B1, 0x03A3, 0xA6B2, 0x03A4, 0xA6B3, 0x03A5, 0xA6B4, 0x03A6, 0xA6B5, 0x03A7, 0xA6B6, 0x03A8, 0xA6B7, 0x03A9, 0xA6B8, 0x03B1, 0xA6C1, 0x03B2, 0xA6C2, 0x03B3, 0xA6C3, 0x03B4, 0xA6C4, 0x03B5, 0xA6C5, 0x03B6, 0xA6C6, 0x03B7, 0xA6C7, 0x03B8, 0xA6C8, 0x03B9, 0xA6C9, 0x03BA, 0xA6CA, 0x03BB, 0xA6CB, 0x03BC, 0xA6CC, 0x03BD, 0xA6CD, 0x03BE, 0xA6CE, 0x03BF, 0xA6CF, 0x03C0, 0xA6D0, 0x03C1, 0xA6D1, 0x03C3, 0xA6D2, 0x03C4, 0xA6D3, 0x03C5, 0xA6D4, 0x03C6, 0xA6D5, 0x03C7, 0xA6D6, 0x03C8, 0xA6D7, 0x03C9, 0xA6D8, 0x0401, 0xA7A7, 0x0410, 0xA7A1, 0x0411, 0xA7A2, 0x0412, 0xA7A3, 0x0413, 0xA7A4, 0x0414, 0xA7A5, 0x0415, 0xA7A6, 0x0416, 0xA7A8, 0x0417, 0xA7A9, 0x0418, 0xA7AA, 0x0419, 0xA7AB, 0x041A, 0xA7AC, 0x041B, 0xA7AD, 0x041C, 0xA7AE, 0x041D, 0xA7AF, 0x041E, 0xA7B0, 0x041F, 0xA7B1, 0x0420, 0xA7B2, 0x0421, 0xA7B3, 0x0422, 0xA7B4, 0x0423, 0xA7B5, 0x0424, 0xA7B6, 0x0425, 0xA7B7, 0x0426, 0xA7B8, 0x0427, 0xA7B9, 0x0428, 0xA7BA, 0x0429, 0xA7BB, 0x042A, 0xA7BC, 0x042B, 0xA7BD, 0x042C, 0xA7BE, 0x042D, 0xA7BF, 0x042E, 0xA7C0, 0x042F, 0xA7C1, 0x0430, 0xA7D1, 0x0431, 0xA7D2, 0x0432, 0xA7D3, 0x0433, 0xA7D4, 0x0434, 0xA7D5, 0x0435, 0xA7D6, 0x0436, 0xA7D8, 0x0437, 0xA7D9, 0x0438, 0xA7DA, 0x0439, 0xA7DB, 0x043A, 0xA7DC, 0x043B, 0xA7DD, 0x043C, 0xA7DE, 0x043D, 0xA7DF, 0x043E, 0xA7E0, 0x043F, 0xA7E1, 0x0440, 0xA7E2, 0x0441, 0xA7E3, 0x0442, 0xA7E4, 0x0443, 0xA7E5, 0x0444, 0xA7E6, 0x0445, 0xA7E7, 0x0446, 0xA7E8, 0x0447, 0xA7E9, 0x0448, 0xA7EA, 0x0449, 0xA7EB, 0x044A, 0xA7EC, 0x044B, 0xA7ED, 0x044C, 0xA7EE, 0x044D, 0xA7EF, 0x044E, 0xA7F0, 0x044F, 0xA7F1, 0x0451, 0xA7D7, 0x2010, 0xA95C, 0x2013, 0xA843, 0x2014, 0xA1AA, 0x2015, 0xA844, 0x2016, 0xA1AC, 0x2018, 0xA1AE, 0x2019, 0xA1AF, 0x201C, 0xA1B0, 0x201D, 0xA1B1, 0x2025, 0xA845, 0x2026, 0xA1AD, 0x2030, 0xA1EB, 0x2032, 0xA1E4, 0x2033, 0xA1E5, 0x2035, 0xA846, 0x203B, 0xA1F9, 0x20AC, 0x0080, 0x2103, 0xA1E6, 0x2105, 0xA847, 0x2109, 0xA848, 0x2116, 0xA1ED, 0x2121, 0xA959, 0x2160, 0xA2F1, 0x2161, 0xA2F2, 0x2162, 0xA2F3, 0x2163, 0xA2F4, 0x2164, 0xA2F5, 0x2165, 0xA2F6, 0x2166, 0xA2F7, 0x2167, 0xA2F8, 0x2168, 0xA2F9, 0x2169, 0xA2FA, 0x216A, 0xA2FB, 0x216B, 0xA2FC, 0x2170, 0xA2A1, 0x2171, 0xA2A2, 0x2172, 0xA2A3, 0x2173, 0xA2A4, 0x2174, 0xA2A5, 0x2175, 0xA2A6, 0x2176, 0xA2A7, 0x2177, 0xA2A8, 0x2178, 0xA2A9, 0x2179, 0xA2AA, 0x2190, 0xA1FB, 0x2191, 0xA1FC, 0x2192, 0xA1FA, 0x2193, 0xA1FD, 0x2196, 0xA849, 0x2197, 0xA84A, 0x2198, 0xA84B, 0x2199, 0xA84C, 0x2208, 0xA1CA, 0x220F, 0xA1C7, 0x2211, 0xA1C6, 0x2215, 0xA84D, 0x221A, 0xA1CC, 0x221D, 0xA1D8, 0x221E, 0xA1DE, 0x221F, 0xA84E, 0x2220, 0xA1CF, 0x2223, 0xA84F, 0x2225, 0xA1CE, 0x2227, 0xA1C4, 0x2228, 0xA1C5, 0x2229, 0xA1C9, 0x222A, 0xA1C8, 0x222B, 0xA1D2, 0x222E, 0xA1D3, 0x2234, 0xA1E0, 0x2235, 0xA1DF, 0x2236, 0xA1C3, 0x2237, 0xA1CB, 0x223D, 0xA1D7, 0x2248, 0xA1D6, 0x224C, 0xA1D5, 0x2252, 0xA850, 0x2260, 0xA1D9, 0x2261, 0xA1D4, 0x2264, 0xA1DC, 0x2265, 0xA1DD, 0x2266, 0xA851, 0x2267, 0xA852, 0x226E, 0xA1DA, 0x226F, 0xA1DB, 0x2295, 0xA892, 0x2299, 0xA1D1, 0x22A5, 0xA1CD, 0x22BF, 0xA853, 0x2312, 0xA1D0, 0x2460, 0xA2D9, 0x2461, 0xA2DA, 0x2462, 0xA2DB, 0x2463, 0xA2DC, 0x2464, 0xA2DD, 0x2465, 0xA2DE, 0x2466, 0xA2DF, 0x2467, 0xA2E0, 0x2468, 0xA2E1, 0x2469, 0xA2E2, 0x2474, 0xA2C5, 0x2475, 0xA2C6, 0x2476, 0xA2C7, 0x2477, 0xA2C8, 0x2478, 0xA2C9, 0x2479, 0xA2CA, 0x247A, 0xA2CB, 0x247B, 0xA2CC, 0x247C, 0xA2CD, 0x247D, 0xA2CE, 0x247E, 0xA2CF, 0x247F, 0xA2D0, 0x2480, 0xA2D1, 0x2481, 0xA2D2, 0x2482, 0xA2D3, 0x2483, 0xA2D4, 0x2484, 0xA2D5, 0x2485, 0xA2D6, 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0xFE3B, 0xA6EE, 0xFE3C, 0xA6EF, 0xFE3D, 0xA6E6, 0xFE3E, 0xA6E7, 0xFE3F, 0xA6E4, 0xFE40, 0xA6E5, 0xFE41, 0xA6E8, 0xFE42, 0xA6E9, 0xFE43, 0xA6EA, 0xFE44, 0xA6EB, 0xFE49, 0xA968, 0xFE4A, 0xA969, 0xFE4B, 0xA96A, 0xFE4C, 0xA96B, 0xFE4D, 0xA96C, 0xFE4E, 0xA96D, 0xFE4F, 0xA96E, 0xFE50, 0xA96F, 0xFE51, 0xA970, 0xFE52, 0xA971, 0xFE54, 0xA972, 0xFE55, 0xA973, 0xFE56, 0xA974, 0xFE57, 0xA975, 0xFE59, 0xA976, 0xFE5A, 0xA977, 0xFE5B, 0xA978, 0xFE5C, 0xA979, 0xFE5D, 0xA97A, 0xFE5E, 0xA97B, 0xFE5F, 0xA97C, 0xFE60, 0xA97D, 0xFE61, 0xA97E, 0xFE62, 0xA980, 0xFE63, 0xA981, 0xFE64, 0xA982, 0xFE65, 0xA983, 0xFE66, 0xA984, 0xFE68, 0xA985, 0xFE69, 0xA986, 0xFE6A, 0xA987, 0xFE6B, 0xA988, 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA1E7, 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA3DC, 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, 0xFF5D, 0xA3FD, 0xFF5E, 0xA1AB, 0xFFE0, 0xA1E9, 0xFFE1, 0xA1EA, 0xFFE2, 0xA956, 0xFFE3, 0xA3FE, 0xFFE4, 0xA957, 0xFFE5, 0xA3A4, 0, 0 }; static const WCHAR oem2uni936[] = { /* GBK --> Unicode pairs */ 0x0080, 0x20AC, 0x8140, 0x4E02, 0x8141, 0x4E04, 0x8142, 0x4E05, 0x8143, 0x4E06, 0x8144, 0x4E0F, 0x8145, 0x4E12, 0x8146, 0x4E17, 0x8147, 0x4E1F, 0x8148, 0x4E20, 0x8149, 0x4E21, 0x814A, 0x4E23, 0x814B, 0x4E26, 0x814C, 0x4E29, 0x814D, 0x4E2E, 0x814E, 0x4E2F, 0x814F, 0x4E31, 0x8150, 0x4E33, 0x8151, 0x4E35, 0x8152, 0x4E37, 0x8153, 0x4E3C, 0x8154, 0x4E40, 0x8155, 0x4E41, 0x8156, 0x4E42, 0x8157, 0x4E44, 0x8158, 0x4E46, 0x8159, 0x4E4A, 0x815A, 0x4E51, 0x815B, 0x4E55, 0x815C, 0x4E57, 0x815D, 0x4E5A, 0x815E, 0x4E5B, 0x815F, 0x4E62, 0x8160, 0x4E63, 0x8161, 0x4E64, 0x8162, 0x4E65, 0x8163, 0x4E67, 0x8164, 0x4E68, 0x8165, 0x4E6A, 0x8166, 0x4E6B, 0x8167, 0x4E6C, 0x8168, 0x4E6D, 0x8169, 0x4E6E, 0x816A, 0x4E6F, 0x816B, 0x4E72, 0x816C, 0x4E74, 0x816D, 0x4E75, 0x816E, 0x4E76, 0x816F, 0x4E77, 0x8170, 0x4E78, 0x8171, 0x4E79, 0x8172, 0x4E7A, 0x8173, 0x4E7B, 0x8174, 0x4E7C, 0x8175, 0x4E7D, 0x8176, 0x4E7F, 0x8177, 0x4E80, 0x8178, 0x4E81, 0x8179, 0x4E82, 0x817A, 0x4E83, 0x817B, 0x4E84, 0x817C, 0x4E85, 0x817D, 0x4E87, 0x817E, 0x4E8A, 0x8180, 0x4E90, 0x8181, 0x4E96, 0x8182, 0x4E97, 0x8183, 0x4E99, 0x8184, 0x4E9C, 0x8185, 0x4E9D, 0x8186, 0x4E9E, 0x8187, 0x4EA3, 0x8188, 0x4EAA, 0x8189, 0x4EAF, 0x818A, 0x4EB0, 0x818B, 0x4EB1, 0x818C, 0x4EB4, 0x818D, 0x4EB6, 0x818E, 0x4EB7, 0x818F, 0x4EB8, 0x8190, 0x4EB9, 0x8191, 0x4EBC, 0x8192, 0x4EBD, 0x8193, 0x4EBE, 0x8194, 0x4EC8, 0x8195, 0x4ECC, 0x8196, 0x4ECF, 0x8197, 0x4ED0, 0x8198, 0x4ED2, 0x8199, 0x4EDA, 0x819A, 0x4EDB, 0x819B, 0x4EDC, 0x819C, 0x4EE0, 0x819D, 0x4EE2, 0x819E, 0x4EE6, 0x819F, 0x4EE7, 0x81A0, 0x4EE9, 0x81A1, 0x4EED, 0x81A2, 0x4EEE, 0x81A3, 0x4EEF, 0x81A4, 0x4EF1, 0x81A5, 0x4EF4, 0x81A6, 0x4EF8, 0x81A7, 0x4EF9, 0x81A8, 0x4EFA, 0x81A9, 0x4EFC, 0x81AA, 0x4EFE, 0x81AB, 0x4F00, 0x81AC, 0x4F02, 0x81AD, 0x4F03, 0x81AE, 0x4F04, 0x81AF, 0x4F05, 0x81B0, 0x4F06, 0x81B1, 0x4F07, 0x81B2, 0x4F08, 0x81B3, 0x4F0B, 0x81B4, 0x4F0C, 0x81B5, 0x4F12, 0x81B6, 0x4F13, 0x81B7, 0x4F14, 0x81B8, 0x4F15, 0x81B9, 0x4F16, 0x81BA, 0x4F1C, 0x81BB, 0x4F1D, 0x81BC, 0x4F21, 0x81BD, 0x4F23, 0x81BE, 0x4F28, 0x81BF, 0x4F29, 0x81C0, 0x4F2C, 0x81C1, 0x4F2D, 0x81C2, 0x4F2E, 0x81C3, 0x4F31, 0x81C4, 0x4F33, 0x81C5, 0x4F35, 0x81C6, 0x4F37, 0x81C7, 0x4F39, 0x81C8, 0x4F3B, 0x81C9, 0x4F3E, 0x81CA, 0x4F3F, 0x81CB, 0x4F40, 0x81CC, 0x4F41, 0x81CD, 0x4F42, 0x81CE, 0x4F44, 0x81CF, 0x4F45, 0x81D0, 0x4F47, 0x81D1, 0x4F48, 0x81D2, 0x4F49, 0x81D3, 0x4F4A, 0x81D4, 0x4F4B, 0x81D5, 0x4F4C, 0x81D6, 0x4F52, 0x81D7, 0x4F54, 0x81D8, 0x4F56, 0x81D9, 0x4F61, 0x81DA, 0x4F62, 0x81DB, 0x4F66, 0x81DC, 0x4F68, 0x81DD, 0x4F6A, 0x81DE, 0x4F6B, 0x81DF, 0x4F6D, 0x81E0, 0x4F6E, 0x81E1, 0x4F71, 0x81E2, 0x4F72, 0x81E3, 0x4F75, 0x81E4, 0x4F77, 0x81E5, 0x4F78, 0x81E6, 0x4F79, 0x81E7, 0x4F7A, 0x81E8, 0x4F7D, 0x81E9, 0x4F80, 0x81EA, 0x4F81, 0x81EB, 0x4F82, 0x81EC, 0x4F85, 0x81ED, 0x4F86, 0x81EE, 0x4F87, 0x81EF, 0x4F8A, 0x81F0, 0x4F8C, 0x81F1, 0x4F8E, 0x81F2, 0x4F90, 0x81F3, 0x4F92, 0x81F4, 0x4F93, 0x81F5, 0x4F95, 0x81F6, 0x4F96, 0x81F7, 0x4F98, 0x81F8, 0x4F99, 0x81F9, 0x4F9A, 0x81FA, 0x4F9C, 0x81FB, 0x4F9E, 0x81FC, 0x4F9F, 0x81FD, 0x4FA1, 0x81FE, 0x4FA2, 0x8240, 0x4FA4, 0x8241, 0x4FAB, 0x8242, 0x4FAD, 0x8243, 0x4FB0, 0x8244, 0x4FB1, 0x8245, 0x4FB2, 0x8246, 0x4FB3, 0x8247, 0x4FB4, 0x8248, 0x4FB6, 0x8249, 0x4FB7, 0x824A, 0x4FB8, 0x824B, 0x4FB9, 0x824C, 0x4FBA, 0x824D, 0x4FBB, 0x824E, 0x4FBC, 0x824F, 0x4FBD, 0x8250, 0x4FBE, 0x8251, 0x4FC0, 0x8252, 0x4FC1, 0x8253, 0x4FC2, 0x8254, 0x4FC6, 0x8255, 0x4FC7, 0x8256, 0x4FC8, 0x8257, 0x4FC9, 0x8258, 0x4FCB, 0x8259, 0x4FCC, 0x825A, 0x4FCD, 0x825B, 0x4FD2, 0x825C, 0x4FD3, 0x825D, 0x4FD4, 0x825E, 0x4FD5, 0x825F, 0x4FD6, 0x8260, 0x4FD9, 0x8261, 0x4FDB, 0x8262, 0x4FE0, 0x8263, 0x4FE2, 0x8264, 0x4FE4, 0x8265, 0x4FE5, 0x8266, 0x4FE7, 0x8267, 0x4FEB, 0x8268, 0x4FEC, 0x8269, 0x4FF0, 0x826A, 0x4FF2, 0x826B, 0x4FF4, 0x826C, 0x4FF5, 0x826D, 0x4FF6, 0x826E, 0x4FF7, 0x826F, 0x4FF9, 0x8270, 0x4FFB, 0x8271, 0x4FFC, 0x8272, 0x4FFD, 0x8273, 0x4FFF, 0x8274, 0x5000, 0x8275, 0x5001, 0x8276, 0x5002, 0x8277, 0x5003, 0x8278, 0x5004, 0x8279, 0x5005, 0x827A, 0x5006, 0x827B, 0x5007, 0x827C, 0x5008, 0x827D, 0x5009, 0x827E, 0x500A, 0x8280, 0x500B, 0x8281, 0x500E, 0x8282, 0x5010, 0x8283, 0x5011, 0x8284, 0x5013, 0x8285, 0x5015, 0x8286, 0x5016, 0x8287, 0x5017, 0x8288, 0x501B, 0x8289, 0x501D, 0x828A, 0x501E, 0x828B, 0x5020, 0x828C, 0x5022, 0x828D, 0x5023, 0x828E, 0x5024, 0x828F, 0x5027, 0x8290, 0x502B, 0x8291, 0x502F, 0x8292, 0x5030, 0x8293, 0x5031, 0x8294, 0x5032, 0x8295, 0x5033, 0x8296, 0x5034, 0x8297, 0x5035, 0x8298, 0x5036, 0x8299, 0x5037, 0x829A, 0x5038, 0x829B, 0x5039, 0x829C, 0x503B, 0x829D, 0x503D, 0x829E, 0x503F, 0x829F, 0x5040, 0x82A0, 0x5041, 0x82A1, 0x5042, 0x82A2, 0x5044, 0x82A3, 0x5045, 0x82A4, 0x5046, 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0x77C8, 0xB28B, 0x77C9, 0xB28C, 0x77CA, 0xB28D, 0x77CB, 0xB28E, 0x77CC, 0xB28F, 0x77CE, 0xB290, 0x77CF, 0xB291, 0x77D0, 0xB292, 0x77D1, 0xB293, 0x77D2, 0xB294, 0x77D3, 0xB295, 0x77D4, 0xB296, 0x77D5, 0xB297, 0x77D6, 0xB298, 0x77D8, 0xB299, 0x77D9, 0xB29A, 0x77DA, 0xB29B, 0x77DD, 0xB29C, 0x77DE, 0xB29D, 0x77DF, 0xB29E, 0x77E0, 0xB29F, 0x77E1, 0xB2A0, 0x77E4, 0xB2A1, 0x75C5, 0xB2A2, 0x5E76, 0xB2A3, 0x73BB, 0xB2A4, 0x83E0, 0xB2A5, 0x64AD, 0xB2A6, 0x62E8, 0xB2A7, 0x94B5, 0xB2A8, 0x6CE2, 0xB2A9, 0x535A, 0xB2AA, 0x52C3, 0xB2AB, 0x640F, 0xB2AC, 0x94C2, 0xB2AD, 0x7B94, 0xB2AE, 0x4F2F, 0xB2AF, 0x5E1B, 0xB2B0, 0x8236, 0xB2B1, 0x8116, 0xB2B2, 0x818A, 0xB2B3, 0x6E24, 0xB2B4, 0x6CCA, 0xB2B5, 0x9A73, 0xB2B6, 0x6355, 0xB2B7, 0x535C, 0xB2B8, 0x54FA, 0xB2B9, 0x8865, 0xB2BA, 0x57E0, 0xB2BB, 0x4E0D, 0xB2BC, 0x5E03, 0xB2BD, 0x6B65, 0xB2BE, 0x7C3F, 0xB2BF, 0x90E8, 0xB2C0, 0x6016, 0xB2C1, 0x64E6, 0xB2C2, 0x731C, 0xB2C3, 0x88C1, 0xB2C4, 0x6750, 0xB2C5, 0x624D, 0xB2C6, 0x8D22, 0xB2C7, 0x776C, 0xB2C8, 0x8E29, 0xB2C9, 0x91C7, 0xB2CA, 0x5F69, 0xB2CB, 0x83DC, 0xB2CC, 0x8521, 0xB2CD, 0x9910, 0xB2CE, 0x53C2, 0xB2CF, 0x8695, 0xB2D0, 0x6B8B, 0xB2D1, 0x60ED, 0xB2D2, 0x60E8, 0xB2D3, 0x707F, 0xB2D4, 0x82CD, 0xB2D5, 0x8231, 0xB2D6, 0x4ED3, 0xB2D7, 0x6CA7, 0xB2D8, 0x85CF, 0xB2D9, 0x64CD, 0xB2DA, 0x7CD9, 0xB2DB, 0x69FD, 0xB2DC, 0x66F9, 0xB2DD, 0x8349, 0xB2DE, 0x5395, 0xB2DF, 0x7B56, 0xB2E0, 0x4FA7, 0xB2E1, 0x518C, 0xB2E2, 0x6D4B, 0xB2E3, 0x5C42, 0xB2E4, 0x8E6D, 0xB2E5, 0x63D2, 0xB2E6, 0x53C9, 0xB2E7, 0x832C, 0xB2E8, 0x8336, 0xB2E9, 0x67E5, 0xB2EA, 0x78B4, 0xB2EB, 0x643D, 0xB2EC, 0x5BDF, 0xB2ED, 0x5C94, 0xB2EE, 0x5DEE, 0xB2EF, 0x8BE7, 0xB2F0, 0x62C6, 0xB2F1, 0x67F4, 0xB2F2, 0x8C7A, 0xB2F3, 0x6400, 0xB2F4, 0x63BA, 0xB2F5, 0x8749, 0xB2F6, 0x998B, 0xB2F7, 0x8C17, 0xB2F8, 0x7F20, 0xB2F9, 0x94F2, 0xB2FA, 0x4EA7, 0xB2FB, 0x9610, 0xB2FC, 0x98A4, 0xB2FD, 0x660C, 0xB2FE, 0x7316, 0xB340, 0x77E6, 0xB341, 0x77E8, 0xB342, 0x77EA, 0xB343, 0x77EF, 0xB344, 0x77F0, 0xB345, 0x77F1, 0xB346, 0x77F2, 0xB347, 0x77F4, 0xB348, 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0xFE4F, 0xFA29, 0, 0 }; #endif #if FF_CODE_PAGE == 949 || FF_CODE_PAGE == 0 /* Korean */ static const WCHAR uni2oem949[] = { /* Unicode --> Korean pairs */ 0x00A1, 0xA2AE, 0x00A4, 0xA2B4, 0x00A7, 0xA1D7, 0x00A8, 0xA1A7, 0x00AA, 0xA8A3, 0x00AD, 0xA1A9, 0x00AE, 0xA2E7, 0x00B0, 0xA1C6, 0x00B1, 0xA1BE, 0x00B2, 0xA9F7, 0x00B3, 0xA9F8, 0x00B4, 0xA2A5, 0x00B6, 0xA2D2, 0x00B7, 0xA1A4, 0x00B8, 0xA2AC, 0x00B9, 0xA9F6, 0x00BA, 0xA8AC, 0x00BC, 0xA8F9, 0x00BD, 0xA8F6, 0x00BE, 0xA8FA, 0x00BF, 0xA2AF, 0x00C6, 0xA8A1, 0x00D0, 0xA8A2, 0x00D7, 0xA1BF, 0x00D8, 0xA8AA, 0x00DE, 0xA8AD, 0x00DF, 0xA9AC, 0x00E6, 0xA9A1, 0x00F0, 0xA9A3, 0x00F7, 0xA1C0, 0x00F8, 0xA9AA, 0x00FE, 0xA9AD, 0x0111, 0xA9A2, 0x0126, 0xA8A4, 0x0127, 0xA9A4, 0x0131, 0xA9A5, 0x0132, 0xA8A6, 0x0133, 0xA9A6, 0x0138, 0xA9A7, 0x013F, 0xA8A8, 0x0140, 0xA9A8, 0x0141, 0xA8A9, 0x0142, 0xA9A9, 0x0149, 0xA9B0, 0x014A, 0xA8AF, 0x014B, 0xA9AF, 0x0152, 0xA8AB, 0x0153, 0xA9AB, 0x0166, 0xA8AE, 0x0167, 0xA9AE, 0x02C7, 0xA2A7, 0x02D0, 0xA2B0, 0x02D8, 0xA2A8, 0x02D9, 0xA2AB, 0x02DA, 0xA2AA, 0x02DB, 0xA2AD, 0x02DD, 0xA2A9, 0x0391, 0xA5C1, 0x0392, 0xA5C2, 0x0393, 0xA5C3, 0x0394, 0xA5C4, 0x0395, 0xA5C5, 0x0396, 0xA5C6, 0x0397, 0xA5C7, 0x0398, 0xA5C8, 0x0399, 0xA5C9, 0x039A, 0xA5CA, 0x039B, 0xA5CB, 0x039C, 0xA5CC, 0x039D, 0xA5CD, 0x039E, 0xA5CE, 0x039F, 0xA5CF, 0x03A0, 0xA5D0, 0x03A1, 0xA5D1, 0x03A3, 0xA5D2, 0x03A4, 0xA5D3, 0x03A5, 0xA5D4, 0x03A6, 0xA5D5, 0x03A7, 0xA5D6, 0x03A8, 0xA5D7, 0x03A9, 0xA5D8, 0x03B1, 0xA5E1, 0x03B2, 0xA5E2, 0x03B3, 0xA5E3, 0x03B4, 0xA5E4, 0x03B5, 0xA5E5, 0x03B6, 0xA5E6, 0x03B7, 0xA5E7, 0x03B8, 0xA5E8, 0x03B9, 0xA5E9, 0x03BA, 0xA5EA, 0x03BB, 0xA5EB, 0x03BC, 0xA5EC, 0x03BD, 0xA5ED, 0x03BE, 0xA5EE, 0x03BF, 0xA5EF, 0x03C0, 0xA5F0, 0x03C1, 0xA5F1, 0x03C3, 0xA5F2, 0x03C4, 0xA5F3, 0x03C5, 0xA5F4, 0x03C6, 0xA5F5, 0x03C7, 0xA5F6, 0x03C8, 0xA5F7, 0x03C9, 0xA5F8, 0x0401, 0xACA7, 0x0410, 0xACA1, 0x0411, 0xACA2, 0x0412, 0xACA3, 0x0413, 0xACA4, 0x0414, 0xACA5, 0x0415, 0xACA6, 0x0416, 0xACA8, 0x0417, 0xACA9, 0x0418, 0xACAA, 0x0419, 0xACAB, 0x041A, 0xACAC, 0x041B, 0xACAD, 0x041C, 0xACAE, 0x041D, 0xACAF, 0x041E, 0xACB0, 0x041F, 0xACB1, 0x0420, 0xACB2, 0x0421, 0xACB3, 0x0422, 0xACB4, 0x0423, 0xACB5, 0x0424, 0xACB6, 0x0425, 0xACB7, 0x0426, 0xACB8, 0x0427, 0xACB9, 0x0428, 0xACBA, 0x0429, 0xACBB, 0x042A, 0xACBC, 0x042B, 0xACBD, 0x042C, 0xACBE, 0x042D, 0xACBF, 0x042E, 0xACC0, 0x042F, 0xACC1, 0x0430, 0xACD1, 0x0431, 0xACD2, 0x0432, 0xACD3, 0x0433, 0xACD4, 0x0434, 0xACD5, 0x0435, 0xACD6, 0x0436, 0xACD8, 0x0437, 0xACD9, 0x0438, 0xACDA, 0x0439, 0xACDB, 0x043A, 0xACDC, 0x043B, 0xACDD, 0x043C, 0xACDE, 0x043D, 0xACDF, 0x043E, 0xACE0, 0x043F, 0xACE1, 0x0440, 0xACE2, 0x0441, 0xACE3, 0x0442, 0xACE4, 0x0443, 0xACE5, 0x0444, 0xACE6, 0x0445, 0xACE7, 0x0446, 0xACE8, 0x0447, 0xACE9, 0x0448, 0xACEA, 0x0449, 0xACEB, 0x044A, 0xACEC, 0x044B, 0xACED, 0x044C, 0xACEE, 0x044D, 0xACEF, 0x044E, 0xACF0, 0x044F, 0xACF1, 0x0451, 0xACD7, 0x2015, 0xA1AA, 0x2018, 0xA1AE, 0x2019, 0xA1AF, 0x201C, 0xA1B0, 0x201D, 0xA1B1, 0x2020, 0xA2D3, 0x2021, 0xA2D4, 0x2025, 0xA1A5, 0x2026, 0xA1A6, 0x2030, 0xA2B6, 0x2032, 0xA1C7, 0x2033, 0xA1C8, 0x203B, 0xA1D8, 0x2074, 0xA9F9, 0x207F, 0xA9FA, 0x2081, 0xA9FB, 0x2082, 0xA9FC, 0x2083, 0xA9FD, 0x2084, 0xA9FE, 0x20AC, 0xA2E6, 0x2103, 0xA1C9, 0x2109, 0xA2B5, 0x2113, 0xA7A4, 0x2116, 0xA2E0, 0x2121, 0xA2E5, 0x2122, 0xA2E2, 0x2126, 0xA7D9, 0x212B, 0xA1CA, 0x2153, 0xA8F7, 0x2154, 0xA8F8, 0x215B, 0xA8FB, 0x215C, 0xA8FC, 0x215D, 0xA8FD, 0x215E, 0xA8FE, 0x2160, 0xA5B0, 0x2161, 0xA5B1, 0x2162, 0xA5B2, 0x2163, 0xA5B3, 0x2164, 0xA5B4, 0x2165, 0xA5B5, 0x2166, 0xA5B6, 0x2167, 0xA5B7, 0x2168, 0xA5B8, 0x2169, 0xA5B9, 0x2170, 0xA5A1, 0x2171, 0xA5A2, 0x2172, 0xA5A3, 0x2173, 0xA5A4, 0x2174, 0xA5A5, 0x2175, 0xA5A6, 0x2176, 0xA5A7, 0x2177, 0xA5A8, 0x2178, 0xA5A9, 0x2179, 0xA5AA, 0x2190, 0xA1E7, 0x2191, 0xA1E8, 0x2192, 0xA1E6, 0x2193, 0xA1E9, 0x2194, 0xA1EA, 0x2195, 0xA2D5, 0x2196, 0xA2D8, 0x2197, 0xA2D6, 0x2198, 0xA2D9, 0x2199, 0xA2D7, 0x21D2, 0xA2A1, 0x21D4, 0xA2A2, 0x2200, 0xA2A3, 0x2202, 0xA1D3, 0x2203, 0xA2A4, 0x2207, 0xA1D4, 0x2208, 0xA1F4, 0x220B, 0xA1F5, 0x220F, 0xA2B3, 0x2211, 0xA2B2, 0x221A, 0xA1EE, 0x221D, 0xA1F0, 0x221E, 0xA1C4, 0x2220, 0xA1D0, 0x2225, 0xA1AB, 0x2227, 0xA1FC, 0x2228, 0xA1FD, 0x2229, 0xA1FB, 0x222A, 0xA1FA, 0x222B, 0xA1F2, 0x222C, 0xA1F3, 0x222E, 0xA2B1, 0x2234, 0xA1C5, 0x2235, 0xA1F1, 0x223C, 0xA1AD, 0x223D, 0xA1EF, 0x2252, 0xA1D6, 0x2260, 0xA1C1, 0x2261, 0xA1D5, 0x2264, 0xA1C2, 0x2265, 0xA1C3, 0x226A, 0xA1EC, 0x226B, 0xA1ED, 0x2282, 0xA1F8, 0x2283, 0xA1F9, 0x2286, 0xA1F6, 0x2287, 0xA1F7, 0x2299, 0xA2C1, 0x22A5, 0xA1D1, 0x2312, 0xA1D2, 0x2460, 0xA8E7, 0x2461, 0xA8E8, 0x2462, 0xA8E9, 0x2463, 0xA8EA, 0x2464, 0xA8EB, 0x2465, 0xA8EC, 0x2466, 0xA8ED, 0x2467, 0xA8EE, 0x2468, 0xA8EF, 0x2469, 0xA8F0, 0x246A, 0xA8F1, 0x246B, 0xA8F2, 0x246C, 0xA8F3, 0x246D, 0xA8F4, 0x246E, 0xA8F5, 0x2474, 0xA9E7, 0x2475, 0xA9E8, 0x2476, 0xA9E9, 0x2477, 0xA9EA, 0x2478, 0xA9EB, 0x2479, 0xA9EC, 0x247A, 0xA9ED, 0x247B, 0xA9EE, 0x247C, 0xA9EF, 0x247D, 0xA9F0, 0x247E, 0xA9F1, 0x247F, 0xA9F2, 0x2480, 0xA9F3, 0x2481, 0xA9F4, 0x2482, 0xA9F5, 0x249C, 0xA9CD, 0x249D, 0xA9CE, 0x249E, 0xA9CF, 0x249F, 0xA9D0, 0x24A0, 0xA9D1, 0x24A1, 0xA9D2, 0x24A2, 0xA9D3, 0x24A3, 0xA9D4, 0x24A4, 0xA9D5, 0x24A5, 0xA9D6, 0x24A6, 0xA9D7, 0x24A7, 0xA9D8, 0x24A8, 0xA9D9, 0x24A9, 0xA9DA, 0x24AA, 0xA9DB, 0x24AB, 0xA9DC, 0x24AC, 0xA9DD, 0x24AD, 0xA9DE, 0x24AE, 0xA9DF, 0x24AF, 0xA9E0, 0x24B0, 0xA9E1, 0x24B1, 0xA9E2, 0x24B2, 0xA9E3, 0x24B3, 0xA9E4, 0x24B4, 0xA9E5, 0x24B5, 0xA9E6, 0x24D0, 0xA8CD, 0x24D1, 0xA8CE, 0x24D2, 0xA8CF, 0x24D3, 0xA8D0, 0x24D4, 0xA8D1, 0x24D5, 0xA8D2, 0x24D6, 0xA8D3, 0x24D7, 0xA8D4, 0x24D8, 0xA8D5, 0x24D9, 0xA8D6, 0x24DA, 0xA8D7, 0x24DB, 0xA8D8, 0x24DC, 0xA8D9, 0x24DD, 0xA8DA, 0x24DE, 0xA8DB, 0x24DF, 0xA8DC, 0x24E0, 0xA8DD, 0x24E1, 0xA8DE, 0x24E2, 0xA8DF, 0x24E3, 0xA8E0, 0x24E4, 0xA8E1, 0x24E5, 0xA8E2, 0x24E6, 0xA8E3, 0x24E7, 0xA8E4, 0x24E8, 0xA8E5, 0x24E9, 0xA8E6, 0x2500, 0xA6A1, 0x2501, 0xA6AC, 0x2502, 0xA6A2, 0x2503, 0xA6AD, 0x250C, 0xA6A3, 0x250D, 0xA6C8, 0x250E, 0xA6C7, 0x250F, 0xA6AE, 0x2510, 0xA6A4, 0x2511, 0xA6C2, 0x2512, 0xA6C1, 0x2513, 0xA6AF, 0x2514, 0xA6A6, 0x2515, 0xA6C6, 0x2516, 0xA6C5, 0x2517, 0xA6B1, 0x2518, 0xA6A5, 0x2519, 0xA6C4, 0x251A, 0xA6C3, 0x251B, 0xA6B0, 0x251C, 0xA6A7, 0x251D, 0xA6BC, 0x251E, 0xA6C9, 0x251F, 0xA6CA, 0x2520, 0xA6B7, 0x2521, 0xA6CB, 0x2522, 0xA6CC, 0x2523, 0xA6B2, 0x2524, 0xA6A9, 0x2525, 0xA6BE, 0x2526, 0xA6CD, 0x2527, 0xA6CE, 0x2528, 0xA6B9, 0x2529, 0xA6CF, 0x252A, 0xA6D0, 0x252B, 0xA6B4, 0x252C, 0xA6A8, 0x252D, 0xA6D1, 0x252E, 0xA6D2, 0x252F, 0xA6B8, 0x2530, 0xA6BD, 0x2531, 0xA6D3, 0x2532, 0xA6D4, 0x2533, 0xA6B3, 0x2534, 0xA6AA, 0x2535, 0xA6D5, 0x2536, 0xA6D6, 0x2537, 0xA6BA, 0x2538, 0xA6BF, 0x2539, 0xA6D7, 0x253A, 0xA6D8, 0x253B, 0xA6B5, 0x253C, 0xA6AB, 0x253D, 0xA6D9, 0x253E, 0xA6DA, 0x253F, 0xA6BB, 0x2540, 0xA6DB, 0x2541, 0xA6DC, 0x2542, 0xA6C0, 0x2543, 0xA6DD, 0x2544, 0xA6DE, 0x2545, 0xA6DF, 0x2546, 0xA6E0, 0x2547, 0xA6E1, 0x2548, 0xA6E2, 0x2549, 0xA6E3, 0x254A, 0xA6E4, 0x254B, 0xA6B6, 0x2592, 0xA2C6, 0x25A0, 0xA1E1, 0x25A1, 0xA1E0, 0x25A3, 0xA2C3, 0x25A4, 0xA2C7, 0x25A5, 0xA2C8, 0x25A6, 0xA2CB, 0x25A7, 0xA2CA, 0x25A8, 0xA2C9, 0x25A9, 0xA2CC, 0x25B2, 0xA1E3, 0x25B3, 0xA1E2, 0x25B6, 0xA2BA, 0x25B7, 0xA2B9, 0x25BC, 0xA1E5, 0x25BD, 0xA1E4, 0x25C0, 0xA2B8, 0x25C1, 0xA2B7, 0x25C6, 0xA1DF, 0x25C7, 0xA1DE, 0x25C8, 0xA2C2, 0x25CB, 0xA1DB, 0x25CE, 0xA1DD, 0x25CF, 0xA1DC, 0x25D0, 0xA2C4, 0x25D1, 0xA2C5, 0x2605, 0xA1DA, 0x2606, 0xA1D9, 0x260E, 0xA2CF, 0x260F, 0xA2CE, 0x261C, 0xA2D0, 0x261E, 0xA2D1, 0x2640, 0xA1CF, 0x2642, 0xA1CE, 0x2660, 0xA2BC, 0x2661, 0xA2BD, 0x2663, 0xA2C0, 0x2664, 0xA2BB, 0x2665, 0xA2BE, 0x2667, 0xA2BF, 0x2668, 0xA2CD, 0x2669, 0xA2DB, 0x266A, 0xA2DC, 0x266C, 0xA2DD, 0x266D, 0xA2DA, 0x3000, 0xA1A1, 0x3001, 0xA1A2, 0x3002, 0xA1A3, 0x3003, 0xA1A8, 0x3008, 0xA1B4, 0x3009, 0xA1B5, 0x300A, 0xA1B6, 0x300B, 0xA1B7, 0x300C, 0xA1B8, 0x300D, 0xA1B9, 0x300E, 0xA1BA, 0x300F, 0xA1BB, 0x3010, 0xA1BC, 0x3011, 0xA1BD, 0x3013, 0xA1EB, 0x3014, 0xA1B2, 0x3015, 0xA1B3, 0x3041, 0xAAA1, 0x3042, 0xAAA2, 0x3043, 0xAAA3, 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0xB1CA, 0x8772, 0xB1CB, 0x8773, 0xB1CC, 0xB3FA, 0xB1CD, 0x8774, 0xB1CE, 0x8775, 0xB1CF, 0x8776, 0xB1D0, 0xB3FB, 0xB1D1, 0x8777, 0xB1D2, 0x8778, 0xB1D3, 0x8779, 0xB1D4, 0xB3FC, 0xB1D5, 0x877A, 0xB1D6, 0x8781, 0xB1D7, 0x8782, 0xB1D8, 0x8783, 0xB1D9, 0x8784, 0xB1DA, 0x8785, 0xB1DB, 0x8786, 0xB1DC, 0xB3FD, 0xB1DD, 0xB3FE, 0xB1DE, 0x8787, 0xB1DF, 0xB4A1, 0xB1E0, 0x8788, 0xB1E1, 0x8789, 0xB1E2, 0x878A, 0xB1E3, 0x878B, 0xB1E4, 0x878C, 0xB1E5, 0x878D, 0xB1E6, 0x878E, 0xB1E7, 0x878F, 0xB1E8, 0xB4A2, 0xB1E9, 0xB4A3, 0xB1EA, 0x8790, 0xB1EB, 0x8791, 0xB1EC, 0xB4A4, 0xB1ED, 0x8792, 0xB1EE, 0x8793, 0xB1EF, 0x8794, 0xB1F0, 0xB4A5, 0xB1F1, 0x8795, 0xB1F2, 0x8796, 0xB1F3, 0x8797, 0xB1F4, 0x8798, 0xB1F5, 0x8799, 0xB1F6, 0x879A, 0xB1F7, 0x879B, 0xB1F8, 0x879C, 0xB1F9, 0xB4A6, 0xB1FA, 0x879D, 0xB1FB, 0xB4A7, 0xB1FC, 0x879E, 0xB1FD, 0xB4A8, 0xB1FE, 0x879F, 0xB1FF, 0x87A0, 0xB200, 0x87A1, 0xB201, 0x87A2, 0xB202, 0x87A3, 0xB203, 0x87A4, 0xB204, 0xB4A9, 0xB205, 0xB4AA, 0xB206, 0x87A5, 0xB207, 0x87A6, 0xB208, 0xB4AB, 0xB209, 0x87A7, 0xB20A, 0x87A8, 0xB20B, 0xB4AC, 0xB20C, 0xB4AD, 0xB20D, 0x87A9, 0xB20E, 0x87AA, 0xB20F, 0x87AB, 0xB210, 0x87AC, 0xB211, 0x87AD, 0xB212, 0x87AE, 0xB213, 0x87AF, 0xB214, 0xB4AE, 0xB215, 0xB4AF, 0xB216, 0x87B0, 0xB217, 0xB4B0, 0xB218, 0x87B1, 0xB219, 0xB4B1, 0xB21A, 0x87B2, 0xB21B, 0x87B3, 0xB21C, 0x87B4, 0xB21D, 0x87B5, 0xB21E, 0x87B6, 0xB21F, 0x87B7, 0xB220, 0xB4B2, 0xB221, 0x87B8, 0xB222, 0x87B9, 0xB223, 0x87BA, 0xB224, 0x87BB, 0xB225, 0x87BC, 0xB226, 0x87BD, 0xB227, 0x87BE, 0xB228, 0x87BF, 0xB229, 0x87C0, 0xB22A, 0x87C1, 0xB22B, 0x87C2, 0xB22C, 0x87C3, 0xB22D, 0x87C4, 0xB22E, 0x87C5, 0xB22F, 0x87C6, 0xB230, 0x87C7, 0xB231, 0x87C8, 0xB232, 0x87C9, 0xB233, 0x87CA, 0xB234, 0xB4B3, 0xB235, 0x87CB, 0xB236, 0x87CC, 0xB237, 0x87CD, 0xB238, 0x87CE, 0xB239, 0x87CF, 0xB23A, 0x87D0, 0xB23B, 0x87D1, 0xB23C, 0xB4B4, 0xB23D, 0x87D2, 0xB23E, 0x87D3, 0xB23F, 0x87D4, 0xB240, 0x87D5, 0xB241, 0x87D6, 0xB242, 0x87D7, 0xB243, 0x87D8, 0xB244, 0x87D9, 0xB245, 0x87DA, 0xB246, 0x87DB, 0xB247, 0x87DC, 0xB248, 0x87DD, 0xB249, 0x87DE, 0xB24A, 0x87DF, 0xB24B, 0x87E0, 0xB24C, 0x87E1, 0xB24D, 0x87E2, 0xB24E, 0x87E3, 0xB24F, 0x87E4, 0xB250, 0x87E5, 0xB251, 0x87E6, 0xB252, 0x87E7, 0xB253, 0x87E8, 0xB254, 0x87E9, 0xB255, 0x87EA, 0xB256, 0x87EB, 0xB257, 0x87EC, 0xB258, 0xB4B5, 0xB259, 0x87ED, 0xB25A, 0x87EE, 0xB25B, 0x87EF, 0xB25C, 0xB4B6, 0xB25D, 0x87F0, 0xB25E, 0x87F1, 0xB25F, 0x87F2, 0xB260, 0xB4B7, 0xB261, 0x87F3, 0xB262, 0x87F4, 0xB263, 0x87F5, 0xB264, 0x87F6, 0xB265, 0x87F7, 0xB266, 0x87F8, 0xB267, 0x87F9, 0xB268, 0xB4B8, 0xB269, 0xB4B9, 0xB26A, 0x87FA, 0xB26B, 0x87FB, 0xB26C, 0x87FC, 0xB26D, 0x87FD, 0xB26E, 0x87FE, 0xB26F, 0x8841, 0xB270, 0x8842, 0xB271, 0x8843, 0xB272, 0x8844, 0xB273, 0x8845, 0xB274, 0xB4BA, 0xB275, 0xB4BB, 0xB276, 0x8846, 0xB277, 0x8847, 0xB278, 0x8848, 0xB279, 0x8849, 0xB27A, 0x884A, 0xB27B, 0x884B, 0xB27C, 0xB4BC, 0xB27D, 0x884C, 0xB27E, 0x884D, 0xB27F, 0x884E, 0xB280, 0x884F, 0xB281, 0x8850, 0xB282, 0x8851, 0xB283, 0x8852, 0xB284, 0xB4BD, 0xB285, 0xB4BE, 0xB286, 0x8853, 0xB287, 0x8854, 0xB288, 0x8855, 0xB289, 0xB4BF, 0xB28A, 0x8856, 0xB28B, 0x8857, 0xB28C, 0x8858, 0xB28D, 0x8859, 0xB28E, 0x885A, 0xB28F, 0x8861, 0xB290, 0xB4C0, 0xB291, 0xB4C1, 0xB292, 0x8862, 0xB293, 0x8863, 0xB294, 0xB4C2, 0xB295, 0x8864, 0xB296, 0x8865, 0xB297, 0x8866, 0xB298, 0xB4C3, 0xB299, 0xB4C4, 0xB29A, 0xB4C5, 0xB29B, 0x8867, 0xB29C, 0x8868, 0xB29D, 0x8869, 0xB29E, 0x886A, 0xB29F, 0x886B, 0xB2A0, 0xB4C6, 0xB2A1, 0xB4C7, 0xB2A2, 0x886C, 0xB2A3, 0xB4C8, 0xB2A4, 0x886D, 0xB2A5, 0xB4C9, 0xB2A6, 0xB4CA, 0xB2A7, 0x886E, 0xB2A8, 0x886F, 0xB2A9, 0x8870, 0xB2AA, 0xB4CB, 0xB2AB, 0x8871, 0xB2AC, 0xB4CC, 0xB2AD, 0x8872, 0xB2AE, 0x8873, 0xB2AF, 0x8874, 0xB2B0, 0xB4CD, 0xB2B1, 0x8875, 0xB2B2, 0x8876, 0xB2B3, 0x8877, 0xB2B4, 0xB4CE, 0xB2B5, 0x8878, 0xB2B6, 0x8879, 0xB2B7, 0x887A, 0xB2B8, 0x8881, 0xB2B9, 0x8882, 0xB2BA, 0x8883, 0xB2BB, 0x8884, 0xB2BC, 0x8885, 0xB2BD, 0x8886, 0xB2BE, 0x8887, 0xB2BF, 0x8888, 0xB2C0, 0x8889, 0xB2C1, 0x888A, 0xB2C2, 0x888B, 0xB2C3, 0x888C, 0xB2C4, 0x888D, 0xB2C5, 0x888E, 0xB2C6, 0x888F, 0xB2C7, 0x8890, 0xB2C8, 0xB4CF, 0xB2C9, 0xB4D0, 0xB2CA, 0x8891, 0xB2CB, 0x8892, 0xB2CC, 0xB4D1, 0xB2CD, 0x8893, 0xB2CE, 0x8894, 0xB2CF, 0x8895, 0xB2D0, 0xB4D2, 0xB2D1, 0x8896, 0xB2D2, 0xB4D3, 0xB2D3, 0x8897, 0xB2D4, 0x8898, 0xB2D5, 0x8899, 0xB2D6, 0x889A, 0xB2D7, 0x889B, 0xB2D8, 0xB4D4, 0xB2D9, 0xB4D5, 0xB2DA, 0x889C, 0xB2DB, 0xB4D6, 0xB2DC, 0x889D, 0xB2DD, 0xB4D7, 0xB2DE, 0x889E, 0xB2DF, 0x889F, 0xB2E0, 0x88A0, 0xB2E1, 0x88A1, 0xB2E2, 0xB4D8, 0xB2E3, 0x88A2, 0xB2E4, 0xB4D9, 0xB2E5, 0xB4DA, 0xB2E6, 0xB4DB, 0xB2E7, 0x88A3, 0xB2E8, 0xB4DC, 0xB2E9, 0x88A4, 0xB2EA, 0x88A5, 0xB2EB, 0xB4DD, 0xB2EC, 0xB4DE, 0xB2ED, 0xB4DF, 0xB2EE, 0xB4E0, 0xB2EF, 0xB4E1, 0xB2F0, 0x88A6, 0xB2F1, 0x88A7, 0xB2F2, 0x88A8, 0xB2F3, 0xB4E2, 0xB2F4, 0xB4E3, 0xB2F5, 0xB4E4, 0xB2F6, 0x88A9, 0xB2F7, 0xB4E5, 0xB2F8, 0xB4E6, 0xB2F9, 0xB4E7, 0xB2FA, 0xB4E8, 0xB2FB, 0xB4E9, 0xB2FC, 0x88AA, 0xB2FD, 0x88AB, 0xB2FE, 0x88AC, 0xB2FF, 0xB4EA, 0xB300, 0xB4EB, 0xB301, 0xB4EC, 0xB302, 0x88AD, 0xB303, 0x88AE, 0xB304, 0xB4ED, 0xB305, 0x88AF, 0xB306, 0x88B0, 0xB307, 0x88B1, 0xB308, 0xB4EE, 0xB309, 0x88B2, 0xB30A, 0x88B3, 0xB30B, 0x88B4, 0xB30C, 0x88B5, 0xB30D, 0x88B6, 0xB30E, 0x88B7, 0xB30F, 0x88B8, 0xB310, 0xB4EF, 0xB311, 0xB4F0, 0xB312, 0x88B9, 0xB313, 0xB4F1, 0xB314, 0xB4F2, 0xB315, 0xB4F3, 0xB316, 0x88BA, 0xB317, 0x88BB, 0xB318, 0x88BC, 0xB319, 0x88BD, 0xB31A, 0x88BE, 0xB31B, 0x88BF, 0xB31C, 0xB4F4, 0xB31D, 0x88C0, 0xB31E, 0x88C1, 0xB31F, 0x88C2, 0xB320, 0x88C3, 0xB321, 0x88C4, 0xB322, 0x88C5, 0xB323, 0x88C6, 0xB324, 0x88C7, 0xB325, 0x88C8, 0xB326, 0x88C9, 0xB327, 0x88CA, 0xB328, 0x88CB, 0xB329, 0x88CC, 0xB32A, 0x88CD, 0xB32B, 0x88CE, 0xB32C, 0x88CF, 0xB32D, 0x88D0, 0xB32E, 0x88D1, 0xB32F, 0x88D2, 0xB330, 0x88D3, 0xB331, 0x88D4, 0xB332, 0x88D5, 0xB333, 0x88D6, 0xB334, 0x88D7, 0xB335, 0x88D8, 0xB336, 0x88D9, 0xB337, 0x88DA, 0xB338, 0x88DB, 0xB339, 0x88DC, 0xB33A, 0x88DD, 0xB33B, 0x88DE, 0xB33C, 0x88DF, 0xB33D, 0x88E0, 0xB33E, 0x88E1, 0xB33F, 0x88E2, 0xB340, 0x88E3, 0xB341, 0x88E4, 0xB342, 0x88E5, 0xB343, 0x88E6, 0xB344, 0x88E7, 0xB345, 0x88E8, 0xB346, 0x88E9, 0xB347, 0x88EA, 0xB348, 0x88EB, 0xB349, 0x88EC, 0xB34A, 0x88ED, 0xB34B, 0x88EE, 0xB34C, 0x88EF, 0xB34D, 0x88F0, 0xB34E, 0x88F1, 0xB34F, 0x88F2, 0xB350, 0x88F3, 0xB351, 0x88F4, 0xB352, 0x88F5, 0xB353, 0x88F6, 0xB354, 0xB4F5, 0xB355, 0xB4F6, 0xB356, 0xB4F7, 0xB357, 0x88F7, 0xB358, 0xB4F8, 0xB359, 0x88F8, 0xB35A, 0x88F9, 0xB35B, 0xB4F9, 0xB35C, 0xB4FA, 0xB35D, 0x88FA, 0xB35E, 0xB4FB, 0xB35F, 0xB4FC, 0xB360, 0x88FB, 0xB361, 0x88FC, 0xB362, 0x88FD, 0xB363, 0x88FE, 0xB364, 0xB4FD, 0xB365, 0xB4FE, 0xB366, 0x8941, 0xB367, 0xB5A1, 0xB368, 0x8942, 0xB369, 0xB5A2, 0xB36A, 0x8943, 0xB36B, 0xB5A3, 0xB36C, 0x8944, 0xB36D, 0x8945, 0xB36E, 0xB5A4, 0xB36F, 0x8946, 0xB370, 0xB5A5, 0xB371, 0xB5A6, 0xB372, 0x8947, 0xB373, 0x8948, 0xB374, 0xB5A7, 0xB375, 0x8949, 0xB376, 0x894A, 0xB377, 0x894B, 0xB378, 0xB5A8, 0xB379, 0x894C, 0xB37A, 0x894D, 0xB37B, 0x894E, 0xB37C, 0x894F, 0xB37D, 0x8950, 0xB37E, 0x8951, 0xB37F, 0x8952, 0xB380, 0xB5A9, 0xB381, 0xB5AA, 0xB382, 0x8953, 0xB383, 0xB5AB, 0xB384, 0xB5AC, 0xB385, 0xB5AD, 0xB386, 0x8954, 0xB387, 0x8955, 0xB388, 0x8956, 0xB389, 0x8957, 0xB38A, 0x8958, 0xB38B, 0x8959, 0xB38C, 0xB5AE, 0xB38D, 0x895A, 0xB38E, 0x8961, 0xB38F, 0x8962, 0xB390, 0xB5AF, 0xB391, 0x8963, 0xB392, 0x8964, 0xB393, 0x8965, 0xB394, 0xB5B0, 0xB395, 0x8966, 0xB396, 0x8967, 0xB397, 0x8968, 0xB398, 0x8969, 0xB399, 0x896A, 0xB39A, 0x896B, 0xB39B, 0x896C, 0xB39C, 0x896D, 0xB39D, 0x896E, 0xB39E, 0x896F, 0xB39F, 0x8970, 0xB3A0, 0xB5B1, 0xB3A1, 0xB5B2, 0xB3A2, 0x8971, 0xB3A3, 0x8972, 0xB3A4, 0x8973, 0xB3A5, 0x8974, 0xB3A6, 0x8975, 0xB3A7, 0x8976, 0xB3A8, 0xB5B3, 0xB3A9, 0x8977, 0xB3AA, 0x8978, 0xB3AB, 0x8979, 0xB3AC, 0xB5B4, 0xB3AD, 0x897A, 0xB3AE, 0x8981, 0xB3AF, 0x8982, 0xB3B0, 0x8983, 0xB3B1, 0x8984, 0xB3B2, 0x8985, 0xB3B3, 0x8986, 0xB3B4, 0x8987, 0xB3B5, 0x8988, 0xB3B6, 0x8989, 0xB3B7, 0x898A, 0xB3B8, 0x898B, 0xB3B9, 0x898C, 0xB3BA, 0x898D, 0xB3BB, 0x898E, 0xB3BC, 0x898F, 0xB3BD, 0x8990, 0xB3BE, 0x8991, 0xB3BF, 0x8992, 0xB3C0, 0x8993, 0xB3C1, 0x8994, 0xB3C2, 0x8995, 0xB3C3, 0x8996, 0xB3C4, 0xB5B5, 0xB3C5, 0xB5B6, 0xB3C6, 0x8997, 0xB3C7, 0x8998, 0xB3C8, 0xB5B7, 0xB3C9, 0x8999, 0xB3CA, 0x899A, 0xB3CB, 0xB5B8, 0xB3CC, 0xB5B9, 0xB3CD, 0x899B, 0xB3CE, 0xB5BA, 0xB3CF, 0x899C, 0xB3D0, 0xB5BB, 0xB3D1, 0x899D, 0xB3D2, 0x899E, 0xB3D3, 0x899F, 0xB3D4, 0xB5BC, 0xB3D5, 0xB5BD, 0xB3D6, 0x89A0, 0xB3D7, 0xB5BE, 0xB3D8, 0x89A1, 0xB3D9, 0xB5BF, 0xB3DA, 0x89A2, 0xB3DB, 0xB5C0, 0xB3DC, 0x89A3, 0xB3DD, 0xB5C1, 0xB3DE, 0x89A4, 0xB3DF, 0x89A5, 0xB3E0, 0xB5C2, 0xB3E1, 0x89A6, 0xB3E2, 0x89A7, 0xB3E3, 0x89A8, 0xB3E4, 0xB5C3, 0xB3E5, 0x89A9, 0xB3E6, 0x89AA, 0xB3E7, 0x89AB, 0xB3E8, 0xB5C4, 0xB3E9, 0x89AC, 0xB3EA, 0x89AD, 0xB3EB, 0x89AE, 0xB3EC, 0x89AF, 0xB3ED, 0x89B0, 0xB3EE, 0x89B1, 0xB3EF, 0x89B2, 0xB3F0, 0x89B3, 0xB3F1, 0x89B4, 0xB3F2, 0x89B5, 0xB3F3, 0x89B6, 0xB3F4, 0x89B7, 0xB3F5, 0x89B8, 0xB3F6, 0x89B9, 0xB3F7, 0x89BA, 0xB3F8, 0x89BB, 0xB3F9, 0x89BC, 0xB3FA, 0x89BD, 0xB3FB, 0x89BE, 0xB3FC, 0xB5C5, 0xB3FD, 0x89BF, 0xB3FE, 0x89C0, 0xB3FF, 0x89C1, 0xB400, 0x89C2, 0xB401, 0x89C3, 0xB402, 0x89C4, 0xB403, 0x89C5, 0xB404, 0x89C6, 0xB405, 0x89C7, 0xB406, 0x89C8, 0xB407, 0x89C9, 0xB408, 0x89CA, 0xB409, 0x89CB, 0xB40A, 0x89CC, 0xB40B, 0x89CD, 0xB40C, 0x89CE, 0xB40D, 0x89CF, 0xB40E, 0x89D0, 0xB40F, 0x89D1, 0xB410, 0xB5C6, 0xB411, 0x89D2, 0xB412, 0x89D3, 0xB413, 0x89D4, 0xB414, 0x89D5, 0xB415, 0x89D6, 0xB416, 0x89D7, 0xB417, 0x89D8, 0xB418, 0xB5C7, 0xB419, 0x89D9, 0xB41A, 0x89DA, 0xB41B, 0x89DB, 0xB41C, 0xB5C8, 0xB41D, 0x89DC, 0xB41E, 0x89DD, 0xB41F, 0x89DE, 0xB420, 0xB5C9, 0xB421, 0x89DF, 0xB422, 0x89E0, 0xB423, 0x89E1, 0xB424, 0x89E2, 0xB425, 0x89E3, 0xB426, 0x89E4, 0xB427, 0x89E5, 0xB428, 0xB5CA, 0xB429, 0xB5CB, 0xB42A, 0x89E6, 0xB42B, 0xB5CC, 0xB42C, 0x89E7, 0xB42D, 0x89E8, 0xB42E, 0x89E9, 0xB42F, 0x89EA, 0xB430, 0x89EB, 0xB431, 0x89EC, 0xB432, 0x89ED, 0xB433, 0x89EE, 0xB434, 0xB5CD, 0xB435, 0x89EF, 0xB436, 0x89F0, 0xB437, 0x89F1, 0xB438, 0x89F2, 0xB439, 0x89F3, 0xB43A, 0x89F4, 0xB43B, 0x89F5, 0xB43C, 0x89F6, 0xB43D, 0x89F7, 0xB43E, 0x89F8, 0xB43F, 0x89F9, 0xB440, 0x89FA, 0xB441, 0x89FB, 0xB442, 0x89FC, 0xB443, 0x89FD, 0xB444, 0x89FE, 0xB445, 0x8A41, 0xB446, 0x8A42, 0xB447, 0x8A43, 0xB448, 0x8A44, 0xB449, 0x8A45, 0xB44A, 0x8A46, 0xB44B, 0x8A47, 0xB44C, 0x8A48, 0xB44D, 0x8A49, 0xB44E, 0x8A4A, 0xB44F, 0x8A4B, 0xB450, 0xB5CE, 0xB451, 0xB5CF, 0xB452, 0x8A4C, 0xB453, 0x8A4D, 0xB454, 0xB5D0, 0xB455, 0x8A4E, 0xB456, 0x8A4F, 0xB457, 0x8A50, 0xB458, 0xB5D1, 0xB459, 0x8A51, 0xB45A, 0x8A52, 0xB45B, 0x8A53, 0xB45C, 0x8A54, 0xB45D, 0x8A55, 0xB45E, 0x8A56, 0xB45F, 0x8A57, 0xB460, 0xB5D2, 0xB461, 0xB5D3, 0xB462, 0x8A58, 0xB463, 0xB5D4, 0xB464, 0x8A59, 0xB465, 0xB5D5, 0xB466, 0x8A5A, 0xB467, 0x8A61, 0xB468, 0x8A62, 0xB469, 0x8A63, 0xB46A, 0x8A64, 0xB46B, 0x8A65, 0xB46C, 0xB5D6, 0xB46D, 0x8A66, 0xB46E, 0x8A67, 0xB46F, 0x8A68, 0xB470, 0x8A69, 0xB471, 0x8A6A, 0xB472, 0x8A6B, 0xB473, 0x8A6C, 0xB474, 0x8A6D, 0xB475, 0x8A6E, 0xB476, 0x8A6F, 0xB477, 0x8A70, 0xB478, 0x8A71, 0xB479, 0x8A72, 0xB47A, 0x8A73, 0xB47B, 0x8A74, 0xB47C, 0x8A75, 0xB47D, 0x8A76, 0xB47E, 0x8A77, 0xB47F, 0x8A78, 0xB480, 0xB5D7, 0xB481, 0x8A79, 0xB482, 0x8A7A, 0xB483, 0x8A81, 0xB484, 0x8A82, 0xB485, 0x8A83, 0xB486, 0x8A84, 0xB487, 0x8A85, 0xB488, 0xB5D8, 0xB489, 0x8A86, 0xB48A, 0x8A87, 0xB48B, 0x8A88, 0xB48C, 0x8A89, 0xB48D, 0x8A8A, 0xB48E, 0x8A8B, 0xB48F, 0x8A8C, 0xB490, 0x8A8D, 0xB491, 0x8A8E, 0xB492, 0x8A8F, 0xB493, 0x8A90, 0xB494, 0x8A91, 0xB495, 0x8A92, 0xB496, 0x8A93, 0xB497, 0x8A94, 0xB498, 0x8A95, 0xB499, 0x8A96, 0xB49A, 0x8A97, 0xB49B, 0x8A98, 0xB49C, 0x8A99, 0xB49D, 0xB5D9, 0xB49E, 0x8A9A, 0xB49F, 0x8A9B, 0xB4A0, 0x8A9C, 0xB4A1, 0x8A9D, 0xB4A2, 0x8A9E, 0xB4A3, 0x8A9F, 0xB4A4, 0xB5DA, 0xB4A5, 0x8AA0, 0xB4A6, 0x8AA1, 0xB4A7, 0x8AA2, 0xB4A8, 0xB5DB, 0xB4A9, 0x8AA3, 0xB4AA, 0x8AA4, 0xB4AB, 0x8AA5, 0xB4AC, 0xB5DC, 0xB4AD, 0x8AA6, 0xB4AE, 0x8AA7, 0xB4AF, 0x8AA8, 0xB4B0, 0x8AA9, 0xB4B1, 0x8AAA, 0xB4B2, 0x8AAB, 0xB4B3, 0x8AAC, 0xB4B4, 0x8AAD, 0xB4B5, 0xB5DD, 0xB4B6, 0x8AAE, 0xB4B7, 0xB5DE, 0xB4B8, 0x8AAF, 0xB4B9, 0xB5DF, 0xB4BA, 0x8AB0, 0xB4BB, 0x8AB1, 0xB4BC, 0x8AB2, 0xB4BD, 0x8AB3, 0xB4BE, 0x8AB4, 0xB4BF, 0x8AB5, 0xB4C0, 0xB5E0, 0xB4C1, 0x8AB6, 0xB4C2, 0x8AB7, 0xB4C3, 0x8AB8, 0xB4C4, 0xB5E1, 0xB4C5, 0x8AB9, 0xB4C6, 0x8ABA, 0xB4C7, 0x8ABB, 0xB4C8, 0xB5E2, 0xB4C9, 0x8ABC, 0xB4CA, 0x8ABD, 0xB4CB, 0x8ABE, 0xB4CC, 0x8ABF, 0xB4CD, 0x8AC0, 0xB4CE, 0x8AC1, 0xB4CF, 0x8AC2, 0xB4D0, 0xB5E3, 0xB4D1, 0x8AC3, 0xB4D2, 0x8AC4, 0xB4D3, 0x8AC5, 0xB4D4, 0x8AC6, 0xB4D5, 0xB5E4, 0xB4D6, 0x8AC7, 0xB4D7, 0x8AC8, 0xB4D8, 0x8AC9, 0xB4D9, 0x8ACA, 0xB4DA, 0x8ACB, 0xB4DB, 0x8ACC, 0xB4DC, 0xB5E5, 0xB4DD, 0xB5E6, 0xB4DE, 0x8ACD, 0xB4DF, 0x8ACE, 0xB4E0, 0xB5E7, 0xB4E1, 0x8ACF, 0xB4E2, 0x8AD0, 0xB4E3, 0xB5E8, 0xB4E4, 0xB5E9, 0xB4E5, 0x8AD1, 0xB4E6, 0xB5EA, 0xB4E7, 0x8AD2, 0xB4E8, 0x8AD3, 0xB4E9, 0x8AD4, 0xB4EA, 0x8AD5, 0xB4EB, 0x8AD6, 0xB4EC, 0xB5EB, 0xB4ED, 0xB5EC, 0xB4EE, 0x8AD7, 0xB4EF, 0xB5ED, 0xB4F0, 0x8AD8, 0xB4F1, 0xB5EE, 0xB4F2, 0x8AD9, 0xB4F3, 0x8ADA, 0xB4F4, 0x8ADB, 0xB4F5, 0x8ADC, 0xB4F6, 0x8ADD, 0xB4F7, 0x8ADE, 0xB4F8, 0xB5EF, 0xB4F9, 0x8ADF, 0xB4FA, 0x8AE0, 0xB4FB, 0x8AE1, 0xB4FC, 0x8AE2, 0xB4FD, 0x8AE3, 0xB4FE, 0x8AE4, 0xB4FF, 0x8AE5, 0xB500, 0x8AE6, 0xB501, 0x8AE7, 0xB502, 0x8AE8, 0xB503, 0x8AE9, 0xB504, 0x8AEA, 0xB505, 0x8AEB, 0xB506, 0x8AEC, 0xB507, 0x8AED, 0xB508, 0x8AEE, 0xB509, 0x8AEF, 0xB50A, 0x8AF0, 0xB50B, 0x8AF1, 0xB50C, 0x8AF2, 0xB50D, 0x8AF3, 0xB50E, 0x8AF4, 0xB50F, 0x8AF5, 0xB510, 0x8AF6, 0xB511, 0x8AF7, 0xB512, 0x8AF8, 0xB513, 0x8AF9, 0xB514, 0xB5F0, 0xB515, 0xB5F1, 0xB516, 0x8AFA, 0xB517, 0x8AFB, 0xB518, 0xB5F2, 0xB519, 0x8AFC, 0xB51A, 0x8AFD, 0xB51B, 0xB5F3, 0xB51C, 0xB5F4, 0xB51D, 0x8AFE, 0xB51E, 0x8B41, 0xB51F, 0x8B42, 0xB520, 0x8B43, 0xB521, 0x8B44, 0xB522, 0x8B45, 0xB523, 0x8B46, 0xB524, 0xB5F5, 0xB525, 0xB5F6, 0xB526, 0x8B47, 0xB527, 0xB5F7, 0xB528, 0xB5F8, 0xB529, 0xB5F9, 0xB52A, 0xB5FA, 0xB52B, 0x8B48, 0xB52C, 0x8B49, 0xB52D, 0x8B4A, 0xB52E, 0x8B4B, 0xB52F, 0x8B4C, 0xB530, 0xB5FB, 0xB531, 0xB5FC, 0xB532, 0x8B4D, 0xB533, 0x8B4E, 0xB534, 0xB5FD, 0xB535, 0x8B4F, 0xB536, 0x8B50, 0xB537, 0x8B51, 0xB538, 0xB5FE, 0xB539, 0x8B52, 0xB53A, 0x8B53, 0xB53B, 0x8B54, 0xB53C, 0x8B55, 0xB53D, 0x8B56, 0xB53E, 0x8B57, 0xB53F, 0x8B58, 0xB540, 0xB6A1, 0xB541, 0xB6A2, 0xB542, 0x8B59, 0xB543, 0xB6A3, 0xB544, 0xB6A4, 0xB545, 0xB6A5, 0xB546, 0x8B5A, 0xB547, 0x8B61, 0xB548, 0x8B62, 0xB549, 0x8B63, 0xB54A, 0x8B64, 0xB54B, 0xB6A6, 0xB54C, 0xB6A7, 0xB54D, 0xB6A8, 0xB54E, 0x8B65, 0xB54F, 0x8B66, 0xB550, 0xB6A9, 0xB551, 0x8B67, 0xB552, 0x8B68, 0xB553, 0x8B69, 0xB554, 0xB6AA, 0xB555, 0x8B6A, 0xB556, 0x8B6B, 0xB557, 0x8B6C, 0xB558, 0x8B6D, 0xB559, 0x8B6E, 0xB55A, 0x8B6F, 0xB55B, 0x8B70, 0xB55C, 0xB6AB, 0xB55D, 0xB6AC, 0xB55E, 0x8B71, 0xB55F, 0xB6AD, 0xB560, 0xB6AE, 0xB561, 0xB6AF, 0xB562, 0x8B72, 0xB563, 0x8B73, 0xB564, 0x8B74, 0xB565, 0x8B75, 0xB566, 0x8B76, 0xB567, 0x8B77, 0xB568, 0x8B78, 0xB569, 0x8B79, 0xB56A, 0x8B7A, 0xB56B, 0x8B81, 0xB56C, 0x8B82, 0xB56D, 0x8B83, 0xB56E, 0x8B84, 0xB56F, 0x8B85, 0xB570, 0x8B86, 0xB571, 0x8B87, 0xB572, 0x8B88, 0xB573, 0x8B89, 0xB574, 0x8B8A, 0xB575, 0x8B8B, 0xB576, 0x8B8C, 0xB577, 0x8B8D, 0xB578, 0x8B8E, 0xB579, 0x8B8F, 0xB57A, 0x8B90, 0xB57B, 0x8B91, 0xB57C, 0x8B92, 0xB57D, 0x8B93, 0xB57E, 0x8B94, 0xB57F, 0x8B95, 0xB580, 0x8B96, 0xB581, 0x8B97, 0xB582, 0x8B98, 0xB583, 0x8B99, 0xB584, 0x8B9A, 0xB585, 0x8B9B, 0xB586, 0x8B9C, 0xB587, 0x8B9D, 0xB588, 0x8B9E, 0xB589, 0x8B9F, 0xB58A, 0x8BA0, 0xB58B, 0x8BA1, 0xB58C, 0x8BA2, 0xB58D, 0x8BA3, 0xB58E, 0x8BA4, 0xB58F, 0x8BA5, 0xB590, 0x8BA6, 0xB591, 0x8BA7, 0xB592, 0x8BA8, 0xB593, 0x8BA9, 0xB594, 0x8BAA, 0xB595, 0x8BAB, 0xB596, 0x8BAC, 0xB597, 0x8BAD, 0xB598, 0x8BAE, 0xB599, 0x8BAF, 0xB59A, 0x8BB0, 0xB59B, 0x8BB1, 0xB59C, 0x8BB2, 0xB59D, 0x8BB3, 0xB59E, 0x8BB4, 0xB59F, 0x8BB5, 0xB5A0, 0xB6B0, 0xB5A1, 0xB6B1, 0xB5A2, 0x8BB6, 0xB5A3, 0x8BB7, 0xB5A4, 0xB6B2, 0xB5A5, 0x8BB8, 0xB5A6, 0x8BB9, 0xB5A7, 0x8BBA, 0xB5A8, 0xB6B3, 0xB5A9, 0x8BBB, 0xB5AA, 0xB6B4, 0xB5AB, 0xB6B5, 0xB5AC, 0x8BBC, 0xB5AD, 0x8BBD, 0xB5AE, 0x8BBE, 0xB5AF, 0x8BBF, 0xB5B0, 0xB6B6, 0xB5B1, 0xB6B7, 0xB5B2, 0x8BC0, 0xB5B3, 0xB6B8, 0xB5B4, 0xB6B9, 0xB5B5, 0xB6BA, 0xB5B6, 0x8BC1, 0xB5B7, 0x8BC2, 0xB5B8, 0x8BC3, 0xB5B9, 0x8BC4, 0xB5BA, 0x8BC5, 0xB5BB, 0xB6BB, 0xB5BC, 0xB6BC, 0xB5BD, 0xB6BD, 0xB5BE, 0x8BC6, 0xB5BF, 0x8BC7, 0xB5C0, 0xB6BE, 0xB5C1, 0x8BC8, 0xB5C2, 0x8BC9, 0xB5C3, 0x8BCA, 0xB5C4, 0xB6BF, 0xB5C5, 0x8BCB, 0xB5C6, 0x8BCC, 0xB5C7, 0x8BCD, 0xB5C8, 0x8BCE, 0xB5C9, 0x8BCF, 0xB5CA, 0x8BD0, 0xB5CB, 0x8BD1, 0xB5CC, 0xB6C0, 0xB5CD, 0xB6C1, 0xB5CE, 0x8BD2, 0xB5CF, 0xB6C2, 0xB5D0, 0xB6C3, 0xB5D1, 0xB6C4, 0xB5D2, 0x8BD3, 0xB5D3, 0x8BD4, 0xB5D4, 0x8BD5, 0xB5D5, 0x8BD6, 0xB5D6, 0x8BD7, 0xB5D7, 0x8BD8, 0xB5D8, 0xB6C5, 0xB5D9, 0x8BD9, 0xB5DA, 0x8BDA, 0xB5DB, 0x8BDB, 0xB5DC, 0x8BDC, 0xB5DD, 0x8BDD, 0xB5DE, 0x8BDE, 0xB5DF, 0x8BDF, 0xB5E0, 0x8BE0, 0xB5E1, 0x8BE1, 0xB5E2, 0x8BE2, 0xB5E3, 0x8BE3, 0xB5E4, 0x8BE4, 0xB5E5, 0x8BE5, 0xB5E6, 0x8BE6, 0xB5E7, 0x8BE7, 0xB5E8, 0x8BE8, 0xB5E9, 0x8BE9, 0xB5EA, 0x8BEA, 0xB5EB, 0x8BEB, 0xB5EC, 0xB6C6, 0xB5ED, 0x8BEC, 0xB5EE, 0x8BED, 0xB5EF, 0x8BEE, 0xB5F0, 0x8BEF, 0xB5F1, 0x8BF0, 0xB5F2, 0x8BF1, 0xB5F3, 0x8BF2, 0xB5F4, 0x8BF3, 0xB5F5, 0x8BF4, 0xB5F6, 0x8BF5, 0xB5F7, 0x8BF6, 0xB5F8, 0x8BF7, 0xB5F9, 0x8BF8, 0xB5FA, 0x8BF9, 0xB5FB, 0x8BFA, 0xB5FC, 0x8BFB, 0xB5FD, 0x8BFC, 0xB5FE, 0x8BFD, 0xB5FF, 0x8BFE, 0xB600, 0x8C41, 0xB601, 0x8C42, 0xB602, 0x8C43, 0xB603, 0x8C44, 0xB604, 0x8C45, 0xB605, 0x8C46, 0xB606, 0x8C47, 0xB607, 0x8C48, 0xB608, 0x8C49, 0xB609, 0x8C4A, 0xB60A, 0x8C4B, 0xB60B, 0x8C4C, 0xB60C, 0x8C4D, 0xB60D, 0x8C4E, 0xB60E, 0x8C4F, 0xB60F, 0x8C50, 0xB610, 0xB6C7, 0xB611, 0xB6C8, 0xB612, 0x8C51, 0xB613, 0x8C52, 0xB614, 0xB6C9, 0xB615, 0x8C53, 0xB616, 0x8C54, 0xB617, 0x8C55, 0xB618, 0xB6CA, 0xB619, 0x8C56, 0xB61A, 0x8C57, 0xB61B, 0x8C58, 0xB61C, 0x8C59, 0xB61D, 0x8C5A, 0xB61E, 0x8C61, 0xB61F, 0x8C62, 0xB620, 0x8C63, 0xB621, 0x8C64, 0xB622, 0x8C65, 0xB623, 0x8C66, 0xB624, 0x8C67, 0xB625, 0xB6CB, 0xB626, 0x8C68, 0xB627, 0x8C69, 0xB628, 0x8C6A, 0xB629, 0x8C6B, 0xB62A, 0x8C6C, 0xB62B, 0x8C6D, 0xB62C, 0xB6CC, 0xB62D, 0x8C6E, 0xB62E, 0x8C6F, 0xB62F, 0x8C70, 0xB630, 0x8C71, 0xB631, 0x8C72, 0xB632, 0x8C73, 0xB633, 0x8C74, 0xB634, 0xB6CD, 0xB635, 0x8C75, 0xB636, 0x8C76, 0xB637, 0x8C77, 0xB638, 0x8C78, 0xB639, 0x8C79, 0xB63A, 0x8C7A, 0xB63B, 0x8C81, 0xB63C, 0x8C82, 0xB63D, 0x8C83, 0xB63E, 0x8C84, 0xB63F, 0x8C85, 0xB640, 0x8C86, 0xB641, 0x8C87, 0xB642, 0x8C88, 0xB643, 0x8C89, 0xB644, 0x8C8A, 0xB645, 0x8C8B, 0xB646, 0x8C8C, 0xB647, 0x8C8D, 0xB648, 0xB6CE, 0xB649, 0x8C8E, 0xB64A, 0x8C8F, 0xB64B, 0x8C90, 0xB64C, 0x8C91, 0xB64D, 0x8C92, 0xB64E, 0x8C93, 0xB64F, 0x8C94, 0xB650, 0x8C95, 0xB651, 0x8C96, 0xB652, 0x8C97, 0xB653, 0x8C98, 0xB654, 0x8C99, 0xB655, 0x8C9A, 0xB656, 0x8C9B, 0xB657, 0x8C9C, 0xB658, 0x8C9D, 0xB659, 0x8C9E, 0xB65A, 0x8C9F, 0xB65B, 0x8CA0, 0xB65C, 0x8CA1, 0xB65D, 0x8CA2, 0xB65E, 0x8CA3, 0xB65F, 0x8CA4, 0xB660, 0x8CA5, 0xB661, 0x8CA6, 0xB662, 0x8CA7, 0xB663, 0x8CA8, 0xB664, 0xB6CF, 0xB665, 0x8CA9, 0xB666, 0x8CAA, 0xB667, 0x8CAB, 0xB668, 0xB6D0, 0xB669, 0x8CAC, 0xB66A, 0x8CAD, 0xB66B, 0x8CAE, 0xB66C, 0x8CAF, 0xB66D, 0x8CB0, 0xB66E, 0x8CB1, 0xB66F, 0x8CB2, 0xB670, 0x8CB3, 0xB671, 0x8CB4, 0xB672, 0x8CB5, 0xB673, 0x8CB6, 0xB674, 0x8CB7, 0xB675, 0x8CB8, 0xB676, 0x8CB9, 0xB677, 0x8CBA, 0xB678, 0x8CBB, 0xB679, 0x8CBC, 0xB67A, 0x8CBD, 0xB67B, 0x8CBE, 0xB67C, 0x8CBF, 0xB67D, 0x8CC0, 0xB67E, 0x8CC1, 0xB67F, 0x8CC2, 0xB680, 0x8CC3, 0xB681, 0x8CC4, 0xB682, 0x8CC5, 0xB683, 0x8CC6, 0xB684, 0x8CC7, 0xB685, 0x8CC8, 0xB686, 0x8CC9, 0xB687, 0x8CCA, 0xB688, 0x8CCB, 0xB689, 0x8CCC, 0xB68A, 0x8CCD, 0xB68B, 0x8CCE, 0xB68C, 0x8CCF, 0xB68D, 0x8CD0, 0xB68E, 0x8CD1, 0xB68F, 0x8CD2, 0xB690, 0x8CD3, 0xB691, 0x8CD4, 0xB692, 0x8CD5, 0xB693, 0x8CD6, 0xB694, 0x8CD7, 0xB695, 0x8CD8, 0xB696, 0x8CD9, 0xB697, 0x8CDA, 0xB698, 0x8CDB, 0xB699, 0x8CDC, 0xB69A, 0x8CDD, 0xB69B, 0x8CDE, 0xB69C, 0xB6D1, 0xB69D, 0xB6D2, 0xB69E, 0x8CDF, 0xB69F, 0x8CE0, 0xB6A0, 0xB6D3, 0xB6A1, 0x8CE1, 0xB6A2, 0x8CE2, 0xB6A3, 0x8CE3, 0xB6A4, 0xB6D4, 0xB6A5, 0x8CE4, 0xB6A6, 0x8CE5, 0xB6A7, 0x8CE6, 0xB6A8, 0x8CE7, 0xB6A9, 0x8CE8, 0xB6AA, 0x8CE9, 0xB6AB, 0xB6D5, 0xB6AC, 0xB6D6, 0xB6AD, 0x8CEA, 0xB6AE, 0x8CEB, 0xB6AF, 0x8CEC, 0xB6B0, 0x8CED, 0xB6B1, 0xB6D7, 0xB6B2, 0x8CEE, 0xB6B3, 0x8CEF, 0xB6B4, 0x8CF0, 0xB6B5, 0x8CF1, 0xB6B6, 0x8CF2, 0xB6B7, 0x8CF3, 0xB6B8, 0x8CF4, 0xB6B9, 0x8CF5, 0xB6BA, 0x8CF6, 0xB6BB, 0x8CF7, 0xB6BC, 0x8CF8, 0xB6BD, 0x8CF9, 0xB6BE, 0x8CFA, 0xB6BF, 0x8CFB, 0xB6C0, 0x8CFC, 0xB6C1, 0x8CFD, 0xB6C2, 0x8CFE, 0xB6C3, 0x8D41, 0xB6C4, 0x8D42, 0xB6C5, 0x8D43, 0xB6C6, 0x8D44, 0xB6C7, 0x8D45, 0xB6C8, 0x8D46, 0xB6C9, 0x8D47, 0xB6CA, 0x8D48, 0xB6CB, 0x8D49, 0xB6CC, 0x8D4A, 0xB6CD, 0x8D4B, 0xB6CE, 0x8D4C, 0xB6CF, 0x8D4D, 0xB6D0, 0x8D4E, 0xB6D1, 0x8D4F, 0xB6D2, 0x8D50, 0xB6D3, 0x8D51, 0xB6D4, 0xB6D8, 0xB6D5, 0x8D52, 0xB6D6, 0x8D53, 0xB6D7, 0x8D54, 0xB6D8, 0x8D55, 0xB6D9, 0x8D56, 0xB6DA, 0x8D57, 0xB6DB, 0x8D58, 0xB6DC, 0x8D59, 0xB6DD, 0x8D5A, 0xB6DE, 0x8D61, 0xB6DF, 0x8D62, 0xB6E0, 0x8D63, 0xB6E1, 0x8D64, 0xB6E2, 0x8D65, 0xB6E3, 0x8D66, 0xB6E4, 0x8D67, 0xB6E5, 0x8D68, 0xB6E6, 0x8D69, 0xB6E7, 0x8D6A, 0xB6E8, 0x8D6B, 0xB6E9, 0x8D6C, 0xB6EA, 0x8D6D, 0xB6EB, 0x8D6E, 0xB6EC, 0x8D6F, 0xB6ED, 0x8D70, 0xB6EE, 0x8D71, 0xB6EF, 0x8D72, 0xB6F0, 0xB6D9, 0xB6F1, 0x8D73, 0xB6F2, 0x8D74, 0xB6F3, 0x8D75, 0xB6F4, 0xB6DA, 0xB6F5, 0x8D76, 0xB6F6, 0x8D77, 0xB6F7, 0x8D78, 0xB6F8, 0xB6DB, 0xB6F9, 0x8D79, 0xB6FA, 0x8D7A, 0xB6FB, 0x8D81, 0xB6FC, 0x8D82, 0xB6FD, 0x8D83, 0xB6FE, 0x8D84, 0xB6FF, 0x8D85, 0xB700, 0xB6DC, 0xB701, 0xB6DD, 0xB702, 0x8D86, 0xB703, 0x8D87, 0xB704, 0x8D88, 0xB705, 0xB6DE, 0xB706, 0x8D89, 0xB707, 0x8D8A, 0xB708, 0x8D8B, 0xB709, 0x8D8C, 0xB70A, 0x8D8D, 0xB70B, 0x8D8E, 0xB70C, 0x8D8F, 0xB70D, 0x8D90, 0xB70E, 0x8D91, 0xB70F, 0x8D92, 0xB710, 0x8D93, 0xB711, 0x8D94, 0xB712, 0x8D95, 0xB713, 0x8D96, 0xB714, 0x8D97, 0xB715, 0x8D98, 0xB716, 0x8D99, 0xB717, 0x8D9A, 0xB718, 0x8D9B, 0xB719, 0x8D9C, 0xB71A, 0x8D9D, 0xB71B, 0x8D9E, 0xB71C, 0x8D9F, 0xB71D, 0x8DA0, 0xB71E, 0x8DA1, 0xB71F, 0x8DA2, 0xB720, 0x8DA3, 0xB721, 0x8DA4, 0xB722, 0x8DA5, 0xB723, 0x8DA6, 0xB724, 0x8DA7, 0xB725, 0x8DA8, 0xB726, 0x8DA9, 0xB727, 0x8DAA, 0xB728, 0xB6DF, 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0xB7A6, 0x8E47, 0xB7A7, 0x8E48, 0xB7A8, 0xB7A5, 0xB7A9, 0xB7A6, 0xB7AA, 0x8E49, 0xB7AB, 0xB7A7, 0xB7AC, 0xB7A8, 0xB7AD, 0xB7A9, 0xB7AE, 0x8E4A, 0xB7AF, 0x8E4B, 0xB7B0, 0x8E4C, 0xB7B1, 0x8E4D, 0xB7B2, 0x8E4E, 0xB7B3, 0x8E4F, 0xB7B4, 0xB7AA, 0xB7B5, 0xB7AB, 0xB7B6, 0x8E50, 0xB7B7, 0x8E51, 0xB7B8, 0xB7AC, 0xB7B9, 0x8E52, 0xB7BA, 0x8E53, 0xB7BB, 0x8E54, 0xB7BC, 0x8E55, 0xB7BD, 0x8E56, 0xB7BE, 0x8E57, 0xB7BF, 0x8E58, 0xB7C0, 0x8E59, 0xB7C1, 0x8E5A, 0xB7C2, 0x8E61, 0xB7C3, 0x8E62, 0xB7C4, 0x8E63, 0xB7C5, 0x8E64, 0xB7C6, 0x8E65, 0xB7C7, 0xB7AD, 0xB7C8, 0x8E66, 0xB7C9, 0xB7AE, 0xB7CA, 0x8E67, 0xB7CB, 0x8E68, 0xB7CC, 0x8E69, 0xB7CD, 0x8E6A, 0xB7CE, 0x8E6B, 0xB7CF, 0x8E6C, 0xB7D0, 0x8E6D, 0xB7D1, 0x8E6E, 0xB7D2, 0x8E6F, 0xB7D3, 0x8E70, 0xB7D4, 0x8E71, 0xB7D5, 0x8E72, 0xB7D6, 0x8E73, 0xB7D7, 0x8E74, 0xB7D8, 0x8E75, 0xB7D9, 0x8E76, 0xB7DA, 0x8E77, 0xB7DB, 0x8E78, 0xB7DC, 0x8E79, 0xB7DD, 0x8E7A, 0xB7DE, 0x8E81, 0xB7DF, 0x8E82, 0xB7E0, 0x8E83, 0xB7E1, 0x8E84, 0xB7E2, 0x8E85, 0xB7E3, 0x8E86, 0xB7E4, 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0xD669, 0xC8B2, 0xD66A, 0xC367, 0xD66B, 0xC368, 0xD66C, 0xC369, 0xD66D, 0xC36A, 0xD66E, 0xC36B, 0xD66F, 0xC36C, 0xD670, 0xC8B3, 0xD671, 0xC8B4, 0xD672, 0xC36D, 0xD673, 0xC36E, 0xD674, 0xC8B5, 0xD675, 0xC36F, 0xD676, 0xC370, 0xD677, 0xC371, 0xD678, 0xC372, 0xD679, 0xC373, 0xD67A, 0xC374, 0xD67B, 0xC375, 0xD67C, 0xC376, 0xD67D, 0xC377, 0xD67E, 0xC378, 0xD67F, 0xC379, 0xD680, 0xC37A, 0xD681, 0xC381, 0xD682, 0xC382, 0xD683, 0xC8B6, 0xD684, 0xC383, 0xD685, 0xC8B7, 0xD686, 0xC384, 0xD687, 0xC385, 0xD688, 0xC386, 0xD689, 0xC387, 0xD68A, 0xC388, 0xD68B, 0xC389, 0xD68C, 0xC8B8, 0xD68D, 0xC8B9, 0xD68E, 0xC38A, 0xD68F, 0xC38B, 0xD690, 0xC8BA, 0xD691, 0xC38C, 0xD692, 0xC38D, 0xD693, 0xC38E, 0xD694, 0xC8BB, 0xD695, 0xC38F, 0xD696, 0xC390, 0xD697, 0xC391, 0xD698, 0xC392, 0xD699, 0xC393, 0xD69A, 0xC394, 0xD69B, 0xC395, 0xD69C, 0xC396, 0xD69D, 0xC8BC, 0xD69E, 0xC397, 0xD69F, 0xC8BD, 0xD6A0, 0xC398, 0xD6A1, 0xC8BE, 0xD6A2, 0xC399, 0xD6A3, 0xC39A, 0xD6A4, 0xC39B, 0xD6A5, 0xC39C, 0xD6A6, 0xC39D, 0xD6A7, 0xC39E, 0xD6A8, 0xC8BF, 0xD6A9, 0xC39F, 0xD6AA, 0xC3A0, 0xD6AB, 0xC441, 0xD6AC, 0xC8C0, 0xD6AD, 0xC442, 0xD6AE, 0xC443, 0xD6AF, 0xC444, 0xD6B0, 0xC8C1, 0xD6B1, 0xC445, 0xD6B2, 0xC446, 0xD6B3, 0xC447, 0xD6B4, 0xC448, 0xD6B5, 0xC449, 0xD6B6, 0xC44A, 0xD6B7, 0xC44B, 0xD6B8, 0xC44C, 0xD6B9, 0xC8C2, 0xD6BA, 0xC44D, 0xD6BB, 0xC8C3, 0xD6BC, 0xC44E, 0xD6BD, 0xC44F, 0xD6BE, 0xC450, 0xD6BF, 0xC451, 0xD6C0, 0xC452, 0xD6C1, 0xC453, 0xD6C2, 0xC454, 0xD6C3, 0xC455, 0xD6C4, 0xC8C4, 0xD6C5, 0xC8C5, 0xD6C6, 0xC456, 0xD6C7, 0xC457, 0xD6C8, 0xC8C6, 0xD6C9, 0xC458, 0xD6CA, 0xC459, 0xD6CB, 0xC45A, 0xD6CC, 0xC8C7, 0xD6CD, 0xC461, 0xD6CE, 0xC462, 0xD6CF, 0xC463, 0xD6D0, 0xC464, 0xD6D1, 0xC8C8, 0xD6D2, 0xC465, 0xD6D3, 0xC466, 0xD6D4, 0xC8C9, 0xD6D5, 0xC467, 0xD6D6, 0xC468, 0xD6D7, 0xC8CA, 0xD6D8, 0xC469, 0xD6D9, 0xC8CB, 0xD6DA, 0xC46A, 0xD6DB, 0xC46B, 0xD6DC, 0xC46C, 0xD6DD, 0xC46D, 0xD6DE, 0xC46E, 0xD6DF, 0xC46F, 0xD6E0, 0xC8CC, 0xD6E1, 0xC470, 0xD6E2, 0xC471, 0xD6E3, 0xC472, 0xD6E4, 0xC8CD, 0xD6E5, 0xC473, 0xD6E6, 0xC474, 0xD6E7, 0xC475, 0xD6E8, 0xC8CE, 0xD6E9, 0xC476, 0xD6EA, 0xC477, 0xD6EB, 0xC478, 0xD6EC, 0xC479, 0xD6ED, 0xC47A, 0xD6EE, 0xC481, 0xD6EF, 0xC482, 0xD6F0, 0xC8CF, 0xD6F1, 0xC483, 0xD6F2, 0xC484, 0xD6F3, 0xC485, 0xD6F4, 0xC486, 0xD6F5, 0xC8D0, 0xD6F6, 0xC487, 0xD6F7, 0xC488, 0xD6F8, 0xC489, 0xD6F9, 0xC48A, 0xD6FA, 0xC48B, 0xD6FB, 0xC48C, 0xD6FC, 0xC8D1, 0xD6FD, 0xC8D2, 0xD6FE, 0xC48D, 0xD6FF, 0xC48E, 0xD700, 0xC8D3, 0xD701, 0xC48F, 0xD702, 0xC490, 0xD703, 0xC491, 0xD704, 0xC8D4, 0xD705, 0xC492, 0xD706, 0xC493, 0xD707, 0xC494, 0xD708, 0xC495, 0xD709, 0xC496, 0xD70A, 0xC497, 0xD70B, 0xC498, 0xD70C, 0xC499, 0xD70D, 0xC49A, 0xD70E, 0xC49B, 0xD70F, 0xC49C, 0xD710, 0xC49D, 0xD711, 0xC8D5, 0xD712, 0xC49E, 0xD713, 0xC49F, 0xD714, 0xC4A0, 0xD715, 0xC541, 0xD716, 0xC542, 0xD717, 0xC543, 0xD718, 0xC8D6, 0xD719, 0xC8D7, 0xD71A, 0xC544, 0xD71B, 0xC545, 0xD71C, 0xC8D8, 0xD71D, 0xC546, 0xD71E, 0xC547, 0xD71F, 0xC548, 0xD720, 0xC8D9, 0xD721, 0xC549, 0xD722, 0xC54A, 0xD723, 0xC54B, 0xD724, 0xC54C, 0xD725, 0xC54D, 0xD726, 0xC54E, 0xD727, 0xC54F, 0xD728, 0xC8DA, 0xD729, 0xC8DB, 0xD72A, 0xC550, 0xD72B, 0xC8DC, 0xD72C, 0xC551, 0xD72D, 0xC8DD, 0xD72E, 0xC552, 0xD72F, 0xC553, 0xD730, 0xC554, 0xD731, 0xC555, 0xD732, 0xC556, 0xD733, 0xC557, 0xD734, 0xC8DE, 0xD735, 0xC8DF, 0xD736, 0xC558, 0xD737, 0xC559, 0xD738, 0xC8E0, 0xD739, 0xC55A, 0xD73A, 0xC561, 0xD73B, 0xC562, 0xD73C, 0xC8E1, 0xD73D, 0xC563, 0xD73E, 0xC564, 0xD73F, 0xC565, 0xD740, 0xC566, 0xD741, 0xC567, 0xD742, 0xC568, 0xD743, 0xC569, 0xD744, 0xC8E2, 0xD745, 0xC56A, 0xD746, 0xC56B, 0xD747, 0xC8E3, 0xD748, 0xC56C, 0xD749, 0xC8E4, 0xD74A, 0xC56D, 0xD74B, 0xC56E, 0xD74C, 0xC56F, 0xD74D, 0xC570, 0xD74E, 0xC571, 0xD74F, 0xC572, 0xD750, 0xC8E5, 0xD751, 0xC8E6, 0xD752, 0xC573, 0xD753, 0xC574, 0xD754, 0xC8E7, 0xD755, 0xC575, 0xD756, 0xC8E8, 0xD757, 0xC8E9, 0xD758, 0xC8EA, 0xD759, 0xC8EB, 0xD75A, 0xC576, 0xD75B, 0xC577, 0xD75C, 0xC578, 0xD75D, 0xC579, 0xD75E, 0xC57A, 0xD75F, 0xC581, 0xD760, 0xC8EC, 0xD761, 0xC8ED, 0xD762, 0xC582, 0xD763, 0xC8EE, 0xD764, 0xC583, 0xD765, 0xC8EF, 0xD766, 0xC584, 0xD767, 0xC585, 0xD768, 0xC586, 0xD769, 0xC8F0, 0xD76A, 0xC587, 0xD76B, 0xC588, 0xD76C, 0xC8F1, 0xD76D, 0xC589, 0xD76E, 0xC58A, 0xD76F, 0xC58B, 0xD770, 0xC8F2, 0xD771, 0xC58C, 0xD772, 0xC58D, 0xD773, 0xC58E, 0xD774, 0xC8F3, 0xD775, 0xC58F, 0xD776, 0xC590, 0xD777, 0xC591, 0xD778, 0xC592, 0xD779, 0xC593, 0xD77A, 0xC594, 0xD77B, 0xC595, 0xD77C, 0xC8F4, 0xD77D, 0xC8F5, 0xD77E, 0xC596, 0xD77F, 0xC597, 0xD780, 0xC598, 0xD781, 0xC8F6, 0xD782, 0xC599, 0xD783, 0xC59A, 0xD784, 0xC59B, 0xD785, 0xC59C, 0xD786, 0xC59D, 0xD787, 0xC59E, 0xD788, 0xC8F7, 0xD789, 0xC8F8, 0xD78A, 0xC59F, 0xD78B, 0xC5A0, 0xD78C, 0xC8F9, 0xD78D, 0xC641, 0xD78E, 0xC642, 0xD78F, 0xC643, 0xD790, 0xC8FA, 0xD791, 0xC644, 0xD792, 0xC645, 0xD793, 0xC646, 0xD794, 0xC647, 0xD795, 0xC648, 0xD796, 0xC649, 0xD797, 0xC64A, 0xD798, 0xC8FB, 0xD799, 0xC8FC, 0xD79A, 0xC64B, 0xD79B, 0xC8FD, 0xD79C, 0xC64C, 0xD79D, 0xC8FE, 0xD79E, 0xC64D, 0xD79F, 0xC64E, 0xD7A0, 0xC64F, 0xD7A1, 0xC650, 0xD7A2, 0xC651, 0xD7A3, 0xC652, 0xF900, 0xCBD0, 0xF901, 0xCBD6, 0xF902, 0xCBE7, 0xF903, 0xCDCF, 0xF904, 0xCDE8, 0xF905, 0xCEAD, 0xF906, 0xCFFB, 0xF907, 0xD0A2, 0xF908, 0xD0B8, 0xF909, 0xD0D0, 0xF90A, 0xD0DD, 0xF90B, 0xD1D4, 0xF90C, 0xD1D5, 0xF90D, 0xD1D8, 0xF90E, 0xD1DB, 0xF90F, 0xD1DC, 0xF910, 0xD1DD, 0xF911, 0xD1DE, 0xF912, 0xD1DF, 0xF913, 0xD1E0, 0xF914, 0xD1E2, 0xF915, 0xD1E3, 0xF916, 0xD1E4, 0xF917, 0xD1E5, 0xF918, 0xD1E6, 0xF919, 0xD1E8, 0xF91A, 0xD1E9, 0xF91B, 0xD1EA, 0xF91C, 0xD1EB, 0xF91D, 0xD1ED, 0xF91E, 0xD1EF, 0xF91F, 0xD1F0, 0xF920, 0xD1F2, 0xF921, 0xD1F6, 0xF922, 0xD1FA, 0xF923, 0xD1FC, 0xF924, 0xD1FD, 0xF925, 0xD1FE, 0xF926, 0xD2A2, 0xF927, 0xD2A3, 0xF928, 0xD2A7, 0xF929, 0xD2A8, 0xF92A, 0xD2A9, 0xF92B, 0xD2AA, 0xF92C, 0xD2AB, 0xF92D, 0xD2AD, 0xF92E, 0xD2B2, 0xF92F, 0xD2BE, 0xF930, 0xD2C2, 0xF931, 0xD2C3, 0xF932, 0xD2C4, 0xF933, 0xD2C6, 0xF934, 0xD2C7, 0xF935, 0xD2C8, 0xF936, 0xD2C9, 0xF937, 0xD2CA, 0xF938, 0xD2CB, 0xF939, 0xD2CD, 0xF93A, 0xD2CE, 0xF93B, 0xD2CF, 0xF93C, 0xD2D0, 0xF93D, 0xD2D1, 0xF93E, 0xD2D2, 0xF93F, 0xD2D3, 0xF940, 0xD2D4, 0xF941, 0xD2D5, 0xF942, 0xD2D6, 0xF943, 0xD2D7, 0xF944, 0xD2D9, 0xF945, 0xD2DA, 0xF946, 0xD2DE, 0xF947, 0xD2DF, 0xF948, 0xD2E1, 0xF949, 0xD2E2, 0xF94A, 0xD2E4, 0xF94B, 0xD2E5, 0xF94C, 0xD2E6, 0xF94D, 0xD2E7, 0xF94E, 0xD2E8, 0xF94F, 0xD2E9, 0xF950, 0xD2EA, 0xF951, 0xD2EB, 0xF952, 0xD2F0, 0xF953, 0xD2F1, 0xF954, 0xD2F2, 0xF955, 0xD2F3, 0xF956, 0xD2F4, 0xF957, 0xD2F5, 0xF958, 0xD2F7, 0xF959, 0xD2F8, 0xF95A, 0xD4E6, 0xF95B, 0xD4FC, 0xF95C, 0xD5A5, 0xF95D, 0xD5AB, 0xF95E, 0xD5AE, 0xF95F, 0xD6B8, 0xF960, 0xD6CD, 0xF961, 0xD7CB, 0xF962, 0xD7E4, 0xF963, 0xDBC5, 0xF964, 0xDBE4, 0xF965, 0xDCA5, 0xF966, 0xDDA5, 0xF967, 0xDDD5, 0xF968, 0xDDF4, 0xF969, 0xDEFC, 0xF96A, 0xDEFE, 0xF96B, 0xDFB3, 0xF96C, 0xDFE1, 0xF96D, 0xDFE8, 0xF96E, 0xE0F1, 0xF96F, 0xE1AD, 0xF970, 0xE1ED, 0xF971, 0xE3F5, 0xF972, 0xE4A1, 0xF973, 0xE4A9, 0xF974, 0xE5AE, 0xF975, 0xE5B1, 0xF976, 0xE5B2, 0xF977, 0xE5B9, 0xF978, 0xE5BB, 0xF979, 0xE5BC, 0xF97A, 0xE5C4, 0xF97B, 0xE5CE, 0xF97C, 0xE5D0, 0xF97D, 0xE5D2, 0xF97E, 0xE5D6, 0xF97F, 0xE5FA, 0xF980, 0xE5FB, 0xF981, 0xE5FC, 0xF982, 0xE5FE, 0xF983, 0xE6A1, 0xF984, 0xE6A4, 0xF985, 0xE6A7, 0xF986, 0xE6AD, 0xF987, 0xE6AF, 0xF988, 0xE6B0, 0xF989, 0xE6B1, 0xF98A, 0xE6B3, 0xF98B, 0xE6B7, 0xF98C, 0xE6B8, 0xF98D, 0xE6BC, 0xF98E, 0xE6C4, 0xF98F, 0xE6C6, 0xF990, 0xE6C7, 0xF991, 0xE6CA, 0xF992, 0xE6D2, 0xF993, 0xE6D6, 0xF994, 0xE6D9, 0xF995, 0xE6DC, 0xF996, 0xE6DF, 0xF997, 0xE6E1, 0xF998, 0xE6E4, 0xF999, 0xE6E5, 0xF99A, 0xE6E6, 0xF99B, 0xE6E8, 0xF99C, 0xE6EA, 0xF99D, 0xE6EB, 0xF99E, 0xE6EC, 0xF99F, 0xE6EF, 0xF9A0, 0xE6F1, 0xF9A1, 0xE6F2, 0xF9A2, 0xE6F5, 0xF9A3, 0xE6F6, 0xF9A4, 0xE6F7, 0xF9A5, 0xE6F9, 0xF9A6, 0xE7A1, 0xF9A7, 0xE7A6, 0xF9A8, 0xE7A9, 0xF9A9, 0xE7AA, 0xF9AA, 0xE7AC, 0xF9AB, 0xE7AD, 0xF9AC, 0xE7B0, 0xF9AD, 0xE7BF, 0xF9AE, 0xE7C1, 0xF9AF, 0xE7C6, 0xF9B0, 0xE7C7, 0xF9B1, 0xE7CB, 0xF9B2, 0xE7CD, 0xF9B3, 0xE7CF, 0xF9B4, 0xE7D0, 0xF9B5, 0xE7D3, 0xF9B6, 0xE7DF, 0xF9B7, 0xE7E4, 0xF9B8, 0xE7E6, 0xF9B9, 0xE7F7, 0xF9BA, 0xE8E7, 0xF9BB, 0xE8E8, 0xF9BC, 0xE8F0, 0xF9BD, 0xE8F1, 0xF9BE, 0xE8F7, 0xF9BF, 0xE8F9, 0xF9C0, 0xE8FB, 0xF9C1, 0xE8FE, 0xF9C2, 0xE9A7, 0xF9C3, 0xE9AC, 0xF9C4, 0xE9CC, 0xF9C5, 0xE9F7, 0xF9C6, 0xEAC1, 0xF9C7, 0xEAE5, 0xF9C8, 0xEAF4, 0xF9C9, 0xEAF7, 0xF9CA, 0xEAFC, 0xF9CB, 0xEAFE, 0xF9CC, 0xEBA4, 0xF9CD, 0xEBA7, 0xF9CE, 0xEBA9, 0xF9CF, 0xEBAA, 0xF9D0, 0xEBBA, 0xF9D1, 0xEBBB, 0xF9D2, 0xEBBD, 0xF9D3, 0xEBC1, 0xF9D4, 0xEBC2, 0xF9D5, 0xEBC6, 0xF9D6, 0xEBC7, 0xF9D7, 0xEBCC, 0xF9D8, 0xEBCF, 0xF9D9, 0xEBD0, 0xF9DA, 0xEBD1, 0xF9DB, 0xEBD2, 0xF9DC, 0xEBD8, 0xF9DD, 0xECA6, 0xF9DE, 0xECA7, 0xF9DF, 0xECAA, 0xF9E0, 0xECAF, 0xF9E1, 0xECB0, 0xF9E2, 0xECB1, 0xF9E3, 0xECB2, 0xF9E4, 0xECB5, 0xF9E5, 0xECB8, 0xF9E6, 0xECBA, 0xF9E7, 0xECC0, 0xF9E8, 0xECC1, 0xF9E9, 0xECC5, 0xF9EA, 0xECC6, 0xF9EB, 0xECC9, 0xF9EC, 0xECCA, 0xF9ED, 0xECD5, 0xF9EE, 0xECDD, 0xF9EF, 0xECDE, 0xF9F0, 0xECE1, 0xF9F1, 0xECE4, 0xF9F2, 0xECE7, 0xF9F3, 0xECE8, 0xF9F4, 0xECF7, 0xF9F5, 0xECF8, 0xF9F6, 0xECFA, 0xF9F7, 0xEDA1, 0xF9F8, 0xEDA2, 0xF9F9, 0xEDA3, 0xF9FA, 0xEDEE, 0xF9FB, 0xEEDB, 0xF9FC, 0xF2BD, 0xF9FD, 0xF2FA, 0xF9FE, 0xF3B1, 0xF9FF, 0xF4A7, 0xFA00, 0xF4EE, 0xFA01, 0xF6F4, 0xFA02, 0xF6F6, 0xFA03, 0xF7B8, 0xFA04, 0xF7C8, 0xFA05, 0xF7D3, 0xFA06, 0xF8DB, 0xFA07, 0xF8F0, 0xFA08, 0xFAA1, 0xFA09, 0xFAA2, 0xFA0A, 0xFAE6, 0xFA0B, 0xFCA9, 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA3A4, 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA1AC, 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, 0xFF5D, 0xA3FD, 0xFF5E, 0xA2A6, 0xFFE0, 0xA1CB, 0xFFE1, 0xA1CC, 0xFFE2, 0xA1FE, 0xFFE3, 0xA3FE, 0xFFE5, 0xA1CD, 0xFFE6, 0xA3DC, 0, 0 }; static const WCHAR oem2uni949[] = { /* Korean --> Unicode pairs */ 0x8141, 0xAC02, 0x8142, 0xAC03, 0x8143, 0xAC05, 0x8144, 0xAC06, 0x8145, 0xAC0B, 0x8146, 0xAC0C, 0x8147, 0xAC0D, 0x8148, 0xAC0E, 0x8149, 0xAC0F, 0x814A, 0xAC18, 0x814B, 0xAC1E, 0x814C, 0xAC1F, 0x814D, 0xAC21, 0x814E, 0xAC22, 0x814F, 0xAC23, 0x8150, 0xAC25, 0x8151, 0xAC26, 0x8152, 0xAC27, 0x8153, 0xAC28, 0x8154, 0xAC29, 0x8155, 0xAC2A, 0x8156, 0xAC2B, 0x8157, 0xAC2E, 0x8158, 0xAC32, 0x8159, 0xAC33, 0x815A, 0xAC34, 0x8161, 0xAC35, 0x8162, 0xAC36, 0x8163, 0xAC37, 0x8164, 0xAC3A, 0x8165, 0xAC3B, 0x8166, 0xAC3D, 0x8167, 0xAC3E, 0x8168, 0xAC3F, 0x8169, 0xAC41, 0x816A, 0xAC42, 0x816B, 0xAC43, 0x816C, 0xAC44, 0x816D, 0xAC45, 0x816E, 0xAC46, 0x816F, 0xAC47, 0x8170, 0xAC48, 0x8171, 0xAC49, 0x8172, 0xAC4A, 0x8173, 0xAC4C, 0x8174, 0xAC4E, 0x8175, 0xAC4F, 0x8176, 0xAC50, 0x8177, 0xAC51, 0x8178, 0xAC52, 0x8179, 0xAC53, 0x817A, 0xAC55, 0x8181, 0xAC56, 0x8182, 0xAC57, 0x8183, 0xAC59, 0x8184, 0xAC5A, 0x8185, 0xAC5B, 0x8186, 0xAC5D, 0x8187, 0xAC5E, 0x8188, 0xAC5F, 0x8189, 0xAC60, 0x818A, 0xAC61, 0x818B, 0xAC62, 0x818C, 0xAC63, 0x818D, 0xAC64, 0x818E, 0xAC65, 0x818F, 0xAC66, 0x8190, 0xAC67, 0x8191, 0xAC68, 0x8192, 0xAC69, 0x8193, 0xAC6A, 0x8194, 0xAC6B, 0x8195, 0xAC6C, 0x8196, 0xAC6D, 0x8197, 0xAC6E, 0x8198, 0xAC6F, 0x8199, 0xAC72, 0x819A, 0xAC73, 0x819B, 0xAC75, 0x819C, 0xAC76, 0x819D, 0xAC79, 0x819E, 0xAC7B, 0x819F, 0xAC7C, 0x81A0, 0xAC7D, 0x81A1, 0xAC7E, 0x81A2, 0xAC7F, 0x81A3, 0xAC82, 0x81A4, 0xAC87, 0x81A5, 0xAC88, 0x81A6, 0xAC8D, 0x81A7, 0xAC8E, 0x81A8, 0xAC8F, 0x81A9, 0xAC91, 0x81AA, 0xAC92, 0x81AB, 0xAC93, 0x81AC, 0xAC95, 0x81AD, 0xAC96, 0x81AE, 0xAC97, 0x81AF, 0xAC98, 0x81B0, 0xAC99, 0x81B1, 0xAC9A, 0x81B2, 0xAC9B, 0x81B3, 0xAC9E, 0x81B4, 0xACA2, 0x81B5, 0xACA3, 0x81B6, 0xACA4, 0x81B7, 0xACA5, 0x81B8, 0xACA6, 0x81B9, 0xACA7, 0x81BA, 0xACAB, 0x81BB, 0xACAD, 0x81BC, 0xACAE, 0x81BD, 0xACB1, 0x81BE, 0xACB2, 0x81BF, 0xACB3, 0x81C0, 0xACB4, 0x81C1, 0xACB5, 0x81C2, 0xACB6, 0x81C3, 0xACB7, 0x81C4, 0xACBA, 0x81C5, 0xACBE, 0x81C6, 0xACBF, 0x81C7, 0xACC0, 0x81C8, 0xACC2, 0x81C9, 0xACC3, 0x81CA, 0xACC5, 0x81CB, 0xACC6, 0x81CC, 0xACC7, 0x81CD, 0xACC9, 0x81CE, 0xACCA, 0x81CF, 0xACCB, 0x81D0, 0xACCD, 0x81D1, 0xACCE, 0x81D2, 0xACCF, 0x81D3, 0xACD0, 0x81D4, 0xACD1, 0x81D5, 0xACD2, 0x81D6, 0xACD3, 0x81D7, 0xACD4, 0x81D8, 0xACD6, 0x81D9, 0xACD8, 0x81DA, 0xACD9, 0x81DB, 0xACDA, 0x81DC, 0xACDB, 0x81DD, 0xACDC, 0x81DE, 0xACDD, 0x81DF, 0xACDE, 0x81E0, 0xACDF, 0x81E1, 0xACE2, 0x81E2, 0xACE3, 0x81E3, 0xACE5, 0x81E4, 0xACE6, 0x81E5, 0xACE9, 0x81E6, 0xACEB, 0x81E7, 0xACED, 0x81E8, 0xACEE, 0x81E9, 0xACF2, 0x81EA, 0xACF4, 0x81EB, 0xACF7, 0x81EC, 0xACF8, 0x81ED, 0xACF9, 0x81EE, 0xACFA, 0x81EF, 0xACFB, 0x81F0, 0xACFE, 0x81F1, 0xACFF, 0x81F2, 0xAD01, 0x81F3, 0xAD02, 0x81F4, 0xAD03, 0x81F5, 0xAD05, 0x81F6, 0xAD07, 0x81F7, 0xAD08, 0x81F8, 0xAD09, 0x81F9, 0xAD0A, 0x81FA, 0xAD0B, 0x81FB, 0xAD0E, 0x81FC, 0xAD10, 0x81FD, 0xAD12, 0x81FE, 0xAD13, 0x8241, 0xAD14, 0x8242, 0xAD15, 0x8243, 0xAD16, 0x8244, 0xAD17, 0x8245, 0xAD19, 0x8246, 0xAD1A, 0x8247, 0xAD1B, 0x8248, 0xAD1D, 0x8249, 0xAD1E, 0x824A, 0xAD1F, 0x824B, 0xAD21, 0x824C, 0xAD22, 0x824D, 0xAD23, 0x824E, 0xAD24, 0x824F, 0xAD25, 0x8250, 0xAD26, 0x8251, 0xAD27, 0x8252, 0xAD28, 0x8253, 0xAD2A, 0x8254, 0xAD2B, 0x8255, 0xAD2E, 0x8256, 0xAD2F, 0x8257, 0xAD30, 0x8258, 0xAD31, 0x8259, 0xAD32, 0x825A, 0xAD33, 0x8261, 0xAD36, 0x8262, 0xAD37, 0x8263, 0xAD39, 0x8264, 0xAD3A, 0x8265, 0xAD3B, 0x8266, 0xAD3D, 0x8267, 0xAD3E, 0x8268, 0xAD3F, 0x8269, 0xAD40, 0x826A, 0xAD41, 0x826B, 0xAD42, 0x826C, 0xAD43, 0x826D, 0xAD46, 0x826E, 0xAD48, 0x826F, 0xAD4A, 0x8270, 0xAD4B, 0x8271, 0xAD4C, 0x8272, 0xAD4D, 0x8273, 0xAD4E, 0x8274, 0xAD4F, 0x8275, 0xAD51, 0x8276, 0xAD52, 0x8277, 0xAD53, 0x8278, 0xAD55, 0x8279, 0xAD56, 0x827A, 0xAD57, 0x8281, 0xAD59, 0x8282, 0xAD5A, 0x8283, 0xAD5B, 0x8284, 0xAD5C, 0x8285, 0xAD5D, 0x8286, 0xAD5E, 0x8287, 0xAD5F, 0x8288, 0xAD60, 0x8289, 0xAD62, 0x828A, 0xAD64, 0x828B, 0xAD65, 0x828C, 0xAD66, 0x828D, 0xAD67, 0x828E, 0xAD68, 0x828F, 0xAD69, 0x8290, 0xAD6A, 0x8291, 0xAD6B, 0x8292, 0xAD6E, 0x8293, 0xAD6F, 0x8294, 0xAD71, 0x8295, 0xAD72, 0x8296, 0xAD77, 0x8297, 0xAD78, 0x8298, 0xAD79, 0x8299, 0xAD7A, 0x829A, 0xAD7E, 0x829B, 0xAD80, 0x829C, 0xAD83, 0x829D, 0xAD84, 0x829E, 0xAD85, 0x829F, 0xAD86, 0x82A0, 0xAD87, 0x82A1, 0xAD8A, 0x82A2, 0xAD8B, 0x82A3, 0xAD8D, 0x82A4, 0xAD8E, 0x82A5, 0xAD8F, 0x82A6, 0xAD91, 0x82A7, 0xAD92, 0x82A8, 0xAD93, 0x82A9, 0xAD94, 0x82AA, 0xAD95, 0x82AB, 0xAD96, 0x82AC, 0xAD97, 0x82AD, 0xAD98, 0x82AE, 0xAD99, 0x82AF, 0xAD9A, 0x82B0, 0xAD9B, 0x82B1, 0xAD9E, 0x82B2, 0xAD9F, 0x82B3, 0xADA0, 0x82B4, 0xADA1, 0x82B5, 0xADA2, 0x82B6, 0xADA3, 0x82B7, 0xADA5, 0x82B8, 0xADA6, 0x82B9, 0xADA7, 0x82BA, 0xADA8, 0x82BB, 0xADA9, 0x82BC, 0xADAA, 0x82BD, 0xADAB, 0x82BE, 0xADAC, 0x82BF, 0xADAD, 0x82C0, 0xADAE, 0x82C1, 0xADAF, 0x82C2, 0xADB0, 0x82C3, 0xADB1, 0x82C4, 0xADB2, 0x82C5, 0xADB3, 0x82C6, 0xADB4, 0x82C7, 0xADB5, 0x82C8, 0xADB6, 0x82C9, 0xADB8, 0x82CA, 0xADB9, 0x82CB, 0xADBA, 0x82CC, 0xADBB, 0x82CD, 0xADBC, 0x82CE, 0xADBD, 0x82CF, 0xADBE, 0x82D0, 0xADBF, 0x82D1, 0xADC2, 0x82D2, 0xADC3, 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0xAE15, 0x8354, 0xAE16, 0x8355, 0xAE17, 0x8356, 0xAE18, 0x8357, 0xAE19, 0x8358, 0xAE1A, 0x8359, 0xAE1B, 0x835A, 0xAE1C, 0x8361, 0xAE1D, 0x8362, 0xAE1E, 0x8363, 0xAE1F, 0x8364, 0xAE20, 0x8365, 0xAE21, 0x8366, 0xAE22, 0x8367, 0xAE23, 0x8368, 0xAE24, 0x8369, 0xAE25, 0x836A, 0xAE26, 0x836B, 0xAE27, 0x836C, 0xAE28, 0x836D, 0xAE29, 0x836E, 0xAE2A, 0x836F, 0xAE2B, 0x8370, 0xAE2C, 0x8371, 0xAE2D, 0x8372, 0xAE2E, 0x8373, 0xAE2F, 0x8374, 0xAE32, 0x8375, 0xAE33, 0x8376, 0xAE35, 0x8377, 0xAE36, 0x8378, 0xAE39, 0x8379, 0xAE3B, 0x837A, 0xAE3C, 0x8381, 0xAE3D, 0x8382, 0xAE3E, 0x8383, 0xAE3F, 0x8384, 0xAE42, 0x8385, 0xAE44, 0x8386, 0xAE47, 0x8387, 0xAE48, 0x8388, 0xAE49, 0x8389, 0xAE4B, 0x838A, 0xAE4F, 0x838B, 0xAE51, 0x838C, 0xAE52, 0x838D, 0xAE53, 0x838E, 0xAE55, 0x838F, 0xAE57, 0x8390, 0xAE58, 0x8391, 0xAE59, 0x8392, 0xAE5A, 0x8393, 0xAE5B, 0x8394, 0xAE5E, 0x8395, 0xAE62, 0x8396, 0xAE63, 0x8397, 0xAE64, 0x8398, 0xAE66, 0x8399, 0xAE67, 0x839A, 0xAE6A, 0x839B, 0xAE6B, 0x839C, 0xAE6D, 0x839D, 0xAE6E, 0x839E, 0xAE6F, 0x839F, 0xAE71, 0x83A0, 0xAE72, 0x83A1, 0xAE73, 0x83A2, 0xAE74, 0x83A3, 0xAE75, 0x83A4, 0xAE76, 0x83A5, 0xAE77, 0x83A6, 0xAE7A, 0x83A7, 0xAE7E, 0x83A8, 0xAE7F, 0x83A9, 0xAE80, 0x83AA, 0xAE81, 0x83AB, 0xAE82, 0x83AC, 0xAE83, 0x83AD, 0xAE86, 0x83AE, 0xAE87, 0x83AF, 0xAE88, 0x83B0, 0xAE89, 0x83B1, 0xAE8A, 0x83B2, 0xAE8B, 0x83B3, 0xAE8D, 0x83B4, 0xAE8E, 0x83B5, 0xAE8F, 0x83B6, 0xAE90, 0x83B7, 0xAE91, 0x83B8, 0xAE92, 0x83B9, 0xAE93, 0x83BA, 0xAE94, 0x83BB, 0xAE95, 0x83BC, 0xAE96, 0x83BD, 0xAE97, 0x83BE, 0xAE98, 0x83BF, 0xAE99, 0x83C0, 0xAE9A, 0x83C1, 0xAE9B, 0x83C2, 0xAE9C, 0x83C3, 0xAE9D, 0x83C4, 0xAE9E, 0x83C5, 0xAE9F, 0x83C6, 0xAEA0, 0x83C7, 0xAEA1, 0x83C8, 0xAEA2, 0x83C9, 0xAEA3, 0x83CA, 0xAEA4, 0x83CB, 0xAEA5, 0x83CC, 0xAEA6, 0x83CD, 0xAEA7, 0x83CE, 0xAEA8, 0x83CF, 0xAEA9, 0x83D0, 0xAEAA, 0x83D1, 0xAEAB, 0x83D2, 0xAEAC, 0x83D3, 0xAEAD, 0x83D4, 0xAEAE, 0x83D5, 0xAEAF, 0x83D6, 0xAEB0, 0x83D7, 0xAEB1, 0x83D8, 0xAEB2, 0x83D9, 0xAEB3, 0x83DA, 0xAEB4, 0x83DB, 0xAEB5, 0x83DC, 0xAEB6, 0x83DD, 0xAEB7, 0x83DE, 0xAEB8, 0x83DF, 0xAEB9, 0x83E0, 0xAEBA, 0x83E1, 0xAEBB, 0x83E2, 0xAEBF, 0x83E3, 0xAEC1, 0x83E4, 0xAEC2, 0x83E5, 0xAEC3, 0x83E6, 0xAEC5, 0x83E7, 0xAEC6, 0x83E8, 0xAEC7, 0x83E9, 0xAEC8, 0x83EA, 0xAEC9, 0x83EB, 0xAECA, 0x83EC, 0xAECB, 0x83ED, 0xAECE, 0x83EE, 0xAED2, 0x83EF, 0xAED3, 0x83F0, 0xAED4, 0x83F1, 0xAED5, 0x83F2, 0xAED6, 0x83F3, 0xAED7, 0x83F4, 0xAEDA, 0x83F5, 0xAEDB, 0x83F6, 0xAEDD, 0x83F7, 0xAEDE, 0x83F8, 0xAEDF, 0x83F9, 0xAEE0, 0x83FA, 0xAEE1, 0x83FB, 0xAEE2, 0x83FC, 0xAEE3, 0x83FD, 0xAEE4, 0x83FE, 0xAEE5, 0x8441, 0xAEE6, 0x8442, 0xAEE7, 0x8443, 0xAEE9, 0x8444, 0xAEEA, 0x8445, 0xAEEC, 0x8446, 0xAEEE, 0x8447, 0xAEEF, 0x8448, 0xAEF0, 0x8449, 0xAEF1, 0x844A, 0xAEF2, 0x844B, 0xAEF3, 0x844C, 0xAEF5, 0x844D, 0xAEF6, 0x844E, 0xAEF7, 0x844F, 0xAEF9, 0x8450, 0xAEFA, 0x8451, 0xAEFB, 0x8452, 0xAEFD, 0x8453, 0xAEFE, 0x8454, 0xAEFF, 0x8455, 0xAF00, 0x8456, 0xAF01, 0x8457, 0xAF02, 0x8458, 0xAF03, 0x8459, 0xAF04, 0x845A, 0xAF05, 0x8461, 0xAF06, 0x8462, 0xAF09, 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0x888F, 0xB2C6, 0x8890, 0xB2C7, 0x8891, 0xB2CA, 0x8892, 0xB2CB, 0x8893, 0xB2CD, 0x8894, 0xB2CE, 0x8895, 0xB2CF, 0x8896, 0xB2D1, 0x8897, 0xB2D3, 0x8898, 0xB2D4, 0x8899, 0xB2D5, 0x889A, 0xB2D6, 0x889B, 0xB2D7, 0x889C, 0xB2DA, 0x889D, 0xB2DC, 0x889E, 0xB2DE, 0x889F, 0xB2DF, 0x88A0, 0xB2E0, 0x88A1, 0xB2E1, 0x88A2, 0xB2E3, 0x88A3, 0xB2E7, 0x88A4, 0xB2E9, 0x88A5, 0xB2EA, 0x88A6, 0xB2F0, 0x88A7, 0xB2F1, 0x88A8, 0xB2F2, 0x88A9, 0xB2F6, 0x88AA, 0xB2FC, 0x88AB, 0xB2FD, 0x88AC, 0xB2FE, 0x88AD, 0xB302, 0x88AE, 0xB303, 0x88AF, 0xB305, 0x88B0, 0xB306, 0x88B1, 0xB307, 0x88B2, 0xB309, 0x88B3, 0xB30A, 0x88B4, 0xB30B, 0x88B5, 0xB30C, 0x88B6, 0xB30D, 0x88B7, 0xB30E, 0x88B8, 0xB30F, 0x88B9, 0xB312, 0x88BA, 0xB316, 0x88BB, 0xB317, 0x88BC, 0xB318, 0x88BD, 0xB319, 0x88BE, 0xB31A, 0x88BF, 0xB31B, 0x88C0, 0xB31D, 0x88C1, 0xB31E, 0x88C2, 0xB31F, 0x88C3, 0xB320, 0x88C4, 0xB321, 0x88C5, 0xB322, 0x88C6, 0xB323, 0x88C7, 0xB324, 0x88C8, 0xB325, 0x88C9, 0xB326, 0x88CA, 0xB327, 0x88CB, 0xB328, 0x88CC, 0xB329, 0x88CD, 0xB32A, 0x88CE, 0xB32B, 0x88CF, 0xB32C, 0x88D0, 0xB32D, 0x88D1, 0xB32E, 0x88D2, 0xB32F, 0x88D3, 0xB330, 0x88D4, 0xB331, 0x88D5, 0xB332, 0x88D6, 0xB333, 0x88D7, 0xB334, 0x88D8, 0xB335, 0x88D9, 0xB336, 0x88DA, 0xB337, 0x88DB, 0xB338, 0x88DC, 0xB339, 0x88DD, 0xB33A, 0x88DE, 0xB33B, 0x88DF, 0xB33C, 0x88E0, 0xB33D, 0x88E1, 0xB33E, 0x88E2, 0xB33F, 0x88E3, 0xB340, 0x88E4, 0xB341, 0x88E5, 0xB342, 0x88E6, 0xB343, 0x88E7, 0xB344, 0x88E8, 0xB345, 0x88E9, 0xB346, 0x88EA, 0xB347, 0x88EB, 0xB348, 0x88EC, 0xB349, 0x88ED, 0xB34A, 0x88EE, 0xB34B, 0x88EF, 0xB34C, 0x88F0, 0xB34D, 0x88F1, 0xB34E, 0x88F2, 0xB34F, 0x88F3, 0xB350, 0x88F4, 0xB351, 0x88F5, 0xB352, 0x88F6, 0xB353, 0x88F7, 0xB357, 0x88F8, 0xB359, 0x88F9, 0xB35A, 0x88FA, 0xB35D, 0x88FB, 0xB360, 0x88FC, 0xB361, 0x88FD, 0xB362, 0x88FE, 0xB363, 0x8941, 0xB366, 0x8942, 0xB368, 0x8943, 0xB36A, 0x8944, 0xB36C, 0x8945, 0xB36D, 0x8946, 0xB36F, 0x8947, 0xB372, 0x8948, 0xB373, 0x8949, 0xB375, 0x894A, 0xB376, 0x894B, 0xB377, 0x894C, 0xB379, 0x894D, 0xB37A, 0x894E, 0xB37B, 0x894F, 0xB37C, 0x8950, 0xB37D, 0x8951, 0xB37E, 0x8952, 0xB37F, 0x8953, 0xB382, 0x8954, 0xB386, 0x8955, 0xB387, 0x8956, 0xB388, 0x8957, 0xB389, 0x8958, 0xB38A, 0x8959, 0xB38B, 0x895A, 0xB38D, 0x8961, 0xB38E, 0x8962, 0xB38F, 0x8963, 0xB391, 0x8964, 0xB392, 0x8965, 0xB393, 0x8966, 0xB395, 0x8967, 0xB396, 0x8968, 0xB397, 0x8969, 0xB398, 0x896A, 0xB399, 0x896B, 0xB39A, 0x896C, 0xB39B, 0x896D, 0xB39C, 0x896E, 0xB39D, 0x896F, 0xB39E, 0x8970, 0xB39F, 0x8971, 0xB3A2, 0x8972, 0xB3A3, 0x8973, 0xB3A4, 0x8974, 0xB3A5, 0x8975, 0xB3A6, 0x8976, 0xB3A7, 0x8977, 0xB3A9, 0x8978, 0xB3AA, 0x8979, 0xB3AB, 0x897A, 0xB3AD, 0x8981, 0xB3AE, 0x8982, 0xB3AF, 0x8983, 0xB3B0, 0x8984, 0xB3B1, 0x8985, 0xB3B2, 0x8986, 0xB3B3, 0x8987, 0xB3B4, 0x8988, 0xB3B5, 0x8989, 0xB3B6, 0x898A, 0xB3B7, 0x898B, 0xB3B8, 0x898C, 0xB3B9, 0x898D, 0xB3BA, 0x898E, 0xB3BB, 0x898F, 0xB3BC, 0x8990, 0xB3BD, 0x8991, 0xB3BE, 0x8992, 0xB3BF, 0x8993, 0xB3C0, 0x8994, 0xB3C1, 0x8995, 0xB3C2, 0x8996, 0xB3C3, 0x8997, 0xB3C6, 0x8998, 0xB3C7, 0x8999, 0xB3C9, 0x899A, 0xB3CA, 0x899B, 0xB3CD, 0x899C, 0xB3CF, 0x899D, 0xB3D1, 0x899E, 0xB3D2, 0x899F, 0xB3D3, 0x89A0, 0xB3D6, 0x89A1, 0xB3D8, 0x89A2, 0xB3DA, 0x89A3, 0xB3DC, 0x89A4, 0xB3DE, 0x89A5, 0xB3DF, 0x89A6, 0xB3E1, 0x89A7, 0xB3E2, 0x89A8, 0xB3E3, 0x89A9, 0xB3E5, 0x89AA, 0xB3E6, 0x89AB, 0xB3E7, 0x89AC, 0xB3E9, 0x89AD, 0xB3EA, 0x89AE, 0xB3EB, 0x89AF, 0xB3EC, 0x89B0, 0xB3ED, 0x89B1, 0xB3EE, 0x89B2, 0xB3EF, 0x89B3, 0xB3F0, 0x89B4, 0xB3F1, 0x89B5, 0xB3F2, 0x89B6, 0xB3F3, 0x89B7, 0xB3F4, 0x89B8, 0xB3F5, 0x89B9, 0xB3F6, 0x89BA, 0xB3F7, 0x89BB, 0xB3F8, 0x89BC, 0xB3F9, 0x89BD, 0xB3FA, 0x89BE, 0xB3FB, 0x89BF, 0xB3FD, 0x89C0, 0xB3FE, 0x89C1, 0xB3FF, 0x89C2, 0xB400, 0x89C3, 0xB401, 0x89C4, 0xB402, 0x89C5, 0xB403, 0x89C6, 0xB404, 0x89C7, 0xB405, 0x89C8, 0xB406, 0x89C9, 0xB407, 0x89CA, 0xB408, 0x89CB, 0xB409, 0x89CC, 0xB40A, 0x89CD, 0xB40B, 0x89CE, 0xB40C, 0x89CF, 0xB40D, 0x89D0, 0xB40E, 0x89D1, 0xB40F, 0x89D2, 0xB411, 0x89D3, 0xB412, 0x89D4, 0xB413, 0x89D5, 0xB414, 0x89D6, 0xB415, 0x89D7, 0xB416, 0x89D8, 0xB417, 0x89D9, 0xB419, 0x89DA, 0xB41A, 0x89DB, 0xB41B, 0x89DC, 0xB41D, 0x89DD, 0xB41E, 0x89DE, 0xB41F, 0x89DF, 0xB421, 0x89E0, 0xB422, 0x89E1, 0xB423, 0x89E2, 0xB424, 0x89E3, 0xB425, 0x89E4, 0xB426, 0x89E5, 0xB427, 0x89E6, 0xB42A, 0x89E7, 0xB42C, 0x89E8, 0xB42D, 0x89E9, 0xB42E, 0x89EA, 0xB42F, 0x89EB, 0xB430, 0x89EC, 0xB431, 0x89ED, 0xB432, 0x89EE, 0xB433, 0x89EF, 0xB435, 0x89F0, 0xB436, 0x89F1, 0xB437, 0x89F2, 0xB438, 0x89F3, 0xB439, 0x89F4, 0xB43A, 0x89F5, 0xB43B, 0x89F6, 0xB43C, 0x89F7, 0xB43D, 0x89F8, 0xB43E, 0x89F9, 0xB43F, 0x89FA, 0xB440, 0x89FB, 0xB441, 0x89FC, 0xB442, 0x89FD, 0xB443, 0x89FE, 0xB444, 0x8A41, 0xB445, 0x8A42, 0xB446, 0x8A43, 0xB447, 0x8A44, 0xB448, 0x8A45, 0xB449, 0x8A46, 0xB44A, 0x8A47, 0xB44B, 0x8A48, 0xB44C, 0x8A49, 0xB44D, 0x8A4A, 0xB44E, 0x8A4B, 0xB44F, 0x8A4C, 0xB452, 0x8A4D, 0xB453, 0x8A4E, 0xB455, 0x8A4F, 0xB456, 0x8A50, 0xB457, 0x8A51, 0xB459, 0x8A52, 0xB45A, 0x8A53, 0xB45B, 0x8A54, 0xB45C, 0x8A55, 0xB45D, 0x8A56, 0xB45E, 0x8A57, 0xB45F, 0x8A58, 0xB462, 0x8A59, 0xB464, 0x8A5A, 0xB466, 0x8A61, 0xB467, 0x8A62, 0xB468, 0x8A63, 0xB469, 0x8A64, 0xB46A, 0x8A65, 0xB46B, 0x8A66, 0xB46D, 0x8A67, 0xB46E, 0x8A68, 0xB46F, 0x8A69, 0xB470, 0x8A6A, 0xB471, 0x8A6B, 0xB472, 0x8A6C, 0xB473, 0x8A6D, 0xB474, 0x8A6E, 0xB475, 0x8A6F, 0xB476, 0x8A70, 0xB477, 0x8A71, 0xB478, 0x8A72, 0xB479, 0x8A73, 0xB47A, 0x8A74, 0xB47B, 0x8A75, 0xB47C, 0x8A76, 0xB47D, 0x8A77, 0xB47E, 0x8A78, 0xB47F, 0x8A79, 0xB481, 0x8A7A, 0xB482, 0x8A81, 0xB483, 0x8A82, 0xB484, 0x8A83, 0xB485, 0x8A84, 0xB486, 0x8A85, 0xB487, 0x8A86, 0xB489, 0x8A87, 0xB48A, 0x8A88, 0xB48B, 0x8A89, 0xB48C, 0x8A8A, 0xB48D, 0x8A8B, 0xB48E, 0x8A8C, 0xB48F, 0x8A8D, 0xB490, 0x8A8E, 0xB491, 0x8A8F, 0xB492, 0x8A90, 0xB493, 0x8A91, 0xB494, 0x8A92, 0xB495, 0x8A93, 0xB496, 0x8A94, 0xB497, 0x8A95, 0xB498, 0x8A96, 0xB499, 0x8A97, 0xB49A, 0x8A98, 0xB49B, 0x8A99, 0xB49C, 0x8A9A, 0xB49E, 0x8A9B, 0xB49F, 0x8A9C, 0xB4A0, 0x8A9D, 0xB4A1, 0x8A9E, 0xB4A2, 0x8A9F, 0xB4A3, 0x8AA0, 0xB4A5, 0x8AA1, 0xB4A6, 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0xB18E, 0xCF52, 0xB18F, 0xCF53, 0xB190, 0xCF56, 0xB191, 0xCF57, 0xB192, 0xCF59, 0xB193, 0xCF5A, 0xB194, 0xCF5B, 0xB195, 0xCF5D, 0xB196, 0xCF5E, 0xB197, 0xCF5F, 0xB198, 0xCF60, 0xB199, 0xCF61, 0xB19A, 0xCF62, 0xB19B, 0xCF63, 0xB19C, 0xCF66, 0xB19D, 0xCF68, 0xB19E, 0xCF6A, 0xB19F, 0xCF6B, 0xB1A0, 0xCF6C, 0xB1A1, 0xAD0C, 0xB1A2, 0xAD0D, 0xB1A3, 0xAD0F, 0xB1A4, 0xAD11, 0xB1A5, 0xAD18, 0xB1A6, 0xAD1C, 0xB1A7, 0xAD20, 0xB1A8, 0xAD29, 0xB1A9, 0xAD2C, 0xB1AA, 0xAD2D, 0xB1AB, 0xAD34, 0xB1AC, 0xAD35, 0xB1AD, 0xAD38, 0xB1AE, 0xAD3C, 0xB1AF, 0xAD44, 0xB1B0, 0xAD45, 0xB1B1, 0xAD47, 0xB1B2, 0xAD49, 0xB1B3, 0xAD50, 0xB1B4, 0xAD54, 0xB1B5, 0xAD58, 0xB1B6, 0xAD61, 0xB1B7, 0xAD63, 0xB1B8, 0xAD6C, 0xB1B9, 0xAD6D, 0xB1BA, 0xAD70, 0xB1BB, 0xAD73, 0xB1BC, 0xAD74, 0xB1BD, 0xAD75, 0xB1BE, 0xAD76, 0xB1BF, 0xAD7B, 0xB1C0, 0xAD7C, 0xB1C1, 0xAD7D, 0xB1C2, 0xAD7F, 0xB1C3, 0xAD81, 0xB1C4, 0xAD82, 0xB1C5, 0xAD88, 0xB1C6, 0xAD89, 0xB1C7, 0xAD8C, 0xB1C8, 0xAD90, 0xB1C9, 0xAD9C, 0xB1CA, 0xAD9D, 0xB1CB, 0xADA4, 0xB1CC, 0xADB7, 0xB1CD, 0xADC0, 0xB1CE, 0xADC1, 0xB1CF, 0xADC4, 0xB1D0, 0xADC8, 0xB1D1, 0xADD0, 0xB1D2, 0xADD1, 0xB1D3, 0xADD3, 0xB1D4, 0xADDC, 0xB1D5, 0xADE0, 0xB1D6, 0xADE4, 0xB1D7, 0xADF8, 0xB1D8, 0xADF9, 0xB1D9, 0xADFC, 0xB1DA, 0xADFF, 0xB1DB, 0xAE00, 0xB1DC, 0xAE01, 0xB1DD, 0xAE08, 0xB1DE, 0xAE09, 0xB1DF, 0xAE0B, 0xB1E0, 0xAE0D, 0xB1E1, 0xAE14, 0xB1E2, 0xAE30, 0xB1E3, 0xAE31, 0xB1E4, 0xAE34, 0xB1E5, 0xAE37, 0xB1E6, 0xAE38, 0xB1E7, 0xAE3A, 0xB1E8, 0xAE40, 0xB1E9, 0xAE41, 0xB1EA, 0xAE43, 0xB1EB, 0xAE45, 0xB1EC, 0xAE46, 0xB1ED, 0xAE4A, 0xB1EE, 0xAE4C, 0xB1EF, 0xAE4D, 0xB1F0, 0xAE4E, 0xB1F1, 0xAE50, 0xB1F2, 0xAE54, 0xB1F3, 0xAE56, 0xB1F4, 0xAE5C, 0xB1F5, 0xAE5D, 0xB1F6, 0xAE5F, 0xB1F7, 0xAE60, 0xB1F8, 0xAE61, 0xB1F9, 0xAE65, 0xB1FA, 0xAE68, 0xB1FB, 0xAE69, 0xB1FC, 0xAE6C, 0xB1FD, 0xAE70, 0xB1FE, 0xAE78, 0xB241, 0xCF6D, 0xB242, 0xCF6E, 0xB243, 0xCF6F, 0xB244, 0xCF72, 0xB245, 0xCF73, 0xB246, 0xCF75, 0xB247, 0xCF76, 0xB248, 0xCF77, 0xB249, 0xCF79, 0xB24A, 0xCF7A, 0xB24B, 0xCF7B, 0xB24C, 0xCF7C, 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0xCFC1, 0xB298, 0xCFC2, 0xB299, 0xCFC3, 0xB29A, 0xCFC5, 0xB29B, 0xCFC6, 0xB29C, 0xCFC7, 0xB29D, 0xCFC8, 0xB29E, 0xCFC9, 0xB29F, 0xCFCA, 0xB2A0, 0xCFCB, 0xB2A1, 0xAE79, 0xB2A2, 0xAE7B, 0xB2A3, 0xAE7C, 0xB2A4, 0xAE7D, 0xB2A5, 0xAE84, 0xB2A6, 0xAE85, 0xB2A7, 0xAE8C, 0xB2A8, 0xAEBC, 0xB2A9, 0xAEBD, 0xB2AA, 0xAEBE, 0xB2AB, 0xAEC0, 0xB2AC, 0xAEC4, 0xB2AD, 0xAECC, 0xB2AE, 0xAECD, 0xB2AF, 0xAECF, 0xB2B0, 0xAED0, 0xB2B1, 0xAED1, 0xB2B2, 0xAED8, 0xB2B3, 0xAED9, 0xB2B4, 0xAEDC, 0xB2B5, 0xAEE8, 0xB2B6, 0xAEEB, 0xB2B7, 0xAEED, 0xB2B8, 0xAEF4, 0xB2B9, 0xAEF8, 0xB2BA, 0xAEFC, 0xB2BB, 0xAF07, 0xB2BC, 0xAF08, 0xB2BD, 0xAF0D, 0xB2BE, 0xAF10, 0xB2BF, 0xAF2C, 0xB2C0, 0xAF2D, 0xB2C1, 0xAF30, 0xB2C2, 0xAF32, 0xB2C3, 0xAF34, 0xB2C4, 0xAF3C, 0xB2C5, 0xAF3D, 0xB2C6, 0xAF3F, 0xB2C7, 0xAF41, 0xB2C8, 0xAF42, 0xB2C9, 0xAF43, 0xB2CA, 0xAF48, 0xB2CB, 0xAF49, 0xB2CC, 0xAF50, 0xB2CD, 0xAF5C, 0xB2CE, 0xAF5D, 0xB2CF, 0xAF64, 0xB2D0, 0xAF65, 0xB2D1, 0xAF79, 0xB2D2, 0xAF80, 0xB2D3, 0xAF84, 0xB2D4, 0xAF88, 0xB2D5, 0xAF90, 0xB2D6, 0xAF91, 0xB2D7, 0xAF95, 0xB2D8, 0xAF9C, 0xB2D9, 0xAFB8, 0xB2DA, 0xAFB9, 0xB2DB, 0xAFBC, 0xB2DC, 0xAFC0, 0xB2DD, 0xAFC7, 0xB2DE, 0xAFC8, 0xB2DF, 0xAFC9, 0xB2E0, 0xAFCB, 0xB2E1, 0xAFCD, 0xB2E2, 0xAFCE, 0xB2E3, 0xAFD4, 0xB2E4, 0xAFDC, 0xB2E5, 0xAFE8, 0xB2E6, 0xAFE9, 0xB2E7, 0xAFF0, 0xB2E8, 0xAFF1, 0xB2E9, 0xAFF4, 0xB2EA, 0xAFF8, 0xB2EB, 0xB000, 0xB2EC, 0xB001, 0xB2ED, 0xB004, 0xB2EE, 0xB00C, 0xB2EF, 0xB010, 0xB2F0, 0xB014, 0xB2F1, 0xB01C, 0xB2F2, 0xB01D, 0xB2F3, 0xB028, 0xB2F4, 0xB044, 0xB2F5, 0xB045, 0xB2F6, 0xB048, 0xB2F7, 0xB04A, 0xB2F8, 0xB04C, 0xB2F9, 0xB04E, 0xB2FA, 0xB053, 0xB2FB, 0xB054, 0xB2FC, 0xB055, 0xB2FD, 0xB057, 0xB2FE, 0xB059, 0xB341, 0xCFCC, 0xB342, 0xCFCD, 0xB343, 0xCFCE, 0xB344, 0xCFCF, 0xB345, 0xCFD0, 0xB346, 0xCFD1, 0xB347, 0xCFD2, 0xB348, 0xCFD3, 0xB349, 0xCFD4, 0xB34A, 0xCFD5, 0xB34B, 0xCFD6, 0xB34C, 0xCFD7, 0xB34D, 0xCFD8, 0xB34E, 0xCFD9, 0xB34F, 0xCFDA, 0xB350, 0xCFDB, 0xB351, 0xCFDC, 0xB352, 0xCFDD, 0xB353, 0xCFDE, 0xB354, 0xCFDF, 0xB355, 0xCFE2, 0xB356, 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0x5F6D, 0xF8B1, 0x6F8E, 0xF8B2, 0x70F9, 0xF8B3, 0x81A8, 0xF8B4, 0x610E, 0xF8B5, 0x4FBF, 0xF8B6, 0x504F, 0xF8B7, 0x6241, 0xF8B8, 0x7247, 0xF8B9, 0x7BC7, 0xF8BA, 0x7DE8, 0xF8BB, 0x7FE9, 0xF8BC, 0x904D, 0xF8BD, 0x97AD, 0xF8BE, 0x9A19, 0xF8BF, 0x8CB6, 0xF8C0, 0x576A, 0xF8C1, 0x5E73, 0xF8C2, 0x67B0, 0xF8C3, 0x840D, 0xF8C4, 0x8A55, 0xF8C5, 0x5420, 0xF8C6, 0x5B16, 0xF8C7, 0x5E63, 0xF8C8, 0x5EE2, 0xF8C9, 0x5F0A, 0xF8CA, 0x6583, 0xF8CB, 0x80BA, 0xF8CC, 0x853D, 0xF8CD, 0x9589, 0xF8CE, 0x965B, 0xF8CF, 0x4F48, 0xF8D0, 0x5305, 0xF8D1, 0x530D, 0xF8D2, 0x530F, 0xF8D3, 0x5486, 0xF8D4, 0x54FA, 0xF8D5, 0x5703, 0xF8D6, 0x5E03, 0xF8D7, 0x6016, 0xF8D8, 0x629B, 0xF8D9, 0x62B1, 0xF8DA, 0x6355, 0xF8DB, 0xFA06, 0xF8DC, 0x6CE1, 0xF8DD, 0x6D66, 0xF8DE, 0x75B1, 0xF8DF, 0x7832, 0xF8E0, 0x80DE, 0xF8E1, 0x812F, 0xF8E2, 0x82DE, 0xF8E3, 0x8461, 0xF8E4, 0x84B2, 0xF8E5, 0x888D, 0xF8E6, 0x8912, 0xF8E7, 0x900B, 0xF8E8, 0x92EA, 0xF8E9, 0x98FD, 0xF8EA, 0x9B91, 0xF8EB, 0x5E45, 0xF8EC, 0x66B4, 0xF8ED, 0x66DD, 0xF8EE, 0x7011, 0xF8EF, 0x7206, 0xF8F0, 0xFA07, 0xF8F1, 0x4FF5, 0xF8F2, 0x527D, 0xF8F3, 0x5F6A, 0xF8F4, 0x6153, 0xF8F5, 0x6753, 0xF8F6, 0x6A19, 0xF8F7, 0x6F02, 0xF8F8, 0x74E2, 0xF8F9, 0x7968, 0xF8FA, 0x8868, 0xF8FB, 0x8C79, 0xF8FC, 0x98C7, 0xF8FD, 0x98C4, 0xF8FE, 0x9A43, 0xF9A1, 0x54C1, 0xF9A2, 0x7A1F, 0xF9A3, 0x6953, 0xF9A4, 0x8AF7, 0xF9A5, 0x8C4A, 0xF9A6, 0x98A8, 0xF9A7, 0x99AE, 0xF9A8, 0x5F7C, 0xF9A9, 0x62AB, 0xF9AA, 0x75B2, 0xF9AB, 0x76AE, 0xF9AC, 0x88AB, 0xF9AD, 0x907F, 0xF9AE, 0x9642, 0xF9AF, 0x5339, 0xF9B0, 0x5F3C, 0xF9B1, 0x5FC5, 0xF9B2, 0x6CCC, 0xF9B3, 0x73CC, 0xF9B4, 0x7562, 0xF9B5, 0x758B, 0xF9B6, 0x7B46, 0xF9B7, 0x82FE, 0xF9B8, 0x999D, 0xF9B9, 0x4E4F, 0xF9BA, 0x903C, 0xF9BB, 0x4E0B, 0xF9BC, 0x4F55, 0xF9BD, 0x53A6, 0xF9BE, 0x590F, 0xF9BF, 0x5EC8, 0xF9C0, 0x6630, 0xF9C1, 0x6CB3, 0xF9C2, 0x7455, 0xF9C3, 0x8377, 0xF9C4, 0x8766, 0xF9C5, 0x8CC0, 0xF9C6, 0x9050, 0xF9C7, 0x971E, 0xF9C8, 0x9C15, 0xF9C9, 0x58D1, 0xF9CA, 0x5B78, 0xF9CB, 0x8650, 0xF9CC, 0x8B14, 0xF9CD, 0x9DB4, 0xF9CE, 0x5BD2, 0xF9CF, 0x6068, 0xF9D0, 0x608D, 0xF9D1, 0x65F1, 0xF9D2, 0x6C57, 0xF9D3, 0x6F22, 0xF9D4, 0x6FA3, 0xF9D5, 0x701A, 0xF9D6, 0x7F55, 0xF9D7, 0x7FF0, 0xF9D8, 0x9591, 0xF9D9, 0x9592, 0xF9DA, 0x9650, 0xF9DB, 0x97D3, 0xF9DC, 0x5272, 0xF9DD, 0x8F44, 0xF9DE, 0x51FD, 0xF9DF, 0x542B, 0xF9E0, 0x54B8, 0xF9E1, 0x5563, 0xF9E2, 0x558A, 0xF9E3, 0x6ABB, 0xF9E4, 0x6DB5, 0xF9E5, 0x7DD8, 0xF9E6, 0x8266, 0xF9E7, 0x929C, 0xF9E8, 0x9677, 0xF9E9, 0x9E79, 0xF9EA, 0x5408, 0xF9EB, 0x54C8, 0xF9EC, 0x76D2, 0xF9ED, 0x86E4, 0xF9EE, 0x95A4, 0xF9EF, 0x95D4, 0xF9F0, 0x965C, 0xF9F1, 0x4EA2, 0xF9F2, 0x4F09, 0xF9F3, 0x59EE, 0xF9F4, 0x5AE6, 0xF9F5, 0x5DF7, 0xF9F6, 0x6052, 0xF9F7, 0x6297, 0xF9F8, 0x676D, 0xF9F9, 0x6841, 0xF9FA, 0x6C86, 0xF9FB, 0x6E2F, 0xF9FC, 0x7F38, 0xF9FD, 0x809B, 0xF9FE, 0x822A, 0xFAA1, 0xFA08, 0xFAA2, 0xFA09, 0xFAA3, 0x9805, 0xFAA4, 0x4EA5, 0xFAA5, 0x5055, 0xFAA6, 0x54B3, 0xFAA7, 0x5793, 0xFAA8, 0x595A, 0xFAA9, 0x5B69, 0xFAAA, 0x5BB3, 0xFAAB, 0x61C8, 0xFAAC, 0x6977, 0xFAAD, 0x6D77, 0xFAAE, 0x7023, 0xFAAF, 0x87F9, 0xFAB0, 0x89E3, 0xFAB1, 0x8A72, 0xFAB2, 0x8AE7, 0xFAB3, 0x9082, 0xFAB4, 0x99ED, 0xFAB5, 0x9AB8, 0xFAB6, 0x52BE, 0xFAB7, 0x6838, 0xFAB8, 0x5016, 0xFAB9, 0x5E78, 0xFABA, 0x674F, 0xFABB, 0x8347, 0xFABC, 0x884C, 0xFABD, 0x4EAB, 0xFABE, 0x5411, 0xFABF, 0x56AE, 0xFAC0, 0x73E6, 0xFAC1, 0x9115, 0xFAC2, 0x97FF, 0xFAC3, 0x9909, 0xFAC4, 0x9957, 0xFAC5, 0x9999, 0xFAC6, 0x5653, 0xFAC7, 0x589F, 0xFAC8, 0x865B, 0xFAC9, 0x8A31, 0xFACA, 0x61B2, 0xFACB, 0x6AF6, 0xFACC, 0x737B, 0xFACD, 0x8ED2, 0xFACE, 0x6B47, 0xFACF, 0x96AA, 0xFAD0, 0x9A57, 0xFAD1, 0x5955, 0xFAD2, 0x7200, 0xFAD3, 0x8D6B, 0xFAD4, 0x9769, 0xFAD5, 0x4FD4, 0xFAD6, 0x5CF4, 0xFAD7, 0x5F26, 0xFAD8, 0x61F8, 0xFAD9, 0x665B, 0xFADA, 0x6CEB, 0xFADB, 0x70AB, 0xFADC, 0x7384, 0xFADD, 0x73B9, 0xFADE, 0x73FE, 0xFADF, 0x7729, 0xFAE0, 0x774D, 0xFAE1, 0x7D43, 0xFAE2, 0x7D62, 0xFAE3, 0x7E23, 0xFAE4, 0x8237, 0xFAE5, 0x8852, 0xFAE6, 0xFA0A, 0xFAE7, 0x8CE2, 0xFAE8, 0x9249, 0xFAE9, 0x986F, 0xFAEA, 0x5B51, 0xFAEB, 0x7A74, 0xFAEC, 0x8840, 0xFAED, 0x9801, 0xFAEE, 0x5ACC, 0xFAEF, 0x4FE0, 0xFAF0, 0x5354, 0xFAF1, 0x593E, 0xFAF2, 0x5CFD, 0xFAF3, 0x633E, 0xFAF4, 0x6D79, 0xFAF5, 0x72F9, 0xFAF6, 0x8105, 0xFAF7, 0x8107, 0xFAF8, 0x83A2, 0xFAF9, 0x92CF, 0xFAFA, 0x9830, 0xFAFB, 0x4EA8, 0xFAFC, 0x5144, 0xFAFD, 0x5211, 0xFAFE, 0x578B, 0xFBA1, 0x5F62, 0xFBA2, 0x6CC2, 0xFBA3, 0x6ECE, 0xFBA4, 0x7005, 0xFBA5, 0x7050, 0xFBA6, 0x70AF, 0xFBA7, 0x7192, 0xFBA8, 0x73E9, 0xFBA9, 0x7469, 0xFBAA, 0x834A, 0xFBAB, 0x87A2, 0xFBAC, 0x8861, 0xFBAD, 0x9008, 0xFBAE, 0x90A2, 0xFBAF, 0x93A3, 0xFBB0, 0x99A8, 0xFBB1, 0x516E, 0xFBB2, 0x5F57, 0xFBB3, 0x60E0, 0xFBB4, 0x6167, 0xFBB5, 0x66B3, 0xFBB6, 0x8559, 0xFBB7, 0x8E4A, 0xFBB8, 0x91AF, 0xFBB9, 0x978B, 0xFBBA, 0x4E4E, 0xFBBB, 0x4E92, 0xFBBC, 0x547C, 0xFBBD, 0x58D5, 0xFBBE, 0x58FA, 0xFBBF, 0x597D, 0xFBC0, 0x5CB5, 0xFBC1, 0x5F27, 0xFBC2, 0x6236, 0xFBC3, 0x6248, 0xFBC4, 0x660A, 0xFBC5, 0x6667, 0xFBC6, 0x6BEB, 0xFBC7, 0x6D69, 0xFBC8, 0x6DCF, 0xFBC9, 0x6E56, 0xFBCA, 0x6EF8, 0xFBCB, 0x6F94, 0xFBCC, 0x6FE0, 0xFBCD, 0x6FE9, 0xFBCE, 0x705D, 0xFBCF, 0x72D0, 0xFBD0, 0x7425, 0xFBD1, 0x745A, 0xFBD2, 0x74E0, 0xFBD3, 0x7693, 0xFBD4, 0x795C, 0xFBD5, 0x7CCA, 0xFBD6, 0x7E1E, 0xFBD7, 0x80E1, 0xFBD8, 0x82A6, 0xFBD9, 0x846B, 0xFBDA, 0x84BF, 0xFBDB, 0x864E, 0xFBDC, 0x865F, 0xFBDD, 0x8774, 0xFBDE, 0x8B77, 0xFBDF, 0x8C6A, 0xFBE0, 0x93AC, 0xFBE1, 0x9800, 0xFBE2, 0x9865, 0xFBE3, 0x60D1, 0xFBE4, 0x6216, 0xFBE5, 0x9177, 0xFBE6, 0x5A5A, 0xFBE7, 0x660F, 0xFBE8, 0x6DF7, 0xFBE9, 0x6E3E, 0xFBEA, 0x743F, 0xFBEB, 0x9B42, 0xFBEC, 0x5FFD, 0xFBED, 0x60DA, 0xFBEE, 0x7B0F, 0xFBEF, 0x54C4, 0xFBF0, 0x5F18, 0xFBF1, 0x6C5E, 0xFBF2, 0x6CD3, 0xFBF3, 0x6D2A, 0xFBF4, 0x70D8, 0xFBF5, 0x7D05, 0xFBF6, 0x8679, 0xFBF7, 0x8A0C, 0xFBF8, 0x9D3B, 0xFBF9, 0x5316, 0xFBFA, 0x548C, 0xFBFB, 0x5B05, 0xFBFC, 0x6A3A, 0xFBFD, 0x706B, 0xFBFE, 0x7575, 0xFCA1, 0x798D, 0xFCA2, 0x79BE, 0xFCA3, 0x82B1, 0xFCA4, 0x83EF, 0xFCA5, 0x8A71, 0xFCA6, 0x8B41, 0xFCA7, 0x8CA8, 0xFCA8, 0x9774, 0xFCA9, 0xFA0B, 0xFCAA, 0x64F4, 0xFCAB, 0x652B, 0xFCAC, 0x78BA, 0xFCAD, 0x78BB, 0xFCAE, 0x7A6B, 0xFCAF, 0x4E38, 0xFCB0, 0x559A, 0xFCB1, 0x5950, 0xFCB2, 0x5BA6, 0xFCB3, 0x5E7B, 0xFCB4, 0x60A3, 0xFCB5, 0x63DB, 0xFCB6, 0x6B61, 0xFCB7, 0x6665, 0xFCB8, 0x6853, 0xFCB9, 0x6E19, 0xFCBA, 0x7165, 0xFCBB, 0x74B0, 0xFCBC, 0x7D08, 0xFCBD, 0x9084, 0xFCBE, 0x9A69, 0xFCBF, 0x9C25, 0xFCC0, 0x6D3B, 0xFCC1, 0x6ED1, 0xFCC2, 0x733E, 0xFCC3, 0x8C41, 0xFCC4, 0x95CA, 0xFCC5, 0x51F0, 0xFCC6, 0x5E4C, 0xFCC7, 0x5FA8, 0xFCC8, 0x604D, 0xFCC9, 0x60F6, 0xFCCA, 0x6130, 0xFCCB, 0x614C, 0xFCCC, 0x6643, 0xFCCD, 0x6644, 0xFCCE, 0x69A5, 0xFCCF, 0x6CC1, 0xFCD0, 0x6E5F, 0xFCD1, 0x6EC9, 0xFCD2, 0x6F62, 0xFCD3, 0x714C, 0xFCD4, 0x749C, 0xFCD5, 0x7687, 0xFCD6, 0x7BC1, 0xFCD7, 0x7C27, 0xFCD8, 0x8352, 0xFCD9, 0x8757, 0xFCDA, 0x9051, 0xFCDB, 0x968D, 0xFCDC, 0x9EC3, 0xFCDD, 0x532F, 0xFCDE, 0x56DE, 0xFCDF, 0x5EFB, 0xFCE0, 0x5F8A, 0xFCE1, 0x6062, 0xFCE2, 0x6094, 0xFCE3, 0x61F7, 0xFCE4, 0x6666, 0xFCE5, 0x6703, 0xFCE6, 0x6A9C, 0xFCE7, 0x6DEE, 0xFCE8, 0x6FAE, 0xFCE9, 0x7070, 0xFCEA, 0x736A, 0xFCEB, 0x7E6A, 0xFCEC, 0x81BE, 0xFCED, 0x8334, 0xFCEE, 0x86D4, 0xFCEF, 0x8AA8, 0xFCF0, 0x8CC4, 0xFCF1, 0x5283, 0xFCF2, 0x7372, 0xFCF3, 0x5B96, 0xFCF4, 0x6A6B, 0xFCF5, 0x9404, 0xFCF6, 0x54EE, 0xFCF7, 0x5686, 0xFCF8, 0x5B5D, 0xFCF9, 0x6548, 0xFCFA, 0x6585, 0xFCFB, 0x66C9, 0xFCFC, 0x689F, 0xFCFD, 0x6D8D, 0xFCFE, 0x6DC6, 0xFDA1, 0x723B, 0xFDA2, 0x80B4, 0xFDA3, 0x9175, 0xFDA4, 0x9A4D, 0xFDA5, 0x4FAF, 0xFDA6, 0x5019, 0xFDA7, 0x539A, 0xFDA8, 0x540E, 0xFDA9, 0x543C, 0xFDAA, 0x5589, 0xFDAB, 0x55C5, 0xFDAC, 0x5E3F, 0xFDAD, 0x5F8C, 0xFDAE, 0x673D, 0xFDAF, 0x7166, 0xFDB0, 0x73DD, 0xFDB1, 0x9005, 0xFDB2, 0x52DB, 0xFDB3, 0x52F3, 0xFDB4, 0x5864, 0xFDB5, 0x58CE, 0xFDB6, 0x7104, 0xFDB7, 0x718F, 0xFDB8, 0x71FB, 0xFDB9, 0x85B0, 0xFDBA, 0x8A13, 0xFDBB, 0x6688, 0xFDBC, 0x85A8, 0xFDBD, 0x55A7, 0xFDBE, 0x6684, 0xFDBF, 0x714A, 0xFDC0, 0x8431, 0xFDC1, 0x5349, 0xFDC2, 0x5599, 0xFDC3, 0x6BC1, 0xFDC4, 0x5F59, 0xFDC5, 0x5FBD, 0xFDC6, 0x63EE, 0xFDC7, 0x6689, 0xFDC8, 0x7147, 0xFDC9, 0x8AF1, 0xFDCA, 0x8F1D, 0xFDCB, 0x9EBE, 0xFDCC, 0x4F11, 0xFDCD, 0x643A, 0xFDCE, 0x70CB, 0xFDCF, 0x7566, 0xFDD0, 0x8667, 0xFDD1, 0x6064, 0xFDD2, 0x8B4E, 0xFDD3, 0x9DF8, 0xFDD4, 0x5147, 0xFDD5, 0x51F6, 0xFDD6, 0x5308, 0xFDD7, 0x6D36, 0xFDD8, 0x80F8, 0xFDD9, 0x9ED1, 0xFDDA, 0x6615, 0xFDDB, 0x6B23, 0xFDDC, 0x7098, 0xFDDD, 0x75D5, 0xFDDE, 0x5403, 0xFDDF, 0x5C79, 0xFDE0, 0x7D07, 0xFDE1, 0x8A16, 0xFDE2, 0x6B20, 0xFDE3, 0x6B3D, 0xFDE4, 0x6B46, 0xFDE5, 0x5438, 0xFDE6, 0x6070, 0xFDE7, 0x6D3D, 0xFDE8, 0x7FD5, 0xFDE9, 0x8208, 0xFDEA, 0x50D6, 0xFDEB, 0x51DE, 0xFDEC, 0x559C, 0xFDED, 0x566B, 0xFDEE, 0x56CD, 0xFDEF, 0x59EC, 0xFDF0, 0x5B09, 0xFDF1, 0x5E0C, 0xFDF2, 0x6199, 0xFDF3, 0x6198, 0xFDF4, 0x6231, 0xFDF5, 0x665E, 0xFDF6, 0x66E6, 0xFDF7, 0x7199, 0xFDF8, 0x71B9, 0xFDF9, 0x71BA, 0xFDFA, 0x72A7, 0xFDFB, 0x79A7, 0xFDFC, 0x7A00, 0xFDFD, 0x7FB2, 0xFDFE, 0x8A70, 0, 0 }; #endif #if FF_CODE_PAGE == 950 || FF_CODE_PAGE == 0 /* Traditional Chinese */ static const WCHAR uni2oem950[] = { /* Unicode --> Big5 pairs */ 0x00A7, 0xA1B1, 0x00AF, 0xA1C2, 0x00B0, 0xA258, 0x00B1, 0xA1D3, 0x00B7, 0xA150, 0x00D7, 0xA1D1, 0x00F7, 0xA1D2, 0x02C7, 0xA3BE, 0x02C9, 0xA3BC, 0x02CA, 0xA3BD, 0x02CB, 0xA3BF, 0x02CD, 0xA1C5, 0x02D9, 0xA3BB, 0x0391, 0xA344, 0x0392, 0xA345, 0x0393, 0xA346, 0x0394, 0xA347, 0x0395, 0xA348, 0x0396, 0xA349, 0x0397, 0xA34A, 0x0398, 0xA34B, 0x0399, 0xA34C, 0x039A, 0xA34D, 0x039B, 0xA34E, 0x039C, 0xA34F, 0x039D, 0xA350, 0x039E, 0xA351, 0x039F, 0xA352, 0x03A0, 0xA353, 0x03A1, 0xA354, 0x03A3, 0xA355, 0x03A4, 0xA356, 0x03A5, 0xA357, 0x03A6, 0xA358, 0x03A7, 0xA359, 0x03A8, 0xA35A, 0x03A9, 0xA35B, 0x03B1, 0xA35C, 0x03B2, 0xA35D, 0x03B3, 0xA35E, 0x03B4, 0xA35F, 0x03B5, 0xA360, 0x03B6, 0xA361, 0x03B7, 0xA362, 0x03B8, 0xA363, 0x03B9, 0xA364, 0x03BA, 0xA365, 0x03BB, 0xA366, 0x03BC, 0xA367, 0x03BD, 0xA368, 0x03BE, 0xA369, 0x03BF, 0xA36A, 0x03C0, 0xA36B, 0x03C1, 0xA36C, 0x03C3, 0xA36D, 0x03C4, 0xA36E, 0x03C5, 0xA36F, 0x03C6, 0xA370, 0x03C7, 0xA371, 0x03C8, 0xA372, 0x03C9, 0xA373, 0x2013, 0xA156, 0x2014, 0xA158, 0x2018, 0xA1A5, 0x2019, 0xA1A6, 0x201C, 0xA1A7, 0x201D, 0xA1A8, 0x2025, 0xA14C, 0x2026, 0xA14B, 0x2027, 0xA145, 0x2032, 0xA1AC, 0x2035, 0xA1AB, 0x203B, 0xA1B0, 0x20AC, 0xA3E1, 0x2103, 0xA24A, 0x2105, 0xA1C1, 0x2109, 0xA24B, 0x2160, 0xA2B9, 0x2161, 0xA2BA, 0x2162, 0xA2BB, 0x2163, 0xA2BC, 0x2164, 0xA2BD, 0x2165, 0xA2BE, 0x2166, 0xA2BF, 0x2167, 0xA2C0, 0x2168, 0xA2C1, 0x2169, 0xA2C2, 0x2190, 0xA1F6, 0x2191, 0xA1F4, 0x2192, 0xA1F7, 0x2193, 0xA1F5, 0x2196, 0xA1F8, 0x2197, 0xA1F9, 0x2198, 0xA1FB, 0x2199, 0xA1FA, 0x2215, 0xA241, 0x221A, 0xA1D4, 0x221E, 0xA1DB, 0x221F, 0xA1E8, 0x2220, 0xA1E7, 0x2223, 0xA1FD, 0x2225, 0xA1FC, 0x2229, 0xA1E4, 0x222A, 0xA1E5, 0x222B, 0xA1EC, 0x222E, 0xA1ED, 0x2234, 0xA1EF, 0x2235, 0xA1EE, 0x2252, 0xA1DC, 0x2260, 0xA1DA, 0x2261, 0xA1DD, 0x2266, 0xA1D8, 0x2267, 0xA1D9, 0x2295, 0xA1F2, 0x2299, 0xA1F3, 0x22A5, 0xA1E6, 0x22BF, 0xA1E9, 0x2500, 0xA277, 0x2502, 0xA278, 0x250C, 0xA27A, 0x2510, 0xA27B, 0x2514, 0xA27C, 0x2518, 0xA27D, 0x251C, 0xA275, 0x2524, 0xA274, 0x252C, 0xA273, 0x2534, 0xA272, 0x253C, 0xA271, 0x2550, 0xA2A4, 0x2550, 0xF9F9, 0x2551, 0xF9F8, 0x2552, 0xF9E6, 0x2553, 0xF9EF, 0x2554, 0xF9DD, 0x2555, 0xF9E8, 0x2556, 0xF9F1, 0x2557, 0xF9DF, 0x2558, 0xF9EC, 0x2559, 0xF9F5, 0x255A, 0xF9E3, 0x255B, 0xF9EE, 0x255C, 0xF9F7, 0x255D, 0xF9E5, 0x255E, 0xA2A5, 0x255E, 0xF9E9, 0x255F, 0xF9F2, 0x2560, 0xF9E0, 0x2561, 0xA2A7, 0x2561, 0xF9EB, 0x2562, 0xF9F4, 0x2563, 0xF9E2, 0x2564, 0xF9E7, 0x2565, 0xF9F0, 0x2566, 0xF9DE, 0x2567, 0xF9ED, 0x2568, 0xF9F6, 0x2569, 0xF9E4, 0x256A, 0xA2A6, 0x256A, 0xF9EA, 0x256B, 0xF9F3, 0x256C, 0xF9E1, 0x256D, 0xA27E, 0x256D, 0xF9FA, 0x256E, 0xA2A1, 0x256E, 0xF9FB, 0x256F, 0xA2A3, 0x256F, 0xF9FD, 0x2570, 0xA2A2, 0x2570, 0xF9FC, 0x2571, 0xA2AC, 0x2572, 0xA2AD, 0x2573, 0xA2AE, 0x2574, 0xA15A, 0x2581, 0xA262, 0x2582, 0xA263, 0x2583, 0xA264, 0x2584, 0xA265, 0x2585, 0xA266, 0x2586, 0xA267, 0x2587, 0xA268, 0x2588, 0xA269, 0x2589, 0xA270, 0x258A, 0xA26F, 0x258B, 0xA26E, 0x258C, 0xA26D, 0x258D, 0xA26C, 0x258E, 0xA26B, 0x258F, 0xA26A, 0x2593, 0xF9FE, 0x2594, 0xA276, 0x2595, 0xA279, 0x25A0, 0xA1BD, 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0xF878, 0x9F07, 0xC652, 0x9F09, 0xF965, 0x9F0A, 0xF97E, 0x9F0E, 0xB9A9, 0x9F0F, 0xE8F2, 0x9F10, 0xE8F3, 0x9F12, 0xECB7, 0x9F13, 0xB9AA, 0x9F15, 0xC35D, 0x9F16, 0xF1E3, 0x9F18, 0xF6CF, 0x9F19, 0xC567, 0x9F1A, 0xF6D0, 0x9F1B, 0xF6CE, 0x9F1C, 0xF879, 0x9F1E, 0xF8E9, 0x9F20, 0xB9AB, 0x9F22, 0xEFB4, 0x9F23, 0xEFB3, 0x9F24, 0xEFB2, 0x9F25, 0xF1E4, 0x9F28, 0xF1E8, 0x9F29, 0xF1E7, 0x9F2A, 0xF1E6, 0x9F2B, 0xF1E5, 0x9F2C, 0xC35E, 0x9F2D, 0xF3F6, 0x9F2E, 0xF5B9, 0x9F2F, 0xC4D3, 0x9F30, 0xF5B8, 0x9F31, 0xF6D1, 0x9F32, 0xF7CB, 0x9F33, 0xF7CA, 0x9F34, 0xC5C4, 0x9F35, 0xF7C9, 0x9F36, 0xF87C, 0x9F37, 0xF87B, 0x9F38, 0xF87A, 0x9F3B, 0xBBF3, 0x9F3D, 0xECB8, 0x9F3E, 0xC24D, 0x9F40, 0xF3F7, 0x9F41, 0xF3F8, 0x9F42, 0xF7CC, 0x9F43, 0xF87D, 0x9F46, 0xF8EA, 0x9F47, 0xF966, 0x9F48, 0xF9B9, 0x9F49, 0xF9D4, 0x9F4A, 0xBBF4, 0x9F4B, 0xC24E, 0x9F4C, 0xF1E9, 0x9F4D, 0xF3F9, 0x9F4E, 0xF6D2, 0x9F4F, 0xF87E, 0x9F52, 0xBEA6, 0x9F54, 0xEFB5, 0x9F55, 0xF1EA, 0x9F56, 0xF3FA, 0x9F57, 0xF3FB, 0x9F58, 0xF3FC, 0x9F59, 0xF5BE, 0x9F5B, 0xF5BA, 0x9F5C, 0xC568, 0x9F5D, 0xF5BD, 0x9F5E, 0xF5BC, 0x9F5F, 0xC4D4, 0x9F60, 0xF5BB, 0x9F61, 0xC4D6, 0x9F63, 0xC4D5, 0x9F64, 0xF6D4, 0x9F65, 0xF6D3, 0x9F66, 0xC569, 0x9F67, 0xC56A, 0x9F6A, 0xC5C6, 0x9F6B, 0xF7CD, 0x9F6C, 0xC5C5, 0x9F6E, 0xF8A3, 0x9F6F, 0xF8A4, 0x9F70, 0xF8A2, 0x9F71, 0xF8A1, 0x9F72, 0xC654, 0x9F74, 0xF8EB, 0x9F75, 0xF8EC, 0x9F76, 0xF8ED, 0x9F77, 0xC653, 0x9F78, 0xF967, 0x9F79, 0xF96A, 0x9F7A, 0xF969, 0x9F7B, 0xF968, 0x9F7E, 0xF9D3, 0x9F8D, 0xC073, 0x9F90, 0xC365, 0x9F91, 0xF5BF, 0x9F92, 0xF6D5, 0x9F94, 0xC5C7, 0x9F95, 0xF7CE, 0x9F98, 0xF9D5, 0x9F9C, 0xC074, 0x9FA0, 0xEFB6, 0x9FA2, 0xF7CF, 0x9FA4, 0xF9A1, 0xFA0C, 0xC94A, 0xFA0D, 0xDDFC, 0xFE30, 0xA14A, 0xFE31, 0xA157, 0xFE33, 0xA159, 0xFE34, 0xA15B, 0xFE35, 0xA15F, 0xFE36, 0xA160, 0xFE37, 0xA163, 0xFE38, 0xA164, 0xFE39, 0xA167, 0xFE3A, 0xA168, 0xFE3B, 0xA16B, 0xFE3C, 0xA16C, 0xFE3D, 0xA16F, 0xFE3E, 0xA170, 0xFE3F, 0xA173, 0xFE40, 0xA174, 0xFE41, 0xA177, 0xFE42, 0xA178, 0xFE43, 0xA17B, 0xFE44, 0xA17C, 0xFE49, 0xA1C6, 0xFE4A, 0xA1C7, 0xFE4B, 0xA1CA, 0xFE4C, 0xA1CB, 0xFE4D, 0xA1C8, 0xFE4E, 0xA1C9, 0xFE4F, 0xA15C, 0xFE50, 0xA14D, 0xFE51, 0xA14E, 0xFE52, 0xA14F, 0xFE54, 0xA151, 0xFE55, 0xA152, 0xFE56, 0xA153, 0xFE57, 0xA154, 0xFE59, 0xA17D, 0xFE5A, 0xA17E, 0xFE5B, 0xA1A1, 0xFE5C, 0xA1A2, 0xFE5D, 0xA1A3, 0xFE5E, 0xA1A4, 0xFE5F, 0xA1CC, 0xFE60, 0xA1CD, 0xFE61, 0xA1CE, 0xFE62, 0xA1DE, 0xFE63, 0xA1DF, 0xFE64, 0xA1E0, 0xFE65, 0xA1E1, 0xFE66, 0xA1E2, 0xFE68, 0xA242, 0xFE69, 0xA24C, 0xFE6A, 0xA24D, 0xFE6B, 0xA24E, 0xFF01, 0xA149, 0xFF03, 0xA1AD, 0xFF04, 0xA243, 0xFF05, 0xA248, 0xFF06, 0xA1AE, 0xFF08, 0xA15D, 0xFF09, 0xA15E, 0xFF0A, 0xA1AF, 0xFF0B, 0xA1CF, 0xFF0C, 0xA141, 0xFF0D, 0xA1D0, 0xFF0E, 0xA144, 0xFF0F, 0xA1FE, 0xFF10, 0xA2AF, 0xFF11, 0xA2B0, 0xFF12, 0xA2B1, 0xFF13, 0xA2B2, 0xFF14, 0xA2B3, 0xFF15, 0xA2B4, 0xFF16, 0xA2B5, 0xFF17, 0xA2B6, 0xFF18, 0xA2B7, 0xFF19, 0xA2B8, 0xFF1A, 0xA147, 0xFF1B, 0xA146, 0xFF1C, 0xA1D5, 0xFF1D, 0xA1D7, 0xFF1E, 0xA1D6, 0xFF1F, 0xA148, 0xFF20, 0xA249, 0xFF21, 0xA2CF, 0xFF22, 0xA2D0, 0xFF23, 0xA2D1, 0xFF24, 0xA2D2, 0xFF25, 0xA2D3, 0xFF26, 0xA2D4, 0xFF27, 0xA2D5, 0xFF28, 0xA2D6, 0xFF29, 0xA2D7, 0xFF2A, 0xA2D8, 0xFF2B, 0xA2D9, 0xFF2C, 0xA2DA, 0xFF2D, 0xA2DB, 0xFF2E, 0xA2DC, 0xFF2F, 0xA2DD, 0xFF30, 0xA2DE, 0xFF31, 0xA2DF, 0xFF32, 0xA2E0, 0xFF33, 0xA2E1, 0xFF34, 0xA2E2, 0xFF35, 0xA2E3, 0xFF36, 0xA2E4, 0xFF37, 0xA2E5, 0xFF38, 0xA2E6, 0xFF39, 0xA2E7, 0xFF3A, 0xA2E8, 0xFF3C, 0xA240, 0xFF3F, 0xA1C4, 0xFF41, 0xA2E9, 0xFF42, 0xA2EA, 0xFF43, 0xA2EB, 0xFF44, 0xA2EC, 0xFF45, 0xA2ED, 0xFF46, 0xA2EE, 0xFF47, 0xA2EF, 0xFF48, 0xA2F0, 0xFF49, 0xA2F1, 0xFF4A, 0xA2F2, 0xFF4B, 0xA2F3, 0xFF4C, 0xA2F4, 0xFF4D, 0xA2F5, 0xFF4E, 0xA2F6, 0xFF4F, 0xA2F7, 0xFF50, 0xA2F8, 0xFF51, 0xA2F9, 0xFF52, 0xA2FA, 0xFF53, 0xA2FB, 0xFF54, 0xA2FC, 0xFF55, 0xA2FD, 0xFF56, 0xA2FE, 0xFF57, 0xA340, 0xFF58, 0xA341, 0xFF59, 0xA342, 0xFF5A, 0xA343, 0xFF5B, 0xA161, 0xFF5C, 0xA155, 0xFF5D, 0xA162, 0xFF5E, 0xA1E3, 0xFFE0, 0xA246, 0xFFE1, 0xA247, 0xFFE3, 0xA1C3, 0xFFE5, 0xA244, 0, 0 }; static const WCHAR oem2uni950[] = { /* Big5 --> Unicode pairs */ 0xA140, 0x3000, 0xA141, 0xFF0C, 0xA142, 0x3001, 0xA143, 0x3002, 0xA144, 0xFF0E, 0xA145, 0x2027, 0xA146, 0xFF1B, 0xA147, 0xFF1A, 0xA148, 0xFF1F, 0xA149, 0xFF01, 0xA14A, 0xFE30, 0xA14B, 0x2026, 0xA14C, 0x2025, 0xA14D, 0xFE50, 0xA14E, 0xFE51, 0xA14F, 0xFE52, 0xA150, 0x00B7, 0xA151, 0xFE54, 0xA152, 0xFE55, 0xA153, 0xFE56, 0xA154, 0xFE57, 0xA155, 0xFF5C, 0xA156, 0x2013, 0xA157, 0xFE31, 0xA158, 0x2014, 0xA159, 0xFE33, 0xA15A, 0x2574, 0xA15B, 0xFE34, 0xA15C, 0xFE4F, 0xA15D, 0xFF08, 0xA15E, 0xFF09, 0xA15F, 0xFE35, 0xA160, 0xFE36, 0xA161, 0xFF5B, 0xA162, 0xFF5D, 0xA163, 0xFE37, 0xA164, 0xFE38, 0xA165, 0x3014, 0xA166, 0x3015, 0xA167, 0xFE39, 0xA168, 0xFE3A, 0xA169, 0x3010, 0xA16A, 0x3011, 0xA16B, 0xFE3B, 0xA16C, 0xFE3C, 0xA16D, 0x300A, 0xA16E, 0x300B, 0xA16F, 0xFE3D, 0xA170, 0xFE3E, 0xA171, 0x3008, 0xA172, 0x3009, 0xA173, 0xFE3F, 0xA174, 0xFE40, 0xA175, 0x300C, 0xA176, 0x300D, 0xA177, 0xFE41, 0xA178, 0xFE42, 0xA179, 0x300E, 0xA17A, 0x300F, 0xA17B, 0xFE43, 0xA17C, 0xFE44, 0xA17D, 0xFE59, 0xA17E, 0xFE5A, 0xA1A1, 0xFE5B, 0xA1A2, 0xFE5C, 0xA1A3, 0xFE5D, 0xA1A4, 0xFE5E, 0xA1A5, 0x2018, 0xA1A6, 0x2019, 0xA1A7, 0x201C, 0xA1A8, 0x201D, 0xA1A9, 0x301D, 0xA1AA, 0x301E, 0xA1AB, 0x2035, 0xA1AC, 0x2032, 0xA1AD, 0xFF03, 0xA1AE, 0xFF06, 0xA1AF, 0xFF0A, 0xA1B0, 0x203B, 0xA1B1, 0x00A7, 0xA1B2, 0x3003, 0xA1B3, 0x25CB, 0xA1B4, 0x25CF, 0xA1B5, 0x25B3, 0xA1B6, 0x25B2, 0xA1B7, 0x25CE, 0xA1B8, 0x2606, 0xA1B9, 0x2605, 0xA1BA, 0x25C7, 0xA1BB, 0x25C6, 0xA1BC, 0x25A1, 0xA1BD, 0x25A0, 0xA1BE, 0x25BD, 0xA1BF, 0x25BC, 0xA1C0, 0x32A3, 0xA1C1, 0x2105, 0xA1C2, 0x00AF, 0xA1C3, 0xFFE3, 0xA1C4, 0xFF3F, 0xA1C5, 0x02CD, 0xA1C6, 0xFE49, 0xA1C7, 0xFE4A, 0xA1C8, 0xFE4D, 0xA1C9, 0xFE4E, 0xA1CA, 0xFE4B, 0xA1CB, 0xFE4C, 0xA1CC, 0xFE5F, 0xA1CD, 0xFE60, 0xA1CE, 0xFE61, 0xA1CF, 0xFF0B, 0xA1D0, 0xFF0D, 0xA1D1, 0x00D7, 0xA1D2, 0x00F7, 0xA1D3, 0x00B1, 0xA1D4, 0x221A, 0xA1D5, 0xFF1C, 0xA1D6, 0xFF1E, 0xA1D7, 0xFF1D, 0xA1D8, 0x2266, 0xA1D9, 0x2267, 0xA1DA, 0x2260, 0xA1DB, 0x221E, 0xA1DC, 0x2252, 0xA1DD, 0x2261, 0xA1DE, 0xFE62, 0xA1DF, 0xFE63, 0xA1E0, 0xFE64, 0xA1E1, 0xFE65, 0xA1E2, 0xFE66, 0xA1E3, 0xFF5E, 0xA1E4, 0x2229, 0xA1E5, 0x222A, 0xA1E6, 0x22A5, 0xA1E7, 0x2220, 0xA1E8, 0x221F, 0xA1E9, 0x22BF, 0xA1EA, 0x33D2, 0xA1EB, 0x33D1, 0xA1EC, 0x222B, 0xA1ED, 0x222E, 0xA1EE, 0x2235, 0xA1EF, 0x2234, 0xA1F0, 0x2640, 0xA1F1, 0x2642, 0xA1F2, 0x2295, 0xA1F3, 0x2299, 0xA1F4, 0x2191, 0xA1F5, 0x2193, 0xA1F6, 0x2190, 0xA1F7, 0x2192, 0xA1F8, 0x2196, 0xA1F9, 0x2197, 0xA1FA, 0x2199, 0xA1FB, 0x2198, 0xA1FC, 0x2225, 0xA1FD, 0x2223, 0xA1FE, 0xFF0F, 0xA240, 0xFF3C, 0xA241, 0x2215, 0xA242, 0xFE68, 0xA243, 0xFF04, 0xA244, 0xFFE5, 0xA245, 0x3012, 0xA246, 0xFFE0, 0xA247, 0xFFE1, 0xA248, 0xFF05, 0xA249, 0xFF20, 0xA24A, 0x2103, 0xA24B, 0x2109, 0xA24C, 0xFE69, 0xA24D, 0xFE6A, 0xA24E, 0xFE6B, 0xA24F, 0x33D5, 0xA250, 0x339C, 0xA251, 0x339D, 0xA252, 0x339E, 0xA253, 0x33CE, 0xA254, 0x33A1, 0xA255, 0x338E, 0xA256, 0x338F, 0xA257, 0x33C4, 0xA258, 0x00B0, 0xA259, 0x5159, 0xA25A, 0x515B, 0xA25B, 0x515E, 0xA25C, 0x515D, 0xA25D, 0x5161, 0xA25E, 0x5163, 0xA25F, 0x55E7, 0xA260, 0x74E9, 0xA261, 0x7CCE, 0xA262, 0x2581, 0xA263, 0x2582, 0xA264, 0x2583, 0xA265, 0x2584, 0xA266, 0x2585, 0xA267, 0x2586, 0xA268, 0x2587, 0xA269, 0x2588, 0xA26A, 0x258F, 0xA26B, 0x258E, 0xA26C, 0x258D, 0xA26D, 0x258C, 0xA26E, 0x258B, 0xA26F, 0x258A, 0xA270, 0x2589, 0xA271, 0x253C, 0xA272, 0x2534, 0xA273, 0x252C, 0xA274, 0x2524, 0xA275, 0x251C, 0xA276, 0x2594, 0xA277, 0x2500, 0xA278, 0x2502, 0xA279, 0x2595, 0xA27A, 0x250C, 0xA27B, 0x2510, 0xA27C, 0x2514, 0xA27D, 0x2518, 0xA27E, 0x256D, 0xA2A1, 0x256E, 0xA2A2, 0x2570, 0xA2A3, 0x256F, 0xA2A4, 0x2550, 0xA2A5, 0x255E, 0xA2A6, 0x256A, 0xA2A7, 0x2561, 0xA2A8, 0x25E2, 0xA2A9, 0x25E3, 0xA2AA, 0x25E5, 0xA2AB, 0x25E4, 0xA2AC, 0x2571, 0xA2AD, 0x2572, 0xA2AE, 0x2573, 0xA2AF, 0xFF10, 0xA2B0, 0xFF11, 0xA2B1, 0xFF12, 0xA2B2, 0xFF13, 0xA2B3, 0xFF14, 0xA2B4, 0xFF15, 0xA2B5, 0xFF16, 0xA2B6, 0xFF17, 0xA2B7, 0xFF18, 0xA2B8, 0xFF19, 0xA2B9, 0x2160, 0xA2BA, 0x2161, 0xA2BB, 0x2162, 0xA2BC, 0x2163, 0xA2BD, 0x2164, 0xA2BE, 0x2165, 0xA2BF, 0x2166, 0xA2C0, 0x2167, 0xA2C1, 0x2168, 0xA2C2, 0x2169, 0xA2C3, 0x3021, 0xA2C4, 0x3022, 0xA2C5, 0x3023, 0xA2C6, 0x3024, 0xA2C7, 0x3025, 0xA2C8, 0x3026, 0xA2C9, 0x3027, 0xA2CA, 0x3028, 0xA2CB, 0x3029, 0xA2CC, 0x5341, 0xA2CD, 0x5344, 0xA2CE, 0x5345, 0xA2CF, 0xFF21, 0xA2D0, 0xFF22, 0xA2D1, 0xFF23, 0xA2D2, 0xFF24, 0xA2D3, 0xFF25, 0xA2D4, 0xFF26, 0xA2D5, 0xFF27, 0xA2D6, 0xFF28, 0xA2D7, 0xFF29, 0xA2D8, 0xFF2A, 0xA2D9, 0xFF2B, 0xA2DA, 0xFF2C, 0xA2DB, 0xFF2D, 0xA2DC, 0xFF2E, 0xA2DD, 0xFF2F, 0xA2DE, 0xFF30, 0xA2DF, 0xFF31, 0xA2E0, 0xFF32, 0xA2E1, 0xFF33, 0xA2E2, 0xFF34, 0xA2E3, 0xFF35, 0xA2E4, 0xFF36, 0xA2E5, 0xFF37, 0xA2E6, 0xFF38, 0xA2E7, 0xFF39, 0xA2E8, 0xFF3A, 0xA2E9, 0xFF41, 0xA2EA, 0xFF42, 0xA2EB, 0xFF43, 0xA2EC, 0xFF44, 0xA2ED, 0xFF45, 0xA2EE, 0xFF46, 0xA2EF, 0xFF47, 0xA2F0, 0xFF48, 0xA2F1, 0xFF49, 0xA2F2, 0xFF4A, 0xA2F3, 0xFF4B, 0xA2F4, 0xFF4C, 0xA2F5, 0xFF4D, 0xA2F6, 0xFF4E, 0xA2F7, 0xFF4F, 0xA2F8, 0xFF50, 0xA2F9, 0xFF51, 0xA2FA, 0xFF52, 0xA2FB, 0xFF53, 0xA2FC, 0xFF54, 0xA2FD, 0xFF55, 0xA2FE, 0xFF56, 0xA340, 0xFF57, 0xA341, 0xFF58, 0xA342, 0xFF59, 0xA343, 0xFF5A, 0xA344, 0x0391, 0xA345, 0x0392, 0xA346, 0x0393, 0xA347, 0x0394, 0xA348, 0x0395, 0xA349, 0x0396, 0xA34A, 0x0397, 0xA34B, 0x0398, 0xA34C, 0x0399, 0xA34D, 0x039A, 0xA34E, 0x039B, 0xA34F, 0x039C, 0xA350, 0x039D, 0xA351, 0x039E, 0xA352, 0x039F, 0xA353, 0x03A0, 0xA354, 0x03A1, 0xA355, 0x03A3, 0xA356, 0x03A4, 0xA357, 0x03A5, 0xA358, 0x03A6, 0xA359, 0x03A7, 0xA35A, 0x03A8, 0xA35B, 0x03A9, 0xA35C, 0x03B1, 0xA35D, 0x03B2, 0xA35E, 0x03B3, 0xA35F, 0x03B4, 0xA360, 0x03B5, 0xA361, 0x03B6, 0xA362, 0x03B7, 0xA363, 0x03B8, 0xA364, 0x03B9, 0xA365, 0x03BA, 0xA366, 0x03BB, 0xA367, 0x03BC, 0xA368, 0x03BD, 0xA369, 0x03BE, 0xA36A, 0x03BF, 0xA36B, 0x03C0, 0xA36C, 0x03C1, 0xA36D, 0x03C3, 0xA36E, 0x03C4, 0xA36F, 0x03C5, 0xA370, 0x03C6, 0xA371, 0x03C7, 0xA372, 0x03C8, 0xA373, 0x03C9, 0xA374, 0x3105, 0xA375, 0x3106, 0xA376, 0x3107, 0xA377, 0x3108, 0xA378, 0x3109, 0xA379, 0x310A, 0xA37A, 0x310B, 0xA37B, 0x310C, 0xA37C, 0x310D, 0xA37D, 0x310E, 0xA37E, 0x310F, 0xA3A1, 0x3110, 0xA3A2, 0x3111, 0xA3A3, 0x3112, 0xA3A4, 0x3113, 0xA3A5, 0x3114, 0xA3A6, 0x3115, 0xA3A7, 0x3116, 0xA3A8, 0x3117, 0xA3A9, 0x3118, 0xA3AA, 0x3119, 0xA3AB, 0x311A, 0xA3AC, 0x311B, 0xA3AD, 0x311C, 0xA3AE, 0x311D, 0xA3AF, 0x311E, 0xA3B0, 0x311F, 0xA3B1, 0x3120, 0xA3B2, 0x3121, 0xA3B3, 0x3122, 0xA3B4, 0x3123, 0xA3B5, 0x3124, 0xA3B6, 0x3125, 0xA3B7, 0x3126, 0xA3B8, 0x3127, 0xA3B9, 0x3128, 0xA3BA, 0x3129, 0xA3BB, 0x02D9, 0xA3BC, 0x02C9, 0xA3BD, 0x02CA, 0xA3BE, 0x02C7, 0xA3BF, 0x02CB, 0xA3E1, 0x20AC, 0xA440, 0x4E00, 0xA441, 0x4E59, 0xA442, 0x4E01, 0xA443, 0x4E03, 0xA444, 0x4E43, 0xA445, 0x4E5D, 0xA446, 0x4E86, 0xA447, 0x4E8C, 0xA448, 0x4EBA, 0xA449, 0x513F, 0xA44A, 0x5165, 0xA44B, 0x516B, 0xA44C, 0x51E0, 0xA44D, 0x5200, 0xA44E, 0x5201, 0xA44F, 0x529B, 0xA450, 0x5315, 0xA451, 0x5341, 0xA452, 0x535C, 0xA453, 0x53C8, 0xA454, 0x4E09, 0xA455, 0x4E0B, 0xA456, 0x4E08, 0xA457, 0x4E0A, 0xA458, 0x4E2B, 0xA459, 0x4E38, 0xA45A, 0x51E1, 0xA45B, 0x4E45, 0xA45C, 0x4E48, 0xA45D, 0x4E5F, 0xA45E, 0x4E5E, 0xA45F, 0x4E8E, 0xA460, 0x4EA1, 0xA461, 0x5140, 0xA462, 0x5203, 0xA463, 0x52FA, 0xA464, 0x5343, 0xA465, 0x53C9, 0xA466, 0x53E3, 0xA467, 0x571F, 0xA468, 0x58EB, 0xA469, 0x5915, 0xA46A, 0x5927, 0xA46B, 0x5973, 0xA46C, 0x5B50, 0xA46D, 0x5B51, 0xA46E, 0x5B53, 0xA46F, 0x5BF8, 0xA470, 0x5C0F, 0xA471, 0x5C22, 0xA472, 0x5C38, 0xA473, 0x5C71, 0xA474, 0x5DDD, 0xA475, 0x5DE5, 0xA476, 0x5DF1, 0xA477, 0x5DF2, 0xA478, 0x5DF3, 0xA479, 0x5DFE, 0xA47A, 0x5E72, 0xA47B, 0x5EFE, 0xA47C, 0x5F0B, 0xA47D, 0x5F13, 0xA47E, 0x624D, 0xA4A1, 0x4E11, 0xA4A2, 0x4E10, 0xA4A3, 0x4E0D, 0xA4A4, 0x4E2D, 0xA4A5, 0x4E30, 0xA4A6, 0x4E39, 0xA4A7, 0x4E4B, 0xA4A8, 0x5C39, 0xA4A9, 0x4E88, 0xA4AA, 0x4E91, 0xA4AB, 0x4E95, 0xA4AC, 0x4E92, 0xA4AD, 0x4E94, 0xA4AE, 0x4EA2, 0xA4AF, 0x4EC1, 0xA4B0, 0x4EC0, 0xA4B1, 0x4EC3, 0xA4B2, 0x4EC6, 0xA4B3, 0x4EC7, 0xA4B4, 0x4ECD, 0xA4B5, 0x4ECA, 0xA4B6, 0x4ECB, 0xA4B7, 0x4EC4, 0xA4B8, 0x5143, 0xA4B9, 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0xF75B, 0x8B7F, 0xF75C, 0x8D15, 0xF75D, 0x8E95, 0xF75E, 0x8E94, 0xF75F, 0x8E9A, 0xF760, 0x8E92, 0xF761, 0x8E90, 0xF762, 0x8E96, 0xF763, 0x8E97, 0xF764, 0x8F60, 0xF765, 0x8F62, 0xF766, 0x9147, 0xF767, 0x944C, 0xF768, 0x9450, 0xF769, 0x944A, 0xF76A, 0x944B, 0xF76B, 0x944F, 0xF76C, 0x9447, 0xF76D, 0x9445, 0xF76E, 0x9448, 0xF76F, 0x9449, 0xF770, 0x9446, 0xF771, 0x973F, 0xF772, 0x97E3, 0xF773, 0x986A, 0xF774, 0x9869, 0xF775, 0x98CB, 0xF776, 0x9954, 0xF777, 0x995B, 0xF778, 0x9A4E, 0xF779, 0x9A53, 0xF77A, 0x9A54, 0xF77B, 0x9A4C, 0xF77C, 0x9A4F, 0xF77D, 0x9A48, 0xF77E, 0x9A4A, 0xF7A1, 0x9A49, 0xF7A2, 0x9A52, 0xF7A3, 0x9A50, 0xF7A4, 0x9AD0, 0xF7A5, 0x9B19, 0xF7A6, 0x9B2B, 0xF7A7, 0x9B3B, 0xF7A8, 0x9B56, 0xF7A9, 0x9B55, 0xF7AA, 0x9C46, 0xF7AB, 0x9C48, 0xF7AC, 0x9C3F, 0xF7AD, 0x9C44, 0xF7AE, 0x9C39, 0xF7AF, 0x9C33, 0xF7B0, 0x9C41, 0xF7B1, 0x9C3C, 0xF7B2, 0x9C37, 0xF7B3, 0x9C34, 0xF7B4, 0x9C32, 0xF7B5, 0x9C3D, 0xF7B6, 0x9C36, 0xF7B7, 0x9DDB, 0xF7B8, 0x9DD2, 0xF7B9, 0x9DDE, 0xF7BA, 0x9DDA, 0xF7BB, 0x9DCB, 0xF7BC, 0x9DD0, 0xF7BD, 0x9DDC, 0xF7BE, 0x9DD1, 0xF7BF, 0x9DDF, 0xF7C0, 0x9DE9, 0xF7C1, 0x9DD9, 0xF7C2, 0x9DD8, 0xF7C3, 0x9DD6, 0xF7C4, 0x9DF5, 0xF7C5, 0x9DD5, 0xF7C6, 0x9DDD, 0xF7C7, 0x9EB6, 0xF7C8, 0x9EF0, 0xF7C9, 0x9F35, 0xF7CA, 0x9F33, 0xF7CB, 0x9F32, 0xF7CC, 0x9F42, 0xF7CD, 0x9F6B, 0xF7CE, 0x9F95, 0xF7CF, 0x9FA2, 0xF7D0, 0x513D, 0xF7D1, 0x5299, 0xF7D2, 0x58E8, 0xF7D3, 0x58E7, 0xF7D4, 0x5972, 0xF7D5, 0x5B4D, 0xF7D6, 0x5DD8, 0xF7D7, 0x882F, 0xF7D8, 0x5F4F, 0xF7D9, 0x6201, 0xF7DA, 0x6203, 0xF7DB, 0x6204, 0xF7DC, 0x6529, 0xF7DD, 0x6525, 0xF7DE, 0x6596, 0xF7DF, 0x66EB, 0xF7E0, 0x6B11, 0xF7E1, 0x6B12, 0xF7E2, 0x6B0F, 0xF7E3, 0x6BCA, 0xF7E4, 0x705B, 0xF7E5, 0x705A, 0xF7E6, 0x7222, 0xF7E7, 0x7382, 0xF7E8, 0x7381, 0xF7E9, 0x7383, 0xF7EA, 0x7670, 0xF7EB, 0x77D4, 0xF7EC, 0x7C67, 0xF7ED, 0x7C66, 0xF7EE, 0x7E95, 0xF7EF, 0x826C, 0xF7F0, 0x863A, 0xF7F1, 0x8640, 0xF7F2, 0x8639, 0xF7F3, 0x863C, 0xF7F4, 0x8631, 0xF7F5, 0x863B, 0xF7F6, 0x863E, 0xF7F7, 0x8830, 0xF7F8, 0x8832, 0xF7F9, 0x882E, 0xF7FA, 0x8833, 0xF7FB, 0x8976, 0xF7FC, 0x8974, 0xF7FD, 0x8973, 0xF7FE, 0x89FE, 0xF840, 0x8B8C, 0xF841, 0x8B8E, 0xF842, 0x8B8B, 0xF843, 0x8B88, 0xF844, 0x8C45, 0xF845, 0x8D19, 0xF846, 0x8E98, 0xF847, 0x8F64, 0xF848, 0x8F63, 0xF849, 0x91BC, 0xF84A, 0x9462, 0xF84B, 0x9455, 0xF84C, 0x945D, 0xF84D, 0x9457, 0xF84E, 0x945E, 0xF84F, 0x97C4, 0xF850, 0x97C5, 0xF851, 0x9800, 0xF852, 0x9A56, 0xF853, 0x9A59, 0xF854, 0x9B1E, 0xF855, 0x9B1F, 0xF856, 0x9B20, 0xF857, 0x9C52, 0xF858, 0x9C58, 0xF859, 0x9C50, 0xF85A, 0x9C4A, 0xF85B, 0x9C4D, 0xF85C, 0x9C4B, 0xF85D, 0x9C55, 0xF85E, 0x9C59, 0xF85F, 0x9C4C, 0xF860, 0x9C4E, 0xF861, 0x9DFB, 0xF862, 0x9DF7, 0xF863, 0x9DEF, 0xF864, 0x9DE3, 0xF865, 0x9DEB, 0xF866, 0x9DF8, 0xF867, 0x9DE4, 0xF868, 0x9DF6, 0xF869, 0x9DE1, 0xF86A, 0x9DEE, 0xF86B, 0x9DE6, 0xF86C, 0x9DF2, 0xF86D, 0x9DF0, 0xF86E, 0x9DE2, 0xF86F, 0x9DEC, 0xF870, 0x9DF4, 0xF871, 0x9DF3, 0xF872, 0x9DE8, 0xF873, 0x9DED, 0xF874, 0x9EC2, 0xF875, 0x9ED0, 0xF876, 0x9EF2, 0xF877, 0x9EF3, 0xF878, 0x9F06, 0xF879, 0x9F1C, 0xF87A, 0x9F38, 0xF87B, 0x9F37, 0xF87C, 0x9F36, 0xF87D, 0x9F43, 0xF87E, 0x9F4F, 0xF8A1, 0x9F71, 0xF8A2, 0x9F70, 0xF8A3, 0x9F6E, 0xF8A4, 0x9F6F, 0xF8A5, 0x56D3, 0xF8A6, 0x56CD, 0xF8A7, 0x5B4E, 0xF8A8, 0x5C6D, 0xF8A9, 0x652D, 0xF8AA, 0x66ED, 0xF8AB, 0x66EE, 0xF8AC, 0x6B13, 0xF8AD, 0x705F, 0xF8AE, 0x7061, 0xF8AF, 0x705D, 0xF8B0, 0x7060, 0xF8B1, 0x7223, 0xF8B2, 0x74DB, 0xF8B3, 0x74E5, 0xF8B4, 0x77D5, 0xF8B5, 0x7938, 0xF8B6, 0x79B7, 0xF8B7, 0x79B6, 0xF8B8, 0x7C6A, 0xF8B9, 0x7E97, 0xF8BA, 0x7F89, 0xF8BB, 0x826D, 0xF8BC, 0x8643, 0xF8BD, 0x8838, 0xF8BE, 0x8837, 0xF8BF, 0x8835, 0xF8C0, 0x884B, 0xF8C1, 0x8B94, 0xF8C2, 0x8B95, 0xF8C3, 0x8E9E, 0xF8C4, 0x8E9F, 0xF8C5, 0x8EA0, 0xF8C6, 0x8E9D, 0xF8C7, 0x91BE, 0xF8C8, 0x91BD, 0xF8C9, 0x91C2, 0xF8CA, 0x946B, 0xF8CB, 0x9468, 0xF8CC, 0x9469, 0xF8CD, 0x96E5, 0xF8CE, 0x9746, 0xF8CF, 0x9743, 0xF8D0, 0x9747, 0xF8D1, 0x97C7, 0xF8D2, 0x97E5, 0xF8D3, 0x9A5E, 0xF8D4, 0x9AD5, 0xF8D5, 0x9B59, 0xF8D6, 0x9C63, 0xF8D7, 0x9C67, 0xF8D8, 0x9C66, 0xF8D9, 0x9C62, 0xF8DA, 0x9C5E, 0xF8DB, 0x9C60, 0xF8DC, 0x9E02, 0xF8DD, 0x9DFE, 0xF8DE, 0x9E07, 0xF8DF, 0x9E03, 0xF8E0, 0x9E06, 0xF8E1, 0x9E05, 0xF8E2, 0x9E00, 0xF8E3, 0x9E01, 0xF8E4, 0x9E09, 0xF8E5, 0x9DFF, 0xF8E6, 0x9DFD, 0xF8E7, 0x9E04, 0xF8E8, 0x9EA0, 0xF8E9, 0x9F1E, 0xF8EA, 0x9F46, 0xF8EB, 0x9F74, 0xF8EC, 0x9F75, 0xF8ED, 0x9F76, 0xF8EE, 0x56D4, 0xF8EF, 0x652E, 0xF8F0, 0x65B8, 0xF8F1, 0x6B18, 0xF8F2, 0x6B19, 0xF8F3, 0x6B17, 0xF8F4, 0x6B1A, 0xF8F5, 0x7062, 0xF8F6, 0x7226, 0xF8F7, 0x72AA, 0xF8F8, 0x77D8, 0xF8F9, 0x77D9, 0xF8FA, 0x7939, 0xF8FB, 0x7C69, 0xF8FC, 0x7C6B, 0xF8FD, 0x7CF6, 0xF8FE, 0x7E9A, 0xF940, 0x7E98, 0xF941, 0x7E9B, 0xF942, 0x7E99, 0xF943, 0x81E0, 0xF944, 0x81E1, 0xF945, 0x8646, 0xF946, 0x8647, 0xF947, 0x8648, 0xF948, 0x8979, 0xF949, 0x897A, 0xF94A, 0x897C, 0xF94B, 0x897B, 0xF94C, 0x89FF, 0xF94D, 0x8B98, 0xF94E, 0x8B99, 0xF94F, 0x8EA5, 0xF950, 0x8EA4, 0xF951, 0x8EA3, 0xF952, 0x946E, 0xF953, 0x946D, 0xF954, 0x946F, 0xF955, 0x9471, 0xF956, 0x9473, 0xF957, 0x9749, 0xF958, 0x9872, 0xF959, 0x995F, 0xF95A, 0x9C68, 0xF95B, 0x9C6E, 0xF95C, 0x9C6D, 0xF95D, 0x9E0B, 0xF95E, 0x9E0D, 0xF95F, 0x9E10, 0xF960, 0x9E0F, 0xF961, 0x9E12, 0xF962, 0x9E11, 0xF963, 0x9EA1, 0xF964, 0x9EF5, 0xF965, 0x9F09, 0xF966, 0x9F47, 0xF967, 0x9F78, 0xF968, 0x9F7B, 0xF969, 0x9F7A, 0xF96A, 0x9F79, 0xF96B, 0x571E, 0xF96C, 0x7066, 0xF96D, 0x7C6F, 0xF96E, 0x883C, 0xF96F, 0x8DB2, 0xF970, 0x8EA6, 0xF971, 0x91C3, 0xF972, 0x9474, 0xF973, 0x9478, 0xF974, 0x9476, 0xF975, 0x9475, 0xF976, 0x9A60, 0xF977, 0x9C74, 0xF978, 0x9C73, 0xF979, 0x9C71, 0xF97A, 0x9C75, 0xF97B, 0x9E14, 0xF97C, 0x9E13, 0xF97D, 0x9EF6, 0xF97E, 0x9F0A, 0xF9A1, 0x9FA4, 0xF9A2, 0x7068, 0xF9A3, 0x7065, 0xF9A4, 0x7CF7, 0xF9A5, 0x866A, 0xF9A6, 0x883E, 0xF9A7, 0x883D, 0xF9A8, 0x883F, 0xF9A9, 0x8B9E, 0xF9AA, 0x8C9C, 0xF9AB, 0x8EA9, 0xF9AC, 0x8EC9, 0xF9AD, 0x974B, 0xF9AE, 0x9873, 0xF9AF, 0x9874, 0xF9B0, 0x98CC, 0xF9B1, 0x9961, 0xF9B2, 0x99AB, 0xF9B3, 0x9A64, 0xF9B4, 0x9A66, 0xF9B5, 0x9A67, 0xF9B6, 0x9B24, 0xF9B7, 0x9E15, 0xF9B8, 0x9E17, 0xF9B9, 0x9F48, 0xF9BA, 0x6207, 0xF9BB, 0x6B1E, 0xF9BC, 0x7227, 0xF9BD, 0x864C, 0xF9BE, 0x8EA8, 0xF9BF, 0x9482, 0xF9C0, 0x9480, 0xF9C1, 0x9481, 0xF9C2, 0x9A69, 0xF9C3, 0x9A68, 0xF9C4, 0x9B2E, 0xF9C5, 0x9E19, 0xF9C6, 0x7229, 0xF9C7, 0x864B, 0xF9C8, 0x8B9F, 0xF9C9, 0x9483, 0xF9CA, 0x9C79, 0xF9CB, 0x9EB7, 0xF9CC, 0x7675, 0xF9CD, 0x9A6B, 0xF9CE, 0x9C7A, 0xF9CF, 0x9E1D, 0xF9D0, 0x7069, 0xF9D1, 0x706A, 0xF9D2, 0x9EA4, 0xF9D3, 0x9F7E, 0xF9D4, 0x9F49, 0xF9D5, 0x9F98, 0xF9D6, 0x7881, 0xF9D7, 0x92B9, 0xF9D8, 0x88CF, 0xF9D9, 0x58BB, 0xF9DA, 0x6052, 0xF9DB, 0x7CA7, 0xF9DC, 0x5AFA, 0xF9DD, 0x2554, 0xF9DE, 0x2566, 0xF9DF, 0x2557, 0xF9E0, 0x2560, 0xF9E1, 0x256C, 0xF9E2, 0x2563, 0xF9E3, 0x255A, 0xF9E4, 0x2569, 0xF9E5, 0x255D, 0xF9E6, 0x2552, 0xF9E7, 0x2564, 0xF9E8, 0x2555, 0xF9E9, 0x255E, 0xF9EA, 0x256A, 0xF9EB, 0x2561, 0xF9EC, 0x2558, 0xF9ED, 0x2567, 0xF9EE, 0x255B, 0xF9EF, 0x2553, 0xF9F0, 0x2565, 0xF9F1, 0x2556, 0xF9F2, 0x255F, 0xF9F3, 0x256B, 0xF9F4, 0x2562, 0xF9F5, 0x2559, 0xF9F6, 0x2568, 0xF9F7, 0x255C, 0xF9F8, 0x2551, 0xF9F9, 0x2550, 0xF9FA, 0x256D, 0xF9FB, 0x256E, 0xF9FC, 0x2570, 0xF9FD, 0x256F, 0xF9FE, 0x2593, 0, 0 }; #endif #if FF_CODE_PAGE == 437 || FF_CODE_PAGE == 0 static const WCHAR uc437[] = { /* CP437(U.S.) to Unicode conversion table */ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 720 || FF_CODE_PAGE == 0 static const WCHAR uc720[] = { /* CP720(Arabic) to Unicode conversion table */ 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 737 || FF_CODE_PAGE == 0 static const WCHAR uc737[] = { /* CP737(Greek) to Unicode conversion table */ 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 771 || FF_CODE_PAGE == 0 static const WCHAR uc771[] = { /* CP771(KBL) to Unicode conversion table */ 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x0104, 0x0105, 0x010C, 0x010D, 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, 0x0118, 0x0119, 0x0116, 0x0117, 0x012E, 0x012F, 0x0160, 0x0161, 0x0172, 0x0173, 0x016A, 0x016B, 0x017D, 0x017E, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 775 || FF_CODE_PAGE == 0 static const WCHAR uc775[] = { /* CP775(Baltic) to Unicode conversion table */ 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 850 || FF_CODE_PAGE == 0 static const WCHAR uc850[] = { /* CP850(Latin 1) to Unicode conversion table */ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 852 || FF_CODE_PAGE == 0 static const WCHAR uc852[] = { /* CP852(Latin 2) to Unicode conversion table */ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 855 || FF_CODE_PAGE == 0 static const WCHAR uc855[] = { /* CP855(Cyrillic) to Unicode conversion table */ 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 857 || FF_CODE_PAGE == 0 static const WCHAR uc857[] = { /* CP857(Turkish) to Unicode conversion table */ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 860 || FF_CODE_PAGE == 0 static const WCHAR uc860[] = { /* CP860(Portuguese) to Unicode conversion table */ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E3, 0x00E0, 0x00C1, 0x00E7, 0x00EA, 0x00CA, 0x00E8, 0x00CD, 0x00D4, 0x00EC, 0x00C3, 0x00C2, 0x00C9, 0x00C0, 0x00C8, 0x00F4, 0x00F5, 0x00F2, 0x00DA, 0x00F9, 0x00CC, 0x00D5, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x20A7, 0x00D3, 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00D2, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 861 || FF_CODE_PAGE == 0 static const WCHAR uc861[] = { /* CP861(Icelandic) to Unicode conversion table */ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00D0, 0x00F0, 0x00DE, 0x00C4, 0x00C5, 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00FE, 0x00FB, 0x00DD, 0x00FD, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192, 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00C1, 0x00CD, 0x00D3, 0x00DA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 862 || FF_CODE_PAGE == 0 static const WCHAR uc862[] = { /* CP862(Hebrew) to Unicode conversion table */ 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 863 || FF_CODE_PAGE == 0 static const WCHAR uc863[] = { /* CP863(Canadian French) to Unicode conversion table */ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00C2, 0x00E0, 0x00B6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x2017, 0x00C0, 0x00C9, 0x00C8, 0x00CA, 0x00F4, 0x00CB, 0x00CF, 0x00FB, 0x00F9, 0x00A4, 0x00D4, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x00DB, 0x0192, 0x00A6, 0x00B4, 0x00F3, 0x00FA, 0x00A8, 0x00BB, 0x00B3, 0x00AF, 0x00CE, 0x3210, 0x00AC, 0x00BD, 0x00BC, 0x00BE, 0x00AB, 0x00BB, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2219, 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 864 || FF_CODE_PAGE == 0 static const WCHAR uc864[] = { /* CP864(Arabic) to Unicode conversion table */ 0x00B0, 0x00B7, 0x2219, 0x221A, 0x2592, 0x2500, 0x2502, 0x253C, 0x2524, 0x252C, 0x251C, 0x2534, 0x2510, 0x250C, 0x2514, 0x2518, 0x03B2, 0x221E, 0x03C6, 0x00B1, 0x00BD, 0x00BC, 0x2248, 0x00AB, 0x00BB, 0xFEF7, 0xFEF8, 0x0000, 0x0000, 0xFEFB, 0xFEFC, 0x0000, 0x00A0, 0x00AD, 0xFE82, 0x00A3, 0x00A4, 0xFE84, 0x0000, 0x20AC, 0xFE8E, 0xFE8F, 0xFE95, 0xFE99, 0x060C, 0xFE9D, 0xFEA1, 0xFEA5, 0x0660, 0x0661, 0x0662, 0x0663, 0x0664, 0x0665, 0x0666, 0x0667, 0x0668, 0x0669, 0xFED1, 0x061B, 0xFEB1, 0xFEB5, 0xFEB9, 0x061F, 0x00A2, 0xFE80, 0xFE81, 0xFE83, 0xFE85, 0xFECA, 0xFE8B, 0xFE8D, 0xFE91, 0xFE93, 0xFE97, 0xFE9B, 0xFE9F, 0xFEA3, 0xFEA7, 0xFEA9, 0xFEAB, 0xFEAD, 0xFEAF, 0xFEB3, 0xFEB7, 0xFEBB, 0xFEBF, 0xFEC1, 0xFEC5, 0xFECB, 0xFECF, 0x00A6, 0x00AC, 0x00F7, 0x00D7, 0xFEC9, 0x0640, 0xFED3, 0xFED7, 0xFEDB, 0xFEDF, 0xFEE3, 0xFEE7, 0xFEEB, 0xFEED, 0xFEEF, 0xFEF3, 0xFEBD, 0xFECC, 0xFECE, 0xFECD, 0xFEE1, 0xFE7D, 0x0651, 0xFEE5, 0xFEE9, 0xFEEC, 0xFEF0, 0xFEF2, 0xFED0, 0xFED5, 0xFEF5, 0xFEF6, 0xFEDD, 0xFED9, 0xFEF1, 0x25A0, 0x0000 }; #endif #if FF_CODE_PAGE == 865 || FF_CODE_PAGE == 0 static const WCHAR uc865[] = { /* CP865(Nordic) to Unicode conversion table */ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, 0x00C5, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192, 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00A4, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 866 || FF_CODE_PAGE == 0 static const WCHAR uc866[] = { /* CP866(Russian) to Unicode conversion table */ 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 }; #endif #if FF_CODE_PAGE == 869 || FF_CODE_PAGE == 0 static const WCHAR uc869[] = { /* CP869(Greek 2) to Unicode conversion table */ 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x0386, 0x00B7, 0x00B7, 0x00AC, 0x00A6, 0x2018, 0x2019, 0x0388, 0x2015, 0x0389, 0x038A, 0x03AA, 0x038C, 0x00B7, 0x00B7, 0x038E, 0x03AB, 0x00A9, 0x038F, 0x00B2, 0x00B3, 0x03AC, 0x00A3, 0x03AD, 0x03AE, 0x03AF, 0x03CA, 0x0390, 0x03CC, 0x03CD, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x00BD, 0x0398, 0x0399, 0x00AB, 0x00BB, 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x039A, 0x039B, 0x039C, 0x039D, 0x2563, 0x2551, 0x2557, 0x255D, 0x039E, 0x039F, 0x2510, 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0A30, 0x03A1, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x2518, 0x250C, 0x2588, 0x2584, 0x03B4, 0x03B5, 0x2580, 0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x0384, 0x00AD, 0x00B1, 0x03C5, 0x03C6, 0x03C7, 0x00A7, 0x03C8, 0x0385, 0x00B0, 0x00A8, 0x03C9, 0x03CB, 0x03B0, 0x03CE, 0x25A0, 0x00A0 }; #endif /*------------------------------------------------------------------------*/ /* OEM <==> Unicode conversions for static code page configuration */ /* SBCS fixed code page */ /*------------------------------------------------------------------------*/ #if FF_CODE_PAGE != 0 && FF_CODE_PAGE < 900 WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */ DWORD uni, /* UTF-16 encoded character to be converted */ WORD cp /* Code page for the conversion */ ) { WCHAR c = 0; const WCHAR *p = CVTBL(uc, FF_CODE_PAGE); if (uni < 0x80) { /* ASCII? */ c = (WCHAR)uni; } else { /* Non-ASCII */ if (uni < 0x10000 && cp == FF_CODE_PAGE) { /* Is it in BMP and valid code page? */ for (c = 0; c < 0x80 && uni != p[c]; c++) ; c = (c + 0x80) & 0xFF; } } return c; } WCHAR ff_oem2uni ( /* Returns Unicode character, zero on error */ WCHAR oem, /* OEM code to be converted */ WORD cp /* Code page for the conversion */ ) { WCHAR c = 0; const WCHAR *p = CVTBL(uc, FF_CODE_PAGE); if (oem < 0x80) { /* ASCII? */ c = oem; } else { /* Extended char */ if (cp == FF_CODE_PAGE) { /* Is it a valid code page? */ if (oem < 0x100) c = p[oem - 0x80]; } } return c; } #endif /*------------------------------------------------------------------------*/ /* OEM <==> Unicode conversions for static code page configuration */ /* DBCS fixed code page */ /*------------------------------------------------------------------------*/ #if FF_CODE_PAGE >= 900 WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */ DWORD uni, /* UTF-16 encoded character to be converted */ WORD cp /* Code page for the conversion */ ) { const WCHAR *p; WCHAR c = 0, uc; UINT i = 0, n, li, hi; if (uni < 0x80) { /* ASCII? */ c = (WCHAR)uni; } else { /* Non-ASCII */ if (uni < 0x10000 && cp == FF_CODE_PAGE) { /* Is it in BMP and valid code page? */ uc = (WCHAR)uni; p = CVTBL(uni2oem, FF_CODE_PAGE); hi = sizeof CVTBL(uni2oem, FF_CODE_PAGE) / 4 - 1; li = 0; for (n = 16; n; n--) { i = li + (hi - li) / 2; if (uc == p[i * 2]) break; if (uc > p[i * 2]) { li = i; } else { hi = i; } } if (n != 0) c = p[i * 2 + 1]; } } return c; } WCHAR ff_oem2uni ( /* Returns Unicode character, zero on error */ WCHAR oem, /* OEM code to be converted */ WORD cp /* Code page for the conversion */ ) { const WCHAR *p; WCHAR c = 0; UINT i = 0, n, li, hi; if (oem < 0x80) { /* ASCII? */ c = oem; } else { /* Extended char */ if (cp == FF_CODE_PAGE) { /* Is it valid code page? */ p = CVTBL(oem2uni, FF_CODE_PAGE); hi = sizeof CVTBL(oem2uni, FF_CODE_PAGE) / 4 - 1; li = 0; for (n = 16; n; n--) { i = li + (hi - li) / 2; if (oem == p[i * 2]) break; if (oem > p[i * 2]) { li = i; } else { hi = i; } } if (n != 0) c = p[i * 2 + 1]; } } return c; } #endif /*------------------------------------------------------------------------*/ /* OEM <==> Unicode conversions for dynamic code page configuration */ /*------------------------------------------------------------------------*/ #if FF_CODE_PAGE == 0 static const WORD cp_code[] = { 437, 720, 737, 771, 775, 850, 852, 855, 857, 860, 861, 862, 863, 864, 865, 866, 869, 0}; static const WCHAR* const cp_table[] = {uc437, uc720, uc737, uc771, uc775, uc850, uc852, uc855, uc857, uc860, uc861, uc862, uc863, uc864, uc865, uc866, uc869, 0}; WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */ DWORD uni, /* UTF-16 encoded character to be converted */ WORD cp /* Code page for the conversion */ ) { const WCHAR *p; WCHAR c = 0, uc; UINT i, n, li, hi; if (uni < 0x80) { /* ASCII? */ c = (WCHAR)uni; } else { /* Non-ASCII */ if (uni < 0x10000) { /* Is it in BMP? */ uc = (WCHAR)uni; p = 0; if (cp < 900) { /* SBCS */ for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ; /* Get conversion table */ p = cp_table[i]; if (p) { /* Is it valid code page ? */ for (c = 0; c < 0x80 && uc != p[c]; c++) ; /* Find OEM code in the table */ c = (c + 0x80) & 0xFF; } } else { /* DBCS */ switch (cp) { /* Get conversion table */ case 932 : p = uni2oem932; hi = sizeof uni2oem932 / 4 - 1; break; case 936 : p = uni2oem936; hi = sizeof uni2oem936 / 4 - 1; break; case 949 : p = uni2oem949; hi = sizeof uni2oem949 / 4 - 1; break; case 950 : p = uni2oem950; hi = sizeof uni2oem950 / 4 - 1; break; } if (p) { /* Is it valid code page? */ li = 0; for (n = 16; n; n--) { /* Find OEM code */ i = li + (hi - li) / 2; if (uc == p[i * 2]) break; if (uc > p[i * 2]) { li = i; } else { hi = i; } } if (n != 0) c = p[i * 2 + 1]; } } } } return c; } WCHAR ff_oem2uni ( /* Returns Unicode character, zero on error */ WCHAR oem, /* OEM code to be converted (DBC if >=0x100) */ WORD cp /* Code page for the conversion */ ) { const WCHAR *p; WCHAR c = 0; UINT i, n, li, hi; if (oem < 0x80) { /* ASCII? */ c = oem; } else { /* Extended char */ p = 0; if (cp < 900) { /* SBCS */ for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ; /* Get table */ p = cp_table[i]; if (p) { /* Is it a valid CP ? */ if (oem < 0x100) c = p[oem - 0x80]; } } else { /* DBCS */ switch (cp) { case 932 : p = oem2uni932; hi = sizeof oem2uni932 / 4 - 1; break; case 936 : p = oem2uni936; hi = sizeof oem2uni936 / 4 - 1; break; case 949 : p = oem2uni949; hi = sizeof oem2uni949 / 4 - 1; break; case 950 : p = oem2uni950; hi = sizeof oem2uni950 / 4 - 1; break; } if (p) { li = 0; for (n = 16; n; n--) { i = li + (hi - li) / 2; if (oem == p[i * 2]) break; if (oem > p[i * 2]) { li = i; } else { hi = i; } } if (n != 0) c = p[i * 2 + 1]; } } } return c; } #endif /*------------------------------------------------------------------------*/ /* Unicode up-case conversion */ /*------------------------------------------------------------------------*/ DWORD ff_wtoupper ( /* Returns up-converted code point */ DWORD uni /* Unicode code point to be up-converted */ ) { const WORD *p; WORD uc, bc, nc, cmd; static const WORD cvt1[] = { /* Compressed up conversion table for U+0000 - U+0FFF */ /* Basic Latin */ 0x0061,0x031A, /* Latin-1 Supplement */ 0x00E0,0x0317, 0x00F8,0x0307, 0x00FF,0x0001,0x0178, /* Latin Extended-A */ 0x0100,0x0130, 0x0132,0x0106, 0x0139,0x0110, 0x014A,0x012E, 0x0179,0x0106, /* Latin Extended-B */ 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, 0x01CD,0x0110, 0x01DD,0x0001,0x018E, 0x01DE,0x0112, 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, 0x01F8,0x0128, 0x0222,0x0112, 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, 0x0246,0x010A, /* IPA Extensions */ 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, /* Greek, Coptic */ 0x037B,0x0003,0x03FD,0x03FE,0x03FF, 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, 0x03B1,0x0311, 0x03C2,0x0002,0x03A3,0x03A3, 0x03C4,0x0308, 0x03CC,0x0003,0x038C,0x038E,0x038F, 0x03D8,0x0118, 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, /* Cyrillic */ 0x0430,0x0320, 0x0450,0x0710, 0x0460,0x0122, 0x048A,0x0136, 0x04C1,0x010E, 0x04CF,0x0001,0x04C0, 0x04D0,0x0144, /* Armenian */ 0x0561,0x0426, 0x0000 /* EOT */ }; static const WORD cvt2[] = { /* Compressed up conversion table for U+1000 - U+FFFF */ /* Phonetic Extensions */ 0x1D7D,0x0001,0x2C63, /* Latin Extended Additional */ 0x1E00,0x0196, 0x1EA0,0x015A, /* Greek Extended */ 0x1F00,0x0608, 0x1F10,0x0606, 0x1F20,0x0608, 0x1F30,0x0608, 0x1F40,0x0606, 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, 0x1F60,0x0608, 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, 0x1F80,0x0608, 0x1F90,0x0608, 0x1FA0,0x0608, 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, 0x1FCC,0x0001,0x1FC3, 0x1FD0,0x0602, 0x1FE0,0x0602, 0x1FE5,0x0001,0x1FEC, 0x1FF3,0x0001,0x1FFC, /* Letterlike Symbols */ 0x214E,0x0001,0x2132, /* Number forms */ 0x2170,0x0210, 0x2184,0x0001,0x2183, /* Enclosed Alphanumerics */ 0x24D0,0x051A, 0x2C30,0x042F, /* Latin Extended-C */ 0x2C60,0x0102, 0x2C67,0x0106, 0x2C75,0x0102, /* Coptic */ 0x2C80,0x0164, /* Georgian Supplement */ 0x2D00,0x0826, /* Full-width */ 0xFF41,0x031A, 0x0000 /* EOT */ }; if (uni < 0x10000) { /* Is it in BMP? */ uc = (WORD)uni; p = uc < 0x1000 ? cvt1 : cvt2; for (;;) { bc = *p++; /* Get the block base */ if (bc == 0 || uc < bc) break; /* Not matched? */ nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ if (uc < bc + nc) { /* In the block? */ switch (cmd) { case 0: uc = p[uc - bc]; break; /* Table conversion */ case 1: uc -= (uc - bc) & 1; break; /* Case pairs */ case 2: uc -= 16; break; /* Shift -16 */ case 3: uc -= 32; break; /* Shift -32 */ case 4: uc -= 48; break; /* Shift -48 */ case 5: uc -= 26; break; /* Shift -26 */ case 6: uc += 8; break; /* Shift +8 */ case 7: uc -= 80; break; /* Shift -80 */ case 8: uc -= 0x1C60; break; /* Shift -0x1C60 */ } break; } if (cmd == 0) p += nc; /* Skip table if needed */ } uni = uc; } return uni; } #endif /* #if FF_USE_LFN */ ================================================ FILE: Huawei_LiteOS/components/fs/fatfs/ff13b/source/integer.h ================================================ /*-------------------------------------------*/ /* Integer type definitions for FatFs module */ /*-------------------------------------------*/ #ifndef FF_INTEGER #define FF_INTEGER #ifdef _WIN32 /* FatFs development platform */ #include typedef unsigned __int64 QWORD; #else /* Embedded platform */ /* These types MUST be 16-bit or 32-bit */ typedef int INT; typedef unsigned int UINT; /* This type MUST be 8-bit */ typedef unsigned char BYTE; /* These types MUST be 16-bit */ typedef short SHORT; typedef unsigned short WORD; typedef unsigned short WCHAR; /* These types MUST be 32-bit */ typedef long LONG; typedef unsigned long DWORD; /* This type MUST be 64-bit (Remove this for ANSI C (C89) compatibility) */ typedef unsigned long long QWORD; #endif #endif ================================================ FILE: Huawei_LiteOS/components/fs/fatfs/los_fatfs.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /* Includes -----------------------------------------------------------------*/ #include #include #include #include "fs/sys/errno.h" #include "fs/sys/fcntl.h" #include "fs/sys/stat.h" #include "fs/los_vfs.h" #include "fs/los_fatfs.h" #include "los_printf.h" /* Defines ------------------------------------------------------------------*/ /* Typedefs -----------------------------------------------------------------*/ /* Macros -------------------------------------------------------------------*/ #ifndef MIN #define MIN(a,b) ((a) < (b) ? (a) : (b)) #endif #ifndef POINTER_ASSERT #define POINTER_ASSERT(p) \ if(p == NULL) \ { \ return -EINVAL; \ } #endif /* Local variables ----------------------------------------------------------*/ struct disk_mnt disk; /* Extern variables ---------------------------------------------------------*/ /* Global variables ---------------------------------------------------------*/ /* Private function prototypes ----------------------------------------------*/ /* Public functions ---------------------------------------------------------*/ static int ret_to_errno(FRESULT result) { int err = 0; switch (result) { case FR_OK: return 0; case FR_NO_PATH: err = ENOTDIR; break; case FR_NO_FILE: err = ENOENT; break; case FR_NO_FILESYSTEM: err = ENODEV; break; case FR_TOO_MANY_OPEN_FILES: err = ENFILE; break; case FR_INVALID_NAME: err = ENAMETOOLONG; break; case FR_INVALID_PARAMETER: case FR_INVALID_OBJECT: case FR_INT_ERR: err = EINVAL; break; case FR_INVALID_DRIVE: case FR_NOT_ENABLED: err = ENXIO; break; case FR_EXIST: err = EEXIST; break; case FR_DISK_ERR: case FR_NOT_READY: err = EIO; break; case FR_WRITE_PROTECTED: err = EROFS; break; case FR_LOCKED: err = EBUSY; break; case FR_DENIED: err = EISDIR; break; case FR_MKFS_ABORTED: err = EBUSY; break; case FR_NOT_ENOUGH_CORE: err = ENOMEM; break; case FR_TIMEOUT: err = ETIMEDOUT; break; default: err = EIO; break; } VFS_ERRNO_SET (err); return -err; } /** * @brief Links a compatible diskio driver/lun id and increments the number of active * linked drivers. * @note The number of linked drivers (volumes) is up to 10 due to FatFs limits. * @param drv: pointer to the disk IO Driver structure * @param lun : only used for USB Key Disk to add multi-lun management else the parameter must be equal to 0 * @retval Returns -1 in case of failure, otherwise return the drive (0 to volumes). */ static int fatfs_link_driver(const struct diskio_drv *drv, uint8_t lun) { int ret = -1; int i; if(disk.num >= FF_VOLUMES) return ret; for(i = 0; i < FF_VOLUMES; i++) { if(disk.dev[i].drv != 0) continue; disk.dev[disk.num].state = 0; disk.dev[disk.num].drv = drv; disk.dev[disk.num].lun = lun; disk.num++; return i; } return ret; } /** * @brief Unlinks a diskio driver and decrements the number of active linked * drivers. * @param drive: the disk drive (0 to volumes) * @param lun : not used * @retval Returns -1 in case of failure, otherwise return the drive (0 to volumes). */ static int fatfs_unlink_driver(uint8_t drive, uint8_t lun) { int ret = -1; if(disk.num >= 1 && drive < FF_VOLUMES) { if(disk.dev[drive].drv != 0) { disk.dev[drive].state= 0; disk.dev[drive].drv = 0; disk.dev[drive].lun = 0; disk.num--; return drive; } } return ret; } int fatfs_register(const struct diskio_drv *drv) { return fatfs_link_driver(drv, 0); } int fatfs_unregister(uint8_t drive) { return fatfs_unlink_driver(drive, 0); } static int fatfs_flags_get (int oflags) { int flags = 0; switch (oflags & O_ACCMODE) { case O_RDONLY: flags |= FA_READ; break; case O_WRONLY: flags |= FA_WRITE; break; case O_RDWR: flags |= FA_READ | FA_WRITE; break; default: break; } if (oflags & O_CREAT) { flags |= FA_OPEN_ALWAYS; } if ((oflags & O_CREAT) && (oflags & O_EXCL)) { flags |= FA_CREATE_NEW; } if (oflags & O_TRUNC) { flags |= FA_CREATE_ALWAYS; } if (oflags & O_APPEND) { flags |= FA_READ | FA_WRITE | FA_OPEN_APPEND; } return flags; } static int fatfs_op_open (struct file *file, const char *path_in_mp, int flags) { FRESULT res; FIL *fp; FILINFO info = {0}; fp = (FIL *) malloc (sizeof(FIL)); if (fp == NULL) { PRINT_ERR ("fail to malloc memory in FATFS, is needed," "make sure it is added\n"); return -EINVAL; } if (!(flags & O_CREAT) && (flags & O_TRUNC)) { res = f_stat(path_in_mp, &info); if(res != FR_OK) { free(fp); return res; } } res = f_open (fp, path_in_mp, fatfs_flags_get (flags)); if(res == FR_OK) { file->f_data = (void *) fp; } else { free(fp); } if (FR_LOCKED == res) { int err = 0; VFS_ERRNO_SET (EACCES); err = EACCES; return -err; } else { return ret_to_errno(res); } } static int fatfs_op_close (struct file *file) { FRESULT res; FIL *fp = (FIL *)file->f_data; POINTER_ASSERT(fp); res = f_close(fp); if(res == FR_OK) { free(fp); file->f_data = NULL; } return ret_to_errno(res); } static ssize_t fatfs_op_read (struct file *file, char *buff, size_t bytes) { ssize_t size = 0; FRESULT res; FIL *fp = (FIL *)file->f_data; if (buff == NULL || bytes == 0) return -EINVAL; POINTER_ASSERT(fp); res = f_read (fp, buff, bytes, (UINT *)&size); if(res != FR_OK) { PRINT_ERR ("failed to read, res=%d\n", res); return ret_to_errno(res); } return size; } static ssize_t fatfs_op_write (struct file *file, const char *buff, size_t bytes) { ssize_t size = 0; FRESULT res; FIL *fp = (FIL *)file->f_data; if (buff == NULL || bytes == 0) return -EINVAL; POINTER_ASSERT(fp); res = f_write (fp, buff, bytes, (UINT *)&size); if(res != FR_OK || size == 0) { PRINT_ERR ("failed to write, res=%d\n", res); return ret_to_errno(res); } return size; } static off_t fatfs_op_lseek (struct file *file, off_t off, int whence) { FIL *fp = (FIL *)file->f_data; POINTER_ASSERT(fp); switch (whence) { case 0: // SEEK_SET break; case 1: // SEEK_CUR off += f_tell(fp); break; case 2: // SEEK_END off += f_size(fp); break; default: ret_to_errno(FR_INVALID_PARAMETER); return -1; } if (off < 0) { return ret_to_errno(FR_INVALID_PARAMETER); } FRESULT res = f_lseek(fp, off); if (res == FR_OK) { return off; } else return ret_to_errno(res); } int fatfs_op_stat (struct mount_point *mp, const char *path_in_mp, struct stat *stat) { FRESULT res; FILINFO info = {0}; memset(stat, 0, sizeof(*stat)); res = f_stat(path_in_mp, &info); if (res == FR_OK) { stat->st_size = info.fsize; if (info.fattrib & AM_DIR) { stat->st_mode = S_IFDIR; } else { stat->st_mode = S_IFREG; } } return ret_to_errno(res); } static int fatfs_op_unlink (struct mount_point *mp, const char *path_in_mp) { FRESULT res = f_unlink(path_in_mp); if (FR_NO_PATH == res) { int err = 0; VFS_ERRNO_SET (ENOENT); err = ENOENT; return -err; } else { return ret_to_errno(res); } } static int fatfs_op_rename (struct mount_point *mp, const char *path_in_mp_old, const char *path_in_mp_new) { FRESULT res = f_rename(path_in_mp_old, path_in_mp_new); return ret_to_errno(res); } static int fatfs_op_sync (struct file *file) { FIL *fp = (FIL *)file->f_data; FRESULT res; POINTER_ASSERT(fp); res = f_sync(fp); return ret_to_errno(res); } static int fatfs_op_opendir (struct dir *dir, const char *path) { FRESULT res; DIR *dp; dp = (DIR *) malloc (sizeof (DIR)); if (dp == NULL) { PRINT_ERR ("fail to malloc memory in SPIFFS, is needed," "make sure it is added\n"); return -ENOMEM; } res = f_opendir(dp, path); if(res != FR_OK) { free(dp); return ret_to_errno(res); } dir->d_data = dp; dir->d_offset = 0; return FR_OK; } static int fatfs_op_readdir (struct dir *dir, struct dirent *dent) { FRESULT res; DIR *dp = (DIR *) dir->d_data; FILINFO e; int len; POINTER_ASSERT(dp); res = f_readdir(dp, &e); if (res != FR_OK) { return ret_to_errno(res); } len = MIN(sizeof(e.fname), LOS_MAX_DIR_NAME_LEN+1) - 1; strncpy ((char *)dent->name, (const char *) e.fname, len); dent->name [len] = '\0'; dent->size = e.fsize; if (e.fattrib == AM_DIR) { dent->type = VFS_TYPE_DIR; } else { dent->type = VFS_TYPE_FILE; } return FR_OK; } static int fatfs_op_closedir (struct dir *dir) { FRESULT res; DIR *dp = (DIR *) dir->d_data; POINTER_ASSERT(dp); res = f_closedir (dp); if(res == FR_OK) { free (dp); dir->d_data = NULL; } return ret_to_errno(res); } static int fatfs_op_mkdir(struct mount_point *mp, const char *path) { FRESULT res = f_mkdir(path); if (FR_NO_PATH == res) { int err = 0; VFS_ERRNO_SET (ENOENT); err = ENOENT; return -err; } else { return ret_to_errno(res); } } static struct file_ops fatfs_ops = { fatfs_op_open, fatfs_op_close, fatfs_op_read, fatfs_op_write, fatfs_op_lseek, fatfs_op_stat, fatfs_op_unlink, fatfs_op_rename, NULL, /* ioctl not supported for now */ fatfs_op_sync, fatfs_op_opendir, fatfs_op_readdir, fatfs_op_closedir, fatfs_op_mkdir }; static struct file_system fatfs_fs = { "fatfs", &fatfs_ops, NULL, 0 }; int fatfs_init (void) { static int fatfs_inited = FALSE; if (fatfs_inited) { return LOS_OK; } if (los_vfs_init () != LOS_OK) { return LOS_NOK; } if (los_fs_register (&fatfs_fs) != LOS_OK) { PRINT_ERR ("failed to register fs!\n"); return LOS_NOK; } fatfs_inited = TRUE; PRINT_INFO ("register fatfs done!\n"); return LOS_OK; } static FATFS *fatfs_ptr = NULL; int fatfs_mount(const char *path, struct diskio_drv *drv, uint8_t *drive) { int s_drive; char dpath[10] = {0}; int ret = -1; BYTE *work_buff = NULL; FRESULT res; FATFS *fs = NULL; s_drive = fatfs_register(drv); if(s_drive < 0) { PRINT_ERR("failed to register diskio!\n"); return s_drive; } fs = (FATFS *) malloc (sizeof (FATFS)); if (fs == NULL) { PRINT_ERR ("fail to malloc memory in FATFS, is needed," "make sure it is added\n"); goto err; } memset(fs, 0, sizeof(FATFS)); sprintf(dpath, "%d:/", s_drive); res = f_mount(fs, (const TCHAR *)dpath, 1); if(res == FR_NO_FILESYSTEM) { work_buff = (BYTE *)malloc(FF_MAX_SS); if(work_buff == NULL) goto err_free; memset(work_buff, 0, FF_MAX_SS); res = f_mkfs((const TCHAR *)dpath, FM_ANY, 0, work_buff, FF_MAX_SS); if(res == FR_OK) { res = f_mount(NULL, (const TCHAR *)dpath, 1); res = f_mount(fs, (const TCHAR *)dpath, 1); } free(work_buff); } if(res != FR_OK) { PRINT_ERR("failed to mount fatfs, res=%d!\n", res); goto err_free; } ret = los_fs_mount ("fatfs", path, fs); if (ret == LOS_OK) { PRINT_INFO ("fatfs mount at %s done!\n", path); *drive = s_drive; fatfs_ptr = fs; return LOS_OK; } PRINT_ERR ("failed to mount!\n"); err_free: if(fs != NULL) free(fs); err: fatfs_unregister(s_drive); return ret; } int fatfs_unmount(const char *path, uint8_t drive) { char dpath[10] = {0}; sprintf(dpath, "%d:/", drive); fatfs_unregister(drive); f_mount(NULL, (const TCHAR *)dpath, 1); los_fs_unmount(path); if (fatfs_ptr) { free(fatfs_ptr); fatfs_ptr = NULL; } return 0; } /* Private functions --------------------------------------------------------*/ ================================================ FILE: Huawei_LiteOS/components/fs/kifs/los_kifs.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include #include #include #include #ifdef __GNUC__ #include #endif #include #include #include struct kifs_node { char name [LOS_MAX_FILE_NAME_LEN]; uint32_t attr; /* R(readable)/W(writable)/E(exclusive)/D(dir)/B(buffer) */ struct kifs_node *sabling; struct kifs_node *parent; union { struct kifs_ops *kiops; /* kiops if is file with ops */ void *buff; /* buff addr, if file is linked to buffer */ struct kifs_node *child; /* child if is dir */ }; union { void *arg; /* arg for ops if is file with ops */ size_t size; /* buff size, if file is linked to buffer */ }; }; static struct kifs_node *kifs_file_find (struct kifs_node *root, const char *path_in_mp, const char **path_unresolved) { struct kifs_node *dir = root; while (1) { const char *c; struct kifs_node *t; int l; if ((dir->attr & KIFS_ATTR_D) == 0) { VFS_ERRNO_SET (ENOTDIR); return NULL; } while (*path_in_mp == '/') path_in_mp++; c = strchr (path_in_mp, '/'); if (c == NULL) { l = strlen (path_in_mp); } else { l = c - path_in_mp; } if (l >= LOS_MAX_FILE_NAME_LEN) { VFS_ERRNO_SET (ENAMETOOLONG); return NULL; } for (t = dir->child; t != NULL; t = t->sabling) { if ((strncmp (t->name, path_in_mp, l) == 0) && (t->name [l] == '\0')) { break; } } if (t == NULL) { break; /* no match */ } path_in_mp += l; dir = t; if (c == NULL) { break; } } *path_unresolved = path_in_mp; return dir; } static int kifs_open (struct file *file, const char *path_in_mp, int flags) { struct kifs_node *node; node = kifs_file_find ((struct kifs_node *) file->f_mp->m_data, path_in_mp, &path_in_mp); if (node == NULL) { return -1; } if (*path_in_mp != '\0') { VFS_ERRNO_SET (ENOENT); return -1; } if (node->attr & KIFS_ATTR_D) { VFS_ERRNO_SET (EISDIR); return -1; } file->f_data = (void *) node; if ((node->attr & KIFS_ATTR_B) != 0) { /* linked buffer do not have kiops */ return 0; } if (node->kiops->open == NULL) { return 0; /* if open is NULL, means the file do not need it! */ } return node->kiops->open (node->arg, flags); } static int kifs_close (struct file *file) { struct kifs_node *node = (struct kifs_node *) file->f_data; if (node == NULL) { return -1; } if (node->attr & KIFS_ATTR_B) { return 0; } if (node->kiops->close == NULL) { return 0; /* if close is NULL, means the file do not need it! */ } return node->kiops->close (node->arg); } static ssize_t kifs_read (struct file *file, char *buff, size_t bytes) { struct kifs_node *node = (struct kifs_node *) file->f_data; if ((node->attr & KIFS_ATTR_R) == 0) { VFS_ERRNO_SET (EACCES); return (ssize_t) - 1; } if (node->attr & KIFS_ATTR_B) { bytes = bytes > node->size ? node->size : bytes; memcpy (buff, node->buff, bytes); return bytes; } if (node->kiops->read == NULL) { VFS_ERRNO_SET (EACCES); return (ssize_t) - 1; } return node->kiops->read (node->arg, buff, bytes); } static ssize_t kifs_write (struct file *file, const char *buff, size_t bytes) { struct kifs_node *node = (struct kifs_node *) file->f_data; if ((node->attr & KIFS_ATTR_W) == 0) { VFS_ERRNO_SET (EACCES); return (ssize_t) - 1; } if (node->attr & KIFS_ATTR_B) { bytes = bytes > node->size ? node->size : bytes; memcpy (node->buff, buff, bytes); return bytes; } if (node->kiops->write == NULL) { VFS_ERRNO_SET (EACCES); return (ssize_t) - 1; } return node->kiops->write (node->arg, buff, bytes); } static int kifs_ioctl (struct file *file, int func, unsigned long arg) { struct kifs_node *node = (struct kifs_node *) file->f_data; if (node->attr & KIFS_ATTR_B) { return -1; } if (node->kiops->ioctl == NULL) { return -1; } /* arg> is the private data for this kifile, the is the one * of ioctl */ return node->kiops->ioctl (node->arg, func, arg); } static int kifs_opendir (struct dir *dir, const char *path_in_mp) { struct kifs_node *node; node = kifs_file_find ((struct kifs_node *) dir->d_mp->m_data, path_in_mp, &path_in_mp); if ((node == NULL) || (*path_in_mp != '\0')) { VFS_ERRNO_SET (ENOENT); return -1; } if ((node->attr & KIFS_ATTR_D) == 0) { VFS_ERRNO_SET (ENOTDIR); return -1; } dir->d_data = (void *) node; dir->d_offset = 0; return 0; } static int kifs_readdir (struct dir *dir, struct dirent *dent) { struct kifs_node *node = (struct kifs_node *) dir->d_data; struct kifs_node *child; off_t i; if (node == NULL) { return -1; } for (i = 0, child = node->child; i < dir->d_offset && child != NULL; i++, child = child->sabling) { /* nop */ } if (child == NULL) { VFS_ERRNO_SET (ENOENT); return -1; } strncpy (dent->name, child->name, LOS_MAX_FILE_NAME_LEN - 1); dent->name [LOS_MAX_FILE_NAME_LEN - 1] = '\0'; dent->size = 0; if ((child->attr & KIFS_ATTR_D) != 0) { dent->type = VFS_TYPE_DIR; } else { dent->type = VFS_TYPE_FILE; dent->size = child->size; } dir->d_offset++; return 0; } static int kifs_closedir (struct dir *dir) { return 0; } static struct file_ops kifs_ops = { kifs_open, kifs_close, kifs_read, kifs_write, NULL, /* lseek not suported */ NULL, /* stat not supported */ NULL, /* unlink not supported */ NULL, /* rename not supported */ kifs_ioctl, /* ioctl not supported */ NULL, /* sync not supported */ kifs_opendir, kifs_readdir, kifs_closedir, NULL /* mkdir not supported */ }; static struct file_system kifs_fs = { "kifs", &kifs_ops, NULL, 0 }; static struct kifs_node *kifs_file_creat (void *root, const char *path_in_mp, uint32_t flags) { struct kifs_node *dir; struct kifs_node *node; const char *t; if (path_in_mp [strlen (path_in_mp) - 1] == '/') { return NULL; } dir = kifs_file_find ((struct kifs_node *) root, path_in_mp, &path_in_mp); if (dir == NULL) /* impossible */ { return NULL; } if (*path_in_mp == '\0') { return NULL; } if ((dir->attr & KIFS_ATTR_D) == 0) { return NULL; } while ((t = strchr (path_in_mp, '/')) != NULL) { if ((t - path_in_mp) >= LOS_MAX_FILE_NAME_LEN) { return NULL; } node = (struct kifs_node *) malloc (sizeof (struct kifs_node)); if (node == NULL) { PRINT_ERR ("fail to malloc memory in KIFS, is needed," "make sure it is added\n"); return NULL; } memset (node, 0, sizeof (struct kifs_node)); strncpy (node->name, path_in_mp, t - path_in_mp); node->parent = dir; node->sabling = dir->child; dir->child = node; node->attr = KIFS_ATTR_D; dir = node; path_in_mp = t + 1; while (*path_in_mp == '/') path_in_mp++; } if (*path_in_mp == '\0') { return NULL; } node = (struct kifs_node *) malloc (sizeof (struct kifs_node)); if (node == NULL) { PRINT_ERR ("fail to malloc memory in KIFS, is needed," "make sure it is added\n"); return NULL; } memset (node, 0, sizeof (struct kifs_node)); strcpy (node->name, path_in_mp); node->parent = dir; node->sabling = dir->child; dir->child = node; node->attr = flags; return node; } int los_kifs_create (void *root, const char *path_in_mp, uint32_t flags, struct kifs_ops *kiops, void *arg) { struct kifs_node *node; if ((kiops == NULL) || ((flags & (KIFS_ATTR_R | KIFS_ATTR_W)) == 0)) { return -1; } node = kifs_file_creat (root, path_in_mp, flags); if (node == NULL) { return -1; } node->kiops = kiops; node->arg = arg; return 0; } int los_kifs_link (void *root, const char *path_in_mp, uint32_t flags, void *buff, size_t size) { struct kifs_node *node; if ((buff == NULL) || ((flags & (KIFS_ATTR_R | KIFS_ATTR_W)) == 0)) { return -1; } node = kifs_file_creat (root, path_in_mp, flags); if (node == NULL) { return -1; } node->buff = buff; node->size = size; node->attr |= KIFS_ATTR_B; return 0; } void *los_kifs_mount (const char *path) { struct kifs_node *root; if (los_vfs_init () != LOS_OK) { PRINT_ERR ("vfs init fail!\n"); return NULL; } if (strlen (path) >= LOS_MAX_FILE_NAME_LEN) { return NULL; } root = (struct kifs_node *) malloc (sizeof (struct kifs_node)); if (root == NULL) { PRINT_ERR ("fail to malloc memory in KIFS, is needed," "make sure it is added\n"); return NULL; } memset (root, 0, sizeof (struct kifs_node)); strcpy (root->name, path); root->attr = KIFS_ATTR_D; if (los_fs_mount ("kifs", path, root) == LOS_OK) { return (void *) root; } free (root); return NULL; } int los_kifs_init (void) { static int kifs_inited = FALSE; if (kifs_inited) { return LOS_OK; } if (los_fs_register (&kifs_fs) != LOS_OK) { PRINT_ERR ("kifs fs register fail!\n"); return LOS_NOK; } kifs_inited = TRUE; return LOS_OK; } ================================================ FILE: Huawei_LiteOS/components/fs/ramfs/los_ramfs.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include #include #include #include #ifdef __GNUC__ #include #endif #if defined (__GNUC__) || defined (__CC_ARM) #include #include #endif #include "los_vfs.h" #define RAMFS_TYPE_DIR VFS_TYPE_DIR #define RAMFS_TYPE_FILE VFS_TYPE_FILE struct ramfs_element { char name [LOS_MAX_FILE_NAME_LEN]; uint32_t type; struct ramfs_element *sabling; struct ramfs_element *parent; volatile uint32_t refs; union { struct { size_t size; char *content; } f; struct { struct ramfs_element *child; } d; }; }; struct ramfs_mount_point { struct ramfs_element root; void *memory; }; static struct ramfs_element *ramfs_file_find (struct mount_point *mp, const char *path_in_mp, const char **path_unresolved) { struct ramfs_element *walk; /* walk every dir */ walk = &((struct ramfs_mount_point *) mp->m_data)->root; while (1) { const char *c; struct ramfs_element *t; int l; if (walk->type != RAMFS_TYPE_DIR) { VFS_ERRNO_SET (ENOTDIR); return NULL; } while (*path_in_mp == '/') path_in_mp++; c = strchr (path_in_mp, '/'); if (c == NULL) { l = strlen (path_in_mp); } else { l = c - path_in_mp; } if (l >= LOS_MAX_FILE_NAME_LEN) { VFS_ERRNO_SET (ENAMETOOLONG); return NULL; } for (t = walk->d.child; t != NULL; t = t->sabling) { if ((strncmp (t->name, path_in_mp, l) == 0) && (t->name [l] == '\0')) { break; } } if (t == NULL) { break; /* no match */ } path_in_mp += l; walk = t; if (c == NULL) { break; } } *path_unresolved = path_in_mp; return walk; } static int ramfs_open (struct file *file, const char *path_in_mp, int flags) { struct ramfs_element *ramfs_file; struct ramfs_element *walk; int ret = -1; /* openning dir like "/romfs/ not support " */ if (*path_in_mp == '\0') { VFS_ERRNO_SET (EISDIR); return ret; } walk = ramfs_file_find (file->f_mp, path_in_mp, &path_in_mp); if (walk == NULL) { /* errno set by ramfs_file_find */ return ret; } if ((walk->type == RAMFS_TYPE_DIR) && (*path_in_mp == '\0')) { VFS_ERRNO_SET (EISDIR); return -1; } if (*path_in_mp == '\0') /* file already exist, we found it */ { ramfs_file = walk; if (ramfs_file->type != RAMFS_TYPE_FILE) { VFS_ERRNO_SET (EISDIR); return -1; } if ((flags & O_CREAT) && (flags & O_EXCL)) { VFS_ERRNO_SET (EEXIST); return -1; } if (flags & O_APPEND) { file->f_offset = ramfs_file->f.size; } ramfs_file->refs++; file->f_data = (void *) ramfs_file; return 0; } /* * file not found, ramfs_file holds the most dir matched, path_in_mp holds * the left path not resolved */ if ((flags & O_CREAT) == 0) { VFS_ERRNO_SET (ENOENT); return -1; } if (walk->type != RAMFS_TYPE_DIR) { /* if here, BUG! */ VFS_ERRNO_SET (ENOTDIR); return -1; } if (strchr (path_in_mp, '/') != NULL) { VFS_ERRNO_SET (ENOENT); /* parent dir not exist */ return -1; } if (strlen (path_in_mp) >= LOS_MAX_FILE_NAME_LEN) { VFS_ERRNO_SET (ENAMETOOLONG); return -1; } ramfs_file = malloc (sizeof (struct ramfs_element)); if (ramfs_file == NULL) { PRINT_ERR ("fail to malloc memory in RAMFS, is needed," "make sure it is added\n"); VFS_ERRNO_SET (ENOMEM); return -1; } strcpy (ramfs_file->name, path_in_mp); /* length of path_in_mp is already verified */ ramfs_file->refs = 1; ramfs_file->type = RAMFS_TYPE_FILE; ramfs_file->sabling = walk->d.child; walk->d.child = ramfs_file; ramfs_file->f.content = NULL; ramfs_file->f.size = 0; ramfs_file->parent = walk; file->f_data = (void *) ramfs_file; return 0; } static int ramfs_close (struct file *file) { struct ramfs_element *ramfs_file = (struct ramfs_element *) file->f_data; ramfs_file->refs--; return 0; /* not file delete, do not free the content */ } static ssize_t ramfs_read (struct file *file, char *buff, size_t bytes) { struct ramfs_element *ramfs_file = (struct ramfs_element *) file->f_data; if (file->f_offset < 0) { file->f_offset = 0; } if (ramfs_file->f.size <= (size_t) file->f_offset) /* nothing to read */ { return 0; } if (ramfs_file->f.size - file->f_offset < bytes) { bytes = ramfs_file->f.size - file->f_offset; } memcpy (buff, ramfs_file->f.content + file->f_offset, bytes); file->f_offset += bytes; return bytes; } static ssize_t ramfs_write (struct file *file, const char *buff, size_t bytes) { struct mount_point *mp = file->f_mp; struct ramfs_element *ramfs_file = (struct ramfs_element *) file->f_data; if (file->f_offset < 0) { file->f_offset = 0; } if (file->f_offset + bytes > ramfs_file->f.size) { char *p; p = LOS_MemRealloc (((struct ramfs_mount_point *) mp->m_data)->memory, ramfs_file->f.content, file->f_offset + bytes); if (p != NULL) { ramfs_file->f.content = p; ramfs_file->f.size = file->f_offset + bytes; } else { if (ramfs_file->f.size <= (size_t) file->f_offset) { VFS_ERRNO_SET (ENOMEM); return (ssize_t) - 1; } bytes = ramfs_file->f.size - file->f_offset; } } memcpy (ramfs_file->f.content + file->f_offset, buff, bytes); file->f_offset += bytes; return bytes; } static off_t ramfs_lseek (struct file *file, off_t off, int whence) { struct ramfs_element *ramfs_file = (struct ramfs_element *) file->f_data; switch (whence) { case SEEK_SET: file->f_offset = off; break; case SEEK_CUR: file->f_offset += off; break; case SEEK_END: file->f_offset = ramfs_file->f.size; break; default: VFS_ERRNO_SET (EINVAL); return -1; } if (file->f_offset < 0) { file->f_offset = 0; } if ((size_t) file->f_offset > ramfs_file->f.size) { file->f_offset = ramfs_file->f.size; } return file->f_offset; } static void ramfs_del (struct ramfs_element *e) { struct ramfs_element *dir; struct ramfs_element *t; if (e->parent == NULL) /* root element, do not delete */ { return; } dir = e->parent; t = dir->d.child; if (t == e) { dir->d.child = e->sabling; } else { while (t->sabling != e) { t = t->sabling; } t->sabling = e->sabling; } free (e); } static int ramfs_unlink (struct mount_point *mp, const char *path_in_mp) { struct ramfs_element *ramfs_file; ramfs_file = ramfs_file_find (mp, path_in_mp, &path_in_mp); if ((ramfs_file == NULL) || (*path_in_mp != '\0')) { VFS_ERRNO_SET (ENOENT); return -1; } if (ramfs_file->refs != 0) { VFS_ERRNO_SET (EBUSY); return -1; } if (ramfs_file->type == RAMFS_TYPE_DIR) { if (ramfs_file->d.child != NULL) { VFS_ERRNO_SET (EBUSY); /* have file under it busy */ return -1; } } else { if (ramfs_file->f.content != NULL) { LOS_MemFree (((struct ramfs_mount_point *) mp->m_data)->memory, ramfs_file->f.content); ramfs_file->f.content = NULL; } } ramfs_del (ramfs_file); return 0; } static int ramfs_rename (struct mount_point *mp, const char *path_in_mp_old, const char *path_in_mp_new) { struct ramfs_element *ramfs_file_old; struct ramfs_element *ramfs_file_new; ramfs_file_old = ramfs_file_find (mp, path_in_mp_old, &path_in_mp_old); if ((ramfs_file_old == NULL) || (*path_in_mp_old != '\0')) { VFS_ERRNO_SET (ENOENT); return -1; } ramfs_file_new = ramfs_file_find (mp, path_in_mp_new, &path_in_mp_new); /* * ramfs_file_new == NULL means at least parent dir not found * *path_in_mp_new == '\0' means file already exist */ if ((ramfs_file_new == NULL) || (*path_in_mp_new == '\0')) { VFS_ERRNO_SET (ENOENT); return -1; } /* must in the same dir */ if (strchr (path_in_mp_new, '/') != NULL) { VFS_ERRNO_SET (EISDIR); return -1; } /* must in the same dir */ if (ramfs_file_new != ramfs_file_old->parent) { VFS_ERRNO_SET (EISDIR); return -1; } if (strlen (path_in_mp_new) >= LOS_MAX_FILE_NAME_LEN) { VFS_ERRNO_SET (ENAMETOOLONG); return -1; } strcpy (ramfs_file_old->name, path_in_mp_new); return 0; } static int ramfs_opendir (struct dir *dir, const char *path_in_mp) { struct ramfs_element *ramfs_dir; struct mount_point *mp = dir->d_mp; ramfs_dir = ramfs_file_find (mp, path_in_mp, &path_in_mp); if ((ramfs_dir == NULL) || (*path_in_mp != '\0')) { VFS_ERRNO_SET (ENOENT); return -1; } if (ramfs_dir->type != RAMFS_TYPE_DIR) { VFS_ERRNO_SET (ENOTDIR); return -1; } ramfs_dir->refs++; dir->d_data = (void *) ramfs_dir; dir->d_offset = 0; return 0; } static int ramfs_readdir (struct dir *dir, struct dirent *dent) { struct ramfs_element *ramfs_dir = (struct ramfs_element *) dir->d_data; struct ramfs_element *child; off_t i; for (i = 0, child = ramfs_dir->d.child; i < dir->d_offset && child != NULL; i++, child = child->sabling) { /* nop */ } if (NULL == child) { VFS_ERRNO_SET (ENOENT); return -1; } strncpy (dent->name, child->name, LOS_MAX_FILE_NAME_LEN - 1); dent->name [LOS_MAX_FILE_NAME_LEN - 1] = '\0'; dent->size = 0; if (child->type == RAMFS_TYPE_DIR) { dent->type = VFS_TYPE_DIR; } else { dent->type = VFS_TYPE_FILE; dent->size = child->f.size; } dir->d_offset++; return 0; } static int ramfs_closedir (struct dir *dir) { struct ramfs_element *ramfs_dir = (struct ramfs_element *) dir->d_data; ramfs_dir->refs--; return 0; } static int ramfs_mkdir (struct mount_point *mp, const char *path_in_mp) { struct ramfs_element *ramfs_parent; struct ramfs_element *ramfs_dir; const char *t; int len; ramfs_parent = ramfs_file_find (mp, path_in_mp, &path_in_mp); if ((ramfs_parent == NULL) || (*path_in_mp == '\0')) { return -1; /* dir already exist */ } t = strchr (path_in_mp, '/'); if (t != NULL) { len = t - path_in_mp; while (*t == '/') t++; if (*t != '\0') { return -1; /* creating dir under non-existed dir */ } } else { len = strlen (path_in_mp); } if (len >= LOS_MAX_FILE_NAME_LEN) { return -1; } ramfs_dir = (struct ramfs_element *) malloc (sizeof (struct ramfs_element)); if (ramfs_dir == NULL) { PRINT_ERR ("fail to malloc memory in RAMFS, is needed," "make sure it is added\n"); return -1; } memset (ramfs_dir, 0, sizeof (struct ramfs_element)); strncpy (ramfs_dir->name, path_in_mp, len); ramfs_dir->type = RAMFS_TYPE_DIR; ramfs_dir->sabling = ramfs_parent->d.child; ramfs_parent->d.child = ramfs_dir; ramfs_dir->parent = ramfs_parent; return 0; } static struct file_ops ramfs_ops = { ramfs_open, ramfs_close, ramfs_read, ramfs_write, ramfs_lseek, NULL, /* stat not supported */ ramfs_unlink, ramfs_rename, NULL, /* ioctl not supported */ NULL, /* sync not supported */ ramfs_opendir, ramfs_readdir, ramfs_closedir, ramfs_mkdir }; static struct file_system ramfs_fs = { "ramfs", &ramfs_ops, NULL, 0 }; int ramfs_mount (const char *path, size_t block_size) { struct ramfs_mount_point *rmp; if (strlen (path) >= LOS_MAX_FILE_NAME_LEN) { return LOS_NOK; } rmp = (struct ramfs_mount_point *) malloc (sizeof (struct ramfs_mount_point)); if (rmp == NULL) { PRINT_ERR ("fail to malloc memory in RAMFS, is needed," "make sure it is added\n"); return LOS_NOK; } memset (rmp, 0, sizeof (struct ramfs_mount_point)); rmp->root.type = RAMFS_TYPE_DIR; strncpy (rmp->root.name, path, LOS_MAX_FILE_NAME_LEN); rmp->memory = malloc (block_size); if (rmp->memory == NULL) { PRINT_ERR ("fail to malloc memory in RAMFS, is needed," "make sure it is added\n"); PRINT_ERR ("failed to allocate memory\n"); return LOS_NOK; } if (LOS_MemInit (rmp->memory, block_size) != LOS_OK) { PRINT_ERR ("failed to init pool\n"); free (rmp->memory); return LOS_NOK; } if (los_fs_mount ("ramfs", path, rmp) == LOS_OK) { PRINT_INFO ("ramfs mount at %s done!\n", path); return LOS_OK; } PRINT_ERR ("failed to register fs!\n"); free (rmp->memory); free (rmp); return LOS_NOK; } int ramfs_init (void) { static int ramfs_inited = FALSE; if (ramfs_inited) { return LOS_OK; } if (los_vfs_init () != LOS_OK) { PRINT_ERR ("vfs init fail!\n"); return LOS_NOK; } if (los_fs_register (&ramfs_fs) != LOS_OK) { PRINT_ERR ("failed to register fs!\n"); return LOS_NOK; } /* alloc 16KB memory as "disk" */ if (ramfs_mount ("/ramfs/", 16 * 1024) != LOS_OK) { PRINT_ERR ("failed to mount ramfs!\n"); return LOS_NOK; } PRINT_INFO ("register fs done!\n"); ramfs_inited = TRUE; return LOS_OK; } #ifdef DEBUG void ramfs_ls (struct ramfs_element *dir, int level) { struct ramfs_element *itr; int i; if (dir->type != RAMFS_TYPE_DIR) { return; } for (itr = dir->d.child; itr != NULL; itr = itr->sabling) { for (i = 0; i < level; i++) PRINTK (" "); PRINTK ("%s%c\n", itr->name, itr->type == RAMFS_TYPE_DIR ? '/' : '\0'); if (itr->type == RAMFS_TYPE_DIR) { ramfs_ls (itr, level + 1); } } } extern struct mount_point *los_mp_find (const char *, const char **); void ramfs_tree (const char *mount_path) { struct mount_point *mp = los_mp_find (mount_path, NULL); struct ramfs_element *walk; if (mp == NULL) { PRINT_ERR ("can not find mount point info for %s\n", mount_path); return; } walk = (struct ramfs_element *) mp->m_data; ramfs_ls (walk, 0); } #endif ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/README ================================================ spiffs适配参考代码：targets/Cloud_STM32F429IGTx_FIRE/Src/spiffs_stm32f4xx.c ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/los_spiffs.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /* NOTE: this is a demo for adapting the SPIFFS */ #include #include #include #include "fs/sys/errno.h" #include "fs/sys/fcntl.h" #include "fs/sys/stat.h" #include "fs/los_vfs.h" #include "los_printf.h" #include "spiffs.h" #include "spiffs_nucleus.h" static int ret_to_errno(int ret) { int err = 0; switch (ret) { case SPIFFS_OK: return 0; case SPIFFS_ERR_DATA_SPAN_MISMATCH: case SPIFFS_ERR_IS_INDEX: case SPIFFS_ERR_INDEX_REF_FREE: case SPIFFS_ERR_INDEX_REF_LU: case SPIFFS_ERR_INDEX_REF_INVALID: case SPIFFS_ERR_INDEX_FREE: case SPIFFS_ERR_INDEX_LU: case SPIFFS_ERR_INDEX_INVALID: case SPIFFS_ERR_CONFLICTING_NAME: case SPIFFS_ERR_INVALID_PARA: err = EINVAL; break; case SPIFFS_ERR_NOT_WRITABLE: case SPIFFS_ERR_NOT_READABLE: case SPIFFS_ERR_NOT_CONFIGURED: err = EACCES; break; case SPIFFS_ERR_NOT_MOUNTED: case SPIFFS_ERR_NOT_A_FS: case SPIFFS_ERR_PROBE_NOT_A_FS: case SPIFFS_ERR_MAGIC_NOT_POSSIBLE: err = ENODEV; break; case SPIFFS_ERR_FULL: case SPIFFS_ERR_PROBE_TOO_FEW_BLOCKS: err = ENOSPC; break; case SPIFFS_ERR_BAD_DESCRIPTOR: case SPIFFS_ERR_OUT_OF_FILE_DESCS: err = EBADF; break; case SPIFFS_ERR_MOUNTED: case SPIFFS_ERR_FILE_EXISTS: err = EEXIST; break; case SPIFFS_ERR_NOT_FOUND: case SPIFFS_ERR_NOT_A_FILE: case SPIFFS_ERR_DELETED: case SPIFFS_ERR_FILE_DELETED: case SPIFFS_ERR_NOT_FINALIZED: case SPIFFS_ERR_NOT_INDEX: case SPIFFS_ERR_IS_FREE: case SPIFFS_ERR_INDEX_SPAN_MISMATCH: case SPIFFS_ERR_FILE_CLOSED: err = ENOENT; break; case SPIFFS_ERR_NAME_TOO_LONG: err = ENAMETOOLONG; break; case SPIFFS_ERR_RO_NOT_IMPL: case SPIFFS_ERR_RO_ABORTED_OPERATION: err = EROFS; break; case SPIFFS_ERR_SEEK_BOUNDS: err = EOVERFLOW; break; case SPIFFS_ERR_END_OF_OBJECT: case SPIFFS_ERR_NO_DELETED_BLOCKS: err = ENODATA; break; case SPIFFS_ERR_ERASE_FAIL: err = EIO; break; default: err = EIO; break; } VFS_ERRNO_SET (err); return -err; } static int spiffs_flags_get (int oflags) { int flags = 0; switch (oflags & O_ACCMODE) { case O_RDONLY: flags |= SPIFFS_O_RDONLY; break; case O_WRONLY: flags |= SPIFFS_O_WRONLY; break; case O_RDWR: flags |= SPIFFS_O_RDWR; break; default: break; } if (oflags & O_CREAT) { flags |= SPIFFS_O_CREAT; } if (oflags & O_EXCL) { flags |= SPIFFS_O_EXCL; } if (oflags & O_TRUNC) { flags |= SPIFFS_O_TRUNC; } if (oflags & O_APPEND) { flags |= SPIFFS_O_CREAT | SPIFFS_O_APPEND; } return flags; } static int spiffs_op_open (struct file *file, const char *path_in_mp, int flags) { spiffs *fs = (spiffs *) file->f_mp->m_data; spiffs_file s_file; s_file = SPIFFS_open (fs, path_in_mp, spiffs_flags_get (flags), 0); if (s_file < SPIFFS_OK) { return ret_to_errno(s_file); } file->f_data = (void *) (uintptr_t) s_file; return 0; } static spiffs_file spifd_from_file (struct file *file) { return (spiffs_file) (uintptr_t) file->f_data; } static int spiffs_op_close (struct file *file) { spiffs_file s_file = spifd_from_file (file); spiffs *fs = (spiffs *) file->f_mp->m_data; s32_t res = SPIFFS_close (fs, s_file); return ret_to_errno(res); } static ssize_t spiffs_op_read (struct file *file, char *buff, size_t bytes) { if (buff == NULL || bytes == 0) return -EINVAL; spiffs_file s_file = spifd_from_file (file); spiffs *fs = (spiffs *) file->f_mp->m_data; s32_t res = SPIFFS_read (fs, s_file, buff, bytes); return res < 0 ? ret_to_errno(res) : res; } static ssize_t spiffs_op_write (struct file *file, const char *buff, size_t bytes) { if (buff == NULL || bytes == 0) return -EINVAL; spiffs_file s_file = spifd_from_file (file); spiffs *fs = (spiffs *) file->f_mp->m_data; s32_t res = SPIFFS_write (fs, s_file, (void *) buff, bytes); return res < 0 ? ret_to_errno(res) : res; } static off_t spiffs_op_lseek (struct file *file, off_t off, int whence) { spiffs_file s_file = spifd_from_file (file); spiffs *fs = (spiffs *) file->f_mp->m_data; s32_t res = SPIFFS_lseek (fs, s_file, off, whence); return res < 0 ? ret_to_errno(res) : res; } int spiffs_op_stat (struct mount_point *mp, const char *path_in_mp, struct stat *stat) { spiffs_stat s = {0}; memset(stat, 0, sizeof(*stat)); s32_t res = SPIFFS_stat((spiffs *)mp->m_data, path_in_mp, &s); if (res == SPIFFS_OK) { stat->st_size = s.size; if (s.type == SPIFFS_TYPE_DIR) { stat->st_mode = S_IFDIR; } else { stat->st_mode = S_IFREG; } } return ret_to_errno(res); } static int spiffs_op_unlink (struct mount_point *mp, const char *path_in_mp) { s32_t res = SPIFFS_remove ((spiffs *) mp->m_data, path_in_mp); return ret_to_errno(res); } static int spiffs_op_rename (struct mount_point *mp, const char *path_in_mp_old, const char *path_in_mp_new) { s32_t res = SPIFFS_rename ((spiffs *) mp->m_data, path_in_mp_old, path_in_mp_new); return ret_to_errno(res); } static int spiffs_op_sync (struct file *file) { spiffs_file s_file = spifd_from_file (file); spiffs *fs = (spiffs *) file->f_mp->m_data; s32_t res = SPIFFS_fflush (fs, s_file); return res < 0 ? ret_to_errno(res) : res; } static int spiffs_op_opendir (struct dir *dir, const char *path) { spiffs *fs = (spiffs *) dir->d_mp->m_data; spiffs_DIR *sdir; sdir = (spiffs_DIR *) malloc (sizeof (spiffs_DIR)); if (sdir == NULL) { PRINT_ERR ("fail to malloc memory in SPIFFS, is needed," "make sure it is added\n"); return -ENOMEM; } dir->d_data = (void *) SPIFFS_opendir (fs, path, sdir); dir->d_offset = 0; if (dir->d_data == 0) { free (sdir); return -ENOENT; } return LOS_OK; } int spiffs_op_readdir (struct dir *dir, struct dirent *dent) { struct spiffs_dirent e; if (NULL == SPIFFS_readdir ((spiffs_DIR *) dir->d_data, &e)) { return -ENOENT; } strncpy (dent->name, (const char *) e.name, LOS_MAX_FILE_NAME_LEN - 1); dent->name [LOS_MAX_FILE_NAME_LEN - 1] = '\0'; dent->size = e.size; if (e.type == SPIFFS_TYPE_DIR) { dent->type = VFS_TYPE_DIR; } else { dent->type = VFS_TYPE_FILE; } return LOS_OK; } static int spiffs_op_closedir (struct dir *dir) { spiffs_DIR *sdir = (spiffs_DIR *) dir->d_data; s32_t res = SPIFFS_closedir (sdir); free (sdir); return ret_to_errno(res); } static struct file_ops spiffs_ops = { spiffs_op_open, spiffs_op_close, spiffs_op_read, spiffs_op_write, spiffs_op_lseek, spiffs_op_stat, spiffs_op_unlink, spiffs_op_rename, NULL, /* ioctl not supported for now */ spiffs_op_sync, spiffs_op_opendir, spiffs_op_readdir, spiffs_op_closedir, NULL /* spiffs do not support mkdir */ }; static struct file_system spiffs_fs = { "spiffs", &spiffs_ops, NULL, 0 }; static spiffs *fs_ptr = NULL; static u8_t *wbuf_ptr = NULL; static u8_t *fds_ptr = NULL; static u8_t *cache_ptr = NULL; int spiffs_mount (const char *path, u32_t phys_addr, u32_t phys_size, u32_t phys_erase_block, u32_t log_block_size, u32_t log_page_size, s32_t (*spi_rd) (struct spiffs_t *, u32_t, u32_t, u8_t *), s32_t (*spi_wr) (struct spiffs_t *, u32_t, u32_t, u8_t *), s32_t (*spi_er) (struct spiffs_t *, u32_t, u32_t)) { spiffs *fs; spiffs_config c; u8_t *wbuf; u8_t *fds; u8_t *cache; int ret = -1; #define LOS_SPIFFS_FD_SIZE (sizeof (spiffs_fd) * 8) #define LOS_SPIFFS_CACHE_SIZE (((log_page_size + 32) * 4) + 40) fs = (spiffs *) malloc (sizeof (spiffs)); wbuf = (u8_t *) malloc (log_page_size * 2); fds = (u8_t *) malloc (LOS_SPIFFS_FD_SIZE); cache = (u8_t *) malloc (LOS_SPIFFS_CACHE_SIZE); if ((fs == NULL) || (wbuf == NULL) || (fds == NULL) || (cache == NULL)) { PRINT_ERR ("fail to malloc memory in SPIFFS, is needed," "make sure it is added\n"); goto err_free; } memset (fs, 0, sizeof (spiffs)); c.hal_read_f = spi_rd; c.hal_write_f = spi_wr; c.hal_erase_f = spi_er; c.log_block_size = log_block_size; c.log_page_size = log_page_size; c.phys_addr = phys_addr; c.phys_erase_block = phys_erase_block; c.phys_size = phys_size; c.fh_ix_offset = TEST_SPIFFS_FILEHDL_OFFSET; ret = SPIFFS_mount (fs, &c, wbuf, fds, LOS_SPIFFS_FD_SIZE, cache, LOS_SPIFFS_CACHE_SIZE, NULL); if (ret == SPIFFS_ERR_NOT_A_FS) { PRINT_INFO ("formating fs...\n"); SPIFFS_format (fs); ret = SPIFFS_mount (fs, &c, wbuf, fds, LOS_SPIFFS_FD_SIZE, cache, LOS_SPIFFS_CACHE_SIZE, NULL); } if (ret != SPIFFS_OK) { PRINT_ERR ("format fail!\n"); goto err_unmount; } ret = los_fs_mount ("spiffs", path, fs); if (ret == LOS_OK) { fs_ptr = fs; wbuf_ptr = wbuf; fds_ptr = fds; cache_ptr = cache; PRINT_INFO ("spiffs mount at %s done!\n", path); return LOS_OK; } PRINT_ERR ("failed to mount!\n"); err_unmount: SPIFFS_unmount (fs); err_free: if (fs != NULL) free (fs); if (wbuf != NULL) free (wbuf); if (fds != NULL) free (fds); if (cache != NULL) free (cache); return ret; } int spiffs_unmount(const char *path) { if (fs_ptr) { SPIFFS_unmount(fs_ptr); free(fs_ptr); fs_ptr = NULL; } if (wbuf_ptr) { free(wbuf_ptr); wbuf_ptr = NULL; } if (fds_ptr) { free(fds_ptr); fds_ptr = NULL; } if (cache_ptr) { free(cache_ptr); cache_ptr = NULL; } los_fs_unmount(path); return 0; } int spiffs_init (void) { static int spiffs_inited = FALSE; if (spiffs_inited) { return LOS_OK; } if (los_vfs_init () != LOS_OK) { return LOS_NOK; } if (los_fs_register (&spiffs_fs) != LOS_OK) { PRINT_ERR ("failed to register fs!\n"); return LOS_NOK; } spiffs_inited = TRUE; PRINT_INFO ("register spiffs done!\n"); return LOS_OK; } ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/FUZZING.md ================================================ # Fuzzing SPIFFS The SPIFFS test suite includes a test program designed for fuzzing with [AFL](http://lcamtuf.coredump.cx/afl/). This automatically exercises the SPIFFS API and verifies that the file system does not crash or interact incorrectly with the flash chip. There are two steps to fuzzing. The first is to build the test suite with the AFL version of gcc. The CC variable should point to your copy of afl-gcc. ``` make clean test CC=/usr/local/bin/afl-gcc ``` There is a new test `afl_test` that reads from stdin a list of commands and arguments. These are interpreted and executed on the API. The `afltests` directory contains a number of test cases that can be fed to the `afl_test` test. The second is to run this test suite under afl as follows (where findings is the output directory): ``` afl-fuzz -i afltests -o findings ./build/linux_spiffs_test -f afl_test ``` This run will take hours (or days) and will (hopefully) not find any crashes. If a crash (or hang) is found, then the input file that caused the crash is saved. This allows the specific test case to be debugged. ## Reducing the size of the file AFL comes with `afl-tmin` which can reduce the size of the test input file to make it easier to debug. ``` afl-tmin -i findings/crashes/ -o smalltest -- build/linux_spiffs_test -f afl_test ``` This will write a short version of the testcase file to `smalltest`. This can then be fed into the test program for debugging: ``` build/linux_spiffs_test -f afl_test < smalltest ``` This should still crash, but allows it to be run under a debugger. ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/LICENSE ================================================ The MIT License (MIT) Copyright (c) 2013-2017 Peter Andersson (pelleplutt1976gmail.com) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/README.md ================================================ # SPIFFS (SPI Flash File System) **V0.3.7** [![Build Status](https://travis-ci.org/pellepl/spiffs.svg?branch=master)](https://travis-ci.org/pellepl/spiffs) Copyright (c) 2013-2017 Peter Andersson (pelleplutt1976 at gmail.com) For legal stuff, see [LICENSE](https://github.com/pellepl/spiffs/blob/master/LICENSE). Basically, you may do whatever you want with the source. Use, modify, sell, print it out, roll it and smoke it - as long as I won't be held responsible. Love to hear feedback though! ## INTRODUCTION Spiffs is a file system intended for SPI NOR flash devices on embedded targets. Spiffs is designed with following characteristics in mind: - Small (embedded) targets, sparse RAM without heap - Only big areas of data (blocks) can be erased - An erase will reset all bits in block to ones - Writing pulls one to zeroes - Zeroes can only be pulled to ones by erase - Wear leveling ## BUILDING `mkdir build; make` Otherwise, configure the `builddir` variable towards the top of `makefile` as something opposed to the default `build`. Sanity check on the host via `make test` and refer to `.travis.yml` for the official in-depth testing procedure. See the wiki for [integrating](https://github.com/pellepl/spiffs/wiki/Integrate-spiffs) spiffs into projects and [spiffsimg](https://github.com/nodemcu/nodemcu-firmware/tree/master/tools/spiffsimg) from [nodemcu](https://github.com/nodemcu) is a good example on the subject. ## FEATURES What spiffs does: - Specifically designed for low ram usage - Uses statically sized ram buffers, independent of number of files - Posix-like api: open, close, read, write, seek, stat, etc - It can run on any NOR flash, not only SPI flash - theoretically also on embedded flash of a microprocessor - Multiple spiffs configurations can run on same target - and even on same SPI flash device - Implements static wear leveling - Built in file system consistency checks - Highly configurable What spiffs does not: - Presently, spiffs does not support directories. It produces a flat structure. Creating a file with path *tmp/myfile.txt* will create a file called *tmp/myfile.txt* instead of a *myfile.txt* under directory *tmp*. - It is not a realtime stack. One write operation might last much longer than another. - Poor scalability. Spiffs is intended for small memory devices - the normal sizes for SPI flashes. Going beyond ~128Mbyte is probably a bad idea. This is a side effect of the design goal to use as little ram as possible. - Presently, it does not detect or handle bad blocks. - One configuration, one binary. There's no generic spiffs binary that handles all types of configurations. ## NOTICE 0.4.0 is under construction. This is a full rewrite and will change the underlying structure. Hence, it will not be compatible with earlier versions of the filesystem. The API is the same, with minor modifications. Some config flags will be removed (as they are mandatory in 0.4.0) and some features might fall away until 0.4.1. If you have any worries or questions, it can be discussed in issue [#179](https://github.com/pellepl/spiffs/issues/179) ## MORE INFO See the [wiki](https://github.com/pellepl/spiffs/wiki) for [configuring](https://github.com/pellepl/spiffs/wiki/Configure-spiffs), [integrating](https://github.com/pellepl/spiffs/wiki/Integrate-spiffs), [using](https://github.com/pellepl/spiffs/wiki/Using-spiffs), and [optimizing](https://github.com/pellepl/spiffs/wiki/Performance-and-Optimizing) spiffs. For design, see [docs/TECH_SPEC](https://github.com/pellepl/spiffs/blob/master/docs/TECH_SPEC). For a generic spi flash driver, see [this](https://github.com/pellepl/spiflash_driver). ## HISTORY ### 0.3.7 - fixed prevent seeking to negative offsets #158 - fixed file descriptor offsets not updated for multiple fds on same file #157 - fixed cache page not closed for removed files #156 - fixed a lseek bug when seeking exactly to end of a fully indexed first level LUT #148 - fixed wear leveling issue #145 - fixed attempt to write out of bounds in flash #130, - set file offset when seeking over end #121 (thanks @sensslen) - fixed seeking in virgin files #120 (thanks @sensslen) - Optional file metadata #128 (thanks @cesanta) - AFL testing framework #100 #143 (thanks @pjsg) - Testframe updates New API functions: - `SPIFFS_update_meta, SPIFFS_fupdate_meta` - updates metadata for a file New config defines: - `SPIFFS_OBJ_META_LEN` - enable possibility to add extra metadata to files ### 0.3.6 - Fix range bug in index memory mapping #98 - Add index memory mapping #97 - Optimize SPIFFS_read for large files #96 - Add temporal cache for opening files #95 - More robust gc #93 (thanks @dismirlian) - Fixed a double write of same data in certain cache situations - Fixed an open bug in READ_ONLY builds - File not visible in SPIFFS_readdir #90 (thanks @benpicco-tmp) - Cache load code cleanup #92 (thanks @niclash) - Fixed lock/unlock asymmetry #88 #87 (thanks @JackJefferson, @dpruessner) - Testframe updates New API functions: - `SPIFFS_ix_map` - map index meta data to memory for a file - `SPIFFS_ix_unmap` - unmaps index meta data for a file - `SPIFFS_ix_remap` - changes file offset for index metadata map - `SPIFFS_bytes_to_ix_map_entries` - utility, get length of needed vector for given amount of bytes - `SPIFFS_ix_map_entries_to_bytes` - utility, get number of bytes a vector can represent given length New config defines: - `SPIFFS_IX_MAP` - enable possibility to map index meta data to memory for reading faster - `SPIFFS_TEMPORAL_FD_CACHE` - enable temporal cache for opening files faster - `SPIFFS_TEMPORAL_CACHE_HIT_SCORE` - for tuning the temporal cache ### 0.3.5 - Fixed a bug in fs check - API returns actual error codes #84) (thanks @Nails) - Fix compiler warnings for non-gcc #83 #81 (thanks @Nails) - Unable to recover from full fs #82 (thanks @rojer) - Define SPIFFS_O_* flags #80 - Problem with long filenames #79 (thanks @psjg) - Duplicate file name bug fix #74 (thanks @igrr) - SPIFFS_eof and SPIFFS_tell return wrong value #72 (thanks @ArtemPisarenko) - Bunch of testframe updates #77 #78 #86 (thanks @dpreussner, @psjg a.o) ### 0.3.4 - Added user callback file func. - Fixed a stat bug with obj id. - SPIFFS_probe_fs added - Add possibility to compile a read-only version of spiffs - Make magic dependent on fs length, if needed (see #59 & #66) (thanks @hreintke) - Exposed SPIFFS_open_by_page_function - Zero-size file cannot be seek #57 (thanks @lishen2) - Add tell and eof functions #54 (thanks @raburton) - Make api string params const #53 (thanks @raburton) - Preserve user_data during mount() #51 (thanks @rojer) New API functions: - `SPIFFS_set_file_callback_func` - register a callback informing about file events - `SPIFFS_probe_fs` - probe a spi flash trying to figure out size of fs - `SPIFFS_open_by_page` - open a file by page index - `SPIFFS_eof` - checks if end of file is reached - `SPIFFS_tell` - returns current file offset New config defines: - `SPIFFS_READ_ONLY` - `SPIFFS_USE_MAGIC_LENGTH` ### 0.3.3 **Might not be compatible with 0.3.2 structures. See issue #40** - Possibility to add integer offset to file handles - Truncate function presumes too few free pages #49 - Bug in truncate function #48 (thanks @PawelDefee) - Update spiffs_gc.c - remove unnecessary parameter (thanks @PawelDefee) - Update INTEGRATION docs (thanks @PawelDefee) - Fix pointer truncation in 64-bit platforms (thanks @igrr) - Zero-sized files cannot be read #44 (thanks @rojer) - (More) correct calculation of max_id in obj_lu_find #42 #41 (thanks @lishen2) - Check correct error code in obj_lu_find_free #41 (thanks @lishen2) - Moar comments for SPIFFS_lseek (thanks @igrr) - Fixed padding in spiffs_page_object_ix #40 (thanks @jmattsson @lishen2) - Fixed gc_quick test (thanks @jmattsson) - Add SPIFFS_EXCL flag #36 - SPIFFS_close may fail silently if cache is enabled #37 - User data in callbacks #34 - Ignoring SINGLETON build in cache setup (thanks Luca) - Compilation error fixed #32 (thanks @chotasanjiv) - Align cand_scores (thanks @hefloryd) - Fix build warnings when SPIFFS_CACHE is 0 (thanks @ajaybhargav) New config defines: - `SPIFFS_FILEHDL_OFFSET` ### 0.3.2 - Limit cache size if too much cache is given (thanks pgeiem) - New feature - Controlled erase. #23 - SPIFFS_rename leaks file descriptors #28 (thanks benpicco) - moved dbg print defines in test framework to params_test.h - lseek should return the resulting offset (thanks hefloryd) - fixed type on dbg ifdefs - silence warning about signed/unsigned comparison when spiffs_obj_id is 32 bit (thanks benpicco) - Possible error in test_spiffs.c #21 (thanks yihcdaso-yeskela) - Cache might writethrough too often #16 - even moar testrunner updates - Test framework update and some added tests - Some thoughts for next gen - Test sigsevs when having too many sectors #13 (thanks alonewolfx2) - GC might be suboptimal #11 - Fix eternal readdir when objheader at last block, last entry New API functions: - `SPIFFS_gc_quick` - call a nonintrusive gc - `SPIFFS_gc` - call a full-scale intrusive gc ### 0.3.1 - Removed two return warnings, was too triggerhappy on release ### 0.3.0 - Added existing namecheck when creating files - Lots of static analysis bugs #6 - Added rename func - Fix SPIFFS_read length when reading beyond file size - Added reading beyond file length testcase - Made build a bit more configurable - Changed name in spiffs from "errno" to "err_code" due to conflicts compiling in mingw - Improved GC checks, fixed an append bug, more robust truncate for very special case - GC checks preempts GC, truncate even less picky - Struct alignment needed for some targets, define in spiffs config #10 - Spiffs filesystem magic, definable in config New config defines: - `SPIFFS_USE_MAGIC` - enable or disable magic check upon mount - `SPIFFS_ALIGNED_OBJECT_INDEX_TABLES` - alignment for certain targets New API functions: - `SPIFFS_rename` - rename files - `SPIFFS_clearerr` - clears last errno - `SPIFFS_info` - returns info on used and total bytes in fs - `SPIFFS_format` - formats the filesystem - `SPIFFS_mounted` - checks if filesystem is mounted ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/docs/TECH_SPEC ================================================ * USING SPIFFS TODO * SPIFFS DESIGN Spiffs is inspired by YAFFS. However, YAFFS is designed for NAND flashes, and for bigger targets with much more ram. Nevertheless, many wise thoughts have been borrowed from YAFFS when writing spiffs. Kudos! The main complication writing spiffs was that it cannot be assumed the target has a heap. Spiffs must go along only with the work ram buffer given to it. This forces extra implementation on many areas of spiffs. ** SPI flash devices using NOR technology Below is a small description of how SPI flashes work internally. This is to give an understanding of the design choices made in spiffs. SPI flash devices are physically divided in blocks. On some SPI flash devices, blocks are further divided into sectors. Datasheets sometimes name blocks as sectors and vice versa. Common memory capacaties for SPI flashes are 512kB up to 8MB of data, where blocks may be 64kB. Sectors can be e.g. 4kB, if supported. Many SPI flashes have uniform block sizes, whereas others have non-uniform - the latter meaning that e.g. the first 16 blocks are 4kB big, and the rest are 64kB. The entire memory is linear and can be read and written in random access. Erasing can only be done block- or sectorwise; or by mass erase. SPI flashes can normally be erased from 100.000 up to 1.000.000 cycles before they fail. A clean SPI flash from factory have all bits in entire memory set to one. A mass erase will reset the device to this state. Block or sector erasing will put the all bits in the area given by the sector or block to ones. Writing to a NOR flash pulls ones to zeroes. Writing 0xFF to an address is simply a no-op. Writing 0b10101010 to a flash address holding 0b00001111 will yield 0b00001010. This way of "write by nand" is used considerably in spiffs. Common characteristics of NOR flashes are quick reads, but slow writes. And finally, unlike NAND flashes, NOR flashes seem to not need any error correction. They always write correctly I gather. ** Spiffs logical structure Some terminology before proceeding. Physical blocks/sectors means sizes stated in the datasheet. Logical blocks and pages is something the integrator choose. ** Blocks and pages Spiffs is allocated to a part or all of the memory of the SPI flash device. This area is divided into logical blocks, which in turn are divided into logical pages. The boundary of a logical block must coincide with one or more physical blocks. The sizes for logical blocks and logical pages always remain the same, they are uniform. Example: non-uniform flash mapped to spiffs with 128kB logical blocks PHYSICAL FLASH BLOCKS SPIFFS LOGICAL BLOCKS: 128kB +-----------------------+ - - - +-----------------------+ | Block 1 : 16kB | | Block 1 : 128kB | +-----------------------+ | | | Block 2 : 16kB | | | +-----------------------+ | | | Block 3 : 16kB | | | +-----------------------+ | | | Block 4 : 16kB | | | +-----------------------+ | | | Block 5 : 64kB | | | +-----------------------+ - - - +-----------------------+ | Block 6 : 64kB | | Block 2 : 128kB | +-----------------------+ | | | Block 7 : 64kB | | | +-----------------------+ - - - +-----------------------+ | Block 8 : 64kB | | Block 3 : 128kB | +-----------------------+ | | | Block 9 : 64kB | | | +-----------------------+ - - - +-----------------------+ | ... | | ... | A logical block is divided further into a number of logical pages. A page defines the smallest data holding element known to spiffs. Hence, if a file is created being one byte big, it will occupy one page for index and one page for data - it will occupy 2 x size of a logical page on flash. So it seems it is good to select a small page size. Each page has a metadata header being normally 5 to 9 bytes. This said, a very small page size will make metadata occupy a lot of the memory on the flash. A page size of 64 bytes will waste 8-14% on metadata, while 256 bytes 2-4%. So it seems it is good to select a big page size. Also, spiffs uses a ram buffer being two times the page size. This ram buffer is used for loading and manipulating pages, but it is also used for algorithms to find free file ids, scanning the file system, etc. Having too small a page size means less work buffer for spiffs, ending up in more reads operations and eventually gives a slower file system. Choosing the page size for the system involves many factors: - How big is the logical block size - What is the normal size of most files - How much ram can be spent - How much data (vs metadata) must be crammed into the file system - How fast must spiffs be - Other things impossible to find out So, chosing the Optimal Page Size (tm) seems tricky, to say the least. Don't fret - there is no optimal page size. This varies from how the target will use spiffs. Use the golden rule: ~~~ Logical Page Size = Logical Block Size / 256 ~~~ This is a good starting point. The final page size can then be derived through heuristical experimenting for us non-analytical minds. ** Objects, indices and look-ups A file, or an object as called in spiffs, is identified by an object id. Another YAFFS rip-off. This object id is a part of the page header. So, all pages know to which object/file they belong - not counting the free pages. An object is made up of two types of pages: object index pages and data pages. Data pages contain the data written by user. Index pages contain metadata about the object, more specifically what data pages are part of the object. The page header also includes something called a span index. Let's say a file is written covering three data pages. The first data page will then have span index 0, the second span index 1, and the last data page will have span index 2. Simple as that. Finally, each page header contain flags, telling if the page is used, deleted, finalized, holds index or data, and more. Object indices also have span indices, where an object index with span index 0 is referred to as the object index header. This page does not only contain references to data pages, but also extra info such as object name, object size in bytes, flags for file or directory, etc. If one were to create a file covering three data pages, named e.g. "spandex-joke.txt", given object id 12, it could look like this: PAGE 0 PAGE 1 page header: [obj_id:12 span_ix:0 flags:USED|DATA] PAGE 2 page header: [obj_id:12 span_ix:1 flags:USED|DATA] PAGE 3 page header: [obj_id:545 span_ix:13 flags:USED|DATA] PAGE 4 page header: [obj_id:12 span_ix:2 flags:USED|DATA] PAGE 5 page header: [obj_id:12 span_ix:0 flags:USED|INDEX] obj ix header: [name:spandex-joke.txt size:600 bytes flags:FILE] obj ix: [1 2 4] Looking in detail at page 5, the object index header page, the object index array refers to each data page in order, as mentioned before. The index of the object index array correlates with the data page span index. entry ix: 0 1 2 obj ix: [1 2 4] | | | PAGE 1, DATA, SPAN_IX 0 --------/ | | PAGE 2, DATA, SPAN_IX 1 --------/ | PAGE 4, DATA, SPAN_IX 2 --------/ Things to be unveiled in page 0 - well.. Spiffs is designed for systems low on ram. We cannot keep a dynamic list on the whereabouts of each object index header so we can find a file fast. There might not even be a heap! But, we do not want to scan all page headers on the flash to find the object index header. The first page(s) of each block contains the so called object look-up. These are not normal pages, they do not have a header. Instead, they are arrays pointing out what object-id the rest of all pages in the block belongs to. By this look-up, only the first page(s) in each block must to scanned to find the actual page which contains the object index header of the desired object. The object lookup is redundant metadata. The assumption is that it presents less overhead reading a full page of data to memory from each block and search that, instead of reading a small amount of data from each page (i.e. the page header) in all blocks. Each read operation from SPI flash normally contains extra data as the read command itself and the flash address. Also, depending on the underlying implementation, other criterions may need to be passed for each read transaction, like mutexes and such. The veiled example unveiled would look like this, with some extra pages: PAGE 0 [ 12 12 545 12 12 34 34 4 0 0 0 0 ...] PAGE 1 page header: [obj_id:12 span_ix:0 flags:USED|DATA] ... PAGE 2 page header: [obj_id:12 span_ix:1 flags:USED|DATA] ... PAGE 3 page header: [obj_id:545 span_ix:13 flags:USED|DATA] ... PAGE 4 page header: [obj_id:12 span_ix:2 flags:USED|DATA] ... PAGE 5 page header: [obj_id:12 span_ix:0 flags:USED|INDEX] ... PAGE 6 page header: [obj_id:34 span_ix:0 flags:USED|DATA] ... PAGE 7 page header: [obj_id:34 span_ix:1 flags:USED|DATA] ... PAGE 8 page header: [obj_id:4 span_ix:1 flags:USED|INDEX] ... PAGE 9 page header: [obj_id:23 span_ix:0 flags:DELETED|INDEX] ... PAGE 10 page header: [obj_id:23 span_ix:0 flags:DELETED|DATA] ... PAGE 11 page header: [obj_id:23 span_ix:1 flags:DELETED|DATA] ... PAGE 12 page header: [obj_id:23 span_ix:2 flags:DELETED|DATA] ... ... Ok, so why are page 9 to 12 marked as 0 when they belong to object id 23? These pages are deleted, so this is marked both in page header flags and in the look up. This is an example where spiffs uses NOR flashes "nand-way" of writing. As a matter of fact, there are two object id's which are special: obj id 0 (all bits zeroes) - indicates a deleted page in object look up obj id 0xff.. (all bits ones) - indicates a free page in object look up Actually, the object id's have another quirk: if the most significant bit is set, this indicates an object index page. If the most significant bit is zero, this indicates a data page. So to be fully correct, page 0 in above example would look like this: PAGE 0 [ 12 12 545 12 *12 34 34 *4 0 0 0 0 ...] where the asterisk means the msb of the object id is set. This is another way to speed up the searches when looking for object indices. By looking on the object id's msb in the object lookup, it is also possible to find out whether the page is an object index page or a data page. ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/docs/TODO ================================================ * When mending lost pages, also see if they fit into length specified in object index header SPIFFS2 thoughts * Instead of exact object id:s in the object lookup tables, use a hash of span index and object id. Eg. object id xor:ed with bit-reversed span index. This should decrease number of actual pages that needs to be visited when looking thru the obj lut. * Logical number of each block. When moving stuff in a garbage collected page, the free page is assigned the same number as the garbage collected. Thus, object index pages do not have to be rewritten. * Steal one page, use as a bit parity page. When starting an fs modification operation, write one bit as zero. When ending, write another bit as zero. On mount, if number of zeroes in page is uneven, a check is automatically run. ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/src/default/spiffs_config.h ================================================ /* * spiffs_config.h * * Created on: Jul 3, 2013 * Author: petera */ #ifndef SPIFFS_CONFIG_H_ #define SPIFFS_CONFIG_H_ #include #include "fs/los_vfs.h" // Physical offset(in bytes) in spi flash used for spiffs // Must be on 64k boundary #define SPIFFS_PHYS_ADDR 0 // Physical size(in bytes) of the spi flash used for spiffs // Must be on 64k boundary #define SPIFFS_PHYS_SIZE 0x100000 // compile time switches #define SPIFFS_USE_MAGIC 1 #define SPIFFS_USE_MAGIC_LENGTH 1 #define SPIFFS_HAL_CALLBACK_EXTRA 1 #define SPIFFS_FILEHDL_OFFSET 1 #define TEST_SPIFFS_FILEHDL_OFFSET 0x1000 #define SPIFFS_OBJ_NAME_LEN LOS_MAX_FILE_NAME_LEN // Set generic spiffs debug output call. #ifndef SPIFFS_DBG #define SPIFFS_DBG(_f, ...) //printf(_f, ## __VA_ARGS__) #endif // Set spiffs debug output call for garbage collecting. #ifndef SPIFFS_GC_DBG #define SPIFFS_GC_DBG(_f, ...) //printf(_f, ## __VA_ARGS__) #endif // Set spiffs debug output call for caching. #ifndef SPIFFS_CACHE_DBG #define SPIFFS_CACHE_DBG(_f, ...) //printf(_f, ## __VA_ARGS__) #endif // Set spiffs debug output call for system consistency checks. #ifndef SPIFFS_CHECK_DBG #define SPIFFS_CHECK_DBG(_f, ...) //printf(_f, ## __VA_ARGS__) #endif // Set spiffs debug output call for all api invocations. #ifndef SPIFFS_API_DBG #define SPIFFS_API_DBG(_f, ...) //printf(_f, ## __VA_ARGS__) #endif // Defines spiffs debug print formatters // some general signed number #ifndef _SPIPRIi #define _SPIPRIi "%ld" #endif // address #ifndef _SPIPRIad #define _SPIPRIad "%08x" #endif // block #ifndef _SPIPRIbl #define _SPIPRIbl "%04x" #endif // page #ifndef _SPIPRIpg #define _SPIPRIpg "%04x" #endif // span index #ifndef _SPIPRIsp #define _SPIPRIsp "%04x" #endif // file descriptor #ifndef _SPIPRIfd #define _SPIPRIfd "%d" #endif // file object id #ifndef _SPIPRIid #define _SPIPRIid "%04x" #endif // file flags #ifndef _SPIPRIfl #define _SPIPRIfl "%02x" #endif // Enable/disable API functions to determine exact number of bytes // for filedescriptor and cache buffers. Once decided for a configuration, // this can be disabled to reduce flash. #ifndef SPIFFS_BUFFER_HELP #define SPIFFS_BUFFER_HELP 0 #endif // Enables/disable memory read caching of nucleus file system operations. // If enabled, memory area must be provided for cache in SPIFFS_mount. #ifndef SPIFFS_CACHE #define SPIFFS_CACHE 1 #endif #if SPIFFS_CACHE // Enables memory write caching for file descriptors in hydrogen #ifndef SPIFFS_CACHE_WR #define SPIFFS_CACHE_WR 1 #endif // Enable/disable statistics on caching. Debug/test purpose only. #ifndef SPIFFS_CACHE_STATS #define SPIFFS_CACHE_STATS 1 #endif #endif // Always check header of each accessed page to ensure consistent state. // If enabled it will increase number of reads, will increase flash. #ifndef SPIFFS_PAGE_CHECK #define SPIFFS_PAGE_CHECK 1 #endif // Define maximum number of gc runs to perform to reach desired free pages. #ifndef SPIFFS_GC_MAX_RUNS #define SPIFFS_GC_MAX_RUNS 5 #endif // Enable/disable statistics on gc. Debug/test purpose only. #ifndef SPIFFS_GC_STATS #define SPIFFS_GC_STATS 1 #endif // Garbage collecting examines all pages in a block which and sums up // to a block score. Deleted pages normally gives positive score and // used pages normally gives a negative score (as these must be moved). // To have a fair wear-leveling, the erase age is also included in score, // whose factor normally is the most positive. // The larger the score, the more likely it is that the block will // picked for garbage collection. // Garbage collecting heuristics - weight used for deleted pages. #ifndef SPIFFS_GC_HEUR_W_DELET #define SPIFFS_GC_HEUR_W_DELET (5) #endif // Garbage collecting heuristics - weight used for used pages. #ifndef SPIFFS_GC_HEUR_W_USED #define SPIFFS_GC_HEUR_W_USED (-1) #endif // Garbage collecting heuristics - weight used for time between // last erased and erase of this block. #ifndef SPIFFS_GC_HEUR_W_ERASE_AGE #define SPIFFS_GC_HEUR_W_ERASE_AGE (50) #endif // Object name maximum length. Note that this length include the // zero-termination character, meaning maximum string of characters // can at most be SPIFFS_OBJ_NAME_LEN - 1. #ifndef SPIFFS_OBJ_NAME_LEN #define SPIFFS_OBJ_NAME_LEN (32) #endif // Maximum length of the metadata associated with an object. // Setting to non-zero value enables metadata-related API but also // changes the on-disk format, so the change is not backward-compatible. // // Do note: the meta length must never exceed // logical_page_size - (SPIFFS_OBJ_NAME_LEN + 64) // // This is derived from following: // logical_page_size - (SPIFFS_OBJ_NAME_LEN + sizeof(spiffs_page_header) + // spiffs_object_ix_header fields + at least some LUT entries) #ifndef SPIFFS_OBJ_META_LEN #define SPIFFS_OBJ_META_LEN (0) #endif // Size of buffer allocated on stack used when copying data. // Lower value generates more read/writes. No meaning having it bigger // than logical page size. #ifndef SPIFFS_COPY_BUFFER_STACK #define SPIFFS_COPY_BUFFER_STACK (64) #endif // Enable this to have an identifiable spiffs filesystem. This will look for // a magic in all sectors to determine if this is a valid spiffs system or // not on mount point. If not, SPIFFS_format must be called prior to mounting // again. #ifndef SPIFFS_USE_MAGIC #define SPIFFS_USE_MAGIC (0) #endif #if SPIFFS_USE_MAGIC // Only valid when SPIFFS_USE_MAGIC is enabled. If SPIFFS_USE_MAGIC_LENGTH is // enabled, the magic will also be dependent on the length of the filesystem. // For example, a filesystem configured and formatted for 4 megabytes will not // be accepted for mounting with a configuration defining the filesystem as 2 // megabytes. #ifndef SPIFFS_USE_MAGIC_LENGTH #define SPIFFS_USE_MAGIC_LENGTH (0) #endif #endif // SPIFFS_LOCK and SPIFFS_UNLOCK protects spiffs from reentrancy on api level // These should be defined on a multithreaded system // define this to enter a mutex if you're running on a multithreaded system #ifndef SPIFFS_LOCK #define SPIFFS_LOCK(fs) #endif // define this to exit a mutex if you're running on a multithreaded system #ifndef SPIFFS_UNLOCK #define SPIFFS_UNLOCK(fs) #endif // Enable if only one spiffs instance with constant configuration will exist // on the target. This will reduce calculations, flash and memory accesses. // Parts of configuration must be defined below instead of at time of mount. #ifndef SPIFFS_SINGLETON #define SPIFFS_SINGLETON 0 #endif #if SPIFFS_SINGLETON // Instead of giving parameters in config struct, singleton build must // give parameters in defines below. #ifndef SPIFFS_CFG_PHYS_SZ #define SPIFFS_CFG_PHYS_SZ(ignore) (1024*1024*2) #endif #ifndef SPIFFS_CFG_PHYS_ERASE_SZ #define SPIFFS_CFG_PHYS_ERASE_SZ(ignore) (65536) #endif #ifndef SPIFFS_CFG_PHYS_ADDR #define SPIFFS_CFG_PHYS_ADDR(ignore) (0) #endif #ifndef SPIFFS_CFG_LOG_PAGE_SZ #define SPIFFS_CFG_LOG_PAGE_SZ(ignore) (256) #endif #ifndef SPIFFS_CFG_LOG_BLOCK_SZ #define SPIFFS_CFG_LOG_BLOCK_SZ(ignore) (65536) #endif #endif // Enable this if your target needs aligned data for index tables #ifndef SPIFFS_ALIGNED_OBJECT_INDEX_TABLES #define SPIFFS_ALIGNED_OBJECT_INDEX_TABLES 0 #endif // Enable this if you want the HAL callbacks to be called with the spiffs struct #ifndef SPIFFS_HAL_CALLBACK_EXTRA #define SPIFFS_HAL_CALLBACK_EXTRA 0 #endif // Enable this if you want to add an integer offset to all file handles // (spiffs_file). This is useful if running multiple instances of spiffs on // same target, in order to recognise to what spiffs instance a file handle // belongs. // NB: This adds config field fh_ix_offset in the configuration struct when // mounting, which must be defined. #ifndef SPIFFS_FILEHDL_OFFSET #define SPIFFS_FILEHDL_OFFSET 0 #endif // Enable this to compile a read only version of spiffs. // This will reduce binary size of spiffs. All code comprising modification // of the file system will not be compiled. Some config will be ignored. // HAL functions for erasing and writing to spi-flash may be null. Cache // can be disabled for even further binary size reduction (and ram savings). // Functions modifying the fs will return SPIFFS_ERR_RO_NOT_IMPL. // If the file system cannot be mounted due to aborted erase operation and // SPIFFS_USE_MAGIC is enabled, SPIFFS_ERR_RO_ABORTED_OPERATION will be // returned. // Might be useful for e.g. bootloaders and such. #ifndef SPIFFS_READ_ONLY #define SPIFFS_READ_ONLY 0 #endif // Enable this to add a temporal file cache using the fd buffer. // The effects of the cache is that SPIFFS_open will find the file faster in // certain cases. It will make it a lot easier for spiffs to find files // opened frequently, reducing number of readings from the spi flash for // finding those files. // This will grow each fd by 6 bytes. If your files are opened in patterns // with a degree of temporal locality, the system is optimized. // Examples can be letting spiffs serve web content, where one file is the css. // The css is accessed for each html file that is opened, meaning it is // accessed almost every second time a file is opened. Another example could be // a log file that is often opened, written, and closed. // The size of the cache is number of given file descriptors, as it piggybacks // on the fd update mechanism. The cache lives in the closed file descriptors. // When closed, the fd know the whereabouts of the file. Instead of forgetting // this, the temporal cache will keep handling updates to that file even if the // fd is closed. If the file is opened again, the location of the file is found // directly. If all available descriptors become opened, all cache memory is // lost. #ifndef SPIFFS_TEMPORAL_FD_CACHE #define SPIFFS_TEMPORAL_FD_CACHE 1 #endif // Temporal file cache hit score. Each time a file is opened, all cached files // will lose one point. If the opened file is found in cache, that entry will // gain SPIFFS_TEMPORAL_CACHE_HIT_SCORE points. One can experiment with this // value for the specific access patterns of the application. However, it must // be between 1 (no gain for hitting a cached entry often) and 255. #ifndef SPIFFS_TEMPORAL_CACHE_HIT_SCORE #define SPIFFS_TEMPORAL_CACHE_HIT_SCORE 4 #endif // Enable to be able to map object indices to memory. // This allows for faster and more deterministic reading if cases of reading // large files and when changing file offset by seeking around a lot. // When mapping a file's index, the file system will be scanned for index pages // and the info will be put in memory provided by user. When reading, the // memory map can be looked up instead of searching for index pages on the // medium. This way, user can trade memory against performance. // Whole, parts of, or future parts not being written yet can be mapped. The // memory array will be owned by spiffs and updated accordingly during garbage // collecting or when modifying the indices. The latter is invoked by when the // file is modified in some way. The index buffer is tied to the file // descriptor. #ifndef SPIFFS_IX_MAP #define SPIFFS_IX_MAP 1 #endif // By default SPIFFS in some cases relies on the property of NOR flash that bits // cannot be set from 0 to 1 by writing and that controllers will ignore such // bit changes. This results in fewer reads as SPIFFS can in some cases perform // blind writes, with all bits set to 1 and only those it needs reset set to 0. // Most of the chips and controllers allow this behavior, so the default is to // use this technique. If your controller is one of the rare ones that don't, // turn this option on and SPIFFS will perform a read-modify-write instead. #ifndef SPIFFS_NO_BLIND_WRITES #define SPIFFS_NO_BLIND_WRITES 0 #endif // Set SPIFFS_TEST_VISUALISATION to non-zero to enable SPIFFS_vis function // in the api. This function will visualize all filesystem using given printf // function. #ifndef SPIFFS_TEST_VISUALISATION #define SPIFFS_TEST_VISUALISATION 1 #endif #if SPIFFS_TEST_VISUALISATION #ifndef spiffs_printf #define spiffs_printf(...) printf(__VA_ARGS__) #endif // spiffs_printf argument for a free page #ifndef SPIFFS_TEST_VIS_FREE_STR #define SPIFFS_TEST_VIS_FREE_STR "_" #endif // spiffs_printf argument for a deleted page #ifndef SPIFFS_TEST_VIS_DELE_STR #define SPIFFS_TEST_VIS_DELE_STR "/" #endif // spiffs_printf argument for an index page for given object id #ifndef SPIFFS_TEST_VIS_INDX_STR #define SPIFFS_TEST_VIS_INDX_STR(id) "i" #endif // spiffs_printf argument for a data page for given object id #ifndef SPIFFS_TEST_VIS_DATA_STR #define SPIFFS_TEST_VIS_DATA_STR(id) "d" #endif #endif typedef signed long s32_t; typedef unsigned long u32_t; typedef signed short s16_t; typedef unsigned short u16_t; typedef signed char s8_t; typedef unsigned char u8_t; // Types depending on configuration such as the amount of flash bytes // given to spiffs file system in total (spiffs_file_system_size), // the logical block size (log_block_size), and the logical page size // (log_page_size) // Block index type. Make sure the size of this type can hold // the highest number of all blocks - i.e. spiffs_file_system_size / log_block_size typedef u16_t spiffs_block_ix; // Page index type. Make sure the size of this type can hold // the highest page number of all pages - i.e. spiffs_file_system_size / log_page_size typedef u16_t spiffs_page_ix; // Object id type - most significant bit is reserved for index flag. Make sure the // size of this type can hold the highest object id on a full system, // i.e. 2 + (spiffs_file_system_size / (2*log_page_size))*2 typedef u16_t spiffs_obj_id; // Object span index type. Make sure the size of this type can // hold the largest possible span index on the system - // i.e. (spiffs_file_system_size / log_page_size) - 1 typedef u16_t spiffs_span_ix; #endif /* SPIFFS_CONFIG_H_ */ ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/src/spiffs.h ================================================ /* * spiffs.h * * Created on: May 26, 2013 * Author: petera */ #ifndef SPIFFS_H_ #define SPIFFS_H_ #if defined(__cplusplus) extern "C" { #endif #include "spiffs_config.h" #define SPIFFS_OK 0 #define SPIFFS_ERR_NOT_MOUNTED -10000 #define SPIFFS_ERR_FULL -10001 #define SPIFFS_ERR_NOT_FOUND -10002 #define SPIFFS_ERR_END_OF_OBJECT -10003 #define SPIFFS_ERR_DELETED -10004 #define SPIFFS_ERR_NOT_FINALIZED -10005 #define SPIFFS_ERR_NOT_INDEX -10006 #define SPIFFS_ERR_OUT_OF_FILE_DESCS -10007 #define SPIFFS_ERR_FILE_CLOSED -10008 #define SPIFFS_ERR_FILE_DELETED -10009 #define SPIFFS_ERR_BAD_DESCRIPTOR -10010 #define SPIFFS_ERR_IS_INDEX -10011 #define SPIFFS_ERR_IS_FREE -10012 #define SPIFFS_ERR_INDEX_SPAN_MISMATCH -10013 #define SPIFFS_ERR_DATA_SPAN_MISMATCH -10014 #define SPIFFS_ERR_INDEX_REF_FREE -10015 #define SPIFFS_ERR_INDEX_REF_LU -10016 #define SPIFFS_ERR_INDEX_REF_INVALID -10017 #define SPIFFS_ERR_INDEX_FREE -10018 #define SPIFFS_ERR_INDEX_LU -10019 #define SPIFFS_ERR_INDEX_INVALID -10020 #define SPIFFS_ERR_NOT_WRITABLE -10021 #define SPIFFS_ERR_NOT_READABLE -10022 #define SPIFFS_ERR_CONFLICTING_NAME -10023 #define SPIFFS_ERR_NOT_CONFIGURED -10024 #define SPIFFS_ERR_NOT_A_FS -10025 #define SPIFFS_ERR_MOUNTED -10026 #define SPIFFS_ERR_ERASE_FAIL -10027 #define SPIFFS_ERR_MAGIC_NOT_POSSIBLE -10028 #define SPIFFS_ERR_NO_DELETED_BLOCKS -10029 #define SPIFFS_ERR_FILE_EXISTS -10030 #define SPIFFS_ERR_NOT_A_FILE -10031 #define SPIFFS_ERR_RO_NOT_IMPL -10032 #define SPIFFS_ERR_RO_ABORTED_OPERATION -10033 #define SPIFFS_ERR_PROBE_TOO_FEW_BLOCKS -10034 #define SPIFFS_ERR_PROBE_NOT_A_FS -10035 #define SPIFFS_ERR_NAME_TOO_LONG -10036 #define SPIFFS_ERR_IX_MAP_UNMAPPED -10037 #define SPIFFS_ERR_IX_MAP_MAPPED -10038 #define SPIFFS_ERR_IX_MAP_BAD_RANGE -10039 #define SPIFFS_ERR_SEEK_BOUNDS -10040 #define SPIFFS_ERR_INVALID_PARA -10041 #define SPIFFS_ERR_INTERNAL -10050 #define SPIFFS_ERR_TEST -10100 // spiffs file descriptor index type. must be signed typedef s16_t spiffs_file; // spiffs file descriptor flags typedef u16_t spiffs_flags; // spiffs file mode typedef u16_t spiffs_mode; // object type typedef u8_t spiffs_obj_type; struct spiffs_t; #if SPIFFS_HAL_CALLBACK_EXTRA /* spi read call function type */ typedef s32_t (*spiffs_read)(struct spiffs_t *fs, u32_t addr, u32_t size, u8_t *dst); /* spi write call function type */ typedef s32_t (*spiffs_write)(struct spiffs_t *fs, u32_t addr, u32_t size, u8_t *src); /* spi erase call function type */ typedef s32_t (*spiffs_erase)(struct spiffs_t *fs, u32_t addr, u32_t size); #else // SPIFFS_HAL_CALLBACK_EXTRA /* spi read call function type */ typedef s32_t (*spiffs_read)(u32_t addr, u32_t size, u8_t *dst); /* spi write call function type */ typedef s32_t (*spiffs_write)(u32_t addr, u32_t size, u8_t *src); /* spi erase call function type */ typedef s32_t (*spiffs_erase)(u32_t addr, u32_t size); #endif // SPIFFS_HAL_CALLBACK_EXTRA /* file system check callback report operation */ typedef enum { SPIFFS_CHECK_LOOKUP = 0, SPIFFS_CHECK_INDEX, SPIFFS_CHECK_PAGE } spiffs_check_type; /* file system check callback report type */ typedef enum { SPIFFS_CHECK_PROGRESS = 0, SPIFFS_CHECK_ERROR, SPIFFS_CHECK_FIX_INDEX, SPIFFS_CHECK_FIX_LOOKUP, SPIFFS_CHECK_DELETE_ORPHANED_INDEX, SPIFFS_CHECK_DELETE_PAGE, SPIFFS_CHECK_DELETE_BAD_FILE } spiffs_check_report; /* file system check callback function */ #if SPIFFS_HAL_CALLBACK_EXTRA typedef void (*spiffs_check_callback)(struct spiffs_t *fs, spiffs_check_type type, spiffs_check_report report, u32_t arg1, u32_t arg2); #else // SPIFFS_HAL_CALLBACK_EXTRA typedef void (*spiffs_check_callback)(spiffs_check_type type, spiffs_check_report report, u32_t arg1, u32_t arg2); #endif // SPIFFS_HAL_CALLBACK_EXTRA /* file system listener callback operation */ typedef enum { /* the file has been created */ SPIFFS_CB_CREATED = 0, /* the file has been updated or moved to another page */ SPIFFS_CB_UPDATED, /* the file has been deleted */ SPIFFS_CB_DELETED } spiffs_fileop_type; /* file system listener callback function */ typedef void (*spiffs_file_callback)(struct spiffs_t *fs, spiffs_fileop_type op, spiffs_obj_id obj_id, spiffs_page_ix pix); #ifndef SPIFFS_DBG #define SPIFFS_DBG(...) \ printf(__VA_ARGS__) #endif #ifndef SPIFFS_GC_DBG #define SPIFFS_GC_DBG(...) printf(__VA_ARGS__) #endif #ifndef SPIFFS_CACHE_DBG #define SPIFFS_CACHE_DBG(...) printf(__VA_ARGS__) #endif #ifndef SPIFFS_CHECK_DBG #define SPIFFS_CHECK_DBG(...) printf(__VA_ARGS__) #endif /* Any write to the filehandle is appended to end of the file */ #define SPIFFS_APPEND (1<<0) #define SPIFFS_O_APPEND SPIFFS_APPEND /* If the opened file exists, it will be truncated to zero length before opened */ #define SPIFFS_TRUNC (1<<1) #define SPIFFS_O_TRUNC SPIFFS_TRUNC /* If the opened file does not exist, it will be created before opened */ #define SPIFFS_CREAT (1<<2) #define SPIFFS_O_CREAT SPIFFS_CREAT /* The opened file may only be read */ #define SPIFFS_RDONLY (1<<3) #define SPIFFS_O_RDONLY SPIFFS_RDONLY /* The opened file may only be written */ #define SPIFFS_WRONLY (1<<4) #define SPIFFS_O_WRONLY SPIFFS_WRONLY /* The opened file may be both read and written */ #define SPIFFS_RDWR (SPIFFS_RDONLY | SPIFFS_WRONLY) #define SPIFFS_O_RDWR SPIFFS_RDWR /* Any writes to the filehandle will never be cached but flushed directly */ #define SPIFFS_DIRECT (1<<5) #define SPIFFS_O_DIRECT SPIFFS_DIRECT /* If SPIFFS_O_CREAT and SPIFFS_O_EXCL are set, SPIFFS_open() shall fail if the file exists */ #define SPIFFS_EXCL (1<<6) #define SPIFFS_O_EXCL SPIFFS_EXCL #define SPIFFS_SEEK_SET (0) #define SPIFFS_SEEK_CUR (1) #define SPIFFS_SEEK_END (2) #define SPIFFS_TYPE_FILE (1) #define SPIFFS_TYPE_DIR (2) #define SPIFFS_TYPE_HARD_LINK (3) #define SPIFFS_TYPE_SOFT_LINK (4) #ifndef SPIFFS_LOCK #define SPIFFS_LOCK(fs) #endif #ifndef SPIFFS_UNLOCK #define SPIFFS_UNLOCK(fs) #endif // phys structs // spiffs spi configuration struct typedef struct { // physical read function spiffs_read hal_read_f; // physical write function spiffs_write hal_write_f; // physical erase function spiffs_erase hal_erase_f; #if SPIFFS_SINGLETON == 0 // physical size of the spi flash u32_t phys_size; // physical offset in spi flash used for spiffs, // must be on block boundary u32_t phys_addr; // physical size when erasing a block u32_t phys_erase_block; // logical size of a block, must be on physical // block size boundary and must never be less than // a physical block u32_t log_block_size; // logical size of a page, must be at least // log_block_size / 8 u32_t log_page_size; #endif #if SPIFFS_FILEHDL_OFFSET // an integer offset added to each file handle u16_t fh_ix_offset; #endif } spiffs_config; typedef struct spiffs_t { // file system configuration spiffs_config cfg; // number of logical blocks u32_t block_count; // cursor for free blocks, block index spiffs_block_ix free_cursor_block_ix; // cursor for free blocks, entry index int free_cursor_obj_lu_entry; // cursor when searching, block index spiffs_block_ix cursor_block_ix; // cursor when searching, entry index int cursor_obj_lu_entry; // primary work buffer, size of a logical page u8_t *lu_work; // secondary work buffer, size of a logical page u8_t *work; // file descriptor memory area u8_t *fd_space; // available file descriptors u32_t fd_count; // last error s32_t err_code; // current number of free blocks u32_t free_blocks; // current number of busy pages u32_t stats_p_allocated; // current number of deleted pages u32_t stats_p_deleted; // flag indicating that garbage collector is cleaning u8_t cleaning; // max erase count amongst all blocks spiffs_obj_id max_erase_count; #if SPIFFS_GC_STATS u32_t stats_gc_runs; #endif #if SPIFFS_CACHE // cache memory void *cache; // cache size u32_t cache_size; #if SPIFFS_CACHE_STATS u32_t cache_hits; u32_t cache_misses; #endif #endif // check callback function spiffs_check_callback check_cb_f; // file callback function spiffs_file_callback file_cb_f; // mounted flag u8_t mounted; // user data void *user_data; // config magic u32_t config_magic; } spiffs; /* spiffs file status struct */ typedef struct { spiffs_obj_id obj_id; u32_t size; spiffs_obj_type type; spiffs_page_ix pix; u8_t name[SPIFFS_OBJ_NAME_LEN]; #if SPIFFS_OBJ_META_LEN u8_t meta[SPIFFS_OBJ_META_LEN]; #endif } spiffs_stat; struct spiffs_dirent { spiffs_obj_id obj_id; u8_t name[SPIFFS_OBJ_NAME_LEN]; spiffs_obj_type type; u32_t size; spiffs_page_ix pix; #if SPIFFS_OBJ_META_LEN u8_t meta[SPIFFS_OBJ_META_LEN]; #endif }; typedef struct { spiffs *fs; spiffs_block_ix block; int entry; } spiffs_DIR; #if SPIFFS_IX_MAP typedef struct { // buffer with looked up data pixes spiffs_page_ix *map_buf; // precise file byte offset u32_t offset; // start data span index of lookup buffer spiffs_span_ix start_spix; // end data span index of lookup buffer spiffs_span_ix end_spix; } spiffs_ix_map; #endif // functions #if SPIFFS_USE_MAGIC && SPIFFS_USE_MAGIC_LENGTH && SPIFFS_SINGLETON==0 /** * Special function. This takes a spiffs config struct and returns the number * of blocks this file system was formatted with. This function relies on * that following info is set correctly in given config struct: * * phys_addr, log_page_size, and log_block_size. * * Also, hal_read_f must be set in the config struct. * * One must be sure of the correct page size and that the physical address is * correct in the probed file system when calling this function. It is not * checked if the phys_addr actually points to the start of the file system, * so one might get a false positive if entering a phys_addr somewhere in the * middle of the file system at block boundary. In addition, it is not checked * if the page size is actually correct. If it is not, weird file system sizes * will be returned. * * If this function detects a file system it returns the assumed file system * size, which can be used to set the phys_size. * * Otherwise, it returns an error indicating why it is not regarded as a file * system. * * Note: this function is not protected with SPIFFS_LOCK and SPIFFS_UNLOCK * macros. It returns the error code directly, instead of as read by * SPIFFS_errno. * * @param config essential parts of the physical and logical * configuration of the file system. */ s32_t SPIFFS_probe_fs(spiffs_config *config); #endif // SPIFFS_USE_MAGIC && SPIFFS_USE_MAGIC_LENGTH && SPIFFS_SINGLETON==0 /** * Initializes the file system dynamic parameters and mounts the filesystem. * If SPIFFS_USE_MAGIC is enabled the mounting may fail with SPIFFS_ERR_NOT_A_FS * if the flash does not contain a recognizable file system. * In this case, SPIFFS_format must be called prior to remounting. * @param fs the file system struct * @param config the physical and logical configuration of the file system * @param work a memory work buffer comprising 2*config->log_page_size * bytes used throughout all file system operations * @param fd_space memory for file descriptors * @param fd_space_size memory size of file descriptors * @param cache memory for cache, may be null * @param cache_size memory size of cache * @param check_cb_f callback function for reporting during consistency checks */ s32_t SPIFFS_mount(spiffs *fs, spiffs_config *config, u8_t *work, u8_t *fd_space, u32_t fd_space_size, void *cache, u32_t cache_size, spiffs_check_callback check_cb_f); /** * Unmounts the file system. All file handles will be flushed of any * cached writes and closed. * @param fs the file system struct */ void SPIFFS_unmount(spiffs *fs); /** * Creates a new file. * @param fs the file system struct * @param path the path of the new file * @param mode ignored, for posix compliance */ s32_t SPIFFS_creat(spiffs *fs, const char *path, spiffs_mode mode); /** * Opens/creates a file. * @param fs the file system struct * @param path the path of the new file * @param flags the flags for the open command, can be combinations of * SPIFFS_O_APPEND, SPIFFS_O_TRUNC, SPIFFS_O_CREAT, SPIFFS_O_RDONLY, * SPIFFS_O_WRONLY, SPIFFS_O_RDWR, SPIFFS_O_DIRECT, SPIFFS_O_EXCL * @param mode ignored, for posix compliance */ spiffs_file SPIFFS_open(spiffs *fs, const char *path, spiffs_flags flags, spiffs_mode mode); /** * Opens a file by given dir entry. * Optimization purposes, when traversing a file system with SPIFFS_readdir * a normal SPIFFS_open would need to traverse the filesystem again to find * the file, whilst SPIFFS_open_by_dirent already knows where the file resides. * @param fs the file system struct * @param e the dir entry to the file * @param flags the flags for the open command, can be combinations of * SPIFFS_APPEND, SPIFFS_TRUNC, SPIFFS_CREAT, SPIFFS_RD_ONLY, * SPIFFS_WR_ONLY, SPIFFS_RDWR, SPIFFS_DIRECT. * SPIFFS_CREAT will have no effect in this case. * @param mode ignored, for posix compliance */ spiffs_file SPIFFS_open_by_dirent(spiffs *fs, struct spiffs_dirent *e, spiffs_flags flags, spiffs_mode mode); /** * Opens a file by given page index. * Optimization purposes, opens a file by directly pointing to the page * index in the spi flash. * If the page index does not point to a file header SPIFFS_ERR_NOT_A_FILE * is returned. * @param fs the file system struct * @param page_ix the page index * @param flags the flags for the open command, can be combinations of * SPIFFS_APPEND, SPIFFS_TRUNC, SPIFFS_CREAT, SPIFFS_RD_ONLY, * SPIFFS_WR_ONLY, SPIFFS_RDWR, SPIFFS_DIRECT. * SPIFFS_CREAT will have no effect in this case. * @param mode ignored, for posix compliance */ spiffs_file SPIFFS_open_by_page(spiffs *fs, spiffs_page_ix page_ix, spiffs_flags flags, spiffs_mode mode); /** * Reads from given filehandle. * @param fs the file system struct * @param fh the filehandle * @param buf where to put read data * @param len how much to read * @returns number of bytes read, or -1 if error */ s32_t SPIFFS_read(spiffs *fs, spiffs_file fh, void *buf, s32_t len); /** * Writes to given filehandle. * @param fs the file system struct * @param fh the filehandle * @param buf the data to write * @param len how much to write * @returns number of bytes written, or -1 if error */ s32_t SPIFFS_write(spiffs *fs, spiffs_file fh, void *buf, s32_t len); /** * Moves the read/write file offset. Resulting offset is returned or negative if error. * lseek(fs, fd, 0, SPIFFS_SEEK_CUR) will thus return current offset. * @param fs the file system struct * @param fh the filehandle * @param offs how much/where to move the offset * @param whence if SPIFFS_SEEK_SET, the file offset shall be set to offset bytes * if SPIFFS_SEEK_CUR, the file offset shall be set to its current location plus offset * if SPIFFS_SEEK_END, the file offset shall be set to the size of the file plus offse, which should be negative */ s32_t SPIFFS_lseek(spiffs *fs, spiffs_file fh, s32_t offs, int whence); /** * Removes a file by path * @param fs the file system struct * @param path the path of the file to remove */ s32_t SPIFFS_remove(spiffs *fs, const char *path); /** * Removes a file by filehandle * @param fs the file system struct * @param fh the filehandle of the file to remove */ s32_t SPIFFS_fremove(spiffs *fs, spiffs_file fh); /** * Gets file status by path * @param fs the file system struct * @param path the path of the file to stat * @param s the stat struct to populate */ s32_t SPIFFS_stat(spiffs *fs, const char *path, spiffs_stat *s); /** * Gets file status by filehandle * @param fs the file system struct * @param fh the filehandle of the file to stat * @param s the stat struct to populate */ s32_t SPIFFS_fstat(spiffs *fs, spiffs_file fh, spiffs_stat *s); /** * Flushes all pending write operations from cache for given file * @param fs the file system struct * @param fh the filehandle of the file to flush */ s32_t SPIFFS_fflush(spiffs *fs, spiffs_file fh); /** * Closes a filehandle. If there are pending write operations, these are finalized before closing. * @param fs the file system struct * @param fh the filehandle of the file to close */ s32_t SPIFFS_close(spiffs *fs, spiffs_file fh); /** * Renames a file * @param fs the file system struct * @param old path of file to rename * @param newPath new path of file */ s32_t SPIFFS_rename(spiffs *fs, const char *old, const char *newPath); #if SPIFFS_OBJ_META_LEN /** * Updates file's metadata * @param fs the file system struct * @param path path to the file * @param meta new metadata. must be SPIFFS_OBJ_META_LEN bytes long. */ s32_t SPIFFS_update_meta(spiffs *fs, const char *name, const void *meta); /** * Updates file's metadata * @param fs the file system struct * @param fh file handle of the file * @param meta new metadata. must be SPIFFS_OBJ_META_LEN bytes long. */ s32_t SPIFFS_fupdate_meta(spiffs *fs, spiffs_file fh, const void *meta); #endif /** * Returns last error of last file operation. * @param fs the file system struct */ s32_t SPIFFS_errno(spiffs *fs); /** * Clears last error. * @param fs the file system struct */ void SPIFFS_clearerr(spiffs *fs); /** * Opens a directory stream corresponding to the given name. * The stream is positioned at the first entry in the directory. * On hydrogen builds the name argument is ignored as hydrogen builds always correspond * to a flat file structure - no directories. * @param fs the file system struct * @param name the name of the directory * @param d pointer the directory stream to be populated */ spiffs_DIR *SPIFFS_opendir(spiffs *fs, const char *name, spiffs_DIR *d); /** * Closes a directory stream * @param d the directory stream to close */ s32_t SPIFFS_closedir(spiffs_DIR *d); /** * Reads a directory into given spifs_dirent struct. * @param d pointer to the directory stream * @param e the dirent struct to be populated * @returns null if error or end of stream, else given dirent is returned */ struct spiffs_dirent *SPIFFS_readdir(spiffs_DIR *d, struct spiffs_dirent *e); /** * Runs a consistency check on given filesystem. * @param fs the file system struct */ s32_t SPIFFS_check(spiffs *fs); /** * Returns number of total bytes available and number of used bytes. * This is an estimation, and depends on if there a many files with little * data or few files with much data. * NB: If used number of bytes exceeds total bytes, a SPIFFS_check should * run. This indicates a power loss in midst of things. In worst case * (repeated powerlosses in mending or gc) you might have to delete some files. * * @param fs the file system struct * @param total total number of bytes in filesystem * @param used used number of bytes in filesystem */ s32_t SPIFFS_info(spiffs *fs, u32_t *total, u32_t *used); /** * Formats the entire file system. All data will be lost. * The filesystem must not be mounted when calling this. * * NB: formatting is awkward. Due to backwards compatibility, SPIFFS_mount * MUST be called prior to formatting in order to configure the filesystem. * If SPIFFS_mount succeeds, SPIFFS_unmount must be called before calling * SPIFFS_format. * If SPIFFS_mount fails, SPIFFS_format can be called directly without calling * SPIFFS_unmount first. * * @param fs the file system struct */ s32_t SPIFFS_format(spiffs *fs); /** * Returns nonzero if spiffs is mounted, or zero if unmounted. * @param fs the file system struct */ u8_t SPIFFS_mounted(spiffs *fs); /** * Tries to find a block where most or all pages are deleted, and erase that * block if found. Does not care for wear levelling. Will not move pages * around. * If parameter max_free_pages are set to 0, only blocks with only deleted * pages will be selected. * * NB: the garbage collector is automatically called when spiffs needs free * pages. The reason for this function is to give possibility to do background * tidying when user knows the system is idle. * * Use with care. * * Setting max_free_pages to anything larger than zero will eventually wear * flash more as a block containing free pages can be erased. * * Will set err_no to SPIFFS_OK if a block was found and erased, * SPIFFS_ERR_NO_DELETED_BLOCK if no matching block was found, * or other error. * * @param fs the file system struct * @param max_free_pages maximum number allowed free pages in block */ s32_t SPIFFS_gc_quick(spiffs *fs, u16_t max_free_pages); /** * Will try to make room for given amount of bytes in the filesystem by moving * pages and erasing blocks. * If it is physically impossible, err_no will be set to SPIFFS_ERR_FULL. If * there already is this amount (or more) of free space, SPIFFS_gc will * silently return. It is recommended to call SPIFFS_info before invoking * this method in order to determine what amount of bytes to give. * * NB: the garbage collector is automatically called when spiffs needs free * pages. The reason for this function is to give possibility to do background * tidying when user knows the system is idle. * * Use with care. * * @param fs the file system struct * @param size amount of bytes that should be freed */ s32_t SPIFFS_gc(spiffs *fs, u32_t size); /** * Check if EOF reached. * @param fs the file system struct * @param fh the filehandle of the file to check */ s32_t SPIFFS_eof(spiffs *fs, spiffs_file fh); /** * Get position in file. * @param fs the file system struct * @param fh the filehandle of the file to check */ s32_t SPIFFS_tell(spiffs *fs, spiffs_file fh); /** * Registers a callback function that keeps track on operations on file * headers. Do note, that this callback is called from within internal spiffs * mechanisms. Any operations on the actual file system being callbacked from * in this callback will mess things up for sure - do not do this. * This can be used to track where files are and move around during garbage * collection, which in turn can be used to build location tables in ram. * Used in conjuction with SPIFFS_open_by_page this may improve performance * when opening a lot of files. * Must be invoked after mount. * * @param fs the file system struct * @param cb_func the callback on file operations */ s32_t SPIFFS_set_file_callback_func(spiffs *fs, spiffs_file_callback cb_func); #if SPIFFS_IX_MAP /** * Maps the first level index lookup to a given memory map. * This will make reading big files faster, as the memory map will be used for * looking up data pages instead of searching for the indices on the physical * medium. When mapping, all affected indicies are found and the information is * copied to the array. * Whole file or only parts of it may be mapped. The index map will cover file * contents from argument offset until and including arguments (offset+len). * It is valid to map a longer range than the current file size. The map will * then be populated when the file grows. * On garbage collections and file data page movements, the map array will be * automatically updated. Do not tamper with the map array, as this contains * the references to the data pages. Modifying it from outside will corrupt any * future readings using this file descriptor. * The map will no longer be used when the file descriptor closed or the file * is unmapped. * This can be useful to get faster and more deterministic timing when reading * large files, or when seeking and reading a lot within a file. * @param fs the file system struct * @param fh the file handle of the file to map * @param map a spiffs_ix_map struct, describing the index map * @param offset absolute file offset where to start the index map * @param len length of the mapping in actual file bytes * @param map_buf the array buffer for the look up data - number of required * elements in the array can be derived from function * SPIFFS_bytes_to_ix_map_entries given the length */ s32_t SPIFFS_ix_map(spiffs *fs, spiffs_file fh, spiffs_ix_map *map, u32_t offset, u32_t len, spiffs_page_ix *map_buf); /** * Unmaps the index lookup from this filehandle. All future readings will * proceed as normal, requiring reading of the first level indices from * physical media. * The map and map buffer given in function SPIFFS_ix_map will no longer be * referenced by spiffs. * It is not strictly necessary to unmap a file before closing it, as closing * a file will automatically unmap it. * @param fs the file system struct * @param fh the file handle of the file to unmap */ s32_t SPIFFS_ix_unmap(spiffs *fs, spiffs_file fh); /** * Moves the offset for the index map given in function SPIFFS_ix_map. Parts or * all of the map buffer will repopulated. * @param fs the file system struct * @param fh the mapped file handle of the file to remap * @param offset new absolute file offset where to start the index map */ s32_t SPIFFS_ix_remap(spiffs *fs, spiffs_file fh, u32_t offs); /** * Utility function to get number of spiffs_page_ix entries a map buffer must * contain on order to map given amount of file data in bytes. * See function SPIFFS_ix_map and SPIFFS_ix_map_entries_to_bytes. * @param fs the file system struct * @param bytes number of file data bytes to map * @return needed number of elements in a spiffs_page_ix array needed to * map given amount of bytes in a file */ s32_t SPIFFS_bytes_to_ix_map_entries(spiffs *fs, u32_t bytes); /** * Utility function to amount of file data bytes that can be mapped when * mapping a file with buffer having given number of spiffs_page_ix entries. * See function SPIFFS_ix_map and SPIFFS_bytes_to_ix_map_entries. * @param fs the file system struct * @param map_page_ix_entries number of entries in a spiffs_page_ix array * @return amount of file data in bytes that can be mapped given a map * buffer having given amount of spiffs_page_ix entries */ s32_t SPIFFS_ix_map_entries_to_bytes(spiffs *fs, u32_t map_page_ix_entries); #endif // SPIFFS_IX_MAP #if SPIFFS_TEST_VISUALISATION /** * Prints out a visualization of the filesystem. * @param fs the file system struct */ s32_t SPIFFS_vis(spiffs *fs); #endif #if SPIFFS_BUFFER_HELP /** * Returns number of bytes needed for the filedescriptor buffer given * amount of file descriptors. */ u32_t SPIFFS_buffer_bytes_for_filedescs(spiffs *fs, u32_t num_descs); #if SPIFFS_CACHE /** * Returns number of bytes needed for the cache buffer given * amount of cache pages. */ u32_t SPIFFS_buffer_bytes_for_cache(spiffs *fs, u32_t num_pages); #endif #endif #if SPIFFS_CACHE #endif #if defined(__cplusplus) } #endif #endif /* SPIFFS_H_ */ ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/src/spiffs_cache.c ================================================ /* * spiffs_cache.c * * Created on: Jun 23, 2013 * Author: petera */ #include "spiffs.h" #include "spiffs_nucleus.h" #if SPIFFS_CACHE // returns cached page for give page index, or null if no such cached page static spiffs_cache_page *spiffs_cache_page_get(spiffs *fs, spiffs_page_ix pix) { spiffs_cache *cache = spiffs_get_cache(fs); if ((cache->cpage_use_map & cache->cpage_use_mask) == 0) return 0; int i; for (i = 0; i < cache->cpage_count; i++) { spiffs_cache_page *cp = spiffs_get_cache_page_hdr(fs, cache, i); if ((cache->cpage_use_map & (1 << i)) && (cp->flags & SPIFFS_CACHE_FLAG_TYPE_WR) == 0 && cp->pix == pix ) { //SPIFFS_CACHE_DBG("CACHE_GET: have cache page "_SPIPRIi" for "_SPIPRIpg"\n", i, pix); cp->last_access = cache->last_access; return cp; } } //SPIFFS_CACHE_DBG("CACHE_GET: no cache for "_SPIPRIpg"\n", pix); return 0; } // frees cached page static s32_t spiffs_cache_page_free(spiffs *fs, int ix, u8_t write_back) { s32_t res = SPIFFS_OK; spiffs_cache *cache = spiffs_get_cache(fs); spiffs_cache_page *cp = spiffs_get_cache_page_hdr(fs, cache, ix); if (cache->cpage_use_map & (1 << ix)) { if (write_back && (cp->flags & SPIFFS_CACHE_FLAG_TYPE_WR) == 0 && (cp->flags & SPIFFS_CACHE_FLAG_DIRTY)) { u8_t *mem = spiffs_get_cache_page(fs, cache, ix); SPIFFS_CACHE_DBG("CACHE_FREE: write cache page "_SPIPRIi" pix "_SPIPRIpg"\n", ix, cp->pix); res = SPIFFS_HAL_WRITE(fs, SPIFFS_PAGE_TO_PADDR(fs, cp->pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), mem); } #if SPIFFS_CACHE_WR if (cp->flags & SPIFFS_CACHE_FLAG_TYPE_WR) { SPIFFS_CACHE_DBG("CACHE_FREE: free cache page "_SPIPRIi" objid "_SPIPRIid"\n", ix, cp->obj_id); } else #endif { SPIFFS_CACHE_DBG("CACHE_FREE: free cache page "_SPIPRIi" pix "_SPIPRIpg"\n", ix, cp->pix); } cache->cpage_use_map &= ~(1 << ix); cp->flags = 0; } return res; } // removes the oldest accessed cached page static s32_t spiffs_cache_page_remove_oldest(spiffs *fs, u8_t flag_mask, u8_t flags) { s32_t res = SPIFFS_OK; spiffs_cache *cache = spiffs_get_cache(fs); if ((cache->cpage_use_map & cache->cpage_use_mask) != cache->cpage_use_mask) { // at least one free cpage return SPIFFS_OK; } // all busy, scan thru all to find the cpage which has oldest access int i; int cand_ix = -1; u32_t oldest_val = 0; for (i = 0; i < cache->cpage_count; i++) { spiffs_cache_page *cp = spiffs_get_cache_page_hdr(fs, cache, i); if ((cache->last_access - cp->last_access) > oldest_val && (cp->flags & flag_mask) == flags) { oldest_val = cache->last_access - cp->last_access; cand_ix = i; } } if (cand_ix >= 0) { res = spiffs_cache_page_free(fs, cand_ix, 1); } return res; } // allocates a new cached page and returns it, or null if all cache pages are busy static spiffs_cache_page *spiffs_cache_page_allocate(spiffs *fs) { spiffs_cache *cache = spiffs_get_cache(fs); if (cache->cpage_use_map == 0xffffffff) { // out of cache memory return 0; } int i; for (i = 0; i < cache->cpage_count; i++) { if ((cache->cpage_use_map & (1 << i)) == 0) { spiffs_cache_page *cp = spiffs_get_cache_page_hdr(fs, cache, i); cache->cpage_use_map |= (1 << i); cp->last_access = cache->last_access; //SPIFFS_CACHE_DBG("CACHE_ALLO: allocated cache page "_SPIPRIi"\n", i); return cp; } } // out of cache entries return 0; } // drops the cache page for give page index void spiffs_cache_drop_page(spiffs *fs, spiffs_page_ix pix) { spiffs_cache_page *cp = spiffs_cache_page_get(fs, pix); if (cp) { spiffs_cache_page_free(fs, cp->ix, 0); } } // ------------------------------ // reads from spi flash or the cache s32_t spiffs_phys_rd( spiffs *fs, u8_t op, spiffs_file fh, u32_t addr, u32_t len, u8_t *dst) { (void)fh; s32_t res = SPIFFS_OK; spiffs_cache *cache = spiffs_get_cache(fs); spiffs_cache_page *cp = spiffs_cache_page_get(fs, SPIFFS_PADDR_TO_PAGE(fs, addr)); cache->last_access++; if (cp) { // we've already got one, you see #if SPIFFS_CACHE_STATS fs->cache_hits++; #endif cp->last_access = cache->last_access; u8_t *mem = spiffs_get_cache_page(fs, cache, cp->ix); _SPIFFS_MEMCPY(dst, &mem[SPIFFS_PADDR_TO_PAGE_OFFSET(fs, addr)], len); } else { if ((op & SPIFFS_OP_TYPE_MASK) == SPIFFS_OP_T_OBJ_LU2) { // for second layer lookup functions, we do not cache in order to prevent shredding return SPIFFS_HAL_READ(fs, addr, len, dst); } #if SPIFFS_CACHE_STATS fs->cache_misses++; #endif // this operation will always free one cache page (unless all already free), // the result code stems from the write operation of the possibly freed cache page res = spiffs_cache_page_remove_oldest(fs, SPIFFS_CACHE_FLAG_TYPE_WR, 0); cp = spiffs_cache_page_allocate(fs); if (cp) { cp->flags = SPIFFS_CACHE_FLAG_WRTHRU; cp->pix = SPIFFS_PADDR_TO_PAGE(fs, addr); SPIFFS_CACHE_DBG("CACHE_ALLO: allocated cache page "_SPIPRIi" for pix "_SPIPRIpg "\n", cp->ix, cp->pix); s32_t res2 = SPIFFS_HAL_READ(fs, addr - SPIFFS_PADDR_TO_PAGE_OFFSET(fs, addr), SPIFFS_CFG_LOG_PAGE_SZ(fs), spiffs_get_cache_page(fs, cache, cp->ix)); if (res2 != SPIFFS_OK) { // honor read failure before possible write failure (bad idea?) res = res2; } u8_t *mem = spiffs_get_cache_page(fs, cache, cp->ix); _SPIFFS_MEMCPY(dst, &mem[SPIFFS_PADDR_TO_PAGE_OFFSET(fs, addr)], len); } else { // this will never happen, last resort for sake of symmetry s32_t res2 = SPIFFS_HAL_READ(fs, addr, len, dst); if (res2 != SPIFFS_OK) { // honor read failure before possible write failure (bad idea?) res = res2; } } } return res; } // writes to spi flash and/or the cache s32_t spiffs_phys_wr( spiffs *fs, u8_t op, spiffs_file fh, u32_t addr, u32_t len, u8_t *src) { (void)fh; spiffs_page_ix pix = SPIFFS_PADDR_TO_PAGE(fs, addr); spiffs_cache *cache = spiffs_get_cache(fs); spiffs_cache_page *cp = spiffs_cache_page_get(fs, pix); if (cp && (op & SPIFFS_OP_COM_MASK) != SPIFFS_OP_C_WRTHRU) { // have a cache page // copy in data to cache page if ((op & SPIFFS_OP_COM_MASK) == SPIFFS_OP_C_DELE && (op & SPIFFS_OP_TYPE_MASK) != SPIFFS_OP_T_OBJ_LU) { // page is being deleted, wipe from cache - unless it is a lookup page spiffs_cache_page_free(fs, cp->ix, 0); return SPIFFS_HAL_WRITE(fs, addr, len, src); } u8_t *mem = spiffs_get_cache_page(fs, cache, cp->ix); _SPIFFS_MEMCPY(&mem[SPIFFS_PADDR_TO_PAGE_OFFSET(fs, addr)], src, len); cache->last_access++; cp->last_access = cache->last_access; if (cp->flags & SPIFFS_CACHE_FLAG_WRTHRU) { // page is being updated, no write-cache, just pass thru return SPIFFS_HAL_WRITE(fs, addr, len, src); } else { return SPIFFS_OK; } } else { // no cache page, no write cache - just write thru return SPIFFS_HAL_WRITE(fs, addr, len, src); } } #if SPIFFS_CACHE_WR // returns the cache page that this fd refers, or null if no cache page spiffs_cache_page *spiffs_cache_page_get_by_fd(spiffs *fs, spiffs_fd *fd) { spiffs_cache *cache = spiffs_get_cache(fs); if ((cache->cpage_use_map & cache->cpage_use_mask) == 0) { // all cpages free, no cpage cannot be assigned to obj_id return 0; } int i; for (i = 0; i < cache->cpage_count; i++) { spiffs_cache_page *cp = spiffs_get_cache_page_hdr(fs, cache, i); if ((cache->cpage_use_map & (1 << i)) && (cp->flags & SPIFFS_CACHE_FLAG_TYPE_WR) && cp->obj_id == fd->obj_id) { return cp; } } return 0; } // allocates a new cache page and refers this to given fd - flushes an old cache // page if all cache is busy spiffs_cache_page *spiffs_cache_page_allocate_by_fd(spiffs *fs, spiffs_fd *fd) { // before this function is called, it is ensured that there is no already existing // cache page with same object id spiffs_cache_page_remove_oldest(fs, SPIFFS_CACHE_FLAG_TYPE_WR, 0); spiffs_cache_page *cp = spiffs_cache_page_allocate(fs); if (cp == 0) { // could not get cache page return 0; } cp->flags = SPIFFS_CACHE_FLAG_TYPE_WR; cp->obj_id = fd->obj_id; fd->cache_page = cp; SPIFFS_CACHE_DBG("CACHE_ALLO: allocated cache page "_SPIPRIi" for fd "_SPIPRIfd ":"_SPIPRIid "\n", cp->ix, fd->file_nbr, fd->obj_id); return cp; } // unrefers all fds that this cache page refers to and releases the cache page void spiffs_cache_fd_release(spiffs *fs, spiffs_cache_page *cp) { if (cp == 0) return; u32_t i; spiffs_fd *fds = (spiffs_fd *)fs->fd_space; for (i = 0; i < fs->fd_count; i++) { spiffs_fd *cur_fd = &fds[i]; if (cur_fd->file_nbr != 0 && cur_fd->cache_page == cp) { cur_fd->cache_page = 0; } } spiffs_cache_page_free(fs, cp->ix, 0); cp->obj_id = 0; } #endif // initializes the cache void spiffs_cache_init(spiffs *fs) { if (fs->cache == 0) return; u32_t sz = fs->cache_size; u32_t cache_mask = 0; int i; int cache_entries = (sz - sizeof(spiffs_cache)) / (SPIFFS_CACHE_PAGE_SIZE(fs)); if (cache_entries <= 0) return; for (i = 0; i < cache_entries; i++) { cache_mask <<= 1; cache_mask |= 1; } spiffs_cache cache; memset(&cache, 0, sizeof(spiffs_cache)); cache.cpage_count = cache_entries; cache.cpages = (u8_t *)((u8_t *)fs->cache + sizeof(spiffs_cache)); cache.cpage_use_map = 0xffffffff; cache.cpage_use_mask = cache_mask; _SPIFFS_MEMCPY(fs->cache, &cache, sizeof(spiffs_cache)); spiffs_cache *c = spiffs_get_cache(fs); memset(c->cpages, 0, c->cpage_count * SPIFFS_CACHE_PAGE_SIZE(fs)); c->cpage_use_map &= ~(c->cpage_use_mask); for (i = 0; i < cache.cpage_count; i++) { spiffs_get_cache_page_hdr(fs, c, i)->ix = i; } } #endif // SPIFFS_CACHE ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/src/spiffs_check.c ================================================ /* * spiffs_check.c * * Contains functionality for checking file system consistency * and mending problems. * Three levels of consistency checks are implemented: * * Look up consistency * Checks if indices in lookup pages are coherent with page headers * Object index consistency * Checks if there are any orphaned object indices (missing object index headers). * If an object index is found but not its header, the object index is deleted. * This is critical for the following page consistency check. * Page consistency * Checks for pages that ought to be indexed, ought not to be indexed, are multiple indexed * * * Created on: Jul 7, 2013 * Author: petera */ #include "spiffs.h" #include "spiffs_nucleus.h" #if !SPIFFS_READ_ONLY #if SPIFFS_HAL_CALLBACK_EXTRA #define CHECK_CB(_fs, _type, _rep, _arg1, _arg2) \ do { \ if ((_fs)->check_cb_f) (_fs)->check_cb_f((_fs), (_type), (_rep), (_arg1), (_arg2)); \ } while (0) #else #define CHECK_CB(_fs, _type, _rep, _arg1, _arg2) \ do { \ if ((_fs)->check_cb_f) (_fs)->check_cb_f((_type), (_rep), (_arg1), (_arg2)); \ } while (0) #endif //--------------------------------------- // Look up consistency // searches in the object indices and returns the referenced page index given // the object id and the data span index // destroys fs->lu_work static s32_t spiffs_object_get_data_page_index_reference( spiffs *fs, spiffs_obj_id obj_id, spiffs_span_ix data_spix, spiffs_page_ix *pix, spiffs_page_ix *objix_pix) { s32_t res; // calculate object index span index for given data page span index spiffs_span_ix objix_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, data_spix); // find obj index for obj id and span index res = spiffs_obj_lu_find_id_and_span(fs, obj_id | SPIFFS_OBJ_ID_IX_FLAG, objix_spix, 0, objix_pix); SPIFFS_CHECK_RES(res); // load obj index entry u32_t addr = SPIFFS_PAGE_TO_PADDR(fs, *objix_pix); if (objix_spix == 0) { // get referenced page from object index header addr += sizeof(spiffs_page_object_ix_header) + data_spix * sizeof(spiffs_page_ix); } else { // get referenced page from object index addr += sizeof(spiffs_page_object_ix) + SPIFFS_OBJ_IX_ENTRY(fs, data_spix) * sizeof(spiffs_page_ix); } res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, addr, sizeof(spiffs_page_ix), (u8_t *)pix); return res; } // copies page contents to a new page static s32_t spiffs_rewrite_page(spiffs *fs, spiffs_page_ix cur_pix, spiffs_page_header *p_hdr, spiffs_page_ix *new_pix) { s32_t res; res = spiffs_page_allocate_data(fs, p_hdr->obj_id, p_hdr, 0, 0, 0, 0, new_pix); SPIFFS_CHECK_RES(res); res = spiffs_phys_cpy(fs, 0, SPIFFS_PAGE_TO_PADDR(fs, *new_pix) + sizeof(spiffs_page_header), SPIFFS_PAGE_TO_PADDR(fs, cur_pix) + sizeof(spiffs_page_header), SPIFFS_DATA_PAGE_SIZE(fs)); SPIFFS_CHECK_RES(res); return res; } // rewrites the object index for given object id and replaces the // data page index to a new page index static s32_t spiffs_rewrite_index(spiffs *fs, spiffs_obj_id obj_id, spiffs_span_ix data_spix, spiffs_page_ix new_data_pix, spiffs_page_ix objix_pix) { s32_t res; spiffs_block_ix bix; int entry; spiffs_page_ix free_pix; obj_id |= SPIFFS_OBJ_ID_IX_FLAG; // find free entry res = spiffs_obj_lu_find_free(fs, fs->free_cursor_block_ix, fs->free_cursor_obj_lu_entry, &bix, &entry); SPIFFS_CHECK_RES(res); free_pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, entry); // calculate object index span index for given data page span index spiffs_span_ix objix_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, data_spix); if (objix_spix == 0) { // calc index in index header entry = data_spix; } else { // calc entry in index entry = SPIFFS_OBJ_IX_ENTRY(fs, data_spix); } // load index res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, objix_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->lu_work); SPIFFS_CHECK_RES(res); spiffs_page_header *objix_p_hdr = (spiffs_page_header *)fs->lu_work; // be ultra safe, double check header against provided data if (objix_p_hdr->obj_id != obj_id) { spiffs_page_delete(fs, free_pix); return SPIFFS_ERR_CHECK_OBJ_ID_MISM; } if (objix_p_hdr->span_ix != objix_spix) { spiffs_page_delete(fs, free_pix); return SPIFFS_ERR_CHECK_SPIX_MISM; } if ((objix_p_hdr->flags & (SPIFFS_PH_FLAG_USED | SPIFFS_PH_FLAG_IXDELE | SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_DELET)) != (SPIFFS_PH_FLAG_IXDELE | SPIFFS_PH_FLAG_DELET)) { spiffs_page_delete(fs, free_pix); return SPIFFS_ERR_CHECK_FLAGS_BAD; } // rewrite in mem if (objix_spix == 0) { ((spiffs_page_ix *)((u8_t *)fs->lu_work + sizeof(spiffs_page_object_ix_header)))[data_spix] = new_data_pix; } else { ((spiffs_page_ix *)((u8_t *)fs->lu_work + sizeof(spiffs_page_object_ix)))[SPIFFS_OBJ_IX_ENTRY(fs, data_spix)] = new_data_pix; } res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, 0, SPIFFS_PAGE_TO_PADDR(fs, free_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->lu_work); SPIFFS_CHECK_RES(res); res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_UPDT, 0, SPIFFS_BLOCK_TO_PADDR(fs, SPIFFS_BLOCK_FOR_PAGE(fs, free_pix)) + SPIFFS_OBJ_LOOKUP_ENTRY_FOR_PAGE(fs, free_pix) * sizeof(spiffs_page_ix), sizeof(spiffs_obj_id), (u8_t *)&obj_id); SPIFFS_CHECK_RES(res); res = spiffs_page_delete(fs, objix_pix); return res; } // deletes an object just by marking object index header as deleted static s32_t spiffs_delete_obj_lazy(spiffs *fs, spiffs_obj_id obj_id) { spiffs_page_ix objix_hdr_pix; s32_t res; res = spiffs_obj_lu_find_id_and_span(fs, obj_id, 0, 0, &objix_hdr_pix); if (res == SPIFFS_ERR_NOT_FOUND) { return SPIFFS_OK; } SPIFFS_CHECK_RES(res); u8_t flags = 0xff; #if SPIFFS_NO_BLIND_WRITES res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, objix_hdr_pix) + offsetof(spiffs_page_header, flags), sizeof(flags), &flags); SPIFFS_CHECK_RES(res); #endif flags &= ~SPIFFS_PH_FLAG_IXDELE; res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_UPDT, 0, SPIFFS_PAGE_TO_PADDR(fs, objix_hdr_pix) + offsetof(spiffs_page_header, flags), sizeof(flags), &flags); return res; } // validates the given look up entry static s32_t spiffs_lookup_check_validate(spiffs *fs, spiffs_obj_id lu_obj_id, spiffs_page_header *p_hdr, spiffs_page_ix cur_pix, spiffs_block_ix cur_block, int cur_entry, int *reload_lu) { (void)cur_block; (void)cur_entry; u8_t delete_page = 0; s32_t res = SPIFFS_OK; spiffs_page_ix objix_pix; spiffs_page_ix ref_pix; // check validity, take actions if (((lu_obj_id == SPIFFS_OBJ_ID_DELETED) && (p_hdr->flags & SPIFFS_PH_FLAG_DELET)) || ((lu_obj_id == SPIFFS_OBJ_ID_FREE) && (p_hdr->flags & SPIFFS_PH_FLAG_USED) == 0)) { // look up entry deleted / free but used in page header SPIFFS_CHECK_DBG("LU: pix "_SPIPRIpg" deleted/free in lu but not on page\n", cur_pix); *reload_lu = 1; delete_page = 1; if (p_hdr->flags & SPIFFS_PH_FLAG_INDEX) { // header says data page // data page can be removed if not referenced by some object index res = spiffs_object_get_data_page_index_reference(fs, p_hdr->obj_id, p_hdr->span_ix, &ref_pix, &objix_pix); if (res == SPIFFS_ERR_NOT_FOUND) { // no object with this id, so remove page safely res = SPIFFS_OK; } else { SPIFFS_CHECK_RES(res); if (ref_pix == cur_pix) { // data page referenced by object index but deleted in lu // copy page to new place and re-write the object index to new place spiffs_page_ix new_pix; res = spiffs_rewrite_page(fs, cur_pix, p_hdr, &new_pix); SPIFFS_CHECK_DBG("LU: FIXUP: data page not found elsewhere, rewriting "_SPIPRIpg" to new page "_SPIPRIpg"\n", cur_pix, new_pix); SPIFFS_CHECK_RES(res); *reload_lu = 1; SPIFFS_CHECK_DBG("LU: FIXUP: "_SPIPRIpg" rewritten to "_SPIPRIpg", affected objix_pix "_SPIPRIpg"\n", cur_pix, new_pix, objix_pix); res = spiffs_rewrite_index(fs, p_hdr->obj_id, p_hdr->span_ix, new_pix, objix_pix); if (res <= _SPIFFS_ERR_CHECK_FIRST && res > _SPIFFS_ERR_CHECK_LAST) { // index bad also, cannot mend this file SPIFFS_CHECK_DBG("LU: FIXUP: index bad "_SPIPRIi", cannot mend!\n", res); res = spiffs_page_delete(fs, new_pix); SPIFFS_CHECK_RES(res); res = spiffs_delete_obj_lazy(fs, p_hdr->obj_id); CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_DELETE_BAD_FILE, p_hdr->obj_id, 0); } else { CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_FIX_INDEX, p_hdr->obj_id, p_hdr->span_ix); } SPIFFS_CHECK_RES(res); } } } else { // header says index page // index page can be removed if other index with same obj_id and spanix is found res = spiffs_obj_lu_find_id_and_span(fs, p_hdr->obj_id | SPIFFS_OBJ_ID_IX_FLAG, p_hdr->span_ix, cur_pix, 0); if (res == SPIFFS_ERR_NOT_FOUND) { // no such index page found, check for a data page amongst page headers // lu cannot be trusted res = spiffs_obj_lu_find_id_and_span_by_phdr(fs, p_hdr->obj_id | SPIFFS_OBJ_ID_IX_FLAG, 0, 0, 0); if (res == SPIFFS_OK) // ignore other errors { // got a data page also, assume lu corruption only, rewrite to new page spiffs_page_ix new_pix; res = spiffs_rewrite_page(fs, cur_pix, p_hdr, &new_pix); SPIFFS_CHECK_DBG("LU: FIXUP: ix page with data not found elsewhere, rewriting "_SPIPRIpg" to new page "_SPIPRIpg"\n", cur_pix, new_pix); SPIFFS_CHECK_RES(res); *reload_lu = 1; CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_FIX_LOOKUP, p_hdr->obj_id, p_hdr->span_ix); } } else { SPIFFS_CHECK_RES(res); } } } if (lu_obj_id != SPIFFS_OBJ_ID_FREE && lu_obj_id != SPIFFS_OBJ_ID_DELETED) { // look up entry used if ((p_hdr->obj_id | SPIFFS_OBJ_ID_IX_FLAG) != (lu_obj_id | SPIFFS_OBJ_ID_IX_FLAG)) { SPIFFS_CHECK_DBG("LU: pix "_SPIPRIpg" differ in obj_id lu:"_SPIPRIid" ph:"_SPIPRIid"\n", cur_pix, lu_obj_id, p_hdr->obj_id); delete_page = 1; if ((p_hdr->flags & SPIFFS_PH_FLAG_DELET) == 0 || (p_hdr->flags & SPIFFS_PH_FLAG_FINAL) || (p_hdr->flags & (SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_IXDELE)) == 0) { // page deleted or not finalized, just remove it } else { if (p_hdr->flags & SPIFFS_PH_FLAG_INDEX) { // if data page, check for reference to this page res = spiffs_object_get_data_page_index_reference(fs, p_hdr->obj_id, p_hdr->span_ix, &ref_pix, &objix_pix); if (res == SPIFFS_ERR_NOT_FOUND) { // no object with this id, so remove page safely res = SPIFFS_OK; } else { SPIFFS_CHECK_RES(res); // if found, rewrite page with object id, update index, and delete current if (ref_pix == cur_pix) { spiffs_page_ix new_pix; res = spiffs_rewrite_page(fs, cur_pix, p_hdr, &new_pix); SPIFFS_CHECK_RES(res); res = spiffs_rewrite_index(fs, p_hdr->obj_id, p_hdr->span_ix, new_pix, objix_pix); if (res <= _SPIFFS_ERR_CHECK_FIRST && res > _SPIFFS_ERR_CHECK_LAST) { // index bad also, cannot mend this file SPIFFS_CHECK_DBG("LU: FIXUP: index bad "_SPIPRIi", cannot mend!\n", res); res = spiffs_page_delete(fs, new_pix); SPIFFS_CHECK_RES(res); res = spiffs_delete_obj_lazy(fs, p_hdr->obj_id); *reload_lu = 1; CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_DELETE_BAD_FILE, p_hdr->obj_id, 0); } SPIFFS_CHECK_RES(res); } } } else { // else if index, check for other pages with both obj_id's and spanix spiffs_page_ix objix_pix_lu, objix_pix_ph; // see if other object index page exists for lookup obj id and span index res = spiffs_obj_lu_find_id_and_span(fs, lu_obj_id | SPIFFS_OBJ_ID_IX_FLAG, p_hdr->span_ix, 0, &objix_pix_lu); if (res == SPIFFS_ERR_NOT_FOUND) { res = SPIFFS_OK; objix_pix_lu = 0; } SPIFFS_CHECK_RES(res); // see if other object index exists for page header obj id and span index res = spiffs_obj_lu_find_id_and_span(fs, p_hdr->obj_id | SPIFFS_OBJ_ID_IX_FLAG, p_hdr->span_ix, 0, &objix_pix_ph); if (res == SPIFFS_ERR_NOT_FOUND) { res = SPIFFS_OK; objix_pix_ph = 0; } SPIFFS_CHECK_RES(res); // if both obj_id's found, just delete current if (objix_pix_ph == 0 || objix_pix_lu == 0) { // otherwise try finding first corresponding data pages spiffs_page_ix data_pix_lu, data_pix_ph; // see if other data page exists for look up obj id and span index res = spiffs_obj_lu_find_id_and_span(fs, lu_obj_id & ~SPIFFS_OBJ_ID_IX_FLAG, 0, 0, &data_pix_lu); if (res == SPIFFS_ERR_NOT_FOUND) { res = SPIFFS_OK; objix_pix_lu = 0; } SPIFFS_CHECK_RES(res); // see if other data page exists for page header obj id and span index res = spiffs_obj_lu_find_id_and_span(fs, p_hdr->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG, 0, 0, &data_pix_ph); if (res == SPIFFS_ERR_NOT_FOUND) { res = SPIFFS_OK; objix_pix_ph = 0; } SPIFFS_CHECK_RES(res); spiffs_page_header new_ph; new_ph.flags = 0xff & ~(SPIFFS_PH_FLAG_USED | SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_FINAL); new_ph.span_ix = p_hdr->span_ix; spiffs_page_ix new_pix; if ((objix_pix_lu && data_pix_lu && data_pix_ph && objix_pix_ph == 0) || (objix_pix_lu == 0 && data_pix_ph && objix_pix_ph == 0)) { // got a data page for page header obj id // rewrite as obj_id_ph new_ph.obj_id = p_hdr->obj_id | SPIFFS_OBJ_ID_IX_FLAG; res = spiffs_rewrite_page(fs, cur_pix, &new_ph, &new_pix); SPIFFS_CHECK_DBG("LU: FIXUP: rewrite page "_SPIPRIpg" as "_SPIPRIid" to pix "_SPIPRIpg"\n", cur_pix, new_ph.obj_id, new_pix); CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_FIX_LOOKUP, p_hdr->obj_id, p_hdr->span_ix); SPIFFS_CHECK_RES(res); *reload_lu = 1; } else if ((objix_pix_ph && data_pix_ph && data_pix_lu && objix_pix_lu == 0) || (objix_pix_ph == 0 && data_pix_lu && objix_pix_lu == 0)) { // got a data page for look up obj id // rewrite as obj_id_lu new_ph.obj_id = lu_obj_id | SPIFFS_OBJ_ID_IX_FLAG; SPIFFS_CHECK_DBG("LU: FIXUP: rewrite page "_SPIPRIpg" as "_SPIPRIid"\n", cur_pix, new_ph.obj_id); CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_FIX_LOOKUP, p_hdr->obj_id, p_hdr->span_ix); res = spiffs_rewrite_page(fs, cur_pix, &new_ph, &new_pix); SPIFFS_CHECK_RES(res); *reload_lu = 1; } else { // cannot safely do anything SPIFFS_CHECK_DBG("LU: FIXUP: nothing to do, just delete\n"); } } } } } else if (((lu_obj_id & SPIFFS_OBJ_ID_IX_FLAG) && (p_hdr->flags & SPIFFS_PH_FLAG_INDEX)) || ((lu_obj_id & SPIFFS_OBJ_ID_IX_FLAG) == 0 && (p_hdr->flags & SPIFFS_PH_FLAG_INDEX) == 0)) { SPIFFS_CHECK_DBG("LU: "_SPIPRIpg" lu/page index marking differ\n", cur_pix); spiffs_page_ix data_pix, objix_pix_d; // see if other data page exists for given obj id and span index res = spiffs_obj_lu_find_id_and_span(fs, lu_obj_id & ~SPIFFS_OBJ_ID_IX_FLAG, p_hdr->span_ix, cur_pix, &data_pix); if (res == SPIFFS_ERR_NOT_FOUND) { res = SPIFFS_OK; data_pix = 0; } SPIFFS_CHECK_RES(res); // see if other object index exists for given obj id and span index res = spiffs_obj_lu_find_id_and_span(fs, lu_obj_id | SPIFFS_OBJ_ID_IX_FLAG, p_hdr->span_ix, cur_pix, &objix_pix_d); if (res == SPIFFS_ERR_NOT_FOUND) { res = SPIFFS_OK; objix_pix_d = 0; } SPIFFS_CHECK_RES(res); delete_page = 1; // if other data page exists and object index exists, just delete page if (data_pix && objix_pix_d) { SPIFFS_CHECK_DBG("LU: FIXUP: other index and data page exists, simply remove\n"); } else // if only data page exists, make this page index if (data_pix && objix_pix_d == 0) { SPIFFS_CHECK_DBG("LU: FIXUP: other data page exists, make this index\n"); CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_FIX_INDEX, lu_obj_id, p_hdr->span_ix); spiffs_page_header new_ph; spiffs_page_ix new_pix; new_ph.flags = 0xff & ~(SPIFFS_PH_FLAG_USED | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_INDEX); new_ph.obj_id = lu_obj_id | SPIFFS_OBJ_ID_IX_FLAG; new_ph.span_ix = p_hdr->span_ix; res = spiffs_page_allocate_data(fs, new_ph.obj_id, &new_ph, 0, 0, 0, 1, &new_pix); SPIFFS_CHECK_RES(res); res = spiffs_phys_cpy(fs, 0, SPIFFS_PAGE_TO_PADDR(fs, new_pix) + sizeof(spiffs_page_header), SPIFFS_PAGE_TO_PADDR(fs, cur_pix) + sizeof(spiffs_page_header), SPIFFS_CFG_LOG_PAGE_SZ(fs) - sizeof(spiffs_page_header)); SPIFFS_CHECK_RES(res); } else // if only index exists, make data page if (data_pix == 0 && objix_pix_d) { SPIFFS_CHECK_DBG("LU: FIXUP: other index page exists, make this data\n"); CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_FIX_LOOKUP, lu_obj_id, p_hdr->span_ix); spiffs_page_header new_ph; spiffs_page_ix new_pix; new_ph.flags = 0xff & ~(SPIFFS_PH_FLAG_USED | SPIFFS_PH_FLAG_FINAL); new_ph.obj_id = lu_obj_id & ~SPIFFS_OBJ_ID_IX_FLAG; new_ph.span_ix = p_hdr->span_ix; res = spiffs_page_allocate_data(fs, new_ph.obj_id, &new_ph, 0, 0, 0, 1, &new_pix); SPIFFS_CHECK_RES(res); res = spiffs_phys_cpy(fs, 0, SPIFFS_PAGE_TO_PADDR(fs, new_pix) + sizeof(spiffs_page_header), SPIFFS_PAGE_TO_PADDR(fs, cur_pix) + sizeof(spiffs_page_header), SPIFFS_CFG_LOG_PAGE_SZ(fs) - sizeof(spiffs_page_header)); SPIFFS_CHECK_RES(res); } else { // if nothing exists, we cannot safely make a decision - delete } } else if ((p_hdr->flags & SPIFFS_PH_FLAG_DELET) == 0) { SPIFFS_CHECK_DBG("LU: pix "_SPIPRIpg" busy in lu but deleted on page\n", cur_pix); delete_page = 1; } else if ((p_hdr->flags & SPIFFS_PH_FLAG_FINAL)) { SPIFFS_CHECK_DBG("LU: pix "_SPIPRIpg" busy but not final\n", cur_pix); // page can be removed if not referenced by object index *reload_lu = 1; res = spiffs_object_get_data_page_index_reference(fs, lu_obj_id, p_hdr->span_ix, &ref_pix, &objix_pix); if (res == SPIFFS_ERR_NOT_FOUND) { // no object with this id, so remove page safely res = SPIFFS_OK; delete_page = 1; } else { SPIFFS_CHECK_RES(res); if (ref_pix != cur_pix) { SPIFFS_CHECK_DBG("LU: FIXUP: other finalized page is referred, just delete\n"); delete_page = 1; } else { // page referenced by object index but not final // just finalize SPIFFS_CHECK_DBG("LU: FIXUP: unfinalized page is referred, finalizing\n"); CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_FIX_LOOKUP, p_hdr->obj_id, p_hdr->span_ix); u8_t flags = 0xff; #if SPIFFS_NO_BLIND_WRITES res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, cur_pix) + offsetof(spiffs_page_header, flags), sizeof(flags), &flags); SPIFFS_CHECK_RES(res); #endif flags &= ~SPIFFS_PH_FLAG_FINAL; res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, 0, SPIFFS_PAGE_TO_PADDR(fs, cur_pix) + offsetof(spiffs_page_header, flags), sizeof(flags), &flags); } } } } if (delete_page) { SPIFFS_CHECK_DBG("LU: FIXUP: deleting page "_SPIPRIpg"\n", cur_pix); CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_DELETE_PAGE, cur_pix, 0); res = spiffs_page_delete(fs, cur_pix); SPIFFS_CHECK_RES(res); } return res; } static s32_t spiffs_lookup_check_v(spiffs *fs, spiffs_obj_id obj_id, spiffs_block_ix cur_block, int cur_entry, const void *user_const_p, void *user_var_p) { (void)user_const_p; (void)user_var_p; s32_t res = SPIFFS_OK; spiffs_page_header p_hdr; spiffs_page_ix cur_pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, cur_block, cur_entry); CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_PROGRESS, (cur_block * 256) / fs->block_count, 0); // load header res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, cur_pix), sizeof(spiffs_page_header), (u8_t *)&p_hdr); SPIFFS_CHECK_RES(res); int reload_lu = 0; res = spiffs_lookup_check_validate(fs, obj_id, &p_hdr, cur_pix, cur_block, cur_entry, &reload_lu); SPIFFS_CHECK_RES(res); if (res == SPIFFS_OK) { return reload_lu ? SPIFFS_VIS_COUNTINUE_RELOAD : SPIFFS_VIS_COUNTINUE; } return res; } // Scans all object look up. For each entry, corresponding page header is checked for validity. // If an object index header page is found, this is also checked s32_t spiffs_lookup_consistency_check(spiffs *fs, u8_t check_all_objects) { (void)check_all_objects; s32_t res = SPIFFS_OK; CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_PROGRESS, 0, 0); res = spiffs_obj_lu_find_entry_visitor(fs, 0, 0, 0, 0, spiffs_lookup_check_v, 0, 0, 0, 0); if (res == SPIFFS_VIS_END) { res = SPIFFS_OK; } if (res != SPIFFS_OK) { CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_ERROR, res, 0); } CHECK_CB(fs, SPIFFS_CHECK_LOOKUP, SPIFFS_CHECK_PROGRESS, 256, 0); return res; } //--------------------------------------- // Page consistency // Scans all pages (except lu pages), reserves 4 bits in working memory for each page // bit 0: 0 == FREE|DELETED, 1 == USED // bit 1: 0 == UNREFERENCED, 1 == REFERENCED // bit 2: 0 == NOT_INDEX, 1 == INDEX // bit 3: unused // A consistent file system will have only pages being // * x000 free, unreferenced, not index // * x011 used, referenced only once, not index // * x101 used, unreferenced, index // The working memory might not fit all pages so several scans might be needed static s32_t spiffs_page_consistency_check_i(spiffs *fs) { const u32_t bits = 4; const spiffs_page_ix pages_per_scan = SPIFFS_CFG_LOG_PAGE_SZ(fs) * 8 / bits; s32_t res = SPIFFS_OK; spiffs_page_ix pix_offset = 0; // for each range of pages fitting into work memory while (pix_offset < SPIFFS_PAGES_PER_BLOCK(fs) * fs->block_count) { // set this flag to abort all checks and rescan the page range u8_t restart = 0; memset(fs->work, 0, SPIFFS_CFG_LOG_PAGE_SZ(fs)); spiffs_block_ix cur_block = 0; // build consistency bitmap for id range traversing all blocks while (!restart && cur_block < fs->block_count) { CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_PROGRESS, (pix_offset * 256) / (SPIFFS_PAGES_PER_BLOCK(fs) * fs->block_count) + ((((cur_block * pages_per_scan * 256) / (SPIFFS_PAGES_PER_BLOCK(fs) * fs->block_count))) / fs->block_count), 0); // traverse each page except for lookup pages spiffs_page_ix cur_pix = SPIFFS_OBJ_LOOKUP_PAGES(fs) + SPIFFS_PAGES_PER_BLOCK(fs) * cur_block; while (!restart && cur_pix < SPIFFS_PAGES_PER_BLOCK(fs) * (cur_block + 1)) { //if ((cur_pix & 0xff) == 0) // SPIFFS_CHECK_DBG("PA: processing pix "_SPIPRIpg", block "_SPIPRIbl" of pix "_SPIPRIpg", block "_SPIPRIbl"\n", // cur_pix, cur_block, SPIFFS_PAGES_PER_BLOCK(fs) * fs->block_count, fs->block_count); // read header spiffs_page_header p_hdr; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, cur_pix), sizeof(spiffs_page_header), (u8_t *)&p_hdr); SPIFFS_CHECK_RES(res); u8_t within_range = (cur_pix >= pix_offset && cur_pix < pix_offset + pages_per_scan); const u32_t pix_byte_ix = (cur_pix - pix_offset) / (8 / bits); const u8_t pix_bit_ix = (cur_pix & ((8 / bits) - 1)) * bits; if (within_range && (p_hdr.flags & SPIFFS_PH_FLAG_DELET) && (p_hdr.flags & SPIFFS_PH_FLAG_USED) == 0) { // used fs->work[pix_byte_ix] |= (1 << (pix_bit_ix + 0)); } if ((p_hdr.flags & SPIFFS_PH_FLAG_DELET) && (p_hdr.flags & SPIFFS_PH_FLAG_IXDELE) && (p_hdr.flags & (SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_USED)) == 0) { // found non-deleted index if (within_range) { fs->work[pix_byte_ix] |= (1 << (pix_bit_ix + 2)); } // load non-deleted index res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, cur_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->lu_work); SPIFFS_CHECK_RES(res); // traverse index for referenced pages spiffs_page_ix *object_page_index; spiffs_page_header *objix_p_hdr = (spiffs_page_header *)fs->lu_work; int entries; int i; spiffs_span_ix data_spix_offset; if (p_hdr.span_ix == 0) { // object header page index entries = SPIFFS_OBJ_HDR_IX_LEN(fs); data_spix_offset = 0; object_page_index = (spiffs_page_ix *)((u8_t *)fs->lu_work + sizeof(spiffs_page_object_ix_header)); } else { // object page index entries = SPIFFS_OBJ_IX_LEN(fs); data_spix_offset = SPIFFS_OBJ_HDR_IX_LEN(fs) + SPIFFS_OBJ_IX_LEN(fs) * (p_hdr.span_ix - 1); object_page_index = (spiffs_page_ix *)((u8_t *)fs->lu_work + sizeof(spiffs_page_object_ix)); } // for all entries in index for (i = 0; !restart && i < entries; i++) { spiffs_page_ix rpix = object_page_index[i]; u8_t rpix_within_range = rpix >= pix_offset && rpix < pix_offset + pages_per_scan; if ((rpix != (spiffs_page_ix) - 1 && rpix > SPIFFS_MAX_PAGES(fs)) || (rpix_within_range && SPIFFS_IS_LOOKUP_PAGE(fs, rpix))) { // bad reference SPIFFS_CHECK_DBG("PA: pix "_SPIPRIpg"x bad pix / LU referenced from page "_SPIPRIpg"\n", rpix, cur_pix); // check for data page elsewhere spiffs_page_ix data_pix; res = spiffs_obj_lu_find_id_and_span(fs, objix_p_hdr->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG, data_spix_offset + i, 0, &data_pix); if (res == SPIFFS_ERR_NOT_FOUND) { res = SPIFFS_OK; data_pix = 0; } SPIFFS_CHECK_RES(res); if (data_pix == 0) { // if not, allocate free page spiffs_page_header new_ph; new_ph.flags = 0xff & ~(SPIFFS_PH_FLAG_USED | SPIFFS_PH_FLAG_FINAL); new_ph.obj_id = objix_p_hdr->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG; new_ph.span_ix = data_spix_offset + i; res = spiffs_page_allocate_data(fs, new_ph.obj_id, &new_ph, 0, 0, 0, 1, &data_pix); SPIFFS_CHECK_RES(res); SPIFFS_CHECK_DBG("PA: FIXUP: found no existing data page, created new @ "_SPIPRIpg"\n", data_pix); } // remap index SPIFFS_CHECK_DBG("PA: FIXUP: rewriting index pix "_SPIPRIpg"\n", cur_pix); res = spiffs_rewrite_index(fs, objix_p_hdr->obj_id | SPIFFS_OBJ_ID_IX_FLAG, data_spix_offset + i, data_pix, cur_pix); if (res <= _SPIFFS_ERR_CHECK_FIRST && res > _SPIFFS_ERR_CHECK_LAST) { // index bad also, cannot mend this file SPIFFS_CHECK_DBG("PA: FIXUP: index bad "_SPIPRIi", cannot mend - delete object\n", res); CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_DELETE_BAD_FILE, objix_p_hdr->obj_id, 0); // delete file res = spiffs_page_delete(fs, cur_pix); } else { CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_FIX_INDEX, objix_p_hdr->obj_id, objix_p_hdr->span_ix); } SPIFFS_CHECK_RES(res); restart = 1; } else if (rpix_within_range) { // valid reference // read referenced page header spiffs_page_header rp_hdr; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, rpix), sizeof(spiffs_page_header), (u8_t *)&rp_hdr); SPIFFS_CHECK_RES(res); // cross reference page header check if (rp_hdr.obj_id != (p_hdr.obj_id & ~SPIFFS_OBJ_ID_IX_FLAG) || rp_hdr.span_ix != data_spix_offset + i || (rp_hdr.flags & (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_USED)) != (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_INDEX)) { SPIFFS_CHECK_DBG("PA: pix "_SPIPRIpg" has inconsistent page header ix id/span:"_SPIPRIid"/"_SPIPRIsp", ref id/span:"_SPIPRIid"/"_SPIPRIsp" flags:"_SPIPRIfl"\n", rpix, p_hdr.obj_id & ~SPIFFS_OBJ_ID_IX_FLAG, data_spix_offset + i, rp_hdr.obj_id, rp_hdr.span_ix, rp_hdr.flags); // try finding correct page spiffs_page_ix data_pix; res = spiffs_obj_lu_find_id_and_span(fs, p_hdr.obj_id & ~SPIFFS_OBJ_ID_IX_FLAG, data_spix_offset + i, rpix, &data_pix); if (res == SPIFFS_ERR_NOT_FOUND) { res = SPIFFS_OK; data_pix = 0; } SPIFFS_CHECK_RES(res); if (data_pix == 0) { // not found, this index is badly borked SPIFFS_CHECK_DBG("PA: FIXUP: index bad, delete object id "_SPIPRIid"\n", p_hdr.obj_id); CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_DELETE_BAD_FILE, p_hdr.obj_id, 0); res = spiffs_delete_obj_lazy(fs, p_hdr.obj_id); SPIFFS_CHECK_RES(res); break; } else { // found it, so rewrite index SPIFFS_CHECK_DBG("PA: FIXUP: found correct data pix "_SPIPRIpg", rewrite ix pix "_SPIPRIpg" id "_SPIPRIid"\n", data_pix, cur_pix, p_hdr.obj_id); res = spiffs_rewrite_index(fs, p_hdr.obj_id, data_spix_offset + i, data_pix, cur_pix); if (res <= _SPIFFS_ERR_CHECK_FIRST && res > _SPIFFS_ERR_CHECK_LAST) { // index bad also, cannot mend this file SPIFFS_CHECK_DBG("PA: FIXUP: index bad "_SPIPRIi", cannot mend!\n", res); CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_DELETE_BAD_FILE, p_hdr.obj_id, 0); res = spiffs_delete_obj_lazy(fs, p_hdr.obj_id); } else { CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_FIX_INDEX, p_hdr.obj_id, p_hdr.span_ix); } SPIFFS_CHECK_RES(res); restart = 1; } } else { // mark rpix as referenced const u32_t rpix_byte_ix = (rpix - pix_offset) / (8 / bits); const u8_t rpix_bit_ix = (rpix & ((8 / bits) - 1)) * bits; if (fs->work[rpix_byte_ix] & (1 << (rpix_bit_ix + 1))) { SPIFFS_CHECK_DBG("PA: pix "_SPIPRIpg" multiple referenced from page "_SPIPRIpg"\n", rpix, cur_pix); // Here, we should have fixed all broken references - getting this means there // must be multiple files with same object id. Only solution is to delete // the object which is referring to this page SPIFFS_CHECK_DBG("PA: FIXUP: removing object "_SPIPRIid" and page "_SPIPRIpg"\n", p_hdr.obj_id, cur_pix); CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_DELETE_BAD_FILE, p_hdr.obj_id, 0); res = spiffs_delete_obj_lazy(fs, p_hdr.obj_id); SPIFFS_CHECK_RES(res); // extra precaution, delete this page also res = spiffs_page_delete(fs, cur_pix); SPIFFS_CHECK_RES(res); restart = 1; } fs->work[rpix_byte_ix] |= (1 << (rpix_bit_ix + 1)); } } } // for all index entries } // found index // next page cur_pix++; } // next block cur_block++; } // check consistency bitmap if (!restart) { spiffs_page_ix objix_pix; spiffs_page_ix rpix; u32_t byte_ix; u8_t bit_ix; for (byte_ix = 0; !restart && byte_ix < SPIFFS_CFG_LOG_PAGE_SZ(fs); byte_ix++) { for (bit_ix = 0; !restart && bit_ix < 8 / bits; bit_ix ++) { u8_t bitmask = (fs->work[byte_ix] >> (bit_ix * bits)) & 0x7; spiffs_page_ix cur_pix = pix_offset + byte_ix * (8 / bits) + bit_ix; // 000 ok - free, unreferenced, not index if (bitmask == 0x1) { // 001 SPIFFS_CHECK_DBG("PA: pix "_SPIPRIpg" USED, UNREFERENCED, not index\n", cur_pix); u8_t rewrite_ix_to_this = 0; u8_t delete_page = 0; // check corresponding object index entry spiffs_page_header p_hdr; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, cur_pix), sizeof(spiffs_page_header), (u8_t *)&p_hdr); SPIFFS_CHECK_RES(res); res = spiffs_object_get_data_page_index_reference(fs, p_hdr.obj_id, p_hdr.span_ix, &rpix, &objix_pix); if (res == SPIFFS_OK) { if (((rpix == (spiffs_page_ix) - 1 || rpix > SPIFFS_MAX_PAGES(fs)) || (SPIFFS_IS_LOOKUP_PAGE(fs, rpix)))) { // pointing to a bad page altogether, rewrite index to this rewrite_ix_to_this = 1; SPIFFS_CHECK_DBG("PA: corresponding ref is bad: "_SPIPRIpg", rewrite to this "_SPIPRIpg"\n", rpix, cur_pix); } else { // pointing to something else, check what spiffs_page_header rp_hdr; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, rpix), sizeof(spiffs_page_header), (u8_t *)&rp_hdr); SPIFFS_CHECK_RES(res); if (((p_hdr.obj_id & ~SPIFFS_OBJ_ID_IX_FLAG) == rp_hdr.obj_id) && ((rp_hdr.flags & (SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_USED | SPIFFS_PH_FLAG_FINAL)) == (SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_DELET))) { // pointing to something else valid, just delete this page then SPIFFS_CHECK_DBG("PA: corresponding ref is good but different: "_SPIPRIpg", delete this "_SPIPRIpg"\n", rpix, cur_pix); delete_page = 1; } else { // pointing to something weird, update index to point to this page instead if (rpix != cur_pix) { SPIFFS_CHECK_DBG("PA: corresponding ref is weird: "_SPIPRIpg" %s%s%s%s, rewrite this "_SPIPRIpg"\n", rpix, (rp_hdr.flags & SPIFFS_PH_FLAG_INDEX) ? "" : "INDEX ", (rp_hdr.flags & SPIFFS_PH_FLAG_DELET) ? "" : "DELETED ", (rp_hdr.flags & SPIFFS_PH_FLAG_USED) ? "NOTUSED " : "", (rp_hdr.flags & SPIFFS_PH_FLAG_FINAL) ? "NOTFINAL " : "", cur_pix); rewrite_ix_to_this = 1; } else { // should not happen, destined for fubar } } } } else if (res == SPIFFS_ERR_NOT_FOUND) { SPIFFS_CHECK_DBG("PA: corresponding ref not found, delete "_SPIPRIpg"\n", cur_pix); delete_page = 1; res = SPIFFS_OK; } if (rewrite_ix_to_this) { // if pointing to invalid page, redirect index to this page SPIFFS_CHECK_DBG("PA: FIXUP: rewrite index id "_SPIPRIid" data spix "_SPIPRIsp" to point to this pix: "_SPIPRIpg"\n", p_hdr.obj_id, p_hdr.span_ix, cur_pix); res = spiffs_rewrite_index(fs, p_hdr.obj_id, p_hdr.span_ix, cur_pix, objix_pix); if (res <= _SPIFFS_ERR_CHECK_FIRST && res > _SPIFFS_ERR_CHECK_LAST) { // index bad also, cannot mend this file SPIFFS_CHECK_DBG("PA: FIXUP: index bad "_SPIPRIi", cannot mend!\n", res); CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_DELETE_BAD_FILE, p_hdr.obj_id, 0); res = spiffs_page_delete(fs, cur_pix); SPIFFS_CHECK_RES(res); res = spiffs_delete_obj_lazy(fs, p_hdr.obj_id); } else { CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_FIX_INDEX, p_hdr.obj_id, p_hdr.span_ix); } SPIFFS_CHECK_RES(res); restart = 1; continue; } else if (delete_page) { SPIFFS_CHECK_DBG("PA: FIXUP: deleting page "_SPIPRIpg"\n", cur_pix); CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_DELETE_PAGE, cur_pix, 0); res = spiffs_page_delete(fs, cur_pix); } SPIFFS_CHECK_RES(res); } if (bitmask == 0x2) { // 010 SPIFFS_CHECK_DBG("PA: pix "_SPIPRIpg" FREE, REFERENCED, not index\n", cur_pix); // no op, this should be taken care of when checking valid references } // 011 ok - busy, referenced, not index if (bitmask == 0x4) { // 100 SPIFFS_CHECK_DBG("PA: pix "_SPIPRIpg" FREE, unreferenced, INDEX\n", cur_pix); // this should never happen, major fubar } // 101 ok - busy, unreferenced, index if (bitmask == 0x6) { // 110 SPIFFS_CHECK_DBG("PA: pix "_SPIPRIpg" FREE, REFERENCED, INDEX\n", cur_pix); // no op, this should be taken care of when checking valid references } if (bitmask == 0x7) { // 111 SPIFFS_CHECK_DBG("PA: pix "_SPIPRIpg" USED, REFERENCED, INDEX\n", cur_pix); // no op, this should be taken care of when checking valid references } } } } SPIFFS_CHECK_DBG("PA: processed "_SPIPRIpg", restart "_SPIPRIi"\n", pix_offset, restart); // next page range if (!restart) { pix_offset += pages_per_scan; } } // while page range not reached end return res; } // Checks consistency amongst all pages and fixes irregularities s32_t spiffs_page_consistency_check(spiffs *fs) { CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_PROGRESS, 0, 0); s32_t res = spiffs_page_consistency_check_i(fs); if (res != SPIFFS_OK) { CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_ERROR, res, 0); } CHECK_CB(fs, SPIFFS_CHECK_PAGE, SPIFFS_CHECK_PROGRESS, 256, 0); return res; } //--------------------------------------- // Object index consistency // searches for given object id in temporary object id index, // returns the index or -1 static int spiffs_object_index_search(spiffs *fs, spiffs_obj_id obj_id) { u32_t i; spiffs_obj_id *obj_table = (spiffs_obj_id *)fs->work; obj_id &= ~SPIFFS_OBJ_ID_IX_FLAG; for (i = 0; i < SPIFFS_CFG_LOG_PAGE_SZ(fs) / sizeof(spiffs_obj_id); i++) { if ((obj_table[i] & ~SPIFFS_OBJ_ID_IX_FLAG) == obj_id) { return i; } } return -1; } static s32_t spiffs_object_index_consistency_check_v(spiffs *fs, spiffs_obj_id obj_id, spiffs_block_ix cur_block, int cur_entry, const void *user_const_p, void *user_var_p) { (void)user_const_p; s32_t res_c = SPIFFS_VIS_COUNTINUE; s32_t res = SPIFFS_OK; u32_t *log_ix = (u32_t *)user_var_p; spiffs_obj_id *obj_table = (spiffs_obj_id *)fs->work; CHECK_CB(fs, SPIFFS_CHECK_INDEX, SPIFFS_CHECK_PROGRESS, (cur_block * 256) / fs->block_count, 0); if (obj_id != SPIFFS_OBJ_ID_FREE && obj_id != SPIFFS_OBJ_ID_DELETED && (obj_id & SPIFFS_OBJ_ID_IX_FLAG)) { spiffs_page_header p_hdr; spiffs_page_ix cur_pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, cur_block, cur_entry); // load header res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, cur_pix), sizeof(spiffs_page_header), (u8_t *)&p_hdr); SPIFFS_CHECK_RES(res); if (p_hdr.span_ix == 0 && (p_hdr.flags & (SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_IXDELE)) == (SPIFFS_PH_FLAG_DELET)) { SPIFFS_CHECK_DBG("IX: pix "_SPIPRIpg", obj id:"_SPIPRIid" spix:"_SPIPRIsp" header not fully deleted - deleting\n", cur_pix, obj_id, p_hdr.span_ix); CHECK_CB(fs, SPIFFS_CHECK_INDEX, SPIFFS_CHECK_DELETE_PAGE, cur_pix, obj_id); res = spiffs_page_delete(fs, cur_pix); SPIFFS_CHECK_RES(res); return res_c; } if ((p_hdr.flags & (SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_IXDELE)) == (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_IXDELE)) { return res_c; } if (p_hdr.span_ix == 0) { // objix header page, register objid as reachable int r = spiffs_object_index_search(fs, obj_id); if (r == -1) { // not registered, do it obj_table[*log_ix] = obj_id & ~SPIFFS_OBJ_ID_IX_FLAG; (*log_ix)++; if (*log_ix >= SPIFFS_CFG_LOG_PAGE_SZ(fs) / sizeof(spiffs_obj_id)) { *log_ix = 0; } } } else // span index { // objix page, see if header can be found int r = spiffs_object_index_search(fs, obj_id); u8_t delete = 0; if (r == -1) { // not in temporary index, try finding it spiffs_page_ix objix_hdr_pix; res = spiffs_obj_lu_find_id_and_span(fs, obj_id | SPIFFS_OBJ_ID_IX_FLAG, 0, 0, &objix_hdr_pix); res_c = SPIFFS_VIS_COUNTINUE_RELOAD; if (res == SPIFFS_OK) { // found, register as reachable obj_table[*log_ix] = obj_id & ~SPIFFS_OBJ_ID_IX_FLAG; } else if (res == SPIFFS_ERR_NOT_FOUND) { // not found, register as unreachable delete = 1; obj_table[*log_ix] = obj_id | SPIFFS_OBJ_ID_IX_FLAG; } else { SPIFFS_CHECK_RES(res); } (*log_ix)++; if (*log_ix >= SPIFFS_CFG_LOG_PAGE_SZ(fs) / sizeof(spiffs_obj_id)) { *log_ix = 0; } } else { // in temporary index, check reachable flag if ((obj_table[r] & SPIFFS_OBJ_ID_IX_FLAG)) { // registered as unreachable delete = 1; } } if (delete) { SPIFFS_CHECK_DBG("IX: FIXUP: pix "_SPIPRIpg", obj id:"_SPIPRIid" spix:"_SPIPRIsp" is orphan index - deleting\n", cur_pix, obj_id, p_hdr.span_ix); CHECK_CB(fs, SPIFFS_CHECK_INDEX, SPIFFS_CHECK_DELETE_ORPHANED_INDEX, cur_pix, obj_id); res = spiffs_page_delete(fs, cur_pix); SPIFFS_CHECK_RES(res); } } // span index } // valid object index id return res_c; } // Removes orphaned and partially deleted index pages. // Scans for index pages. When an index page is found, corresponding index header is searched for. // If no such page exists, the index page cannot be reached as no index header exists and must be // deleted. s32_t spiffs_object_index_consistency_check(spiffs *fs) { s32_t res = SPIFFS_OK; // impl note: // fs->work is used for a temporary object index memory, listing found object ids and // indicating whether they can be reached or not. Acting as a fifo if object ids cannot fit. // In the temporary object index memory, SPIFFS_OBJ_ID_IX_FLAG bit is used to indicate // a reachable/unreachable object id. memset(fs->work, 0, SPIFFS_CFG_LOG_PAGE_SZ(fs)); u32_t obj_id_log_ix = 0; CHECK_CB(fs, SPIFFS_CHECK_INDEX, SPIFFS_CHECK_PROGRESS, 0, 0); res = spiffs_obj_lu_find_entry_visitor(fs, 0, 0, 0, 0, spiffs_object_index_consistency_check_v, 0, &obj_id_log_ix, 0, 0); if (res == SPIFFS_VIS_END) { res = SPIFFS_OK; } if (res != SPIFFS_OK) { CHECK_CB(fs, SPIFFS_CHECK_INDEX, SPIFFS_CHECK_ERROR, res, 0); } CHECK_CB(fs, SPIFFS_CHECK_INDEX, SPIFFS_CHECK_PROGRESS, 256, 0); return res; } #endif // !SPIFFS_READ_ONLY ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/src/spiffs_gc.c ================================================ #include "spiffs.h" #include "spiffs_nucleus.h" #if !SPIFFS_READ_ONLY // Erases a logical block and updates the erase counter. // If cache is enabled, all pages that might be cached in this block // is dropped. static s32_t spiffs_gc_erase_block( spiffs *fs, spiffs_block_ix bix) { s32_t res; SPIFFS_GC_DBG("gc: erase block "_SPIPRIbl"\n", bix); res = spiffs_erase_block(fs, bix); SPIFFS_CHECK_RES(res); #if SPIFFS_CACHE { u32_t i; for (i = 0; i < SPIFFS_PAGES_PER_BLOCK(fs); i++) { spiffs_cache_drop_page(fs, SPIFFS_PAGE_FOR_BLOCK(fs, bix) + i); } } #endif return res; } // Searches for blocks where all entries are deleted - if one is found, // the block is erased. Compared to the non-quick gc, the quick one ensures // that no updates are needed on existing objects on pages that are erased. s32_t spiffs_gc_quick( spiffs *fs, u16_t max_free_pages) { s32_t res = SPIFFS_OK; u32_t blocks = fs->block_count; spiffs_block_ix cur_block = 0; u32_t cur_block_addr = 0; int cur_entry = 0; spiffs_obj_id *obj_lu_buf = (spiffs_obj_id *)fs->lu_work; SPIFFS_GC_DBG("gc_quick: running\n"); #if SPIFFS_GC_STATS fs->stats_gc_runs++; #endif int entries_per_page = (SPIFFS_CFG_LOG_PAGE_SZ(fs) / sizeof(spiffs_obj_id)); // find fully deleted blocks // check each block while (res == SPIFFS_OK && blocks--) { u16_t deleted_pages_in_block = 0; u16_t free_pages_in_block = 0; int obj_lookup_page = 0; // check each object lookup page while (res == SPIFFS_OK && obj_lookup_page < (int)SPIFFS_OBJ_LOOKUP_PAGES(fs)) { int entry_offset = obj_lookup_page * entries_per_page; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, 0, cur_block_addr + SPIFFS_PAGE_TO_PADDR(fs, obj_lookup_page), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->lu_work); // check each entry while (res == SPIFFS_OK && cur_entry - entry_offset < entries_per_page && cur_entry < (int)(SPIFFS_PAGES_PER_BLOCK(fs) - SPIFFS_OBJ_LOOKUP_PAGES(fs))) { spiffs_obj_id obj_id = obj_lu_buf[cur_entry - entry_offset]; if (obj_id == SPIFFS_OBJ_ID_DELETED) { deleted_pages_in_block++; } else if (obj_id == SPIFFS_OBJ_ID_FREE) { // kill scan, go for next block free_pages_in_block++; if (free_pages_in_block > max_free_pages) { obj_lookup_page = SPIFFS_OBJ_LOOKUP_PAGES(fs); res = 1; // kill object lu loop break; } } else { // kill scan, go for next block obj_lookup_page = SPIFFS_OBJ_LOOKUP_PAGES(fs); res = 1; // kill object lu loop break; } cur_entry++; } // per entry obj_lookup_page++; } // per object lookup page if (res == 1) res = SPIFFS_OK; if (res == SPIFFS_OK && deleted_pages_in_block + free_pages_in_block == SPIFFS_PAGES_PER_BLOCK(fs) - SPIFFS_OBJ_LOOKUP_PAGES(fs) && free_pages_in_block <= max_free_pages) { // found a fully deleted block fs->stats_p_deleted -= deleted_pages_in_block; res = spiffs_gc_erase_block(fs, cur_block); return res; } cur_entry = 0; cur_block++; cur_block_addr += SPIFFS_CFG_LOG_BLOCK_SZ(fs); } // per block if (res == SPIFFS_OK) { res = SPIFFS_ERR_NO_DELETED_BLOCKS; } return res; } // Checks if garbage collecting is necessary. If so a candidate block is found, // cleansed and erased s32_t spiffs_gc_check( spiffs *fs, u32_t len) { s32_t res; s32_t free_pages = (SPIFFS_PAGES_PER_BLOCK(fs) - SPIFFS_OBJ_LOOKUP_PAGES(fs)) * (fs->block_count - 2) - fs->stats_p_allocated - fs->stats_p_deleted; int tries = 0; if (fs->free_blocks > 3 && (s32_t)len < free_pages * (s32_t)SPIFFS_DATA_PAGE_SIZE(fs)) { return SPIFFS_OK; } u32_t needed_pages = (len + SPIFFS_DATA_PAGE_SIZE(fs) - 1) / SPIFFS_DATA_PAGE_SIZE(fs); // if (fs->free_blocks <= 2 && (s32_t)needed_pages > free_pages) { // SPIFFS_GC_DBG("gc: full freeblk:"_SPIPRIi" needed:"_SPIPRIi" free:"_SPIPRIi" dele:"_SPIPRIi"\n", fs->free_blocks, needed_pages, free_pages, fs->stats_p_deleted); // return SPIFFS_ERR_FULL; // } if ((s32_t)needed_pages > (s32_t)(free_pages + fs->stats_p_deleted)) { SPIFFS_GC_DBG("gc_check: full freeblk:"_SPIPRIi" needed:"_SPIPRIi" free:"_SPIPRIi" dele:"_SPIPRIi"\n", fs->free_blocks, needed_pages, free_pages, fs->stats_p_deleted); return SPIFFS_ERR_FULL; } do { SPIFFS_GC_DBG("\ngc_check #"_SPIPRIi": run gc free_blocks:"_SPIPRIi" pfree:"_SPIPRIi" pallo:"_SPIPRIi" pdele:"_SPIPRIi" ["_SPIPRIi"] len:"_SPIPRIi" of "_SPIPRIi"\n", tries, fs->free_blocks, free_pages, fs->stats_p_allocated, fs->stats_p_deleted, (free_pages + fs->stats_p_allocated + fs->stats_p_deleted), len, (u32_t)(free_pages * SPIFFS_DATA_PAGE_SIZE(fs))); spiffs_block_ix *cands; int count; spiffs_block_ix cand; s32_t prev_free_pages = free_pages; // if the fs is crammed, ignore block age when selecting candidate - kind of a bad state res = spiffs_gc_find_candidate(fs, &cands, &count, free_pages <= 0); SPIFFS_CHECK_RES(res); if (count == 0) { SPIFFS_GC_DBG("gc_check: no candidates, return\n"); return (s32_t)needed_pages < free_pages ? SPIFFS_OK : SPIFFS_ERR_FULL; } #if SPIFFS_GC_STATS fs->stats_gc_runs++; #endif cand = cands[0]; fs->cleaning = 1; //SPIFFS_GC_DBG("gcing: cleaning block "_SPIPRIi"\n", cand); res = spiffs_gc_clean(fs, cand); fs->cleaning = 0; if (res < 0) { SPIFFS_GC_DBG("gc_check: cleaning block "_SPIPRIi", result "_SPIPRIi"\n", cand, res); } else { SPIFFS_GC_DBG("gc_check: cleaning block "_SPIPRIi", result "_SPIPRIi"\n", cand, res); } SPIFFS_CHECK_RES(res); res = spiffs_gc_erase_page_stats(fs, cand); SPIFFS_CHECK_RES(res); res = spiffs_gc_erase_block(fs, cand); SPIFFS_CHECK_RES(res); free_pages = (SPIFFS_PAGES_PER_BLOCK(fs) - SPIFFS_OBJ_LOOKUP_PAGES(fs)) * (fs->block_count - 2) - fs->stats_p_allocated - fs->stats_p_deleted; if (prev_free_pages <= 0 && prev_free_pages == free_pages) { // abort early to reduce wear, at least tried once SPIFFS_GC_DBG("gc_check: early abort, no result on gc when fs crammed\n"); break; } } while (++tries < SPIFFS_GC_MAX_RUNS && (fs->free_blocks <= 2 || (s32_t)len > free_pages * (s32_t)SPIFFS_DATA_PAGE_SIZE(fs))); free_pages = (SPIFFS_PAGES_PER_BLOCK(fs) - SPIFFS_OBJ_LOOKUP_PAGES(fs)) * (fs->block_count - 2) - fs->stats_p_allocated - fs->stats_p_deleted; if ((s32_t)len > free_pages * (s32_t)SPIFFS_DATA_PAGE_SIZE(fs)) { res = SPIFFS_ERR_FULL; } SPIFFS_GC_DBG("gc_check: finished, "_SPIPRIi" dirty, blocks "_SPIPRIi" free, "_SPIPRIi" pages free, "_SPIPRIi" tries, res "_SPIPRIi"\n", fs->stats_p_allocated + fs->stats_p_deleted, fs->free_blocks, free_pages, tries, res); return res; } // Updates page statistics for a block that is about to be erased s32_t spiffs_gc_erase_page_stats( spiffs *fs, spiffs_block_ix bix) { s32_t res = SPIFFS_OK; int obj_lookup_page = 0; int entries_per_page = (SPIFFS_CFG_LOG_PAGE_SZ(fs) / sizeof(spiffs_obj_id)); spiffs_obj_id *obj_lu_buf = (spiffs_obj_id *)fs->lu_work; int cur_entry = 0; u32_t dele = 0; u32_t allo = 0; // check each object lookup page while (res == SPIFFS_OK && obj_lookup_page < (int)SPIFFS_OBJ_LOOKUP_PAGES(fs)) { int entry_offset = obj_lookup_page * entries_per_page; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, 0, bix * SPIFFS_CFG_LOG_BLOCK_SZ(fs) + SPIFFS_PAGE_TO_PADDR(fs, obj_lookup_page), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->lu_work); // check each entry while (res == SPIFFS_OK && cur_entry - entry_offset < entries_per_page && cur_entry < (int)(SPIFFS_PAGES_PER_BLOCK(fs) - SPIFFS_OBJ_LOOKUP_PAGES(fs))) { spiffs_obj_id obj_id = obj_lu_buf[cur_entry - entry_offset]; if (obj_id == SPIFFS_OBJ_ID_FREE) { } else if (obj_id == SPIFFS_OBJ_ID_DELETED) { dele++; } else { allo++; } cur_entry++; } // per entry obj_lookup_page++; } // per object lookup page SPIFFS_GC_DBG("gc_check: wipe pallo:"_SPIPRIi" pdele:"_SPIPRIi"\n", allo, dele); fs->stats_p_allocated -= allo; fs->stats_p_deleted -= dele; return res; } // Finds block candidates to erase s32_t spiffs_gc_find_candidate( spiffs *fs, spiffs_block_ix **block_candidates, int *candidate_count, char fs_crammed) { s32_t res = SPIFFS_OK; u32_t blocks = fs->block_count; spiffs_block_ix cur_block = 0; u32_t cur_block_addr = 0; spiffs_obj_id *obj_lu_buf = (spiffs_obj_id *)fs->lu_work; int cur_entry = 0; // using fs->work area as sorted candidate memory, (spiffs_block_ix)cand_bix/(s32_t)score int max_candidates = MIN(fs->block_count, (SPIFFS_CFG_LOG_PAGE_SZ(fs) - 8) / (sizeof(spiffs_block_ix) + sizeof(s32_t))); *candidate_count = 0; memset(fs->work, 0xff, SPIFFS_CFG_LOG_PAGE_SZ(fs)); // divide up work area into block indices and scores spiffs_block_ix *cand_blocks = (spiffs_block_ix *)fs->work; s32_t *cand_scores = (s32_t *)(fs->work + max_candidates * sizeof(spiffs_block_ix)); // align cand_scores on s32_t boundary cand_scores = (s32_t *)(((intptr_t)cand_scores + sizeof(intptr_t) - 1) & ~(sizeof(intptr_t) - 1)); *block_candidates = cand_blocks; int entries_per_page = (SPIFFS_CFG_LOG_PAGE_SZ(fs) / sizeof(spiffs_obj_id)); // check each block while (res == SPIFFS_OK && blocks--) { u16_t deleted_pages_in_block = 0; u16_t used_pages_in_block = 0; int obj_lookup_page = 0; // check each object lookup page while (res == SPIFFS_OK && obj_lookup_page < (int)SPIFFS_OBJ_LOOKUP_PAGES(fs)) { int entry_offset = obj_lookup_page * entries_per_page; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, 0, cur_block_addr + SPIFFS_PAGE_TO_PADDR(fs, obj_lookup_page), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->lu_work); // check each entry while (res == SPIFFS_OK && cur_entry - entry_offset < entries_per_page && cur_entry < (int)(SPIFFS_PAGES_PER_BLOCK(fs) - SPIFFS_OBJ_LOOKUP_PAGES(fs))) { spiffs_obj_id obj_id = obj_lu_buf[cur_entry - entry_offset]; if (obj_id == SPIFFS_OBJ_ID_FREE) { // when a free entry is encountered, scan logic ensures that all following entries are free also res = 1; // kill object lu loop break; } else if (obj_id == SPIFFS_OBJ_ID_DELETED) { deleted_pages_in_block++; } else { used_pages_in_block++; } cur_entry++; } // per entry obj_lookup_page++; } // per object lookup page if (res == 1) res = SPIFFS_OK; // calculate score and insert into candidate table // stoneage sort, but probably not so many blocks if (res == SPIFFS_OK /*&& deleted_pages_in_block > 0*/) { // read erase count spiffs_obj_id erase_count; res = _spiffs_rd(fs, SPIFFS_OP_C_READ | SPIFFS_OP_T_OBJ_LU2, 0, SPIFFS_ERASE_COUNT_PADDR(fs, cur_block), sizeof(spiffs_obj_id), (u8_t *)&erase_count); SPIFFS_CHECK_RES(res); spiffs_obj_id erase_age; if (fs->max_erase_count > erase_count) { erase_age = fs->max_erase_count - erase_count; } else { erase_age = SPIFFS_OBJ_ID_FREE - (erase_count - fs->max_erase_count); } s32_t score = deleted_pages_in_block * SPIFFS_GC_HEUR_W_DELET + used_pages_in_block * SPIFFS_GC_HEUR_W_USED + erase_age * (fs_crammed ? 0 : SPIFFS_GC_HEUR_W_ERASE_AGE); int cand_ix = 0; SPIFFS_GC_DBG("gc_check: bix:"_SPIPRIbl" del:"_SPIPRIi" use:"_SPIPRIi" score:"_SPIPRIi"\n", cur_block, deleted_pages_in_block, used_pages_in_block, score); while (cand_ix < max_candidates) { if (cand_blocks[cand_ix] == (spiffs_block_ix) - 1) { cand_blocks[cand_ix] = cur_block; cand_scores[cand_ix] = score; break; } else if (cand_scores[cand_ix] < score) { int reorder_cand_ix = max_candidates - 2; while (reorder_cand_ix >= cand_ix) { cand_blocks[reorder_cand_ix + 1] = cand_blocks[reorder_cand_ix]; cand_scores[reorder_cand_ix + 1] = cand_scores[reorder_cand_ix]; reorder_cand_ix--; } cand_blocks[cand_ix] = cur_block; cand_scores[cand_ix] = score; break; } cand_ix++; } (*candidate_count)++; } cur_entry = 0; cur_block++; cur_block_addr += SPIFFS_CFG_LOG_BLOCK_SZ(fs); } // per block return res; } typedef enum { FIND_OBJ_DATA, MOVE_OBJ_DATA, MOVE_OBJ_IX, FINISHED } spiffs_gc_clean_state; typedef struct { spiffs_gc_clean_state state; spiffs_obj_id cur_obj_id; spiffs_span_ix cur_objix_spix; spiffs_page_ix cur_objix_pix; spiffs_page_ix cur_data_pix; int stored_scan_entry_index; u8_t obj_id_found; } spiffs_gc; // Empties given block by moving all data into free pages of another block // Strategy: // loop: // scan object lookup for object data pages // for first found id, check spix and load corresponding object index page to memory // push object scan lookup entry index // rescan object lookup, find data pages with same id and referenced by same object index // move data page, update object index in memory // when reached end of lookup, store updated object index // pop object scan lookup entry index // repeat loop until end of object lookup // scan object lookup again for remaining object index pages, move to new page in other block // s32_t spiffs_gc_clean(spiffs *fs, spiffs_block_ix bix) { s32_t res = SPIFFS_OK; const int entries_per_page = (SPIFFS_CFG_LOG_PAGE_SZ(fs) / sizeof(spiffs_obj_id)); // this is the global localizer being pushed and popped int cur_entry = 0; spiffs_obj_id *obj_lu_buf = (spiffs_obj_id *)fs->lu_work; spiffs_gc gc; // our stack frame/state spiffs_page_ix cur_pix = 0; spiffs_page_object_ix_header *objix_hdr = (spiffs_page_object_ix_header *)fs->work; spiffs_page_object_ix *objix = (spiffs_page_object_ix *)fs->work; SPIFFS_GC_DBG("gc_clean: cleaning block "_SPIPRIbl"\n", bix); memset(&gc, 0, sizeof(spiffs_gc)); gc.state = FIND_OBJ_DATA; if (fs->free_cursor_block_ix == bix) { // move free cursor to next block, cannot use free pages from the block we want to clean fs->free_cursor_block_ix = (bix + 1) % fs->block_count; fs->free_cursor_obj_lu_entry = 0; SPIFFS_GC_DBG("gc_clean: move free cursor to block "_SPIPRIbl"\n", fs->free_cursor_block_ix); } while (res == SPIFFS_OK && gc.state != FINISHED) { SPIFFS_GC_DBG("gc_clean: state = "_SPIPRIi" entry:"_SPIPRIi"\n", gc.state, cur_entry); gc.obj_id_found = 0; // reset (to no found data page) // scan through lookup pages int obj_lookup_page = cur_entry / entries_per_page; u8_t scan = 1; // check each object lookup page while (scan && res == SPIFFS_OK && obj_lookup_page < (int)SPIFFS_OBJ_LOOKUP_PAGES(fs)) { int entry_offset = obj_lookup_page * entries_per_page; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, 0, bix * SPIFFS_CFG_LOG_BLOCK_SZ(fs) + SPIFFS_PAGE_TO_PADDR(fs, obj_lookup_page), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->lu_work); // check each object lookup entry while (scan && res == SPIFFS_OK && cur_entry - entry_offset < entries_per_page && cur_entry < (int)(SPIFFS_PAGES_PER_BLOCK(fs) - SPIFFS_OBJ_LOOKUP_PAGES(fs))) { spiffs_obj_id obj_id = obj_lu_buf[cur_entry - entry_offset]; cur_pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, cur_entry); // act upon object id depending on gc state switch (gc.state) { case FIND_OBJ_DATA: // find a data page if (obj_id != SPIFFS_OBJ_ID_DELETED && obj_id != SPIFFS_OBJ_ID_FREE && ((obj_id & SPIFFS_OBJ_ID_IX_FLAG) == 0)) { // found a data page, stop scanning and handle in switch case below SPIFFS_GC_DBG("gc_clean: FIND_DATA state:"_SPIPRIi" - found obj id "_SPIPRIid"\n", gc.state, obj_id); gc.obj_id_found = 1; gc.cur_obj_id = obj_id; gc.cur_data_pix = cur_pix; scan = 0; } break; case MOVE_OBJ_DATA: // evacuate found data pages for corresponding object index we have in memory, // update memory representation if (obj_id == gc.cur_obj_id) { spiffs_page_header p_hdr; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, cur_pix), sizeof(spiffs_page_header), (u8_t *)&p_hdr); SPIFFS_CHECK_RES(res); SPIFFS_GC_DBG("gc_clean: MOVE_DATA found data page "_SPIPRIid":"_SPIPRIsp" @ "_SPIPRIpg"\n", gc.cur_obj_id, p_hdr.span_ix, cur_pix); if (SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, p_hdr.span_ix) != gc.cur_objix_spix) { SPIFFS_GC_DBG("gc_clean: MOVE_DATA no objix spix match, take in another run\n"); } else { spiffs_page_ix new_data_pix; if (p_hdr.flags & SPIFFS_PH_FLAG_DELET) { // move page res = spiffs_page_move(fs, 0, 0, obj_id, &p_hdr, cur_pix, &new_data_pix); SPIFFS_GC_DBG("gc_clean: MOVE_DATA move objix "_SPIPRIid":"_SPIPRIsp" page "_SPIPRIpg" to "_SPIPRIpg"\n", gc.cur_obj_id, p_hdr.span_ix, cur_pix, new_data_pix); SPIFFS_CHECK_RES(res); // move wipes obj_lu, reload it res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, 0, bix * SPIFFS_CFG_LOG_BLOCK_SZ(fs) + SPIFFS_PAGE_TO_PADDR(fs, obj_lookup_page), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->lu_work); SPIFFS_CHECK_RES(res); } else { // page is deleted but not deleted in lookup, scrap it - // might seem unnecessary as we will erase this block, but // we might get aborted SPIFFS_GC_DBG("gc_clean: MOVE_DATA wipe objix "_SPIPRIid":"_SPIPRIsp" page "_SPIPRIpg"\n", obj_id, p_hdr.span_ix, cur_pix); res = spiffs_page_delete(fs, cur_pix); SPIFFS_CHECK_RES(res); new_data_pix = SPIFFS_OBJ_ID_FREE; } // update memory representation of object index page with new data page if (gc.cur_objix_spix == 0) { // update object index header page ((spiffs_page_ix *)((u8_t *)objix_hdr + sizeof(spiffs_page_object_ix_header)))[p_hdr.span_ix] = new_data_pix; SPIFFS_GC_DBG("gc_clean: MOVE_DATA wrote page "_SPIPRIpg" to objix_hdr entry "_SPIPRIsp" in mem\n", new_data_pix, (spiffs_span_ix)SPIFFS_OBJ_IX_ENTRY(fs, p_hdr.span_ix)); } else { // update object index page ((spiffs_page_ix *)((u8_t *)objix + sizeof(spiffs_page_object_ix)))[SPIFFS_OBJ_IX_ENTRY(fs, p_hdr.span_ix)] = new_data_pix; SPIFFS_GC_DBG("gc_clean: MOVE_DATA wrote page "_SPIPRIpg" to objix entry "_SPIPRIsp" in mem\n", new_data_pix, (spiffs_span_ix)SPIFFS_OBJ_IX_ENTRY(fs, p_hdr.span_ix)); } } } break; case MOVE_OBJ_IX: // find and evacuate object index pages if (obj_id != SPIFFS_OBJ_ID_DELETED && obj_id != SPIFFS_OBJ_ID_FREE && (obj_id & SPIFFS_OBJ_ID_IX_FLAG)) { // found an index object id spiffs_page_header p_hdr; spiffs_page_ix new_pix; // load header res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, cur_pix), sizeof(spiffs_page_header), (u8_t *)&p_hdr); SPIFFS_CHECK_RES(res); if (p_hdr.flags & SPIFFS_PH_FLAG_DELET) { // move page res = spiffs_page_move(fs, 0, 0, obj_id, &p_hdr, cur_pix, &new_pix); SPIFFS_GC_DBG("gc_clean: MOVE_OBJIX move objix "_SPIPRIid":"_SPIPRIsp" page "_SPIPRIpg" to "_SPIPRIpg"\n", obj_id, p_hdr.span_ix, cur_pix, new_pix); SPIFFS_CHECK_RES(res); spiffs_cb_object_event(fs, (spiffs_page_object_ix *)&p_hdr, SPIFFS_EV_IX_MOV, obj_id, p_hdr.span_ix, new_pix, 0); // move wipes obj_lu, reload it res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, 0, bix * SPIFFS_CFG_LOG_BLOCK_SZ(fs) + SPIFFS_PAGE_TO_PADDR(fs, obj_lookup_page), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->lu_work); SPIFFS_CHECK_RES(res); } else { // page is deleted but not deleted in lookup, scrap it - // might seem unnecessary as we will erase this block, but // we might get aborted SPIFFS_GC_DBG("gc_clean: MOVE_OBJIX wipe objix "_SPIPRIid":"_SPIPRIsp" page "_SPIPRIpg"\n", obj_id, p_hdr.span_ix, cur_pix); res = spiffs_page_delete(fs, cur_pix); if (res == SPIFFS_OK) { spiffs_cb_object_event(fs, (spiffs_page_object_ix *)0, SPIFFS_EV_IX_DEL, obj_id, p_hdr.span_ix, cur_pix, 0); } } SPIFFS_CHECK_RES(res); } break; default: scan = 0; break; } // switch gc state cur_entry++; } // per entry obj_lookup_page++; // no need to check scan variable here, obj_lookup_page is set in start of loop } // per object lookup page if (res != SPIFFS_OK) break; // state finalization and switch switch (gc.state) { case FIND_OBJ_DATA: if (gc.obj_id_found) { // handle found data page - // find out corresponding obj ix page and load it to memory spiffs_page_header p_hdr; spiffs_page_ix objix_pix; gc.stored_scan_entry_index = cur_entry; // push cursor cur_entry = 0; // restart scan from start gc.state = MOVE_OBJ_DATA; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, cur_pix), sizeof(spiffs_page_header), (u8_t *)&p_hdr); SPIFFS_CHECK_RES(res); gc.cur_objix_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, p_hdr.span_ix); SPIFFS_GC_DBG("gc_clean: FIND_DATA find objix span_ix:"_SPIPRIsp"\n", gc.cur_objix_spix); res = spiffs_obj_lu_find_id_and_span(fs, gc.cur_obj_id | SPIFFS_OBJ_ID_IX_FLAG, gc.cur_objix_spix, 0, &objix_pix); if (res == SPIFFS_ERR_NOT_FOUND) { // on borked systems we might get an ERR_NOT_FOUND here - // this is handled by simply deleting the page as it is not referenced // from anywhere SPIFFS_GC_DBG("gc_clean: FIND_OBJ_DATA objix not found! Wipe page "_SPIPRIpg"\n", gc.cur_data_pix); res = spiffs_page_delete(fs, gc.cur_data_pix); SPIFFS_CHECK_RES(res); // then we restore states and continue scanning for data pages cur_entry = gc.stored_scan_entry_index; // pop cursor gc.state = FIND_OBJ_DATA; break; // done } SPIFFS_CHECK_RES(res); SPIFFS_GC_DBG("gc_clean: FIND_DATA found object index at page "_SPIPRIpg"\n", objix_pix); res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, objix_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->work); SPIFFS_CHECK_RES(res); // cannot allow a gc if the presumed index in fact is no index, a // check must run or lot of data may be lost SPIFFS_VALIDATE_OBJIX(objix->p_hdr, gc.cur_obj_id | SPIFFS_OBJ_ID_IX_FLAG, gc.cur_objix_spix); gc.cur_objix_pix = objix_pix; } else { // no more data pages found, passed thru all block, start evacuating object indices gc.state = MOVE_OBJ_IX; cur_entry = 0; // restart entry scan index } break; case MOVE_OBJ_DATA: { // store modified objix (hdr) page residing in memory now that all // data pages belonging to this object index and residing in the block // we want to evacuate spiffs_page_ix new_objix_pix; gc.state = FIND_OBJ_DATA; cur_entry = gc.stored_scan_entry_index; // pop cursor if (gc.cur_objix_spix == 0) { // store object index header page res = spiffs_object_update_index_hdr(fs, 0, gc.cur_obj_id | SPIFFS_OBJ_ID_IX_FLAG, gc.cur_objix_pix, fs->work, 0, 0, 0, &new_objix_pix); SPIFFS_GC_DBG("gc_clean: MOVE_DATA store modified objix_hdr page, "_SPIPRIpg":"_SPIPRIsp"\n", new_objix_pix, 0); SPIFFS_CHECK_RES(res); } else { // store object index page res = spiffs_page_move(fs, 0, fs->work, gc.cur_obj_id | SPIFFS_OBJ_ID_IX_FLAG, 0, gc.cur_objix_pix, &new_objix_pix); SPIFFS_GC_DBG("gc_clean: MOVE_DATA store modified objix page, "_SPIPRIpg":"_SPIPRIsp"\n", new_objix_pix, objix->p_hdr.span_ix); SPIFFS_CHECK_RES(res); spiffs_cb_object_event(fs, (spiffs_page_object_ix *)fs->work, SPIFFS_EV_IX_UPD, gc.cur_obj_id, objix->p_hdr.span_ix, new_objix_pix, 0); } } break; case MOVE_OBJ_IX: // scanned thru all block, no more object indices found - our work here is done gc.state = FINISHED; break; default: cur_entry = 0; break; } // switch gc.state SPIFFS_GC_DBG("gc_clean: state-> "_SPIPRIi"\n", gc.state); } // while state != FINISHED return res; } #endif // !SPIFFS_READ_ONLY ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/src/spiffs_hydrogen.c ================================================ /* * spiffs_hydrogen.c * * Created on: Jun 16, 2013 * Author: petera */ #include "spiffs.h" #include "spiffs_nucleus.h" #if SPIFFS_CACHE == 1 static s32_t spiffs_fflush_cache(spiffs *fs, spiffs_file fh); #endif #if SPIFFS_BUFFER_HELP u32_t SPIFFS_buffer_bytes_for_filedescs(spiffs *fs, u32_t num_descs) { return num_descs * sizeof(spiffs_fd); } #if SPIFFS_CACHE u32_t SPIFFS_buffer_bytes_for_cache(spiffs *fs, u32_t num_pages) { return sizeof(spiffs_cache) + num_pages * (sizeof(spiffs_cache_page) + SPIFFS_CFG_LOG_PAGE_SZ(fs)); } #endif #endif u8_t SPIFFS_mounted(spiffs *fs) { return SPIFFS_CHECK_MOUNT(fs); } s32_t SPIFFS_format(spiffs *fs) { #if SPIFFS_READ_ONLY (void)fs; return SPIFFS_ERR_RO_NOT_IMPL; #else SPIFFS_API_CHECK_CFG(fs); if (SPIFFS_CHECK_MOUNT(fs)) { fs->err_code = SPIFFS_ERR_MOUNTED; return -1; } s32_t res; SPIFFS_LOCK(fs); spiffs_block_ix bix = 0; while (bix < fs->block_count) { fs->max_erase_count = 0; res = spiffs_erase_block(fs, bix); if (res != SPIFFS_OK) { res = SPIFFS_ERR_ERASE_FAIL; } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); bix++; } SPIFFS_UNLOCK(fs); return 0; #endif // SPIFFS_READ_ONLY } #if SPIFFS_USE_MAGIC && SPIFFS_USE_MAGIC_LENGTH && SPIFFS_SINGLETON==0 s32_t SPIFFS_probe_fs(spiffs_config *config) { SPIFFS_API_DBG("%s\n", __func__); s32_t res = spiffs_probe(config); return res; } #endif // SPIFFS_USE_MAGIC && SPIFFS_USE_MAGIC_LENGTH && SPIFFS_SINGLETON==0 s32_t SPIFFS_mount(spiffs *fs, spiffs_config *config, u8_t *work, u8_t *fd_space, u32_t fd_space_size, void *cache, u32_t cache_size, spiffs_check_callback check_cb_f) { SPIFFS_API_DBG("%s " " sz:"_SPIPRIi " logpgsz:"_SPIPRIi " logblksz:"_SPIPRIi " perasz:"_SPIPRIi " addr:"_SPIPRIad " fdsz:"_SPIPRIi " cachesz:"_SPIPRIi "\n", __func__, SPIFFS_CFG_PHYS_SZ(fs), SPIFFS_CFG_LOG_PAGE_SZ(fs), SPIFFS_CFG_LOG_BLOCK_SZ(fs), SPIFFS_CFG_PHYS_ERASE_SZ(fs), SPIFFS_CFG_PHYS_ADDR(fs), fd_space_size, cache_size); void *user_data; SPIFFS_LOCK(fs); user_data = fs->user_data; memset(fs, 0, sizeof(spiffs)); _SPIFFS_MEMCPY(&fs->cfg, config, sizeof(spiffs_config)); fs->user_data = user_data; fs->block_count = SPIFFS_CFG_PHYS_SZ(fs) / SPIFFS_CFG_LOG_BLOCK_SZ(fs); fs->work = &work[0]; fs->lu_work = &work[SPIFFS_CFG_LOG_PAGE_SZ(fs)]; memset(fd_space, 0, fd_space_size); // align fd_space pointer to pointer size byte boundary u8_t ptr_size = sizeof(void *); u8_t addr_lsb = ((u8_t)(intptr_t)fd_space) & (ptr_size - 1); if (addr_lsb) { fd_space += (ptr_size - addr_lsb); fd_space_size -= (ptr_size - addr_lsb); } fs->fd_space = fd_space; fs->fd_count = (fd_space_size / sizeof(spiffs_fd)); // align cache pointer to 4 byte boundary addr_lsb = ((u8_t)(intptr_t)cache) & (ptr_size - 1); if (addr_lsb) { u8_t *cache_8 = (u8_t *)cache; cache_8 += (ptr_size - addr_lsb); cache = cache_8; cache_size -= (ptr_size - addr_lsb); } if (cache_size & (ptr_size - 1)) { cache_size -= (cache_size & (ptr_size - 1)); } #if SPIFFS_CACHE fs->cache = cache; fs->cache_size = (cache_size > (SPIFFS_CFG_LOG_PAGE_SZ(fs) * 32)) ? SPIFFS_CFG_LOG_PAGE_SZ(fs) * 32 : cache_size; spiffs_cache_init(fs); #endif s32_t res; #if SPIFFS_USE_MAGIC res = SPIFFS_CHECK_MAGIC_POSSIBLE(fs) ? SPIFFS_OK : SPIFFS_ERR_MAGIC_NOT_POSSIBLE; SPIFFS_API_CHECK_RES_UNLOCK(fs, res); #endif fs->config_magic = SPIFFS_CONFIG_MAGIC; res = spiffs_obj_lu_scan(fs); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); SPIFFS_DBG("page index byte len: "_SPIPRIi"\n", (u32_t)SPIFFS_CFG_LOG_PAGE_SZ(fs)); SPIFFS_DBG("object lookup pages: "_SPIPRIi"\n", (u32_t)SPIFFS_OBJ_LOOKUP_PAGES(fs)); SPIFFS_DBG("page pages per block: "_SPIPRIi"\n", (u32_t)SPIFFS_PAGES_PER_BLOCK(fs)); SPIFFS_DBG("page header length: "_SPIPRIi"\n", (u32_t)sizeof(spiffs_page_header)); SPIFFS_DBG("object header index entries: "_SPIPRIi"\n", (u32_t)SPIFFS_OBJ_HDR_IX_LEN(fs)); SPIFFS_DBG("object index entries: "_SPIPRIi"\n", (u32_t)SPIFFS_OBJ_IX_LEN(fs)); SPIFFS_DBG("available file descriptors: "_SPIPRIi"\n", (u32_t)fs->fd_count); SPIFFS_DBG("free blocks: "_SPIPRIi"\n", (u32_t)fs->free_blocks); fs->check_cb_f = check_cb_f; fs->mounted = 1; SPIFFS_UNLOCK(fs); return 0; } void SPIFFS_unmount(spiffs *fs) { SPIFFS_API_DBG("%s\n", __func__); if (!SPIFFS_CHECK_CFG(fs) || !SPIFFS_CHECK_MOUNT(fs)) return; SPIFFS_LOCK(fs); u32_t i; spiffs_fd *fds = (spiffs_fd *)fs->fd_space; for (i = 0; i < fs->fd_count; i++) { spiffs_fd *cur_fd = &fds[i]; if (cur_fd->file_nbr != 0) { #if SPIFFS_CACHE (void)spiffs_fflush_cache(fs, cur_fd->file_nbr); #endif spiffs_fd_return(fs, cur_fd->file_nbr); } } fs->mounted = 0; SPIFFS_UNLOCK(fs); } s32_t SPIFFS_errno(spiffs *fs) { return fs->err_code; } void SPIFFS_clearerr(spiffs *fs) { SPIFFS_API_DBG("%s\n", __func__); fs->err_code = SPIFFS_OK; } s32_t SPIFFS_creat(spiffs *fs, const char *path, spiffs_mode mode) { SPIFFS_API_DBG("%s '%s'\n", __func__, path); #if SPIFFS_READ_ONLY (void)fs; (void)path; (void)mode; return SPIFFS_ERR_RO_NOT_IMPL; #else (void)mode; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); if (strlen(path) > SPIFFS_OBJ_NAME_LEN - 1) { SPIFFS_API_CHECK_RES(fs, SPIFFS_ERR_NAME_TOO_LONG); } SPIFFS_LOCK(fs); spiffs_obj_id obj_id; s32_t res; res = spiffs_obj_lu_find_free_obj_id(fs, &obj_id, (const u8_t *)path); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_object_create(fs, obj_id, (const u8_t *)path, 0, SPIFFS_TYPE_FILE, 0); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); SPIFFS_UNLOCK(fs); return 0; #endif // SPIFFS_READ_ONLY } spiffs_file SPIFFS_open(spiffs *fs, const char *path, spiffs_flags flags, spiffs_mode mode) { SPIFFS_API_DBG("%s '%s' "_SPIPRIfl "\n", __func__, path, flags); (void)mode; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); if (strlen(path) > SPIFFS_OBJ_NAME_LEN - 1) { SPIFFS_API_CHECK_RES(fs, SPIFFS_ERR_NAME_TOO_LONG); } SPIFFS_LOCK(fs); spiffs_fd *fd; spiffs_page_ix pix; #if SPIFFS_READ_ONLY // not valid flags in read only mode flags &= ~(SPIFFS_WRONLY | SPIFFS_CREAT | SPIFFS_TRUNC); #endif // SPIFFS_READ_ONLY s32_t res = spiffs_fd_find_new(fs, &fd, path); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_object_find_object_index_header_by_name(fs, (const u8_t *)path, &pix); if ((flags & SPIFFS_O_CREAT) == 0) { if (res < SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } if (res == SPIFFS_OK && (flags & (SPIFFS_O_CREAT | SPIFFS_O_EXCL)) == (SPIFFS_O_CREAT | SPIFFS_O_EXCL)) { // creat and excl and file exists - fail res = SPIFFS_ERR_FILE_EXISTS; spiffs_fd_return(fs, fd->file_nbr); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } if ((flags & SPIFFS_O_CREAT) && res == SPIFFS_ERR_NOT_FOUND) { #if !SPIFFS_READ_ONLY spiffs_obj_id obj_id; // no need to enter conflicting name here, already looked for it above res = spiffs_obj_lu_find_free_obj_id(fs, &obj_id, 0); if (res < SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_object_create(fs, obj_id, (const u8_t *)path, 0, SPIFFS_TYPE_FILE, &pix); if (res < SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); flags &= ~SPIFFS_O_TRUNC; #endif // !SPIFFS_READ_ONLY } else { if (res < SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } res = spiffs_object_open_by_page(fs, pix, fd, flags, mode); if (res < SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); #if !SPIFFS_READ_ONLY if (flags & SPIFFS_O_TRUNC) { res = spiffs_object_truncate(fd, 0, 0); if (res < SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } #endif // !SPIFFS_READ_ONLY fd->fdoffset = 0; SPIFFS_UNLOCK(fs); return SPIFFS_FH_OFFS(fs, fd->file_nbr); } spiffs_file SPIFFS_open_by_dirent(spiffs *fs, struct spiffs_dirent *e, spiffs_flags flags, spiffs_mode mode) { SPIFFS_API_DBG("%s '%s':"_SPIPRIid " "_SPIPRIfl "\n", __func__, e->name, e->obj_id, flags); SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); spiffs_fd *fd; s32_t res = spiffs_fd_find_new(fs, &fd, 0); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_object_open_by_page(fs, e->pix, fd, flags, mode); if (res < SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); #if !SPIFFS_READ_ONLY if (flags & SPIFFS_O_TRUNC) { res = spiffs_object_truncate(fd, 0, 0); if (res < SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } #endif // !SPIFFS_READ_ONLY fd->fdoffset = 0; SPIFFS_UNLOCK(fs); return SPIFFS_FH_OFFS(fs, fd->file_nbr); } spiffs_file SPIFFS_open_by_page(spiffs *fs, spiffs_page_ix page_ix, spiffs_flags flags, spiffs_mode mode) { SPIFFS_API_DBG("%s "_SPIPRIpg " "_SPIPRIfl "\n", __func__, page_ix, flags); SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); spiffs_fd *fd; s32_t res = spiffs_fd_find_new(fs, &fd, 0); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); if (SPIFFS_IS_LOOKUP_PAGE(fs, page_ix)) { res = SPIFFS_ERR_NOT_A_FILE; spiffs_fd_return(fs, fd->file_nbr); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } res = spiffs_object_open_by_page(fs, page_ix, fd, flags, mode); if (res == SPIFFS_ERR_IS_FREE || res == SPIFFS_ERR_DELETED || res == SPIFFS_ERR_NOT_FINALIZED || res == SPIFFS_ERR_NOT_INDEX || res == SPIFFS_ERR_INDEX_SPAN_MISMATCH) { res = SPIFFS_ERR_NOT_A_FILE; } if (res < SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); #if !SPIFFS_READ_ONLY if (flags & SPIFFS_O_TRUNC) { res = spiffs_object_truncate(fd, 0, 0); if (res < SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } #endif // !SPIFFS_READ_ONLY fd->fdoffset = 0; SPIFFS_UNLOCK(fs); return SPIFFS_FH_OFFS(fs, fd->file_nbr); } static s32_t spiffs_hydro_read(spiffs *fs, spiffs_file fh, void *buf, s32_t len) { SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); spiffs_fd *fd; s32_t res; fh = SPIFFS_FH_UNOFFS(fs, fh); res = spiffs_fd_get(fs, fh, &fd); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); if ((fd->flags & SPIFFS_O_RDONLY) == 0) { res = SPIFFS_ERR_NOT_READABLE; SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } if (fd->size == SPIFFS_UNDEFINED_LEN && len > 0) { // special case for zero sized files res = SPIFFS_ERR_END_OF_OBJECT; SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } #if SPIFFS_CACHE_WR spiffs_fflush_cache(fs, fh); #endif if (fd->fdoffset + len >= fd->size) { // reading beyond file size s32_t avail = fd->size - fd->fdoffset; if (avail <= 0) { SPIFFS_API_CHECK_RES_UNLOCK(fs, SPIFFS_ERR_END_OF_OBJECT); } res = spiffs_object_read(fd, fd->fdoffset, avail, (u8_t *)buf); if (res == SPIFFS_ERR_END_OF_OBJECT) { fd->fdoffset += avail; SPIFFS_UNLOCK(fs); return avail; } else { SPIFFS_API_CHECK_RES_UNLOCK(fs, res); len = avail; } } else { // reading within file size res = spiffs_object_read(fd, fd->fdoffset, len, (u8_t *)buf); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } fd->fdoffset += len; SPIFFS_UNLOCK(fs); return len; } s32_t SPIFFS_read(spiffs *fs, spiffs_file fh, void *buf, s32_t len) { SPIFFS_API_DBG("%s "_SPIPRIfd " "_SPIPRIi "\n", __func__, fh, len); s32_t res = spiffs_hydro_read(fs, fh, buf, len); if (res == SPIFFS_ERR_END_OF_OBJECT) { res = 0; } return res; } #if !SPIFFS_READ_ONLY static s32_t spiffs_hydro_write(spiffs *fs, spiffs_fd *fd, void *buf, u32_t offset, s32_t len) { (void)fs; s32_t res = SPIFFS_OK; s32_t remaining = len; if (fd->size != SPIFFS_UNDEFINED_LEN && offset < fd->size) { s32_t m_len = MIN((s32_t)(fd->size - offset), len); res = spiffs_object_modify(fd, offset, (u8_t *)buf, m_len); SPIFFS_CHECK_RES(res); remaining -= m_len; u8_t *buf_8 = (u8_t *)buf; buf_8 += m_len; buf = buf_8; offset += m_len; } if (remaining > 0) { res = spiffs_object_append(fd, offset, (u8_t *)buf, remaining); SPIFFS_CHECK_RES(res); } return len; } #endif // !SPIFFS_READ_ONLY s32_t SPIFFS_write(spiffs *fs, spiffs_file fh, void *buf, s32_t len) { SPIFFS_API_DBG("%s "_SPIPRIfd " "_SPIPRIi "\n", __func__, fh, len); #if SPIFFS_READ_ONLY (void)fs; (void)fh; (void)buf; (void)len; return SPIFFS_ERR_RO_NOT_IMPL; #else SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); spiffs_fd *fd; s32_t res; u32_t offset; fh = SPIFFS_FH_UNOFFS(fs, fh); res = spiffs_fd_get(fs, fh, &fd); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); if ((fd->flags & SPIFFS_O_WRONLY) == 0) { res = SPIFFS_ERR_NOT_WRITABLE; SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } if ((fd->flags & SPIFFS_O_APPEND)) { fd->fdoffset = fd->size == SPIFFS_UNDEFINED_LEN ? 0 : fd->size; } offset = fd->fdoffset; #if SPIFFS_CACHE_WR if (fd->cache_page == 0) { // see if object id is associated with cache already fd->cache_page = spiffs_cache_page_get_by_fd(fs, fd); } #endif if (fd->flags & SPIFFS_O_APPEND) { if (fd->size == SPIFFS_UNDEFINED_LEN) { offset = 0; } else { offset = fd->size; } #if SPIFFS_CACHE_WR if (fd->cache_page) { offset = MAX(offset, fd->cache_page->offset + fd->cache_page->size); } #endif } #if SPIFFS_CACHE_WR if ((fd->flags & SPIFFS_O_DIRECT) == 0) { if (len < (s32_t)SPIFFS_CFG_LOG_PAGE_SZ(fs)) { // small write, try to cache it u8_t alloc_cpage = 1; if (fd->cache_page) { // have a cached page for this fd already, check cache page boundaries if (offset < fd->cache_page->offset || // writing before cache offset > fd->cache_page->offset + fd->cache_page->size || // writing after cache offset + len > fd->cache_page->offset + SPIFFS_CFG_LOG_PAGE_SZ(fs)) // writing beyond cache page { // boundary violation, write back cache first and allocate new SPIFFS_CACHE_DBG("CACHE_WR_DUMP: dumping cache page "_SPIPRIi" for fd "_SPIPRIfd":"_SPIPRIid", boundary viol, offs:"_SPIPRIi" size:"_SPIPRIi"\n", fd->cache_page->ix, fd->file_nbr, fd->obj_id, fd->cache_page->offset, fd->cache_page->size); res = spiffs_hydro_write(fs, fd, spiffs_get_cache_page(fs, spiffs_get_cache(fs), fd->cache_page->ix), fd->cache_page->offset, fd->cache_page->size); spiffs_cache_fd_release(fs, fd->cache_page); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } else { // writing within cache alloc_cpage = 0; } } if (alloc_cpage) { fd->cache_page = spiffs_cache_page_allocate_by_fd(fs, fd); if (fd->cache_page) { fd->cache_page->offset = offset; fd->cache_page->size = 0; SPIFFS_CACHE_DBG("CACHE_WR_ALLO: allocating cache page "_SPIPRIi" for fd "_SPIPRIfd":"_SPIPRIid"\n", fd->cache_page->ix, fd->file_nbr, fd->obj_id); } } if (fd->cache_page) { u32_t offset_in_cpage = offset - fd->cache_page->offset; SPIFFS_CACHE_DBG("CACHE_WR_WRITE: storing to cache page "_SPIPRIi" for fd "_SPIPRIfd":"_SPIPRIid", offs "_SPIPRIi":"_SPIPRIi" len "_SPIPRIi"\n", fd->cache_page->ix, fd->file_nbr, fd->obj_id, offset, offset_in_cpage, len); spiffs_cache *cache = spiffs_get_cache(fs); u8_t *cpage_data = spiffs_get_cache_page(fs, cache, fd->cache_page->ix); #ifdef _SPIFFS_TEST { intptr_t __a1 = (u8_t *)&cpage_data[offset_in_cpage] - (u8_t *)cache; intptr_t __a2 = (u8_t *)&cpage_data[offset_in_cpage] + len - (u8_t *)cache; intptr_t __b = sizeof(spiffs_cache) + cache->cpage_count * (sizeof(spiffs_cache_page) + SPIFFS_CFG_LOG_PAGE_SZ(fs)); if (__a1 > __b || __a2 > __b) { printf("FATAL OOB: CACHE_WR: memcpy to cache buffer ixs:%4ld..%4ld of %4ld\n", __a1, __a2, __b); ERREXIT(); } } #endif _SPIFFS_MEMCPY(&cpage_data[offset_in_cpage], buf, len); fd->cache_page->size = MAX(fd->cache_page->size, offset_in_cpage + len); fd->fdoffset += len; SPIFFS_UNLOCK(fs); return len; } else { res = spiffs_hydro_write(fs, fd, buf, offset, len); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); fd->fdoffset += len; SPIFFS_UNLOCK(fs); return res; } } else { // big write, no need to cache it - but first check if there is a cached write already if (fd->cache_page) { // write back cache first SPIFFS_CACHE_DBG("CACHE_WR_DUMP: dumping cache page "_SPIPRIi" for fd "_SPIPRIfd":"_SPIPRIid", big write, offs:"_SPIPRIi" size:"_SPIPRIi"\n", fd->cache_page->ix, fd->file_nbr, fd->obj_id, fd->cache_page->offset, fd->cache_page->size); res = spiffs_hydro_write(fs, fd, spiffs_get_cache_page(fs, spiffs_get_cache(fs), fd->cache_page->ix), fd->cache_page->offset, fd->cache_page->size); spiffs_cache_fd_release(fs, fd->cache_page); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); // data written below } } } #endif res = spiffs_hydro_write(fs, fd, buf, offset, len); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); fd->fdoffset += len; SPIFFS_UNLOCK(fs); return res; #endif // SPIFFS_READ_ONLY } s32_t SPIFFS_lseek(spiffs *fs, spiffs_file fh, s32_t offs, int whence) { SPIFFS_API_DBG("%s "_SPIPRIfd " "_SPIPRIi " %s\n", __func__, fh, offs, (const char *[]) {"SET", "CUR", "END", "???" }[MIN(whence, 3)]); SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); spiffs_fd *fd; s32_t res; fh = SPIFFS_FH_UNOFFS(fs, fh); res = spiffs_fd_get(fs, fh, &fd); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); #if SPIFFS_CACHE_WR spiffs_fflush_cache(fs, fh); #endif s32_t file_size = fd->size == SPIFFS_UNDEFINED_LEN ? 0 : fd->size; switch (whence) { case SPIFFS_SEEK_SET: break; case SPIFFS_SEEK_CUR: offs = fd->fdoffset + offs; break; case SPIFFS_SEEK_END: offs = file_size + offs; break; default: res = SPIFFS_ERR_INVALID_PARA; break; } if (offs < 0) { SPIFFS_API_CHECK_RES_UNLOCK(fs, SPIFFS_ERR_INVALID_PARA); } if (offs > file_size) { fd->fdoffset = file_size; res = SPIFFS_ERR_SEEK_BOUNDS; } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); spiffs_span_ix data_spix = (offs > 0 ? (offs - 1) : 0) / SPIFFS_DATA_PAGE_SIZE(fs); spiffs_span_ix objix_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, data_spix); if (fd->cursor_objix_spix != objix_spix) { spiffs_page_ix pix; res = spiffs_obj_lu_find_id_and_span( fs, fd->obj_id | SPIFFS_OBJ_ID_IX_FLAG, objix_spix, 0, &pix); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); fd->cursor_objix_spix = objix_spix; fd->cursor_objix_pix = pix; } fd->fdoffset = offs; SPIFFS_UNLOCK(fs); return offs; } s32_t SPIFFS_remove(spiffs *fs, const char *path) { SPIFFS_API_DBG("%s '%s'\n", __func__, path); #if SPIFFS_READ_ONLY (void)fs; (void)path; return SPIFFS_ERR_RO_NOT_IMPL; #else SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); if (strlen(path) > SPIFFS_OBJ_NAME_LEN - 1) { SPIFFS_API_CHECK_RES(fs, SPIFFS_ERR_NAME_TOO_LONG); } SPIFFS_LOCK(fs); spiffs_fd *fd; spiffs_page_ix pix; s32_t res; res = spiffs_fd_find_new(fs, &fd, 0); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_object_find_object_index_header_by_name(fs, (const u8_t *)path, &pix); if (res != SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_object_open_by_page(fs, pix, fd, 0, 0); if (res != SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_object_truncate(fd, 0, 1); if (res != SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); SPIFFS_UNLOCK(fs); return 0; #endif // SPIFFS_READ_ONLY } s32_t SPIFFS_fremove(spiffs *fs, spiffs_file fh) { SPIFFS_API_DBG("%s "_SPIPRIfd "\n", __func__, fh); #if SPIFFS_READ_ONLY (void)fs; (void)fh; return SPIFFS_ERR_RO_NOT_IMPL; #else SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); spiffs_fd *fd; s32_t res; fh = SPIFFS_FH_UNOFFS(fs, fh); res = spiffs_fd_get(fs, fh, &fd); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); if ((fd->flags & SPIFFS_O_WRONLY) == 0) { res = SPIFFS_ERR_NOT_WRITABLE; SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } #if SPIFFS_CACHE_WR spiffs_cache_fd_release(fs, fd->cache_page); #endif res = spiffs_object_truncate(fd, 0, 1); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); SPIFFS_UNLOCK(fs); return 0; #endif // SPIFFS_READ_ONLY } static s32_t spiffs_stat_pix(spiffs *fs, spiffs_page_ix pix, spiffs_file fh, spiffs_stat *s) { (void)fh; spiffs_page_object_ix_header objix_hdr; spiffs_obj_id obj_id; s32_t res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_READ, fh, SPIFFS_PAGE_TO_PADDR(fs, pix), sizeof(spiffs_page_object_ix_header), (u8_t *)&objix_hdr); SPIFFS_API_CHECK_RES(fs, res); u32_t obj_id_addr = SPIFFS_BLOCK_TO_PADDR(fs, SPIFFS_BLOCK_FOR_PAGE(fs , pix)) + SPIFFS_OBJ_LOOKUP_ENTRY_FOR_PAGE(fs, pix) * sizeof(spiffs_obj_id); res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, fh, obj_id_addr, sizeof(spiffs_obj_id), (u8_t *)&obj_id); SPIFFS_API_CHECK_RES(fs, res); s->obj_id = obj_id & ~SPIFFS_OBJ_ID_IX_FLAG; s->type = objix_hdr.type; s->size = objix_hdr.size == SPIFFS_UNDEFINED_LEN ? 0 : objix_hdr.size; s->pix = pix; strncpy((char *)s->name, (char *)objix_hdr.name, SPIFFS_OBJ_NAME_LEN); #if SPIFFS_OBJ_META_LEN _SPIFFS_MEMCPY(s->meta, objix_hdr.meta, SPIFFS_OBJ_META_LEN); #endif return res; } s32_t SPIFFS_stat(spiffs *fs, const char *path, spiffs_stat *s) { SPIFFS_API_DBG("%s '%s'\n", __func__, path); SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); if (strlen(path) > SPIFFS_OBJ_NAME_LEN - 1) { SPIFFS_API_CHECK_RES(fs, SPIFFS_ERR_NAME_TOO_LONG); } SPIFFS_LOCK(fs); s32_t res; spiffs_page_ix pix; res = spiffs_object_find_object_index_header_by_name(fs, (const u8_t *)path, &pix); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_stat_pix(fs, pix, 0, s); SPIFFS_UNLOCK(fs); return res; } s32_t SPIFFS_fstat(spiffs *fs, spiffs_file fh, spiffs_stat *s) { SPIFFS_API_DBG("%s "_SPIPRIfd "\n", __func__, fh); SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); spiffs_fd *fd; s32_t res; fh = SPIFFS_FH_UNOFFS(fs, fh); res = spiffs_fd_get(fs, fh, &fd); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); #if SPIFFS_CACHE_WR spiffs_fflush_cache(fs, fh); #endif res = spiffs_stat_pix(fs, fd->objix_hdr_pix, fh, s); SPIFFS_UNLOCK(fs); return res; } // Checks if there are any cached writes for the object id associated with // given filehandle. If so, these writes are flushed. #if SPIFFS_CACHE == 1 static s32_t spiffs_fflush_cache(spiffs *fs, spiffs_file fh) { (void)fs; (void)fh; s32_t res = SPIFFS_OK; #if !SPIFFS_READ_ONLY && SPIFFS_CACHE_WR spiffs_fd *fd; res = spiffs_fd_get(fs, fh, &fd); SPIFFS_API_CHECK_RES(fs, res); if ((fd->flags & SPIFFS_O_DIRECT) == 0) { if (fd->cache_page == 0) { // see if object id is associated with cache already fd->cache_page = spiffs_cache_page_get_by_fd(fs, fd); } if (fd->cache_page) { SPIFFS_CACHE_DBG("CACHE_WR_DUMP: dumping cache page "_SPIPRIi" for fd "_SPIPRIfd":"_SPIPRIid", flush, offs:"_SPIPRIi" size:"_SPIPRIi"\n", fd->cache_page->ix, fd->file_nbr, fd->obj_id, fd->cache_page->offset, fd->cache_page->size); res = spiffs_hydro_write(fs, fd, spiffs_get_cache_page(fs, spiffs_get_cache(fs), fd->cache_page->ix), fd->cache_page->offset, fd->cache_page->size); if (res < SPIFFS_OK) { fs->err_code = res; } spiffs_cache_fd_release(fs, fd->cache_page); } } #endif return res; } #endif s32_t SPIFFS_fflush(spiffs *fs, spiffs_file fh) { SPIFFS_API_DBG("%s "_SPIPRIfd "\n", __func__, fh); (void)fh; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); s32_t res = SPIFFS_OK; #if !SPIFFS_READ_ONLY && SPIFFS_CACHE_WR SPIFFS_LOCK(fs); fh = SPIFFS_FH_UNOFFS(fs, fh); res = spiffs_fflush_cache(fs, fh); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); SPIFFS_UNLOCK(fs); #endif return res; } s32_t SPIFFS_close(spiffs *fs, spiffs_file fh) { SPIFFS_API_DBG("%s "_SPIPRIfd "\n", __func__, fh); SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); s32_t res = SPIFFS_OK; SPIFFS_LOCK(fs); fh = SPIFFS_FH_UNOFFS(fs, fh); #if SPIFFS_CACHE res = spiffs_fflush_cache(fs, fh); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); #endif res = spiffs_fd_return(fs, fh); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); SPIFFS_UNLOCK(fs); return res; } s32_t SPIFFS_rename(spiffs *fs, const char *old_path, const char *new_path) { SPIFFS_API_DBG("%s %s %s\n", __func__, old_path, new_path); #if SPIFFS_READ_ONLY (void)fs; (void)old_path; (void)new_path; return SPIFFS_ERR_RO_NOT_IMPL; #else SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); if (strlen(new_path) > SPIFFS_OBJ_NAME_LEN - 1 || strlen(old_path) > SPIFFS_OBJ_NAME_LEN - 1) { SPIFFS_API_CHECK_RES(fs, SPIFFS_ERR_NAME_TOO_LONG); } SPIFFS_LOCK(fs); spiffs_page_ix pix_old, pix_dummy; spiffs_fd *fd; s32_t res = spiffs_object_find_object_index_header_by_name(fs, (const u8_t *)old_path, &pix_old); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_object_find_object_index_header_by_name(fs, (const u8_t *)new_path, &pix_dummy); if (res == SPIFFS_ERR_NOT_FOUND) { res = SPIFFS_OK; } else if (res == SPIFFS_OK) { res = SPIFFS_ERR_CONFLICTING_NAME; } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_fd_find_new(fs, &fd, 0); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_object_open_by_page(fs, pix_old, fd, 0, 0); if (res != SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, fd->objix_hdr_pix, 0, (const u8_t *)new_path, 0, 0, &pix_dummy); #if SPIFFS_TEMPORAL_FD_CACHE if (res == SPIFFS_OK) { spiffs_fd_temporal_cache_rehash(fs, old_path, new_path); } #endif spiffs_fd_return(fs, fd->file_nbr); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); SPIFFS_UNLOCK(fs); return res; #endif // SPIFFS_READ_ONLY } #if SPIFFS_OBJ_META_LEN s32_t SPIFFS_update_meta(spiffs *fs, const char *name, const void *meta) { #if SPIFFS_READ_ONLY (void)fs; (void)name; (void)meta; return SPIFFS_ERR_RO_NOT_IMPL; #else SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); spiffs_page_ix pix, pix_dummy; spiffs_fd *fd; s32_t res = spiffs_object_find_object_index_header_by_name(fs, (const u8_t *)name, &pix); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_fd_find_new(fs, &fd, 0); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_object_open_by_page(fs, pix, fd, 0, 0); if (res != SPIFFS_OK) { spiffs_fd_return(fs, fd->file_nbr); } SPIFFS_API_CHECK_RES_UNLOCK(fs, res); res = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, fd->objix_hdr_pix, 0, 0, meta, 0, &pix_dummy); spiffs_fd_return(fs, fd->file_nbr); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); SPIFFS_UNLOCK(fs); return res; #endif // SPIFFS_READ_ONLY } s32_t SPIFFS_fupdate_meta(spiffs *fs, spiffs_file fh, const void *meta) { #if SPIFFS_READ_ONLY (void)fs; (void)fh; (void)meta; return SPIFFS_ERR_RO_NOT_IMPL; #else SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); s32_t res; spiffs_fd *fd; spiffs_page_ix pix_dummy; fh = SPIFFS_FH_UNOFFS(fs, fh); res = spiffs_fd_get(fs, fh, &fd); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); if ((fd->flags & SPIFFS_O_WRONLY) == 0) { res = SPIFFS_ERR_NOT_WRITABLE; SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } res = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, fd->objix_hdr_pix, 0, 0, meta, 0, &pix_dummy); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); SPIFFS_UNLOCK(fs); return res; #endif // SPIFFS_READ_ONLY } #endif // SPIFFS_OBJ_META_LEN spiffs_DIR *SPIFFS_opendir(spiffs *fs, const char *name, spiffs_DIR *d) { SPIFFS_API_DBG("%s\n", __func__); (void)name; if (!SPIFFS_CHECK_CFG((fs))) { (fs)->err_code = SPIFFS_ERR_NOT_CONFIGURED; return 0; } if (!SPIFFS_CHECK_MOUNT(fs)) { fs->err_code = SPIFFS_ERR_NOT_MOUNTED; return 0; } d->fs = fs; d->block = 0; d->entry = 0; return d; } static s32_t spiffs_read_dir_v( spiffs *fs, spiffs_obj_id obj_id, spiffs_block_ix bix, int ix_entry, const void *user_const_p, void *user_var_p) { (void)user_const_p; s32_t res; spiffs_page_object_ix_header objix_hdr; if (obj_id == SPIFFS_OBJ_ID_FREE || obj_id == SPIFFS_OBJ_ID_DELETED || (obj_id & SPIFFS_OBJ_ID_IX_FLAG) == 0) { return SPIFFS_VIS_COUNTINUE; } spiffs_page_ix pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, ix_entry); res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, pix), sizeof(spiffs_page_object_ix_header), (u8_t *)&objix_hdr); if (res != SPIFFS_OK) return res; if ((obj_id & SPIFFS_OBJ_ID_IX_FLAG) && objix_hdr.p_hdr.span_ix == 0 && (objix_hdr.p_hdr.flags & (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_IXDELE)) == (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_IXDELE)) { struct spiffs_dirent *e = (struct spiffs_dirent *)user_var_p; e->obj_id = obj_id; strcpy((char *)e->name, (char *)objix_hdr.name); e->type = objix_hdr.type; e->size = objix_hdr.size == SPIFFS_UNDEFINED_LEN ? 0 : objix_hdr.size; e->pix = pix; #if SPIFFS_OBJ_META_LEN _SPIFFS_MEMCPY(e->meta, objix_hdr.meta, SPIFFS_OBJ_META_LEN); #endif return SPIFFS_OK; } return SPIFFS_VIS_COUNTINUE; } struct spiffs_dirent *SPIFFS_readdir(spiffs_DIR *d, struct spiffs_dirent *e) { SPIFFS_API_DBG("%s\n", __func__); if (!SPIFFS_CHECK_MOUNT(d->fs)) { d->fs->err_code = SPIFFS_ERR_NOT_MOUNTED; return 0; } SPIFFS_LOCK(d->fs); spiffs_block_ix bix; int entry; s32_t res; struct spiffs_dirent *ret = 0; res = spiffs_obj_lu_find_entry_visitor(d->fs, d->block, d->entry, SPIFFS_VIS_NO_WRAP, 0, spiffs_read_dir_v, 0, e, &bix, &entry); if (res == SPIFFS_OK) { d->block = bix; d->entry = entry + 1; e->obj_id &= ~SPIFFS_OBJ_ID_IX_FLAG; ret = e; } else { d->fs->err_code = res; } SPIFFS_UNLOCK(d->fs); return ret; } s32_t SPIFFS_closedir(spiffs_DIR *d) { SPIFFS_API_DBG("%s\n", __func__); SPIFFS_API_CHECK_CFG(d->fs); SPIFFS_API_CHECK_MOUNT(d->fs); return 0; } s32_t SPIFFS_check(spiffs *fs) { SPIFFS_API_DBG("%s\n", __func__); #if SPIFFS_READ_ONLY (void)fs; return SPIFFS_ERR_RO_NOT_IMPL; #else s32_t res; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); res = spiffs_lookup_consistency_check(fs, 0); res = spiffs_object_index_consistency_check(fs); res = spiffs_page_consistency_check(fs); res = spiffs_obj_lu_scan(fs); SPIFFS_UNLOCK(fs); return res; #endif // SPIFFS_READ_ONLY } s32_t SPIFFS_info(spiffs *fs, u32_t *total, u32_t *used) { SPIFFS_API_DBG("%s\n", __func__); s32_t res = SPIFFS_OK; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); u32_t pages_per_block = SPIFFS_PAGES_PER_BLOCK(fs); u32_t blocks = fs->block_count; u32_t obj_lu_pages = SPIFFS_OBJ_LOOKUP_PAGES(fs); u32_t data_page_size = SPIFFS_DATA_PAGE_SIZE(fs); u32_t total_data_pages = (blocks - 2) * (pages_per_block - obj_lu_pages) + 1; // -2 for spare blocks, +1 for emergency page if (total) { *total = total_data_pages * data_page_size; } if (used) { *used = fs->stats_p_allocated * data_page_size; } SPIFFS_UNLOCK(fs); return res; } s32_t SPIFFS_gc_quick(spiffs *fs, u16_t max_free_pages) { SPIFFS_API_DBG("%s "_SPIPRIi "\n", __func__, max_free_pages); #if SPIFFS_READ_ONLY (void)fs; (void)max_free_pages; return SPIFFS_ERR_RO_NOT_IMPL; #else s32_t res; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); res = spiffs_gc_quick(fs, max_free_pages); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); SPIFFS_UNLOCK(fs); return 0; #endif // SPIFFS_READ_ONLY } s32_t SPIFFS_gc(spiffs *fs, u32_t size) { SPIFFS_API_DBG("%s "_SPIPRIi "\n", __func__, size); #if SPIFFS_READ_ONLY (void)fs; (void)size; return SPIFFS_ERR_RO_NOT_IMPL; #else s32_t res; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); res = spiffs_gc_check(fs, size); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); SPIFFS_UNLOCK(fs); return 0; #endif // SPIFFS_READ_ONLY } s32_t SPIFFS_eof(spiffs *fs, spiffs_file fh) { SPIFFS_API_DBG("%s "_SPIPRIfd "\n", __func__, fh); s32_t res; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); fh = SPIFFS_FH_UNOFFS(fs, fh); spiffs_fd *fd; res = spiffs_fd_get(fs, fh, &fd); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); #if SPIFFS_CACHE_WR res = spiffs_fflush_cache(fs, fh); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); #endif res = (fd->fdoffset >= (fd->size == SPIFFS_UNDEFINED_LEN ? 0 : fd->size)); SPIFFS_UNLOCK(fs); return res; } s32_t SPIFFS_tell(spiffs *fs, spiffs_file fh) { SPIFFS_API_DBG("%s "_SPIPRIfd "\n", __func__, fh); s32_t res; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); fh = SPIFFS_FH_UNOFFS(fs, fh); spiffs_fd *fd; res = spiffs_fd_get(fs, fh, &fd); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); #if SPIFFS_CACHE_WR res = spiffs_fflush_cache(fs, fh); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); #endif res = fd->fdoffset; SPIFFS_UNLOCK(fs); return res; } s32_t SPIFFS_set_file_callback_func(spiffs *fs, spiffs_file_callback cb_func) { SPIFFS_API_DBG("%s\n", __func__); SPIFFS_LOCK(fs); fs->file_cb_f = cb_func; SPIFFS_UNLOCK(fs); return 0; } #if SPIFFS_IX_MAP s32_t SPIFFS_ix_map(spiffs *fs, spiffs_file fh, spiffs_ix_map *map, u32_t offset, u32_t len, spiffs_page_ix *map_buf) { SPIFFS_API_DBG("%s "_SPIPRIfd " "_SPIPRIi " "_SPIPRIi "\n", __func__, fh, offset, len); s32_t res; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); fh = SPIFFS_FH_UNOFFS(fs, fh); spiffs_fd *fd; res = spiffs_fd_get(fs, fh, &fd); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); if (fd->ix_map) { SPIFFS_API_CHECK_RES_UNLOCK(fs, SPIFFS_ERR_IX_MAP_MAPPED); } map->map_buf = map_buf; map->offset = offset; // nb: spix range includes last map->start_spix = offset / SPIFFS_DATA_PAGE_SIZE(fs); map->end_spix = (offset + len) / SPIFFS_DATA_PAGE_SIZE(fs); memset(map_buf, 0, sizeof(spiffs_page_ix) * (map->end_spix - map->start_spix + 1)); fd->ix_map = map; // scan for pixes res = spiffs_populate_ix_map(fs, fd, 0, map->end_spix - map->start_spix + 1); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); SPIFFS_UNLOCK(fs); return res; } s32_t SPIFFS_ix_unmap(spiffs *fs, spiffs_file fh) { SPIFFS_API_DBG("%s "_SPIPRIfd "\n", __func__, fh); s32_t res; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); fh = SPIFFS_FH_UNOFFS(fs, fh); spiffs_fd *fd; res = spiffs_fd_get(fs, fh, &fd); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); if (fd->ix_map == 0) { SPIFFS_API_CHECK_RES_UNLOCK(fs, SPIFFS_ERR_IX_MAP_UNMAPPED); } fd->ix_map = 0; SPIFFS_UNLOCK(fs); return res; } s32_t SPIFFS_ix_remap(spiffs *fs, spiffs_file fh, u32_t offset) { SPIFFS_API_DBG("%s "_SPIPRIfd " "_SPIPRIi "\n", __func__, fh, offset); s32_t res = SPIFFS_OK; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); fh = SPIFFS_FH_UNOFFS(fs, fh); spiffs_fd *fd; res = spiffs_fd_get(fs, fh, &fd); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); if (fd->ix_map == 0) { SPIFFS_API_CHECK_RES_UNLOCK(fs, SPIFFS_ERR_IX_MAP_UNMAPPED); } spiffs_ix_map *map = fd->ix_map; s32_t spix_diff = offset / SPIFFS_DATA_PAGE_SIZE(fs) - map->start_spix; map->offset = offset; // move existing pixes if within map offs if (spix_diff != 0) { // move vector int i; const s32_t vec_len = map->end_spix - map->start_spix + 1; // spix range includes last map->start_spix += spix_diff; map->end_spix += spix_diff; if (spix_diff >= vec_len) { // moving beyond range memset(&map->map_buf, 0, vec_len * sizeof(spiffs_page_ix)); // populate_ix_map is inclusive res = spiffs_populate_ix_map(fs, fd, 0, vec_len - 1); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } else if (spix_diff > 0) { // diff positive for (i = 0; i < vec_len - spix_diff; i++) { map->map_buf[i] = map->map_buf[i + spix_diff]; } // memset is non-inclusive memset(&map->map_buf[vec_len - spix_diff], 0, spix_diff * sizeof(spiffs_page_ix)); // populate_ix_map is inclusive res = spiffs_populate_ix_map(fs, fd, vec_len - spix_diff, vec_len - 1); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } else { // diff negative for (i = vec_len - 1; i >= -spix_diff; i--) { map->map_buf[i] = map->map_buf[i + spix_diff]; } // memset is non-inclusive memset(&map->map_buf[0], 0, -spix_diff * sizeof(spiffs_page_ix)); // populate_ix_map is inclusive res = spiffs_populate_ix_map(fs, fd, 0, -spix_diff - 1); SPIFFS_API_CHECK_RES_UNLOCK(fs, res); } } SPIFFS_UNLOCK(fs); return res; } s32_t SPIFFS_bytes_to_ix_map_entries(spiffs *fs, u32_t bytes) { SPIFFS_API_CHECK_CFG(fs); // always add one extra page, the offset might change to the middle of a page return (bytes + SPIFFS_DATA_PAGE_SIZE(fs) ) / SPIFFS_DATA_PAGE_SIZE(fs); } s32_t SPIFFS_ix_map_entries_to_bytes(spiffs *fs, u32_t map_page_ix_entries) { SPIFFS_API_CHECK_CFG(fs); return map_page_ix_entries * SPIFFS_DATA_PAGE_SIZE(fs); } #endif // SPIFFS_IX_MAP #if SPIFFS_TEST_VISUALISATION s32_t SPIFFS_vis(spiffs *fs) { s32_t res = SPIFFS_OK; SPIFFS_API_CHECK_CFG(fs); SPIFFS_API_CHECK_MOUNT(fs); SPIFFS_LOCK(fs); int entries_per_page = (SPIFFS_CFG_LOG_PAGE_SZ(fs) / sizeof(spiffs_obj_id)); spiffs_obj_id *obj_lu_buf = (spiffs_obj_id *)fs->lu_work; spiffs_block_ix bix = 0; while (bix < fs->block_count) { // check each object lookup page int obj_lookup_page = 0; int cur_entry = 0; while (res == SPIFFS_OK && obj_lookup_page < (int)SPIFFS_OBJ_LOOKUP_PAGES(fs)) { int entry_offset = obj_lookup_page * entries_per_page; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, 0, bix * SPIFFS_CFG_LOG_BLOCK_SZ(fs) + SPIFFS_PAGE_TO_PADDR(fs, obj_lookup_page), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->lu_work); // check each entry while (res == SPIFFS_OK && cur_entry - entry_offset < entries_per_page && cur_entry < (int)(SPIFFS_PAGES_PER_BLOCK(fs) - SPIFFS_OBJ_LOOKUP_PAGES(fs))) { spiffs_obj_id obj_id = obj_lu_buf[cur_entry - entry_offset]; if (cur_entry == 0) { spiffs_printf(_SPIPRIbl" ", bix); } else if ((cur_entry & 0x3f) == 0) { spiffs_printf(" "); } if (obj_id == SPIFFS_OBJ_ID_FREE) { spiffs_printf(SPIFFS_TEST_VIS_FREE_STR); } else if (obj_id == SPIFFS_OBJ_ID_DELETED) { spiffs_printf(SPIFFS_TEST_VIS_DELE_STR); } else if (obj_id & SPIFFS_OBJ_ID_IX_FLAG) { spiffs_printf(SPIFFS_TEST_VIS_INDX_STR(obj_id)); } else { spiffs_printf(SPIFFS_TEST_VIS_DATA_STR(obj_id)); } cur_entry++; if ((cur_entry & 0x3f) == 0) { spiffs_printf("\n"); } } // per entry obj_lookup_page++; } // per object lookup page spiffs_obj_id erase_count; res = _spiffs_rd(fs, SPIFFS_OP_C_READ | SPIFFS_OP_T_OBJ_LU2, 0, SPIFFS_ERASE_COUNT_PADDR(fs, bix), sizeof(spiffs_obj_id), (u8_t *)&erase_count); SPIFFS_CHECK_RES(res); if (erase_count != (spiffs_obj_id) - 1) { spiffs_printf("\tera_cnt: %d\n", erase_count); } else { spiffs_printf("\tera_cnt: N/A\n"); } bix++; } // per block spiffs_printf("era_cnt_max: %d\n", fs->max_erase_count); spiffs_printf("last_errno: "_SPIPRIi"\n", fs->err_code); spiffs_printf("blocks: "_SPIPRIi"\n", fs->block_count); spiffs_printf("free_blocks: "_SPIPRIi"\n", fs->free_blocks); spiffs_printf("page_alloc: "_SPIPRIi"\n", fs->stats_p_allocated); spiffs_printf("page_delet: "_SPIPRIi"\n", fs->stats_p_deleted); SPIFFS_UNLOCK(fs); u32_t total, used; SPIFFS_info(fs, &total, &used); spiffs_printf("used: "_SPIPRIi" of "_SPIPRIi"\n", used, total); return res; } #endif ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/src/spiffs_nucleus.c ================================================ #include "spiffs.h" #include "spiffs_nucleus.h" static s32_t spiffs_page_data_check(spiffs *fs, spiffs_fd *fd, spiffs_page_ix pix, spiffs_span_ix spix) { s32_t res = SPIFFS_OK; if (pix == (spiffs_page_ix) - 1) { // referring to page 0xffff...., bad object index return SPIFFS_ERR_INDEX_REF_FREE; } if (pix % SPIFFS_PAGES_PER_BLOCK(fs) < SPIFFS_OBJ_LOOKUP_PAGES(fs)) { // referring to an object lookup page, bad object index return SPIFFS_ERR_INDEX_REF_LU; } if (pix > SPIFFS_MAX_PAGES(fs)) { // referring to a bad page return SPIFFS_ERR_INDEX_REF_INVALID; } #if SPIFFS_PAGE_CHECK spiffs_page_header ph; res = _spiffs_rd( fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_READ, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, pix), sizeof(spiffs_page_header), (u8_t *)&ph); SPIFFS_CHECK_RES(res); SPIFFS_VALIDATE_DATA(ph, fd->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG, spix); #endif return res; } #if !SPIFFS_READ_ONLY static s32_t spiffs_page_index_check(spiffs *fs, spiffs_fd *fd, spiffs_page_ix pix, spiffs_span_ix spix) { s32_t res = SPIFFS_OK; if (pix == (spiffs_page_ix) - 1) { // referring to page 0xffff...., bad object index return SPIFFS_ERR_INDEX_FREE; } if (pix % SPIFFS_PAGES_PER_BLOCK(fs) < SPIFFS_OBJ_LOOKUP_PAGES(fs)) { // referring to an object lookup page, bad object index return SPIFFS_ERR_INDEX_LU; } if (pix > SPIFFS_MAX_PAGES(fs)) { // referring to a bad page return SPIFFS_ERR_INDEX_INVALID; } #if SPIFFS_PAGE_CHECK spiffs_page_header ph; res = _spiffs_rd( fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_READ, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, pix), sizeof(spiffs_page_header), (u8_t *)&ph); SPIFFS_CHECK_RES(res); SPIFFS_VALIDATE_OBJIX(ph, fd->obj_id, spix); #endif return res; } #endif // !SPIFFS_READ_ONLY #if !SPIFFS_CACHE s32_t spiffs_phys_rd( spiffs *fs, u32_t addr, u32_t len, u8_t *dst) { return SPIFFS_HAL_READ(fs, addr, len, dst); } s32_t spiffs_phys_wr( spiffs *fs, u32_t addr, u32_t len, u8_t *src) { return SPIFFS_HAL_WRITE(fs, addr, len, src); } #endif #if !SPIFFS_READ_ONLY s32_t spiffs_phys_cpy( spiffs *fs, spiffs_file fh, u32_t dst, u32_t src, u32_t len) { (void)fh; s32_t res; u8_t b[SPIFFS_COPY_BUFFER_STACK]; while (len > 0) { u32_t chunk_size = MIN(SPIFFS_COPY_BUFFER_STACK, len); res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_MOVS, fh, src, chunk_size, b); SPIFFS_CHECK_RES(res); res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_MOVD, fh, dst, chunk_size, b); SPIFFS_CHECK_RES(res); len -= chunk_size; src += chunk_size; dst += chunk_size; } return SPIFFS_OK; } #endif // !SPIFFS_READ_ONLY // Find object lookup entry containing given id with visitor. // Iterate over object lookup pages in each block until a given object id entry is found. // When found, the visitor function is called with block index, entry index and user data. // If visitor returns SPIFFS_VIS_CONTINUE, the search goes on. Otherwise, the search will be // ended and visitor's return code is returned to caller. // If no visitor is given (0) the search returns on first entry with matching object id. // If no match is found in all look up, SPIFFS_VIS_END is returned. // @param fs the file system // @param starting_block the starting block to start search in // @param starting_lu_entry the look up index entry to start search in // @param flags ored combination of SPIFFS_VIS_CHECK_ID, SPIFFS_VIS_CHECK_PH, // SPIFFS_VIS_NO_WRAP // @param obj_id argument object id // @param v visitor callback function // @param user_const_p any const pointer, passed to the callback visitor function // @param user_var_p any pointer, passed to the callback visitor function // @param block_ix reported block index where match was found // @param lu_entry reported look up index where match was found s32_t spiffs_obj_lu_find_entry_visitor( spiffs *fs, spiffs_block_ix starting_block, int starting_lu_entry, u8_t flags, spiffs_obj_id obj_id, spiffs_visitor_f v, const void *user_const_p, void *user_var_p, spiffs_block_ix *block_ix, int *lu_entry) { s32_t res = SPIFFS_OK; s32_t entry_count = fs->block_count * SPIFFS_OBJ_LOOKUP_MAX_ENTRIES(fs); spiffs_block_ix cur_block = starting_block; u32_t cur_block_addr = starting_block * SPIFFS_CFG_LOG_BLOCK_SZ(fs); spiffs_obj_id *obj_lu_buf = (spiffs_obj_id *)fs->lu_work; int cur_entry = starting_lu_entry; int entries_per_page = (SPIFFS_CFG_LOG_PAGE_SZ(fs) / sizeof(spiffs_obj_id)); // wrap initial if (cur_entry > (int)SPIFFS_OBJ_LOOKUP_MAX_ENTRIES(fs) - 1) { cur_entry = 0; cur_block++; cur_block_addr = cur_block * SPIFFS_CFG_LOG_BLOCK_SZ(fs); if (cur_block >= fs->block_count) { if (flags & SPIFFS_VIS_NO_WRAP) { return SPIFFS_VIS_END; } else { // block wrap cur_block = 0; cur_block_addr = 0; } } } // check each block while (res == SPIFFS_OK && entry_count > 0) { int obj_lookup_page = cur_entry / entries_per_page; // check each object lookup page while (res == SPIFFS_OK && obj_lookup_page < (int)SPIFFS_OBJ_LOOKUP_PAGES(fs)) { int entry_offset = obj_lookup_page * entries_per_page; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, 0, cur_block_addr + SPIFFS_PAGE_TO_PADDR(fs, obj_lookup_page), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->lu_work); // check each entry while (res == SPIFFS_OK && cur_entry - entry_offset < entries_per_page && // for non-last obj lookup pages cur_entry < (int)SPIFFS_OBJ_LOOKUP_MAX_ENTRIES(fs)) // for last obj lookup page { if ((flags & SPIFFS_VIS_CHECK_ID) == 0 || obj_lu_buf[cur_entry - entry_offset] == obj_id) { if (block_ix) *block_ix = cur_block; if (lu_entry) *lu_entry = cur_entry; if (v) { res = v( fs, (flags & SPIFFS_VIS_CHECK_PH) ? obj_id : obj_lu_buf[cur_entry - entry_offset], cur_block, cur_entry, user_const_p, user_var_p); if (res == SPIFFS_VIS_COUNTINUE || res == SPIFFS_VIS_COUNTINUE_RELOAD) { if (res == SPIFFS_VIS_COUNTINUE_RELOAD) { res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, 0, cur_block_addr + SPIFFS_PAGE_TO_PADDR(fs, obj_lookup_page), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->lu_work); SPIFFS_CHECK_RES(res); } res = SPIFFS_OK; cur_entry++; entry_count--; continue; } else { return res; } } else { return SPIFFS_OK; } } entry_count--; cur_entry++; } // per entry obj_lookup_page++; } // per object lookup page cur_entry = 0; cur_block++; cur_block_addr += SPIFFS_CFG_LOG_BLOCK_SZ(fs); if (cur_block >= fs->block_count) { if (flags & SPIFFS_VIS_NO_WRAP) { return SPIFFS_VIS_END; } else { // block wrap cur_block = 0; cur_block_addr = 0; } } } // per block SPIFFS_CHECK_RES(res); return SPIFFS_VIS_END; } #if !SPIFFS_READ_ONLY s32_t spiffs_erase_block( spiffs *fs, spiffs_block_ix bix) { s32_t res; u32_t addr = SPIFFS_BLOCK_TO_PADDR(fs, bix); s32_t size = SPIFFS_CFG_LOG_BLOCK_SZ(fs); // here we ignore res, just try erasing the block while (size > 0) { SPIFFS_DBG("erase "_SPIPRIad":"_SPIPRIi"\n", addr, SPIFFS_CFG_PHYS_ERASE_SZ(fs)); SPIFFS_HAL_ERASE(fs, addr, SPIFFS_CFG_PHYS_ERASE_SZ(fs)); addr += SPIFFS_CFG_PHYS_ERASE_SZ(fs); size -= SPIFFS_CFG_PHYS_ERASE_SZ(fs); } fs->free_blocks++; // register erase count for this block res = _spiffs_wr(fs, SPIFFS_OP_C_WRTHRU | SPIFFS_OP_T_OBJ_LU2, 0, SPIFFS_ERASE_COUNT_PADDR(fs, bix), sizeof(spiffs_obj_id), (u8_t *)&fs->max_erase_count); SPIFFS_CHECK_RES(res); #if SPIFFS_USE_MAGIC // finally, write magic spiffs_obj_id magic = SPIFFS_MAGIC(fs, bix); res = _spiffs_wr(fs, SPIFFS_OP_C_WRTHRU | SPIFFS_OP_T_OBJ_LU2, 0, SPIFFS_MAGIC_PADDR(fs, bix), sizeof(spiffs_obj_id), (u8_t *)&magic); SPIFFS_CHECK_RES(res); #endif fs->max_erase_count++; if (fs->max_erase_count == SPIFFS_OBJ_ID_IX_FLAG) { fs->max_erase_count = 0; } return res; } #endif // !SPIFFS_READ_ONLY #if SPIFFS_USE_MAGIC && SPIFFS_USE_MAGIC_LENGTH && SPIFFS_SINGLETON==0 s32_t spiffs_probe( spiffs_config *cfg) { s32_t res; u32_t paddr; spiffs dummy_fs; // create a dummy fs struct just to be able to use macros _SPIFFS_MEMCPY(&dummy_fs.cfg, cfg, sizeof(spiffs_config)); dummy_fs.block_count = 0; // Read three magics, as one block may be in an aborted erase state. // At least two of these must contain magic and be in decreasing order. spiffs_obj_id magic[3]; spiffs_obj_id bix_count[3]; spiffs_block_ix bix; for (bix = 0; bix < 3; bix++) { paddr = SPIFFS_MAGIC_PADDR(&dummy_fs, bix); #if SPIFFS_HAL_CALLBACK_EXTRA // not any proper fs to report here, so callback with null // (cross fingers that no-one gets angry) res = cfg->hal_read_f((void *)0, paddr, sizeof(spiffs_obj_id), (u8_t *)&magic[bix]); #else res = cfg->hal_read_f(paddr, sizeof(spiffs_obj_id), (u8_t *)&magic[bix]); #endif bix_count[bix] = magic[bix] ^ SPIFFS_MAGIC(&dummy_fs, 0); SPIFFS_CHECK_RES(res); } // check that we have sane number of blocks if (bix_count[0] < 3) return SPIFFS_ERR_PROBE_TOO_FEW_BLOCKS; // check that the order is correct, take aborted erases in calculation // first block aborted erase if (magic[0] == (spiffs_obj_id)(-1) && bix_count[1] - bix_count[2] == 1) { return (bix_count[1] + 1) * cfg->log_block_size; } // second block aborted erase if (magic[1] == (spiffs_obj_id)(-1) && bix_count[0] - bix_count[2] == 2) { return bix_count[0] * cfg->log_block_size; } // third block aborted erase if (magic[2] == (spiffs_obj_id)(-1) && bix_count[0] - bix_count[1] == 1) { return bix_count[0] * cfg->log_block_size; } // no block has aborted erase if (bix_count[0] - bix_count[1] == 1 && bix_count[1] - bix_count[2] == 1) { return bix_count[0] * cfg->log_block_size; } return SPIFFS_ERR_PROBE_NOT_A_FS; } #endif // SPIFFS_USE_MAGIC && SPIFFS_USE_MAGIC_LENGTH && SPIFFS_SINGLETON==0 static s32_t spiffs_obj_lu_scan_v( spiffs *fs, spiffs_obj_id obj_id, spiffs_block_ix bix, int ix_entry, const void *user_const_p, void *user_var_p) { (void)bix; (void)user_const_p; (void)user_var_p; if (obj_id == SPIFFS_OBJ_ID_FREE) { if (ix_entry == 0) { fs->free_blocks++; // todo optimize further, return SPIFFS_NEXT_BLOCK } } else if (obj_id == SPIFFS_OBJ_ID_DELETED) { fs->stats_p_deleted++; } else { fs->stats_p_allocated++; } return SPIFFS_VIS_COUNTINUE; } // Scans thru all obj lu and counts free, deleted and used pages // Find the maximum block erase count // Checks magic if enabled s32_t spiffs_obj_lu_scan( spiffs *fs) { s32_t res; spiffs_block_ix bix; int entry; #if SPIFFS_USE_MAGIC spiffs_block_ix unerased_bix = (spiffs_block_ix) - 1; #endif // find out erase count // if enabled, check magic bix = 0; spiffs_obj_id erase_count_final; spiffs_obj_id erase_count_min = SPIFFS_OBJ_ID_FREE; spiffs_obj_id erase_count_max = 0; while (bix < fs->block_count) { #if SPIFFS_USE_MAGIC spiffs_obj_id magic; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_MAGIC_PADDR(fs, bix) , sizeof(spiffs_obj_id), (u8_t *)&magic); SPIFFS_CHECK_RES(res); if (magic != SPIFFS_MAGIC(fs, bix)) { if (unerased_bix == (spiffs_block_ix) - 1) { // allow one unerased block as it might be powered down during an erase unerased_bix = bix; } else { // more than one unerased block, bail out SPIFFS_CHECK_RES(SPIFFS_ERR_NOT_A_FS); } } #endif spiffs_obj_id erase_count; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_ERASE_COUNT_PADDR(fs, bix) , sizeof(spiffs_obj_id), (u8_t *)&erase_count); SPIFFS_CHECK_RES(res); if (erase_count != SPIFFS_OBJ_ID_FREE) { erase_count_min = MIN(erase_count_min, erase_count); erase_count_max = MAX(erase_count_max, erase_count); } bix++; } if (erase_count_min == 0 && erase_count_max == SPIFFS_OBJ_ID_FREE) { // clean system, set counter to zero erase_count_final = 0; } else if (erase_count_max - erase_count_min > (SPIFFS_OBJ_ID_FREE) / 2) { // wrap, take min erase_count_final = erase_count_min + 1; } else { erase_count_final = erase_count_max + 1; } fs->max_erase_count = erase_count_final; #if SPIFFS_USE_MAGIC if (unerased_bix != (spiffs_block_ix) - 1) { // found one unerased block, remedy SPIFFS_DBG("mount: erase block "_SPIPRIbl"\n", bix); #if SPIFFS_READ_ONLY res = SPIFFS_ERR_RO_ABORTED_OPERATION; #else res = spiffs_erase_block(fs, unerased_bix); #endif // SPIFFS_READ_ONLY SPIFFS_CHECK_RES(res); } #endif // count blocks fs->free_blocks = 0; fs->stats_p_allocated = 0; fs->stats_p_deleted = 0; res = spiffs_obj_lu_find_entry_visitor(fs, 0, 0, 0, 0, spiffs_obj_lu_scan_v, 0, 0, &bix, &entry); if (res == SPIFFS_VIS_END) { res = SPIFFS_OK; } SPIFFS_CHECK_RES(res); return res; } #if !SPIFFS_READ_ONLY // Find free object lookup entry // Iterate over object lookup pages in each block until a free object id entry is found s32_t spiffs_obj_lu_find_free( spiffs *fs, spiffs_block_ix starting_block, int starting_lu_entry, spiffs_block_ix *block_ix, int *lu_entry) { s32_t res; if (!fs->cleaning && fs->free_blocks < 2) { res = spiffs_gc_quick(fs, 0); if (res == SPIFFS_ERR_NO_DELETED_BLOCKS) { res = SPIFFS_OK; } SPIFFS_CHECK_RES(res); if (fs->free_blocks < 2) { return SPIFFS_ERR_FULL; } } res = spiffs_obj_lu_find_id(fs, starting_block, starting_lu_entry, SPIFFS_OBJ_ID_FREE, block_ix, lu_entry); if (res == SPIFFS_OK) { fs->free_cursor_block_ix = *block_ix; fs->free_cursor_obj_lu_entry = (*lu_entry) + 1; if (*lu_entry == 0) { fs->free_blocks--; } } if (res == SPIFFS_ERR_FULL) { SPIFFS_DBG("fs full\n"); } return res; } #endif // !SPIFFS_READ_ONLY // Find object lookup entry containing given id // Iterate over object lookup pages in each block until a given object id entry is found s32_t spiffs_obj_lu_find_id( spiffs *fs, spiffs_block_ix starting_block, int starting_lu_entry, spiffs_obj_id obj_id, spiffs_block_ix *block_ix, int *lu_entry) { s32_t res = spiffs_obj_lu_find_entry_visitor( fs, starting_block, starting_lu_entry, SPIFFS_VIS_CHECK_ID, obj_id, 0, 0, 0, block_ix, lu_entry); if (res == SPIFFS_VIS_END) { res = SPIFFS_ERR_NOT_FOUND; } return res; } static s32_t spiffs_obj_lu_find_id_and_span_v( spiffs *fs, spiffs_obj_id obj_id, spiffs_block_ix bix, int ix_entry, const void *user_const_p, void *user_var_p) { s32_t res; spiffs_page_header ph; spiffs_page_ix pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, ix_entry); res = _spiffs_rd(fs, 0, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, SPIFFS_PAGE_TO_PADDR(fs, pix), sizeof(spiffs_page_header), (u8_t *)&ph); SPIFFS_CHECK_RES(res); if (ph.obj_id == obj_id && ph.span_ix == *((spiffs_span_ix *)user_var_p) && (ph.flags & (SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_USED)) == SPIFFS_PH_FLAG_DELET && !((obj_id & SPIFFS_OBJ_ID_IX_FLAG) && (ph.flags & SPIFFS_PH_FLAG_IXDELE) == 0 && ph.span_ix == 0) && (user_const_p == 0 || *((const spiffs_page_ix *)user_const_p) != pix)) { return SPIFFS_OK; } else { return SPIFFS_VIS_COUNTINUE; } } // Find object lookup entry containing given id and span index // Iterate over object lookup pages in each block until a given object id entry is found s32_t spiffs_obj_lu_find_id_and_span( spiffs *fs, spiffs_obj_id obj_id, spiffs_span_ix spix, spiffs_page_ix exclusion_pix, spiffs_page_ix *pix) { s32_t res; spiffs_block_ix bix; int entry; res = spiffs_obj_lu_find_entry_visitor(fs, fs->cursor_block_ix, fs->cursor_obj_lu_entry, SPIFFS_VIS_CHECK_ID, obj_id, spiffs_obj_lu_find_id_and_span_v, exclusion_pix ? &exclusion_pix : 0, &spix, &bix, &entry); if (res == SPIFFS_VIS_END) { res = SPIFFS_ERR_NOT_FOUND; } SPIFFS_CHECK_RES(res); if (pix) { *pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, entry); } fs->cursor_block_ix = bix; fs->cursor_obj_lu_entry = entry; return res; } // Find object lookup entry containing given id and span index in page headers only // Iterate over object lookup pages in each block until a given object id entry is found s32_t spiffs_obj_lu_find_id_and_span_by_phdr( spiffs *fs, spiffs_obj_id obj_id, spiffs_span_ix spix, spiffs_page_ix exclusion_pix, spiffs_page_ix *pix) { s32_t res; spiffs_block_ix bix; int entry; res = spiffs_obj_lu_find_entry_visitor(fs, fs->cursor_block_ix, fs->cursor_obj_lu_entry, SPIFFS_VIS_CHECK_PH, obj_id, spiffs_obj_lu_find_id_and_span_v, exclusion_pix ? &exclusion_pix : 0, &spix, &bix, &entry); if (res == SPIFFS_VIS_END) { res = SPIFFS_ERR_NOT_FOUND; } SPIFFS_CHECK_RES(res); if (pix) { *pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, entry); } fs->cursor_block_ix = bix; fs->cursor_obj_lu_entry = entry; return res; } #if SPIFFS_IX_MAP // update index map of given fd with given object index data static void spiffs_update_ix_map(spiffs *fs, spiffs_fd *fd, spiffs_span_ix objix_spix, spiffs_page_object_ix *objix) { #if SPIFFS_SINGLETON (void)fs; #endif spiffs_ix_map *map = fd->ix_map; spiffs_span_ix map_objix_start_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, map->start_spix); spiffs_span_ix map_objix_end_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, map->end_spix); // check if updated ix is within map range if (objix_spix < map_objix_start_spix || objix_spix > map_objix_end_spix) { return; } // update memory mapped page index buffer to new pages // get range of updated object index map data span indices spiffs_span_ix objix_data_spix_start = SPIFFS_DATA_SPAN_IX_FOR_OBJ_IX_SPAN_IX(fs, objix_spix); spiffs_span_ix objix_data_spix_end = objix_data_spix_start + (objix_spix == 0 ? SPIFFS_OBJ_HDR_IX_LEN(fs) : SPIFFS_OBJ_IX_LEN(fs)); // calc union of object index range and index map range array spiffs_span_ix map_spix = MAX(map->start_spix, objix_data_spix_start); spiffs_span_ix map_spix_end = MIN(map->end_spix + 1, objix_data_spix_end); while (map_spix < map_spix_end) { spiffs_page_ix objix_data_pix; if (objix_spix == 0) { // get data page from object index header page objix_data_pix = ((spiffs_page_ix *)((u8_t *)objix + sizeof(spiffs_page_object_ix_header)))[map_spix]; } else { // get data page from object index page objix_data_pix = ((spiffs_page_ix *)((u8_t *)objix + sizeof(spiffs_page_object_ix)))[SPIFFS_OBJ_IX_ENTRY(fs, map_spix)]; } if (objix_data_pix == (spiffs_page_ix) - 1) { // reached end of object, abort break; } map->map_buf[map_spix - map->start_spix] = objix_data_pix; SPIFFS_DBG("map "_SPIPRIid":"_SPIPRIsp" ("_SPIPRIsp"--"_SPIPRIsp") objix.spix:"_SPIPRIsp" to pix "_SPIPRIpg"\n", fd->obj_id, map_spix - map->start_spix, map->start_spix, map->end_spix, objix->p_hdr.span_ix, objix_data_pix); map_spix++; } } typedef struct { spiffs_fd *fd; u32_t remaining_objix_pages_to_visit; spiffs_span_ix map_objix_start_spix; spiffs_span_ix map_objix_end_spix; } spiffs_ix_map_populate_state; static s32_t spiffs_populate_ix_map_v( spiffs *fs, spiffs_obj_id obj_id, spiffs_block_ix bix, int ix_entry, const void *user_const_p, void *user_var_p) { (void)user_const_p; s32_t res; spiffs_ix_map_populate_state *state = (spiffs_ix_map_populate_state *)user_var_p; spiffs_page_ix pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, ix_entry); // load header to check it spiffs_page_object_ix *objix = (spiffs_page_object_ix *)fs->work; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, pix), sizeof(spiffs_page_object_ix), (u8_t *)objix); SPIFFS_CHECK_RES(res); SPIFFS_VALIDATE_OBJIX(objix->p_hdr, obj_id, objix->p_hdr.span_ix); // check if hdr is ok, and if objix range overlap with ix map range if ((objix->p_hdr.flags & (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_IXDELE)) == (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_IXDELE) && objix->p_hdr.span_ix >= state->map_objix_start_spix && objix->p_hdr.span_ix <= state->map_objix_end_spix) { // ok, load rest of object index res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, pix) + sizeof(spiffs_page_object_ix), SPIFFS_CFG_LOG_PAGE_SZ(fs) - sizeof(spiffs_page_object_ix), (u8_t *)objix + sizeof(spiffs_page_object_ix)); SPIFFS_CHECK_RES(res); spiffs_update_ix_map(fs, state->fd, objix->p_hdr.span_ix, objix); state->remaining_objix_pages_to_visit--; SPIFFS_DBG("map "_SPIPRIid" ("_SPIPRIsp"--"_SPIPRIsp") remaining objix pages "_SPIPRIi"\n", state->fd->obj_id, state->fd->ix_map->start_spix, state->fd->ix_map->end_spix, state->remaining_objix_pages_to_visit); } if (res == SPIFFS_OK) { res = state->remaining_objix_pages_to_visit ? SPIFFS_VIS_COUNTINUE : SPIFFS_VIS_END; } return res; } // populates index map, from vector entry start to vector entry end, inclusive s32_t spiffs_populate_ix_map(spiffs *fs, spiffs_fd *fd, u32_t vec_entry_start, u32_t vec_entry_end) { s32_t res; spiffs_ix_map *map = fd->ix_map; spiffs_ix_map_populate_state state; vec_entry_start = MIN((u32_t)(map->end_spix - map->start_spix), vec_entry_start); vec_entry_end = MAX((u32_t)(map->end_spix - map->start_spix), vec_entry_end); if (vec_entry_start > vec_entry_end) { return SPIFFS_ERR_IX_MAP_BAD_RANGE; } state.map_objix_start_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, map->start_spix + vec_entry_start); state.map_objix_end_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, map->start_spix + vec_entry_end); state.remaining_objix_pages_to_visit = state.map_objix_end_spix - state.map_objix_start_spix + 1; state.fd = fd; res = spiffs_obj_lu_find_entry_visitor( fs, SPIFFS_BLOCK_FOR_PAGE(fs, fd->objix_hdr_pix), SPIFFS_OBJ_LOOKUP_ENTRY_FOR_PAGE(fs, fd->objix_hdr_pix), SPIFFS_VIS_CHECK_ID, fd->obj_id | SPIFFS_OBJ_ID_IX_FLAG, spiffs_populate_ix_map_v, 0, &state, 0, 0); if (res == SPIFFS_VIS_END) { res = SPIFFS_OK; } return res; } #endif #if !SPIFFS_READ_ONLY // Allocates a free defined page with given obj_id // Occupies object lookup entry and page // data may be NULL; where only page header is stored, len and page_offs is ignored s32_t spiffs_page_allocate_data( spiffs *fs, spiffs_obj_id obj_id, spiffs_page_header *ph, u8_t *data, u32_t len, u32_t page_offs, u8_t finalize, spiffs_page_ix *pix) { s32_t res = SPIFFS_OK; spiffs_block_ix bix; int entry; // find free entry res = spiffs_obj_lu_find_free(fs, fs->free_cursor_block_ix, fs->free_cursor_obj_lu_entry, &bix, &entry); SPIFFS_CHECK_RES(res); // occupy page in object lookup res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_UPDT, 0, SPIFFS_BLOCK_TO_PADDR(fs, bix) + entry * sizeof(spiffs_obj_id), sizeof(spiffs_obj_id), (u8_t *)&obj_id); SPIFFS_CHECK_RES(res); fs->stats_p_allocated++; // write page header ph->flags &= ~SPIFFS_PH_FLAG_USED; res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, 0, SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, bix, entry), sizeof(spiffs_page_header), (u8_t *)ph); SPIFFS_CHECK_RES(res); // write page data if (data) { res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, 0, SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, bix, entry) + sizeof(spiffs_page_header) + page_offs, len, data); SPIFFS_CHECK_RES(res); } // finalize header if necessary if (finalize && (ph->flags & SPIFFS_PH_FLAG_FINAL)) { ph->flags &= ~SPIFFS_PH_FLAG_FINAL; res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, 0, SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, bix, entry) + offsetof(spiffs_page_header, flags), sizeof(u8_t), (u8_t *)&ph->flags); SPIFFS_CHECK_RES(res); } // return written page if (pix) { *pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, entry); } return res; } #endif // !SPIFFS_READ_ONLY #if !SPIFFS_READ_ONLY // Moves a page from src to a free page and finalizes it. Updates page index. Page data is given in param page. // If page data is null, provided header is used for metainfo and page data is physically copied. s32_t spiffs_page_move( spiffs *fs, spiffs_file fh, u8_t *page_data, spiffs_obj_id obj_id, spiffs_page_header *page_hdr, spiffs_page_ix src_pix, spiffs_page_ix *dst_pix) { s32_t res; u8_t was_final = 0; spiffs_page_header *p_hdr; spiffs_block_ix bix; int entry; spiffs_page_ix free_pix; // find free entry res = spiffs_obj_lu_find_free(fs, fs->free_cursor_block_ix, fs->free_cursor_obj_lu_entry, &bix, &entry); SPIFFS_CHECK_RES(res); free_pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, entry); if (dst_pix) *dst_pix = free_pix; p_hdr = page_data ? (spiffs_page_header *)page_data : page_hdr; if (page_data) { // got page data was_final = (p_hdr->flags & SPIFFS_PH_FLAG_FINAL) == 0; // write unfinalized page p_hdr->flags |= SPIFFS_PH_FLAG_FINAL; p_hdr->flags &= ~SPIFFS_PH_FLAG_USED; res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, 0, SPIFFS_PAGE_TO_PADDR(fs, free_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), page_data); } else { // copy page data res = spiffs_phys_cpy(fs, fh, SPIFFS_PAGE_TO_PADDR(fs, free_pix), SPIFFS_PAGE_TO_PADDR(fs, src_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs)); } SPIFFS_CHECK_RES(res); // mark entry in destination object lookup res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_UPDT, 0, SPIFFS_BLOCK_TO_PADDR(fs, SPIFFS_BLOCK_FOR_PAGE(fs, free_pix)) + SPIFFS_OBJ_LOOKUP_ENTRY_FOR_PAGE(fs, free_pix) * sizeof(spiffs_page_ix), sizeof(spiffs_obj_id), (u8_t *)&obj_id); SPIFFS_CHECK_RES(res); fs->stats_p_allocated++; if (was_final) { // mark finalized in destination page p_hdr->flags &= ~(SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_USED); res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, fh, SPIFFS_PAGE_TO_PADDR(fs, free_pix) + offsetof(spiffs_page_header, flags), sizeof(u8_t), (u8_t *)&p_hdr->flags); SPIFFS_CHECK_RES(res); } // mark source deleted res = spiffs_page_delete(fs, src_pix); return res; } #endif // !SPIFFS_READ_ONLY #if !SPIFFS_READ_ONLY // Deletes a page and removes it from object lookup. s32_t spiffs_page_delete( spiffs *fs, spiffs_page_ix pix) { s32_t res; // mark deleted entry in source object lookup spiffs_obj_id d_obj_id = SPIFFS_OBJ_ID_DELETED; res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_DELE, 0, SPIFFS_BLOCK_TO_PADDR(fs, SPIFFS_BLOCK_FOR_PAGE(fs, pix)) + SPIFFS_OBJ_LOOKUP_ENTRY_FOR_PAGE(fs, pix) * sizeof(spiffs_page_ix), sizeof(spiffs_obj_id), (u8_t *)&d_obj_id); SPIFFS_CHECK_RES(res); fs->stats_p_deleted++; fs->stats_p_allocated--; // mark deleted in source page u8_t flags = 0xff; #if SPIFFS_NO_BLIND_WRITES res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, pix) + offsetof(spiffs_page_header, flags), sizeof(flags), &flags); SPIFFS_CHECK_RES(res); #endif flags &= ~(SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_USED); res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_DELE, 0, SPIFFS_PAGE_TO_PADDR(fs, pix) + offsetof(spiffs_page_header, flags), sizeof(flags), &flags); return res; } #endif // !SPIFFS_READ_ONLY #if !SPIFFS_READ_ONLY // Create an object index header page with empty index and undefined length s32_t spiffs_object_create( spiffs *fs, spiffs_obj_id obj_id, const u8_t name[], const u8_t meta[], spiffs_obj_type type, spiffs_page_ix *objix_hdr_pix) { s32_t res = SPIFFS_OK; spiffs_block_ix bix; spiffs_page_object_ix_header oix_hdr; int entry; res = spiffs_gc_check(fs, SPIFFS_DATA_PAGE_SIZE(fs)); SPIFFS_CHECK_RES(res); obj_id |= SPIFFS_OBJ_ID_IX_FLAG; // find free entry res = spiffs_obj_lu_find_free(fs, fs->free_cursor_block_ix, fs->free_cursor_obj_lu_entry, &bix, &entry); SPIFFS_CHECK_RES(res); SPIFFS_DBG("create: found free page @ "_SPIPRIpg" bix:"_SPIPRIbl" entry:"_SPIPRIsp"\n", (spiffs_page_ix)SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, entry), bix, entry); // occupy page in object lookup res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_UPDT, 0, SPIFFS_BLOCK_TO_PADDR(fs, bix) + entry * sizeof(spiffs_obj_id), sizeof(spiffs_obj_id), (u8_t *)&obj_id); SPIFFS_CHECK_RES(res); fs->stats_p_allocated++; // write empty object index page oix_hdr.p_hdr.obj_id = obj_id; oix_hdr.p_hdr.span_ix = 0; oix_hdr.p_hdr.flags = 0xff & ~(SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_USED); oix_hdr.type = type; oix_hdr.size = SPIFFS_UNDEFINED_LEN; // keep ones so we can update later without wasting this page strncpy((char *)oix_hdr.name, (const char *)name, SPIFFS_OBJ_NAME_LEN); #if SPIFFS_OBJ_META_LEN if (meta) { _SPIFFS_MEMCPY(oix_hdr.meta, meta, SPIFFS_OBJ_META_LEN); } else { memset(oix_hdr.meta, 0xff, SPIFFS_OBJ_META_LEN); } #else (void) meta; #endif // update page res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, 0, SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, bix, entry), sizeof(spiffs_page_object_ix_header), (u8_t *)&oix_hdr); SPIFFS_CHECK_RES(res); spiffs_cb_object_event(fs, (spiffs_page_object_ix *)&oix_hdr, SPIFFS_EV_IX_NEW, obj_id, 0, SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, entry), SPIFFS_UNDEFINED_LEN); if (objix_hdr_pix) { *objix_hdr_pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, entry); } return res; } #endif // !SPIFFS_READ_ONLY #if !SPIFFS_READ_ONLY // update object index header with any combination of name/size/index // new_objix_hdr_data may be null, if so the object index header page is loaded // name may be null, if so name is not changed // size may be null, if so size is not changed s32_t spiffs_object_update_index_hdr( spiffs *fs, spiffs_fd *fd, spiffs_obj_id obj_id, spiffs_page_ix objix_hdr_pix, u8_t *new_objix_hdr_data, const u8_t name[], const u8_t meta[], u32_t size, spiffs_page_ix *new_pix) { s32_t res = SPIFFS_OK; spiffs_page_object_ix_header *objix_hdr; spiffs_page_ix new_objix_hdr_pix; obj_id |= SPIFFS_OBJ_ID_IX_FLAG; if (new_objix_hdr_data) { // object index header page already given to us, no need to load it objix_hdr = (spiffs_page_object_ix_header *)new_objix_hdr_data; } else { // read object index header page res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_READ, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, objix_hdr_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->work); SPIFFS_CHECK_RES(res); objix_hdr = (spiffs_page_object_ix_header *)fs->work; } SPIFFS_VALIDATE_OBJIX(objix_hdr->p_hdr, obj_id, 0); // change name if (name) { strncpy((char *)objix_hdr->name, (const char *)name, SPIFFS_OBJ_NAME_LEN); } #if SPIFFS_OBJ_META_LEN if (meta) { _SPIFFS_MEMCPY(objix_hdr->meta, meta, SPIFFS_OBJ_META_LEN); } #else (void) meta; #endif if (size) { objix_hdr->size = size; } // move and update page res = spiffs_page_move(fs, fd == 0 ? 0 : fd->file_nbr, (u8_t *)objix_hdr, obj_id, 0, objix_hdr_pix, &new_objix_hdr_pix); if (res == SPIFFS_OK) { if (new_pix) { *new_pix = new_objix_hdr_pix; } // callback on object index update spiffs_cb_object_event(fs, (spiffs_page_object_ix *)objix_hdr, new_objix_hdr_data ? SPIFFS_EV_IX_UPD : SPIFFS_EV_IX_UPD_HDR, obj_id, objix_hdr->p_hdr.span_ix, new_objix_hdr_pix, objix_hdr->size); if (fd) fd->objix_hdr_pix = new_objix_hdr_pix; // if this is not in the registered cluster } return res; } #endif // !SPIFFS_READ_ONLY void spiffs_cb_object_event( spiffs *fs, spiffs_page_object_ix *objix, int ev, spiffs_obj_id obj_id_raw, spiffs_span_ix spix, spiffs_page_ix new_pix, u32_t new_size) { #if SPIFFS_IX_MAP == 0 (void)objix; #endif // update index caches in all file descriptors spiffs_obj_id obj_id = obj_id_raw & ~SPIFFS_OBJ_ID_IX_FLAG; u32_t i; spiffs_fd *fds = (spiffs_fd *)fs->fd_space; SPIFFS_DBG(" CALLBACK %s obj_id:"_SPIPRIid" spix:"_SPIPRIsp" npix:"_SPIPRIpg" nsz:"_SPIPRIi"\n", (const char *[]) {"UPD", "NEW", "DEL", "MOV", "HUP", "???" }[MIN(ev, 5)], obj_id_raw, spix, new_pix, new_size); for (i = 0; i < fs->fd_count; i++) { spiffs_fd *cur_fd = &fds[i]; if ((cur_fd->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG) != obj_id) continue; // fd not related to updated file #if !SPIFFS_TEMPORAL_FD_CACHE if (cur_fd->file_nbr == 0) continue; // fd closed #endif if (spix == 0) // object index header update { if (ev != SPIFFS_EV_IX_DEL) { #if SPIFFS_TEMPORAL_FD_CACHE if (cur_fd->score == 0) continue; // never used fd #endif SPIFFS_DBG(" callback: setting fd "_SPIPRIfd":"_SPIPRIid"(fdoffs:"_SPIPRIi" offs:"_SPIPRIi") objix_hdr_pix to "_SPIPRIpg", size:"_SPIPRIi"\n", SPIFFS_FH_OFFS(fs, cur_fd->file_nbr), cur_fd->obj_id, cur_fd->fdoffset, cur_fd->offset, new_pix, new_size); cur_fd->objix_hdr_pix = new_pix; if (new_size != 0) { // update size and offsets for fds to this file cur_fd->size = new_size; u32_t act_new_size = new_size == SPIFFS_UNDEFINED_LEN ? 0 : new_size; #if SPIFFS_CACHE_WR if (act_new_size > 0 && cur_fd->cache_page) { act_new_size = MAX(act_new_size, cur_fd->cache_page->offset + cur_fd->cache_page->size); } #endif if (cur_fd->offset > act_new_size) { cur_fd->offset = act_new_size; } if (cur_fd->fdoffset > act_new_size) { cur_fd->fdoffset = act_new_size; } #if SPIFFS_CACHE_WR if (cur_fd->cache_page && cur_fd->cache_page->offset > act_new_size + 1) { SPIFFS_CACHE_DBG("CACHE_DROP: file trunced, dropping cache page "_SPIPRIi", no writeback\n", cur_fd->cache_page->ix); spiffs_cache_fd_release(fs, cur_fd->cache_page); } #endif } } else { // removing file #if SPIFFS_CACHE_WR if (cur_fd->file_nbr && cur_fd->cache_page) { SPIFFS_CACHE_DBG("CACHE_DROP: file deleted, dropping cache page "_SPIPRIi", no writeback\n", cur_fd->cache_page->ix); spiffs_cache_fd_release(fs, cur_fd->cache_page); } #endif SPIFFS_DBG(" callback: release fd "_SPIPRIfd":"_SPIPRIid" span:"_SPIPRIsp" objix_pix to "_SPIPRIpg"\n", SPIFFS_FH_OFFS(fs, cur_fd->file_nbr), cur_fd->obj_id, spix, new_pix); cur_fd->file_nbr = 0; cur_fd->obj_id = SPIFFS_OBJ_ID_DELETED; } } // object index header update if (cur_fd->cursor_objix_spix == spix) { if (ev != SPIFFS_EV_IX_DEL) { SPIFFS_DBG(" callback: setting fd "_SPIPRIfd":"_SPIPRIid" span:"_SPIPRIsp" objix_pix to "_SPIPRIpg"\n", SPIFFS_FH_OFFS(fs, cur_fd->file_nbr), cur_fd->obj_id, spix, new_pix); cur_fd->cursor_objix_pix = new_pix; } else { cur_fd->cursor_objix_pix = 0; } } } // fd update loop #if SPIFFS_IX_MAP // update index maps if (ev == SPIFFS_EV_IX_UPD || ev == SPIFFS_EV_IX_NEW) { for (i = 0; i < fs->fd_count; i++) { spiffs_fd *cur_fd = &fds[i]; // check fd opened, having ix map, match obj id if (cur_fd->file_nbr == 0 || cur_fd->ix_map == 0 || (cur_fd->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG) != obj_id) continue; SPIFFS_DBG(" callback: map ix update fd "_SPIPRIfd":"_SPIPRIid" span:"_SPIPRIsp"\n", SPIFFS_FH_OFFS(fs, cur_fd->file_nbr), cur_fd->obj_id, spix); spiffs_update_ix_map(fs, cur_fd, spix, objix); } } #endif // callback to user if object index header if (fs->file_cb_f && spix == 0 && (obj_id_raw & SPIFFS_OBJ_ID_IX_FLAG)) { spiffs_fileop_type op; if (ev == SPIFFS_EV_IX_NEW) { op = SPIFFS_CB_CREATED; } else if (ev == SPIFFS_EV_IX_UPD || ev == SPIFFS_EV_IX_MOV || ev == SPIFFS_EV_IX_UPD_HDR) { op = SPIFFS_CB_UPDATED; } else if (ev == SPIFFS_EV_IX_DEL) { op = SPIFFS_CB_DELETED; } else { SPIFFS_DBG(" callback: WARNING unknown callback event "_SPIPRIi"\n", ev); return; // bail out } fs->file_cb_f(fs, op, obj_id, new_pix); } } // Open object by id s32_t spiffs_object_open_by_id( spiffs *fs, spiffs_obj_id obj_id, spiffs_fd *fd, spiffs_flags flags, spiffs_mode mode) { s32_t res = SPIFFS_OK; spiffs_page_ix pix; res = spiffs_obj_lu_find_id_and_span(fs, obj_id | SPIFFS_OBJ_ID_IX_FLAG, 0, 0, &pix); SPIFFS_CHECK_RES(res); res = spiffs_object_open_by_page(fs, pix, fd, flags, mode); return res; } // Open object by page index s32_t spiffs_object_open_by_page( spiffs *fs, spiffs_page_ix pix, spiffs_fd *fd, spiffs_flags flags, spiffs_mode mode) { (void)mode; s32_t res = SPIFFS_OK; spiffs_page_object_ix_header oix_hdr; spiffs_obj_id obj_id; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_READ, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, pix), sizeof(spiffs_page_object_ix_header), (u8_t *)&oix_hdr); SPIFFS_CHECK_RES(res); spiffs_block_ix bix = SPIFFS_BLOCK_FOR_PAGE(fs, pix); int entry = SPIFFS_OBJ_LOOKUP_ENTRY_FOR_PAGE(fs, pix); res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU | SPIFFS_OP_C_READ, 0, SPIFFS_BLOCK_TO_PADDR(fs, bix) + entry * sizeof(spiffs_obj_id), sizeof(spiffs_obj_id), (u8_t *)&obj_id); fd->fs = fs; fd->objix_hdr_pix = pix; fd->size = oix_hdr.size; fd->offset = 0; fd->cursor_objix_pix = pix; fd->cursor_objix_spix = 0; fd->obj_id = obj_id; fd->flags = flags; SPIFFS_VALIDATE_OBJIX(oix_hdr.p_hdr, fd->obj_id, 0); SPIFFS_DBG("open: fd "_SPIPRIfd" is obj id "_SPIPRIid"\n", SPIFFS_FH_OFFS(fs, fd->file_nbr), fd->obj_id); return res; } #if !SPIFFS_READ_ONLY // Append to object // keep current object index (header) page in fs->work buffer s32_t spiffs_object_append(spiffs_fd *fd, u32_t offset, u8_t *data, u32_t len) { spiffs *fs = fd->fs; s32_t res = SPIFFS_OK; u32_t written = 0; SPIFFS_DBG("append: "_SPIPRIi" bytes @ offs "_SPIPRIi" of size "_SPIPRIi"\n", len, offset, fd->size); if (offset > fd->size) { SPIFFS_DBG("append: offset reversed to size\n"); offset = fd->size; } res = spiffs_gc_check(fs, len + SPIFFS_DATA_PAGE_SIZE(fs)); // add an extra page of data worth for meta if (res != SPIFFS_OK) { SPIFFS_DBG("append: gc check fail "_SPIPRIi"\n", res); } SPIFFS_CHECK_RES(res); spiffs_page_object_ix_header *objix_hdr = (spiffs_page_object_ix_header *)fs->work; spiffs_page_object_ix *objix = (spiffs_page_object_ix *)fs->work; spiffs_page_header p_hdr; spiffs_span_ix cur_objix_spix = 0; spiffs_span_ix prev_objix_spix = (spiffs_span_ix) - 1; spiffs_page_ix cur_objix_pix = fd->objix_hdr_pix; spiffs_page_ix new_objix_hdr_page; spiffs_span_ix data_spix = offset / SPIFFS_DATA_PAGE_SIZE(fs); spiffs_page_ix data_page; u32_t page_offs = offset % SPIFFS_DATA_PAGE_SIZE(fs); // write all data while (res == SPIFFS_OK && written < len) { // calculate object index page span index cur_objix_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, data_spix); // handle storing and loading of object indices if (cur_objix_spix != prev_objix_spix) { // new object index page // within this clause we return directly if something fails, object index mess-up if (written > 0) { // store previous object index page, unless first pass SPIFFS_DBG("append: "_SPIPRIid" store objix "_SPIPRIpg":"_SPIPRIsp", written "_SPIPRIi"\n", fd->obj_id, cur_objix_pix, prev_objix_spix, written); if (prev_objix_spix == 0) { // this is an update to object index header page objix_hdr->size = offset + written; if (offset == 0) { // was an empty object, update same page (size was 0xffffffff) res = spiffs_page_index_check(fs, fd, cur_objix_pix, 0); SPIFFS_CHECK_RES(res); res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_UPDT, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, cur_objix_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->work); SPIFFS_CHECK_RES(res); } else { // was a nonempty object, update to new page res = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, fd->objix_hdr_pix, fs->work, 0, 0, offset + written, &new_objix_hdr_page); SPIFFS_CHECK_RES(res); SPIFFS_DBG("append: "_SPIPRIid" store new objix_hdr, "_SPIPRIpg":"_SPIPRIsp", written "_SPIPRIi"\n", fd->obj_id, new_objix_hdr_page, 0, written); } } else { // this is an update to an object index page res = spiffs_page_index_check(fs, fd, cur_objix_pix, prev_objix_spix); SPIFFS_CHECK_RES(res); res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_UPDT, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, cur_objix_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->work); SPIFFS_CHECK_RES(res); spiffs_cb_object_event(fs, (spiffs_page_object_ix *)fs->work, SPIFFS_EV_IX_UPD, fd->obj_id, objix->p_hdr.span_ix, cur_objix_pix, 0); // update length in object index header page res = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, fd->objix_hdr_pix, 0, 0, 0, offset + written, &new_objix_hdr_page); SPIFFS_CHECK_RES(res); SPIFFS_DBG("append: "_SPIPRIid" store new size I "_SPIPRIi" in objix_hdr, "_SPIPRIpg":"_SPIPRIsp", written "_SPIPRIi"\n", fd->obj_id, offset + written, new_objix_hdr_page, 0, written); } fd->size = offset + written; fd->offset = offset + written; } // create or load new object index page if (cur_objix_spix == 0) { // load object index header page, must always exist SPIFFS_DBG("append: "_SPIPRIid" load objixhdr page "_SPIPRIpg":"_SPIPRIsp"\n", fd->obj_id, cur_objix_pix, cur_objix_spix); res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_READ, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, cur_objix_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->work); SPIFFS_CHECK_RES(res); SPIFFS_VALIDATE_OBJIX(objix_hdr->p_hdr, fd->obj_id, cur_objix_spix); } else { spiffs_span_ix len_objix_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, (fd->size - 1) / SPIFFS_DATA_PAGE_SIZE(fs)); // on subsequent passes, create a new object index page if (written > 0 || cur_objix_spix > len_objix_spix) { p_hdr.obj_id = fd->obj_id | SPIFFS_OBJ_ID_IX_FLAG; p_hdr.span_ix = cur_objix_spix; p_hdr.flags = 0xff & ~(SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_INDEX); res = spiffs_page_allocate_data(fs, fd->obj_id | SPIFFS_OBJ_ID_IX_FLAG, &p_hdr, 0, 0, 0, 1, &cur_objix_pix); SPIFFS_CHECK_RES(res); // quick "load" of new object index page memset(fs->work, 0xff, SPIFFS_CFG_LOG_PAGE_SZ(fs)); _SPIFFS_MEMCPY(fs->work, &p_hdr, sizeof(spiffs_page_header)); spiffs_cb_object_event(fs, (spiffs_page_object_ix *)fs->work, SPIFFS_EV_IX_NEW, fd->obj_id, cur_objix_spix, cur_objix_pix, 0); SPIFFS_DBG("append: "_SPIPRIid" create objix page, "_SPIPRIpg":"_SPIPRIsp", written "_SPIPRIi"\n", fd->obj_id , cur_objix_pix, cur_objix_spix, written); } else { // on first pass, we load existing object index page spiffs_page_ix pix; SPIFFS_DBG("append: "_SPIPRIid" find objix span_ix:"_SPIPRIsp"\n", fd->obj_id, cur_objix_spix); if (fd->cursor_objix_spix == cur_objix_spix) { pix = fd->cursor_objix_pix; } else { res = spiffs_obj_lu_find_id_and_span(fs, fd->obj_id | SPIFFS_OBJ_ID_IX_FLAG, cur_objix_spix, 0, &pix); SPIFFS_CHECK_RES(res); } SPIFFS_DBG("append: "_SPIPRIid" found object index at page "_SPIPRIpg" [fd size "_SPIPRIi"]\n", fd->obj_id, pix, fd->size); res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_READ, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->work); SPIFFS_CHECK_RES(res); SPIFFS_VALIDATE_OBJIX(objix_hdr->p_hdr, fd->obj_id, cur_objix_spix); cur_objix_pix = pix; } fd->cursor_objix_pix = cur_objix_pix; fd->cursor_objix_spix = cur_objix_spix; fd->offset = offset + written; fd->size = offset + written; } prev_objix_spix = cur_objix_spix; } // write data u32_t to_write = MIN(len - written, SPIFFS_DATA_PAGE_SIZE(fs) - page_offs); if (page_offs == 0) { // at beginning of a page, allocate and write a new page of data p_hdr.obj_id = fd->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG; p_hdr.span_ix = data_spix; p_hdr.flags = 0xff & ~(SPIFFS_PH_FLAG_FINAL); // finalize immediately res = spiffs_page_allocate_data(fs, fd->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG, &p_hdr, &data[written], to_write, page_offs, 1, &data_page); SPIFFS_DBG("append: "_SPIPRIid" store new data page, "_SPIPRIpg":"_SPIPRIsp" offset:"_SPIPRIi", len "_SPIPRIi", written "_SPIPRIi"\n", fd->obj_id, data_page, data_spix, page_offs, to_write, written); } else { // append to existing page, fill out free data in existing page if (cur_objix_spix == 0) { // get data page from object index header page data_page = ((spiffs_page_ix *)((u8_t *)objix_hdr + sizeof(spiffs_page_object_ix_header)))[data_spix]; } else { // get data page from object index page data_page = ((spiffs_page_ix *)((u8_t *)objix + sizeof(spiffs_page_object_ix)))[SPIFFS_OBJ_IX_ENTRY(fs, data_spix)]; } res = spiffs_page_data_check(fs, fd, data_page, data_spix); SPIFFS_CHECK_RES(res); res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, data_page) + sizeof(spiffs_page_header) + page_offs, to_write, &data[written]); SPIFFS_DBG("append: "_SPIPRIid" store to existing data page, "_SPIPRIpg":"_SPIPRIsp" offset:"_SPIPRIi", len "_SPIPRIi", written "_SPIPRIi"\n", fd->obj_id , data_page, data_spix, page_offs, to_write, written); } if (res != SPIFFS_OK) break; // update memory representation of object index page with new data page if (cur_objix_spix == 0) { // update object index header page ((spiffs_page_ix *)((u8_t *)objix_hdr + sizeof(spiffs_page_object_ix_header)))[data_spix] = data_page; SPIFFS_DBG("append: "_SPIPRIid" wrote page "_SPIPRIpg" to objix_hdr entry "_SPIPRIsp" in mem\n", fd->obj_id , data_page, data_spix); objix_hdr->size = offset + written; } else { // update object index page ((spiffs_page_ix *)((u8_t *)objix + sizeof(spiffs_page_object_ix)))[SPIFFS_OBJ_IX_ENTRY(fs, data_spix)] = data_page; SPIFFS_DBG("append: "_SPIPRIid" wrote page "_SPIPRIpg" to objix entry "_SPIPRIsp" in mem\n", fd->obj_id , data_page, (spiffs_span_ix)SPIFFS_OBJ_IX_ENTRY(fs, data_spix)); } // update internals page_offs = 0; data_spix++; written += to_write; } // while all data fd->size = offset + written; fd->offset = offset + written; fd->cursor_objix_pix = cur_objix_pix; fd->cursor_objix_spix = cur_objix_spix; // finalize updated object indices s32_t res2 = SPIFFS_OK; if (cur_objix_spix != 0) { // wrote beyond object index header page // write last modified object index page, unless object header index page SPIFFS_DBG("append: "_SPIPRIid" store objix page, "_SPIPRIpg":"_SPIPRIsp", written "_SPIPRIi"\n", fd->obj_id, cur_objix_pix, cur_objix_spix, written); res2 = spiffs_page_index_check(fs, fd, cur_objix_pix, cur_objix_spix); SPIFFS_CHECK_RES(res2); res2 = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_UPDT, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, cur_objix_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->work); SPIFFS_CHECK_RES(res2); spiffs_cb_object_event(fs, (spiffs_page_object_ix *)fs->work, SPIFFS_EV_IX_UPD, fd->obj_id, objix->p_hdr.span_ix, cur_objix_pix, 0); // update size in object header index page res2 = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, fd->objix_hdr_pix, 0, 0, 0, offset + written, &new_objix_hdr_page); SPIFFS_DBG("append: "_SPIPRIid" store new size II "_SPIPRIi" in objix_hdr, "_SPIPRIpg":"_SPIPRIsp", written "_SPIPRIi", res "_SPIPRIi"\n", fd->obj_id , offset + written, new_objix_hdr_page, 0, written, res2); SPIFFS_CHECK_RES(res2); } else { // wrote within object index header page if (offset == 0) { // wrote to empty object - simply update size and write whole page objix_hdr->size = offset + written; SPIFFS_DBG("append: "_SPIPRIid" store fresh objix_hdr page, "_SPIPRIpg":"_SPIPRIsp", written "_SPIPRIi"\n", fd->obj_id , cur_objix_pix, cur_objix_spix, written); res2 = spiffs_page_index_check(fs, fd, cur_objix_pix, cur_objix_spix); SPIFFS_CHECK_RES(res2); res2 = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_UPDT, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, cur_objix_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->work); SPIFFS_CHECK_RES(res2); // callback on object index update spiffs_cb_object_event(fs, (spiffs_page_object_ix *)fs->work, SPIFFS_EV_IX_UPD_HDR, fd->obj_id, objix_hdr->p_hdr.span_ix, cur_objix_pix, objix_hdr->size); } else { // modifying object index header page, update size and make new copy res2 = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, fd->objix_hdr_pix, fs->work, 0, 0, offset + written, &new_objix_hdr_page); SPIFFS_DBG("append: "_SPIPRIid" store modified objix_hdr page, "_SPIPRIpg":"_SPIPRIsp", written "_SPIPRIi"\n", fd->obj_id , new_objix_hdr_page, 0, written); SPIFFS_CHECK_RES(res2); } } return res; } // spiffs_object_append #endif // !SPIFFS_READ_ONLY #if !SPIFFS_READ_ONLY // Modify object // keep current object index (header) page in fs->work buffer s32_t spiffs_object_modify(spiffs_fd *fd, u32_t offset, u8_t *data, u32_t len) { spiffs *fs = fd->fs; s32_t res = SPIFFS_OK; u32_t written = 0; res = spiffs_gc_check(fs, len + SPIFFS_DATA_PAGE_SIZE(fs)); SPIFFS_CHECK_RES(res); spiffs_page_object_ix_header *objix_hdr = (spiffs_page_object_ix_header *)fs->work; spiffs_page_object_ix *objix = (spiffs_page_object_ix *)fs->work; spiffs_page_header p_hdr; spiffs_span_ix cur_objix_spix = 0; spiffs_span_ix prev_objix_spix = (spiffs_span_ix) - 1; spiffs_page_ix cur_objix_pix = fd->objix_hdr_pix; spiffs_page_ix new_objix_hdr_pix; spiffs_span_ix data_spix = offset / SPIFFS_DATA_PAGE_SIZE(fs); spiffs_page_ix data_pix; u32_t page_offs = offset % SPIFFS_DATA_PAGE_SIZE(fs); // write all data while (res == SPIFFS_OK && written < len) { // calculate object index page span index cur_objix_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, data_spix); // handle storing and loading of object indices if (cur_objix_spix != prev_objix_spix) { // new object index page // within this clause we return directly if something fails, object index mess-up if (written > 0) { // store previous object index (header) page, unless first pass if (prev_objix_spix == 0) { // store previous object index header page res = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, fd->objix_hdr_pix, fs->work, 0, 0, 0, &new_objix_hdr_pix); SPIFFS_DBG("modify: store modified objix_hdr page, "_SPIPRIpg":"_SPIPRIsp", written "_SPIPRIi"\n", new_objix_hdr_pix, 0, written); SPIFFS_CHECK_RES(res); } else { // store new version of previous object index page spiffs_page_ix new_objix_pix; res = spiffs_page_index_check(fs, fd, cur_objix_pix, prev_objix_spix); SPIFFS_CHECK_RES(res); res = spiffs_page_move(fs, fd->file_nbr, (u8_t *)objix, fd->obj_id, 0, cur_objix_pix, &new_objix_pix); SPIFFS_DBG("modify: store previous modified objix page, "_SPIPRIid":"_SPIPRIsp", written "_SPIPRIi"\n", new_objix_pix, objix->p_hdr.span_ix, written); SPIFFS_CHECK_RES(res); spiffs_cb_object_event(fs, (spiffs_page_object_ix *)objix, SPIFFS_EV_IX_UPD, fd->obj_id, objix->p_hdr.span_ix, new_objix_pix, 0); } } // load next object index page if (cur_objix_spix == 0) { // load object index header page, must exist SPIFFS_DBG("modify: load objixhdr page "_SPIPRIpg":"_SPIPRIsp"\n", cur_objix_pix, cur_objix_spix); res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_READ, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, cur_objix_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->work); SPIFFS_CHECK_RES(res); SPIFFS_VALIDATE_OBJIX(objix_hdr->p_hdr, fd->obj_id, cur_objix_spix); } else { // load existing object index page on first pass spiffs_page_ix pix; SPIFFS_DBG("modify: find objix span_ix:"_SPIPRIsp"\n", cur_objix_spix); if (fd->cursor_objix_spix == cur_objix_spix) { pix = fd->cursor_objix_pix; } else { res = spiffs_obj_lu_find_id_and_span(fs, fd->obj_id | SPIFFS_OBJ_ID_IX_FLAG, cur_objix_spix, 0, &pix); SPIFFS_CHECK_RES(res); } SPIFFS_DBG("modify: found object index at page "_SPIPRIpg"\n", pix); res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_READ, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->work); SPIFFS_CHECK_RES(res); SPIFFS_VALIDATE_OBJIX(objix_hdr->p_hdr, fd->obj_id, cur_objix_spix); cur_objix_pix = pix; } fd->cursor_objix_pix = cur_objix_pix; fd->cursor_objix_spix = cur_objix_spix; fd->offset = offset + written; prev_objix_spix = cur_objix_spix; } // write partial data u32_t to_write = MIN(len - written, SPIFFS_DATA_PAGE_SIZE(fs) - page_offs); spiffs_page_ix orig_data_pix; if (cur_objix_spix == 0) { // get data page from object index header page orig_data_pix = ((spiffs_page_ix *)((u8_t *)objix_hdr + sizeof(spiffs_page_object_ix_header)))[data_spix]; } else { // get data page from object index page orig_data_pix = ((spiffs_page_ix *)((u8_t *)objix + sizeof(spiffs_page_object_ix)))[SPIFFS_OBJ_IX_ENTRY(fs, data_spix)]; } p_hdr.obj_id = fd->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG; p_hdr.span_ix = data_spix; p_hdr.flags = 0xff; if (page_offs == 0 && to_write == SPIFFS_DATA_PAGE_SIZE(fs)) { // a full page, allocate and write a new page of data res = spiffs_page_allocate_data(fs, fd->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG, &p_hdr, &data[written], to_write, page_offs, 1, &data_pix); SPIFFS_DBG("modify: store new data page, "_SPIPRIpg":"_SPIPRIsp" offset:"_SPIPRIi", len "_SPIPRIi", written "_SPIPRIi"\n", data_pix, data_spix, page_offs, to_write, written); } else { // write to existing page, allocate new and copy unmodified data res = spiffs_page_data_check(fs, fd, orig_data_pix, data_spix); SPIFFS_CHECK_RES(res); res = spiffs_page_allocate_data(fs, fd->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG, &p_hdr, 0, 0, 0, 0, &data_pix); if (res != SPIFFS_OK) break; // copy unmodified data if (page_offs > 0) { // before modification res = spiffs_phys_cpy(fs, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, data_pix) + sizeof(spiffs_page_header), SPIFFS_PAGE_TO_PADDR(fs, orig_data_pix) + sizeof(spiffs_page_header), page_offs); if (res != SPIFFS_OK) break; } if (page_offs + to_write < SPIFFS_DATA_PAGE_SIZE(fs)) { // after modification res = spiffs_phys_cpy(fs, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, data_pix) + sizeof(spiffs_page_header) + page_offs + to_write, SPIFFS_PAGE_TO_PADDR(fs, orig_data_pix) + sizeof(spiffs_page_header) + page_offs + to_write, SPIFFS_DATA_PAGE_SIZE(fs) - (page_offs + to_write)); if (res != SPIFFS_OK) break; } res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, data_pix) + sizeof(spiffs_page_header) + page_offs, to_write, &data[written]); if (res != SPIFFS_OK) break; p_hdr.flags &= ~SPIFFS_PH_FLAG_FINAL; res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, data_pix) + offsetof(spiffs_page_header, flags), sizeof(u8_t), (u8_t *)&p_hdr.flags); if (res != SPIFFS_OK) break; SPIFFS_DBG("modify: store to existing data page, src:"_SPIPRIpg", dst:"_SPIPRIpg":"_SPIPRIsp" offset:"_SPIPRIi", len "_SPIPRIi", written "_SPIPRIi"\n", orig_data_pix, data_pix, data_spix, page_offs, to_write, written); } // delete original data page res = spiffs_page_delete(fs, orig_data_pix); if (res != SPIFFS_OK) break; // update memory representation of object index page with new data page if (cur_objix_spix == 0) { // update object index header page ((spiffs_page_ix *)((u8_t *)objix_hdr + sizeof(spiffs_page_object_ix_header)))[data_spix] = data_pix; SPIFFS_DBG("modify: wrote page "_SPIPRIpg" to objix_hdr entry "_SPIPRIsp" in mem\n", data_pix, data_spix); } else { // update object index page ((spiffs_page_ix *)((u8_t *)objix + sizeof(spiffs_page_object_ix)))[SPIFFS_OBJ_IX_ENTRY(fs, data_spix)] = data_pix; SPIFFS_DBG("modify: wrote page "_SPIPRIpg" to objix entry "_SPIPRIsp" in mem\n", data_pix, (spiffs_span_ix)SPIFFS_OBJ_IX_ENTRY(fs, data_spix)); } // update internals page_offs = 0; data_spix++; written += to_write; } // while all data fd->offset = offset + written; fd->cursor_objix_pix = cur_objix_pix; fd->cursor_objix_spix = cur_objix_spix; // finalize updated object indices s32_t res2 = SPIFFS_OK; if (cur_objix_spix != 0) { // wrote beyond object index header page // write last modified object index page // move and update page spiffs_page_ix new_objix_pix; res2 = spiffs_page_index_check(fs, fd, cur_objix_pix, cur_objix_spix); SPIFFS_CHECK_RES(res2); res2 = spiffs_page_move(fs, fd->file_nbr, (u8_t *)objix, fd->obj_id, 0, cur_objix_pix, &new_objix_pix); SPIFFS_DBG("modify: store modified objix page, "_SPIPRIpg":"_SPIPRIsp", written "_SPIPRIi"\n", new_objix_pix, cur_objix_spix, written); fd->cursor_objix_pix = new_objix_pix; fd->cursor_objix_spix = cur_objix_spix; SPIFFS_CHECK_RES(res2); spiffs_cb_object_event(fs, (spiffs_page_object_ix *)objix, SPIFFS_EV_IX_UPD, fd->obj_id, objix->p_hdr.span_ix, new_objix_pix, 0); } else { // wrote within object index header page res2 = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, fd->objix_hdr_pix, fs->work, 0, 0, 0, &new_objix_hdr_pix); SPIFFS_DBG("modify: store modified objix_hdr page, "_SPIPRIpg":"_SPIPRIsp", written "_SPIPRIi"\n", new_objix_hdr_pix, 0, written); SPIFFS_CHECK_RES(res2); } return res; } // spiffs_object_modify #endif // !SPIFFS_READ_ONLY static s32_t spiffs_object_find_object_index_header_by_name_v( spiffs *fs, spiffs_obj_id obj_id, spiffs_block_ix bix, int ix_entry, const void *user_const_p, void *user_var_p) { (void)user_var_p; s32_t res; spiffs_page_object_ix_header objix_hdr; spiffs_page_ix pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, ix_entry); if (obj_id == SPIFFS_OBJ_ID_FREE || obj_id == SPIFFS_OBJ_ID_DELETED || (obj_id & SPIFFS_OBJ_ID_IX_FLAG) == 0) { return SPIFFS_VIS_COUNTINUE; } res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, pix), sizeof(spiffs_page_object_ix_header), (u8_t *)&objix_hdr); SPIFFS_CHECK_RES(res); if (objix_hdr.p_hdr.span_ix == 0 && (objix_hdr.p_hdr.flags & (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_IXDELE)) == (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_IXDELE)) { if (strcmp((const char *)user_const_p, (char *)objix_hdr.name) == 0) { return SPIFFS_OK; } } return SPIFFS_VIS_COUNTINUE; } // Finds object index header page by name s32_t spiffs_object_find_object_index_header_by_name( spiffs *fs, const u8_t name[SPIFFS_OBJ_NAME_LEN], spiffs_page_ix *pix) { s32_t res; spiffs_block_ix bix; int entry; res = spiffs_obj_lu_find_entry_visitor(fs, fs->cursor_block_ix, fs->cursor_obj_lu_entry, 0, 0, spiffs_object_find_object_index_header_by_name_v, name, 0, &bix, &entry); if (res == SPIFFS_VIS_END) { res = SPIFFS_ERR_NOT_FOUND; } SPIFFS_CHECK_RES(res); if (pix) { *pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, entry); } fs->cursor_block_ix = bix; fs->cursor_obj_lu_entry = entry; return res; } #if !SPIFFS_READ_ONLY // Truncates object to new size. If new size is null, object may be removed totally s32_t spiffs_object_truncate( spiffs_fd *fd, u32_t new_size, u8_t remove_full) { s32_t res = SPIFFS_OK; spiffs *fs = fd->fs; if ((fd->size == SPIFFS_UNDEFINED_LEN || fd->size == 0) && !remove_full) { // no op return res; } // need 2 pages if not removing: object index page + possibly chopped data page if (remove_full == 0) { res = spiffs_gc_check(fs, SPIFFS_DATA_PAGE_SIZE(fs) * 2); SPIFFS_CHECK_RES(res); } spiffs_page_ix objix_pix = fd->objix_hdr_pix; spiffs_span_ix data_spix = (fd->size > 0 ? fd->size - 1 : 0) / SPIFFS_DATA_PAGE_SIZE(fs); u32_t cur_size = fd->size == (u32_t)SPIFFS_UNDEFINED_LEN ? 0 : fd->size ; spiffs_span_ix cur_objix_spix = 0; spiffs_span_ix prev_objix_spix = (spiffs_span_ix) - 1; spiffs_page_object_ix_header *objix_hdr = (spiffs_page_object_ix_header *)fs->work; spiffs_page_object_ix *objix = (spiffs_page_object_ix *)fs->work; spiffs_page_ix data_pix; spiffs_page_ix new_objix_hdr_pix; // before truncating, check if object is to be fully removed and mark this if (remove_full && new_size == 0) { u8_t flags = ~( SPIFFS_PH_FLAG_USED | SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_IXDELE); res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_UPDT, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, fd->objix_hdr_pix) + offsetof(spiffs_page_header, flags), sizeof(u8_t), (u8_t *)&flags); SPIFFS_CHECK_RES(res); } // delete from end of object until desired len is reached while (cur_size > new_size) { cur_objix_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, data_spix); // put object index for current data span index in work buffer if (prev_objix_spix != cur_objix_spix) { if (prev_objix_spix != (spiffs_span_ix) - 1) { // remove previous object index page SPIFFS_DBG("truncate: delete objix page "_SPIPRIpg":"_SPIPRIsp"\n", objix_pix, prev_objix_spix); res = spiffs_page_index_check(fs, fd, objix_pix, prev_objix_spix); SPIFFS_CHECK_RES(res); res = spiffs_page_delete(fs, objix_pix); SPIFFS_CHECK_RES(res); spiffs_cb_object_event(fs, (spiffs_page_object_ix *)0, SPIFFS_EV_IX_DEL, fd->obj_id, objix->p_hdr.span_ix, objix_pix, 0); if (prev_objix_spix > 0) { // Update object index header page, unless we totally want to remove the file. // If fully removing, we're not keeping consistency as good as when storing the header between chunks, // would we be aborted. But when removing full files, a crammed system may otherwise // report ERR_FULL a la windows. We cannot have that. // Hence, take the risk - if aborted, a file check would free the lost pages and mend things // as the file is marked as fully deleted in the beginning. if (remove_full == 0) { SPIFFS_DBG("truncate: update objix hdr page "_SPIPRIpg":"_SPIPRIsp" to size "_SPIPRIi"\n", fd->objix_hdr_pix, prev_objix_spix, cur_size); res = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, fd->objix_hdr_pix, 0, 0, 0, cur_size, &new_objix_hdr_pix); SPIFFS_CHECK_RES(res); } fd->size = cur_size; } } // load current object index (header) page if (cur_objix_spix == 0) { objix_pix = fd->objix_hdr_pix; } else { res = spiffs_obj_lu_find_id_and_span(fs, fd->obj_id | SPIFFS_OBJ_ID_IX_FLAG, cur_objix_spix, 0, &objix_pix); SPIFFS_CHECK_RES(res); } SPIFFS_DBG("truncate: load objix page "_SPIPRIpg":"_SPIPRIsp" for data spix:"_SPIPRIsp"\n", objix_pix, cur_objix_spix, data_spix); res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_READ, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, objix_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->work); SPIFFS_CHECK_RES(res); SPIFFS_VALIDATE_OBJIX(objix_hdr->p_hdr, fd->obj_id, cur_objix_spix); fd->cursor_objix_pix = objix_pix; fd->cursor_objix_spix = cur_objix_spix; fd->offset = cur_size; prev_objix_spix = cur_objix_spix; } if (cur_objix_spix == 0) { // get data page from object index header page data_pix = ((spiffs_page_ix *)((u8_t *)objix_hdr + sizeof(spiffs_page_object_ix_header)))[data_spix]; ((spiffs_page_ix *)((u8_t *)objix_hdr + sizeof(spiffs_page_object_ix_header)))[data_spix] = SPIFFS_OBJ_ID_FREE; } else { // get data page from object index page data_pix = ((spiffs_page_ix *)((u8_t *)objix + sizeof(spiffs_page_object_ix)))[SPIFFS_OBJ_IX_ENTRY(fs, data_spix)]; ((spiffs_page_ix *)((u8_t *)objix + sizeof(spiffs_page_object_ix)))[SPIFFS_OBJ_IX_ENTRY(fs, data_spix)] = SPIFFS_OBJ_ID_FREE; } SPIFFS_DBG("truncate: got data pix "_SPIPRIpg"\n", data_pix); if (new_size == 0 || remove_full || cur_size - new_size >= SPIFFS_DATA_PAGE_SIZE(fs)) { // delete full data page res = spiffs_page_data_check(fs, fd, data_pix, data_spix); if (res != SPIFFS_ERR_DELETED && res != SPIFFS_OK && res != SPIFFS_ERR_INDEX_REF_FREE) { SPIFFS_DBG("truncate: err validating data pix "_SPIPRIi"\n", res); break; } if (res == SPIFFS_OK) { res = spiffs_page_delete(fs, data_pix); if (res != SPIFFS_OK) { SPIFFS_DBG("truncate: err deleting data pix "_SPIPRIi"\n", res); break; } } else if (res == SPIFFS_ERR_DELETED || res == SPIFFS_ERR_INDEX_REF_FREE) { res = SPIFFS_OK; } // update current size if (cur_size % SPIFFS_DATA_PAGE_SIZE(fs) == 0) { cur_size -= SPIFFS_DATA_PAGE_SIZE(fs); } else { cur_size -= cur_size % SPIFFS_DATA_PAGE_SIZE(fs); } fd->size = cur_size; fd->offset = cur_size; SPIFFS_DBG("truncate: delete data page "_SPIPRIpg" for data spix:"_SPIPRIsp", cur_size:"_SPIPRIi"\n", data_pix, data_spix, cur_size); } else { // delete last page, partially spiffs_page_header p_hdr; spiffs_page_ix new_data_pix; u32_t bytes_to_remove = SPIFFS_DATA_PAGE_SIZE(fs) - (new_size % SPIFFS_DATA_PAGE_SIZE(fs)); SPIFFS_DBG("truncate: delete "_SPIPRIi" bytes from data page "_SPIPRIpg" for data spix:"_SPIPRIsp", cur_size:"_SPIPRIi"\n", bytes_to_remove, data_pix, data_spix, cur_size); res = spiffs_page_data_check(fs, fd, data_pix, data_spix); if (res != SPIFFS_OK) break; p_hdr.obj_id = fd->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG; p_hdr.span_ix = data_spix; p_hdr.flags = 0xff; // allocate new page and copy unmodified data res = spiffs_page_allocate_data(fs, fd->obj_id & ~SPIFFS_OBJ_ID_IX_FLAG, &p_hdr, 0, 0, 0, 0, &new_data_pix); if (res != SPIFFS_OK) break; res = spiffs_phys_cpy(fs, 0, SPIFFS_PAGE_TO_PADDR(fs, new_data_pix) + sizeof(spiffs_page_header), SPIFFS_PAGE_TO_PADDR(fs, data_pix) + sizeof(spiffs_page_header), SPIFFS_DATA_PAGE_SIZE(fs) - bytes_to_remove); if (res != SPIFFS_OK) break; // delete original data page res = spiffs_page_delete(fs, data_pix); if (res != SPIFFS_OK) break; p_hdr.flags &= ~SPIFFS_PH_FLAG_FINAL; res = _spiffs_wr(fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_UPDT, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, new_data_pix) + offsetof(spiffs_page_header, flags), sizeof(u8_t), (u8_t *)&p_hdr.flags); if (res != SPIFFS_OK) break; // update memory representation of object index page with new data page if (cur_objix_spix == 0) { // update object index header page ((spiffs_page_ix *)((u8_t *)objix_hdr + sizeof(spiffs_page_object_ix_header)))[data_spix] = new_data_pix; SPIFFS_DBG("truncate: wrote page "_SPIPRIpg" to objix_hdr entry "_SPIPRIsp" in mem\n", new_data_pix, (spiffs_span_ix)SPIFFS_OBJ_IX_ENTRY(fs, data_spix)); } else { // update object index page ((spiffs_page_ix *)((u8_t *)objix + sizeof(spiffs_page_object_ix)))[SPIFFS_OBJ_IX_ENTRY(fs, data_spix)] = new_data_pix; SPIFFS_DBG("truncate: wrote page "_SPIPRIpg" to objix entry "_SPIPRIsp" in mem\n", new_data_pix, (spiffs_span_ix)SPIFFS_OBJ_IX_ENTRY(fs, data_spix)); } cur_size = new_size; fd->size = new_size; fd->offset = cur_size; break; } data_spix--; } // while all data // update object indices if (cur_objix_spix == 0) { // update object index header page if (cur_size == 0) { if (remove_full) { // remove object altogether SPIFFS_DBG("truncate: remove object index header page "_SPIPRIpg"\n", objix_pix); res = spiffs_page_index_check(fs, fd, objix_pix, 0); SPIFFS_CHECK_RES(res); res = spiffs_page_delete(fs, objix_pix); SPIFFS_CHECK_RES(res); spiffs_cb_object_event(fs, (spiffs_page_object_ix *)0, SPIFFS_EV_IX_DEL, fd->obj_id, 0, objix_pix, 0); } else { // make uninitialized object SPIFFS_DBG("truncate: reset objix_hdr page "_SPIPRIpg"\n", objix_pix); memset(fs->work + sizeof(spiffs_page_object_ix_header), 0xff, SPIFFS_CFG_LOG_PAGE_SZ(fs) - sizeof(spiffs_page_object_ix_header)); res = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, objix_pix, fs->work, 0, 0, SPIFFS_UNDEFINED_LEN, &new_objix_hdr_pix); SPIFFS_CHECK_RES(res); } } else { // update object index header page SPIFFS_DBG("truncate: update object index header page with indices and size\n"); res = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, objix_pix, fs->work, 0, 0, cur_size, &new_objix_hdr_pix); SPIFFS_CHECK_RES(res); } } else { // update both current object index page and object index header page spiffs_page_ix new_objix_pix; res = spiffs_page_index_check(fs, fd, objix_pix, cur_objix_spix); SPIFFS_CHECK_RES(res); // move and update object index page res = spiffs_page_move(fs, fd->file_nbr, (u8_t *)objix_hdr, fd->obj_id, 0, objix_pix, &new_objix_pix); SPIFFS_CHECK_RES(res); spiffs_cb_object_event(fs, (spiffs_page_object_ix *)objix_hdr, SPIFFS_EV_IX_UPD, fd->obj_id, objix->p_hdr.span_ix, new_objix_pix, 0); SPIFFS_DBG("truncate: store modified objix page, "_SPIPRIpg":"_SPIPRIsp"\n", new_objix_pix, cur_objix_spix); fd->cursor_objix_pix = new_objix_pix; fd->cursor_objix_spix = cur_objix_spix; fd->offset = cur_size; // update object index header page with new size res = spiffs_object_update_index_hdr(fs, fd, fd->obj_id, fd->objix_hdr_pix, 0, 0, 0, cur_size, &new_objix_hdr_pix); SPIFFS_CHECK_RES(res); } fd->size = cur_size; return res; } // spiffs_object_truncate #endif // !SPIFFS_READ_ONLY s32_t spiffs_object_read( spiffs_fd *fd, u32_t offset, u32_t len, u8_t *dst) { s32_t res = SPIFFS_OK; spiffs *fs = fd->fs; spiffs_page_ix objix_pix; spiffs_page_ix data_pix; spiffs_span_ix data_spix = offset / SPIFFS_DATA_PAGE_SIZE(fs); u32_t cur_offset = offset; spiffs_span_ix cur_objix_spix; spiffs_span_ix prev_objix_spix = (spiffs_span_ix) - 1; spiffs_page_object_ix_header *objix_hdr = (spiffs_page_object_ix_header *)fs->work; spiffs_page_object_ix *objix = (spiffs_page_object_ix *)fs->work; while (cur_offset < offset + len) { #if SPIFFS_IX_MAP // check if we have a memory, index map and if so, if we're within index map's range // and if so, if the entry is populated if (fd->ix_map && data_spix >= fd->ix_map->start_spix && data_spix <= fd->ix_map->end_spix && fd->ix_map->map_buf[data_spix - fd->ix_map->start_spix]) { data_pix = fd->ix_map->map_buf[data_spix - fd->ix_map->start_spix]; } else { #endif cur_objix_spix = SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, data_spix); if (prev_objix_spix != cur_objix_spix) { // load current object index (header) page if (cur_objix_spix == 0) { objix_pix = fd->objix_hdr_pix; } else { SPIFFS_DBG("read: find objix "_SPIPRIid":"_SPIPRIsp"\n", fd->obj_id, cur_objix_spix); if (fd->cursor_objix_spix == cur_objix_spix) { objix_pix = fd->cursor_objix_pix; } else { res = spiffs_obj_lu_find_id_and_span(fs, fd->obj_id | SPIFFS_OBJ_ID_IX_FLAG, cur_objix_spix, 0, &objix_pix); SPIFFS_CHECK_RES(res); } } SPIFFS_DBG("read: load objix page "_SPIPRIpg":"_SPIPRIsp" for data spix:"_SPIPRIsp"\n", objix_pix, cur_objix_spix, data_spix); res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_IX | SPIFFS_OP_C_READ, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, objix_pix), SPIFFS_CFG_LOG_PAGE_SZ(fs), fs->work); SPIFFS_CHECK_RES(res); SPIFFS_VALIDATE_OBJIX(objix->p_hdr, fd->obj_id, cur_objix_spix); fd->offset = cur_offset; fd->cursor_objix_pix = objix_pix; fd->cursor_objix_spix = cur_objix_spix; prev_objix_spix = cur_objix_spix; } if (cur_objix_spix == 0) { // get data page from object index header page data_pix = ((spiffs_page_ix *)((u8_t *)objix_hdr + sizeof(spiffs_page_object_ix_header)))[data_spix]; } else { // get data page from object index page data_pix = ((spiffs_page_ix *)((u8_t *)objix + sizeof(spiffs_page_object_ix)))[SPIFFS_OBJ_IX_ENTRY(fs, data_spix)]; } #if SPIFFS_IX_MAP } #endif // all remaining data u32_t len_to_read = offset + len - cur_offset; // remaining data in page len_to_read = MIN(len_to_read, SPIFFS_DATA_PAGE_SIZE(fs) - (cur_offset % SPIFFS_DATA_PAGE_SIZE(fs))); // remaining data in file len_to_read = MIN(len_to_read, fd->size); SPIFFS_DBG("read: offset:"_SPIPRIi" rd:"_SPIPRIi" data spix:"_SPIPRIsp" is data_pix:"_SPIPRIpg" addr:"_SPIPRIad"\n", cur_offset, len_to_read, data_spix, data_pix, (u32_t)(SPIFFS_PAGE_TO_PADDR(fs, data_pix) + sizeof(spiffs_page_header) + (cur_offset % SPIFFS_DATA_PAGE_SIZE(fs)))); if (len_to_read <= 0) { res = SPIFFS_ERR_END_OF_OBJECT; break; } res = spiffs_page_data_check(fs, fd, data_pix, data_spix); SPIFFS_CHECK_RES(res); res = _spiffs_rd( fs, SPIFFS_OP_T_OBJ_DA | SPIFFS_OP_C_READ, fd->file_nbr, SPIFFS_PAGE_TO_PADDR(fs, data_pix) + sizeof(spiffs_page_header) + (cur_offset % SPIFFS_DATA_PAGE_SIZE(fs)), len_to_read, dst); SPIFFS_CHECK_RES(res); dst += len_to_read; cur_offset += len_to_read; fd->offset = cur_offset; data_spix++; } return res; } #if !SPIFFS_READ_ONLY typedef struct { spiffs_obj_id min_obj_id; spiffs_obj_id max_obj_id; u32_t compaction; const u8_t *conflicting_name; } spiffs_free_obj_id_state; static s32_t spiffs_obj_lu_find_free_obj_id_bitmap_v(spiffs *fs, spiffs_obj_id id, spiffs_block_ix bix, int ix_entry, const void *user_const_p, void *user_var_p) { if (id != SPIFFS_OBJ_ID_FREE && id != SPIFFS_OBJ_ID_DELETED) { spiffs_obj_id min_obj_id = *((spiffs_obj_id *)user_var_p); const u8_t *conflicting_name = (const u8_t *)user_const_p; // if conflicting name parameter is given, also check if this name is found in object index hdrs if (conflicting_name && (id & SPIFFS_OBJ_ID_IX_FLAG)) { spiffs_page_ix pix = SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, bix, ix_entry); int res; spiffs_page_object_ix_header objix_hdr; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_PAGE_TO_PADDR(fs, pix), sizeof(spiffs_page_object_ix_header), (u8_t *)&objix_hdr); SPIFFS_CHECK_RES(res); if (objix_hdr.p_hdr.span_ix == 0 && (objix_hdr.p_hdr.flags & (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_IXDELE)) == (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_IXDELE)) { if (strcmp((const char *)user_const_p, (char *)objix_hdr.name) == 0) { return SPIFFS_ERR_CONFLICTING_NAME; } } } id &= ~SPIFFS_OBJ_ID_IX_FLAG; u32_t bit_ix = (id - min_obj_id) & 7; int byte_ix = (id - min_obj_id) >> 3; if (byte_ix >= 0 && (u32_t)byte_ix < SPIFFS_CFG_LOG_PAGE_SZ(fs)) { fs->work[byte_ix] |= (1 << bit_ix); } } return SPIFFS_VIS_COUNTINUE; } static s32_t spiffs_obj_lu_find_free_obj_id_compact_v(spiffs *fs, spiffs_obj_id id, spiffs_block_ix bix, int ix_entry, const void *user_const_p, void *user_var_p) { (void)user_var_p; if (id != SPIFFS_OBJ_ID_FREE && id != SPIFFS_OBJ_ID_DELETED && (id & SPIFFS_OBJ_ID_IX_FLAG)) { s32_t res; const spiffs_free_obj_id_state *state = (const spiffs_free_obj_id_state *)user_const_p; spiffs_page_object_ix_header objix_hdr; res = _spiffs_rd(fs, SPIFFS_OP_T_OBJ_LU2 | SPIFFS_OP_C_READ, 0, SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, bix, ix_entry), sizeof(spiffs_page_object_ix_header), (u8_t *)&objix_hdr); if (res == SPIFFS_OK && objix_hdr.p_hdr.span_ix == 0 && ((objix_hdr.p_hdr.flags & (SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_DELET)) == (SPIFFS_PH_FLAG_DELET))) { // ok object look up entry if (state->conflicting_name && strcmp((const char *)state->conflicting_name, (char *)objix_hdr.name) == 0) { return SPIFFS_ERR_CONFLICTING_NAME; } id &= ~SPIFFS_OBJ_ID_IX_FLAG; if (id >= state->min_obj_id && id <= state->max_obj_id) { u8_t *map = (u8_t *)fs->work; int ix = (id - state->min_obj_id) / state->compaction; //SPIFFS_DBG("free_obj_id: add ix "_SPIPRIi" for id "_SPIPRIid" min"_SPIPRIid" max"_SPIPRIid" comp:"_SPIPRIi"\n", ix, id, state->min_obj_id, state->max_obj_id, state->compaction); map[ix]++; } } } return SPIFFS_VIS_COUNTINUE; } // Scans thru all object lookup for object index header pages. If total possible number of // object ids cannot fit into a work buffer, these are grouped. When a group containing free // object ids is found, the object lu is again scanned for object ids within group and bitmasked. // Finally, the bitmask is searched for a free id s32_t spiffs_obj_lu_find_free_obj_id(spiffs *fs, spiffs_obj_id *obj_id, const u8_t *conflicting_name) { s32_t res = SPIFFS_OK; u32_t max_objects = (fs->block_count * SPIFFS_OBJ_LOOKUP_MAX_ENTRIES(fs)) / 2; spiffs_free_obj_id_state state; spiffs_obj_id free_obj_id = SPIFFS_OBJ_ID_FREE; state.min_obj_id = 1; state.max_obj_id = max_objects + 1; if (state.max_obj_id & SPIFFS_OBJ_ID_IX_FLAG) { state.max_obj_id = ((spiffs_obj_id) - 1) & ~SPIFFS_OBJ_ID_IX_FLAG; } state.compaction = 0; state.conflicting_name = conflicting_name; while (res == SPIFFS_OK && free_obj_id == SPIFFS_OBJ_ID_FREE) { if (state.max_obj_id - state.min_obj_id <= (spiffs_obj_id)SPIFFS_CFG_LOG_PAGE_SZ(fs) * 8) { // possible to represent in bitmap u32_t i, j; SPIFFS_DBG("free_obj_id: BITM min:"_SPIPRIid" max:"_SPIPRIid"\n", state.min_obj_id, state.max_obj_id); memset(fs->work, 0, SPIFFS_CFG_LOG_PAGE_SZ(fs)); res = spiffs_obj_lu_find_entry_visitor(fs, 0, 0, 0, 0, spiffs_obj_lu_find_free_obj_id_bitmap_v, conflicting_name, &state.min_obj_id, 0, 0); if (res == SPIFFS_VIS_END) res = SPIFFS_OK; SPIFFS_CHECK_RES(res); // traverse bitmask until found free obj_id for (i = 0; i < SPIFFS_CFG_LOG_PAGE_SZ(fs); i++) { u8_t mask = fs->work[i]; if (mask == 0xff) { continue; } for (j = 0; j < 8; j++) { if ((mask & (1 << j)) == 0) { *obj_id = (i << 3) + j + state.min_obj_id; return SPIFFS_OK; } } } return SPIFFS_ERR_FULL; } else { // not possible to represent all ids in range in a bitmap, compact and count if (state.compaction != 0) { // select element in compacted table, decrease range and recompact u32_t i, min_i = 0; u8_t *map = (u8_t *)fs->work; u8_t min_count = 0xff; for (i = 0; i < SPIFFS_CFG_LOG_PAGE_SZ(fs) / sizeof(u8_t); i++) { if (map[i] < min_count) { min_count = map[i]; min_i = i; if (min_count == 0) { break; } } } if (min_count == state.compaction) { // there are no free objids! SPIFFS_DBG("free_obj_id: compacted table is full\n"); return SPIFFS_ERR_FULL; } SPIFFS_DBG("free_obj_id: COMP select index:"_SPIPRIi" min_count:"_SPIPRIi" min:"_SPIPRIid" max:"_SPIPRIid" compact:"_SPIPRIi"\n", min_i, min_count, state.min_obj_id, state.max_obj_id, state.compaction); if (min_count == 0) { // no id in this range, skip compacting and use directly *obj_id = min_i * state.compaction + state.min_obj_id; return SPIFFS_OK; } else { SPIFFS_DBG("free_obj_id: COMP SEL chunk:"_SPIPRIi" min:"_SPIPRIid" -> "_SPIPRIid"\n", state.compaction, state.min_obj_id, state.min_obj_id + min_i * state.compaction); state.min_obj_id += min_i * state.compaction; state.max_obj_id = state.min_obj_id + state.compaction; // decrease compaction } if ((state.max_obj_id - state.min_obj_id <= (spiffs_obj_id)SPIFFS_CFG_LOG_PAGE_SZ(fs) * 8)) { // no need for compacting, use bitmap continue; } } // in a work memory of log_page_size bytes, we may fit in log_page_size ids // todo what if compaction is > 255 - then we cannot fit it in a byte state.compaction = (state.max_obj_id - state.min_obj_id) / ((SPIFFS_CFG_LOG_PAGE_SZ(fs) / sizeof(u8_t))); SPIFFS_DBG("free_obj_id: COMP min:"_SPIPRIid" max:"_SPIPRIid" compact:"_SPIPRIi"\n", state.min_obj_id, state.max_obj_id, state.compaction); memset(fs->work, 0, SPIFFS_CFG_LOG_PAGE_SZ(fs)); res = spiffs_obj_lu_find_entry_visitor(fs, 0, 0, 0, 0, spiffs_obj_lu_find_free_obj_id_compact_v, &state, 0, 0, 0); if (res == SPIFFS_VIS_END) res = SPIFFS_OK; SPIFFS_CHECK_RES(res); state.conflicting_name = 0; // searched for conflicting name once, no need to do it again } } return res; } #endif // !SPIFFS_READ_ONLY #if SPIFFS_TEMPORAL_FD_CACHE // djb2 hash static u32_t spiffs_hash(spiffs *fs, const u8_t *name) { (void)fs; u32_t hash = 5381; u8_t c; int i = 0; while (0 != (c = name[i++]) && i < SPIFFS_OBJ_NAME_LEN) { hash = (hash * 33) ^ c; } return hash; } #endif s32_t spiffs_fd_find_new(spiffs *fs, spiffs_fd **fd, const char *name) { #if SPIFFS_TEMPORAL_FD_CACHE u32_t i; u16_t min_score = 0xffff; u32_t cand_ix = (u32_t) - 1; u32_t name_hash = name ? spiffs_hash(fs, (const u8_t *)name) : 0; spiffs_fd *fds = (spiffs_fd *)fs->fd_space; if (name) { // first, decrease score of all closed descriptors for (i = 0; i < fs->fd_count; i++) { spiffs_fd *cur_fd = &fds[i]; if (cur_fd->file_nbr == 0) { if (cur_fd->score > 1) // score == 0 indicates never used fd { cur_fd->score--; } } } } // find the free fd with least score or name match for (i = 0; i < fs->fd_count; i++) { spiffs_fd *cur_fd = &fds[i]; if (cur_fd->file_nbr == 0) { if (name && cur_fd->name_hash == name_hash) { cand_ix = i; break; } if (cur_fd->score < min_score) { min_score = cur_fd->score; cand_ix = i; } } } if (cand_ix != (u32_t) - 1) { spiffs_fd *cur_fd = &fds[cand_ix]; if (name) { if (cur_fd->name_hash == name_hash && cur_fd->score > 0) { // opened an fd with same name hash, assume same file // set search point to saved obj index page and hope we have a correct match directly // when start searching - if not, we will just keep searching until it is found fs->cursor_block_ix = SPIFFS_BLOCK_FOR_PAGE(fs, cur_fd->objix_hdr_pix); fs->cursor_obj_lu_entry = SPIFFS_OBJ_LOOKUP_ENTRY_FOR_PAGE(fs, cur_fd->objix_hdr_pix); // update score if (cur_fd->score < 0xffff - SPIFFS_TEMPORAL_CACHE_HIT_SCORE) { cur_fd->score += SPIFFS_TEMPORAL_CACHE_HIT_SCORE; } else { cur_fd->score = 0xffff; } } else { // no hash hit, restore this fd to initial state cur_fd->score = SPIFFS_TEMPORAL_CACHE_HIT_SCORE; cur_fd->name_hash = name_hash; } } cur_fd->file_nbr = cand_ix + 1; *fd = cur_fd; return SPIFFS_OK; } else { return SPIFFS_ERR_OUT_OF_FILE_DESCS; } #else (void)name; u32_t i; spiffs_fd *fds = (spiffs_fd *)fs->fd_space; for (i = 0; i < fs->fd_count; i++) { spiffs_fd *cur_fd = &fds[i]; if (cur_fd->file_nbr == 0) { cur_fd->file_nbr = i + 1; *fd = cur_fd; return SPIFFS_OK; } } return SPIFFS_ERR_OUT_OF_FILE_DESCS; #endif } s32_t spiffs_fd_return(spiffs *fs, spiffs_file f) { if (f <= 0 || f > (s16_t)fs->fd_count) { return SPIFFS_ERR_BAD_DESCRIPTOR; } spiffs_fd *fds = (spiffs_fd *)fs->fd_space; spiffs_fd *fd = &fds[f - 1]; if (fd->file_nbr == 0) { return SPIFFS_ERR_FILE_CLOSED; } fd->file_nbr = 0; #if SPIFFS_IX_MAP fd->ix_map = 0; #endif return SPIFFS_OK; } s32_t spiffs_fd_get(spiffs *fs, spiffs_file f, spiffs_fd **fd) { if (f <= 0 || f > (s16_t)fs->fd_count) { return SPIFFS_ERR_BAD_DESCRIPTOR; } spiffs_fd *fds = (spiffs_fd *)fs->fd_space; *fd = &fds[f - 1]; if ((*fd)->file_nbr == 0) { return SPIFFS_ERR_FILE_CLOSED; } return SPIFFS_OK; } #if SPIFFS_TEMPORAL_FD_CACHE void spiffs_fd_temporal_cache_rehash( spiffs *fs, const char *old_path, const char *new_path) { u32_t i; u32_t old_hash = spiffs_hash(fs, (const u8_t *)old_path); u32_t new_hash = spiffs_hash(fs, (const u8_t *)new_path); spiffs_fd *fds = (spiffs_fd *)fs->fd_space; for (i = 0; i < fs->fd_count; i++) { spiffs_fd *cur_fd = &fds[i]; if (cur_fd->score > 0 && cur_fd->name_hash == old_hash) { cur_fd->name_hash = new_hash; } } } #endif ================================================ FILE: Huawei_LiteOS/components/fs/spiffs/spiffs_git/src/spiffs_nucleus.h ================================================ /* * spiffs_nucleus.h * * Created on: Jun 15, 2013 * Author: petera */ /* SPIFFS layout * * spiffs is designed for following spi flash characteristics: * - only big areas of data (blocks) can be erased * - erasing resets all bits in a block to ones * - writing pulls ones to zeroes * - zeroes cannot be pulled to ones, without erase * - wear leveling * * spiffs is also meant to be run on embedded, memory constraint devices. * * Entire area is divided in blocks. Entire area is also divided in pages. * Each block contains same number of pages. A page cannot be erased, but a * block can be erased. * * Entire area must be block_size * x * page_size must be block_size / (2^y) where y > 2 * * ex: area = 1024*1024 bytes, block size = 65536 bytes, page size = 256 bytes * * BLOCK 0 PAGE 0 object lookup 1 * PAGE 1 object lookup 2 * ... * PAGE n-1 object lookup n * PAGE n object data 1 * PAGE n+1 object data 2 * ... * PAGE n+m-1 object data m * * BLOCK 1 PAGE n+m object lookup 1 * PAGE n+m+1 object lookup 2 * ... * PAGE 2n+m-1 object lookup n * PAGE 2n+m object data 1 * PAGE 2n+m object data 2 * ... * PAGE 2n+2m-1 object data m * ... * * n is number of object lookup pages, which is number of pages needed to index all pages * in a block by object id * : block_size / page_size * sizeof(obj_id) / page_size * m is number data pages, which is number of pages in block minus number of lookup pages * : block_size / page_size - block_size / page_size * sizeof(obj_id) / page_size * thus, n+m is total number of pages in a block * : block_size / page_size * * ex: n = 65536/256*2/256 = 2, m = 65536/256 - 2 = 254 => n+m = 65536/256 = 256 * * Object lookup pages contain object id entries. Each entry represent the corresponding * data page. * Assuming a 16 bit object id, an object id being 0xffff represents a free page. * An object id being 0x0000 represents a deleted page. * * ex: page 0 : lookup : 0008 0001 0aaa ffff ffff ffff ffff ffff .. * page 1 : lookup : ffff ffff ffff ffff ffff ffff ffff ffff .. * page 2 : data : data for object id 0008 * page 3 : data : data for object id 0001 * page 4 : data : data for object id 0aaa * ... * * * Object data pages can be either object index pages or object content. * All object data pages contains a data page header, containing object id and span index. * The span index denotes the object page ordering amongst data pages with same object id. * This applies to both object index pages (when index spans more than one page of entries), * and object data pages. * An object index page contains page entries pointing to object content page. The entry index * in a object index page correlates to the span index in the actual object data page. * The first object index page (span index 0) is called object index header page, and also * contains object flags (directory/file), size, object name etc. * * ex: * BLOCK 1 * PAGE 256: objectl lookup page 1 * [*123] [ 123] [ 123] [ 123] * [ 123] [*123] [ 123] [ 123] * [free] [free] [free] [free] ... * PAGE 257: objectl lookup page 2 * [free] [free] [free] [free] ... * PAGE 258: object index page (header) * obj.id:0123 span.ix:0000 flags:INDEX * size:1600 name:ex.txt type:file * [259] [260] [261] [262] * PAGE 259: object data page * obj.id:0123 span.ix:0000 flags:DATA * PAGE 260: object data page * obj.id:0123 span.ix:0001 flags:DATA * PAGE 261: object data page * obj.id:0123 span.ix:0002 flags:DATA * PAGE 262: object data page * obj.id:0123 span.ix:0003 flags:DATA * PAGE 263: object index page * obj.id:0123 span.ix:0001 flags:INDEX * [264] [265] [fre] [fre] * [fre] [fre] [fre] [fre] * PAGE 264: object data page * obj.id:0123 span.ix:0004 flags:DATA * PAGE 265: object data page * obj.id:0123 span.ix:0005 flags:DATA * */ #ifndef SPIFFS_NUCLEUS_H_ #define SPIFFS_NUCLEUS_H_ #define _SPIFFS_ERR_CHECK_FIRST (SPIFFS_ERR_INTERNAL - 1) #define SPIFFS_ERR_CHECK_OBJ_ID_MISM (SPIFFS_ERR_INTERNAL - 1) #define SPIFFS_ERR_CHECK_SPIX_MISM (SPIFFS_ERR_INTERNAL - 2) #define SPIFFS_ERR_CHECK_FLAGS_BAD (SPIFFS_ERR_INTERNAL - 3) #define _SPIFFS_ERR_CHECK_LAST (SPIFFS_ERR_INTERNAL - 4) // visitor result, continue searching #define SPIFFS_VIS_COUNTINUE (SPIFFS_ERR_INTERNAL - 20) // visitor result, continue searching after reloading lu buffer #define SPIFFS_VIS_COUNTINUE_RELOAD (SPIFFS_ERR_INTERNAL - 21) // visitor result, stop searching #define SPIFFS_VIS_END (SPIFFS_ERR_INTERNAL - 22) // updating an object index contents #define SPIFFS_EV_IX_UPD (0) // creating a new object index #define SPIFFS_EV_IX_NEW (1) // deleting an object index #define SPIFFS_EV_IX_DEL (2) // moving an object index without updating contents #define SPIFFS_EV_IX_MOV (3) // updating an object index header data only, not the table itself #define SPIFFS_EV_IX_UPD_HDR (4) #define SPIFFS_OBJ_ID_IX_FLAG ((spiffs_obj_id)(1<<(8*sizeof(spiffs_obj_id)-1))) #define SPIFFS_UNDEFINED_LEN (u32_t)(-1) #define SPIFFS_OBJ_ID_DELETED ((spiffs_obj_id)0) #define SPIFFS_OBJ_ID_FREE ((spiffs_obj_id)-1) #if defined(__GNUC__) || defined(__clang__) || defined(__TI_COMPILER_VERSION__) /* For GCC, clang and TI compilers */ #define SPIFFS_PACKED __attribute__((packed)) #elif defined(__ICCARM__) || defined(__CC_ARM) /* For IAR ARM and Keil MDK-ARM compilers */ #define SPIFFS_PACKED #else /* Unknown compiler */ #define SPIFFS_PACKED #endif #if SPIFFS_USE_MAGIC #if !SPIFFS_USE_MAGIC_LENGTH #define SPIFFS_MAGIC(fs, bix) \ ((spiffs_obj_id)(0x20140529 ^ SPIFFS_CFG_LOG_PAGE_SZ(fs))) #else // SPIFFS_USE_MAGIC_LENGTH #define SPIFFS_MAGIC(fs, bix) \ ((spiffs_obj_id)(0x20140529 ^ SPIFFS_CFG_LOG_PAGE_SZ(fs) ^ ((fs)->block_count - (bix)))) #endif // SPIFFS_USE_MAGIC_LENGTH #endif // SPIFFS_USE_MAGIC #define SPIFFS_CONFIG_MAGIC (0x20090315) #if SPIFFS_SINGLETON == 0 #define SPIFFS_CFG_LOG_PAGE_SZ(fs) \ ((fs)->cfg.log_page_size) #define SPIFFS_CFG_LOG_BLOCK_SZ(fs) \ ((fs)->cfg.log_block_size) #define SPIFFS_CFG_PHYS_SZ(fs) \ ((fs)->cfg.phys_size) #define SPIFFS_CFG_PHYS_ERASE_SZ(fs) \ ((fs)->cfg.phys_erase_block) #define SPIFFS_CFG_PHYS_ADDR(fs) \ ((fs)->cfg.phys_addr) #endif // total number of pages #define SPIFFS_MAX_PAGES(fs) \ ( SPIFFS_CFG_PHYS_SZ(fs)/SPIFFS_CFG_LOG_PAGE_SZ(fs) ) // total number of pages per block, including object lookup pages #define SPIFFS_PAGES_PER_BLOCK(fs) \ ( SPIFFS_CFG_LOG_BLOCK_SZ(fs)/SPIFFS_CFG_LOG_PAGE_SZ(fs) ) // number of object lookup pages per block #define SPIFFS_OBJ_LOOKUP_PAGES(fs) \ (MAX(1, (SPIFFS_PAGES_PER_BLOCK(fs) * sizeof(spiffs_obj_id)) / SPIFFS_CFG_LOG_PAGE_SZ(fs)) ) // checks if page index belongs to object lookup #define SPIFFS_IS_LOOKUP_PAGE(fs,pix) \ (((pix) % SPIFFS_PAGES_PER_BLOCK(fs)) < SPIFFS_OBJ_LOOKUP_PAGES(fs)) // number of object lookup entries in all object lookup pages #define SPIFFS_OBJ_LOOKUP_MAX_ENTRIES(fs) \ (SPIFFS_PAGES_PER_BLOCK(fs)-SPIFFS_OBJ_LOOKUP_PAGES(fs)) // converts a block to physical address #define SPIFFS_BLOCK_TO_PADDR(fs, block) \ ( SPIFFS_CFG_PHYS_ADDR(fs) + (block)* SPIFFS_CFG_LOG_BLOCK_SZ(fs) ) // converts a object lookup entry to page index #define SPIFFS_OBJ_LOOKUP_ENTRY_TO_PIX(fs, block, entry) \ ((block)*SPIFFS_PAGES_PER_BLOCK(fs) + (SPIFFS_OBJ_LOOKUP_PAGES(fs) + entry)) // converts a object lookup entry to physical address of corresponding page #define SPIFFS_OBJ_LOOKUP_ENTRY_TO_PADDR(fs, block, entry) \ (SPIFFS_BLOCK_TO_PADDR(fs, block) + (SPIFFS_OBJ_LOOKUP_PAGES(fs) + entry) * SPIFFS_CFG_LOG_PAGE_SZ(fs) ) // converts a page to physical address #define SPIFFS_PAGE_TO_PADDR(fs, page) \ ( SPIFFS_CFG_PHYS_ADDR(fs) + (page) * SPIFFS_CFG_LOG_PAGE_SZ(fs) ) // converts a physical address to page #define SPIFFS_PADDR_TO_PAGE(fs, addr) \ ( ((addr) - SPIFFS_CFG_PHYS_ADDR(fs)) / SPIFFS_CFG_LOG_PAGE_SZ(fs) ) // gives index in page for a physical address #define SPIFFS_PADDR_TO_PAGE_OFFSET(fs, addr) \ ( ((addr) - SPIFFS_CFG_PHYS_ADDR(fs)) % SPIFFS_CFG_LOG_PAGE_SZ(fs) ) // returns containing block for given page #define SPIFFS_BLOCK_FOR_PAGE(fs, page) \ ( (page) / SPIFFS_PAGES_PER_BLOCK(fs) ) // returns starting page for block #define SPIFFS_PAGE_FOR_BLOCK(fs, block) \ ( (block) * SPIFFS_PAGES_PER_BLOCK(fs) ) // converts page to entry in object lookup page #define SPIFFS_OBJ_LOOKUP_ENTRY_FOR_PAGE(fs, page) \ ( (page) % SPIFFS_PAGES_PER_BLOCK(fs) - SPIFFS_OBJ_LOOKUP_PAGES(fs) ) // returns data size in a data page #define SPIFFS_DATA_PAGE_SIZE(fs) \ ( SPIFFS_CFG_LOG_PAGE_SZ(fs) - sizeof(spiffs_page_header) ) // returns physical address for block's erase count, // always in the physical last entry of the last object lookup page #define SPIFFS_ERASE_COUNT_PADDR(fs, bix) \ ( SPIFFS_BLOCK_TO_PADDR(fs, bix) + SPIFFS_OBJ_LOOKUP_PAGES(fs) * SPIFFS_CFG_LOG_PAGE_SZ(fs) - sizeof(spiffs_obj_id) ) // returns physical address for block's magic, // always in the physical second last entry of the last object lookup page #define SPIFFS_MAGIC_PADDR(fs, bix) \ ( SPIFFS_BLOCK_TO_PADDR(fs, bix) + SPIFFS_OBJ_LOOKUP_PAGES(fs) * SPIFFS_CFG_LOG_PAGE_SZ(fs) - sizeof(spiffs_obj_id)*2 ) // checks if there is any room for magic in the object luts #define SPIFFS_CHECK_MAGIC_POSSIBLE(fs) \ ( (SPIFFS_OBJ_LOOKUP_MAX_ENTRIES(fs) % (SPIFFS_CFG_LOG_PAGE_SZ(fs)/sizeof(spiffs_obj_id))) * sizeof(spiffs_obj_id) \ <= (SPIFFS_CFG_LOG_PAGE_SZ(fs)-sizeof(spiffs_obj_id)*2) ) // define helpers object // entries in an object header page index #define SPIFFS_OBJ_HDR_IX_LEN(fs) \ ((SPIFFS_CFG_LOG_PAGE_SZ(fs) - sizeof(spiffs_page_object_ix_header))/sizeof(spiffs_page_ix)) // entries in an object page index #define SPIFFS_OBJ_IX_LEN(fs) \ ((SPIFFS_CFG_LOG_PAGE_SZ(fs) - sizeof(spiffs_page_object_ix))/sizeof(spiffs_page_ix)) // object index entry for given data span index #define SPIFFS_OBJ_IX_ENTRY(fs, spix) \ ((spix) < SPIFFS_OBJ_HDR_IX_LEN(fs) ? (spix) : (((spix)-SPIFFS_OBJ_HDR_IX_LEN(fs))%SPIFFS_OBJ_IX_LEN(fs))) // object index span index number for given data span index or entry #define SPIFFS_OBJ_IX_ENTRY_SPAN_IX(fs, spix) \ ((spix) < SPIFFS_OBJ_HDR_IX_LEN(fs) ? 0 : (1+((spix)-SPIFFS_OBJ_HDR_IX_LEN(fs))/SPIFFS_OBJ_IX_LEN(fs))) // get data span index for object index span index #define SPIFFS_DATA_SPAN_IX_FOR_OBJ_IX_SPAN_IX(fs, spix) \ ( (spix) == 0 ? 0 : (SPIFFS_OBJ_HDR_IX_LEN(fs) + (((spix)-1) * SPIFFS_OBJ_IX_LEN(fs))) ) #if SPIFFS_FILEHDL_OFFSET #define SPIFFS_FH_OFFS(fs, fh) ((fh) != 0 ? ((fh) + (fs)->cfg.fh_ix_offset) : 0) #define SPIFFS_FH_UNOFFS(fs, fh) ((fh) != 0 ? ((fh) - (fs)->cfg.fh_ix_offset) : 0) #else #define SPIFFS_FH_OFFS(fs, fh) (fh) #define SPIFFS_FH_UNOFFS(fs, fh) (fh) #endif #define SPIFFS_OP_T_OBJ_LU (0<<0) #define SPIFFS_OP_T_OBJ_LU2 (1<<0) #define SPIFFS_OP_T_OBJ_IX (2<<0) #define SPIFFS_OP_T_OBJ_DA (3<<0) #define SPIFFS_OP_C_DELE (0<<2) #define SPIFFS_OP_C_UPDT (1<<2) #define SPIFFS_OP_C_MOVS (2<<2) #define SPIFFS_OP_C_MOVD (3<<2) #define SPIFFS_OP_C_FLSH (4<<2) #define SPIFFS_OP_C_READ (5<<2) #define SPIFFS_OP_C_WRTHRU (6<<2) #define SPIFFS_OP_TYPE_MASK (3<<0) #define SPIFFS_OP_COM_MASK (7<<2) // if 0, this page is written to, else clean #define SPIFFS_PH_FLAG_USED (1<<0) // if 0, writing is finalized, else under modification #define SPIFFS_PH_FLAG_FINAL (1<<1) // if 0, this is an index page, else a data page #define SPIFFS_PH_FLAG_INDEX (1<<2) // if 0, page is deleted, else valid #define SPIFFS_PH_FLAG_DELET (1<<7) // if 0, this index header is being deleted #define SPIFFS_PH_FLAG_IXDELE (1<<6) #define SPIFFS_CHECK_MOUNT(fs) \ ((fs)->mounted != 0) #define SPIFFS_CHECK_CFG(fs) \ ((fs)->config_magic == SPIFFS_CONFIG_MAGIC) #define SPIFFS_CHECK_RES(res) \ do { \ if ((res) < SPIFFS_OK) return (res); \ } while (0); #define SPIFFS_API_CHECK_MOUNT(fs) \ if (!SPIFFS_CHECK_MOUNT((fs))) { \ (fs)->err_code = SPIFFS_ERR_NOT_MOUNTED; \ return SPIFFS_ERR_NOT_MOUNTED; \ } #define SPIFFS_API_CHECK_CFG(fs) \ if (!SPIFFS_CHECK_CFG((fs))) { \ (fs)->err_code = SPIFFS_ERR_NOT_CONFIGURED; \ return SPIFFS_ERR_NOT_CONFIGURED; \ } #define SPIFFS_API_CHECK_RES(fs, res) \ if ((res) < SPIFFS_OK) { \ (fs)->err_code = (res); \ return (res); \ } #define SPIFFS_API_CHECK_RES_UNLOCK(fs, res) \ if ((res) < SPIFFS_OK) { \ (fs)->err_code = (res); \ SPIFFS_UNLOCK(fs); \ return (res); \ } #define SPIFFS_VALIDATE_OBJIX(ph, objid, spix) \ if (((ph).flags & SPIFFS_PH_FLAG_USED) != 0) return SPIFFS_ERR_IS_FREE; \ if (((ph).flags & SPIFFS_PH_FLAG_DELET) == 0) return SPIFFS_ERR_DELETED; \ if (((ph).flags & SPIFFS_PH_FLAG_FINAL) != 0) return SPIFFS_ERR_NOT_FINALIZED; \ if (((ph).flags & SPIFFS_PH_FLAG_INDEX) != 0) return SPIFFS_ERR_NOT_INDEX; \ if (((objid) & SPIFFS_OBJ_ID_IX_FLAG) == 0) return SPIFFS_ERR_NOT_INDEX; \ if ((ph).span_ix != (spix)) return SPIFFS_ERR_INDEX_SPAN_MISMATCH; //if ((spix) == 0 && ((ph).flags & SPIFFS_PH_FLAG_IXDELE) == 0) return SPIFFS_ERR_DELETED; #define SPIFFS_VALIDATE_DATA(ph, objid, spix) \ if (((ph).flags & SPIFFS_PH_FLAG_USED) != 0) return SPIFFS_ERR_IS_FREE; \ if (((ph).flags & SPIFFS_PH_FLAG_DELET) == 0) return SPIFFS_ERR_DELETED; \ if (((ph).flags & SPIFFS_PH_FLAG_FINAL) != 0) return SPIFFS_ERR_NOT_FINALIZED; \ if (((ph).flags & SPIFFS_PH_FLAG_INDEX) == 0) return SPIFFS_ERR_IS_INDEX; \ if ((objid) & SPIFFS_OBJ_ID_IX_FLAG) return SPIFFS_ERR_IS_INDEX; \ if ((ph).span_ix != (spix)) return SPIFFS_ERR_DATA_SPAN_MISMATCH; // check id, only visit matching objec ids #define SPIFFS_VIS_CHECK_ID (1<<0) // report argument object id to visitor - else object lookup id is reported #define SPIFFS_VIS_CHECK_PH (1<<1) // stop searching at end of all look up pages #define SPIFFS_VIS_NO_WRAP (1<<2) #if SPIFFS_HAL_CALLBACK_EXTRA #define SPIFFS_HAL_WRITE(_fs, _paddr, _len, _src) \ (_fs)->cfg.hal_write_f((_fs), (_paddr), (_len), (_src)) #define SPIFFS_HAL_READ(_fs, _paddr, _len, _dst) \ (_fs)->cfg.hal_read_f((_fs), (_paddr), (_len), (_dst)) #define SPIFFS_HAL_ERASE(_fs, _paddr, _len) \ (_fs)->cfg.hal_erase_f((_fs), (_paddr), (_len)) #else // SPIFFS_HAL_CALLBACK_EXTRA #define SPIFFS_HAL_WRITE(_fs, _paddr, _len, _src) \ (_fs)->cfg.hal_write_f((_paddr), (_len), (_src)) #define SPIFFS_HAL_READ(_fs, _paddr, _len, _dst) \ (_fs)->cfg.hal_read_f((_paddr), (_len), (_dst)) #define SPIFFS_HAL_ERASE(_fs, _paddr, _len) \ (_fs)->cfg.hal_erase_f((_paddr), (_len)) #endif // SPIFFS_HAL_CALLBACK_EXTRA #if SPIFFS_CACHE #define SPIFFS_CACHE_FLAG_DIRTY (1<<0) #define SPIFFS_CACHE_FLAG_WRTHRU (1<<1) #define SPIFFS_CACHE_FLAG_OBJLU (1<<2) #define SPIFFS_CACHE_FLAG_OBJIX (1<<3) #define SPIFFS_CACHE_FLAG_DATA (1<<4) #define SPIFFS_CACHE_FLAG_TYPE_WR (1<<7) #define SPIFFS_CACHE_PAGE_SIZE(fs) \ (sizeof(spiffs_cache_page) + SPIFFS_CFG_LOG_PAGE_SZ(fs)) #define spiffs_get_cache(fs) \ ((spiffs_cache *)((fs)->cache)) #define spiffs_get_cache_page_hdr(fs, c, ix) \ ((spiffs_cache_page *)(&((c)->cpages[(ix) * SPIFFS_CACHE_PAGE_SIZE(fs)]))) #define spiffs_get_cache_page(fs, c, ix) \ ((u8_t *)(&((c)->cpages[(ix) * SPIFFS_CACHE_PAGE_SIZE(fs)])) + sizeof(spiffs_cache_page)) // cache page struct typedef struct { // cache flags u8_t flags; // cache page index u8_t ix; // last access of this cache page u32_t last_access; union { // type read cache struct { // read cache page index spiffs_page_ix pix; }; #if SPIFFS_CACHE_WR // type write cache struct { // write cache spiffs_obj_id obj_id; // offset in cache page u32_t offset; // size of cache page u16_t size; }; #endif }; } spiffs_cache_page; // cache struct typedef struct { u8_t cpage_count; u32_t last_access; u32_t cpage_use_map; u32_t cpage_use_mask; u8_t *cpages; } spiffs_cache; #endif // spiffs nucleus file descriptor typedef struct { // the filesystem of this descriptor spiffs *fs; // number of file descriptor - if 0, the file descriptor is closed spiffs_file file_nbr; // object id - if SPIFFS_OBJ_ID_ERASED, the file was deleted spiffs_obj_id obj_id; // size of the file u32_t size; // cached object index header page index spiffs_page_ix objix_hdr_pix; // cached offset object index page index spiffs_page_ix cursor_objix_pix; // cached offset object index span index spiffs_span_ix cursor_objix_spix; // current absolute offset u32_t offset; // current file descriptor offset (cached) u32_t fdoffset; // fd flags spiffs_flags flags; #if SPIFFS_CACHE_WR spiffs_cache_page *cache_page; #endif #if SPIFFS_TEMPORAL_FD_CACHE // djb2 hash of filename u32_t name_hash; // hit score (score == 0 indicates never used fd) u16_t score; #endif #if SPIFFS_IX_MAP // spiffs index map, if 0 it means unmapped spiffs_ix_map *ix_map; #endif } spiffs_fd; // object structs // page header, part of each page except object lookup pages // NB: this is always aligned when the data page is an object index, // as in this case struct spiffs_page_object_ix is used typedef struct SPIFFS_PACKED { // object id spiffs_obj_id obj_id; // object span index spiffs_span_ix span_ix; // flags u8_t flags; } spiffs_page_header; // object index header page header typedef struct SPIFFS_PACKED #if SPIFFS_ALIGNED_OBJECT_INDEX_TABLES __attribute(( aligned(sizeof(spiffs_page_ix)) )) #endif { // common page header spiffs_page_header p_hdr; // alignment u8_t _align0[4 - ((sizeof(spiffs_page_header)&3)==0 ? 4 : (sizeof(spiffs_page_header)&3))]; // size of object u32_t size; // type of object spiffs_obj_type type; u8_t _align1[4 - ((sizeof(spiffs_obj_type)&3)==0 ? 4 : (sizeof(spiffs_obj_type)&3))]; // name of object u8_t name[SPIFFS_OBJ_NAME_LEN]; #if SPIFFS_OBJ_META_LEN // metadata. not interpreted by SPIFFS in any way. u8_t meta[SPIFFS_OBJ_META_LEN]; #endif } spiffs_page_object_ix_header; // object index page header typedef struct SPIFFS_PACKED { spiffs_page_header p_hdr; u8_t _align[4 - ((sizeof(spiffs_page_header)&3)==0 ? 4 : (sizeof(spiffs_page_header)&3))]; } spiffs_page_object_ix; // callback func for object lookup visitor typedef s32_t (*spiffs_visitor_f)(spiffs *fs, spiffs_obj_id id, spiffs_block_ix bix, int ix_entry, const void *user_const_p, void *user_var_p); #if SPIFFS_CACHE #define _spiffs_rd(fs, op, fh, addr, len, dst) \ spiffs_phys_rd((fs), (op), (fh), (addr), (len), (dst)) #define _spiffs_wr(fs, op, fh, addr, len, src) \ spiffs_phys_wr((fs), (op), (fh), (addr), (len), (src)) #else #define _spiffs_rd(fs, op, fh, addr, len, dst) \ spiffs_phys_rd((fs), (addr), (len), (dst)) #define _spiffs_wr(fs, op, fh, addr, len, src) \ spiffs_phys_wr((fs), (addr), (len), (src)) #endif #ifndef MIN #define MIN(a,b) ((a) < (b) ? (a) : (b)) #endif #ifndef MAX #define MAX(a,b) ((a) > (b) ? (a) : (b)) #endif // --------------- s32_t spiffs_phys_rd( spiffs *fs, #if SPIFFS_CACHE u8_t op, spiffs_file fh, #endif u32_t addr, u32_t len, u8_t *dst); s32_t spiffs_phys_wr( spiffs *fs, #if SPIFFS_CACHE u8_t op, spiffs_file fh, #endif u32_t addr, u32_t len, u8_t *src); s32_t spiffs_phys_cpy( spiffs *fs, spiffs_file fh, u32_t dst, u32_t src, u32_t len); s32_t spiffs_phys_count_free_blocks( spiffs *fs); s32_t spiffs_obj_lu_find_entry_visitor( spiffs *fs, spiffs_block_ix starting_block, int starting_lu_entry, u8_t flags, spiffs_obj_id obj_id, spiffs_visitor_f v, const void *user_const_p, void *user_var_p, spiffs_block_ix *block_ix, int *lu_entry); s32_t spiffs_erase_block( spiffs *fs, spiffs_block_ix bix); #if SPIFFS_USE_MAGIC && SPIFFS_USE_MAGIC_LENGTH s32_t spiffs_probe( spiffs_config *cfg); #endif // SPIFFS_USE_MAGIC && SPIFFS_USE_MAGIC_LENGTH // --------------- s32_t spiffs_obj_lu_scan( spiffs *fs); s32_t spiffs_obj_lu_find_free_obj_id( spiffs *fs, spiffs_obj_id *obj_id, const u8_t *conflicting_name); s32_t spiffs_obj_lu_find_free( spiffs *fs, spiffs_block_ix starting_block, int starting_lu_entry, spiffs_block_ix *block_ix, int *lu_entry); s32_t spiffs_obj_lu_find_id( spiffs *fs, spiffs_block_ix starting_block, int starting_lu_entry, spiffs_obj_id obj_id, spiffs_block_ix *block_ix, int *lu_entry); s32_t spiffs_obj_lu_find_id_and_span( spiffs *fs, spiffs_obj_id obj_id, spiffs_span_ix spix, spiffs_page_ix exclusion_pix, spiffs_page_ix *pix); s32_t spiffs_obj_lu_find_id_and_span_by_phdr( spiffs *fs, spiffs_obj_id obj_id, spiffs_span_ix spix, spiffs_page_ix exclusion_pix, spiffs_page_ix *pix); // --------------- s32_t spiffs_page_allocate_data( spiffs *fs, spiffs_obj_id obj_id, spiffs_page_header *ph, u8_t *data, u32_t len, u32_t page_offs, u8_t finalize, spiffs_page_ix *pix); s32_t spiffs_page_move( spiffs *fs, spiffs_file fh, u8_t *page_data, spiffs_obj_id obj_id, spiffs_page_header *page_hdr, spiffs_page_ix src_pix, spiffs_page_ix *dst_pix); s32_t spiffs_page_delete( spiffs *fs, spiffs_page_ix pix); // --------------- s32_t spiffs_object_create( spiffs *fs, spiffs_obj_id obj_id, const u8_t name[], const u8_t meta[], spiffs_obj_type type, spiffs_page_ix *objix_hdr_pix); s32_t spiffs_object_update_index_hdr( spiffs *fs, spiffs_fd *fd, spiffs_obj_id obj_id, spiffs_page_ix objix_hdr_pix, u8_t *new_objix_hdr_data, const u8_t name[], const u8_t meta[], u32_t size, spiffs_page_ix *new_pix); #if SPIFFS_IX_MAP s32_t spiffs_populate_ix_map( spiffs *fs, spiffs_fd *fd, u32_t vec_entry_start, u32_t vec_entry_end); #endif void spiffs_cb_object_event( spiffs *fs, spiffs_page_object_ix *objix, int ev, spiffs_obj_id obj_id, spiffs_span_ix spix, spiffs_page_ix new_pix, u32_t new_size); s32_t spiffs_object_open_by_id( spiffs *fs, spiffs_obj_id obj_id, spiffs_fd *f, spiffs_flags flags, spiffs_mode mode); s32_t spiffs_object_open_by_page( spiffs *fs, spiffs_page_ix pix, spiffs_fd *f, spiffs_flags flags, spiffs_mode mode); s32_t spiffs_object_append( spiffs_fd *fd, u32_t offset, u8_t *data, u32_t len); s32_t spiffs_object_modify( spiffs_fd *fd, u32_t offset, u8_t *data, u32_t len); s32_t spiffs_object_read( spiffs_fd *fd, u32_t offset, u32_t len, u8_t *dst); s32_t spiffs_object_truncate( spiffs_fd *fd, u32_t new_len, u8_t remove_object); s32_t spiffs_object_find_object_index_header_by_name( spiffs *fs, const u8_t name[SPIFFS_OBJ_NAME_LEN], spiffs_page_ix *pix); // --------------- s32_t spiffs_gc_check( spiffs *fs, u32_t len); s32_t spiffs_gc_erase_page_stats( spiffs *fs, spiffs_block_ix bix); s32_t spiffs_gc_find_candidate( spiffs *fs, spiffs_block_ix **block_candidate, int *candidate_count, char fs_crammed); s32_t spiffs_gc_clean( spiffs *fs, spiffs_block_ix bix); s32_t spiffs_gc_quick( spiffs *fs, u16_t max_free_pages); // --------------- s32_t spiffs_fd_find_new( spiffs *fs, spiffs_fd **fd, const char *name); s32_t spiffs_fd_return( spiffs *fs, spiffs_file f); s32_t spiffs_fd_get( spiffs *fs, spiffs_file f, spiffs_fd **fd); #if SPIFFS_TEMPORAL_FD_CACHE void spiffs_fd_temporal_cache_rehash( spiffs *fs, const char *old_path, const char *new_path); #endif #if SPIFFS_CACHE void spiffs_cache_init( spiffs *fs); void spiffs_cache_drop_page( spiffs *fs, spiffs_page_ix pix); #if SPIFFS_CACHE_WR spiffs_cache_page *spiffs_cache_page_allocate_by_fd( spiffs *fs, spiffs_fd *fd); void spiffs_cache_fd_release( spiffs *fs, spiffs_cache_page *cp); spiffs_cache_page *spiffs_cache_page_get_by_fd( spiffs *fs, spiffs_fd *fd); #endif #endif s32_t spiffs_lookup_consistency_check( spiffs *fs, u8_t check_all_objects); s32_t spiffs_page_consistency_check( spiffs *fs); s32_t spiffs_object_index_consistency_check( spiffs *fs); // memcpy macro, // checked in test builds, otherwise plain memcpy (unless already defined) #ifdef _SPIFFS_TEST #define _SPIFFS_MEMCPY(__d, __s, __l) do { \ intptr_t __a1 = (intptr_t)((u8_t*)(__s)); \ intptr_t __a2 = (intptr_t)((u8_t*)(__s)+(__l)); \ intptr_t __b1 = (intptr_t)((u8_t*)(__d)); \ intptr_t __b2 = (intptr_t)((u8_t*)(__d)+(__l)); \ if (__a1 <= __b2 && __b1 <= __a2) { \ printf("FATAL OVERLAP: memcpy from %lx..%lx to %lx..%lx\n", __a1, __a2, __b1, __b2); \ ERREXIT(); \ } \ memcpy((__d),(__s),(__l)); \ } while (0) #else #ifndef _SPIFFS_MEMCPY #define _SPIFFS_MEMCPY(__d, __s, __l) do{memcpy((__d),(__s),(__l));}while(0) #endif #endif //_SPIFFS_TEST #endif /* SPIFFS_NUCLEUS_H_ */ ================================================ FILE: Huawei_LiteOS/components/fs/vfs/los_vfs.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include #include #include #include #include "los_config.h" #include "los_mux.h" #include "fs/sys/errno.h" #include "fs/sys/fcntl.h" #include "fs/los_vfs.h" #if (LOSCFG_ENABLE_VFS == YES) struct file files [LOS_MAX_FILES]; UINT32 fs_mutex = LOS_ERRNO_MUX_PTR_NULL; struct mount_point *mount_points = NULL; struct file_system *file_systems = NULL; static int _file_2_fd (struct file *file) { return file - files; } static struct file *_fd_2_file (int fd) { return &files [fd]; } static struct file *los_file_get (void) { int i; /* protected by fs_mutex */ for (i = 0; i < LOS_MAX_FILES; i++) { if (files[i].f_status == FILE_STATUS_NOT_USED) { files[i].f_status = FILE_STATUS_INITING; return &files[i]; } } return NULL; } static void los_file_put(struct file *file) { file->f_flags = 0; file->f_fops = NULL; file->f_data = NULL; file->f_mp = NULL; file->f_offset = 0; file->f_owner = (UINT32) - 1; file->f_status = FILE_STATUS_NOT_USED; } struct mount_point *los_mp_find (const char *path, const char **path_in_mp) { struct mount_point *mp = mount_points; struct mount_point *best_mp = NULL; int best_matches = 0; if (path == NULL) { return NULL; } if (path_in_mp != NULL) { *path_in_mp = NULL; } while (mp != NULL) { const char *m_path = mp->m_path; /* mount point path */ const char *i_path = path; /* input path */ int matches = 0; const char *t; do { while (*m_path == '/') m_path++; while (*i_path == '/') i_path++; t = strchr (m_path, '/'); if (t == NULL) { /* * m_path now is as follows: * 1) string like "abc" * 2) empty string "\0" * if it is empty string, means current mp matched */ t = strchr (m_path, '\0'); if (t == m_path) { break; } } if (strncmp (m_path, i_path, t - m_path) != 0) { goto next; /* this mount point do not match, check next */ } /* * if m_path is "abc", i_path maybe: * 1) "abc" * 2) "abc/" * 3) "abcd..." * if it is not 1) or 2), this mp does not match, just goto next one */ i_path += (t - m_path); if ((*i_path != '\0') && (*i_path != '/')) { goto next; } matches += (t - m_path); m_path += (t - m_path); } while (*m_path != '\0'); if (matches > best_matches) { best_matches = matches; best_mp = mp; while (*i_path == '/') i_path++; if (path_in_mp != NULL) { *path_in_mp = i_path; } } next: mp = mp->m_next; } return best_mp; } int los_open (const char *path, int flags) { struct file *file = NULL; int fd = -1; const char *path_in_mp = NULL; struct mount_point *mp; if (path == NULL) { VFS_ERRNO_SET (EINVAL); return fd; } /* can not open dir */ if (path [strlen (path) - 1] == '/') { VFS_ERRNO_SET (EINVAL); return fd; } /* prevent fs/mp being removed while opening */ if (LOS_OK != LOS_MuxPend (fs_mutex, LOS_WAIT_FOREVER)) { VFS_ERRNO_SET (EAGAIN); return fd; } file = los_file_get (); if (file == NULL) { VFS_ERRNO_SET (ENFILE); goto err_post_exit; } mp = los_mp_find (path, &path_in_mp); if ((mp == NULL) || (path_in_mp == NULL) || (*path_in_mp == '\0') || (mp->m_fs->fs_fops->open == NULL)) { VFS_ERRNO_SET (ENOENT); goto err_post_exit; }; if (LOS_OK != LOS_MuxPend (mp->m_mutex, LOS_WAIT_FOREVER)) { VFS_ERRNO_SET (EAGAIN); goto err_post_exit; } LOS_MuxPost (fs_mutex); file->f_flags = flags; file->f_offset = 0; file->f_data = NULL; file->f_fops = mp->m_fs->fs_fops; file->f_mp = mp; file->f_owner = LOS_CurTaskIDGet (); if (file->f_fops->open (file, path_in_mp, flags) == 0) { mp->m_refs++; fd = _file_2_fd (file); file->f_status = FILE_STATUS_READY; /* file now ready to use */ } else { los_file_put (file); } LOS_MuxPost (mp->m_mutex); return fd; err_post_exit: LOS_MuxPost (fs_mutex); if ((fd < 0) && (file != NULL)) { los_file_put (file); } return fd; } /* attach to a file and then set new status */ static struct file *_los_attach_file (int fd, UINT32 status) { struct file *file = NULL; if ((fd < 0) || (fd >= LOS_MAX_FILES)) { VFS_ERRNO_SET (EBADF); return file; } file = _fd_2_file (fd); /* * Prevent file closed after the checking of: * * if (file->f_status == FILE_STATUS_READY) * * Because our files are not privated to one task, it may be operated * by every task. * So we should take the mutex of current mount point before operating it, * but for now we don't know if this file is valid (FILE_STATUS_READY), if * this file is not valid, the f_mp may be incorrect. so * we must check the status first, but this file may be closed/removed * after the checking if the senquence is not correct. * * Consider the following code: * * los_attach_file (...) * { * if (file->f_status == FILE_STATUS_READY) * { * while (LOS_MuxPend (file->f_mp->m_mutex, LOS_WAIT_FOREVER) != LOS_OK); * * return file; * } * } * * It is not safe: * * If current task is interrupted by an IRQ just after the checking and then * a new task is swapped in and the new task just closed this file. * * So is acquire first and then check if it is valid: if not, just * return NULL (which means fail); If yes, the mutex for current mount point * is qcquired. And the close operation will also set task to * FILE_STATUS_CLOSING to prevent other tasks operate on this file (and also * prevent other tasks pend on the mutex of this mount point for this file). * At last is released. And return the file handle (struct file *). * * As this logic used in almost all the operation routines, this routine is * made to reduce the redundant code. */ while (LOS_MuxPend (fs_mutex, LOS_WAIT_FOREVER) != LOS_OK); if (file->f_status == FILE_STATUS_READY) { while (LOS_MuxPend (file->f_mp->m_mutex, LOS_WAIT_FOREVER) != LOS_OK); if (status != FILE_STATUS_READY) { file->f_status = status; } } else { VFS_ERRNO_SET (EBADF); file = NULL; } LOS_MuxPost (fs_mutex); return file; } static struct file *los_attach_file (int fd) { return _los_attach_file (fd, FILE_STATUS_READY); } static struct file *los_attach_file_with_status (int fd, int status) { return _los_attach_file (fd, status); } static UINT32 los_detach_file (struct file *file) { return LOS_MuxPost (file->f_mp->m_mutex); } int los_close (int fd) { struct file *file; int ret = -1; file = los_attach_file_with_status (fd, FILE_STATUS_CLOSING); if (file == NULL) { return ret; } if (file->f_fops->close != NULL) { ret = file->f_fops->close (file); } else { VFS_ERRNO_SET (ENOTSUP); } if (0 == ret) { file->f_mp->m_refs--; } los_detach_file (file); los_file_put (file); return ret; } ssize_t los_read (int fd, char *buff, size_t bytes) { struct file *file; ssize_t ret = (ssize_t) - 1; if (buff == NULL || bytes == 0) { VFS_ERRNO_SET (EINVAL); return ret; } file = los_attach_file (fd); if (file == NULL) { return ret; } if ((file->f_flags & O_ACCMODE) == O_WRONLY) { VFS_ERRNO_SET (EACCES); } else if (file->f_fops->read != NULL) { ret = file->f_fops->read (file, buff, bytes); } else { VFS_ERRNO_SET (ENOTSUP); } /* else ret will be -1 */ los_detach_file (file); return ret; } ssize_t los_write (int fd, const void *buff, size_t bytes) { struct file *file; ssize_t ret = -1; if (buff == NULL || bytes == 0) { VFS_ERRNO_SET (EINVAL); return ret; } file = los_attach_file (fd); if (file == NULL) { return ret; } if ((file->f_flags & O_ACCMODE) == O_RDONLY) { VFS_ERRNO_SET (EACCES); } else if (file->f_fops->write != NULL) { ret = file->f_fops->write (file, buff, bytes); } else { VFS_ERRNO_SET (ENOTSUP); } /* else ret will be -1 */ los_detach_file (file); return ret; } off_t los_lseek (int fd, off_t off, int whence) { struct file *file; off_t ret = -1; file = los_attach_file (fd); if (file == NULL) { return ret; } if (file->f_fops->lseek == NULL) { ret = file->f_offset; } else { ret = file->f_fops->lseek (file, off, whence); } los_detach_file (file); return ret; } int los_stat (const char *path, struct stat *stat) { struct mount_point *mp = NULL; const char *path_in_mp = NULL; int ret = -1; if (path == NULL || stat == NULL) { VFS_ERRNO_SET (EINVAL); return ret; } if (LOS_OK != LOS_MuxPend (fs_mutex, LOS_WAIT_FOREVER)) { VFS_ERRNO_SET (EAGAIN); return ret; } mp = los_mp_find (path, &path_in_mp); if ((mp == NULL) || (path_in_mp == NULL) || (*path_in_mp == '\0')) { VFS_ERRNO_SET (ENOENT); LOS_MuxPost (fs_mutex); return ret; } if (mp->m_fs->fs_fops->stat != NULL) { ret = mp->m_fs->fs_fops->stat (mp, path_in_mp, stat); } else { VFS_ERRNO_SET (ENOTSUP); } LOS_MuxPost (fs_mutex); return ret; } int los_unlink (const char *path) { struct mount_point *mp; const char *path_in_mp = NULL; int ret = -1; if (path == NULL) { VFS_ERRNO_SET (EINVAL); return ret; } LOS_MuxPend (fs_mutex, LOS_WAIT_FOREVER); /* prevent the file open/rename */ mp = los_mp_find (path, &path_in_mp); if ((mp == NULL) || (path_in_mp == NULL) || (*path_in_mp == '\0') || (mp->m_fs->fs_fops->unlink == NULL)) { VFS_ERRNO_SET (ENOENT); goto out; } ret = mp->m_fs->fs_fops->unlink (mp, path_in_mp); out: LOS_MuxPost (fs_mutex); return ret; } int los_rename (const char *old, const char *new) { struct mount_point *mp_old; struct mount_point *mp_new; const char *path_in_mp_old = NULL; const char *path_in_mp_new = NULL; int ret = -1; if (old == NULL || new == NULL) { VFS_ERRNO_SET (EINVAL); return ret; } LOS_MuxPend (fs_mutex, LOS_WAIT_FOREVER); /* prevent file open/unlink */ mp_old = los_mp_find (old, &path_in_mp_old); if(path_in_mp_old == NULL) { VFS_ERRNO_SET (EINVAL); goto out; } if ((mp_old == NULL) || (*path_in_mp_old == '\0') || (mp_old->m_fs->fs_fops->unlink == NULL)) { VFS_ERRNO_SET (EINVAL); goto out; } mp_new = los_mp_find (new, &path_in_mp_new); if ((mp_new == NULL) || (path_in_mp_new == NULL) || (*path_in_mp_new == '\0') || (mp_new->m_fs->fs_fops->unlink == NULL)) { VFS_ERRNO_SET (EINVAL); goto out; } if (mp_old != mp_new) { VFS_ERRNO_SET (EXDEV); goto out; } if (mp_old->m_fs->fs_fops->rename != NULL) { ret = mp_old->m_fs->fs_fops->rename (mp_old, path_in_mp_old, path_in_mp_new); } else { VFS_ERRNO_SET (ENOTSUP); } out: LOS_MuxPost (fs_mutex); return ret; } int los_ioctl (int fd, int func, ...) { va_list ap; unsigned long arg; struct file *file; int ret = -1; va_start (ap, func); arg = va_arg (ap, unsigned long); va_end (ap); file = los_attach_file (fd); if (file == NULL) { return ret; } if (file->f_fops->ioctl != NULL) { ret = file->f_fops->ioctl (file, func, arg); } else { VFS_ERRNO_SET (ENOTSUP); } los_detach_file (file); return ret; } int los_sync (int fd) { struct file *file; int ret = -1; file = los_attach_file (fd); if (file == NULL) { return ret; } if (file->f_fops->sync != NULL) { ret = file->f_fops->sync (file); } else { VFS_ERRNO_SET (ENOTSUP); } los_detach_file (file); return ret; } struct dir *los_opendir (const char *path) { struct mount_point *mp; const char *path_in_mp = NULL; struct dir *dir = NULL; int ret = -1; if (path == NULL) { VFS_ERRNO_SET (EINVAL); return NULL; } dir = (struct dir *) malloc (sizeof (struct dir)); if (dir == NULL) { PRINT_ERR ("fail to malloc memory in VFS, is needed," "make sure it is added\n"); VFS_ERRNO_SET (ENOMEM); return NULL; } if (LOS_OK != LOS_MuxPend (fs_mutex, LOS_WAIT_FOREVER)) { VFS_ERRNO_SET (EAGAIN); free (dir); return NULL; } mp = los_mp_find (path, &path_in_mp); if (mp == NULL || path_in_mp == NULL) { VFS_ERRNO_SET (ENOENT); LOS_MuxPost (fs_mutex); free (dir); return NULL; } ret = LOS_MuxPend (mp->m_mutex, LOS_WAIT_FOREVER); LOS_MuxPost (fs_mutex); if (ret != LOS_OK) { VFS_ERRNO_SET (EAGAIN); free (dir); return NULL; } if (mp->m_fs->fs_fops->opendir == NULL) { VFS_ERRNO_SET (ENOTSUP); LOS_MuxPost (mp->m_mutex); free (dir); return NULL; } dir->d_mp = mp; dir->d_offset = 0; ret = mp->m_fs->fs_fops->opendir (dir, path_in_mp); if (ret == 0) { mp->m_refs++; } else { free (dir); dir = NULL; } LOS_MuxPost (mp->m_mutex); return dir; } struct dirent *los_readdir (struct dir *dir) { struct mount_point *mp; struct dirent *ret = NULL; if (dir == NULL) { VFS_ERRNO_SET (EINVAL); return NULL; } mp = dir->d_mp; if (LOS_OK != LOS_MuxPend (mp->m_mutex, LOS_WAIT_FOREVER)) { VFS_ERRNO_SET (EAGAIN); return NULL; } if (dir->d_mp->m_fs->fs_fops->readdir != NULL) { if (dir->d_mp->m_fs->fs_fops->readdir (dir, &dir->d_dent) == 0) { ret = &dir->d_dent; } else { VFS_ERRNO_SET (EBADF); } } else { VFS_ERRNO_SET (ENOTSUP); } LOS_MuxPost (mp->m_mutex); return ret; } int los_closedir (struct dir *dir) { struct mount_point *mp; int ret = -1; if (dir == NULL) { VFS_ERRNO_SET (EBADF); return -1; } mp = dir->d_mp; if (LOS_OK != LOS_MuxPend (mp->m_mutex, LOS_WAIT_FOREVER)) { VFS_ERRNO_SET (EAGAIN); return -1; } if (dir->d_mp->m_fs->fs_fops->closedir != NULL) { ret = dir->d_mp->m_fs->fs_fops->closedir (dir); } else { VFS_ERRNO_SET (ENOTSUP); } if (ret == 0) { free (dir); mp->m_refs--; } else { VFS_ERRNO_SET (EBADF); } LOS_MuxPost (mp->m_mutex); return ret; } int los_mkdir (const char *path, int mode) { struct mount_point *mp; const char *path_in_mp = NULL; int ret = -1; (void) mode; if (path == NULL) { VFS_ERRNO_SET (EINVAL); return -1; } if (LOS_OK != LOS_MuxPend (fs_mutex, LOS_WAIT_FOREVER)) { VFS_ERRNO_SET (EAGAIN); return -1; } mp = los_mp_find (path, &path_in_mp); if ((mp == NULL) || (path_in_mp == NULL) || (*path_in_mp == '\0')) { VFS_ERRNO_SET (ENOENT); LOS_MuxPost (fs_mutex); return -1; } ret = LOS_MuxPend (mp->m_mutex, LOS_WAIT_FOREVER); LOS_MuxPost (fs_mutex); if (ret != LOS_OK) { VFS_ERRNO_SET (EAGAIN); return -1; } if (mp->m_fs->fs_fops->mkdir != NULL) { ret = mp->m_fs->fs_fops->mkdir (mp, path_in_mp); } else { VFS_ERRNO_SET (ENOTSUP); ret = -1; } LOS_MuxPost (mp->m_mutex); return ret; } static int los_fs_name_check (const char *name) { char ch; int len = 0; do { ch = *name++; if (ch == '\0') { break; } if ((('a' <= ch) && (ch <= 'z')) || (('A' <= ch) && (ch <= 'Z')) || (('0' <= ch) && (ch <= '9')) || (ch == '_') || (ch == '-')) { len++; if (len == LOS_FS_MAX_NAME_LEN) { return LOS_NOK; } continue; } return LOS_NOK; } while (1); return len == 0 ? LOS_NOK : LOS_OK; } static struct file_system *los_fs_find (const char *name) { struct file_system *fs; for (fs = file_systems; fs != NULL; fs = fs->fs_next) { if (strncmp(fs->fs_name, name, LOS_FS_MAX_NAME_LEN) == 0) { break; } } return fs; } int los_fs_register (struct file_system *fs) { if ((fs == NULL) || (fs->fs_fops == NULL) || (fs->fs_fops->open == NULL)) { return LOS_NOK; } if (los_fs_name_check (fs->fs_name) != LOS_OK) { return LOS_NOK; } if (LOS_MuxPend (fs_mutex, LOS_WAIT_FOREVER) != LOS_OK) { return LOS_NOK; } if (los_fs_find (fs->fs_name) != NULL) { LOS_MuxPost (fs_mutex); return LOS_NOK; } fs->fs_next = file_systems; file_systems = fs; LOS_MuxPost (fs_mutex); return LOS_OK; } int los_fs_unregister (struct file_system *fs) { struct file_system *prev; int ret = LOS_OK; if (fs == NULL) { return LOS_NOK; } if (LOS_MuxPend (fs_mutex, LOS_WAIT_FOREVER) != LOS_OK) { return LOS_NOK; } if (fs->fs_refs > 0) { goto out; } if (file_systems == fs) { file_systems = fs->fs_next; goto out; } prev = file_systems; while (prev != NULL) { if (prev->fs_next == fs) { break; } prev = prev->fs_next; } if (prev == NULL) { ret = LOS_NOK; } else { prev->fs_next = fs->fs_next; } out: LOS_MuxPost (fs_mutex); return ret; } int los_fs_mount (const char *fsname, const char *path, void *data) { struct file_system *fs; struct mount_point *mp; const char *tmp = NULL; if (fsname == NULL || path == NULL || path [0] == '\0' || path [0] != '/') { return LOS_NOK; } LOS_MuxPend (fs_mutex, LOS_WAIT_FOREVER); fs = los_fs_find (fsname); if (fs == NULL) { goto err_post_exit; } mp = los_mp_find (path, &tmp); if ((mp != NULL) && (tmp != NULL) && (*tmp == '\0')) { goto err_post_exit; } mp = malloc (sizeof (struct mount_point)); if (mp == NULL) { PRINT_ERR ("fail to malloc memory in VFS, is needed," "make sure it is added\n"); goto err_post_exit; } memset (mp, 0, sizeof (struct mount_point)); mp->m_fs = fs; mp->m_path = path; mp->m_data = data; mp->m_refs = 0; if (LOS_OK != LOS_MuxCreate (&mp->m_mutex)) { goto err_free_exit; } mp->m_next = mount_points; mount_points = mp; fs->fs_refs++; LOS_MuxPost (fs_mutex); return LOS_OK; err_free_exit: free (mp); err_post_exit: LOS_MuxPost (fs_mutex); return LOS_NOK; } int los_fs_unmount (const char *path) { struct mount_point *mp; struct mount_point *prev; const char *tmp = NULL; int ret = LOS_NOK; if (path == NULL) { return ret; } LOS_MuxPend (fs_mutex, LOS_WAIT_FOREVER); mp = los_mp_find (path, &tmp); if ((mp == NULL) || (tmp == NULL) || (*tmp != '\0') || (mp->m_refs != 0)) { goto post_exit; } if (mount_points == mp) { mount_points = mp->m_next; } else { for (prev = mount_points; prev != NULL; prev = prev->m_next) { if (prev->m_next != mp) { continue; } prev->m_next = mp->m_next; break; } } LOS_MuxDelete (mp->m_mutex); mp->m_fs->fs_refs--; free (mp); ret = LOS_OK; post_exit: LOS_MuxPost (fs_mutex); return ret; } int los_vfs_init (void) { if (fs_mutex != LOS_ERRNO_MUX_PTR_NULL) { return LOS_OK; } if (LOS_MuxCreate (&fs_mutex) == LOS_OK) { return LOS_OK; } PRINT_ERR ("los_vfs_init fail!\n"); return LOS_NOK; } #ifndef WITH_LINUX #define MAP_TO_POSIX_RET(ret) ( (ret) < 0 ? -1 : (ret) ) int open (const char *path, int flags,...) { int ret = los_open (path, flags); return MAP_TO_POSIX_RET(ret); } int close (int fd) { int ret = los_close (fd); return MAP_TO_POSIX_RET(ret); } ssize_t read (int fd, void *buff, size_t bytes) { ssize_t ret = los_read (fd, buff, bytes); return MAP_TO_POSIX_RET(ret); } ssize_t write (int fd, const void *buff, size_t bytes) { ssize_t ret = los_write (fd, buff, bytes); return MAP_TO_POSIX_RET(ret); } off_t lseek (int fd, off_t off, int whence) { off_t ret = los_lseek (fd, off, whence); return MAP_TO_POSIX_RET(ret); } int stat (const char *path, struct stat *stat) { int ret = los_stat (path, stat); return MAP_TO_POSIX_RET(ret); } int unlink (const char *path) { int ret = los_unlink (path); return MAP_TO_POSIX_RET(ret); } int rename (const char *oldpath, const char *newpath) { int ret = los_rename (oldpath, newpath); return MAP_TO_POSIX_RET(ret); } int fsync (int fd) { int ret = los_sync (fd); return MAP_TO_POSIX_RET(ret); } struct dir *opendir (const char *path) { return los_opendir (path); } struct dirent *readdir (struct dir *dir) { return los_readdir (dir); } int closedir (struct dir *dir) { int ret = los_closedir (dir); return MAP_TO_POSIX_RET(ret); } int mkdir (const char *path, int mode) { int ret = los_mkdir (path, mode); return MAP_TO_POSIX_RET(ret); } #endif #endif ================================================ FILE: Huawei_LiteOS/components/lib/cJSON/cJSON.c ================================================ /* Copyright (c) 2009-2017 Dave Gamble and cJSON contributors Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* cJSON */ /* JSON parser in C. */ /* disable warnings about old C89 functions in MSVC */ #if !defined(_CRT_SECURE_NO_DEPRECATE) && defined(_MSC_VER) #define _CRT_SECURE_NO_DEPRECATE #endif #ifdef __GNUC__ #pragma GCC visibility push(default) #endif #if defined(_MSC_VER) #pragma warning (push) /* disable warning about single line comments in system headers */ #pragma warning (disable : 4001) #endif #include #include #include #include #include #include #ifdef ENABLE_LOCALES #include #endif #if defined(_MSC_VER) #pragma warning (pop) #endif #ifdef __GNUC__ #pragma GCC visibility pop #endif #include "cJSON.h" /* define our own boolean type */ #define true ((cJSON_bool)1) #define false ((cJSON_bool)0) typedef struct { const unsigned char *json; size_t position; } error; static error global_error = { NULL, 0 }; CJSON_PUBLIC(const char *) cJSON_GetErrorPtr(void) { return (const char*) (global_error.json + global_error.position); } CJSON_PUBLIC(char *) cJSON_GetStringValue(cJSON *item) { if (!cJSON_IsString(item)) { return NULL; } return item->valuestring; } /* This is a safeguard to prevent copy-pasters from using incompatible C and header files */ #if (CJSON_VERSION_MAJOR != 1) || (CJSON_VERSION_MINOR != 7) || (CJSON_VERSION_PATCH != 8) #error cJSON.h and cJSON.c have different versions. Make sure that both have the same. #endif CJSON_PUBLIC(const char*) cJSON_Version(void) { static char version[15]; sprintf(version, "%i.%i.%i", CJSON_VERSION_MAJOR, CJSON_VERSION_MINOR, CJSON_VERSION_PATCH); return version; } /* Case insensitive string comparison, doesn't consider two NULL pointers equal though */ static int case_insensitive_strcmp(const unsigned char *string1, const unsigned char *string2) { if ((string1 == NULL) || (string2 == NULL)) { return 1; } if (string1 == string2) { return 0; } for(; tolower(*string1) == tolower(*string2); (void)string1++, string2++) { if (*string1 == '\0') { return 0; } } return tolower(*string1) - tolower(*string2); } typedef struct internal_hooks { void *(CJSON_CDECL *allocate)(size_t size); void (CJSON_CDECL *deallocate)(void *pointer); void *(CJSON_CDECL *reallocate)(void *pointer, size_t size); } internal_hooks; #if defined(_MSC_VER) /* work around MSVC error C2322: '...' address of dillimport '...' is not static */ static void * CJSON_CDECL internal_malloc(size_t size) { return malloc(size); } static void CJSON_CDECL internal_free(void *pointer) { free(pointer); } static void * CJSON_CDECL internal_realloc(void *pointer, size_t size) { return realloc(pointer, size); } #else #define internal_malloc malloc #define internal_free free #define internal_realloc realloc #endif static internal_hooks global_hooks = { internal_malloc, internal_free, internal_realloc }; static unsigned char* cJSON_strdup(const unsigned char* string, const internal_hooks * const hooks) { size_t length = 0; unsigned char *copy = NULL; if (string == NULL) { return NULL; } length = strlen((const char*)string) + sizeof(""); copy = (unsigned char*)hooks->allocate(length); if (copy == NULL) { return NULL; } memcpy(copy, string, length); return copy; } CJSON_PUBLIC(void) cJSON_InitHooks(cJSON_Hooks* hooks) { if (hooks == NULL) { /* Reset hooks */ global_hooks.allocate = malloc; global_hooks.deallocate = free; global_hooks.reallocate = realloc; return; } global_hooks.allocate = malloc; if (hooks->malloc_fn != NULL) { global_hooks.allocate = hooks->malloc_fn; } global_hooks.deallocate = free; if (hooks->free_fn != NULL) { global_hooks.deallocate = hooks->free_fn; } /* use realloc only if both free and malloc are used */ global_hooks.reallocate = NULL; if ((global_hooks.allocate == malloc) && (global_hooks.deallocate == free)) { global_hooks.reallocate = realloc; } } /* Internal constructor. */ static cJSON *cJSON_New_Item(const internal_hooks * const hooks) { cJSON* node = (cJSON*)hooks->allocate(sizeof(cJSON)); if (node) { memset(node, '\0', sizeof(cJSON)); } return node; } /* Delete a cJSON structure. */ CJSON_PUBLIC(void) cJSON_Delete(cJSON *item) { cJSON *next = NULL; while (item != NULL) { next = item->next; if (!(item->type & cJSON_IsReference) && (item->child != NULL)) { cJSON_Delete(item->child); } if (!(item->type & cJSON_IsReference) && (item->valuestring != NULL)) { global_hooks.deallocate(item->valuestring); } if (!(item->type & cJSON_StringIsConst) && (item->string != NULL)) { global_hooks.deallocate(item->string); } global_hooks.deallocate(item); item = next; } } /* get the decimal point character of the current locale */ static unsigned char get_decimal_point(void) { #ifdef ENABLE_LOCALES struct lconv *lconv = localeconv(); return (unsigned char) lconv->decimal_point[0]; #else return '.'; #endif } typedef struct { const unsigned char *content; size_t length; size_t offset; size_t depth; /* How deeply nested (in arrays/objects) is the input at the current offset. */ internal_hooks hooks; } parse_buffer; /* check if the given size is left to read in a given parse buffer (starting with 1) */ #define can_read(buffer, size) ((buffer != NULL) && (((buffer)->offset + size) <= (buffer)->length)) /* check if the buffer can be accessed at the given index (starting with 0) */ #define can_access_at_index(buffer, index) ((buffer != NULL) && (((buffer)->offset + index) < (buffer)->length)) #define cannot_access_at_index(buffer, index) (!can_access_at_index(buffer, index)) /* get a pointer to the buffer at the position */ #define buffer_at_offset(buffer) ((buffer)->content + (buffer)->offset) /* Parse the input text to generate a number, and populate the result into item. */ static cJSON_bool parse_number(cJSON * const item, parse_buffer * const input_buffer) { double number = 0; unsigned char *after_end = NULL; unsigned char number_c_string[64]; unsigned char decimal_point = get_decimal_point(); size_t i = 0; if ((input_buffer == NULL) || (input_buffer->content == NULL)) { return false; } /* copy the number into a temporary buffer and replace '.' with the decimal point * of the current locale (for strtod) * This also takes care of '\0' not necessarily being available for marking the end of the input */ for (i = 0; (i < (sizeof(number_c_string) - 1)) && can_access_at_index(input_buffer, i); i++) { switch (buffer_at_offset(input_buffer)[i]) { case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': case '+': case '-': case 'e': case 'E': number_c_string[i] = buffer_at_offset(input_buffer)[i]; break; case '.': number_c_string[i] = decimal_point; break; default: goto loop_end; } } loop_end: number_c_string[i] = '\0'; number = strtod((const char*)number_c_string, (char**)&after_end); if (number_c_string == after_end) { return false; /* parse_error */ } item->valuedouble = number; /* use saturation in case of overflow */ if (number >= INT_MAX) { item->valueint = INT_MAX; } else if (number <= INT_MIN) { item->valueint = INT_MIN; } else { item->valueint = (int)number; } item->type = cJSON_Number; input_buffer->offset += (size_t)(after_end - number_c_string); return true; } /* don't ask me, but the original cJSON_SetNumberValue returns an integer or double */ CJSON_PUBLIC(double) cJSON_SetNumberHelper(cJSON *object, double number) { if (number >= INT_MAX) { object->valueint = INT_MAX; } else if (number <= INT_MIN) { object->valueint = INT_MIN; } else { object->valueint = (int)number; } return object->valuedouble = number; } typedef struct { unsigned char *buffer; size_t length; size_t offset; size_t depth; /* current nesting depth (for formatted printing) */ cJSON_bool noalloc; cJSON_bool format; /* is this print a formatted print */ internal_hooks hooks; } printbuffer; /* realloc printbuffer if necessary to have at least "needed" bytes more */ static unsigned char* ensure(printbuffer * const p, size_t needed) { unsigned char *newbuffer = NULL; size_t newsize = 0; if ((p == NULL) || (p->buffer == NULL)) { return NULL; } if ((p->length > 0) && (p->offset >= p->length)) { /* make sure that offset is valid */ return NULL; } if (needed > INT_MAX) { /* sizes bigger than INT_MAX are currently not supported */ return NULL; } needed += p->offset + 1; if (needed <= p->length) { return p->buffer + p->offset; } if (p->noalloc) { return NULL; } /* calculate new buffer size */ if (needed > (INT_MAX / 2)) { /* overflow of int, use INT_MAX if possible */ if (needed <= INT_MAX) { newsize = INT_MAX; } else { return NULL; } } else { newsize = needed * 2; } if (p->hooks.reallocate != NULL) { /* reallocate with realloc if available */ newbuffer = (unsigned char*)p->hooks.reallocate(p->buffer, newsize); if (newbuffer == NULL) { p->hooks.deallocate(p->buffer); p->length = 0; p->buffer = NULL; return NULL; } } else { /* otherwise reallocate manually */ newbuffer = (unsigned char*)p->hooks.allocate(newsize); if (!newbuffer) { p->hooks.deallocate(p->buffer); p->length = 0; p->buffer = NULL; return NULL; } if (newbuffer) { memcpy(newbuffer, p->buffer, p->offset + 1); } p->hooks.deallocate(p->buffer); } p->length = newsize; p->buffer = newbuffer; return newbuffer + p->offset; } /* calculate the new length of the string in a printbuffer and update the offset */ static void update_offset(printbuffer * const buffer) { const unsigned char *buffer_pointer = NULL; if ((buffer == NULL) || (buffer->buffer == NULL)) { return; } buffer_pointer = buffer->buffer + buffer->offset; buffer->offset += strlen((const char*)buffer_pointer); } /* Render the number nicely from the given item into a string. */ static cJSON_bool print_number(const cJSON * const item, printbuffer * const output_buffer) { unsigned char *output_pointer = NULL; double d = item->valuedouble; int length = 0; size_t i = 0; unsigned char number_buffer[26]; /* temporary buffer to print the number into */ unsigned char decimal_point = get_decimal_point(); double test; if (output_buffer == NULL) { return false; } /* This checks for NaN and Infinity */ if ((d * 0) != 0) { length = sprintf((char*)number_buffer, "null"); } else { /* Try 15 decimal places of precision to avoid nonsignificant nonzero digits */ length = sprintf((char*)number_buffer, "%1.15g", d); /* Check whether the original double can be recovered */ if ((sscanf((char*)number_buffer, "%lg", &test) != 1) || ((double)test != d)) { /* If not, print with 17 decimal places of precision */ length = sprintf((char*)number_buffer, "%1.17g", d); } } /* sprintf failed or buffer overrun occured */ if ((length < 0) || (length > (int)(sizeof(number_buffer) - 1))) { return false; } /* reserve appropriate space in the output */ output_pointer = ensure(output_buffer, (size_t)length + sizeof("")); if (output_pointer == NULL) { return false; } /* copy the printed number to the output and replace locale * dependent decimal point with '.' */ for (i = 0; i < ((size_t)length); i++) { if (number_buffer[i] == decimal_point) { output_pointer[i] = '.'; continue; } output_pointer[i] = number_buffer[i]; } output_pointer[i] = '\0'; output_buffer->offset += (size_t)length; return true; } /* parse 4 digit hexadecimal number */ static unsigned parse_hex4(const unsigned char * const input) { unsigned int h = 0; size_t i = 0; for (i = 0; i < 4; i++) { /* parse digit */ if ((input[i] >= '0') && (input[i] <= '9')) { h += (unsigned int) input[i] - '0'; } else if ((input[i] >= 'A') && (input[i] <= 'F')) { h += (unsigned int) 10 + input[i] - 'A'; } else if ((input[i] >= 'a') && (input[i] <= 'f')) { h += (unsigned int) 10 + input[i] - 'a'; } else /* invalid */ { return 0; } if (i < 3) { /* shift left to make place for the next nibble */ h = h << 4; } } return h; } /* converts a UTF-16 literal to UTF-8 * A literal can be one or two sequences of the form \uXXXX */ static unsigned char utf16_literal_to_utf8(const unsigned char * const input_pointer, const unsigned char * const input_end, unsigned char **output_pointer) { long unsigned int codepoint = 0; unsigned int first_code = 0; const unsigned char *first_sequence = input_pointer; unsigned char utf8_length = 0; unsigned char utf8_position = 0; unsigned char sequence_length = 0; unsigned char first_byte_mark = 0; if ((input_end - first_sequence) < 6) { /* input ends unexpectedly */ goto fail; } /* get the first utf16 sequence */ first_code = parse_hex4(first_sequence + 2); /* check that the code is valid */ if (((first_code >= 0xDC00) && (first_code <= 0xDFFF))) { goto fail; } /* UTF16 surrogate pair */ if ((first_code >= 0xD800) && (first_code <= 0xDBFF)) { const unsigned char *second_sequence = first_sequence + 6; unsigned int second_code = 0; sequence_length = 12; /* \uXXXX\uXXXX */ if ((input_end - second_sequence) < 6) { /* input ends unexpectedly */ goto fail; } if ((second_sequence[0] != '\\') || (second_sequence[1] != 'u')) { /* missing second half of the surrogate pair */ goto fail; } /* get the second utf16 sequence */ second_code = parse_hex4(second_sequence + 2); /* check that the code is valid */ if ((second_code < 0xDC00) || (second_code > 0xDFFF)) { /* invalid second half of the surrogate pair */ goto fail; } /* calculate the unicode codepoint from the surrogate pair */ codepoint = 0x10000 + (((first_code & 0x3FF) << 10) | (second_code & 0x3FF)); } else { sequence_length = 6; /* \uXXXX */ codepoint = first_code; } /* encode as UTF-8 * takes at maximum 4 bytes to encode: * 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx */ if (codepoint < 0x80) { /* normal ascii, encoding 0xxxxxxx */ utf8_length = 1; } else if (codepoint < 0x800) { /* two bytes, encoding 110xxxxx 10xxxxxx */ utf8_length = 2; first_byte_mark = 0xC0; /* 11000000 */ } else if (codepoint < 0x10000) { /* three bytes, encoding 1110xxxx 10xxxxxx 10xxxxxx */ utf8_length = 3; first_byte_mark = 0xE0; /* 11100000 */ } else if (codepoint <= 0x10FFFF) { /* four bytes, encoding 1110xxxx 10xxxxxx 10xxxxxx 10xxxxxx */ utf8_length = 4; first_byte_mark = 0xF0; /* 11110000 */ } else { /* invalid unicode codepoint */ goto fail; } /* encode as utf8 */ for (utf8_position = (unsigned char)(utf8_length - 1); utf8_position > 0; utf8_position--) { /* 10xxxxxx */ (*output_pointer)[utf8_position] = (unsigned char)((codepoint | 0x80) & 0xBF); codepoint >>= 6; } /* encode first byte */ if (utf8_length > 1) { (*output_pointer)[0] = (unsigned char)((codepoint | first_byte_mark) & 0xFF); } else { (*output_pointer)[0] = (unsigned char)(codepoint & 0x7F); } *output_pointer += utf8_length; return sequence_length; fail: return 0; } /* Parse the input text into an unescaped cinput, and populate item. */ static cJSON_bool parse_string(cJSON * const item, parse_buffer * const input_buffer) { const unsigned char *input_pointer = buffer_at_offset(input_buffer) + 1; const unsigned char *input_end = buffer_at_offset(input_buffer) + 1; unsigned char *output_pointer = NULL; unsigned char *output = NULL; /* not a string */ if (buffer_at_offset(input_buffer)[0] != '\"') { goto fail; } { /* calculate approximate size of the output (overestimate) */ size_t allocation_length = 0; size_t skipped_bytes = 0; while (((size_t)(input_end - input_buffer->content) < input_buffer->length) && (*input_end != '\"')) { /* is escape sequence */ if (input_end[0] == '\\') { if ((size_t)(input_end + 1 - input_buffer->content) >= input_buffer->length) { /* prevent buffer overflow when last input character is a backslash */ goto fail; } skipped_bytes++; input_end++; } input_end++; } if (((size_t)(input_end - input_buffer->content) >= input_buffer->length) || (*input_end != '\"')) { goto fail; /* string ended unexpectedly */ } /* This is at most how much we need for the output */ allocation_length = (size_t) (input_end - buffer_at_offset(input_buffer)) - skipped_bytes; output = (unsigned char*)input_buffer->hooks.allocate(allocation_length + sizeof("")); if (output == NULL) { goto fail; /* allocation failure */ } } output_pointer = output; /* loop through the string literal */ while (input_pointer < input_end) { if (*input_pointer != '\\') { *output_pointer++ = *input_pointer++; } /* escape sequence */ else { unsigned char sequence_length = 2; if ((input_end - input_pointer) < 1) { goto fail; } switch (input_pointer[1]) { case 'b': *output_pointer++ = '\b'; break; case 'f': *output_pointer++ = '\f'; break; case 'n': *output_pointer++ = '\n'; break; case 'r': *output_pointer++ = '\r'; break; case 't': *output_pointer++ = '\t'; break; case '\"': case '\\': case '/': *output_pointer++ = input_pointer[1]; break; /* UTF-16 literal */ case 'u': sequence_length = utf16_literal_to_utf8(input_pointer, input_end, &output_pointer); if (sequence_length == 0) { /* failed to convert UTF16-literal to UTF-8 */ goto fail; } break; default: goto fail; } input_pointer += sequence_length; } } /* zero terminate the output */ *output_pointer = '\0'; item->type = cJSON_String; item->valuestring = (char*)output; input_buffer->offset = (size_t) (input_end - input_buffer->content); input_buffer->offset++; return true; fail: if (output != NULL) { input_buffer->hooks.deallocate(output); } if (input_pointer != NULL) { input_buffer->offset = (size_t)(input_pointer - input_buffer->content); } return false; } /* Render the cstring provided to an escaped version that can be printed. */ static cJSON_bool print_string_ptr(const unsigned char * const input, printbuffer * const output_buffer) { const unsigned char *input_pointer = NULL; unsigned char *output = NULL; unsigned char *output_pointer = NULL; size_t output_length = 0; /* numbers of additional characters needed for escaping */ size_t escape_characters = 0; if (output_buffer == NULL) { return false; } /* empty string */ if (input == NULL) { output = ensure(output_buffer, sizeof("\"\"")); if (output == NULL) { return false; } strcpy((char*)output, "\"\""); return true; } /* set "flag" to 1 if something needs to be escaped */ for (input_pointer = input; *input_pointer; input_pointer++) { switch (*input_pointer) { case '\"': case '\\': case '\b': case '\f': case '\n': case '\r': case '\t': /* one character escape sequence */ escape_characters++; break; default: if (*input_pointer < 32) { /* UTF-16 escape sequence uXXXX */ escape_characters += 5; } break; } } output_length = (size_t)(input_pointer - input) + escape_characters; output = ensure(output_buffer, output_length + sizeof("\"\"")); if (output == NULL) { return false; } /* no characters have to be escaped */ if (escape_characters == 0) { output[0] = '\"'; memcpy(output + 1, input, output_length); output[output_length + 1] = '\"'; output[output_length + 2] = '\0'; return true; } output[0] = '\"'; output_pointer = output + 1; /* copy the string */ for (input_pointer = input; *input_pointer != '\0'; (void)input_pointer++, output_pointer++) { if ((*input_pointer > 31) && (*input_pointer != '\"') && (*input_pointer != '\\')) { /* normal character, copy */ *output_pointer = *input_pointer; } else { /* character needs to be escaped */ *output_pointer++ = '\\'; switch (*input_pointer) { case '\\': *output_pointer = '\\'; break; case '\"': *output_pointer = '\"'; break; case '\b': *output_pointer = 'b'; break; case '\f': *output_pointer = 'f'; break; case '\n': *output_pointer = 'n'; break; case '\r': *output_pointer = 'r'; break; case '\t': *output_pointer = 't'; break; default: /* escape and print as unicode codepoint */ sprintf((char*)output_pointer, "u%04x", *input_pointer); output_pointer += 4; break; } } } output[output_length + 1] = '\"'; output[output_length + 2] = '\0'; return true; } /* Invoke print_string_ptr (which is useful) on an item. */ static cJSON_bool print_string(const cJSON * const item, printbuffer * const p) { return print_string_ptr((unsigned char*)item->valuestring, p); } /* Predeclare these prototypes. */ static cJSON_bool parse_value(cJSON * const item, parse_buffer * const input_buffer); static cJSON_bool print_value(const cJSON * const item, printbuffer * const output_buffer); static cJSON_bool parse_array(cJSON * const item, parse_buffer * const input_buffer); static cJSON_bool print_array(const cJSON * const item, printbuffer * const output_buffer); static cJSON_bool parse_object(cJSON * const item, parse_buffer * const input_buffer); static cJSON_bool print_object(const cJSON * const item, printbuffer * const output_buffer); /* Utility to jump whitespace and cr/lf */ static parse_buffer *buffer_skip_whitespace(parse_buffer * const buffer) { if ((buffer == NULL) || (buffer->content == NULL)) { return NULL; } while (can_access_at_index(buffer, 0) && (buffer_at_offset(buffer)[0] <= 32)) { buffer->offset++; } if (buffer->offset == buffer->length) { buffer->offset--; } return buffer; } /* skip the UTF-8 BOM (byte order mark) if it is at the beginning of a buffer */ static parse_buffer *skip_utf8_bom(parse_buffer * const buffer) { if ((buffer == NULL) || (buffer->content == NULL) || (buffer->offset != 0)) { return NULL; } if (can_access_at_index(buffer, 4) && (strncmp((const char*)buffer_at_offset(buffer), "\xEF\xBB\xBF", 3) == 0)) { buffer->offset += 3; } return buffer; } /* Parse an object - create a new root, and populate. */ CJSON_PUBLIC(cJSON *) cJSON_ParseWithOpts(const char *value, const char **return_parse_end, cJSON_bool require_null_terminated) { parse_buffer buffer = { 0, 0, 0, 0, { 0, 0, 0 } }; cJSON *item = NULL; /* reset error position */ global_error.json = NULL; global_error.position = 0; if (value == NULL) { goto fail; } buffer.content = (const unsigned char*)value; buffer.length = strlen((const char*)value) + sizeof(""); buffer.offset = 0; buffer.hooks = global_hooks; item = cJSON_New_Item(&global_hooks); if (item == NULL) /* memory fail */ { goto fail; } if (!parse_value(item, buffer_skip_whitespace(skip_utf8_bom(&buffer)))) { /* parse failure. ep is set. */ goto fail; } /* if we require null-terminated JSON without appended garbage, skip and then check for a null terminator */ if (require_null_terminated) { buffer_skip_whitespace(&buffer); if ((buffer.offset >= buffer.length) || buffer_at_offset(&buffer)[0] != '\0') { goto fail; } } if (return_parse_end) { *return_parse_end = (const char*)buffer_at_offset(&buffer); } return item; fail: if (item != NULL) { cJSON_Delete(item); } if (value != NULL) { error local_error; local_error.json = (const unsigned char*)value; local_error.position = 0; if (buffer.offset < buffer.length) { local_error.position = buffer.offset; } else if (buffer.length > 0) { local_error.position = buffer.length - 1; } if (return_parse_end != NULL) { *return_parse_end = (const char*)local_error.json + local_error.position; } global_error = local_error; } return NULL; } /* Default options for cJSON_Parse */ CJSON_PUBLIC(cJSON *) cJSON_Parse(const char *value) { return cJSON_ParseWithOpts(value, 0, 0); } #define cjson_min(a, b) ((a < b) ? a : b) static unsigned char *print(const cJSON * const item, cJSON_bool format, const internal_hooks * const hooks) { static const size_t default_buffer_size = 256; printbuffer buffer[1]; unsigned char *printed = NULL; memset(buffer, 0, sizeof(buffer)); /* create buffer */ buffer->buffer = (unsigned char*) hooks->allocate(default_buffer_size); buffer->length = default_buffer_size; buffer->format = format; buffer->hooks = *hooks; if (buffer->buffer == NULL) { goto fail; } /* print the value */ if (!print_value(item, buffer)) { goto fail; } update_offset(buffer); /* check if reallocate is available */ if (hooks->reallocate != NULL) { printed = (unsigned char*) hooks->reallocate(buffer->buffer, buffer->offset + 1); if (printed == NULL) { goto fail; } buffer->buffer = NULL; } else /* otherwise copy the JSON over to a new buffer */ { printed = (unsigned char*) hooks->allocate(buffer->offset + 1); if (printed == NULL) { goto fail; } memcpy(printed, buffer->buffer, cjson_min(buffer->length, buffer->offset + 1)); printed[buffer->offset] = '\0'; /* just to be sure */ /* free the buffer */ hooks->deallocate(buffer->buffer); } return printed; fail: if (buffer->buffer != NULL) { hooks->deallocate(buffer->buffer); } if (printed != NULL) { hooks->deallocate(printed); } return NULL; } /* Render a cJSON item/entity/structure to text. */ CJSON_PUBLIC(char *) cJSON_Print(const cJSON *item) { return (char*)print(item, true, &global_hooks); } CJSON_PUBLIC(char *) cJSON_PrintUnformatted(const cJSON *item) { return (char*)print(item, false, &global_hooks); } CJSON_PUBLIC(char *) cJSON_PrintBuffered(const cJSON *item, int prebuffer, cJSON_bool fmt) { printbuffer p = { 0, 0, 0, 0, 0, 0, { 0, 0, 0 } }; if (prebuffer < 0) { return NULL; } p.buffer = (unsigned char*)global_hooks.allocate((size_t)prebuffer); if (!p.buffer) { return NULL; } p.length = (size_t)prebuffer; p.offset = 0; p.noalloc = false; p.format = fmt; p.hooks = global_hooks; if (!print_value(item, &p)) { global_hooks.deallocate(p.buffer); return NULL; } return (char*)p.buffer; } CJSON_PUBLIC(cJSON_bool) cJSON_PrintPreallocated(cJSON *item, char *buf, const int len, const cJSON_bool fmt) { printbuffer p = { 0, 0, 0, 0, 0, 0, { 0, 0, 0 } }; if ((len < 0) || (buf == NULL)) { return false; } p.buffer = (unsigned char*)buf; p.length = (size_t)len; p.offset = 0; p.noalloc = true; p.format = fmt; p.hooks = global_hooks; return print_value(item, &p); } /* Parser core - when encountering text, process appropriately. */ static cJSON_bool parse_value(cJSON * const item, parse_buffer * const input_buffer) { if ((input_buffer == NULL) || (input_buffer->content == NULL)) { return false; /* no input */ } /* parse the different types of values */ /* null */ if (can_read(input_buffer, 4) && (strncmp((const char*)buffer_at_offset(input_buffer), "null", 4) == 0)) { item->type = cJSON_NULL; input_buffer->offset += 4; return true; } /* false */ if (can_read(input_buffer, 5) && (strncmp((const char*)buffer_at_offset(input_buffer), "false", 5) == 0)) { item->type = cJSON_False; input_buffer->offset += 5; return true; } /* true */ if (can_read(input_buffer, 4) && (strncmp((const char*)buffer_at_offset(input_buffer), "true", 4) == 0)) { item->type = cJSON_True; item->valueint = 1; input_buffer->offset += 4; return true; } /* string */ if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == '\"')) { return parse_string(item, input_buffer); } /* number */ if (can_access_at_index(input_buffer, 0) && ((buffer_at_offset(input_buffer)[0] == '-') || ((buffer_at_offset(input_buffer)[0] >= '0') && (buffer_at_offset(input_buffer)[0] <= '9')))) { return parse_number(item, input_buffer); } /* array */ if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == '[')) { return parse_array(item, input_buffer); } /* object */ if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == '{')) { return parse_object(item, input_buffer); } return false; } /* Render a value to text. */ static cJSON_bool print_value(const cJSON * const item, printbuffer * const output_buffer) { unsigned char *output = NULL; if ((item == NULL) || (output_buffer == NULL)) { return false; } switch ((item->type) & 0xFF) { case cJSON_NULL: output = ensure(output_buffer, 5); if (output == NULL) { return false; } strcpy((char*)output, "null"); return true; case cJSON_False: output = ensure(output_buffer, 6); if (output == NULL) { return false; } strcpy((char*)output, "false"); return true; case cJSON_True: output = ensure(output_buffer, 5); if (output == NULL) { return false; } strcpy((char*)output, "true"); return true; case cJSON_Number: return print_number(item, output_buffer); case cJSON_Raw: { size_t raw_length = 0; if (item->valuestring == NULL) { return false; } raw_length = strlen(item->valuestring) + sizeof(""); output = ensure(output_buffer, raw_length); if (output == NULL) { return false; } memcpy(output, item->valuestring, raw_length); return true; } case cJSON_String: return print_string(item, output_buffer); case cJSON_Array: return print_array(item, output_buffer); case cJSON_Object: return print_object(item, output_buffer); default: return false; } } /* Build an array from input text. */ static cJSON_bool parse_array(cJSON * const item, parse_buffer * const input_buffer) { cJSON *head = NULL; /* head of the linked list */ cJSON *current_item = NULL; if (input_buffer->depth >= CJSON_NESTING_LIMIT) { return false; /* to deeply nested */ } input_buffer->depth++; if (buffer_at_offset(input_buffer)[0] != '[') { /* not an array */ goto fail; } input_buffer->offset++; buffer_skip_whitespace(input_buffer); if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == ']')) { /* empty array */ goto success; } /* check if we skipped to the end of the buffer */ if (cannot_access_at_index(input_buffer, 0)) { input_buffer->offset--; goto fail; } /* step back to character in front of the first element */ input_buffer->offset--; /* loop through the comma separated array elements */ do { /* allocate next item */ cJSON *new_item = cJSON_New_Item(&(input_buffer->hooks)); if (new_item == NULL) { goto fail; /* allocation failure */ } /* attach next item to list */ if (head == NULL) { /* start the linked list */ current_item = head = new_item; } else { /* add to the end and advance */ current_item->next = new_item; new_item->prev = current_item; current_item = new_item; } /* parse next value */ input_buffer->offset++; buffer_skip_whitespace(input_buffer); if (!parse_value(current_item, input_buffer)) { goto fail; /* failed to parse value */ } buffer_skip_whitespace(input_buffer); } while (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == ',')); if (cannot_access_at_index(input_buffer, 0) || buffer_at_offset(input_buffer)[0] != ']') { goto fail; /* expected end of array */ } success: input_buffer->depth--; item->type = cJSON_Array; item->child = head; input_buffer->offset++; return true; fail: if (head != NULL) { cJSON_Delete(head); } return false; } /* Render an array to text */ static cJSON_bool print_array(const cJSON * const item, printbuffer * const output_buffer) { unsigned char *output_pointer = NULL; size_t length = 0; cJSON *current_element = item->child; if (output_buffer == NULL) { return false; } /* Compose the output array. */ /* opening square bracket */ output_pointer = ensure(output_buffer, 1); if (output_pointer == NULL) { return false; } *output_pointer = '['; output_buffer->offset++; output_buffer->depth++; while (current_element != NULL) { if (!print_value(current_element, output_buffer)) { return false; } update_offset(output_buffer); if (current_element->next) { length = (size_t) (output_buffer->format ? 2 : 1); output_pointer = ensure(output_buffer, length + 1); if (output_pointer == NULL) { return false; } *output_pointer++ = ','; if(output_buffer->format) { *output_pointer++ = ' '; } *output_pointer = '\0'; output_buffer->offset += length; } current_element = current_element->next; } output_pointer = ensure(output_buffer, 2); if (output_pointer == NULL) { return false; } *output_pointer++ = ']'; *output_pointer = '\0'; output_buffer->depth--; return true; } /* Build an object from the text. */ static cJSON_bool parse_object(cJSON * const item, parse_buffer * const input_buffer) { cJSON *head = NULL; /* linked list head */ cJSON *current_item = NULL; if (input_buffer->depth >= CJSON_NESTING_LIMIT) { return false; /* to deeply nested */ } input_buffer->depth++; if (cannot_access_at_index(input_buffer, 0) || (buffer_at_offset(input_buffer)[0] != '{')) { goto fail; /* not an object */ } input_buffer->offset++; buffer_skip_whitespace(input_buffer); if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == '}')) { goto success; /* empty object */ } /* check if we skipped to the end of the buffer */ if (cannot_access_at_index(input_buffer, 0)) { input_buffer->offset--; goto fail; } /* step back to character in front of the first element */ input_buffer->offset--; /* loop through the comma separated array elements */ do { /* allocate next item */ cJSON *new_item = cJSON_New_Item(&(input_buffer->hooks)); if (new_item == NULL) { goto fail; /* allocation failure */ } /* attach next item to list */ if (head == NULL) { /* start the linked list */ current_item = head = new_item; } else { /* add to the end and advance */ current_item->next = new_item; new_item->prev = current_item; current_item = new_item; } /* parse the name of the child */ input_buffer->offset++; buffer_skip_whitespace(input_buffer); if (!parse_string(current_item, input_buffer)) { goto fail; /* faile to parse name */ } buffer_skip_whitespace(input_buffer); /* swap valuestring and string, because we parsed the name */ current_item->string = current_item->valuestring; current_item->valuestring = NULL; if (cannot_access_at_index(input_buffer, 0) || (buffer_at_offset(input_buffer)[0] != ':')) { goto fail; /* invalid object */ } /* parse the value */ input_buffer->offset++; buffer_skip_whitespace(input_buffer); if (!parse_value(current_item, input_buffer)) { goto fail; /* failed to parse value */ } buffer_skip_whitespace(input_buffer); } while (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == ',')); if (cannot_access_at_index(input_buffer, 0) || (buffer_at_offset(input_buffer)[0] != '}')) { goto fail; /* expected end of object */ } success: input_buffer->depth--; item->type = cJSON_Object; item->child = head; input_buffer->offset++; return true; fail: if (head != NULL) { cJSON_Delete(head); } return false; } /* Render an object to text. */ static cJSON_bool print_object(const cJSON * const item, printbuffer * const output_buffer) { unsigned char *output_pointer = NULL; size_t length = 0; cJSON *current_item = item->child; if (output_buffer == NULL) { return false; } /* Compose the output: */ length = (size_t) (output_buffer->format ? 2 : 1); /* fmt: {\n */ output_pointer = ensure(output_buffer, length + 1); if (output_pointer == NULL) { return false; } *output_pointer++ = '{'; output_buffer->depth++; if (output_buffer->format) { *output_pointer++ = '\n'; } output_buffer->offset += length; while (current_item) { if (output_buffer->format) { size_t i; output_pointer = ensure(output_buffer, output_buffer->depth); if (output_pointer == NULL) { return false; } for (i = 0; i < output_buffer->depth; i++) { *output_pointer++ = '\t'; } output_buffer->offset += output_buffer->depth; } /* print key */ if (!print_string_ptr((unsigned char*)current_item->string, output_buffer)) { return false; } update_offset(output_buffer); length = (size_t) (output_buffer->format ? 2 : 1); output_pointer = ensure(output_buffer, length); if (output_pointer == NULL) { return false; } *output_pointer++ = ':'; if (output_buffer->format) { *output_pointer++ = '\t'; } output_buffer->offset += length; /* print value */ if (!print_value(current_item, output_buffer)) { return false; } update_offset(output_buffer); /* print comma if not last */ length = (size_t) ((output_buffer->format ? 1 : 0) + (current_item->next ? 1 : 0)); output_pointer = ensure(output_buffer, length + 1); if (output_pointer == NULL) { return false; } if (current_item->next) { *output_pointer++ = ','; } if (output_buffer->format) { *output_pointer++ = '\n'; } *output_pointer = '\0'; output_buffer->offset += length; current_item = current_item->next; } output_pointer = ensure(output_buffer, output_buffer->format ? (output_buffer->depth + 1) : 2); if (output_pointer == NULL) { return false; } if (output_buffer->format) { size_t i; for (i = 0; i < (output_buffer->depth - 1); i++) { *output_pointer++ = '\t'; } } *output_pointer++ = '}'; *output_pointer = '\0'; output_buffer->depth--; return true; } /* Get Array size/item / object item. */ CJSON_PUBLIC(int) cJSON_GetArraySize(const cJSON *array) { cJSON *child = NULL; size_t size = 0; if (array == NULL) { return 0; } child = array->child; while(child != NULL) { size++; child = child->next; } /* FIXME: Can overflow here. Cannot be fixed without breaking the API */ return (int)size; } static cJSON* get_array_item(const cJSON *array, size_t index) { cJSON *current_child = NULL; if (array == NULL) { return NULL; } current_child = array->child; while ((current_child != NULL) && (index > 0)) { index--; current_child = current_child->next; } return current_child; } CJSON_PUBLIC(cJSON *) cJSON_GetArrayItem(const cJSON *array, int index) { if (index < 0) { return NULL; } return get_array_item(array, (size_t)index); } static cJSON *get_object_item(const cJSON * const object, const char * const name, const cJSON_bool case_sensitive) { cJSON *current_element = NULL; if ((object == NULL) || (name == NULL)) { return NULL; } current_element = object->child; if (case_sensitive) { while ((current_element != NULL) && (strcmp(name, current_element->string) != 0)) { current_element = current_element->next; } } else { while ((current_element != NULL) && (case_insensitive_strcmp((const unsigned char*)name, (const unsigned char*)(current_element->string)) != 0)) { current_element = current_element->next; } } return current_element; } CJSON_PUBLIC(cJSON *) cJSON_GetObjectItem(const cJSON * const object, const char * const string) { return get_object_item(object, string, false); } CJSON_PUBLIC(cJSON *) cJSON_GetObjectItemCaseSensitive(const cJSON * const object, const char * const string) { return get_object_item(object, string, true); } CJSON_PUBLIC(cJSON_bool) cJSON_HasObjectItem(const cJSON *object, const char *string) { return cJSON_GetObjectItem(object, string) ? 1 : 0; } /* Utility for array list handling. */ static void suffix_object(cJSON *prev, cJSON *item) { prev->next = item; item->prev = prev; } /* Utility for handling references. */ static cJSON *create_reference(const cJSON *item, const internal_hooks * const hooks) { cJSON *reference = NULL; if (item == NULL) { return NULL; } reference = cJSON_New_Item(hooks); if (reference == NULL) { return NULL; } memcpy(reference, item, sizeof(cJSON)); reference->string = NULL; reference->type |= cJSON_IsReference; reference->next = reference->prev = NULL; return reference; } static cJSON_bool add_item_to_array(cJSON *array, cJSON *item) { cJSON *child = NULL; if ((item == NULL) || (array == NULL)) { return false; } child = array->child; if (child == NULL) { /* list is empty, start new one */ array->child = item; } else { /* append to the end */ while (child->next) { child = child->next; } suffix_object(child, item); } return true; } /* Add item to array/object. */ CJSON_PUBLIC(void) cJSON_AddItemToArray(cJSON *array, cJSON *item) { add_item_to_array(array, item); } #if defined(__clang__) || (defined(__GNUC__) && ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ > 5)))) #pragma GCC diagnostic push #endif #ifdef __GNUC__ #pragma GCC diagnostic ignored "-Wcast-qual" #endif /* helper function to cast away const */ static void* cast_away_const(const void* string) { return (void*)string; } #if defined(__clang__) || (defined(__GNUC__) && ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ > 5)))) #pragma GCC diagnostic pop #endif static cJSON_bool add_item_to_object(cJSON * const object, const char * const string, cJSON * const item, const internal_hooks * const hooks, const cJSON_bool constant_key) { char *new_key = NULL; int new_type = cJSON_Invalid; if ((object == NULL) || (string == NULL) || (item == NULL)) { return false; } if (constant_key) { new_key = (char*)cast_away_const(string); new_type = item->type | cJSON_StringIsConst; } else { new_key = (char*)cJSON_strdup((const unsigned char*)string, hooks); if (new_key == NULL) { return false; } new_type = item->type & ~cJSON_StringIsConst; } if (!(item->type & cJSON_StringIsConst) && (item->string != NULL)) { hooks->deallocate(item->string); } item->string = new_key; item->type = new_type; return add_item_to_array(object, item); } CJSON_PUBLIC(void) cJSON_AddItemToObject(cJSON *object, const char *string, cJSON *item) { add_item_to_object(object, string, item, &global_hooks, false); } /* Add an item to an object with constant string as key */ CJSON_PUBLIC(void) cJSON_AddItemToObjectCS(cJSON *object, const char *string, cJSON *item) { add_item_to_object(object, string, item, &global_hooks, true); } CJSON_PUBLIC(void) cJSON_AddItemReferenceToArray(cJSON *array, cJSON *item) { if (array == NULL) { return; } add_item_to_array(array, create_reference(item, &global_hooks)); } CJSON_PUBLIC(void) cJSON_AddItemReferenceToObject(cJSON *object, const char *string, cJSON *item) { if ((object == NULL) || (string == NULL)) { return; } add_item_to_object(object, string, create_reference(item, &global_hooks), &global_hooks, false); } CJSON_PUBLIC(cJSON*) cJSON_AddNullToObject(cJSON * const object, const char * const name) { cJSON *null = cJSON_CreateNull(); if (add_item_to_object(object, name, null, &global_hooks, false)) { return null; } cJSON_Delete(null); return NULL; } CJSON_PUBLIC(cJSON*) cJSON_AddTrueToObject(cJSON * const object, const char * const name) { cJSON *true_item = cJSON_CreateTrue(); if (add_item_to_object(object, name, true_item, &global_hooks, false)) { return true_item; } cJSON_Delete(true_item); return NULL; } CJSON_PUBLIC(cJSON*) cJSON_AddFalseToObject(cJSON * const object, const char * const name) { cJSON *false_item = cJSON_CreateFalse(); if (add_item_to_object(object, name, false_item, &global_hooks, false)) { return false_item; } cJSON_Delete(false_item); return NULL; } CJSON_PUBLIC(cJSON*) cJSON_AddBoolToObject(cJSON * const object, const char * const name, const cJSON_bool boolean) { cJSON *bool_item = cJSON_CreateBool(boolean); if (add_item_to_object(object, name, bool_item, &global_hooks, false)) { return bool_item; } cJSON_Delete(bool_item); return NULL; } CJSON_PUBLIC(cJSON*) cJSON_AddNumberToObject(cJSON * const object, const char * const name, const double number) { cJSON *number_item = cJSON_CreateNumber(number); if (add_item_to_object(object, name, number_item, &global_hooks, false)) { return number_item; } cJSON_Delete(number_item); return NULL; } CJSON_PUBLIC(cJSON*) cJSON_AddStringToObject(cJSON * const object, const char * const name, const char * const string) { cJSON *string_item = cJSON_CreateString(string); if (add_item_to_object(object, name, string_item, &global_hooks, false)) { return string_item; } cJSON_Delete(string_item); return NULL; } CJSON_PUBLIC(cJSON*) cJSON_AddRawToObject(cJSON * const object, const char * const name, const char * const raw) { cJSON *raw_item = cJSON_CreateRaw(raw); if (add_item_to_object(object, name, raw_item, &global_hooks, false)) { return raw_item; } cJSON_Delete(raw_item); return NULL; } CJSON_PUBLIC(cJSON*) cJSON_AddObjectToObject(cJSON * const object, const char * const name) { cJSON *object_item = cJSON_CreateObject(); if (add_item_to_object(object, name, object_item, &global_hooks, false)) { return object_item; } cJSON_Delete(object_item); return NULL; } CJSON_PUBLIC(cJSON*) cJSON_AddArrayToObject(cJSON * const object, const char * const name) { cJSON *array = cJSON_CreateArray(); if (add_item_to_object(object, name, array, &global_hooks, false)) { return array; } cJSON_Delete(array); return NULL; } CJSON_PUBLIC(cJSON *) cJSON_DetachItemViaPointer(cJSON *parent, cJSON * const item) { if ((parent == NULL) || (item == NULL)) { return NULL; } if (item->prev != NULL) { /* not the first element */ item->prev->next = item->next; } if (item->next != NULL) { /* not the last element */ item->next->prev = item->prev; } if (item == parent->child) { /* first element */ parent->child = item->next; } /* make sure the detached item doesn't point anywhere anymore */ item->prev = NULL; item->next = NULL; return item; } CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromArray(cJSON *array, int which) { if (which < 0) { return NULL; } return cJSON_DetachItemViaPointer(array, get_array_item(array, (size_t)which)); } CJSON_PUBLIC(void) cJSON_DeleteItemFromArray(cJSON *array, int which) { cJSON_Delete(cJSON_DetachItemFromArray(array, which)); } CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromObject(cJSON *object, const char *string) { cJSON *to_detach = cJSON_GetObjectItem(object, string); return cJSON_DetachItemViaPointer(object, to_detach); } CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromObjectCaseSensitive(cJSON *object, const char *string) { cJSON *to_detach = cJSON_GetObjectItemCaseSensitive(object, string); return cJSON_DetachItemViaPointer(object, to_detach); } CJSON_PUBLIC(void) cJSON_DeleteItemFromObject(cJSON *object, const char *string) { cJSON_Delete(cJSON_DetachItemFromObject(object, string)); } CJSON_PUBLIC(void) cJSON_DeleteItemFromObjectCaseSensitive(cJSON *object, const char *string) { cJSON_Delete(cJSON_DetachItemFromObjectCaseSensitive(object, string)); } /* Replace array/object items with new ones. */ CJSON_PUBLIC(void) cJSON_InsertItemInArray(cJSON *array, int which, cJSON *newitem) { cJSON *after_inserted = NULL; if (which < 0) { return; } after_inserted = get_array_item(array, (size_t)which); if (after_inserted == NULL) { add_item_to_array(array, newitem); return; } newitem->next = after_inserted; newitem->prev = after_inserted->prev; after_inserted->prev = newitem; if (after_inserted == array->child) { array->child = newitem; } else { newitem->prev->next = newitem; } } CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemViaPointer(cJSON * const parent, cJSON * const item, cJSON * replacement) { if ((parent == NULL) || (replacement == NULL) || (item == NULL)) { return false; } if (replacement == item) { return true; } replacement->next = item->next; replacement->prev = item->prev; if (replacement->next != NULL) { replacement->next->prev = replacement; } if (replacement->prev != NULL) { replacement->prev->next = replacement; } if (parent->child == item) { parent->child = replacement; } item->next = NULL; item->prev = NULL; cJSON_Delete(item); return true; } CJSON_PUBLIC(void) cJSON_ReplaceItemInArray(cJSON *array, int which, cJSON *newitem) { if (which < 0) { return; } cJSON_ReplaceItemViaPointer(array, get_array_item(array, (size_t)which), newitem); } static cJSON_bool replace_item_in_object(cJSON *object, const char *string, cJSON *replacement, cJSON_bool case_sensitive) { if ((replacement == NULL) || (string == NULL)) { return false; } /* replace the name in the replacement */ if (!(replacement->type & cJSON_StringIsConst) && (replacement->string != NULL)) { cJSON_free(replacement->string); } replacement->string = (char*)cJSON_strdup((const unsigned char*)string, &global_hooks); replacement->type &= ~cJSON_StringIsConst; cJSON_ReplaceItemViaPointer(object, get_object_item(object, string, case_sensitive), replacement); return true; } CJSON_PUBLIC(void) cJSON_ReplaceItemInObject(cJSON *object, const char *string, cJSON *newitem) { replace_item_in_object(object, string, newitem, false); } CJSON_PUBLIC(void) cJSON_ReplaceItemInObjectCaseSensitive(cJSON *object, const char *string, cJSON *newitem) { replace_item_in_object(object, string, newitem, true); } /* Create basic types: */ CJSON_PUBLIC(cJSON *) cJSON_CreateNull(void) { cJSON *item = cJSON_New_Item(&global_hooks); if(item) { item->type = cJSON_NULL; } return item; } CJSON_PUBLIC(cJSON *) cJSON_CreateTrue(void) { cJSON *item = cJSON_New_Item(&global_hooks); if(item) { item->type = cJSON_True; } return item; } CJSON_PUBLIC(cJSON *) cJSON_CreateFalse(void) { cJSON *item = cJSON_New_Item(&global_hooks); if(item) { item->type = cJSON_False; } return item; } CJSON_PUBLIC(cJSON *) cJSON_CreateBool(cJSON_bool b) { cJSON *item = cJSON_New_Item(&global_hooks); if(item) { item->type = b ? cJSON_True : cJSON_False; } return item; } CJSON_PUBLIC(cJSON *) cJSON_CreateNumber(double num) { cJSON *item = cJSON_New_Item(&global_hooks); if(item) { item->type = cJSON_Number; item->valuedouble = num; /* use saturation in case of overflow */ if (num >= INT_MAX) { item->valueint = INT_MAX; } else if (num <= INT_MIN) { item->valueint = INT_MIN; } else { item->valueint = (int)num; } } return item; } CJSON_PUBLIC(cJSON *) cJSON_CreateString(const char *string) { cJSON *item = cJSON_New_Item(&global_hooks); if(item) { item->type = cJSON_String; item->valuestring = (char*)cJSON_strdup((const unsigned char*)string, &global_hooks); if(!item->valuestring) { cJSON_Delete(item); return NULL; } } return item; } CJSON_PUBLIC(cJSON *) cJSON_CreateStringReference(const char *string) { cJSON *item = cJSON_New_Item(&global_hooks); if (item != NULL) { item->type = cJSON_String | cJSON_IsReference; item->valuestring = (char*)cast_away_const(string); } return item; } CJSON_PUBLIC(cJSON *) cJSON_CreateObjectReference(const cJSON *child) { cJSON *item = cJSON_New_Item(&global_hooks); if (item != NULL) { item->type = cJSON_Object | cJSON_IsReference; item->child = (cJSON*)cast_away_const(child); } return item; } CJSON_PUBLIC(cJSON *) cJSON_CreateArrayReference(const cJSON *child) { cJSON *item = cJSON_New_Item(&global_hooks); if (item != NULL) { item->type = cJSON_Array | cJSON_IsReference; item->child = (cJSON*)cast_away_const(child); } return item; } CJSON_PUBLIC(cJSON *) cJSON_CreateRaw(const char *raw) { cJSON *item = cJSON_New_Item(&global_hooks); if(item) { item->type = cJSON_Raw; item->valuestring = (char*)cJSON_strdup((const unsigned char*)raw, &global_hooks); if(!item->valuestring) { cJSON_Delete(item); return NULL; } } return item; } CJSON_PUBLIC(cJSON *) cJSON_CreateArray(void) { cJSON *item = cJSON_New_Item(&global_hooks); if(item) { item->type=cJSON_Array; } return item; } CJSON_PUBLIC(cJSON *) cJSON_CreateObject(void) { cJSON *item = cJSON_New_Item(&global_hooks); if (item) { item->type = cJSON_Object; } return item; } /* Create Arrays: */ CJSON_PUBLIC(cJSON *) cJSON_CreateIntArray(const int *numbers, int count) { size_t i = 0; cJSON *n = NULL; cJSON *p = NULL; cJSON *a = NULL; if ((count < 0) || (numbers == NULL)) { return NULL; } a = cJSON_CreateArray(); for(i = 0; a && (i < (size_t)count); i++) { n = cJSON_CreateNumber(numbers[i]); if (!n) { cJSON_Delete(a); return NULL; } if(!i) { a->child = n; } else { suffix_object(p, n); } p = n; } return a; } CJSON_PUBLIC(cJSON *) cJSON_CreateFloatArray(const float *numbers, int count) { size_t i = 0; cJSON *n = NULL; cJSON *p = NULL; cJSON *a = NULL; if ((count < 0) || (numbers == NULL)) { return NULL; } a = cJSON_CreateArray(); for(i = 0; a && (i < (size_t)count); i++) { n = cJSON_CreateNumber((double)numbers[i]); if(!n) { cJSON_Delete(a); return NULL; } if(!i) { a->child = n; } else { suffix_object(p, n); } p = n; } return a; } CJSON_PUBLIC(cJSON *) cJSON_CreateDoubleArray(const double *numbers, int count) { size_t i = 0; cJSON *n = NULL; cJSON *p = NULL; cJSON *a = NULL; if ((count < 0) || (numbers == NULL)) { return NULL; } a = cJSON_CreateArray(); for(i = 0;a && (i < (size_t)count); i++) { n = cJSON_CreateNumber(numbers[i]); if(!n) { cJSON_Delete(a); return NULL; } if(!i) { a->child = n; } else { suffix_object(p, n); } p = n; } return a; } CJSON_PUBLIC(cJSON *) cJSON_CreateStringArray(const char **strings, int count) { size_t i = 0; cJSON *n = NULL; cJSON *p = NULL; cJSON *a = NULL; if ((count < 0) || (strings == NULL)) { return NULL; } a = cJSON_CreateArray(); for (i = 0; a && (i < (size_t)count); i++) { n = cJSON_CreateString(strings[i]); if(!n) { cJSON_Delete(a); return NULL; } if(!i) { a->child = n; } else { suffix_object(p,n); } p = n; } return a; } /* Duplication */ CJSON_PUBLIC(cJSON *) cJSON_Duplicate(const cJSON *item, cJSON_bool recurse) { cJSON *newitem = NULL; cJSON *child = NULL; cJSON *next = NULL; cJSON *newchild = NULL; /* Bail on bad ptr */ if (!item) { goto fail; } /* Create new item */ newitem = cJSON_New_Item(&global_hooks); if (!newitem) { goto fail; } /* Copy over all vars */ newitem->type = item->type & (~cJSON_IsReference); newitem->valueint = item->valueint; newitem->valuedouble = item->valuedouble; if (item->valuestring) { newitem->valuestring = (char*)cJSON_strdup((unsigned char*)item->valuestring, &global_hooks); if (!newitem->valuestring) { goto fail; } } if (item->string) { newitem->string = (item->type&cJSON_StringIsConst) ? item->string : (char*)cJSON_strdup((unsigned char*)item->string, &global_hooks); if (!newitem->string) { goto fail; } } /* If non-recursive, then we're done! */ if (!recurse) { return newitem; } /* Walk the ->next chain for the child. */ child = item->child; while (child != NULL) { newchild = cJSON_Duplicate(child, true); /* Duplicate (with recurse) each item in the ->next chain */ if (!newchild) { goto fail; } if (next != NULL) { /* If newitem->child already set, then crosswire ->prev and ->next and move on */ next->next = newchild; newchild->prev = next; next = newchild; } else { /* Set newitem->child and move to it */ newitem->child = newchild; next = newchild; } child = child->next; } return newitem; fail: if (newitem != NULL) { cJSON_Delete(newitem); } return NULL; } CJSON_PUBLIC(void) cJSON_Minify(char *json) { unsigned char *into = (unsigned char*)json; if (json == NULL) { return; } while (*json) { if (*json == ' ') { json++; } else if (*json == '\t') { /* Whitespace characters. */ json++; } else if (*json == '\r') { json++; } else if (*json=='\n') { json++; } else if ((*json == '/') && (json[1] == '/')) { /* double-slash comments, to end of line. */ while (*json && (*json != '\n')) { json++; } } else if ((*json == '/') && (json[1] == '*')) { /* multiline comments. */ while (*json && !((*json == '*') && (json[1] == '/'))) { json++; } json += 2; } else if (*json == '\"') { /* string literals, which are \" sensitive. */ *into++ = (unsigned char)*json++; while (*json && (*json != '\"')) { if (*json == '\\') { *into++ = (unsigned char)*json++; } *into++ = (unsigned char)*json++; } *into++ = (unsigned char)*json++; } else { /* All other characters. */ *into++ = (unsigned char)*json++; } } /* and null-terminate. */ *into = '\0'; } CJSON_PUBLIC(cJSON_bool) cJSON_IsInvalid(const cJSON * const item) { if (item == NULL) { return false; } return (item->type & 0xFF) == cJSON_Invalid; } CJSON_PUBLIC(cJSON_bool) cJSON_IsFalse(const cJSON * const item) { if (item == NULL) { return false; } return (item->type & 0xFF) == cJSON_False; } CJSON_PUBLIC(cJSON_bool) cJSON_IsTrue(const cJSON * const item) { if (item == NULL) { return false; } return (item->type & 0xff) == cJSON_True; } CJSON_PUBLIC(cJSON_bool) cJSON_IsBool(const cJSON * const item) { if (item == NULL) { return false; } return (item->type & (cJSON_True | cJSON_False)) != 0; } CJSON_PUBLIC(cJSON_bool) cJSON_IsNull(const cJSON * const item) { if (item == NULL) { return false; } return (item->type & 0xFF) == cJSON_NULL; } CJSON_PUBLIC(cJSON_bool) cJSON_IsNumber(const cJSON * const item) { if (item == NULL) { return false; } return (item->type & 0xFF) == cJSON_Number; } CJSON_PUBLIC(cJSON_bool) cJSON_IsString(const cJSON * const item) { if (item == NULL) { return false; } return (item->type & 0xFF) == cJSON_String; } CJSON_PUBLIC(cJSON_bool) cJSON_IsArray(const cJSON * const item) { if (item == NULL) { return false; } return (item->type & 0xFF) == cJSON_Array; } CJSON_PUBLIC(cJSON_bool) cJSON_IsObject(const cJSON * const item) { if (item == NULL) { return false; } return (item->type & 0xFF) == cJSON_Object; } CJSON_PUBLIC(cJSON_bool) cJSON_IsRaw(const cJSON * const item) { if (item == NULL) { return false; } return (item->type & 0xFF) == cJSON_Raw; } CJSON_PUBLIC(cJSON_bool) cJSON_Compare(const cJSON * const a, const cJSON * const b, const cJSON_bool case_sensitive) { if ((a == NULL) || (b == NULL) || ((a->type & 0xFF) != (b->type & 0xFF)) || cJSON_IsInvalid(a)) { return false; } /* check if type is valid */ switch (a->type & 0xFF) { case cJSON_False: case cJSON_True: case cJSON_NULL: case cJSON_Number: case cJSON_String: case cJSON_Raw: case cJSON_Array: case cJSON_Object: break; default: return false; } /* identical objects are equal */ if (a == b) { return true; } switch (a->type & 0xFF) { /* in these cases and equal type is enough */ case cJSON_False: case cJSON_True: case cJSON_NULL: return true; case cJSON_Number: if (a->valuedouble == b->valuedouble) { return true; } return false; case cJSON_String: case cJSON_Raw: if ((a->valuestring == NULL) || (b->valuestring == NULL)) { return false; } if (strcmp(a->valuestring, b->valuestring) == 0) { return true; } return false; case cJSON_Array: { cJSON *a_element = a->child; cJSON *b_element = b->child; for (; (a_element != NULL) && (b_element != NULL);) { if (!cJSON_Compare(a_element, b_element, case_sensitive)) { return false; } a_element = a_element->next; b_element = b_element->next; } /* one of the arrays is longer than the other */ if (a_element != b_element) { return false; } return true; } case cJSON_Object: { cJSON *a_element = NULL; cJSON *b_element = NULL; cJSON_ArrayForEach(a_element, a) { /* TODO This has O(n^2) runtime, which is horrible! */ b_element = get_object_item(b, a_element->string, case_sensitive); if (b_element == NULL) { return false; } if (!cJSON_Compare(a_element, b_element, case_sensitive)) { return false; } } /* doing this twice, once on a and b to prevent true comparison if a subset of b * TODO: Do this the proper way, this is just a fix for now */ cJSON_ArrayForEach(b_element, b) { a_element = get_object_item(a, b_element->string, case_sensitive); if (a_element == NULL) { return false; } if (!cJSON_Compare(b_element, a_element, case_sensitive)) { return false; } } return true; } default: return false; } } CJSON_PUBLIC(void *) cJSON_malloc(size_t size) { return global_hooks.allocate(size); } CJSON_PUBLIC(void) cJSON_free(void *object) { global_hooks.deallocate(object); } ================================================ FILE: Huawei_LiteOS/components/lib/cJSON/cJSON.h ================================================ /* Copyright (c) 2009-2017 Dave Gamble and cJSON contributors Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef cJSON__h #define cJSON__h #ifdef __cplusplus extern "C" { #endif #if !defined(__WINDOWS__) && (defined(WIN32) || defined(WIN64) || defined(_MSC_VER) || defined(_WIN32)) #define __WINDOWS__ #endif #ifdef __WINDOWS__ /* When compiling for windows, we specify a specific calling convention to avoid issues where we are being called from a project with a different default calling convention. For windows you have 3 define options: CJSON_HIDE_SYMBOLS - Define this in the case where you don't want to ever dllexport symbols CJSON_EXPORT_SYMBOLS - Define this on library build when you want to dllexport symbols (default) CJSON_IMPORT_SYMBOLS - Define this if you want to dllimport symbol For *nix builds that support visibility attribute, you can define similar behavior by setting default visibility to hidden by adding -fvisibility=hidden (for gcc) or -xldscope=hidden (for sun cc) to CFLAGS then using the CJSON_API_VISIBILITY flag to "export" the same symbols the way CJSON_EXPORT_SYMBOLS does */ #define CJSON_CDECL __cdecl #define CJSON_STDCALL __stdcall /* export symbols by default, this is necessary for copy pasting the C and header file */ #if !defined(CJSON_HIDE_SYMBOLS) && !defined(CJSON_IMPORT_SYMBOLS) && !defined(CJSON_EXPORT_SYMBOLS) #define CJSON_EXPORT_SYMBOLS #endif #if defined(CJSON_HIDE_SYMBOLS) #define CJSON_PUBLIC(type) type CJSON_STDCALL #elif defined(CJSON_EXPORT_SYMBOLS) #define CJSON_PUBLIC(type) __declspec(dllexport) type CJSON_STDCALL #elif defined(CJSON_IMPORT_SYMBOLS) #define CJSON_PUBLIC(type) __declspec(dllimport) type CJSON_STDCALL #endif #else /* !__WINDOWS__ */ #define CJSON_CDECL #define CJSON_STDCALL #if (defined(__GNUC__) || defined(__SUNPRO_CC) || defined (__SUNPRO_C)) && defined(CJSON_API_VISIBILITY) #define CJSON_PUBLIC(type) __attribute__((visibility("default"))) type #else #define CJSON_PUBLIC(type) type #endif #endif /* project version */ #define CJSON_VERSION_MAJOR 1 #define CJSON_VERSION_MINOR 7 #define CJSON_VERSION_PATCH 8 #include /* cJSON Types: */ #define cJSON_Invalid (0) #define cJSON_False (1 << 0) #define cJSON_True (1 << 1) #define cJSON_NULL (1 << 2) #define cJSON_Number (1 << 3) #define cJSON_String (1 << 4) #define cJSON_Array (1 << 5) #define cJSON_Object (1 << 6) #define cJSON_Raw (1 << 7) /* raw json */ #define cJSON_IsReference 256 #define cJSON_StringIsConst 512 /* The cJSON structure: */ typedef struct cJSON { /* next/prev allow you to walk array/object chains. Alternatively, use GetArraySize/GetArrayItem/GetObjectItem */ struct cJSON *next; struct cJSON *prev; /* An array or object item will have a child pointer pointing to a chain of the items in the array/object. */ struct cJSON *child; /* The type of the item, as above. */ int type; /* The item's string, if type==cJSON_String and type == cJSON_Raw */ char *valuestring; /* writing to valueint is DEPRECATED, use cJSON_SetNumberValue instead */ int valueint; /* The item's number, if type==cJSON_Number */ double valuedouble; /* The item's name string, if this item is the child of, or is in the list of subitems of an object. */ char *string; } cJSON; typedef struct cJSON_Hooks { /* malloc/free are CDECL on Windows regardless of the default calling convention of the compiler, so ensure the hooks allow passing those functions directly. */ void *(CJSON_CDECL *malloc_fn)(size_t sz); void (CJSON_CDECL *free_fn)(void *ptr); } cJSON_Hooks; typedef int cJSON_bool; /* Limits how deeply nested arrays/objects can be before cJSON rejects to parse them. * This is to prevent stack overflows. */ #ifndef CJSON_NESTING_LIMIT #define CJSON_NESTING_LIMIT 10 #endif /* returns the version of cJSON as a string */ CJSON_PUBLIC(const char*) cJSON_Version(void); /* Supply malloc, realloc and free functions to cJSON */ CJSON_PUBLIC(void) cJSON_InitHooks(cJSON_Hooks* hooks); /* Memory Management: the caller is always responsible to free the results from all variants of cJSON_Parse (with cJSON_Delete) and cJSON_Print (with stdlib free, cJSON_Hooks.free_fn, or cJSON_free as appropriate). The exception is cJSON_PrintPreallocated, where the caller has full responsibility of the buffer. */ /* Supply a block of JSON, and this returns a cJSON object you can interrogate. */ CJSON_PUBLIC(cJSON *) cJSON_Parse(const char *value); /* ParseWithOpts allows you to require (and check) that the JSON is null terminated, and to retrieve the pointer to the final byte parsed. */ /* If you supply a ptr in return_parse_end and parsing fails, then return_parse_end will contain a pointer to the error so will match cJSON_GetErrorPtr(). */ CJSON_PUBLIC(cJSON *) cJSON_ParseWithOpts(const char *value, const char **return_parse_end, cJSON_bool require_null_terminated); /* Render a cJSON entity to text for transfer/storage. */ CJSON_PUBLIC(char *) cJSON_Print(const cJSON *item); /* Render a cJSON entity to text for transfer/storage without any formatting. */ CJSON_PUBLIC(char *) cJSON_PrintUnformatted(const cJSON *item); /* Render a cJSON entity to text using a buffered strategy. prebuffer is a guess at the final size. guessing well reduces reallocation. fmt=0 gives unformatted, =1 gives formatted */ CJSON_PUBLIC(char *) cJSON_PrintBuffered(const cJSON *item, int prebuffer, cJSON_bool fmt); /* Render a cJSON entity to text using a buffer already allocated in memory with given length. Returns 1 on success and 0 on failure. */ /* NOTE: cJSON is not always 100% accurate in estimating how much memory it will use, so to be safe allocate 5 bytes more than you actually need */ CJSON_PUBLIC(cJSON_bool) cJSON_PrintPreallocated(cJSON *item, char *buffer, const int length, const cJSON_bool format); /* Delete a cJSON entity and all subentities. */ CJSON_PUBLIC(void) cJSON_Delete(cJSON *c); /* Returns the number of items in an array (or object). */ CJSON_PUBLIC(int) cJSON_GetArraySize(const cJSON *array); /* Retrieve item number "index" from array "array". Returns NULL if unsuccessful. */ CJSON_PUBLIC(cJSON *) cJSON_GetArrayItem(const cJSON *array, int index); /* Get item "string" from object. Case insensitive. */ CJSON_PUBLIC(cJSON *) cJSON_GetObjectItem(const cJSON * const object, const char * const string); CJSON_PUBLIC(cJSON *) cJSON_GetObjectItemCaseSensitive(const cJSON * const object, const char * const string); CJSON_PUBLIC(cJSON_bool) cJSON_HasObjectItem(const cJSON *object, const char *string); /* For analysing failed parses. This returns a pointer to the parse error. You'll probably need to look a few chars back to make sense of it. Defined when cJSON_Parse() returns 0. 0 when cJSON_Parse() succeeds. */ CJSON_PUBLIC(const char *) cJSON_GetErrorPtr(void); /* Check if the item is a string and return its valuestring */ CJSON_PUBLIC(char *) cJSON_GetStringValue(cJSON *item); /* These functions check the type of an item */ CJSON_PUBLIC(cJSON_bool) cJSON_IsInvalid(const cJSON * const item); CJSON_PUBLIC(cJSON_bool) cJSON_IsFalse(const cJSON * const item); CJSON_PUBLIC(cJSON_bool) cJSON_IsTrue(const cJSON * const item); CJSON_PUBLIC(cJSON_bool) cJSON_IsBool(const cJSON * const item); CJSON_PUBLIC(cJSON_bool) cJSON_IsNull(const cJSON * const item); CJSON_PUBLIC(cJSON_bool) cJSON_IsNumber(const cJSON * const item); CJSON_PUBLIC(cJSON_bool) cJSON_IsString(const cJSON * const item); CJSON_PUBLIC(cJSON_bool) cJSON_IsArray(const cJSON * const item); CJSON_PUBLIC(cJSON_bool) cJSON_IsObject(const cJSON * const item); CJSON_PUBLIC(cJSON_bool) cJSON_IsRaw(const cJSON * const item); /* These calls create a cJSON item of the appropriate type. */ CJSON_PUBLIC(cJSON *) cJSON_CreateNull(void); CJSON_PUBLIC(cJSON *) cJSON_CreateTrue(void); CJSON_PUBLIC(cJSON *) cJSON_CreateFalse(void); CJSON_PUBLIC(cJSON *) cJSON_CreateBool(cJSON_bool boolean); CJSON_PUBLIC(cJSON *) cJSON_CreateNumber(double num); CJSON_PUBLIC(cJSON *) cJSON_CreateString(const char *string); /* raw json */ CJSON_PUBLIC(cJSON *) cJSON_CreateRaw(const char *raw); CJSON_PUBLIC(cJSON *) cJSON_CreateArray(void); CJSON_PUBLIC(cJSON *) cJSON_CreateObject(void); /* Create a string where valuestring references a string so * it will not be freed by cJSON_Delete */ CJSON_PUBLIC(cJSON *) cJSON_CreateStringReference(const char *string); /* Create an object/arrray that only references it's elements so * they will not be freed by cJSON_Delete */ CJSON_PUBLIC(cJSON *) cJSON_CreateObjectReference(const cJSON *child); CJSON_PUBLIC(cJSON *) cJSON_CreateArrayReference(const cJSON *child); /* These utilities create an Array of count items. */ CJSON_PUBLIC(cJSON *) cJSON_CreateIntArray(const int *numbers, int count); CJSON_PUBLIC(cJSON *) cJSON_CreateFloatArray(const float *numbers, int count); CJSON_PUBLIC(cJSON *) cJSON_CreateDoubleArray(const double *numbers, int count); CJSON_PUBLIC(cJSON *) cJSON_CreateStringArray(const char **strings, int count); /* Append item to the specified array/object. */ CJSON_PUBLIC(void) cJSON_AddItemToArray(cJSON *array, cJSON *item); CJSON_PUBLIC(void) cJSON_AddItemToObject(cJSON *object, const char *string, cJSON *item); /* Use this when string is definitely const (i.e. a literal, or as good as), and will definitely survive the cJSON object. * WARNING: When this function was used, make sure to always check that (item->type & cJSON_StringIsConst) is zero before * writing to `item->string` */ CJSON_PUBLIC(void) cJSON_AddItemToObjectCS(cJSON *object, const char *string, cJSON *item); /* Append reference to item to the specified array/object. Use this when you want to add an existing cJSON to a new cJSON, but don't want to corrupt your existing cJSON. */ CJSON_PUBLIC(void) cJSON_AddItemReferenceToArray(cJSON *array, cJSON *item); CJSON_PUBLIC(void) cJSON_AddItemReferenceToObject(cJSON *object, const char *string, cJSON *item); /* Remove/Detatch items from Arrays/Objects. */ CJSON_PUBLIC(cJSON *) cJSON_DetachItemViaPointer(cJSON *parent, cJSON * const item); CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromArray(cJSON *array, int which); CJSON_PUBLIC(void) cJSON_DeleteItemFromArray(cJSON *array, int which); CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromObject(cJSON *object, const char *string); CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromObjectCaseSensitive(cJSON *object, const char *string); CJSON_PUBLIC(void) cJSON_DeleteItemFromObject(cJSON *object, const char *string); CJSON_PUBLIC(void) cJSON_DeleteItemFromObjectCaseSensitive(cJSON *object, const char *string); /* Update array items. */ CJSON_PUBLIC(void) cJSON_InsertItemInArray(cJSON *array, int which, cJSON *newitem); /* Shifts pre-existing items to the right. */ CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemViaPointer(cJSON * const parent, cJSON * const item, cJSON * replacement); CJSON_PUBLIC(void) cJSON_ReplaceItemInArray(cJSON *array, int which, cJSON *newitem); CJSON_PUBLIC(void) cJSON_ReplaceItemInObject(cJSON *object,const char *string,cJSON *newitem); CJSON_PUBLIC(void) cJSON_ReplaceItemInObjectCaseSensitive(cJSON *object,const char *string,cJSON *newitem); /* Duplicate a cJSON item */ CJSON_PUBLIC(cJSON *) cJSON_Duplicate(const cJSON *item, cJSON_bool recurse); /* Duplicate will create a new, identical cJSON item to the one you pass, in new memory that will need to be released. With recurse!=0, it will duplicate any children connected to the item. The item->next and ->prev pointers are always zero on return from Duplicate. */ /* Recursively compare two cJSON items for equality. If either a or b is NULL or invalid, they will be considered unequal. * case_sensitive determines if object keys are treated case sensitive (1) or case insensitive (0) */ CJSON_PUBLIC(cJSON_bool) cJSON_Compare(const cJSON * const a, const cJSON * const b, const cJSON_bool case_sensitive); CJSON_PUBLIC(void) cJSON_Minify(char *json); /* Helper functions for creating and adding items to an object at the same time. * They return the added item or NULL on failure. */ CJSON_PUBLIC(cJSON*) cJSON_AddNullToObject(cJSON * const object, const char * const name); CJSON_PUBLIC(cJSON*) cJSON_AddTrueToObject(cJSON * const object, const char * const name); CJSON_PUBLIC(cJSON*) cJSON_AddFalseToObject(cJSON * const object, const char * const name); CJSON_PUBLIC(cJSON*) cJSON_AddBoolToObject(cJSON * const object, const char * const name, const cJSON_bool boolean); CJSON_PUBLIC(cJSON*) cJSON_AddNumberToObject(cJSON * const object, const char * const name, const double number); CJSON_PUBLIC(cJSON*) cJSON_AddStringToObject(cJSON * const object, const char * const name, const char * const string); CJSON_PUBLIC(cJSON*) cJSON_AddRawToObject(cJSON * const object, const char * const name, const char * const raw); CJSON_PUBLIC(cJSON*) cJSON_AddObjectToObject(cJSON * const object, const char * const name); CJSON_PUBLIC(cJSON*) cJSON_AddArrayToObject(cJSON * const object, const char * const name); /* When assigning an integer value, it needs to be propagated to valuedouble too. */ #define cJSON_SetIntValue(object, number) ((object) ? (object)->valueint = (object)->valuedouble = (number) : (number)) /* helper for the cJSON_SetNumberValue macro */ CJSON_PUBLIC(double) cJSON_SetNumberHelper(cJSON *object, double number); #define cJSON_SetNumberValue(object, number) ((object != NULL) ? cJSON_SetNumberHelper(object, (double)number) : (number)) /* Macro for iterating over an array or object */ #define cJSON_ArrayForEach(element, array) for(element = (array != NULL) ? (array)->child : NULL; element != NULL; element = element->next) /* malloc/free objects using the malloc/free functions that have been set with cJSON_InitHooks */ CJSON_PUBLIC(void *) cJSON_malloc(size_t size); CJSON_PUBLIC(void) cJSON_free(void *object); #ifdef __cplusplus } #endif #endif ================================================ FILE: Huawei_LiteOS/components/lib/libc/errno.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ /* Includes -----------------------------------------------------------------*/ #include "los_config.h" #include "los_task.h" #include "los_printf.h" /* Typedefs -----------------------------------------------------------------*/ typedef struct TaskReent { int errno; } TaskReent; /* Local variables ----------------------------------------------------------*/ static TaskReent g_task_reent[LOSCFG_BASE_CORE_TSK_LIMIT + 1]; /* Public functions ---------------------------------------------------------*/ int *task_errno(void) { UINT32 taskid = LOS_CurTaskIDGet(); if (taskid <= LOSCFG_BASE_CORE_TSK_LIMIT) { return &g_task_reent[taskid].errno; } else { PRINT_WARN("TaskID[%d] is invalid\n", taskid); return &g_task_reent[0].errno; } } ================================================ FILE: Huawei_LiteOS/components/lib/libc/malloc.c ================================================ /************************************************************************ * Copyright (c) <2013-2015>, * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice,this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice,this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. ************************************************************************/ /************************************************************************ * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, * which might include those applicable to Huawei LiteOS of U.S. and the country * in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in * compliance with such applicable export control laws and regulations. ************************************************************************/ #include "stdlib.h" #include "los_memory.h" #include "string.h" #if defined(LOS_LIBC_MALLOC_ALIGN) && !defined(LOS_LIBC_MALLOC_ALIGN_SIZE) #error "macro LOS_LIBC_MALLOC_ALIGN_SIZE undefined" #endif /***************************************************************************** Function : free Description : Deallocates the memory previously allocated by a call to calloc, malloc, or realloc. The argument ptr points to the space that was previously allocated. If ptr points to a memory block that was not allocated with calloc, malloc, or realloc, or is a space that has been deallocated, then the result is undefined. Input : [1] void *ptr, pointed to the memory need to free. Output : nothing. Return : No value is returned. *****************************************************************************/ void free(void *ptr) { if (ptr == NULL) return; LOS_MemFree((void *)OS_SYS_MEM_ADDR, ptr);/*lint !e534*/ } /***************************************************************************** Function : malloc Description : Allocates the requested memory and returns a pointer to it. The requested size is size bytes. The value of the space is indeterminate. Input : [1] size_t size, spcified the size need to allocate. Output : nothing. Return : On success a pointer to the requested space is returned. On failure a null pointer is returned. *****************************************************************************/ void *malloc(size_t size) /*lint !e31 !e10*/ { void *ptr = NULL; /*lint !e64 !e10*/ if (size == 0) return NULL; /*lint !e64*/ #if defined(LOS_LIBC_MALLOC_ALIGN) ptr = LOS_MemAllocAlign((void *)OS_SYS_MEM_ADDR, (UINT32)size, LOS_LIBC_MALLOC_ALIGN_SIZE); #else ptr = LOS_MemAlloc((void *)OS_SYS_MEM_ADDR, (UINT32)size); #endif return ptr; } void *zalloc(size_t size) /*lint !e10*/ { void *ptr = malloc (size); if (ptr != NULL) { memset((void *)ptr, (int)0, size); } return ptr; } /***************************************************************************** Function : calloc Description : Allocates the requested memory and returns a pointer to it. The requested size is nitems each size bytes long (total memory requested is nitems*size). The space is initialized to all zero bits. Input : [1] size_t nitems, [2] size_t size, Output : nothing. Return : On success a pointer to the requested space is returned. On failure a null pointer is returned. *****************************************************************************/ void *calloc(size_t nitems, size_t size) /*lint !e578*/ { return zalloc(nitems * size); } /***************************************************************************** Function : memalign Description : allocates a block of size bytes whose address is a multiple of boundary. The boundary must be a power of two! Input : [1] size_t size, spcified the size need to allocate. [2] size_t boundary, the returned memory address will be a multiple of boundary. This argument must be a power of two. This property is not checked by memalign, so misuse may result in random runtime errors. Output : nothing. Return : On success a pointer to the requested space is returned. On failure a null pointer is returned. *****************************************************************************/ void *memalign (size_t boundary, size_t size) /*lint !e18 !e578*/ { /*lint !e18 !e578*/ void *ptr = NULL; if(size == 0) return NULL; /*lint !e64*/ ptr = LOS_MemAllocAlign((void *)OS_SYS_MEM_ADDR, (UINT32)size, (UINT32)boundary); return ptr; /*lint !e64*/ } /***************************************************************************** Function : realloc Description : Attempts to resize the memory block pointed to by ptr that was previously allocated with a call to malloc or calloc. The contents pointed to by ptr are unchanged. If the value of size is greater than the previous size of the block, then the additional bytes have an undeterminate value. If the value of size is less than the previous size of the block, then the difference of bytes at the end of the block are freed. If ptr is null, then it behaves like malloc. If ptr points to a memory block that was not allocated with calloc or malloc, or is a space that has been deallocated, then the result is undefined. If the new space cannot be allocated, then the contents pointed to by ptr are unchanged. If size is zero, then the memory block is completely freed. Input : [1] void *ptr, pointed to the memory which need to remalloc. [2] size_t size, specified the size to remalloc. Output : nothing. Return : On success a pointer to the memory block is returned (which may be in a different location as before). On failure or if size is zero, a null pointer is returned. *****************************************************************************/ void *realloc(void *ptr, size_t size) { if (ptr == NULL) { return malloc(size); /*lint !e64*/ } if (size == 0) { free(ptr); return NULL; } return LOS_MemRealloc((void *)OS_SYS_MEM_ADDR, (void *)ptr, (UINT32)size); } #if OS_SYS_NOCACHEMEM_SIZE /***************************************************************************** Function : nocache_free Description : Deallocates the memory previously allocated by a call to calloc, malloc, or realloc. The argument ptr points to the space that was previously allocated. If ptr points to a memory block that was not allocated with calloc, malloc, or realloc, or is a space that has been deallocated, then the result is undefined. Input : [1] void *ptr, pointed to the memory need to free. Output : nothing. Return : No value is returned. *****************************************************************************/ void nocache_free(void *ptr) { if(ptr == NULL) return; LOS_MemFree((void *)OS_SYS_NOCACHEMEM_ADDR, ptr); } /***************************************************************************** Function : nocache_malloc Description : Allocates the requested memory and returns a pointer to it. The requested size is size bytes. The value of the space is indeterminate. Input : [1] size_t size, spcified the size need to allocate. Output : nothing. Return : On success a pointer to the requested space is returned. On failure a null pointer is returned. *****************************************************************************/ void *nocache_malloc(size_t size) { void *ptr = NULL; if(size == 0) return NULL; ptr = LOS_MemAlloc((void *)OS_SYS_NOCACHEMEM_ADDR, (UINT32)size); return ptr; } void *nocache_zalloc(size_t size) { void *ptr = nocache_malloc(size); if (ptr != NULL) { memset((void *)ptr, (int)0, size); } return ptr; } /***************************************************************************** Function : nocache_calloc Description : Allocates the requested memory and returns a pointer to it. The requested size is nitems each size bytes long (total memory requested is nitems*size). The space is initialized to all zero bits. Input : [1] size_t nitems, [2] size_t size, Output : nothing. Return : On success a pointer to the requested space is returned. On failure a null pointer is returned. *****************************************************************************/ void *nocache_calloc(size_t nitems, size_t size) { return nocache_zalloc (nitems * size); } /***************************************************************************** Function : nocache_realloc Description : Attempts to resize the memory block pointed to by ptr that was previously allocated with a call to malloc or calloc. The contents pointed to by ptr are unchanged. If the value of size is greater than the previous size of the block, then the additional bytes have an undeterminate value. If the value of size is less than the previous size of the block, then the difference of bytes at the end of the block are freed. If ptr is null, then it behaves like malloc. If ptr points to a memory block that was not allocated with calloc or malloc, or is a space that has been deallocated, then the result is undefined. If the new space cannot be allocated, then the contents pointed to by ptr are unchanged. If size is zero, then the memory block is completely freed. Input : [1] void *ptr, pointed to the memory which need to remalloc. [2] size_t size, specified the size to remalloc. Output : nothing. Return : On success a pointer to the memory block is returned (which may be in a different location as before). On failure or if size is zero, a null pointer is returned. *****************************************************************************/ void *nocache_realloc(void *ptr, size_t size) { if (ptr == NULL) { ptr = malloc(size); return ptr; } if (size == 0) { free(ptr); return NULL; } return LOS_MemRealloc((void *)OS_SYS_NOCACHEMEM_ADDR, (void *)ptr, (UINT32)size); } #endif /* EOF malloc.c */ ================================================ FILE: Huawei_LiteOS/components/lib/libc/newlib_stub.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2013-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include #include #include #include #include #include #include #include #include #include "fs/los_vfs.h" #include "los_config.h" int _execve_r(struct _reent *ptr, const char *name, char *const *argv, char *const *env) { /* not support */ ptr->_errno = ENOTSUP; return -1; } _CLOCK_T_ _times_r(struct _reent *ptr, struct tms *ptms) { /* not support */ ptr->_errno = ENOTSUP; return -1; } int _unlink_r(struct _reent *ptr, const char *file) { return los_unlink (file); } int _wait_r(struct _reent *ptr, int *status) { /* not support */ ptr->_errno = ENOTSUP; return -1; } int _gettimeofday_r(struct _reent *ptr, struct timeval *tv, void *__tzp) { /* not support */ ptr->_errno = ENOTSUP; return -1; } void *_malloc_r(struct _reent *ptr, size_t size) { return malloc(size); } void *_realloc_r(struct _reent *ptr, void *old, size_t newlen) { return realloc (old, newlen); } void *_calloc_r(struct _reent *ptr, size_t size, size_t len) { return calloc(size, len); } void _free_r(struct _reent *ptr, void *addr) { free(addr); } void _exit(int status) { while (1); } void _system(const char *s) { return; } void abort(void) { while (1); } ================================================ FILE: Huawei_LiteOS/components/log/atiny_log.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include "log/atiny_log.h" static atiny_log_e g_atiny_log_level = LOG_ERR; static const char *g_log_names[] = { "DEBUG", "INFO", "WARNING", "ERR", "FATAL", }; void atiny_set_log_level(atiny_log_e level) { g_atiny_log_level = level; } atiny_log_e atiny_get_log_level(void) { return g_atiny_log_level; } const char *atiny_get_log_level_name(atiny_log_e log_level) { if (log_level >= LOG_MAX) { return "UNKOWN"; } return g_log_names[log_level]; } ================================================ FILE: Huawei_LiteOS/components/net/at_device/emtc_bg36/bg36.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include #include #include "bg36.h" extern at_task at; #define MAX_BG36_SOCK_NUM 11 at_config at_user_conf = { .name = AT_MODU_NAME, .usart_port = AT_USART_PORT, .buardrate = AT_BUARDRATE, .linkid_num = MAX_BG36_SOCK_NUM, .user_buf_len = MAX_AT_USERDATA_LEN, .cmd_begin = AT_CMD_BEGIN, .line_end = AT_LINE_END, .mux_mode = 1, //support multi connection mode .timeout = BG36_TIMEOUT, // ms }; emtc_socket_info sockinfo[MAX_BG36_SOCK_NUM]; int bg36_cmd(char *cmd, int32_t len, const char *suffix, char *resp_buf, int* resp_len) { AT_LOG("bg36 cmd:%s len:%d",cmd, (int)len); return at.cmd((int8_t *)cmd, len, suffix, resp_buf, resp_len); } static int bg36_close_sock(int sockid) { char *cmd = "AT+QICLOSE="; char buf[64]; int cmd_len; cmd_len = snprintf(buf, sizeof(buf), "%s%d\r", cmd, sockid); return bg36_cmd(buf, cmd_len, "OK", NULL,NULL); } //Direct Push Mode int32_t bg36_data_handler(void *arg, int8_t *buf, int32_t len) { int32_t sockid = 0; int32_t data_len = 0; const char *p1 = NULL; const char *p2 = NULL; QUEUE_BUFF qbuf; int32_t ret = 0; int32_t offset = 0; while(offset < len) { p1 = strstr((char *)(buf+offset), "recv"); if (p1 == NULL) { AT_LOG("buf done, offset:%ld len:%ld",offset, len); return AT_OK; } p1 += strlen("\"recv\""); sockid = chartoint(p1+1); if (sockid >= MAX_BG36_SOCK_NUM || sockinfo[sockid].used_flag == false) { AT_LOG("invalid sock id %ld", sockid); return AT_FAILED; } p2 = strstr((char *)(p1+1), ","); if (p2 == NULL) { AT_LOG("invalid data %ld", sockid); return AT_FAILED; } data_len = chartoint(p2+1); if (data_len > AT_DATA_LEN*2 || data_len <= 0) { AT_LOG("datalen too long:%ld", data_len); return AT_FAILED; } qbuf.addr = at_malloc(data_len); if (qbuf.addr == NULL) { AT_LOG("at_malloc null"); return AT_OK; } p1 = strstr(p2, "\r\n"); if (p1 != NULL) { memcpy(qbuf.addr, p1+2, data_len); qbuf.len = data_len; ret = LOS_QueueWriteCopy(at.linkid[sockid].qid, &qbuf, sizeof(qbuf), 0); if (LOS_OK != ret) { AT_LOG("LOS_QueueWriteCopy failed! ret %ld", ret); at_free(qbuf.addr); } offset+=data_len+strlen("+QIURC: \"recv\","); } else { AT_LOG("recv data null!"); return AT_FAILED; } } return AT_OK; } int32_t bg36_cmd_match(const char *buf, char* featurestr,int len) { return (strstr((char *)buf, featurestr) != NULL) ? 0: -1; } int32_t bg36_create_socket(const int8_t * host, const int8_t *port, int32_t proto, char* service_type) { int rbuflen = 64; char inbuf[64] = {0}; char tmpbuf[32] = {0}; int conid = 0; int err = 0; char* str = NULL; int id = 0; int ret = 0; char cmd[64] = {0}; AT_LOG("port:%s\r\n", port); if (at.mux_mode != AT_MUXMODE_MULTI) { AT_LOG("Only support in multi mode!\r\n"); return AT_FAILED; } id = at.get_id(); if (id >= MAX_BG36_SOCK_NUM) { AT_LOG("sock num exceeded,socket is %d", id); return AT_FAILED; } (void)snprintf(cmd, 64, "%s,%d,\"%s\",\"%s\",%s,0,1\r", QIOPEN_SOCKET, id, service_type, host, port); ret = bg36_cmd(cmd, strlen(cmd), "+QIOPEN:", inbuf, &rbuflen); str = strstr(inbuf, "+QIOPEN:"); if (str == NULL || ret != AT_OK) { AT_LOG("QIOPEN no reply, sockid:%d", id); (void)bg36_close_sock((int)id); (void)LOS_TaskDelay(10000); ret = bg36_cmd(cmd, strlen(cmd), "+QIOPEN:", inbuf, &rbuflen); str = strstr(inbuf, "+QIOPEN:"); if (str == NULL || ret != AT_OK) { at.linkid[id].usable = AT_LINK_UNUSE; return AT_FAILED; } } ret = sscanf(str,"+QIOPEN: %d,%d%s", &conid, &err, tmpbuf); if(ret == -1 || err != 0 || conid != id) { AT_LOG("Create socket %d failed. conid:%d, ret %d, err:%d", id, conid, ret, err); (void)bg36_close_sock(conid); at.linkid[id].usable = AT_LINK_UNUSE; return AT_FAILED; } if (LOS_QueueCreate("dataQueue", 16, &at.linkid[id].qid, 0, sizeof(QUEUE_BUFF)) != LOS_OK) { AT_LOG("init dataQueue failed!"); (void)bg36_close_sock(conid); at.linkid[id].usable = AT_LINK_UNUSE; return AT_FAILED; } sockinfo[id].used_flag = true; AT_LOG("create socket %d success!",id); return id; } int32_t bg36_bind(const int8_t * host, const int8_t *port, int32_t proto) { return bg36_create_socket(host, port, proto, "TCP"); } int32_t bg36_connect(const int8_t * host, const int8_t *port, int32_t proto) { char *cmd2 = "AT+QISTATE=1,"; char cmd[64] = {0}; int sockid; sockid = bg36_create_socket(host, port, proto, "TCP"); if(sockid < 0 || sockid >= MAX_BG36_SOCK_NUM) { return AT_FAILED; } (void)snprintf(cmd, 64, "%s%d\r", cmd2, sockid); (void)bg36_cmd(cmd, strlen(cmd), "+QISTATE:", NULL, NULL); return sockid; } int32_t bg36_send(int32_t id , const uint8_t *buf, uint32_t len) { char *cmd1 = "AT+QISEND="; char cmd[64] = {0}; int ret; if (id < 0 || id >= MAX_BG36_SOCK_NUM || len >= MAX_SEND_DATA_LEN) { AT_LOG("invalid args sockid:%d len:%d",(int)id, (int)len); return AT_FAILED; } (void)snprintf(cmd, sizeof(cmd),"%s%d,%d%c",cmd1, (int)id, (int)len,'\r'); ret = bg36_cmd(cmd, strlen(cmd), ">", NULL, NULL); if(ret) { AT_LOG("socket invalid,no >"); return AT_FAILED; } ret = bg36_cmd((char *)buf, len, "OK", NULL, NULL); if(ret) { AT_LOG("data send failed"); return AT_FAILED; } return len; } static int32_t bg36_recv_timeout(int32_t id , uint8_t *buf, uint32_t len,char* ipaddr,int* port, int32_t timeout) { int rlen =0; int copylen =0; int ret; QUEUE_BUFF qbuf; UINT32 qlen = sizeof(QUEUE_BUFF); if (id >= MAX_BG36_SOCK_NUM) { AT_LOG("link id %d invalid", (int)id); return AT_FAILED; } if (sockinfo[id].buf == NULL) { ret = LOS_QueueReadCopy(at.linkid[id].qid, &qbuf, &qlen, timeout); if (ret != LOS_OK) { return AT_TIMEOUT; } AT_LOG("Read queue len:%d",(int)qbuf.len); sockinfo[id].buf = (char*)qbuf.addr; sockinfo[id].len = qbuf.len; sockinfo[id].offset = 0; } if(sockinfo[id].len - sockinfo[id].offset > len) { memcpy(buf, sockinfo[id].buf + sockinfo[id].offset, len); sockinfo[id].offset += len; return len; } else { copylen = sockinfo[id].len - sockinfo[id].offset; memcpy(buf, sockinfo[id].buf + sockinfo[id].offset, copylen); at_free(sockinfo[id].buf); sockinfo[id].offset = 0; sockinfo[id].buf = NULL; sockinfo[id].len = 0; rlen = copylen; while(rlen < len) { ret = LOS_QueueReadCopy(at.linkid[id].qid, &qbuf, &qlen, 0); if (ret == LOS_OK) { sockinfo[id].buf = (char*)qbuf.addr; sockinfo[id].len = qbuf.len; sockinfo[id].offset = 0; if(len-rlen < qbuf.len) { memcpy(buf+rlen, sockinfo[id].buf, len - rlen); sockinfo[id].offset = len - rlen; return len; } else { memcpy(buf+rlen, sockinfo[id].buf, qbuf.len); rlen += qbuf.len; at_free(sockinfo[id].buf); sockinfo[id].offset = 0; sockinfo[id].buf = NULL; sockinfo[id].len = 0; } } else { return rlen; } } return rlen; } } static int32_t bg36_recv(int32_t id , uint8_t *buf, uint32_t len) { return bg36_recv_timeout(id, buf, len, NULL, NULL, LOS_WAIT_FOREVER);/*lint !e569*/ } static int32_t bg36_close(int32_t id) { int ret; QUEUE_BUFF qbuf = {0}; char *cmd2 = "AT+QISTATE=1,"; char cmd[64] = {0}; UINT32 qlen = sizeof(QUEUE_BUFF); (void)snprintf(cmd, 64, "%s%d\r", cmd2, (int)id); (void)bg36_cmd(cmd, strlen(cmd), "+QISTATE:", NULL, NULL); ret = bg36_close_sock((int)id); if (ret != AT_OK) { AT_LOG("close no reply,continue. sockid:%d", (int)id); (void)LOS_TaskDelay(10000); (void)bg36_close_sock((int)id); (void)LOS_TaskDelay(10000); (void)bg36_cmd(cmd, strlen(cmd), "+QISTATE:", NULL, NULL); } sockinfo[id].used_flag = false; at.linkid[id].usable = false; if(sockinfo[id].buf != NULL) { at_free(sockinfo[id].buf); } do { qbuf.addr = NULL; ret = LOS_QueueReadCopy(at.linkid[id].qid, &qbuf, &qlen, 0); if (ret == LOS_OK && qbuf.addr != NULL) { at_free(qbuf.addr); } }while(ret == LOS_OK); ret = LOS_QueueDelete(at.linkid[id].qid); if (ret != LOS_OK) { AT_LOG("LOS_QueueDelete failed, ret is %d!,qid %d", ret, at.linkid[id].qid); } return ret; } static int32_t bg36_init(void) { int rbuflen = 64; char inbuf[64] = {0}; char tmpbuf[64] = {0}; int creg = 0; int i = 0; int ret; at.init(&at_user_conf); memset(sockinfo, 0, sizeof(emtc_socket_info) * MAX_BG36_SOCK_NUM);/*lint !e545*/ (void)at.oob_register(AT_DATAF_PREFIX, strlen(AT_DATAF_PREFIX), bg36_data_handler, bg36_cmd_match); (void)bg36_cmd(ATI, strlen(ATI), "OK", NULL, NULL); (void)bg36_cmd(ATE0, strlen(ATE0), "OK", NULL, NULL); (void)bg36_cmd(CPIN, strlen(CPIN), "+CPIN: READY", NULL, NULL); while(1) { (void)bg36_cmd(QUERYCFATT, strlen(QUERYCFATT), "+CGATT", inbuf,&rbuflen); if (strlen(inbuf)!=0) { ret = sscanf(inbuf,"\r\n+CGATT: %d\r\n%s",&creg,tmpbuf); if(ret == -1) { continue; } if (creg == 1) { break; } } (void)LOS_TaskDelay(100); memset(inbuf, 0, sizeof(inbuf)); } for( i = 0; i < MAX_BG36_SOCK_NUM; i++) { (void)bg36_close((int32_t)i);/*lint !e534*/ } return bg36_cmd(QIACTQUERY, strlen(QIACTQUERY), "OK", NULL, NULL); } at_adaptor_api emtc_bg36_interface = { .init = bg36_init, .bind = bg36_bind, .connect = bg36_connect, .send = bg36_send, .sendto = NULL, .recv_timeout = bg36_recv_timeout, .recv = bg36_recv, .recvfrom = NULL, .close = bg36_close, .recv_cb = NULL, .deinit = NULL, }; ================================================ FILE: Huawei_LiteOS/components/net/at_device/emtc_bg36/bg36.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef __EMTC_BG36_H__ #define __EMTC_BG36_H__ #include "at_frame/at_main.h" #define AT_MODU_NAME "BG36" #define AT_USART_PORT 3 #define AT_BUARDRATE 115200 #define BG36_TIMEOUT 10000 //ms #define MAX_AT_USERDATA_LEN (1024*4) #define MAX_SEND_DATA_LEN 1400 #define AT_LINE_END "\r" #define AT_CMD_BEGIN "\r\n" typedef struct emtc_socket_info_t { int len; int offset; char *buf; bool used_flag; }emtc_socket_info; #define ATI "ATI\r" #define ATE0 "ATE0\r" #define CMEE "AT+CMEE=2\r" #define QCFG "AT+QCFG=\"nwscanseq\",03\r" #define CPIN "AT+CPIN?\r" #define CREG "AT+CREG?\r" #define GETQICSGP "AT+QICSGP=1\r" #define SETCELL "AT+CGREG=2\r" #define QUERYCELL "AT+CGREG?\r" #define QICSGP "AT+QICSGP=1,1,\"HUAWEI.COM\",\"\",\"\",1\r" #define QIACT "AT+QIACT=1\r" #define QIACTQUERY "AT+QIACT?\r" #define CSQ "AT+CSQ\r" #define QIOPEN_SOCKET "AT+QIOPEN=1" #define QUERYCFATT "AT+CGATT?\r" #define AT_DATAF_PREFIX "+QIURC:" #endif ================================================ FILE: Huawei_LiteOS/components/net/at_device/gprs_sim900a/sim900a.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #if defined(WITH_AT_FRAMEWORK) #include "sim900a.h" extern at_task at; at_adaptor_api sim900a_interface; char prefix_name[15]; int32_t sim900a_echo_off(void) { return at.cmd((int8_t *)AT_CMD_ECHO_OFF, strlen(AT_CMD_ECHO_OFF), "OK\r\n", NULL,NULL); } int32_t sim900a_echo_on(void) { return at.cmd((int8_t *)AT_CMD_ECHO_ON, strlen(AT_CMD_ECHO_OFF), "OK\r\n", NULL,NULL); } int32_t sim900a_reset(void) { int32_t ret = 0; //at.cmd((int8_t*)AT_CMD_CLOSE,strlen(AT_CMD_CLOSE),"CLOSE OK","ERROR"); ret = at.cmd((int8_t *)AT_CMD_SHUT, strlen(AT_CMD_SHUT), "SHUT OK", NULL,NULL); return ret; } int32_t sim900a_set_mux_mode(int32_t m) { char cmd[64] = {0}; snprintf(cmd, 64, "%s=%d", AT_CMD_MUX, (int)m); return at.cmd((int8_t *)cmd, strlen(cmd), "OK", NULL,NULL); } int32_t sim900a_connect(const int8_t *host, const int8_t *port, int32_t proto) { int32_t ret = AT_FAILED; int32_t id = at.get_id(); sim900a_reset(); char cmd1[64] = {0}; snprintf(cmd1, 64, "%s=\"B\"", AT_CMD_CLASS); at.cmd((int8_t *)cmd1, strlen(cmd1), "OK", NULL,NULL); char cmd2[64] = {0}; snprintf(cmd2, 64, "%s=1,\"IP\",\"CMNET\"", AT_CMD_PDP_CONT); at.cmd((int8_t *)cmd2, strlen(cmd2), "OK", NULL,NULL); char cmd3[64] = {0}; snprintf(cmd3, 64, "%s=1", AT_CMD_PDP_ATT); at.cmd((int8_t *)cmd3, strlen(cmd3), "OK", NULL,NULL); char cmd4[64] = {0}; snprintf(cmd4, 64, "%s=1", AT_CMD_CIPHEAD); at.cmd((int8_t *)cmd4, strlen(cmd4), "OK", NULL,NULL); char cmd5[64] = {0}; AT_LOG_DEBUG("host:%s, port:%s", host, port); if (AT_MUXMODE_SINGLE == at.mux_mode) { snprintf(cmd5, 64, "%s=\"%s\",\"%s\",\"%s\"", AT_CMD_CONN, proto == ATINY_PROTO_UDP ? "UDP" : "TCP", host, port); } else { at.cmd((int8_t *)(AT_CMD_PDP_ACT"=1,1"), strlen(AT_CMD_PDP_ACT"=1,1"), "OK", NULL,NULL); at.cmd((int8_t *)AT_CMD_CSTT, strlen(AT_CMD_CSTT), "OK", NULL,NULL); at.cmd((int8_t *)AT_CMD_CIICR, strlen(AT_CMD_CIICR), "OK", NULL,NULL); at.cmd((int8_t *)AT_CMD_CIFSR, strlen(AT_CMD_CIFSR), "", NULL,NULL); snprintf(cmd5, 64, "%s=%ld,\"%s\",\"%s\",\"%s\"", AT_CMD_CONN, id, proto == ATINY_PROTO_UDP ? "UDP" : "TCP", host, port); } if (id < 0 || id >= AT_MAX_LINK_NUM) { AT_LOG("no vailed linkid for use(id = %ld)", id); return -1; } ret = LOS_QueueCreate("dataQueue", 16, &at.linkid[id].qid, 0, sizeof(QUEUE_BUFF)); if (ret != LOS_OK) { AT_LOG("init dataQueue failed!"); at.linkid[id].usable = AT_LINK_UNUSE; return -1; } at.cmd((int8_t *)cmd5, strlen(cmd5), "CONNECT OK", NULL,NULL); return id; } int32_t sim900a_recv_timeout(int32_t id, uint8_t *buf, uint32_t len, char* ipaddr,int* port, int32_t timeout) { uint32_t qlen = sizeof(QUEUE_BUFF); uint32_t rxlen = 0; (void)ipaddr; //gprs not need remote ip (void)port; //gprs not need remote port QUEUE_BUFF qbuf = {0, NULL}; AT_LOG("****at.linkid[id].qid=%d***\n", at.linkid[id].qid); int ret = LOS_QueueReadCopy(at.linkid[id].qid, (void *)&qbuf, (UINT32 *)&qlen, timeout); AT_LOG("ret = %x, len = %ld, id = %ld", ret, qbuf.len, id); if (ret != LOS_OK) { return AT_FAILED; } if (qbuf.len) { rxlen = (len < qbuf.len) ? len : qbuf.len; memcpy(buf, qbuf.addr, rxlen); at_free(qbuf.addr); } return rxlen; } int32_t sim900a_recv(int32_t id, uint8_t *buf, uint32_t len) { return sim900a_recv_timeout(id, buf, len, NULL,NULL,LOS_WAIT_FOREVER); } int32_t sim900a_send(int32_t id , const uint8_t *buf, uint32_t len) { int32_t ret = -1; char cmd[64] = {0}; if (AT_MUXMODE_SINGLE == at.mux_mode) { snprintf(cmd, 64, "%s=%ld", AT_CMD_SEND, len); } else { snprintf(cmd, 64, "%s=%ld,%ld", AT_CMD_SEND, id, len); } ret = at.write((int8_t *)cmd, (int8_t *)"SEND OK", (int8_t *)buf, len); return ret; } void sim900a_check(void) { //check module response while(AT_FAILED == at.cmd((int8_t *)AT_CMD_AT, strlen(AT_CMD_AT), "OK", NULL,NULL)) { printf("\r\ncheck module response unnormal\r\n"); printf("\r\nplease check the module pin connection and the power switch\r\n"); SIM900A_DELAY(500); } if(AT_FAILED != at.cmd((int8_t *)AT_CMD_CPIN, strlen(AT_CMD_CPIN), "OK", NULL,NULL)) { printf("detected sim card\n"); } if(AT_FAILED != at.cmd((int8_t *)AT_CMD_COPS, strlen(AT_CMD_COPS), "CHINA MOBILE", NULL,NULL)) { printf("registerd to the network\n"); } } int32_t sim900a_recv_cb(int32_t id) { return AT_FAILED; } int32_t sim900a_close(int32_t id) { char cmd[64] = {0}; if (AT_MUXMODE_SINGLE == at.mux_mode) { snprintf(cmd, 64, "%s", AT_CMD_CLOSE); } else { uint32_t qlen = sizeof(QUEUE_BUFF); QUEUE_BUFF qbuf = {0, NULL}; while(LOS_OK == LOS_QueueReadCopy(at.linkid[id].qid, (void *)&qbuf, (UINT32 *)&qlen, 10)) { if (qbuf.len) { at_free(qbuf.addr); memset(&qbuf, 0, sizeof(QUEUE_BUFF)); // don't use qlen } } (void)LOS_QueueDelete(at.linkid[id].qid); at.linkid[id].usable = 0; snprintf(cmd, 64, "%s=%ld", AT_CMD_CLOSE, id); } return at.cmd((int8_t *)cmd, strlen(cmd), "OK", NULL,NULL); } int32_t sim900a_data_handler(void *arg, int8_t *buf, int32_t len) { if (NULL == buf || len <= 0) { AT_LOG("param invailed!"); return -1; } AT_LOG("entry!"); //process data frame ,like +IPD,linkid,len:data int32_t ret = 0; int32_t linkid = 0, data_len = 0; char *p1, *p2; QUEUE_BUFF qbuf; p1 = (char *)buf; if (0 == memcmp(p1, prefix_name, strlen(prefix_name))) { p2 = strstr(p1, ","); if (NULL == p2) { AT_LOG("got data prefix invailed!"); goto END; } if (AT_MUXMODE_MULTI == at.mux_mode) { linkid = 0; for (p2++; *p2 <= '9' && *p2 >= '0'; p2++) { linkid = linkid * 10 + (*p2 - '0'); } } for (p2++; *p2 <= '9' && *p2 >= '0' ; p2++) { data_len = (data_len * 10 + (*p2 - '0')); } p2++; //over ':' if (data_len > len) { AT_LOG("error !! receive data not complete data_len:%ld len:%ld",data_len,len); goto END; } qbuf.addr = at_malloc(data_len); if (NULL == qbuf.addr) { AT_LOG("malloc for qbuf failed!"); goto END; } qbuf.len = data_len; if(AT_MUXMODE_MULTI == at.mux_mode) { p2++; p2++;//multi-connect prefix is +RECEIVE,0,13:\r\n+packet content } memcpy(qbuf.addr, p2, data_len); if (LOS_OK != (ret = LOS_QueueWriteCopy(at.linkid[linkid].qid, &qbuf, sizeof(QUEUE_BUFF), 0))) { AT_LOG("LOS_QueueWriteCopy failed! ret = %lx", ret); at_free(qbuf.addr); goto END; } ret = (p2 + data_len - (char *)buf); } END: return ret; } int32_t sim900a_cmd_match(const char *buf, char* featurestr,int len) { return memcmp(buf,featurestr,len); } int32_t sim900a_ini() { at_config at_user_conf = { .name = AT_MODU_NAME, .usart_port = AT_USART_PORT, .buardrate = AT_BUARDRATE, .linkid_num = AT_MAX_LINK_NUM, .user_buf_len = MAX_AT_USERDATA_LEN, .cmd_begin = AT_CMD_BEGIN, .line_end = AT_LINE_END, .mux_mode = 1, //support multi connection mode .timeout = AT_CMD_TIMEOUT, // ms }; at.init(&at_user_conf); //single and multi connect prefix is different if (AT_MUXMODE_MULTI == at.mux_mode) { memcpy(prefix_name, AT_DATAF_PREFIX_MULTI, sizeof(AT_DATAF_PREFIX_MULTI)); } else { memcpy(prefix_name, AT_DATAF_PREFIX, sizeof(AT_DATAF_PREFIX)); } at.oob_register((char *)prefix_name, strlen((char *)prefix_name), sim900a_data_handler,sim900a_cmd_match); sim900a_echo_off(); sim900a_check(); sim900a_reset(); sim900a_set_mux_mode(at.mux_mode); at.cmd((int8_t *)("AT+CIPMUX?"), strlen("AT+CIPMUX?"), "OK", NULL,NULL); return AT_OK; } int32_t sim900a_deinit(void) { int id = 0; if(NULL != at.linkid) { for(id = 0; id < AT_MAX_LINK_NUM; id++) { if(AT_LINK_INUSE == at.linkid[id].usable) { if(AT_OK != sim900a_close(id)) { AT_LOG("sim900a_close(%d) failed", id); } } } } at.deinit(); return AT_OK; } at_adaptor_api sim900a_interface = { .init = sim900a_ini, .connect = sim900a_connect, /*TCP or UDP connect*/ .send = sim900a_send, /*send data, if no response, retrun error*/ .recv_timeout = sim900a_recv_timeout, .recv = sim900a_recv, .close = sim900a_close,/*close connect*/ .recv_cb = sim900a_recv_cb,/*receive event handle, no available by now */ .deinit = sim900a_deinit, }; #endif //#if NETWORK_TYPE == SIM_900A ================================================ FILE: Huawei_LiteOS/components/net/at_device/gprs_sim900a/sim900a.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef __SIM900A_H__ #define __SIM900A_H__ #include "at_frame/at_main.h" #define AT_MODU_NAME "SIM900A" #define AT_USART_PORT 2 #define AT_BUARDRATE 115200 #define AT_CMD_TIMEOUT 10000 //ms #define AT_MAX_LINK_NUM 4 #define AT_LINE_END "\r" #define AT_CMD_BEGIN "\r\n" #define MAX_AT_USERDATA_LEN (1024*5) #define AT_CMD_AT "AT" #define AT_CMD_CPIN "AT+CPIN?"//check sim card #define AT_CMD_COPS "AT+COPS?"//check register network #define AT_CMD_CLOSE "AT+CIPCLOSE" #define AT_CMD_SHUT "AT+CIPSHUT" #define AT_CMD_ECHO_OFF "ATE0" #define AT_CMD_ECHO_ON "ATE1" #define AT_CMD_MUX "AT+CIPMUX" #define AT_CMD_CLASS "AT+CGCLASS"//set MS type #define AT_CMD_PDP_CONT "AT+CGDCONT"//configure pdp context #define AT_CMD_PDP_ATT "AT+CGATT"//pdp attach network #define AT_CMD_PDP_ACT "AT+CGACT"//active pdp context #define AT_CMD_CSTT "AT+CSTT"//start task #define AT_CMD_CIICR "AT+CIICR"//start gprs connect #define AT_CMD_CIFSR "AT+CIFSR"//get local ip #define AT_CMD_CIPHEAD "AT+CIPHEAD" #define AT_CMD_CONN "AT+CIPSTART" #define AT_CMD_SEND "AT+CIPSEND" #define AT_CMD_CLOSE "AT+CIPCLOSE" #define AT_DATAF_PREFIX "\r\n+IPD" #define AT_DATAF_PREFIX_MULTI "\r\n+RECEIVE" #define SIM900A_DELAY LOS_TaskDelay #endif /* __SIM900A_H__ */ ================================================ FILE: Huawei_LiteOS/components/net/at_device/nb_bc95/bc95.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #include #include #if defined(WITH_AT_FRAMEWORK) #include "at_device/bc95.h" #include "at_hal.h" //#include "bc95_test.h" extern at_task at; at_adaptor_api bc95_interface; extern char rbuf[AT_DATA_LEN]; extern char wbuf[AT_DATA_LEN]; typedef struct { uint32_t data_len; int link_idx; bool valid_flag; }nb_data_ind_info_s; char tmpbuf[AT_DATA_LEN]={0}; //transform to hex socket_info sockinfo[MAX_SOCK_NUM]; static nb_data_ind_info_s g_data_ind_info; #if defined ( __CC_ARM ) || defined ( __ICCARM__ ) static char *strnstr(const char *s1, const char *s2, size_t len) { size_t l2; l2 = strlen(s2); if (!l2) return (char *)s1; while (len >= l2) { len--; if (!memcmp(s1, s2, l2)) return (char *)s1; s1++; } return NULL; } #endif static int nb_alloc_sock(int socket) { int idx; for (uint32_t i = 0; i < MAX_SOCK_NUM; ++i) { if (sockinfo[i].used_flag && (sockinfo[i].socket == socket)) { return i; } } idx = (socket % MAX_SOCK_NUM); if (!sockinfo[idx].used_flag) { return idx; } for (uint32_t i = 0; i < MAX_SOCK_NUM; ++i) { if (!sockinfo[i].used_flag) { return i; } } AT_LOG("save socket fail %d", socket); return MAX_SOCK_NUM; } static int nb_sock_to_idx(int socket) { int idx; idx = (socket % MAX_SOCK_NUM); if (sockinfo[idx].used_flag && (socket == sockinfo[idx].socket)) { return idx; } for (uint32_t i = 0; i < MAX_SOCK_NUM; ++i) { if (sockinfo[i].used_flag && (socket == sockinfo[i].socket)) { return i; } } return MAX_SOCK_NUM; } int str_to_hex(const char *bufin, int len, char *bufout) { int i = 0; if (NULL == bufin || len <= 0 || NULL == bufout) { return -1; } for(i = 0; i < len; i++) { sprintf(bufout+i*2, "%02X", bufin[i]); } return 0; } void HexStrToStr(const unsigned char *source, unsigned char *dest, int sourceLen) { short i; unsigned char highByte, lowByte; for (i = 0; i < sourceLen; i += 2) { highByte = toupper(source[i]); lowByte = toupper(source[i + 1]); if (highByte > 0x39) highByte -= 0x37; else highByte -= 0x30; if (lowByte > 0x39) lowByte -= 0x37; else lowByte -= 0x30; dest[i / 2] = (highByte << 4) | lowByte; } return ; } int32_t nb_reboot(void) { // memset(sockinfo, 0, MAX_SOCK_NUM * sizeof(struct _socket_info_t)); return at.cmd((int8_t*)AT_NB_reboot, strlen(AT_NB_reboot), "OK", NULL,NULL); } int32_t nb_hw_detect(void)//"AT+CFUN?\r" { return at.cmd((int8_t*)AT_NB_hw_detect, strlen(AT_NB_hw_detect), "+CFUN:1", NULL,NULL); } int32_t nb_check_csq(void) { char *cmd = "AT+CSQ\r"; return at.cmd((int8_t*)cmd, strlen(cmd), "+CSQ:", NULL,NULL); } int32_t nb_set_cdpserver(char* host, char* port) { char *cmd = "AT+NCDP="; char *cmd2 = "AT+NCDP?"; char *cmdNNMI = "AT+NNMI=1\r"; char *cmdCMEE = "AT+CMEE=1\r"; //char *cmdCGP = "AT+CGPADDR"; char tmpbuf[128] = {0}; int ret = -1; char ipaddr[100] = {0}; if(strlen(host) > 70 || strlen(port) > 20 || host==NULL || port == NULL) { ret = at.cmd((int8_t*)cmdNNMI, strlen(cmdNNMI), "OK", NULL,NULL); ret = at.cmd((int8_t*)cmdCMEE, strlen(cmdCMEE), "OK", NULL,NULL); return ret; } snprintf(ipaddr, sizeof(ipaddr) - 1, "%s,%s\r", host, port); snprintf(tmpbuf, sizeof(tmpbuf) - 1, "%s%s%c", cmd, ipaddr, '\r'); ret = at.cmd((int8_t*)tmpbuf, strlen(tmpbuf), "OK", NULL,NULL); if(ret < 0) { return ret; } ret = at.cmd((int8_t*)cmd2, strlen(cmd2), ipaddr, NULL,NULL); //LOS_TaskDelay(1000); ret = at.cmd((int8_t*)cmdNNMI, strlen(cmdNNMI), "OK", NULL,NULL); //at.cmd((int8_t*)cmdCMEE, strlen(cmdCMEE), "OK", NULL, NULL); //ret = at.cmd((int8_t*)cmdCGP, strlen(cmdCGP), NULL, NULL); return ret; } int32_t nb_send_psk(char* pskid, char* psk) { char* cmds = "AT+QSECSWT";//AT+QSECSWT=1,100 OK char* cmdp = "AT+QSETPSK";//AT+QSETPSK=86775942,E6F4C799 OK sprintf(wbuf, "%s=%d,%d\r", cmds, 1, 100);//min at.cmd((int8_t*)wbuf, strlen(wbuf), "OK", NULL,NULL); snprintf(wbuf, AT_DATA_LEN, "%s=%s,%s\r", cmdp, pskid, psk); return at.cmd((int8_t*)wbuf, strlen(wbuf), "OK", NULL,NULL); } int32_t nb_set_no_encrypt(void) { char* cmd = "AT+QSECSWT=0\r"; return at.cmd((int8_t*)cmd, strlen(cmd), "OK", NULL,NULL); } #ifdef WITH_SOTA int sota_cmd(int8_t *cmd, int32_t len, const char *suffix, char *resp_buf, int* resp_len) { AT_LOG("sota_cmd:%s", cmd); LOS_MuxPend(at.cmd_mux, LOS_WAIT_FOREVER); at_transmit((uint8_t *)cmd, len, 1); LOS_MuxPost(at.cmd_mux); return AT_OK; } int nb_send_str(const char* buf, int len) { char *cmd1 = "AT+NMGS="; memset(wbuf, 0, AT_DATA_LEN); memset(rbuf, 0, AT_DATA_LEN); snprintf(wbuf, AT_DATA_LEN, "%s%d,%s%c",cmd1,(int)len/2,buf,'\r'); return sota_cmd((int8_t*)wbuf, strlen(wbuf), "OK", NULL,NULL); } #endif int32_t nb_send_payload(const char* buf, int len) { char *cmd1 = "AT+NMGS="; char *cmd2 = "AT+NQMGS\r"; int ret; char* str = NULL; int curcnt = 0; int rbuflen; static int sndcnt = 0; if(buf == NULL || len > AT_MAX_PAYLOADLEN) { AT_LOG("payload too long"); return -1; } memset(tmpbuf, 0, AT_DATA_LEN); memset(wbuf, 0, AT_DATA_LEN); str_to_hex(buf, len, tmpbuf); memset(rbuf, 0, AT_DATA_LEN); snprintf(wbuf, AT_DATA_LEN,"%s%d,%s%c",cmd1,(int)len,tmpbuf,'\r'); ret = at.cmd((int8_t*)wbuf, strlen(wbuf), "OK", NULL,NULL); if(ret < 0) return -1; ret = at.cmd((int8_t*)cmd2, strlen(cmd2), "SENT=", rbuf,&rbuflen); if(ret < 0) return -1; str = strstr(rbuf,"SENT="); if(str == NULL) return -1; sscanf(str,"SENT=%d,%s",&curcnt,wbuf); if(curcnt == sndcnt) return -1; sndcnt = curcnt; return ret; } int nb_query_ip(void) { char *cmd = "AT+CGPADDR\r"; return at.cmd((int8_t*)cmd, strlen(cmd), "+CGPADDR:0,", NULL,NULL); } int32_t nb_get_netstat(void) { char *cmd = "AT+CGATT?\r"; return at.cmd((int8_t*)cmd, strlen(cmd), "CGATT:1", NULL,NULL); } static int32_t nb_cmd_with_2_suffix(const int8_t *cmd, int len, const char* suffix_ok, const char* suffix_err, char *resp_buf, uint32_t* resp_len) { const char *suffix[2] = {0}; at_cmd_info_s cmd_info = {0}; suffix[0] = suffix_ok; suffix[1] = suffix_err; cmd_info.suffix = suffix; cmd_info.suffix_num = array_size(suffix); cmd_info.resp_buf = resp_buf; cmd_info.resp_len = resp_len; if (at.cmd_multi_suffix(cmd, len, &cmd_info) != AT_OK) { return AT_FAILED; } if (cmd_info.match_idx != 0) { AT_LOG("cmd_info.match_idx %d", cmd_info.match_idx); return AT_FAILED; } return AT_OK; } int32_t nb_create_sock(int port,int proto) { int socket; int rbuflen = AT_DATA_LEN; const char *cmdudp = "AT+NSOCR=DGRAM,17,";//udp const char *cmdtcp = "AT+NSOCR=STREAM,6,";//tcp int ret; char buf[64]; int cmd_len; if(proto!=17 && proto!=6) { AT_LOG("proto invalid!"); return -1; } memset(rbuf, 0, AT_DATA_LEN); if (proto == 17) { cmd_len = snprintf(buf, sizeof(buf), "%s%d,1\r", cmdudp, port);//udp } else { cmd_len = snprintf(buf, sizeof(buf), "%s%d,1\r", cmdtcp, port); } nb_cmd_with_2_suffix((int8_t*)buf, cmd_len, "OK", "ERROR", rbuf, (uint32_t *)&rbuflen); ret = sscanf(rbuf, "%d\r%s",&socket, tmpbuf); if ((2 == ret) && (socket >= 0) && (strnstr(tmpbuf, "OK", sizeof(tmpbuf)))) { return socket; } AT_LOG("sscanf fail,ret=%d,socket=%d", ret, socket); return -1; } static bool nb_is_addr_valid(const char *addr) { const int size = 4; int tmp[4]; int ret; ret = sscanf(addr, "%d.%d.%d.%d", &tmp[0], &tmp[1], &tmp[2], &tmp[3]); return (size == ret); } int nb_decompose_str(const char* str, int *readleft, int *out_sockid) { const char *tmp,*trans; int sockid; QUEUE_BUFF qbuf; int ret = AT_FAILED; int rlen; int link_id; tmp = strstr(str,","); if(tmp == NULL) { return AT_FAILED; } sockid = chartoint(str); trans = strstr(tmp+1,","); if(trans == NULL) { return AT_FAILED; } strncpy(qbuf.ipaddr,tmp+1,MIN((trans-tmp),AT_DATA_LEN/2)); qbuf.ipaddr[trans-tmp-1] = '\0'; if (!nb_is_addr_valid(qbuf.ipaddr)) { return AT_FAILED; } qbuf.port = chartoint((char*)(trans+1)); tmp = strstr(trans+1,","); if(tmp == NULL) { return AT_FAILED; } rlen = chartoint((char*)(tmp+1)); if(rlen >= AT_DATA_LEN/2 || rlen < 0) { AT_LOG("rlen %d", rlen); return AT_FAILED; } trans = strstr(tmp+1,","); if(trans == NULL) { return AT_FAILED; } tmp = strstr(trans+1,","); if (tmp == NULL) { return AT_FAILED; } *readleft = chartoint((char*)(tmp+1)); *out_sockid = sockid; link_id = nb_sock_to_idx(sockid); if (link_id >= MAX_SOCK_NUM) { AT_LOG("sockid invalid %d", sockid); return AT_OK; } qbuf.addr = at_malloc(rlen); if (qbuf.addr == NULL) { AT_LOG("at_malloc null"); return AT_OK; } HexStrToStr((const unsigned char*)(trans+1), qbuf.addr, (rlen)*2); qbuf.len = rlen; ret = LOS_QueueWriteCopy(at.linkid[link_id].qid, &qbuf, sizeof(qbuf), 0); if (LOS_OK != ret) { AT_LOG("LOS_QueueWriteCopy failed! ret %d", ret); at_free(qbuf.addr); } //AT_LOG("wwww write data,qid %d, len %ld, ret %d", at.linkid[link_id].qid, qbuf.len, ret); return AT_OK; } static void nb_close_sock(int sock) { const char *cmd = "AT+NSOCL="; char buf[64]; int cmd_len; cmd_len = snprintf(buf, sizeof(buf), "%s%d\r", cmd, sock); nb_cmd_with_2_suffix((int8_t*)buf, cmd_len, "OK", "ERROR", NULL,NULL); } static int nb_create_sock_link(int portnum, int *link_id) { int ret = 0; int sock; sock = nb_create_sock(portnum, UDP_PROTO); if(sock < 0) { AT_LOG("sock num exceeded,ret is %d", sock); return AT_FAILED; } ret = nb_alloc_sock(sock); if (ret >= MAX_SOCK_NUM) { AT_LOG("sock num exceeded,socket is %d", sock); goto CLOSE_SOCk; } if (LOS_QueueCreate("dataQueue", 16, &at.linkid[ret].qid, 0, sizeof(QUEUE_BUFF)) != LOS_OK) { AT_LOG("init dataQueue failed, ret is %d!",ret); goto CLOSE_SOCk; } *link_id = ret; sockinfo[ret].socket = sock; sockinfo[ret].used_flag = true; return AT_OK; CLOSE_SOCk: nb_close_sock(sock); return AT_FAILED; } int32_t nb_bind(const int8_t * host, const int8_t *port, int32_t proto) { int ret = 0; int portnum; (void)host; (void)proto; portnum = chartoint((char*)port); if (nb_create_sock_link(portnum, &ret) != AT_OK) { return AT_FAILED; } sockinfo[ret].localport = *(unsigned short*)portnum; return AT_OK; } int32_t nb_connect(const int8_t * host, const int8_t *port, int32_t proto) { int ret = 0; static uint16_t localport = NB_STAT_LOCALPORT; const int COAP_SEVER_PORT = 5683; if (nb_create_sock_link(localport, &ret) != AT_OK) { return AT_FAILED; } localport++; if (localport == COAP_SEVER_PORT || localport == (COAP_SEVER_PORT + 1)) { localport = 5685; } strncpy(sockinfo[ret].remoteip, (const char *)host, sizeof(sockinfo[ret].remoteip)); sockinfo[ret].remoteip[sizeof(sockinfo[ret].remoteip) - 1] = '\0'; sockinfo[ret].remoteport = chartoint((char*)port); AT_LOG("ret:%d remoteip:%s port:%d",ret,sockinfo[ret].remoteip,sockinfo[ret].remoteport); return ret; } int32_t nb_sendto(int32_t id , const uint8_t *buf, uint32_t len, char* ipaddr, int port) { char *cmd = "AT+NSOST="; int data_len = len/2; int cmd_len; if(buf == NULL || data_len > AT_MAX_PAYLOADLEN || id >= MAX_SOCK_NUM) { AT_LOG("invalid args"); return -1; } AT_LOG("id:%d remoteip:%s port:%d",(int)sockinfo[id].socket, ipaddr, port); memset(wbuf, 0, AT_DATA_LEN); memset(tmpbuf, 0, AT_DATA_LEN); str_to_hex((const char *)buf, len, tmpbuf); cmd_len = snprintf(wbuf, AT_DATA_LEN, "%s%d,%s,%d,%d,%s\r",cmd,(int)sockinfo[id].socket, ipaddr, port, (int)len, tmpbuf); if (nb_cmd_with_2_suffix((int8_t*)wbuf, cmd_len, "OK", "ERROR", NULL, NULL) != AT_OK) { return AT_FAILED; } return len; } int32_t nb_send(int32_t id , const uint8_t *buf, uint32_t len) { if (id >= MAX_SOCK_NUM) { AT_LOG("invalid args"); return AT_FAILED; } return nb_sendto(id , buf, len, sockinfo[id].remoteip,(int)sockinfo[id].remoteport); } int32_t nb_recv(int32_t id , uint8_t *buf, uint32_t len) { return nb_recv_timeout(id, buf, len,NULL,NULL, LOS_WAIT_FOREVER); } int32_t nb_recvfrom(int32_t id , uint8_t *buf, uint32_t len,char* ipaddr,int* port) { return nb_recv_timeout(id, buf, len, ipaddr,port,LOS_WAIT_FOREVER); } int32_t nb_recv_timeout(int32_t id , uint8_t *buf, uint32_t len,char* ipaddr,int* port, int32_t timeout) { int rlen = 0; int ret; QUEUE_BUFF qbuf; UINT32 qlen = sizeof(QUEUE_BUFF); if (id >= MAX_SOCK_NUM) { AT_LOG("link id %ld invalid", id); return AT_FAILED; } ret = LOS_QueueReadCopy(at.linkid[id].qid, &qbuf, &qlen, timeout); //AT_LOG("wwww LOS_QueueReadCopy data,qid %d, len %ld, ret %d", at.linkid[id].qid, qbuf.len, ret); if (ret != LOS_OK) { return AT_TIMEOUT; } if (('\0' == sockinfo[id].remoteip[0]) || (0 == sockinfo[id].remoteport)) { AT_LOG("update ip and port for link %ld", id); strncpy(sockinfo[id].remoteip, qbuf.ipaddr, sizeof(sockinfo[id].remoteip)); sockinfo[id].remoteip[sizeof(sockinfo[id].remoteip) - 1] = '\0'; sockinfo[id].remoteport = qbuf.port; } if(ipaddr != NULL) { memcpy(ipaddr,qbuf.ipaddr,strlen(qbuf.ipaddr)); *port = qbuf.port; } rlen = MIN(qbuf.len, len); //AT_LOG("recv data, %d", rlen); if (rlen){ memcpy(buf, qbuf.addr, rlen); at_free(qbuf.addr); } return rlen; } int32_t nb_close(int32_t id) { int ret; if ((id >= MAX_SOCK_NUM) || (!sockinfo[id].used_flag)) { AT_LOG("link id %ld invalid", id); return AT_FAILED; } nb_close_sock(sockinfo[id].socket); do { QUEUE_BUFF qbuf = {0}; UINT32 qlen = sizeof(QUEUE_BUFF); ret = LOS_QueueReadCopy(at.linkid[id].qid, &qbuf, &qlen, 0); if (ret == LOS_OK && qbuf.addr != NULL) { at_free(qbuf.addr); } }while(ret == LOS_OK); ret = LOS_QueueDelete(at.linkid[id].qid); if (ret != LOS_OK) { AT_LOG("LOS_QueueDelete failed, ret is %d!,qid %d", ret, at.linkid[id].qid); } (void)memset(&sockinfo[id], 0, sizeof(sockinfo[id])); return AT_OK; } int32_t nb_recv_cb(int32_t id) { return AT_FAILED; } static int32_t nb_init(void) { at_config at_user_conf = { .name = AT_MODU_NAME, .usart_port = AT_USART_PORT, .buardrate = AT_BUARDRATE, .linkid_num = AT_MAX_LINK_NUM, .user_buf_len = MAX_AT_USERDATA_LEN, .cmd_begin = AT_CMD_BEGIN, .line_end = AT_LINE_END, .mux_mode = 1, //support multi connection mode .timeout = AT_CMD_TIMEOUT, // ms }; at_set_config(&at_user_conf); memset(&sockinfo, 0, sizeof(sockinfo)); memset(&g_data_ind_info, 0, sizeof(g_data_ind_info)); at_reg_step_callback(&at, nb_step); return AT_OK; } int32_t nb_deinit(void) { for (int i = 0; i < MAX_SOCK_NUM; ++i) { if (sockinfo[i].used_flag) { nb_close(i); } } return nb_reboot(); } at_adaptor_api bc95_interface = { .init = nb_init, .bind = nb_bind, .connect = nb_connect, .send = nb_send, .sendto = nb_sendto, .recv_timeout = nb_recv_timeout, .recv = nb_recv, .recvfrom = nb_recvfrom, .close = nb_close, .recv_cb = nb_recv_cb, .deinit = nb_deinit, }; void nb_reattach(void) { (void)nb_cmd_with_2_suffix((int8_t*)CGATT, strlen(CGATT), "OK", "ERROR", NULL, NULL); (void)nb_cmd_with_2_suffix((int8_t*)CGATT_DEATTACH, strlen(CGATT_DEATTACH), "OK", "ERROR", NULL, NULL); LOS_TaskDelay(1000); (void)nb_cmd_with_2_suffix((int8_t*)CGATT_ATTACH, strlen(CGATT_ATTACH), "OK", "ERROR", NULL, NULL); } static int nb_cmd_rcv_data(int sockid, int readleft); static int32_t nb_handle_sock_data(const int8_t *data, uint32_t len) { (void) len; char *curr = (char *)data; if (strstr((char *) data, "ERROR") != NULL) { return AT_OK; } do { int readleft; int sockid; char *next = strstr(curr, "\r\n"); if (next == curr) { curr += 2; } if (next != NULL) { next += 2; } if (nb_decompose_str(curr, &readleft, &sockid) == AT_OK) { /* if (readleft != 0) { nb_cmd_rcv_data(sockid, readleft); }*/ return AT_OK; } curr = next; }while(curr); return AT_FAILED; } static int nb_cmd_rcv_data(int sockid, int readleft) { int cmdlen; char cmdbuf[40]; const char* cmd = "AT+NSORF="; const uint32_t timeout = 10; cmdlen = snprintf(cmdbuf, sizeof(cmdbuf), "%s%d,%d\r", cmd, sockid, readleft); return at_cmd_in_callback((int8_t*)cmdbuf, cmdlen, nb_handle_sock_data, timeout); } static int32_t nb_handle_data_ind(const char *buf) { int32_t sockid; int32_t data_len; const char *p1, *p2; int link_idx; p2 = strstr(buf, AT_DATAF_PREFIX); if (NULL == p2) { return AT_FAILED; } p2+=strlen(AT_DATAF_PREFIX); p1 = strstr(p2, ","); if (p1 == NULL) { return AT_FAILED; } sockid = chartoint(p2); data_len = chartoint(p1 + 1); link_idx = nb_sock_to_idx(sockid); if (link_idx >= MAX_SOCK_NUM) { AT_LOG("invalid sock id %ld", sockid); return AT_OK; } if (nb_cmd_rcv_data(sockid, data_len) != AT_OK) { g_data_ind_info.data_len = (uint32_t)data_len; g_data_ind_info.link_idx = link_idx; g_data_ind_info.valid_flag = true; } else { g_data_ind_info.valid_flag = false; } return AT_OK; } int32_t nb_cmd_match(const char *buf, char* featurestr,int len) { if (buf == NULL) { return AT_FAILED; } nb_handle_data_ind(buf); return AT_FAILED; } void nb_step(void) { if ((!g_data_ind_info.valid_flag) || (!sockinfo[g_data_ind_info.link_idx].used_flag)) { return; } if (nb_cmd_rcv_data(sockinfo[g_data_ind_info.link_idx].socket, g_data_ind_info.data_len) == AT_OK) { g_data_ind_info.valid_flag = false; } } #endif ================================================ FILE: Huawei_LiteOS/components/net/at_device/wifi_esp8266/esp8266.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #if defined(WITH_AT_FRAMEWORK) #include "esp8266.h" extern at_task at; int esp8266_cmd(int8_t *cmd, int32_t len, const char *suffix, char *resp_buf, int* resp_len) { return at.cmd(cmd, len, suffix, resp_buf, resp_len); } int32_t esp8266_echo_off(void) { return esp8266_cmd((int8_t *)AT_CMD_ECHO_OFF, strlen(AT_CMD_ECHO_OFF), "OK\r\n", NULL, NULL); } int32_t esp8266_reset(void) { return esp8266_cmd((int8_t *)AT_CMD_RST, strlen(AT_CMD_RST), "ready\r\n", NULL, NULL); } int32_t esp8266_choose_net_mode(enum_net_mode m) { char cmd[64] = {0}; snprintf(cmd, 64, "%s=%d", AT_CMD_CWMODE, (int)m); return esp8266_cmd((int8_t *)cmd, strlen(cmd), "OK\r\n", NULL, NULL); } int32_t esp8266_set_mux_mode(int32_t m) { char cmd[64] = {0}; snprintf(cmd, 64, "%s=%d", AT_CMD_MUX, (int)m); return esp8266_cmd((int8_t *)cmd, strlen(cmd), "OK\r\n", NULL, NULL); } int32_t esp8266_joinap(char *pssid, char *ppasswd) { char cmd[64] = {0}; snprintf(cmd, 64, "%s=\"%s\",\"%s\"", AT_CMD_JOINAP, pssid, ppasswd); return esp8266_cmd((int8_t *)cmd, strlen(cmd), "OK\r\n", NULL, NULL); } int32_t esp8266_connect(const int8_t *host, const int8_t *port, int32_t proto) { int32_t ret = AT_FAILED; int32_t id = 0; char cmd[64] = {0}; AT_LOG("host:%s, port:%s", host, port); if (AT_MUXMODE_SINGLE == at.mux_mode) { snprintf(cmd, 64, "%s=\"%s\",\"%s\",%s", AT_CMD_CONN, proto == ATINY_PROTO_UDP ? "UDP" : "TCP", host, port); } else { id = at.get_id(); if (id < 0 || id >= AT_MAX_LINK_NUM) { AT_LOG("no vailed linkid for use(id = %ld)", id); return AT_FAILED; } snprintf(cmd, 64, "%s=%ld,\"%s\",\"%s\",%s", AT_CMD_CONN, id, proto == ATINY_PROTO_UDP ? "UDP" : "TCP", host, port); } //init at_link memcpy(at.linkid[id].remote_ip, host, sizeof(at.linkid[id].remote_ip)); (void)sscanf((char*)port, "%d", &at.linkid[id].remote_port); ret = LOS_QueueCreate("dataQueue", 16, &at.linkid[id].qid, 0, sizeof(QUEUE_BUFF)); if (ret != LOS_OK) { AT_LOG("init dataQueue failed!"); at.linkid[id].usable = AT_LINK_UNUSE; return AT_FAILED; } ret = esp8266_cmd((int8_t *)cmd, strlen(cmd), "OK\r\n", NULL, NULL); if (AT_FAILED == ret) { AT_LOG("at.cmd return failed!"); (void)LOS_QueueDelete(at.linkid[id].qid); at.linkid[id].usable = AT_LINK_UNUSE; return AT_FAILED; } return id; } int32_t esp8266_send(int32_t id , const uint8_t *buf, uint32_t len) { int32_t ret = AT_FAILED; char cmd[64] = {0}; if (AT_MUXMODE_SINGLE == at.mux_mode) { snprintf(cmd, 64, "%s=%lu,\"%s\",%d", AT_CMD_SEND, len,at.linkid[0].remote_ip, at.linkid[0].remote_port); } else { snprintf(cmd, 64, "%s=%ld,%lu,\"%s\",%d", AT_CMD_SEND, id, len,at.linkid[id].remote_ip, at.linkid[id].remote_port); } // at.cmd(cmd, strlen(cmd), ">", NULL); ret = at.write((int8_t *)cmd, (int8_t *)"SEND OK\r\n", (int8_t *)buf, len); return ret; } int32_t esp8266_recv_timeout(int32_t id, uint8_t *buf, uint32_t len, char * host, int * port, int32_t timeout) { uint32_t qlen = sizeof(QUEUE_BUFF); uint32_t rxlen = 0; QUEUE_BUFF qbuf = {0, NULL}; int ret = LOS_QueueReadCopy(at.linkid[id].qid, (void *)&qbuf, (UINT32 *)&qlen, timeout); // AT_LOG("ret = %x, len = %ld, id = %ld, timeout = %d", ret, qbuf.len, id, timeout); if (ret != LOS_OK) { return AT_FAILED; } if (qbuf.len) { rxlen = (len < qbuf.len) ? len : qbuf.len; memcpy(buf, qbuf.addr, rxlen); at_free(qbuf.addr); } return rxlen; } int32_t esp8266_recv(int32_t id, uint8_t *buf, uint32_t len) { return esp8266_recv_timeout(id, buf, len, NULL, NULL, LOS_WAIT_FOREVER); } int32_t esp8266_close(int32_t id) { char cmd[64] = {0}; if(at.linkid[id].usable == AT_LINK_UNUSE) return 0; if (AT_MUXMODE_SINGLE == at.mux_mode) { snprintf(cmd, 64, "%s", AT_CMD_CLOSE); } else { uint32_t qlen = sizeof(QUEUE_BUFF); QUEUE_BUFF qbuf = {0, NULL}; while(LOS_OK == LOS_QueueReadCopy(at.linkid[id].qid, (void *)&qbuf, (UINT32 *)&qlen, 10)) { if (qbuf.len) { at_free(qbuf.addr); memset(&qbuf, 0, sizeof(QUEUE_BUFF)); // don't use qlen } } (void)LOS_QueueDelete(at.linkid[id].qid); memset(&at.linkid[id], 0, sizeof(at_link)); snprintf(cmd, 64, "%s=%ld", AT_CMD_CLOSE, id); } return esp8266_cmd((int8_t *)cmd, strlen(cmd), "OK\r\n", NULL, NULL); } int32_t esp8266_data_handler(void *arg, int8_t *buf, int32_t len) { if (NULL == buf || len <= 0) { AT_LOG("param invailed!"); return AT_FAILED; } AT_LOG("entry!"); //process data frame ,like +IPD,linkid,len:data int32_t ret = -1; int32_t linkid = 0, data_len = 0; int32_t remote_port = 0; char * remote_ip; char *p1, *p2; QUEUE_BUFF qbuf; p1 = (char *)buf; LOOP: if (0 == memcmp(p1, AT_DATAF_PREFIX, strlen(AT_DATAF_PREFIX))) { p2 = strstr(p1, ","); if (NULL == p2) { AT_LOG("got data prefix invailed!"); goto END; } if (AT_MUXMODE_MULTI == at.mux_mode) { linkid = 0; for (p2++; *p2 <= '9' && *p2 >= '0'; p2++) { linkid = linkid * 10 + (*p2 - '0'); } } data_len = 0; for (p2++; *p2 <= '9' && *p2 >= '0' ; p2++) { data_len = (data_len * 10 + (*p2 - '0')); } //remote ip:str remote_ip = (char *)at.linkid[linkid].remote_ip; for (p2++; *p2 != ',' ; p2++) { *(remote_ip++) = *p2; } //remote port remote_port = 0; for (p2++; *p2 <= '9' && *p2 >= '0' ; p2++) { remote_port = (remote_port * 10 + (*p2 - '0')); } at.linkid[linkid].remote_port = remote_port; p2++; //over ':' qbuf.addr = at_malloc(data_len); if (NULL == qbuf.addr) { AT_LOG("malloc for qbuf failed!"); goto END; } qbuf.len = data_len; memcpy(qbuf.addr, p2, data_len); if (LOS_OK != (ret = LOS_QueueWriteCopy(at.linkid[linkid].qid, &qbuf, sizeof(QUEUE_BUFF), 0))) { AT_LOG("LOS_QueueWriteCopy failed! ret = %lx", ret); at_free(qbuf.addr); goto END; } p1 = (p2 + data_len); if ((p1 - (char*)buf) < len) goto LOOP; } END: return 0; } int8_t esp8266_get_localip(int8_t *ip, int8_t *gw, int8_t *mask) /*get local IP*/ { char resp[512] = {0}; int len = 512; esp8266_cmd((int8_t *)AT_CMD_CHECK_IP, strlen((char *)AT_CMD_CHECK_IP), "OK", resp, &len); AT_LOG("resp:%s", resp); char *p1, *p2; p1 = strstr(resp, "ip"); if (ip && p1) { p1 = strstr(p1, "\""); p2 = strstr(p1 + 1, "\""); memcpy(ip, p1 + 1, p2 - p1 - 1); } p1 = strstr(resp, "gateway"); if (gw && p1) { p1 = strstr(p1, "\""); p2 = strstr(p1 + 1, "\""); memcpy(gw, p1 + 1, p2 - p1 - 1); } p1 = strstr(resp, "netmask"); if (mask && p1) { p1 = strstr(p1, "\""); p2 = strstr(p1 + 1, "\""); memcpy(mask, p1 + 1, p2 - p1 - 1); } // printf("get ip :%s", resp); return AT_OK; } int8_t esp8266_get_localmac(int8_t *mac) /*get local mac*/ { char resp[512] = {0}; char *p1, *p2; int len = 512; esp8266_cmd((int8_t *)AT_CMD_CHECK_MAC, strlen((char *)AT_CMD_CHECK_MAC), "OK", resp, &len); AT_LOG("resp:%s", resp); p1 = strstr(resp, ":"); if (mac && p1) { p1 = strstr(p1, "\""); p2 = strstr(p1 + 1, "\""); memcpy(mac, p1 + 1, p2 - p1 - 1); } // printf("get ip :%s", resp); return AT_OK; } int32_t esp8266_bind(const int8_t *host, const int8_t *port, int32_t proto) { int ret = AT_FAILED; int port_i = 0; char cmd[64] = {0}; (void)sscanf((char *)port, "%d", &port_i); AT_LOG("get port = %d\r\n", port_i); if (at.mux_mode != AT_MUXMODE_MULTI) { AT_LOG("Only support in multi mode!\r\n"); return -1; } int id = at.get_id(); ret = LOS_QueueCreate("dataQueue", 16, &at.linkid[id].qid, 0, sizeof(QUEUE_BUFF)); if (ret != LOS_OK) { AT_LOG("init dataQueue failed!"); at.linkid[id].usable = AT_LINK_UNUSE; return AT_FAILED; } snprintf(cmd, 64, "%s=%d,\"%s\",\"0.0.0.0\",0,%d,0", AT_CMD_CONN, id, proto == ATINY_PROTO_UDP ? "UDP" : "TCP", port_i); esp8266_cmd((int8_t *)cmd, strlen(cmd), "OK\r\n", NULL, NULL); return id; } int32_t esp8266_recv_cb(int32_t id) { return AT_FAILED; } int32_t esp8266_deinit(void) { int id = 0; if(NULL != at.linkid) { for(id = 0; id < AT_MAX_LINK_NUM; id++) { if(AT_LINK_INUSE == at.linkid[id].usable) { if(AT_OK != esp8266_close(id)) { AT_LOG("esp8266_close(%d) failed", id); } } } } at.deinit(); return AT_OK; } int32_t esp8266_show_dinfo(int32_t s) { char cmd[64] = {0}; snprintf(cmd, 64, "%s=%ld", AT_CMD_SHOW_DINFO, s); return esp8266_cmd((int8_t *)cmd, strlen(cmd), "OK\r\n", NULL, NULL); } int32_t esp8266_cmd_match(const char *buf, char* featurestr,int len) { return memcmp(buf,featurestr,len); } int32_t esp8266_init() { at_config at_user_conf = { .name = AT_MODU_NAME, .usart_port = AT_USART_PORT, .buardrate = AT_BUARDRATE, .linkid_num = AT_MAX_LINK_NUM, .user_buf_len = MAX_AT_USERDATA_LEN, .cmd_begin = AT_CMD_BEGIN, .line_end = AT_LINE_END, .mux_mode = 1, //support multi connection mode .timeout = AT_CMD_TIMEOUT, // ms }; at.init(&at_user_conf); //at.add_listener((int8_t*)AT_DATAF_PREFIX, NULL, esp8266_data_handler); at.oob_register(AT_DATAF_PREFIX, strlen(AT_DATAF_PREFIX), esp8266_data_handler, esp8266_cmd_match); esp8266_reset(); esp8266_echo_off(); esp8266_show_dinfo(1); esp8266_choose_net_mode(STA); while(AT_FAILED == esp8266_joinap(WIFI_SSID, WIFI_PASSWD)) { AT_LOG("connect ap failed, repeat..."); }; esp8266_set_mux_mode(at.mux_mode); static int8_t ip[32]; static int8_t gw[32]; static int8_t mac[32]; esp8266_get_localip(ip, gw, NULL); esp8266_get_localmac(mac); AT_LOG_DEBUG("get ip:%s, gw:%s mac:%s", ip, gw, mac); return AT_OK; } at_adaptor_api esp8266_interface = { .init = esp8266_init, .get_localmac = esp8266_get_localmac, /*get local MAC*/ .get_localip = esp8266_get_localip,/*get local IP*/ /*build TCP or UDP connection*/ .connect = esp8266_connect, .bind = esp8266_bind, .send = esp8266_send, .recv_timeout = esp8266_recv_timeout, .recv = esp8266_recv, .close = esp8266_close,/*close connection*/ .recv_cb = esp8266_recv_cb,/* operation for events, not implements yet */ .deinit = esp8266_deinit, }; #endif ================================================ FILE: Huawei_LiteOS/components/net/at_device/wifi_esp8266/esp8266.h ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #ifndef __ESP8266_H__ #define __ESP8266_H__ #include "at_frame/at_main.h" #define WIFI_SSID "APAP1234" #define WIFI_PASSWD "87654321" #define AT_MODU_NAME "ESP8266" #define AT_USART_PORT 3 #define AT_BUARDRATE 115200 #define AT_CMD_TIMEOUT 10000 //ms #define AT_MAX_LINK_NUM 4 #define AT_LINE_END "\r\n" #define AT_CMD_BEGIN "\r\n" #define MAX_AT_USERDATA_LEN (1024*5) #define AT_CMD_RST "AT+RST" #define AT_CMD_ECHO_OFF "ATE0" #define AT_CMD_CWMODE "AT+CWMODE_CUR" #define AT_CMD_JOINAP "AT+CWJAP_CUR" #define AT_CMD_MUX "AT+CIPMUX" #define AT_CMD_CONN "AT+CIPSTART" #define AT_CMD_SEND "AT+CIPSEND" #define AT_CMD_CLOSE "AT+CIPCLOSE" #define AT_CMD_CHECK_IP "AT+CIPSTA_CUR?" #define AT_CMD_CHECK_MAC "AT+CIPSTAMAC_CUR?" #define AT_CMD_SHOW_DINFO "AT+CIPDINFO" #define AT_DATAF_PREFIX "\r\n+IPD" typedef enum { STA = 1, AP, ATA_AP, }enum_net_mode; #endif ================================================ FILE: Huawei_LiteOS/components/net/at_frame/at_api.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #if defined(WITH_AT_FRAMEWORK) #include "at_frame/at_api.h" static at_adaptor_api *gp_at_adaptor_api = NULL; int32_t at_api_register(at_adaptor_api *api) { if (NULL == gp_at_adaptor_api) { gp_at_adaptor_api = api; if (gp_at_adaptor_api && gp_at_adaptor_api->init) { return gp_at_adaptor_api->init(); } } return 0; } int32_t at_api_bind(const char *host, const char *port, int proto) { int32_t ret = -1; if (gp_at_adaptor_api && gp_at_adaptor_api->bind) { ret = gp_at_adaptor_api->bind((int8_t *)host, (int8_t *)port, proto); } return ret; } int32_t at_api_connect(const char *host, const char *port, int proto) { int32_t ret = -1; if (gp_at_adaptor_api && gp_at_adaptor_api->connect) { ret = gp_at_adaptor_api->connect((int8_t *)host, (int8_t *)port, proto); } return ret; } int32_t at_api_send(int32_t id , const unsigned char *buf, uint32_t len) { if (gp_at_adaptor_api && gp_at_adaptor_api->send) { return gp_at_adaptor_api->send(id, buf, len); } return -1; } int32_t at_api_sendto(int32_t id , uint8_t *buf, uint32_t len,char* ipaddr,int port) { if (gp_at_adaptor_api && gp_at_adaptor_api->sendto) { return gp_at_adaptor_api->sendto(id, buf, len,ipaddr, port); } return -1; } int32_t at_api_recv(int32_t id, unsigned char *buf, size_t len) { if (gp_at_adaptor_api && gp_at_adaptor_api->recv) { return gp_at_adaptor_api->recv(id, buf, len); } return -1; } int32_t at_api_recv_timeout(int32_t id , uint8_t *buf, uint32_t len,char* ipaddr,int* port, int32_t timeout) { if (gp_at_adaptor_api && gp_at_adaptor_api->recv_timeout) { return gp_at_adaptor_api->recv_timeout(id , buf, len, ipaddr, port, timeout); } return -1; } int32_t at_api_close(int32_t fd) { if (gp_at_adaptor_api && gp_at_adaptor_api->close) { return gp_at_adaptor_api->close(fd); } return -1; } #endif ================================================ FILE: Huawei_LiteOS/components/net/at_frame/at_main.c ================================================ /*---------------------------------------------------------------------------- * Copyright (c) <2016-2018>, * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * 3. Neither the name of the copyright holder nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------- * Notice of Export Control Law * =============================================== * Huawei LiteOS may be subject to applicable export control laws and regulations, which might * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such * applicable export control laws and regulations. *---------------------------------------------------------------------------*/ #if defined(WITH_AT_FRAMEWORK) #include "los_memory.h" #include "at_frame/at_main.h" #include "at_hal.h" #ifdef WITH_SOTA #include "sota/sota.h" #endif #include "los_sys.ph" #include "los_tick.ph" static at_config at_user_conf; /* FUNCTION */ void at_set_config(at_config *config); at_config *at_get_config(void); int32_t at_init(at_config *config); //int32_t at_read(int32_t id, int8_t * buf, uint32_t len, int32_t timeout); int32_t at_write(int8_t *cmd, int8_t *suffix, int8_t *buf, int32_t len); int32_t at_get_unuse_linkid(void); void at_listener_list_add(at_listener *p); void at_listner_list_del(at_listener *p); int32_t at_cmd(int8_t *cmd, int32_t len, const char *suffix, char *resp_buf, int* resp_len); int32_t at_oob_register(char *featurestr, int cmdlen, oob_callback callback, oob_cmd_match cmd_match); void at_deinit(void); //init function for at struct at_oob_t at_oob; char rbuf[AT_DATA_LEN] = {0}; char wbuf[AT_DATA_LEN] = {0}; uint32_t at_get_time(void) { return ((uint32_t)(LOS_TickCountGet()* (OS_SYS_MS_PER_SECOND / LOSCFG_BASE_CORE_TICK_PER_SECOND)) )/ 1000; } int chartoint(const char* port) { int tmp=0; while(*port >= '0' && *port <= '9') { tmp = tmp*10+*port-'0'; port++; } return tmp; } //add p to tail; void at_listener_list_add(at_listener *p) { at_listener *head = at.head; at_listener *cur; //AT_LOG("www add listener %p, callback %p", p, p->handle_data); p->next = NULL; if (NULL == head) { at.head = p; return; } cur = head; while(cur->next) { cur = cur->next; } cur->next = p; } void at_listner_list_del(at_listener *p) { at_listener *head = at.head; at_listener *cur; //AT_LOG("www del listener %p callback %p", p, p->handle_data); if (p == head) { at.head = head->next; return; } cur = head; while(cur->next) { if (cur->next == p) { cur->next = p->next; break; } } } void at_listner_list_destroy(at_task *at_tsk) { at_listener *head; while(at_tsk->head != NULL) { head = at_tsk->head; at_tsk->head = head->next; if (head->handle_data != NULL) { at_free(head); } } } static void at_rm_node(at_listener *listener, at_listener *pre) { //AT_LOG("www del listener %p callback %p", listener, listener->handle_data); if (at.head == listener) { at.head = listener->next; } else { if (pre) { pre->next = listener->next; } } at_free(listener); LOS_MuxPost(at.trx_mux); } static void at_rm_timeout_nodes() { at_listener *pre = NULL; at_listener *next = NULL; for (at_listener *listener = at.head; listener != NULL; listener = next) { next = listener->next; if (listener->handle_data == NULL) { pre = listener; continue; } if (listener->expire_time <= at_get_time()) { AT_LOG("get recv data timeout"); at_rm_node(listener, pre); } else { pre = listener; } } } int32_t at_get_unuse_linkid(void) { int i = 0; if (AT_MUXMODE_MULTI == at.mux_mode) { for (i = 0; i < at_user_conf.linkid_num; i++) { if (AT_LINK_UNUSE == at.linkid[i].usable) { break; } } } if (i < at_user_conf.linkid_num) at.linkid[i].usable = AT_LINK_INUSE; return i; } void store_resp_buf(int8_t *resp_buf, const int8_t *src, uint32_t src_len, uint32_t* maxlen) { int copy_len; copy_len = MIN(*maxlen, src_len); memcpy((char *)resp_buf, (char *)src, copy_len); *maxlen = copy_len; } int32_t at_cmd_in_callback(const int8_t *cmd, int32_t len, int32_t (*handle_data)(const int8_t *data, uint32_t len), uint32_t timeout) { int32_t ret = AT_FAILED; if (handle_data != NULL) { if (LOS_MuxPend(at.trx_mux, 0) != AT_OK) { return AT_FAILED; } } LOS_MuxPend(at.cmd_mux, LOS_WAIT_FOREVER); //at_rm_timeout_nodes(); at_transmit((uint8_t *)cmd, len, 1); if (handle_data != NULL) { at_listener *listener = NULL; listener = at_malloc(sizeof(*listener)); if (listener == NULL) { AT_LOG("at_malloc fail"); goto EXIT; } memset(listener, 0 ,sizeof(*listener)); listener->handle_data = handle_data; listener->expire_time = at_get_time() + timeout; at_listener_list_add(listener); } ret = AT_OK; EXIT: LOS_MuxPost(at.cmd_mux); AT_LOG("len %ld,cmd %s", len, cmd); return ret; } int32_t at_cmd_multi_suffix(const int8_t *cmd, int len, at_cmd_info_s *cmd_info) { at_listener listener; int ret; int print_len; if ((cmd_info == NULL) || (cmd == NULL)) { return AT_FAILED; } memset(&listener, 0, sizeof(listener)); listener.cmd_info = *cmd_info; print_len = ((cmd_info->resp_buf && cmd_info->resp_len) ? (int)*(cmd_info->resp_len) : -1); AT_LOG("cmd len %d, %p,%d", print_len,cmd_info->resp_buf,(int)cmd_info->resp_len); LOS_MuxPend(at.trx_mux, LOS_WAIT_FOREVER); LOS_MuxPend(at.cmd_mux, LOS_WAIT_FOREVER); //at_rm_timeout_nodes(); at_listener_list_add(&listener); at_transmit((uint8_t *)cmd, len, 1); LOS_MuxPost(at.cmd_mux); ret = LOS_SemPend(at.resp_sem, at.timeout); LOS_MuxPend(at.cmd_mux, LOS_WAIT_FOREVER); at_listner_list_del(&listener); LOS_MuxPost(at.cmd_mux); LOS_MuxPost(at.trx_mux); write_at_task_msg(AT_SENT_DONE); if (ret != LOS_OK) { AT_LOG("LOS_SemPend for listener.resp_sem failed(ret = %x, cmd = %s)!", ret,cmd); return AT_FAILED; } *cmd_info = listener.cmd_info; return AT_OK; } int32_t at_cmd(int8_t *cmd, int32_t len, const char *suffix, char *resp_buf, int* resp_len) { const char *suffix_array[1] = {suffix}; at_cmd_info_s cmd_info; memset(&cmd_info, 0, sizeof(cmd_info)); cmd_info.suffix = suffix_array; cmd_info.suffix_num = array_size(suffix_array); cmd_info.resp_buf = resp_buf; cmd_info.resp_len = (uint32_t *)resp_len; return at_cmd_multi_suffix(cmd, len, &cmd_info); } int32_t at_write(int8_t *cmd, int8_t *suffix, int8_t *buf, int32_t len) { const char *suffix_array[1]; at_listener listener; int ret = AT_FAILED; memset(&listener, 0, sizeof(listener)); listener.cmd_info.suffix_num = 1; suffix_array[0] = ">"; listener.cmd_info.suffix = suffix_array; LOS_MuxPend(at.trx_mux, LOS_WAIT_FOREVER); LOS_MuxPend(at.cmd_mux, LOS_WAIT_FOREVER); //at_rm_timeout_nodes(); at_listener_list_add(&listener); at_transmit((uint8_t *)cmd, strlen((char *)cmd), 1); LOS_MuxPost(at.cmd_mux); (void)LOS_SemPend(at.resp_sem, 200); LOS_MuxPend(at.cmd_mux, LOS_WAIT_FOREVER); suffix_array[0] = (char *)suffix; at_listner_list_del(&listener); at_listener_list_add(&listener); at_transmit((uint8_t *)buf, len, 0); LOS_MuxPost(at.cmd_mux); ret = LOS_SemPend(at.resp_sem, at.timeout); LOS_MuxPend(at.cmd_mux, LOS_WAIT_FOREVER); at_listner_list_del(&listener); LOS_MuxPost(at.cmd_mux); LOS_MuxPost(at.trx_mux); write_at_task_msg(AT_SENT_DONE); if (ret != LOS_OK) { AT_LOG("LOS_SemPend for listener.resp_sem failed(ret = %x)!", ret); return AT_FAILED; } return len; } int cloud_cmd_matching(int8_t *buf, int32_t len) { int ret = 0; char *cmp = NULL; int i; // int rlen; // memset(wbuf, 0, AT_DATA_LEN); for(i = 0; i < at_oob.oob_num; i++) { //cmp = strstr((char *)buf, at_oob.oob[i].featurestr); ret = at_oob.oob[i].cmd_match((const char *)buf, at_oob.oob[i].featurestr,at_oob.oob[i].len); if(ret == 0) { cmp += at_oob.oob[i].len; // sscanf(cmp,"%d,%s",&rlen,wbuf); if(at_oob.oob[i].callback != NULL) { (void)at_oob.oob[i].callback(at_oob.oob[i].arg, (int8_t *)buf, (int32_t)len); } return len; } } return 0; } static int at_handle_callback_cmd_resp(at_listener *listener, int8_t *resp_buf, uint32_t resp_len) { if (listener->handle_data == NULL) { return AT_FAILED; } if (listener->handle_data(resp_buf, resp_len) == AT_OK) { at_rm_node(listener, NULL); return AT_OK; } return AT_FAILED; } static void at_handle_resp(int8_t *resp_buf, uint32_t resp_len) { at_listener *listener = NULL; listener = at.head; if (NULL == listener) return; if (at_handle_callback_cmd_resp(listener, resp_buf, resp_len) == AT_OK) { return; } if(listener->cmd_info.suffix == NULL) { //store_resp_buf((int8_t *)listener->resp, (int8_t*)p1, p2 - p1); (void)LOS_SemPost(at.resp_sem); listener = NULL; return; } for (uint32_t i = 0; i < listener->cmd_info.suffix_num; i++) { char *suffix; if (listener->cmd_info.suffix[i] == NULL) { continue; } suffix = strstr((char *)resp_buf, (const char *)listener->cmd_info.suffix[i]); if (suffix != NULL) { if ((NULL != listener->cmd_info.resp_buf) && (NULL != listener->cmd_info.resp_len) && (resp_len > 0)) { store_resp_buf((int8_t *)listener->cmd_info.resp_buf, resp_buf, resp_len, listener->cmd_info.resp_len);//suffix + strlen((char *)listener->suffix) - p1 } listener->cmd_info.match_idx = i; (void)LOS_SemPost(at.resp_sem); break; } } } static uint32_t at_get_queue_wait_time() { uint32_t ret; if (at.step_callback == NULL) { return LOS_WAIT_FOREVER; } LOS_MuxPend(at.cmd_mux, LOS_WAIT_FOREVER); if ((at.head == NULL) || (at.head->handle_data == NULL)) { ret = LOS_WAIT_FOREVER; } else { const uint32_t min_wait_time = 100; uint32_t current = at_get_time(); ret = ((current >= at.head->expire_time) ? min_wait_time :((at.head->expire_time - current) * 1000)); } LOS_MuxPost(at.cmd_mux); return ret; } void at_recv_task() { uint32_t recv_len = 0; uint8_t *tmp = at.userdata; //[MAX_USART_BUF_LEN] = {0}; int ret = 0; recv_buff recv_buf; UINT32 rlen = sizeof(recv_buff); while(1) { uint32_t wait_time = at_get_queue_wait_time(); //AT_LOG("www wait time %ld", wait_time); ret = LOS_QueueReadCopy(at.rid, &recv_buf, &rlen, wait_time); if(ret != LOS_OK) { continue; } if (recv_buf.msg_type == AT_TASK_QUIT) { AT_LOG("at recv task quit"); break; } LOS_MuxPend(at.cmd_mux, LOS_WAIT_FOREVER); at_rm_timeout_nodes(); LOS_MuxPost(at.cmd_mux); if (at.step_callback) { at.step_callback(); } if (recv_buf.msg_type != AT_USART_RX) { AT_LOG("at recv msg sent done"); continue; } memset(tmp, 0, at_user_conf.user_buf_len); recv_len = read_resp(tmp, &recv_buf); if (recv_len <= 0) { AT_LOG("err, recv_len = %ld", recv_len); continue; } AT_LOG_DEBUG("recv len = %lu buf = %s ", recv_len, tmp); ret = cloud_cmd_matching((int8_t *)tmp, recv_len); if(ret > 0) { continue; } LOS_MuxPend(at.cmd_mux, LOS_WAIT_FOREVER); at_rm_timeout_nodes(); at_handle_resp((int8_t *)tmp, recv_len); LOS_MuxPost(at.cmd_mux); } } uint32_t create_at_recv_task() { uint32_t uwRet = LOS_OK; TSK_INIT_PARAM_S task_init_param; task_init_param.usTaskPrio = 0; task_init_param.pcName = "at_recv_task"; task_init_param.pfnTaskEntry = (TSK_ENTRY_FUNC)at_recv_task; task_init_param.uwStackSize = 0x1000; uwRet = LOS_TaskCreate((UINT32 *)&at.tsk_hdl, &task_init_param); if(LOS_OK != uwRet) { return uwRet; } return uwRet; } void at_init_oob(void) { at_oob.oob_num = 0; memset(at_oob.oob, 0, OOB_MAX_NUM * sizeof(struct oob_s)); } int32_t at_struct_init(at_task *at) { int ret = -1; if (NULL == at) { AT_LOG("invaild param!"); return ret; } ret = LOS_QueueCreate("recvQueue", 32, (UINT32 *)&at->rid, 0, sizeof(recv_buff)); if (ret != LOS_OK) { AT_LOG("init recvQueue failed!"); return AT_FAILED; } at->rid_flag = true; ret = LOS_SemCreate(0, (UINT32 *)&at->recv_sem); if (ret != LOS_OK) { AT_LOG("init at_recv_sem failed!"); goto at_recv_sem_failed; } ret = LOS_MuxCreate((UINT32 *)&at->cmd_mux); if (ret != LOS_OK) { AT_LOG("init cmd_mux failed!"); goto at_cmd_mux_failed; } ret = LOS_MuxCreate((UINT32 *)&at->trx_mux); if (ret != LOS_OK) { AT_LOG("init cmd_mux failed!"); goto at_cmd_mux_failed; } at->trx_mux_flag = true; ret = LOS_SemCreate(0, (UINT32 *)&at->resp_sem); if (ret != LOS_OK) { AT_LOG("init resp_sem failed!"); goto at_resp_sem_failed; } #ifndef USE_USARTRX_DMA at->recv_buf = at_malloc(at_user_conf.user_buf_len); if (NULL == at->recv_buf) { AT_LOG("malloc recv_buf failed!"); goto malloc_recv_buf; } #else at->recv_buf = at_malloc(at_user_conf.recv_buf_len); if (NULL == at->recv_buf) { AT_LOG("malloc recv_buf failed!"); goto malloc_recv_buf; } #endif at->cmdresp = at_malloc(at_user_conf.user_buf_len); if (NULL == at->cmdresp) { AT_LOG("malloc cmdresp failed!"); goto malloc_resp_buf; } at->userdata = at_malloc(at_user_conf.user_buf_len); if (NULL == at->userdata) { AT_LOG("malloc userdata failed!"); goto malloc_userdata_buf; } at->saveddata = at_malloc(at_user_conf.user_buf_len); if (NULL == at->saveddata) { AT_LOG("malloc saveddata failed!"); goto malloc_saveddata_buf; } at->linkid = (at_link *)at_malloc(at_user_conf.linkid_num * sizeof(at_link)); if (NULL == at->linkid) { AT_LOG("malloc for at linkid array failed!"); goto malloc_linkid_failed; } memset(at->linkid, 0, at_user_conf.linkid_num * sizeof(at_link)); at->head = NULL; at->mux_mode = at_user_conf.mux_mode; at->timeout = at_user_conf.timeout; return AT_OK; // atiny_free(at->linkid); malloc_linkid_failed: at_free(at->saveddata); malloc_saveddata_buf: at_free(at->userdata); malloc_userdata_buf: at_free(at->cmdresp); malloc_resp_buf: at_free(at->recv_buf); malloc_recv_buf: (void)LOS_SemDelete(at->resp_sem); at_resp_sem_failed: (void)LOS_MuxDelete(at->cmd_mux); at_cmd_mux_failed: (void)LOS_SemDelete(at->recv_sem); at_recv_sem_failed: if (at->trx_mux_flag) { (void)LOS_MuxDelete(at->trx_mux); at->trx_mux_flag = false; } if (at->rid_flag) { (VOID)LOS_QueueDelete(at->rid); at->rid_flag = false; } return AT_FAILED; } int32_t at_struct_deinit(at_task *at) { int32_t ret = AT_OK; if(at == NULL) { AT_LOG("invaild param!"); return AT_FAILED; } LOS_MuxPend(at->cmd_mux, LOS_WAIT_FOREVER); at_listner_list_destroy(at); LOS_MuxPost(at->cmd_mux); if (LOS_SemDelete(at->recv_sem) != LOS_OK) { AT_LOG("delete at.recv_sem failed!"); ret = AT_FAILED; } if (LOS_MuxDelete(at->cmd_mux) != LOS_OK) { AT_LOG("delete at.cmd_mux failed!"); ret = AT_FAILED; } if (LOS_SemDelete(at->resp_sem) != LOS_OK) { AT_LOG("delete at.resp_sem failed!"); ret = AT_FAILED; } if (at->trx_mux_flag) { (void)LOS_MuxDelete(at->trx_mux); at->trx_mux_flag = false; } if (at->rid_flag) { (VOID)LOS_QueueDelete(at->rid); at->rid_flag = false; } if (NULL != at->recv_buf) { at_free(at->recv_buf); at->recv_buf = NULL; } if (NULL != at->cmdresp) { at_free(at->cmdresp); at->cmdresp = NULL; } if (NULL != at->userdata) { at_free(at->userdata); at->userdata = NULL; } if (NULL != at->saveddata) { at_free(at->saveddata); at->saveddata = NULL; } if (NULL != at->linkid) { at_free(at->linkid); at->linkid = NULL; } at->tsk_hdl = 0xFFFF; at->head = NULL; at->mux_mode = AT_MUXMODE_SINGLE; at->timeout = 0; return ret; } void at_set_config(at_config *config) { if(NULL != config){ memcpy(&at_user_conf,config,sizeof(at_config)); } } at_config *at_get_config(void) { return &at_user_conf; } int32_t at_init(at_config *config) { if(NULL == config) { AT_LOG("Config is NULL, failed!!\n"); return AT_FAILED; } memcpy(&at_user_conf,config,sizeof(at_config)); AT_LOG_DEBUG("Config %s(buffer total is %lu)......\n", at_user_conf.name, at_user_conf.user_buf_len); //LOS_TaskDelay(200); if (AT_OK != at_struct_init(&at)) { AT_LOG("prepare AT struct failed!"); return AT_FAILED; } at_init_oob(); if(AT_OK != at_usart_init()) { AT_LOG("at_usart_init failed!"); (void)at_struct_deinit(&at); return AT_FAILED; } if(LOS_OK != create_at_recv_task()) { AT_LOG("create_at_recv_task failed!"); at_usart_deinit(); (void)at_struct_deinit(&at); return AT_FAILED; } AT_LOG("Config complete!!\n"); return AT_OK; } void at_deinit(void) { int cnt = 0; const int max_try_num = 10; while(LOS_TaskNameGet(at.tsk_hdl) != NULL && cnt < max_try_num) { write_at_task_msg(AT_TASK_QUIT); LOS_TaskDelay(1000); cnt++; } if (LOS_TaskNameGet(at.tsk_hdl) != NULL) { if(LOS_OK != LOS_TaskDelete(at.tsk_hdl)) { AT_LOG("at_recv_task delete failed!"); } } at_usart_deinit(); if(AT_OK != at_struct_deinit(&at)) { AT_LOG("at_struct_deinit failed!"); } at_init_oob(); } int32_t at_oob_register(char *featurestr, int cmdlen, oob_callback callback, oob_cmd_match cmd_match) { oob_t *oob; if(featurestr == NULL || cmd_match == NULL || at_oob.oob_num == OOB_MAX_NUM || cmdlen >= OOB_CMD_LEN - 1) return -1; oob = &(at_oob.oob[at_oob.oob_num++]); memcpy(oob->featurestr, featurestr, cmdlen); oob->len = strlen(featurestr); oob->callback = callback; oob->cmd_match = cmd_match; return 0; } void *at_malloc(size_t size) { void *pMem = LOS_MemAlloc(m_aucSysMem0, size); if(NULL != pMem) { memset(pMem, 0, size); } return pMem; } void at_free(void *ptr) { (void)LOS_MemFree(m_aucSysMem0, ptr); } void at_reg_step_callback(at_task *at_tsk, void (*step_callback)(void)) { at_tsk->step_callback = step_callback; } at_task at = { .tsk_hdl = 0xFFFF, .recv_buf = NULL, .cmdresp = NULL, .userdata = NULL, .linkid = NULL, .head = NULL, .init = at_init, .deinit = at_deinit, .cmd = at_cmd, .write = at_write, .oob_register = at_oob_register, .get_id = at_get_unuse_linkid, .cmd_multi_suffix = at_cmd_multi_suffix }; #endif ================================================ FILE: Huawei_LiteOS/components/net/lwip/lwip-2.0.3/CHANGELOG ================================================ HISTORY (git master) * [Enter new changes just after this line - do not remove this line] (STABLE-2.0.3) ++ Bugfixes: 2017-09-11: Simon Goldschmidt * tcp_in.c: fix bug #51937 (leaking tcp_pcbs on passive close with unacked data) 2017-08-02: Abroz Bizjak/Simon Goldschmidt * multiple fixes in IPv4 reassembly (leading to corrupted datagrams received) 2017-03-30: Simon Goldschmidt * dhcp.c: return ERR_VAL instead of asserting on offset-out-of-pbuf 2017-03-23: Dirk Ziegelmeier * dhcp.h: fix bug #50618 (dhcp_remove_struct() macro does not work) (STABLE-2.0.2) ++ New features: 2017-02-10: Dirk Ziegelmeier * Implement task #14367: Hooks need a better place to be defined: We now have a #define for a header file name that is #included in every .c file that provides hooks. 2017-02-10: Simon Goldschmidt * tcp_close does not fail on memory error (instead, FIN is sent from tcp_tmr) ++ Bugfixes: 2017-03-08 * tcp: do not keep sending SYNs when getting ACKs 2017-03-08: Joel Cunningham * tcp: Initialize ssthresh to TCP_SND_BUF (bug #50476) 2017-03-01: Simon Goldschmidt * httpd: LWIP_HTTPD_POST_MANUAL_WND: fixed double-free when httpd_post_data_recved is called nested from httpd_post_receive_data() (bug #50424) 2017-02-28: David van Moolenbroek/Simon Goldschmidt * tcp: fixed bug #50418: LWIP_EVENT_API: fix invalid calbacks for SYN_RCVD pcb 2017-02-17: Simon Goldschmidt * dns: Improved DNS_LOCAL_HOSTLIST interface (bug #50325) 2017-02-16: Simon Goldschmidt * LWIP_NETCONN_FULLDUPLEX: fixed shutdown during write (bug #50274) 2017-02-13: Simon Goldschmidt/Dirk Ziegelmeier * For tiny targtes, LWIP_RAND is optional (fix compile time checks) 2017-02-10: Simon Goldschmidt * tcp: Fixed bug #47485 (tcp_close() should not fail on memory error) by retrying to send FIN from tcp_fasttmr 2017-02-09: Simon Goldschmidt * sockets: Fixed bug #44032 (LWIP_NETCONN_FULLDUPLEX: select might work on invalid/reused socket) by not allowing to reallocate a socket that has "select_waiting != 0" 2017-02-09: Simon Goldschmidt * httpd: Fixed bug #50059 (httpd LWIP_HTTPD_SUPPORT_11_KEEPALIVE vs. LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED) 2017-02-08: Dirk Ziegelmeier * Rename "IPv6 mapped IPv4 addresses" to their correct name from RFC4191: "IPv4-mapped IPv6 address" 2017-02-08: Luc Revardel * mld6.c: Fix bug #50220 (mld6_leavegroup does not send ICMP6_TYPE_MLD, even if last reporter) 2017-02-08: David van Moolenbroek * ip6.c: Patch #9250: fix source substitution in ip6_output_if() 2017-02-08: Simon Goldschmidt * tcp_out.c: Fixed bug #50090 (last_unsent->oversize_left can become wrong value in tcp_write error path) 2017-02-02: Dirk Ziegelmeier * Fix bug #50206: UDP Netconn bind to IP6_ADDR_ANY fails 2017-01-18: Dirk Ziegelmeier * Fix zero-copy RX, see bug bug #50064. PBUF_REFs were not supported as ARP requests. 2017-01-15: Axel Lin, Dirk Ziegelmeier * minor bug fixes in mqtt 2017-01-11: Knut Andre Tidemann * sockets/netconn: fix broken default ICMPv6 handling of checksums (STABLE-2.0.1) ++ New features: 2016-12-31: Simon Goldschmidt * tcp.h/.c: added function tcp_listen_with_backlog_and_err() to get the error reason when listening fails (bug #49861) 2016-12-20: Erik Andersen * Add MQTT client 2016-12-14: Jan Breuer: * opt.h, ndc.h/.c: add support for RDNSS option (as per RFC 6106) 2016-12-14: David van Moolenbroek * opt.h, nd6.c: Added LWIP_HOOK_ND6_GET_GW() 2016-12-09: Dirk Ziegelmeier * ip6_frag.c: Implemented support for LWIP_NETIF_TX_SINGLE_PBUF 2016-12-09: Simon Goldschmidt * dns.c: added one-shot multicast DNS queries 2016-11-24: Ambroz Bizjak, David van Moolenbroek * tcp_out.c: Optimize passing contiguous nocopy buffers to tcp_write (bug #46290) 2016-11-16: Dirk Ziegelmeier * sockets.c: added support for IPv6 mapped IPv4 addresses ++ Bugfixes: 2016-12-16: Thomas Mueller * api_lib.c: fixed race condition in return value of netconn_gethostbyname() (and thus also lwip_gethostbyname/_r() and lwip_getaddrinfo()) 2016-12-15: David van Moolenbroek * opt.h, tcp: added LWIP_HOOK_TCP_ISN() to implement less predictable initial sequence numbers (see contrib/addons/tcp_isn for an example implementation) 2016-12-05: Dirk Ziegelmeier * fixed compiling with IPv4 disabled (IPv6 only case) 2016-11-28: Simon Goldschmidt * api_lib.c: fixed bug #49725 (send-timeout: netconn_write() can return ERR_OK without all bytes being written) 2016-11-28: Ambroz Bizjak * tcpi_in.c: fixed bug #49717 (window size in received SYN and SYN-ACK assumed scaled) 2016-11-25: Simon Goldschmidt * dhcp.c: fixed bug #49676 (Possible endless loop when parsing dhcp options) 2016-11-23: Dirk Ziegelmeier * udp.c: fixed bug #49662: multicast traffic is now only received on a UDP PCB (and therefore on a UDP socket/netconn) when the PCB is bound to IP_ADDR_ANY 2016-11-16: Dirk Ziegelmeier * *: Fixed dual-stack behaviour, IPv6 mapped IPv4 support in socket API 2016-11-14: Joel Cunningham * tcp_out.c: fixed bug #49533 (start persist timer when unsent seg can't fit in window) 2016-11-16: Roberto Barbieri Carrera * autoip.c: fixed bug #49610 (sometimes AutoIP fails to reuse the same address) 2016-11-11: Dirk Ziegelmeier * sockets.c: fixed bug #49578 (dropping multicast membership does not work with LWIP_SOCKET_OFFSET) (STABLE-2.0.0) ++ New features: 2016-07-27: Simon Goldschmidt * opt.h, timeouts.h/.c: added LWIP_TIMERS_CUSTOM to override the default implementation of timeouts 2016-07-xx: Dirk Ziegelmeier * Large overhaul of doxygen documentation 2016-04-05: Simon Goldschmidt * timers.h/.c: prepare for overriding current timeout implementation: all stack-internal caclic timers are avaliable in the lwip_cyclic_timers array 2016-03-23: Simon Goldschmidt * tcp: call accept-callback with ERR_MEM when allocating a pcb fails on passive open to inform the application about this error ATTENTION: applications have to handle NULL pcb in accept callback! 2016-02-22: Ivan Delamer * Initial 6LoWPAN support 2016-02-XX to 2016-03-XX: Dirk Ziegelmeier * Cleanup TCPIP thread sync methods in a way that it is possibe to use them in arbitrary code that needs things to be done in TCPIP thread. Used to decouple netconn, netif, ppp and 6LoWPAN from LWIP core. 2016-02-XX: Dirk Ziegelmeier * Implement dual-stack support in RAW, UDP and TCP. Add new IP address type IPADDR_ANY_TYPE for this. Netconn/Socket API: Dual-stack is automatically supported when an IPv6 netconn/socket is created. 2015-12-26: Martin Hentschel and Dirk Ziegelmeier * Rewrite SNMP agent. SNMPv2c + MIB compiler. 2015-11-12: Dirk Ziegelmeier * Decouple SNMP stack from lwIP core and move stack to apps/ directory. Breaking change: Users have to call snmp_init() now! 2015-11-12: Dirk Ziegelmeier * Implement possibility to declare private memory pools. This is useful to decouple some apps from the core (SNMP stack) or make contrib app usage simpler (httpserver_raw) 2015-10-09: Simon Goldschmidt * started to move "private" header files containing implementation details to "lwip/priv/" include directory to seperate the API from the implementation. 2015-10-07: Simon Goldschmidt * added sntp client as first "supported" application layer protocol implementation added 'apps' folder 2015-09-30: Dirk Ziegelmeier * snmp_structs.h, mib_structs.c, mib2.c: snmp: fixed ugly inheritance implementation by aggregating the "base class" (struct mib_node) in all derived node classes to get more type-safe code 2015-09-23: Simon Goldschmidt * netif.h/.c, nd6.c: task #13729: Convert netif addresses (IPv4 & IPv6) to ip_addr_t (so they can be used without conversion/temporary storage) 2015-09-08: Dirk Ziegelmeier * snmp: Separate mib2 counter/table callbacks from snmp agent. This both cleans up the code and should allow integration of a 3rd party agent/mib2. Simple counters are kept in MIB2_STATS, tree/table change function prototypes moved to snmp_mib2.h. 2015-09-03: Simon Goldschmidt * opt.h, dns.h/.c: DNS/IPv6: added support for AAAA records 2015-09-01: Simon Goldschmidt * task #12178: hardware checksum capabilities can be configured per netif (use NETIF_SET_CHECKSUM_CTRL() in your netif's init function) 2015-08-30: Simon Goldschmidt * PBUF_REF with "custom" pbufs is now supported for RX pbufs (see pcapif in contrib for an example, LWIP_SUPPORT_CUSTOM_PBUF is required) 2015-08-30: Simon Goldschmidt * support IPv4 source based routing: define LWIP_HOOK_IP4_ROUTE_SRC to point to a routing function 2015-08-05: Simon Goldschmidt * many files: allow multicast socket options IP_MULTICAST_TTL, IP_MULTICAST_IF and IP_MULTICAST_LOOP to be used without IGMP 2015-04-24: Simon Goldschmidt * dhcp.h/c, autoip.h/.c: added functions dhcp/autoip_supplied_address() to check for the source of address assignment (replacement for NETIF_FLAG_DHCP) 2015-04-10: Simon Goldschmidt * many files: task #13480: added LWIP_IPV4 define - IPv4 can be disabled, leaving an IPv6-only stack 2015-04-09: Simon Goldschmidt * nearly all files: task #12722 (improve IPv4/v6 address handling): renamed ip_addr_t to ip4_addr_t, renamed ipX_addr_t to ip_addr_t and added IP version; ip_addr_t is used for all generic IP addresses for the API, ip(4/6)_addr_t are only used internally or when initializing netifs or when calling version-related functions 2015-03-24: Simon Goldschmidt * opt.h, ip4_addr.h, ip4.c, ip6.c: loopif is not required for loopback traffic any more but passed through any netif (ENABLE_LOOPBACK has to be enabled) 2015-03-23: Simon Goldschmidt * opt.h, etharp.c: with ETHARP_TABLE_MATCH_NETIF== 1, duplicate (Auto)-IP addresses on multiple netifs should now be working correctly (if correctly addressed by routing, that is) 2015-03-23: Simon Goldschmidt * etharp.c: Stable etharp entries that are about to expire are now refreshed using unicast to prevent unnecessary broadcast. Only if no answer is received after 15 seconds, broadcast is used. 2015-03-06: Philip Gladstone * netif.h/.c: patch #8359 (Provide utility function to add an IPv6 address to an interface) 2015-03-05: Simon Goldschmidt * netif.c, ip4.c, dhcp.c, autoip.c: fixed bug #37068 (netif up/down handling is unclear): correclty separated administrative status of a netif (up/down) from 'valid address' status ATTENTION: netif_set_up() now always has to be called, even when dhcp/autoip is used! 2015-02-26: patch by TabascoEye * netif.c, udp.h/.c: fixed bug #40753 (re-bind UDP pcbs on change of IP address) 2015-02-22: chrysn, Simon Goldschmidt * *.*: Changed nearly all functions taking 'ip(X)_addr_t' pointer to take const pointers (changed user callbacks: raw_recv_fn, udp_recv_fn; changed port callbacks: netif_output_fn, netif_igmp_mac_filter_fn) 2015-02-19: Ivan Delamer * netif.h, dhcp.c: Removed unused netif flag for DHCP. The preferred way to evaluate if DHCP is active is through netif->dhcp field. 2015-02-19: Ivan Delamer * netif.h, slipif.c, ppp.c: Removed unused netif flag for point to point connections 2015-02-18: Simon Goldschmidt * api_lib.c: fixed bug #37958 "netconn API doesn't handle correctly connections half-closed by peer" 2015-02-18: Simon Goldschmidt * tcp.c: tcp_alloc() prefers killing CLOSING/LAST_ACK over active connections (see bug #39565) 2015-02-16: Claudius Zingerli, Sergio Caprile * opt.h, dhcp.h/.c: patch #8361 "Add support for NTP option in DHCP" 2015-02-14: Simon Goldschmidt * opt.h, snmp*: added support for write-access community and dedicated community for sending traps 2015-02-13: Simon Goldschmidt * opt.h, memp.c: added hook LWIP_HOOK_MEMP_AVAILABLE() to get informed when a memp pool was empty and an item is now available 2015-02-13: Simon Goldschmidt * opt.h, pbuf.h/.c, etharp.c: Added the option PBUF_LINK_ENCAPSULATION_HLEN to allocate additional header space for TX on netifs requiring additional headers 2015-02-12: chrysn * timers.h/.c: introduce sys_timeouts_sleeptime (returns the time left before the next timeout is due, for NO_SYS==1) 2015-02-11: Nick van Ijzendoorn * opt.h, sockets.h/c: patch #7702 "Include ability to increase the socket number with defined offset" 2015-02-11: Frederick Baksik * opt.h, def.h, others: patch #8423 "arch/perf.h" should be made an optional item 2015-02-11: Simon Goldschmidt * api_msg.c, opt.h: started to implement fullduplex sockets/netconns (note that this is highly unstable yet!) 2015-01-17: Simon Goldschmidt * api: allow enabling socket API without (public) netconn API - netconn API is still used by sockets, but keeping it private (static) should allow better compiler optimizations 2015-01-16: Simon Goldschmidt * tcp_in.c: fixed bug #20506 "Initial congestion window is very small" again by implementing the calculation formula from RFC3390 2014-12-10: Simon Goldschmidt * api: added option LWIP_NETCONN_SEM_PER_THREAD to use a semaphore per thread instead of using one per netconn and per select call 2014-12-08: Simon Goldschmidt * ip6.h: fixed bug #43778: IPv6 header version not set on 16-bit platform (macro IP6H_VTCFL_SET()) 2014-12-08: Simon Goldschmidt * icmp.c, ip4.c, pbuf.c, udp.c, pbuf.h: task #11472 Support PBUF_REF for RX (IPv6 and IPv4/v6 reassembly might not work yet) 2014-11-06: Simon Goldschmidt * sockets.c/.h, init.c: lwip_socket_init() is not needed any more -> compatibility define 2014-09-16: Simon Goldschmidt * dns.c, opt.h: reduced ram usage by parsing DNS responses in place 2014-09-16: Simon Goldschmidt * pbuf.h/.c: added pbuf_take_at() and pbuf_put_at() 2014-09-15: Simon Goldschmidt * dns.c: added source port randomization to make the DNS client more robust (see bug #43144) 2013-09-02: Simon Goldschmidt * arch.h and many other files: added optional macros PACK_STRUCT_FLD_8() and PACK_STRUCT_FLD_S() to prevent gcc 4 from warning about struct members that do not need packing 2013-08-19: Simon Goldschmidt * netif.h: bug #42998: made NETIF_MAX_HWADDR_LEN overridable for some special networks 2013-03-17: Simon Goldschmidt (patch by Ghobad Emadi) * opt.h, etharp.c: Added LWIP_HOOK_ETHARP_GET_GW to implement IPv4 routing with multiple gateways 2013-04-20: Fatih Asici * opt.h, etharp.h/.c: patch #7993: Added support for transmitting packets with VLAN headers via hook function LWIP_HOOK_VLAN_SET and to check them via hook function LWIP_HOOK_VLAN_CHECK 2014-02-20: Simon Goldschmidt (based on patch by Artem Pisarenko) * patch #7885: modification of api modules to support FreeRTOS-MPU (don't pass stack-pointers to other threads) 2014-02-05: Simon Goldschmidt (patch by "xtian" and "alex_ab") * patch #6537/#7858: TCP window scaling support 2014-01-17: Jiri Engelthaler * icmp, icmp6, opt.h: patch #8027: Completed HW checksuming for IPv4 and IPv6 ICMP's 2012-08-22: Sylvain Rochet * New PPP stack for lwIP, developed in ppp-new branch. Based from pppd 2.4.5, released 2009-11-17, with huge changes to match code size and memory requirements for embedded devices, including: - Gluing together the previous low-level PPP code in lwIP to pppd 2.4.5, which is more or less what pppd sys-* files are, so that we get something working using the unix port. - Merged some patchs from lwIP Git repository which add interesting features or fix bugs. - Merged some patchs from Debian pppd package which add interesting features or fix bugs. - Ported PPP timeout handling to the lwIP timers system - Disabled all the PPP code using filesystem access, replaced in necessary cases to configuration variables. - Disabled all the PPP code forking processes. - Removed IPX support, lwIP does not support IPX. - Ported and improved random module from the previous PPP port. - Removed samba TDB (file-driven database) usage, because it needs a filesystem. - MS-CHAP required a DES implementation, we added the latest PolarSSL DES implementation which is under a BSD-ish license. - Also switched to PolarSSL MD4,MD5,SHA1 implementations, which are meant to be used in embedded devices with reduced memory footprint. - Removed PPP configuration file parsing support. - Added macro definition EAP_SUPPORT to make EAP support optional. - Added macro definition CHAP_SUPPORT to make CHAP support optional. - Added macro definition MSCHAP_SUPPORT to make MSCHAP support optional. - Added macro definition PAP_SUPPORT to make PAP support optional. - Cleared all Linux syscall calls. - Disabled demand support using a macro, so that it can be ported later. - Disabled ECP support using a macro, so that it can be ported later. - Disabled CCP support using a macro, so that it can be ported later. - Disabled CBCP support using a macro, so that it can be ported later. - Disabled LQR support using a macro, so that it can be ported later. - Print packet debug feature optional, through PRINTPKT_SUPPORT - Removed POSIX signal usage. - Fully ported PPPoS code from the previous port. - Fully ported PPPoE code from the previous port. - Fully ported VJ compression protocol code from the previous port. - Removed all malloc()/free() use from PPP, replaced by stack usage or PBUF. - Disabled PPP server support using a macro, so that it can be ported later. - Switched all PPP debug to lwIP debug system. - Created PPP Control Block (PPP PCB), removed PPP unit integer everywhere, removed all global variables everywhere, did everything necessary for the PPP stack to support more than one PPP session (pppd only support one session per process). - Removed the statically allocated output buffer, now using PBUF. - Improved structure size of all PPP modules, deep analyze of code to reduce variables size to the bare minimum. Switched all boolean type (char type in most architecture) to compiler generated bitfields. - Added PPP IPv6 support, glued lwIP IPv6 support to PPP. - Now using a persistent netif interface which can then be used in lwIP functions requiring a netif. - Now initializing PPP in lwip_init() function. - Reworked completely the PPP state machine, so that we don't end up in anymore in inconsistent state, especially with PPPoE. - Improved the way we handle PPP reconnection after disconnect, cleaning everything required so that we start the PPP connection again from a clean state. - Added PPP holdoff support, allow the lwIP user to wait a little bit before reconnecting, prevents connection flood, especially when using PPPoL2TP. - Added PPPoL2TP LAC support (a.k.a. UDP tunnels), adding a VPN client feature to lwIP, L2TP being a widely used tunnel protocol. - Switched all used PPP types to lwIP types (u8t, u16t, u32t, ...) - Added PPP API "sequential" thread-safe API, based from NETIFAPI. 2011-07-21: Simon Goldschmidt * sockets.c, opt.h: (bug #30185): added LWIP_FIONREAD_LINUXMODE that makes ioctl/FIONREAD return the size of the next pending datagram. 2011-05-25: Simon Goldschmidt * again nearly the whole stack, renamed ip.c to ip4.c, ip_addr.c to ip4_addr.c, combined ipv4/ipv6 inet_chksum.c, added ip.h, ip_addr.h: Combined IPv4 and IPv6 code where possible, added defines to access IPv4/IPv6 in non-IP code so that the code is more readable. 2011-05-17: Patch by Ivan Delamer (only checked in by Simon Goldschmidt) * nearly the whole stack: Finally, we got decent IPv6 support, big thanks to Ivan! (this is work in progress: we're just post release anyway :-) ++ Bugfixes: 2016-08-23: Simon Goldschmidt * etharp: removed ETHARP_TRUST_IP_MAC since it is insecure and we don't need it any more after implementing unicast ARP renewal towards arp entry timeout 2016-07-20: Simon Goldschmidt * memp.h/.c: fixed bug #48442 (memp stats don't work for MEMP_MEM_MALLOC) 2016-07-21: Simon Goldschmidt (patch by Ambroz Bizjak) * tcp_in.c, tcp_out.c: fixed bug #48543 (TCP sent callback may prematurely report sent data when only part of a segment is acked) and don't include SYN/FIN in snd_buf counter 2016-07-19: Simon Goldschmidt * etharp.c: fixed bug #48477 (ARP input packet might update static entry) 2016-07-11: Simon Goldschmidt * tcp_in.c: fixed bug #48476 (TCP sent callback called wrongly due to picking up old pcb->acked 2016-06-30: Simon Goldschmidt (original patch by Fabian Koch) * tcp_in.c: fixed bug #48170 (Vulnerable to TCP RST spoofing) 2016-05-20: Dirk Ziegelmeier * sntp.h/.c: Fix return value of sntp_getserver() call to return a pointer 2016-04-05: Simon Goldschmidt (patch by Philip Gladstone) * udp.c: patch #8358: allow more combinations of listening PCB for IPv6 2016-04-05: Simon Goldschmidt * netconn/socket API: fixed bug# 43739 (Accept not reporting errors about aborted connections): netconn_accept() returns ERR_ABRT (sockets: ECONNABORTED) for aborted connections, ERR_CLSD (sockets: EINVAL) if the listening netconn is closed, which better seems to follow the standard. 2016-03-23: Florent Matignon * dhcp.c: fixed bug #38203: DHCP options are not recorded in all DHCP ack messages 2016-03-22: Simon Goldschmidt * tcp: changed accept handling to be done internally: the application does not have to call tcp_accepted() any more. Instead, when delaying accept (e.g. sockets do), call tcp_backlog_delayed()/tcp_backlog_accepted() (fixes bug #46696) 2016-03-22: Simon Goldschmidt * dns.c: ignore dns response parsing errors, only abort resolving for correct responses or error responses from correct server (bug #47459) 2016-03-17: Simon Goldschmidt * api_msg.c: fixed bug #47448 (netconn/socket leak if RST is received during close) 2016-03-17: Joel Cunningham * api_msg.c: don't fail closing a socket/netconn when failing to allocate the FIN segment; blocking the calling thread for a while is better than risking leaking a netconn/socket (see bug #46701) 2016-03-16: Joel Cunningham * tcp_out.c: reset rto timer on fast retransmission 2016-03-16: Deomid Ryabkov * tcp_out.c: fixed bug #46384 Segment size calculation bug with MSS != TCP_MSS 2016-03-05: Simon Goldschmidt * err.h/.c, sockets.c: ERR_IF is not necessarily a fatal error 2015-11-19: fix by Kerem Hadimli * sockets.c: fixed bug #46471: lwip_accept() leaks socket descriptors if new netconn was already closed because of peer behavior 2015-11-12: fix by Valery Ushakov * tcp_in.c: fixed bug #46365 tcp_accept_null() should call tcp_abort() 2015-10-02: Dirk Ziegelmeier/Simon Goldschmidt * snmp: cleaned up snmp structs API (fixed race conditions from bug #46089, reduce ram/rom usage of tables): incompatible change for private MIBs 2015-09-30: Simon Goldschmidt * ip4_addr.c: fixed bug #46072: ip4addr_aton() does not check the number range of all address parts 2015-08-28: Simon Goldschmidt * tcp.c, tcp_in.c: fixed bug #44023: TCP ssthresh value is unclear: ssthresh is set to the full send window for active open, too, and is updated once after SYN to ensure the correct send window is used 2015-08-28: Simon Goldschmidt * tcp: fixed bug #45559: Window scaling casts u32_t to u16_t without checks 2015-08-26: Simon Goldschmidt * ip6_frag.h/.c: fixed bug bug #41009: IPv6 reassembly broken on 64-bit platforms: define IPV6_FRAG_COPYHEADER==1 on these platforms to copy the IPv6 header instead of referencing it, which gives more room for struct ip6_reass_helper 2015-08-25: Simon Goldschmidt * sockets.c: fixed bug #45827: recvfrom: TCP window is updated with MSG_PEEK 2015-08-20: Manoj Kumar * snmp_msg.h, msg_in.c: fixed bug #43790: Sending octet string of Length >255 from SNMP agent 2015-08-19: Jens Nielsen * icmp.c, ip4.c, tcp_in.c, udp.c, raw.c: fixed bug #45120: Broadcast & multiple interfaces handling 2015-08-19: Simon Goldschmidt (patch by "Sandra") * dns.c: fixed bug #45004: dns response without answer might be discarded 2015-08-18: Chrysn * timers.c: patch #8704 fix sys_timeouts_sleeptime function 2015-07-01: Erik Ekman * puf.c: fixed bug #45454 (pbuf_take_at() skips write and returns OK if offset is at start of pbuf in chain) 2015-05-19: Simon Goldschmidt * dhcp.h/.c: fixed bugs #45140 and #45141 (dhcp was not stopped correctly after fixing bug #38204) 2015-03-21: Simon Goldschmidt (patch by Homyak) * tcp_in.c: fixed bug #44766 (LWIP_WND_SCALE: tcphdr->wnd was not scaled in two places) 2015-03-21: Simon Goldschmidt * tcp_impl.h, tcp.c, tcp_in.c: fixed bug #41318 (Bad memory ref in tcp_input() after tcp_close()) 2015-03-21: Simon Goldschmidt * tcp_in.c: fixed bug #38468 (tcp_sent() not called on half-open connection for data ACKed with the same ack as FIN) 2015-03-21: Simon Goldschmidt (patch by Christoffer Lind) * dhcp.h/.c: fixed bug #38204 (DHCP lease time not handled correctly) 2015-03-20: Simon Goldschmidt * dhcp.c: fixed bug #38714 (Missing option and client address in DHCPRELEASE message) 2015-03-19: Simon Goldschmidt * api.h, tcpip.h, api_lib.c, api_msg.c: fixed race conditions in assigning netconn->last_err (fixed bugs #38121 and #37676) 2015-03-09: Simon Goldschmidt * ip4.c: fixed the IPv4 part of bug #43904 (ip_route() must detect linkup status) 2015-03-04: Simon Goldschmidt * nd6.c: fixed bug #43784 (a host should send at least one Router Solicitation) 2015-03-04: Valery Ushakov * ip6.c: fixed bug #41094 (Byte-order bug in IPv6 fragmentation header test) 2015-03-04: Zach Smith * nd6.c: fixed bug #38153 (nd6_input() byte order issues) 2015-02-26: Simon Goldschmidt * netif.c, tcp.h/.c: fixed bug #44378 (TCP connections are not aborted on netif remove) 2015-02-25: Simon Goldschmidt * ip4.c, etharp.c: fixed bug #40177 (System hangs when dealing with corrupted packets), implemented task #12357 (Ensure that malicious packets don't assert-fail): improved some pbuf_header calls to not assert-fail. 2015-02-25: patch by Joel Cunningham * udp.h/.c, sockets.c: fixed bug #43028 (IP_MULTICAST_TTL affects unicast datagrams) 2015-02-25: patch by Greg Renda * ip4_frag.c: fixed bug #38210 (ip reassembly while remove oldest datagram) 2015-02-25: Simon Goldschmidt * sockets.c: fixed bug #38165 (socket with mulicast): ensure igmp membership are dropped when socket (not netconn!) is closed. 2015-02-25: Simon Goldschmidt * ip4.h/.c, udp.c: fixed bug #38061 (wrong multicast routing in IPv4) by adding an optional default netif for multicast routing 2015-02-25: Simon Goldschmidt * netconn API: fixed that netconn_connect still used message passing for LWIP_TCPIP_CORE_LOCKING==1 2015-02-22: patch by Jens Nielsen * icmp.c: fixed bug #38803 (Source address in broadcast ping reply) 2015-02-22: Simon Goldschmidt * udp.h, sockets.c: added proper accessor functions for pcb->multicast_ip (previously used by get/setsockopt only) 2015-02-18: Simon Goldschmidt * sockets.c: Fixed select not reporting received FIN as 'readable' in certain rare cases (bug #43779: select(), close(), and TCP retransmission error) 2015-02-17: Simon Goldschmidt * err.h, sockets.c, api_msg.c: fixed bug #38853 "connect() use a wrong errno": return ERR_ALREADY/EALRADY during connect, ERR_ISCONN/EISCONN when already connected 2015-02-17: Simon Goldschmidt * tcp_impl.h, tcp_out.c, tcp.c, api_msg.c: fixed bug #37614 "Errors from ipX_output are not processed". Now tcp_output(_segment) checks for the return value of ipX_output and does not try to send more on error. A netif driver can call tcp_txnow() (from tcpip_thread!) to try to send again if TX buffers are available again. 2015-02-14: patches by Freddie Chopin * snmp*: made community writable, fixed some const pointers 2015-02-13: Simon Goldschmidt * msg_in.c: fixed bug #22070 "MIB_OBJECT_WRITE_ONLY not implemented in SNMP" 2015-02-12: Simon Goldschmidt * ip.h, ip4.c, ip6.c: fixed bug #36403 "ip4_input() and ip6_input() always pass inp to higher layers": now the accepting netif is passed up, but the input netif is available through ip_current_input_netif() if required. 2015-02-11: patch by hichard * tcpip.c: fixed bug #43094 "The function tcpip_input() forget to handle IPv6" 2015-02-10: Simon Goldschmidt * netconn API: fixed that netconn_close/netconn_delete still used message passing for LWIP_TCPIP_CORE_LOCKING==1 2015-02-10: Simon Goldschmidt * netconn/socket api: fixed bug #44225 "closing TCP socket should time out eventually", implemented task #6930 "Implement SO_LINGER": closing TCP sockets times out after 20 seconds or after the configured SND_TIMEOUT or depending on the linger settings. 2015-01-27: Simon Goldschmidt * api_msg.c: fixed that SHUT_RD followed by SHUT_WR was different to SHUT_RDWR, fixed return value of lwip_netconn_do_close on unconnected netconns 2015-01-17: Simon Goldschmidt * sockets.c: fixed bug #43361 select() crashes with stale FDs 2015-01-17: Simon Goldschmidt * sockets.c/.h, memp_std.h: fixed bug #40788 "lwip_setsockopt_internal() crashes" by rewriting set/getsockopt functions to combine checks with the actual code and add more NULL checks; this also fixes that CORE_LOCKING used message passing for set/getsockopt. 2014-12-19: Simon Goldschmidt * opt.h, dhcp.h/.c: prevent dhcp from starting when netif link is down (only when LWIP_DHCP_CHECK_LINK_UP==1, which is disabled by default for compatibility reasons) 2014-12-17: Simon Goldschmidt * tcp_out.c: fixed bug #43840 Checksum error for TCP_CHECKSUM_ON_COPY==1 for no-copy data with odd length 2014-12-10: Simon Goldschmidt * sockets.c, tcp.c, others: fixed bug #43797 set/getsockopt: SO_SNDTIMEO/SO_RCVTIMEO take int as option but should take timeval (LWIP_SO_SNDRCVTIMEO_STANDARD==0 can be used to revert to the old 'winsock' style behaviour) Fixed implementation of SO_ACCEPTCONN to just look at the pcb state 2014-12-09: Simon Goldschmidt * ip4.c: fixed bug #43596 IGMP queries from 0.0.0.0 are discarded 2014-10-21: Simon Goldschmidt (patch by Joel Cunningham and Albert Huitsing) * sockts.c: fixed bugs #41495 Possible threading issue in select() and #43278 event_callback() handle context switch when calling sys_sem_signal() 2014-10-21: Simon Goldschmidt * api_msg.c: fixed bug #38219 Assert on TCP netconn_write with sndtimeout set 2014-09-16: Kevin Cernekee * dns.c: patch #8480 Fix handling of dns_seqno wraparound 2014-09-16: Simon Goldschmidt * tcp_out.c: fixed bug #43192 tcp_enqueue_flags() should not check TCP_SND_QUEUELEN when sending FIN 2014-09-03: Simon Goldschmidt * msg_in.c: fixed bug #39355 SNMP Memory Leak in case of error 2014-09-02: Simon Goldschmidt * err.h/.c, sockets.c, api_msg.c: fixed bug #43110 call getpeername() before listen() will cause a error 2014-09-02: Simon Goldschmidt * sockets.c: fixed bug #42117 lwip_fcntl does not set errno 2014-09-02: Simon Goldschmidt * tcp.c: fixed bug #42299 tcp_abort() leaves freed pcb on tcp_bound_pcbs list 2014-08-20: Simon Goldschmidt * dns.c: fixed bug #42987 lwIP is vulnerable to DNS cache poisoning due to non-randomized TXIDs 2014-06-03: Simon Goldschmidt * tcp_impl.h, tcp_in.c: fixed bug #37969 SYN packet dropped as short packet in tcp_input function 2014-05-20: Simon Goldschmidt * tcp_out.c: fixed bug #37184 tcp_write problem for pcbs in the SYN_SENT state 2014-05-19: Simon Goldschmidt * *.h: Fixed bug #35874 reserved identifier violation (removed leading underscores from header include guards) 2014-04-08: Simon Goldschmidt * tcp.c: Fixed bug #36167 tcp server crash when client closes (maximum window) 2014-04-06: Simon Goldschmidt * tcp_in.c: Fixed bug #36210 lwIP does not elicit an empty ACK when received unacceptable ACK 2014-04-06: Simon Goldschmidt * dhcp.c, ip4.c/.h, ip6.c/.h, udp.c/.h, ip.h: Fixed bug #41787 DHCP Discovery is invalid when an IP is set to thet netif. 2014-03-14: Simon Goldschmidt * tcp_out.c: Fixed bug #36153 TCP Cheksum error if LWIP_CHECKSUM_ON_COPY=1 2014-03-11: Simon Goldschmidt (patch by Mason) * opt.h, sockets.c: fixed bug #35928 BSD sockets functions must set errno for POSIX-compliance 2014-02-27: Simon Goldschmidt * dhcp.c: fixed bug #40303 DHCP xid renewed when sending a DHCPREQUEST 2014-02-27: Simon Goldschmidt * raw.c: fixed bug #41680 raw socket can not receive IPv6 packet when IP_SOF_BROADCAST_RECV==1 2014-02-27: Simon Goldschmidt * api_msg.c, sockets.c: fixed bug #38404 getpeeraddr returns success on unconnected/listening TCP sockets 2014-02-27: Simon Goldschmidt * sockets.c: fixed bug #41729 Some socket functions return Exyz instead of -1 2014-02-25: Simon Goldschmidt * ip4.c: fixed bug #39514 ip_route() may return an IPv6-only interface 2014-02-25: Simon Goldschmidt, patch by Fatih Asici * pbuf.c: fixed bug #39356 Wrong increment in pbuf_memfind() 2014-02-25: Simon Goldschmidt * netif.c/.h, udp.c: fixed bug #39225 udp.c uses netif_matches_ip6_addr() incorrectly; renamed function netif_matches_ip6_addr() to netif_get_ip6_addr_match() 2014-02-25: Simon Goldschmidt * igmp.c: fixed bug #39145 IGMP membership report for 224.0.0.1 2014-02-22: Simon Goldschmidt (patch by Amir Shalem) * etharp.c, opt.h: fixed bug #34681 Limit ARP queue length by ARP_QUEUE_LEN (=3) 2014-02-22: Simon Goldschmidt (patch by Amir Shalem) * etharp.h/.c: fixed bug #34682 Limit ARP request flood for unresolved entry 2014-02-20: Simon Goldschmidt * tcp_out.c: fixed bug #39683 Assertion "seg->tcphdr not aligned" failed with MEM_ALIGNMENT = 8 2014-02-20: Simon Goldschmidt * sockets.c: fixed bug #39882 No function shall set errno to 0 2014-02-20: Simon Goldschmidt * mib_structs.c: fixed bug #40050 SNMP problem with MIB arrays > 255 2014-02-20: Simon Goldschmidt * api.h, sockets.c: fixed bug #41499 netconn::recv_avail can overflow 2014-01-08: Stathis Voukelatos * memp_std.h: patch #7928 Fixed size calculation in MALLOC memory pool creation macro 2014-01-18: Brian Fahs * tcp_out.c: patch #8237: tcp_rexmit_rto fails to update pcb->unsent_oversize when necessary 2014-01-17: Grant Erickson, Jay Logue, Simon Goldschmidt * ipv6.c, netif.c: patch #7913 Enable Support for IPv6 Loopback 2014-01-16: Stathis Voukelatos * netif.c: patch #7902 Fixed netif_poll() operation when LWIP_LOOPBACK_MAX_PBUFS > 0 2014-01-14: "Freddie Chopin" * snmp.h, mib2.c: fixed constness and spelling of sysdescr 2014-01-14: Simon Goldschmidt (patch by Thomas Faber) * tcpip.c: patch #8241: Fix implicit declaration of ip_input with LWIP_TCPIP_CORE_LOCKING_INPUT disabled 2014-01-14: chrysn * timers.c: patch #8244 make timeouts usable reliably from outside of the timeout routine 2014-01-10: Simon Goldschmidt * ip_frag.c, ip6_frag.c: fixed bug #41041 Potential use-after-free in IPv6 reassembly 2014-01-10: Simon Goldschmidt * memp.c: fixed bug #41188 Alignment error in memp_init() when MEMP_SEPARATE_POOLS==1 2014-01-10: Simon Goldschmidt * tcp.c: fixed bug #39898 tcp_fasttmr() possible lock due to infinte queue process loop 2013-06-29: Simon Goldschmidt * inet.h, sockets.h: partially fixed bug #37585: IPv6 compatibility (in socket structs) 2013-06-29: Simon Goldschmidt * inet6.h: bug #37585/task #12600: fixed struct in6_addr.s6_addr to conform to spec 2013-04-24: patch by Liam * api_msg.c: patch #8008 Fix a potential null pointer dereference in assert 2013-04-24: Simon Goldschmidt * igmp.c: fixed possible division by zero 2013-04-24: Simon Goldschmidt * ip6.h, some ipv6 C files: fixed bug #38526 Coverity: Recursive Header Inclusion in ip6.h 2013-04-24: Simon Goldschmidt (patch by Emil Ljungdahl): * netif.c: fixed bug #38586 netif_loop_output() "deadlocks" 2013-01-15: Simon Goldschmidt * ip4.c: fixed bug #37665 ip_canforward operates on address in wrong byte order 2013-01-15: Simon Goldschmidt * pbuf.h: fixed bug #38097 pbuf_free_ooseq() warning 2013-01-14: Simon Goldschmidt * dns.c: fixed bug #37705 Possible memory corruption in DNS query 2013-01-11: Simon Goldschmidt * raw.c: fixed bug #38066 Raw pcbs can alter packet without eating it 2012-08-22: Simon Goldschmidt * memp.c: fixed bug #37166: memp_sanity check loops itself 2012-08-13: Simon Goldschmidt * dhcp.c: fixed bug #36645: Calling dhcp_release before dhcp_start dereferences NULL 2012-08-13: Simon Goldschmidt * msg_out.c: fixed bug #36840 snmp_send_trap() NULL de-reference if traps configured but no interfaces available 2012-08-13: Simon Goldschmidt * dns.c: fixed bug #36899 DNS TTL 0 is cached for a long time 2012-05-11: Simon Goldschmidt (patch by Marty) * memp.c: fixed bug #36412: memp.c does not compile when MEMP_OVERFLOW_CHECK > zero and MEMP_SEPARATE_POOLS == 1 2012-05-03: Simon Goldschmidt (patch by Sylvain Rochet) * ppp.c: fixed bug #36283 (PPP struct used on header size computation and not packed) 2012-05-03: Simon Goldschmidt (patch by David Empson) * ppp.c: fixed bug #36388 (PPP: checksum-only in last pbuf leads to pbuf with zero length) 2012-03-25: Simon Goldschmidt * api_msg.c: Fixed bug #35817: do_connect() invalidly signals op_completed for UDP/RAW with LWIP_TCPIP_CORE_LOCKING==1 2012-03-25: Simon Goldschmidt * api_msg.h, api_lib.c, api_msg.c, netifapi.c: fixed bug #35931: Name space pollution in api_msg.c and netifapi.c 2011-08-24: Simon Goldschmidt * inet6.h: fixed bug #34124 struct in6_addr does not conform to the standard (STABLE-1.4.1) ++ New features: 2012-03-25: Simon Goldschmidt (idea by Mason) * posix/*: added posix-compatibility include files posix/netdb.h and posix/sys/socket.h which are a simple wrapper to the correct lwIP include files. 2012-01-16: Simon Goldschmidt * opt.h, icmp.c: Added option CHECKSUM_GEN_ICMP 2011-12-17: Simon Goldschmidt * ip.h: implemented API functions to access so_options of IP pcbs (UDP, TCP, RAW) (fixes bug #35061) 2011-09-27: Simon Goldschmidt * opt.h, tcp.c, tcp_in.c: Implemented limiting data on ooseq queue (task #9989) (define TCP_OOSEQ_MAX_BYTES / TCP_OOSEQ_MAX_PBUFS in lwipopts.h) 2011-09-21: Simon Goldschmidt * opt.h, api.h, api_lib.c, api_msg.h/.c, sockets.c: Implemented timeout on send (TCP only, bug #33820) 2011-09-21: Simon Goldschmidt * init.c: Converted runtime-sanity-checks into compile-time checks that can be disabled (since runtime checks can often not be seen on embedded targets) 2011-09-11: Simon Goldschmidt * ppp.h, ppp_impl.h: splitted ppp.h to an internal and external header file to get a clear separation of which functions an application or port may use (task #11281) 2011-09-11: Simon Goldschmidt * opt.h, tcp_impl.h, tcp.c, udp.h/.c: Added a config option to randomize initial local TCP/UDP ports (so that different port ranges are used after a reboot; bug #33818; this one added tcp_init/udp_init functions again) 2011-09-03: Simon Goldschmidt * dhcp.c: DHCP uses LWIP_RAND() for xid's (bug #30302) 2011-08-24: Simon Goldschmidt * opt.h, netif.h/.c: added netif remove callback (bug #32397) 2011-07-26: Simon Goldschmidt * etharp.c: ETHARP_SUPPORT_VLAN: add support for an external VLAN filter function instead of only checking for one VLAN (define ETHARP_VLAN_CHECK_FN) 2011-07-21: Simon Goldschmidt (patch by hanhui) * ip4.c, etharp.c, pbuf.h: bug #33634 ip_forward() have a faulty behaviour: Added pbuf flags to mark incoming packets as link-layer broadcast/multicast. Also added code to allow ip_forward() to forward non-broadcast packets to the input netif (set IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1). 2011-06-26: Simon Goldschmidt (patch by Cameron Gutman) * tcp.c, tcp_out.c: bug #33604: added some more asserts to check that pcb->state != LISTEN 2011-05-14: Simon Goldschmidt (patch by Stéphane Lesage) * tcpip.c/.h: patch #7449 allow tcpip callback from interrupt with static memory message ++ Bugfixes: 2012-09-26: Simon Goldschmidt * api_msg.c: fixed bug #37405 'err_tcp()' uses already freed 'netconn' object 2012-09-26: patch by Henrik Persson * dhcp.c: patch #7843 Fix corner case with dhcp timeouts 2012-09-26: patch by Henrik Persson * dhcp.c: patch #7840 Segfault in dhcp_parse_reply if no end marker in dhcp packet 2012-08-22: Simon Goldschmidt * memp.c: fixed bug #37166: memp_sanity check loops itself 2012-05-08: Simon Goldschmidt * tcp_out.c: fixed bug: #36380 unsent_oversize mismatch in 1.4.1RC1 (this was a debug-check issue only) 2012-03-27: Simon Goldschmidt * vj.c: fixed bug #35756 header length calculation problem in ppp/vj.c 2012-03-27: Simon Goldschmidt (patch by Mason) * tcp_out.c: fixed bug #35945: SYN packet should provide the recv MSS not the send MSS 2012-03-22: Simon Goldschmidt * ip4.c: fixed bug #35927: missing refragmentaion in ip_forward 2012-03-20: Simon Goldschmidt (patch by Mason) * netdb.c: fixed bug #35907: lwip_gethostbyname_r returns an invalid h_addr_list 2012-03-12: Simon Goldschmidt (patch by Bostjan Meglic) * ppp.c: fixed bug #35809: PPP GetMask(): Compiler warning on big endian, possible bug on little endian system 2012-02-23: Simon Goldschmidt * etharp.c: fixed bug #35595: Impossible to send broadcast without a gateway (introduced when fixing bug# 33551) 2012-02-16: Simon Goldschmidt * ppp.c: fixed pbuf leak when PPP session is aborted through pppSigHUP() (bug #35541: PPP Memory Leak) 2012-02-16: Simon Goldschmidt * etharp.c: fixed bug #35531: Impossible to send multicast without a gateway (introduced when fixing bug# 33551) 2012-02-16: Simon Goldschmidt (patch by Stéphane Lesage) * msg_in.c, msg_out.c: fixed bug #35536 SNMP: error too big response is malformed 2012-02-15: Simon Goldschmidt * init.c: fixed bug #35537: MEMP_NUM_* sanity checks should be disabled with MEMP_MEM_MALLOC==1 2012-02-12: Simon Goldschmidt * tcp.h, tcp_in.c, tcp_out.c: partly fixed bug #25882: TCP hangs on MSS > pcb->snd_wnd (by not creating segments bigger than half the window) 2012-02-11: Simon Goldschmidt * tcp.c: fixed bug #35435: No pcb state check before adding it to time-wait queue while closing 2012-01-22: Simon Goldschmidt * tcp.c, tcp_in.c: fixed bug #35305: pcb may be freed too early on shutdown(WR) 2012-01-21: Simon Goldschmidt * tcp.c: fixed bug #34636: FIN_WAIT_2 - Incorrect shutdown of TCP pcb 2012-01-20: Simon Goldschmidt * dhcp.c: fixed bug #35151: DHCP asserts on incoming option lengths 2012-01-20: Simon Goldschmidt * pbuf.c: fixed bug #35291: NULL pointer in pbuf_copy 2011-11-25: Simon Goldschmidt * tcp.h/.c, tcp_impl.h, tcp_in.c: fixed bug #31177: tcp timers can corrupt tcp_active_pcbs in some cases 2011-11-23: Simon Goldschmidt * sys.c: fixed bug #34884: sys_msleep() body needs to be surrounded with '#ifndef sys_msleep' 2011-11-22: Simon Goldschmidt * netif.c, etharp.h/.c: fixed bug #34684: Clear the arp table cache when netif is brought down 2011-10-28: Simon Goldschmidt * tcp_in.c: fixed bug #34638: Dead code in tcp_receive - pcb->dupacks 2011-10-23: Simon Goldschmidt * mem.c: fixed bug #34429: possible memory corruption with LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT set to 1 2011-10-18: Simon Goldschmidt * arch.h, netdb.c: fixed bug #34592: lwip_gethostbyname_r uses nonstandard error value 2011-10-18: Simon Goldschmidt * opt.h: fixed default values of TCP_SNDLOWAT and TCP_SNDQUEUELOWAT for small windows (bug #34176 select after non-blocking send times out) 2011-10-18: Simon Goldschmidt * tcp_impl.h, tcp_out.c: fixed bug #34587: TCP_BUILD_MSS_OPTION doesn't consider netif->mtu, causes slow network 2011-10-18: Simon Goldschmidt * sockets.c: fixed bug #34581 missing parentheses in udplite sockets code 2011-10-18: Simon Goldschmidt * sockets.h: fixed bug #34580 fcntl() is missing in LWIP_COMPAT_SOCKETS 2011-10-17: Simon Goldschmidt * api_msg.c: fixed bug #34569: shutdown(SHUT_WR) crashes netconn/socket api 2011-10-13: Simon Goldschmidt * tcp_in.c, tcp_out.c: fixed bug #34517 (persist timer is started although no zero window is received) by starting the persist timer when a zero window is received, not when we have more data queued for sending than fits into the window 2011-10-13: Simon Goldschmidt * def.h, timers.c: fixed bug #34541: LWIP_U32_DIFF is unnecessarily complex 2011-10-13: Simon Goldschmidt * sockets.c, api_lib.c: fixed bug #34540: compiler error when CORE_LOCKING is used and not all protocols are enabled 2011-10-12: Simon Goldschmidt * pbuf.c: fixed bug #34534: Error in sending fragmented IP if MEM_ALIGNMENT > 4 2011-10-09: Simon Goldschmidt * tcp_out.c: fixed bug #34426: tcp_zero_window_probe() transmits incorrect byte value when pcb->unacked != NULL 2011-10-09: Simon Goldschmidt * ip4.c: fixed bug #34447 LWIP_IP_ACCEPT_UDP_PORT(dst_port) wrong 2011-09-27: Simon Goldschmidt * tcp_in.c, tcp_out.c: Reset pcb->unsent_oversize in 2 more places... 2011-09-27: Simon Goldschmidt * tcp_in.c: fixed bug #28288: Data after FIN in oos queue 2011-09-27: Simon Goldschmidt * dhcp.c: fixed bug #34406 dhcp_option_hostname() can overflow the pbuf 2011-09-24: Simon Goldschmidt * mem.h: fixed bug #34377 MEM_SIZE_F is not defined if MEM_LIBC_MALLOC==1 2011-09-23: Simon Goldschmidt * pbuf.h, tcp.c, tcp_in.c: fixed bug #33871: rejecting TCP_EVENT_RECV() for the last packet including FIN can lose data 2011-09-22: Simon Goldschmidt * tcp_impl.h: fixed bug #34355: nagle does not take snd_buf/snd_queuelen into account 2011-09-21: Simon Goldschmidt * opt.h: fixed default value of TCP_SND_BUF to not violate the sanity checks in init.c 2011-09-20: Simon Goldschmidt * timers.c: fixed bug #34337 (possible NULL pointer in sys_check_timeouts) 2011-09-11: Simon Goldschmidt * tcp_out.c: use pcb->mss instead of TCP_MSS for preallocate mss-sized pbufs (bug #34019) 2011-09-09: Simon Goldschmidt * udp.c: fixed bug #34072: UDP broadcast is received from wrong UDP pcb if udp port matches 2011-09-03: Simon Goldschmidt * tcp_in.c: fixed bug #33952 PUSH flag in incoming packet is lost when packet is aggregated and sent to application 2011-09-01: Simon Goldschmidt * opt.h: fixed bug #31809 LWIP_EVENT_API in opts.h is inconsistent compared to other options 2011-09-01: Simon Goldschmidt * tcp_in.c: fixed bug #34111 RST for ACK to listening pcb has wrong seqno 2011-08-24: Simon Goldschmidt * api_msg.c, sockets.c: fixed bug #33956 Wrong error returned when calling accept() on UDP connections 2011-08-24: Simon Goldschmidt * sockets.h: fixed bug #34057 socklen_t should be a typedef 2011-08-24: Simon Goldschmidt * pbuf.c: fixed bug #34112 Odd check in pbuf_alloced_custom (typo) 2011-08-24: Simon Goldschmidt * dhcp.c: fixed bug #34122 dhcp: hostname can overflow 2011-08-24: Simon Goldschmidt * netif.c: fixed bug #34121 netif_add/netif_set_ipaddr fail on NULL ipaddr 2011-08-22: Simon Goldschmidt * tcp_out.c: fixed bug #33962 TF_FIN not always set after FIN is sent. (This merely prevents nagle from not transmitting fast after closing.) 2011-07-22: Simon Goldschmidt * api_lib.c, api_msg.c, sockets.c, api.h: fixed bug #31084 (socket API returns always EMSGSIZE on non-blocking sockets if data size > send buffers) -> now lwip_send() sends as much as possible for non-blocking sockets 2011-07-22: Simon Goldschmidt * pbuf.c/.h, timers.c: freeing ooseq pbufs when the pbuf pool is empty implemented for NO_SYS==1: when not using sys_check_timeouts(), call PBUF_CHECK_FREE_OOSEQ() at regular intervals from main level. 2011-07-21: Simon Goldschmidt * etharp.c: fixed bug #33551 (ARP entries may time out although in use) by sending an ARP request when an ARP entry is used in the last minute before it would time out. 2011-07-04: Simon Goldschmidt * sys_arch.txt: Fixed documentation after changing sys arch prototypes for 1.4.0. 2011-06-26: Simon Goldschmidt * tcp.c: fixed bug #31723 (tcp_kill_prio() kills pcbs with the same prio) by updating its documentation only. 2011-06-26: Simon Goldschmidt * mem.c: fixed bug #33545: With MEM_USE_POOLS==1, mem_malloc can return an unaligned pointer. 2011-06-26: Simon Goldschmidt * mem.c: fixed bug #33544 "warning in mem.c in lwip 1.4.0 with NO_SYS=1" 2011-05-25: Simon Goldschmidt * tcp.c: fixed bug #33398 (pointless conversion when checking TCP port range) (STABLE-1.4.0) ++ New features: 2011-03-27: Simon Goldschmidt * tcp_impl.h, tcp_in.c, tcp_out.c: Removed 'dataptr' from 'struct tcp_seg' and calculate it in tcp_zero_window_probe (the only place where it was used). 2010-11-21: Simon Goldschmidt * dhcp.c/.h: Added a function to deallocate the struct dhcp from a netif (fixes bug #31525). 2010-07-12: Simon Goldschmidt (patch by Stephane Lesage) * ip.c, udp.c/.h, pbuf.h, sockets.c: task #10495: Added support for IP_MULTICAST_LOOP at socket- and raw-API level. 2010-06-16: Simon Goldschmidt * ip.c: Added an optional define (LWIP_IP_ACCEPT_UDP_PORT) that can allow link-layer-addressed UDP traffic to be received while a netif is down (just like DHCP during configuration) 2010-05-22: Simon Goldschmidt * many many files: bug #27352: removed packing from ip_addr_t, the packed version is now only used in protocol headers. Added global storage for current src/dest IP address while in input functions. 2010-05-16: Simon Goldschmidt * def.h: task #10391: Add preprocessor-macros for compile-time htonl calculation (and use them throughout the stack where applicable) 2010-05-16: Simon Goldschmidt * opt.h, memp_std.h, memp.c, ppp_oe.h/.c: PPPoE now uses its own MEMP pool instead of the heap (moved struct pppoe_softc from ppp_oe.c to ppp_oe.h) 2010-05-16: Simon Goldschmidt * opt.h, memp_std.h, dns.h/.c: DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses its own MEMP pool instead of the heap 2010-05-13: Simon Goldschmidt * tcp.c, udp.c: task #6995: Implement SO_REUSEADDR (correctly), added new option SO_REUSE_RXTOALL to pass received UDP broadcast/multicast packets to more than one pcb. 2010-05-02: Simon Goldschmidt * netbuf.h/.c, sockets.c, api_msg.c: use checksum-on-copy for sending UDP data for LWIP_NETIF_TX_SINGLE_PBUF==1 2010-04-30: Simon Goldschmidt * udp.h/.c, pbuf.h/.c: task #6849: added udp_send(_to/_if) functions that take a precalculated checksum, added pbuf_fill_chksum() to copy data into a pbuf and at the same time calculating the checksum for that data 2010-04-29: Simon Goldschmidt * ip_addr.h, etharp.h/.c, autoip.c: Create overridable macros for copying 2-byte-aligned IP addresses and MAC addresses 2010-04-28: Patch by Bill Auerbach * ip.c: Inline generating IP checksum to save a function call 2010-04-14: Simon Goldschmidt * tcpip.h/.c, timers.c: Added an overridable define to get informed when the tcpip_thread processes messages or timeouts to implement a watchdog. 2010-03-28: Simon Goldschmidt * ip_frag.c: create a new (contiguous) PBUF_RAM for every outgoing fragment if LWIP_NETIF_TX_SINGLE_PBUF==1 2010-03-27: Simon Goldschmidt * etharp.c: Speedup TX by moving code from find_entry to etharp_output/ etharp_query to prevent unnecessary function calls (inspired by patch #7135). 2010-03-20: Simon Goldschmidt * opt.h, tcpip.c/.h: Added an option to disable tcpip_(un)timeout code since the linker cannot do this automatically to save space. 2010-03-20: Simon Goldschmidt * opt.h, etharp.c/.h: Added support for static ARP table entries 2010-03-14: Simon Goldschmidt * tcp_impl.h, tcp_out.c, inet_chksum.h/.c: task #6849: Calculate checksum when creating TCP segments, not when (re-)transmitting them. 2010-03-07: Simon Goldschmidt * sockets.c: bug #28775 (select/event_callback: only check select_cb_list on change) plus use SYS_LIGHTWEIGHT_PROT to protect the select code. This should speed up receiving data on sockets as the select code in event_callback is only executed when select is waiting. 2010-03-06: Simon Goldschmidt * tcp_out.c: task #7013 (Create option to have all packets delivered to netif->output in one piece): Always copy to try to create single pbufs in tcp_write. 2010-03-06: Simon Goldschmidt * api.h, api_lib.c, sockets.c: task #10167 (sockets: speed up TCP recv by not allocating a netbuf): added function netconn_recv_tcp_pbuf() for tcp netconns to receive pbufs, not netbufs; use that function for tcp sockets. 2010-03-05: Jakob Ole Stoklundsen / Simon Goldschmidt * opt.h, tcp.h, tcp_impl.h, tcp.c, tcp_in.c, tcp_out.c: task #7040: Work on tcp_enqueue: Don't waste memory when chaining segments, added option TCP_OVERSIZE to prevent creating many small pbufs when calling tcp_write with many small blocks of data. Instead, pbufs are allocated larger than needed and the space is used for later calls to tcp_write. 2010-02-21: Simon Goldschmidt * stats.c/.h: Added const char* name to mem- and memp-stats for easier debugging. 2010-02-21: Simon Goldschmidt * tcp.h (and usages), added tcp_impl.h: Splitted API and internal implementation of tcp to make API usage cleare to application programmers 2010-02-14: Simon Goldschmidt/Stephane Lesage * ip_addr.h: Improved some defines working on ip addresses, added faster macro to copy addresses that cannot be NULL 2010-02-13: Simon Goldschmidt * api.h, api_lib.c, api_msg.c, sockets.c: task #7865 (implement non- blocking send operation) 2010-02-12: Simon Goldschmidt * sockets.c/.h: Added a minimal version of posix fctl() to have a standardised way to set O_NONBLOCK for nonblocking sockets. 2010-02-12: Simon Goldschmidt * dhcp.c/.h, autoip.c/.h: task #10139 (Prefer statically allocated memory): added autoip_set_struct() and dhcp_set_struct() to let autoip and dhcp work with user-allocated structs instead of callin mem_malloc 2010-02-12: Simon Goldschmidt/Jeff Barber * tcp.c/h: patch #6865 (SO_REUSEADDR for TCP): if pcb.so_options has SOF_REUSEADDR set, allow binding to endpoint in TIME_WAIT 2010-02-12: Simon Goldschmidt * sys layer: task #10139 (Prefer statically allocated memory): converted mbox and semaphore functions to take pointers to sys_mbox_t/sys_sem_t; converted sys_mbox_new/sys_sem_new to take pointers and return err_t; task #7212: Add Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX to let sys.h use binary semaphores instead of mutexes - as before) 2010-02-09: Simon Goldschmidt (Simon Kallweit) * timers.c/.h: Added function sys_restart_timeouts() from patch #7085 (Restart system timeout handling) 2010-02-09: Simon Goldschmidt * netif.c/.h, removed loopif.c/.h: task #10153 (Integrate loopif into netif.c) - loopif does not have to be created by the port any more, just define LWIP_HAVE_LOOPIF to 1. 2010-02-08: Simon Goldschmidt * inet.h, ip_addr.c/.h: Added reentrant versions of inet_ntoa/ipaddr_ntoa inet_ntoa_r/ipaddr_ntoa_r 2010-02-08: Simon Goldschmidt * netif.h: Added netif_s/get_igmp_mac_filter() macros 2010-02-05: Simon Goldschmidt * netif.h: Added function-like macros to get/set the hostname on a netif 2010-02-04: Simon Goldschmidt * nearly every file: Replaced struct ip_addr by typedef ip_addr_t to make changing the actual implementation behind the typedef easier. 2010-02-01: Simon Goldschmidt * opt.h, memp_std.h, dns.h, netdb.c, memp.c: Let netdb use a memp pool for allocating memory when getaddrinfo() is called. 2010-01-31: Simon Goldschmidt * dhcp.h, dhcp.c: Reworked the code that parses DHCP options: parse them once instead of parsing for every option. This also removes the need for mem_malloc from dhcp_recv and makes it possible to correctly retrieve the BOOTP file. 2010-01-30: simon Goldschmidt * sockets.c: Use SYS_LIGHTWEIGHT_PROT instead of a semaphore to protect the sockets array. 2010-01-29: Simon Goldschmidt (patch by Laura Garrett) * api.h, api_msg.c, sockets.c: Added except set support in select (patch #6860) 2010-01-29: Simon Goldschmidt (patch by Laura Garrett) * api.h, sockets.h, err.h, api_lib.c, api_msg.c, sockets.c, err.c: Add non-blocking support for connect (partly from patch #6860), plus many cleanups in socket & netconn API. 2010-01-27: Simon Goldschmidt * opt.h, tcp.h, init.c, api_msg.c: Added TCP_SNDQUEUELOWAT corresponding to TCP_SNDLOWAT and added tcp_sndqueuelen() - this fixes bug #28605 2010-01-26: Simon Goldschmidt * snmp: Use memp pools for snmp instead of the heap; added 4 new pools. 2010-01-14: Simon Goldschmidt * ppp.c/.h: Fixed bug #27856: PPP: Set netif link- and status-callback by adding ppp_set_netif_statuscallback()/ppp_set_netif_linkcallback() 2010-01-13: Simon Goldschmidt * mem.c: The heap now may be moved to user-defined memory by defining LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address (patch #6966 and bug #26133) 2010-01-10: Simon Goldschmidt (Bill Auerbach) * opt.h, memp.c: patch #6822 (Add option to place memory pools in separate arrays) 2010-01-10: Simon Goldschmidt * init.c, igmp.c: patch #6463 (IGMP - Adding Random Delay): added define LWIP_RAND() for lwip-wide randomization (to be defined in cc.h) 2009-12-31: Simon Goldschmidt * tcpip.c, init.c, memp.c, sys.c, memp_std.h, sys.h, tcpip.h added timers.c/.h: Separated timer implementation from semaphore/mbox implementation, moved timer implementation to timers.c/.h, timers are now only called from tcpip_thread or by explicitly checking them. (TASK#7235) 2009-12-27: Simon Goldschmidt * opt.h, etharp.h/.c, init.c, tcpip.c: Added an additional option LWIP_ETHERNET to support ethernet without ARP (necessary for pure PPPoE) ++ Bugfixes: 2011-04-20: Simon Goldschmidt * sys_arch.txt: sys_arch_timeouts() is not needed any more. 2011-04-13: Simon Goldschmidt * tcp.c, udp.c: Fixed bug #33048 (Bad range for IP source port numbers) by using ports in the IANA private/dynamic range (49152 through 65535). 2011-03-29: Simon Goldschmidt, patch by Emil Lhungdahl: * etharp.h/.c: Fixed broken VLAN support. 2011-03-27: Simon Goldschmidt * tcp.c: Fixed bug #32926 (TCP_RMV(&tcp_bound_pcbs) is called on unbound tcp pcbs) by checking if the pcb was bound (local_port != 0). 2011-03-27: Simon Goldschmidt * ppp.c: Fixed bug #32280 (ppp: a pbuf is freed twice) 2011-03-27: Simon Goldschmidt * sockets.c: Fixed bug #32906: lwip_connect+lwip_send did not work for udp and raw pcbs with LWIP_TCPIP_CORE_LOCKING==1. 2011-03-27: Simon Goldschmidt * tcp_out.c: Fixed bug #32820 (Outgoing TCP connections created before route is present never times out) by starting retransmission timer before checking route. 2011-03-22: Simon Goldschmidt * ppp.c: Fixed bug #32648 (PPP code crashes when terminating a link) by only calling sio_read_abort() if the file descriptor is valid. 2011-03-14: Simon Goldschmidt * err.h/.c, sockets.c, api_msg.c: fixed bug #31748 (Calling non-blocking connect more than once can render a socket useless) since it mainly involves changing "FATAL" classification of error codes: ERR_USE and ERR_ISCONN just aren't fatal. 2011-03-13: Simon Goldschmidt * sockets.c: fixed bug #32769 (ESHUTDOWN is linux-specific) by fixing err_to_errno_table (ERR_CLSD: ENOTCONN instead of ESHUTDOWN), ERR_ISCONN: use EALRADY instead of -1 2011-03-13: Simon Goldschmidt * api_lib.c: netconn_accept: return ERR_ABRT instead of ERR_CLSD if the connection has been aborted by err_tcp (since this is not a normal closing procedure). 2011-03-13: Simon Goldschmidt * tcp.c: tcp_bind: return ERR_VAL instead of ERR_ISCONN when trying to bind with pcb->state != CLOSED 2011-02-17: Simon Goldschmidt * rawapi.txt: Fixed bug #32561 tcp_poll argument definition out-of-order in documentation 2011-02-17: Simon Goldschmidt * many files: Added missing U/UL modifiers to fix 16-bit-arch portability. 2011-01-24: Simon Goldschmidt * sockets.c: Fixed bug #31741: lwip_select seems to have threading problems 2010-12-02: Simon Goldschmidt * err.h: Fixed ERR_IS_FATAL so that ERR_WOULDBLOCK is not fatal. 2010-11-23: Simon Goldschmidt * api.h, api_lib.c, api_msg.c, sockets.c: netconn.recv_avail is only used for LWIP_SO_RCVBUF and ioctl/FIONREAD. 2010-11-23: Simon Goldschmidt * etharp.c: Fixed bug #31720: ARP-queueing: RFC 1122 recommends to queue at least 1 packet -> ARP_QUEUEING==0 now queues the most recent packet. 2010-11-23: Simon Goldschmidt * tcp_in.c: Fixed bug #30577: tcp_input: don't discard ACK-only packets after refusing 'refused_data' again. 2010-11-22: Simon Goldschmidt * sockets.c: Fixed bug #31590: getsockopt(... SO_ERROR ...) gives EINPROGRESS after a successful nonblocking connection. 2010-11-22: Simon Goldschmidt * etharp.c: Fixed bug #31722: IP packets sent with an AutoIP source addr must be sent link-local 2010-11-22: Simon Goldschmidt * timers.c: patch #7329: tcp_timer_needed prototype was ifdef'ed out for LWIP_TIMERS==0 2010-11-20: Simon Goldschmidt * sockets.c: Fixed bug #31170: lwip_setsockopt() does not set socket number 2010-11-20: Simon Goldschmidt * sockets.h: Fixed bug #31304: Changed SHUT_RD, SHUT_WR and SHUT_RDWR to resemble other stacks. 2010-11-20: Simon Goldschmidt * dns.c: Fixed bug #31535: TCP_SND_QUEUELEN must be at least 2 or else no-copy TCP writes will never succeed. 2010-11-20: Simon Goldschmidt * dns.c: Fixed bug #31701: Error return value from dns_gethostbyname() does not match documentation: return ERR_ARG instead of ERR_VAL if not initialized or wrong argument. 2010-10-20: Simon Goldschmidt * sockets.h: Fixed bug #31385: sizeof(struct sockaddr) is 30 but should be 16 2010-10-05: Simon Goldschmidt * dhcp.c: Once again fixed #30038: DHCP/AutoIP cooperation failed when replugging the network cable after an AutoIP address was assigned. 2010-08-10: Simon Goldschmidt * tcp.c: Fixed bug #30728: tcp_new_port() did not check listen pcbs 2010-08-03: Simon Goldschmidt * udp.c, raw.c: Don't chain empty pbufs when sending them (fixes bug #30625) 2010-08-01: Simon Goldschmidt (patch by Greg Renda) * ppp.c: Applied patch #7264 (PPP protocols are rejected incorrectly on big endian architectures) 2010-07-28: Simon Goldschmidt * api_lib.c, api_msg.c, sockets.c, mib2.c: Fixed compilation with TCP or UDP disabled. 2010-07-27: Simon Goldschmidt * tcp.c: Fixed bug #30565 (tcp_connect() check bound list): that check did no harm but never did anything 2010-07-21: Simon Goldschmidt * ip.c: Fixed invalid fix for bug #30402 (CHECKSUM_GEN_IP_INLINE does not add IP options) 2010-07-16: Kieran Mansley * msg_in.c: Fixed SNMP ASN constant defines to not use ! operator 2010-07-10: Simon Goldschmidt * ip.c: Fixed bug #30402: CHECKSUM_GEN_IP_INLINE does not add IP options 2010-06-30: Simon Goldschmidt * api_msg.c: fixed bug #30300 (shutdown parameter was not initialized in netconn_delete) 2010-06-28: Kieran Mansley * timers.c remove unportable printing of C function pointers 2010-06-24: Simon Goldschmidt * init.c, timers.c/.h, opt.h, memp_std.h: From patch #7221: added flag NO_SYS_NO_TIMERS to drop timer support for NO_SYS==1 for easier upgrading 2010-06-24: Simon Goldschmidt * api(_lib).c/.h, api_msg.c/.h, sockets.c/.h: Fixed bug #10088: Correctly implemented shutdown at socket level. 2010-06-21: Simon Goldschmidt * pbuf.c/.h, ip_frag.c/.h, opt.h, memp_std.h: Fixed bug #29361 (ip_frag has problems with zero-copy DMA MACs) by adding custom pbufs and implementing custom pbufs that reference other (original) pbufs. Additionally set IP_FRAG_USES_STATIC_BUF=0 as default to be on the safe side. 2010-06-15: Simon Goldschmidt * dhcp.c: Fixed bug #29970: DHCP endian issue parsing option responses 2010-06-14: Simon Goldschmidt * autoip.c: Fixed bug #30039: AutoIP does not reuse previous addresses 2010-06-12: Simon Goldschmidt * dhcp.c: Fixed bug #30038: dhcp_network_changed doesn't reset AUTOIP coop state 2010-05-17: Simon Goldschmidt * netdb.c: Correctly NULL-terminate h_addr_list 2010-05-16: Simon Goldschmidt * def.h/.c: changed the semantics of LWIP_PREFIX_BYTEORDER_FUNCS to prevent "symbol already defined" i.e. when linking to winsock 2010-05-05: Simon Goldschmidt * def.h, timers.c: Fixed bug #29769 (sys_check_timeouts: sys_now() may overflow) 2010-04-21: Simon Goldschmidt * api_msg.c: Fixed bug #29617 (sometime cause stall on delete listening connection) 2010-03-28: Luca Ceresoli * ip_addr.c/.h: patch #7143: Add a few missing const qualifiers 2010-03-27: Luca Ceresoli * mib2.c: patch #7130: remove meaningless const qualifiers 2010-03-26: Simon Goldschmidt * tcp_out.c: Make LWIP_NETIF_TX_SINGLE_PBUF work for TCP, too 2010-03-26: Simon Goldschmidt * various files: Fixed compiling with different options disabled (TCP/UDP), triggered by bug #29345; don't allocate acceptmbox if LWIP_TCP is disabled 2010-03-25: Simon Goldschmidt * sockets.c: Fixed bug #29332: lwip_select() processes readset incorrectly 2010-03-25: Simon Goldschmidt * tcp_in.c, test_tcp_oos.c: Fixed bug #29080: Correctly handle remote side overrunning our rcv_wnd in ooseq case. 2010-03-22: Simon Goldschmidt * tcp.c: tcp_listen() did not copy the pcb's prio. 2010-03-19: Simon Goldschmidt * snmp_msg.c: Fixed bug #29256: SNMP Trap address was not correctly set 2010-03-14: Simon Goldschmidt * opt.h, etharp.h: Fixed bug #29148 (Incorrect PBUF_POOL_BUFSIZE for ports where ETH_PAD_SIZE > 0) by moving definition of ETH_PAD_SIZE to opt.h and basing PBUF_LINK_HLEN on it. 2010-03-08: Simon Goldschmidt * netif.c, ipv4/ip.c: task #10241 (AutoIP: don't break existing connections when assiging routable address): when checking incoming packets and aborting existing connection on address change, filter out link-local addresses. 2010-03-06: Simon Goldschmidt * sockets.c: Fixed LWIP_NETIF_TX_SINGLE_PBUF for LWIP_TCPIP_CORE_LOCKING 2010-03-06: Simon Goldschmidt * ipv4/ip.c: Don't try to forward link-local addresses 2010-03-06: Simon Goldschmidt * etharp.c: Fixed bug #29087: etharp: don't send packets for LinkLocal- addresses to gw 2010-03-05: Simon Goldschmidt * dhcp.c: Fixed bug #29072: Correctly set ciaddr based on message-type and state. 2010-03-05: Simon Goldschmidt * api_msg.c: Correctly set TCP_WRITE_FLAG_MORE when netconn_write is split into multiple calls to tcp_write. 2010-02-21: Simon Goldschmidt * opt.h, mem.h, dns.c: task #10140: Remove DNS_USES_STATIC_BUF (keep the implementation of DNS_USES_STATIC_BUF==1) 2010-02-20: Simon Goldschmidt * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Task #10088: Correctly implement close() vs. shutdown(). Now the application does not get any more recv callbacks after calling tcp_close(). Added tcp_shutdown(). 2010-02-19: Simon Goldschmidt * mem.c/.h, pbuf.c: Renamed mem_realloc() to mem_trim() to prevent confusion with realloc() 2010-02-15: Simon Goldschmidt/Stephane Lesage * netif.c/.h: Link status does not depend on LWIP_NETIF_LINK_CALLBACK (fixes bug #28899) 2010-02-14: Simon Goldschmidt * netif.c: Fixed bug #28877 (Duplicate ARP gratuitous packet with LWIP_NETIF_LINK_CALLBACK set on) by only sending if both link- and admin-status of a netif are up 2010-02-14: Simon Goldschmidt * opt.h: Disable ETHARP_TRUST_IP_MAC by default since it slows down packet reception and is not really necessary 2010-02-14: Simon Goldschmidt * etharp.c/.h: Fixed ARP input processing: only add a new entry if a request was directed as us (RFC 826, Packet Reception), otherwise only update existing entries; internalized some functions 2010-02-14: Simon Goldschmidt * netif.h, etharp.c, tcpip.c: Fixed bug #28183 (ARP and TCP/IP cannot be disabled on netif used for PPPoE) by adding a new netif flag (NETIF_FLAG_ETHERNET) that tells the stack the device is an ethernet device but prevents usage of ARP (so that ethernet_input can be used for PPPoE). 2010-02-12: Simon Goldschmidt * netif.c: netif_set_link_up/down: only do something if the link state actually changes 2010-02-12: Simon Goldschmidt/Stephane Lesage * api_msg.c: Fixed bug #28865 (Cannot close socket/netconn in non-blocking connect) 2010-02-12: Simon Goldschmidt * mem.h: Fixed bug #28866 (mem_realloc function defined in mem.h) 2010-02-09: Simon Goldschmidt * api_lib.c, api_msg.c, sockets.c, api.h, api_msg.h: Fixed bug #22110 (recv() makes receive window update for data that wasn't received by application) 2010-02-09: Simon Goldschmidt/Stephane Lesage * sockets.c: Fixed bug #28853 (lwip_recvfrom() returns 0 on receive time-out or any netconn_recv() error) 2010-02-09: Simon Goldschmidt * ppp.c: task #10154 (PPP: Update snmp in/out counters for tx/rx packets) 2010-02-09: Simon Goldschmidt * netif.c: For loopback packets, adjust the stats- and snmp-counters for the loopback netif. 2010-02-08: Simon Goldschmidt * igmp.c/.h, ip.h: Moved most defines from igmp.h to igmp.c for clarity since they are not used anywhere else. 2010-02-08: Simon Goldschmidt (Stéphane Lesage) * igmp.c, igmp.h, stats.c, stats.h: Improved IGMP stats (patch from bug #28798) 2010-02-08: Simon Goldschmidt (Stéphane Lesage) * igmp.c: Fixed bug #28798 (Error in "Max Response Time" processing) and another bug when LWIP_RAND() returns zero. 2010-02-04: Simon Goldschmidt * nearly every file: Use macros defined in ip_addr.h (some of them new) to work with IP addresses (preparation for bug #27352 - Change ip_addr from struct to typedef (u32_t) - and better code). 2010-01-31: Simon Goldschmidt * netif.c: Don't call the link-callback from netif_set_up/down() since this invalidly retriggers DHCP. 2010-01-29: Simon Goldschmidt * ip_addr.h, inet.h, def.h, inet.c, def.c, more: Cleanly separate the portability file inet.h and its contents from the stack: moved htonX- functions to def.h (and the new def.c - they are not ipv4 dependent), let inet.h depend on ip_addr.h and not the other way round. This fixes bug #28732. 2010-01-28: Kieran Mansley * tcp.c: Ensure ssthresh >= 2*MSS 2010-01-27: Simon Goldschmidt * tcp.h, tcp.c, tcp_in.c: Fixed bug #27871: Calling tcp_abort() in recv callback can lead to accessing unallocated memory. As a consequence, ERR_ABRT means the application has called tcp_abort()! 2010-01-25: Simon Goldschmidt * snmp_structs.h, msg_in.c: Partly fixed bug #22070 (MIB_OBJECT_WRITE_ONLY not implemented in SNMP): write-only or not-accessible are still returned by getnext (though not by get) 2010-01-24: Simon Goldschmidt * snmp: Renamed the private mib node from 'private' to 'mib_private' to not use reserved C/C++ keywords 2010-01-23: Simon Goldschmidt * sockets.c: Fixed bug #28716: select() returns 0 after waiting for less than 1 ms 2010-01-21: Simon Goldschmidt * tcp.c, api_msg.c: Fixed bug #28651 (tcp_connect: no callbacks called if tcp_enqueue fails) both in raw- and netconn-API 2010-01-19: Simon Goldschmidt * api_msg.c: Fixed bug #27316: netconn: Possible deadlock in err_tcp 2010-01-18: Iordan Neshev/Simon Goldschmidt * src/netif/ppp: reorganised PPP sourcecode to 2.3.11 including some bugfix backports from 2.4.x. 2010-01-18: Simon Goldschmidt * mem.c: Fixed bug #28679: mem_realloc calculates mem_stats wrong 2010-01-17: Simon Goldschmidt * api_lib.c, api_msg.c, (api_msg.h, api.h, sockets.c, tcpip.c): task #10102: "netconn: clean up conn->err threading issues" by adding error return value to struct api_msg_msg 2010-01-17: Simon Goldschmidt * api.h, api_lib.c, sockets.c: Changed netconn_recv() and netconn_accept() to return err_t (bugs #27709 and #28087) 2010-01-14: Simon Goldschmidt * ...: Use typedef for function prototypes throughout the stack. 2010-01-13: Simon Goldschmidt * api_msg.h/.c, api_lib.c: Fixed bug #26672 (close connection when receive window = 0) by correctly draining recvmbox/acceptmbox 2010-01-11: Simon Goldschmidt * pap.c: Fixed bug #13315 (PPP PAP authentication can result in erroneous callbacks) by copying the code from recent pppd 2010-01-10: Simon Goldschmidt * raw.c: Fixed bug #28506 (raw_bind should filter received packets) 2010-01-10: Simon Goldschmidt * tcp.h/.c: bug #28127 (remove call to tcp_output() from tcp_ack(_now)()) 2010-01-08: Simon Goldschmidt * sockets.c: Fixed bug #28519 (lwip_recvfrom bug with len > 65535) 2010-01-08: Simon Goldschmidt * dns.c: Copy hostname for DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1 since string passed to dns_local_addhost() might be volatile 2010-01-07: Simon Goldschmidt * timers.c, tcp.h: Call tcp_timer_needed() with NO_SYS==1, too 2010-01-06: Simon Goldschmidt * netdb.h: Fixed bug #28496: missing include guards in netdb.h 2009-12-31: Simon Goldschmidt * many ppp files: Reorganised PPP source code from ucip structure to pppd structure to easily compare our code against the pppd code (around v2.3.1) 2009-12-27: Simon Goldschmidt * tcp_in.c: Another fix for bug #28241 (ooseq processing) and adapted unit test (STABLE-1.3.2) ++ New features: 2009-10-27 Simon Goldschmidt/Stephan Lesage * netifapi.c/.h: Added netifapi_netif_set_addr() 2009-10-07 Simon Goldschmidt/Fabian Koch * api_msg.c, netbuf.c/.h, opt.h: patch #6888: Patch for UDP Netbufs to support dest-addr and dest-port (optional: LWIP_NETBUF_RECVINFO) 2009-08-26 Simon Goldschmidt/Simon Kallweit * slipif.c/.h: bug #26397: SLIP polling support 2009-08-25 Simon Goldschmidt * opt.h, etharp.h/.c: task #9033: Support IEEE 802.1q tagged frame (VLAN), New configuration options ETHARP_SUPPORT_VLAN and ETHARP_VLAN_CHECK. 2009-08-25 Simon Goldschmidt * ip_addr.h, netdb.c: patch #6900: added define ip_ntoa(struct ip_addr*) 2009-08-24 Jakob Stoklund Olesen * autoip.c, dhcp.c, netif.c: patch #6725: Teach AutoIP and DHCP to respond to netif_set_link_up(). 2009-08-23 Simon Goldschmidt * tcp.h/.c: Added function tcp_debug_state_str() to convert a tcp state to a human-readable string. ++ Bugfixes: 2009-12-24: Kieran Mansley * tcp_in.c Apply patches from Oleg Tyshev to improve OOS processing (BUG#28241) 2009-12-06: Simon Goldschmidt * ppp.h/.c: Fixed bug #27079 (Yet another leak in PPP): outpacket_buf can be statically allocated (like in ucip) 2009-12-04: Simon Goldschmidt (patch by Ioardan Neshev) * pap.c: patch #6969: PPP: missing PAP authentication UNTIMEOUT 2009-12-03: Simon Goldschmidt * tcp.h, tcp_in.c, tcp_out.c: Fixed bug #28106: dup ack for fast retransmit could have non-zero length 2009-12-02: Simon Goldschmidt * tcp_in.c: Fixed bug #27904: TCP sends too many ACKs: delay resetting tcp_input_pcb until after calling the pcb's callbacks 2009-11-29: Simon Goldschmidt * tcp_in.c: Fixed bug #28054: Two segments with FIN flag on the out-of- sequence queue, also fixed PBUF_POOL leak in the out-of-sequence code 2009-11-29: Simon Goldschmidt * pbuf.c: Fixed bug #28064: pbuf_alloc(PBUF_POOL) is not thread-safe by queueing a call into tcpip_thread to free ooseq-bufs if the pool is empty 2009-11-26: Simon Goldschmidt * tcp.h: Fixed bug #28098: Nagle can prevent fast retransmit from sending segment 2009-11-26: Simon Goldschmidt * tcp.h, sockets.c: Fixed bug #28099: API required to disable Nagle algorithm at PCB level 2009-11-22: Simon Goldschmidt * tcp_out.c: Fixed bug #27905: FIN isn't combined with data on unsent 2009-11-22: Simon Goldschmidt (suggested by Bill Auerbach) * tcp.c: tcp_alloc: prevent increasing stats.err for MEMP_TCP_PCB when reusing time-wait pcb 2009-11-20: Simon Goldschmidt (patch by Albert Bartel) * sockets.c: Fixed bug #28062: Data received directly after accepting does not wake up select 2009-11-11: Simon Goldschmidt * netdb.h: Fixed bug #27994: incorrect define for freeaddrinfo(addrinfo) 2009-10-30: Simon Goldschmidt * opt.h: Increased default value for TCP_MSS to 536, updated default value for TCP_WND to 4*TCP_MSS to keep delayed ACK working. 2009-10-28: Kieran Mansley * tcp_in.c, tcp_out.c, tcp.h: re-work the fast retransmission code to follow algorithm from TCP/IP Illustrated 2009-10-27: Kieran Mansley * tcp_in.c: fix BUG#27445: grow cwnd with every duplicate ACK 2009-10-25: Simon Goldschmidt * tcp.h: bug-fix in the TCP_EVENT_RECV macro (has to call tcp_recved if pcb->recv is NULL to keep rcv_wnd correct) 2009-10-25: Simon Goldschmidt * tcp_in.c: Fixed bug #26251: RST process in TIME_WAIT TCP state 2009-10-23: Simon Goldschmidt (David Empson) * tcp.c: Fixed bug #27783: Silly window avoidance for small window sizes 2009-10-21: Simon Goldschmidt * tcp_in.c: Fixed bug #27215: TCP sent() callback gives leading and trailing 1 byte len (SYN/FIN) 2009-10-21: Simon Goldschmidt * tcp_out.c: Fixed bug #27315: zero window probe and FIN 2009-10-19: Simon Goldschmidt * dhcp.c/.h: Minor code simplification (don't store received pbuf, change conditional code to assert where applicable), check pbuf length before testing for valid reply 2009-10-19: Simon Goldschmidt * dhcp.c: Removed most calls to udp_connect since they aren't necessary when using udp_sendto_if() - always stay connected to IP_ADDR_ANY. 2009-10-16: Simon Goldschmidt * ip.c: Fixed bug #27390: Source IP check in ip_input() causes it to drop valid DHCP packets -> allow 0.0.0.0 as source address when LWIP_DHCP is enabled 2009-10-15: Simon Goldschmidt (Oleg Tyshev) * tcp_in.c: Fixed bug #27329: dupacks by unidirectional data transmit 2009-10-15: Simon Goldschmidt * api_lib.c: Fixed bug #27709: conn->err race condition on netconn_recv() timeout 2009-10-15: Simon Goldschmidt * autoip.c: Fixed bug #27704: autoip starts with wrong address LWIP_AUTOIP_CREATE_SEED_ADDR() returned address in host byte order instead of network byte order 2009-10-11 Simon Goldschmidt (Jörg Kesten) * tcp_out.c: Fixed bug #27504: tcp_enqueue wrongly concatenates segments which are not consecutive when retransmitting unacked segments 2009-10-09 Simon Goldschmidt * opt.h: Fixed default values of some stats to only be enabled if used Fixes bug #27338: sys_stats is defined when NO_SYS = 1 2009-08-30 Simon Goldschmidt * ip.c: Fixed bug bug #27345: "ip_frag() does not use the LWIP_NETIF_LOOPBACK function" by checking for loopback before calling ip_frag 2009-08-25 Simon Goldschmidt * dhcp.c: fixed invalid dependency to etharp_query if DHCP_DOES_ARP_CHECK==0 2009-08-23 Simon Goldschmidt * ppp.c: bug #27078: Possible memory leak in pppInit() 2009-08-23 Simon Goldschmidt * netdb.c, dns.c: bug #26657: DNS, if host name is "localhost", result is error. 2009-08-23 Simon Goldschmidt * opt.h, init.c: bug #26649: TCP fails when TCP_MSS > TCP_SND_BUF Fixed wrong parenthesis, added check in init.c 2009-08-23 Simon Goldschmidt * ppp.c: bug #27266: wait-state debug message in pppMain occurs every ms 2009-08-23 Simon Goldschmidt * many ppp files: bug #27267: Added include to string.h where needed 2009-08-23 Simon Goldschmidt * tcp.h: patch #6843: tcp.h macro optimization patch (for little endian) (STABLE-1.3.1) ++ New features: 2009-05-10 Simon Goldschmidt * opt.h, sockets.c, pbuf.c, netbuf.h, pbuf.h: task #7013: Added option LWIP_NETIF_TX_SINGLE_PBUF to try to create transmit packets from only one pbuf to help MACs that don't support scatter-gather DMA. 2009-05-09 Simon Goldschmidt * icmp.h, icmp.c: Shrinked ICMP code, added option to NOT check icoming ECHO pbuf for size (just use it): LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN 2009-05-05 Simon Goldschmidt, Jakob Stoklund Olesen * ip.h, ip.c: Added ip_current_netif() & ip_current_header() to receive extended info about the currently received packet. 2009-04-27 Simon Goldschmidt * sys.h: Made SYS_LIGHTWEIGHT_PROT and sys_now() work with NO_SYS=1 2009-04-25 Simon Goldschmidt * mem.c, opt.h: Added option MEM_USE_POOLS_TRY_BIGGER_POOL to try the next bigger malloc pool if one is empty (only usable with MEM_USE_POOLS). 2009-04-21 Simon Goldschmidt * dns.c, init.c, dns.h, opt.h: task #7507, patch #6786: DNS supports static hosts table. New configuration options DNS_LOCAL_HOSTLIST and DNS_LOCAL_HOSTLIST_IS_DYNAMIC. Also, DNS_LOOKUP_LOCAL_EXTERN() can be defined as an external function for lookup. 2009-04-15 Simon Goldschmidt * dhcp.c: patch #6763: Global DHCP XID can be redefined to something more unique 2009-03-31 Kieran Mansley * tcp.c, tcp_out.c, tcp_in.c, sys.h, tcp.h, opts.h: add support for TCP timestamp options, off by default. Rework tcp_enqueue() to take option flags rather than specified option data 2009-02-18 Simon Goldschmidt * cc.h: Added printf formatter for size_t: SZT_F 2009-02-16 Simon Goldschmidt (patch by Rishi Khan) * icmp.c, opt.h: patch #6539: (configurable) response to broadcast- and multicast pings 2009-02-12 Simon Goldschmidt * init.h: Added LWIP_VERSION to get the current version of the stack 2009-02-11 Simon Goldschmidt (suggested by Gottfried Spitaler) * opt.h, memp.h/.c: added MEMP_MEM_MALLOC to use mem_malloc/mem_free instead of the pool allocator (can save code size with MEM_LIBC_MALLOC if libc-malloc is otherwise used) 2009-01-28 Jonathan Larmour (suggested by Bill Bauerbach) * ipv4/inet_chksum.c, ipv4/lwip/inet_chksum.h: inet_chksum_pseudo_partial() is only used by UDPLITE at present, so conditionalise it. 2008-12-03 Simon Goldschmidt (base on patch from Luca Ceresoli) * autoip.c: checked in (slightly modified) patch #6683: Customizable AUTOIP "seed" address. This should reduce AUTOIP conflicts if LWIP_AUTOIP_CREATE_SEED_ADDR is overridden. 2008-10-02 Jonathan Larmour and Rishi Khan * sockets.c (lwip_accept): Return EWOULDBLOCK if would block on non-blocking socket. 2008-06-30 Simon Goldschmidt * mem.c, opt.h, stats.h: fixed bug #21433: Calling mem_free/pbuf_free from interrupt context isn't safe: LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT allows mem_free to run between mem_malloc iterations. Added illegal counter for mem stats. 2008-06-27 Simon Goldschmidt * stats.h/.c, some other files: patch #6483: stats module improvement: Added defines to display each module's statistic individually, added stats defines for MEM, MEMP and SYS modules, removed (unused) rexmit counter. 2008-06-17 Simon Goldschmidt * err.h: patch #6459: Made err_t overridable to use a more efficient type (define LWIP_ERR_T in cc.h) 2008-06-17 Simon Goldschmidt * slipif.c: patch #6480: Added a configuration option for slipif for symmetry to loopif 2008-06-17 Simon Goldschmidt (patch by Luca Ceresoli) * netif.c, loopif.c, ip.c, netif.h, loopif.h, opt.h: Checked in slightly modified version of patch # 6370: Moved loopif code to netif.c so that loopback traffic is supported on all netifs (all local IPs). Added option to limit loopback packets for each netifs. ++ Bugfixes: 2009-08-12 Kieran Mansley * tcp_in.c, tcp.c: Fix bug #27209: handle trimming of segments when out of window or out of order properly 2009-08-12 Kieran Mansley * tcp_in.c: Fix bug #27199: use snd_wl2 instead of snd_wl1 2009-07-28 Simon Goldschmidt * mem.h: Fixed bug #27105: "realloc() cannot replace mem_realloc()"s 2009-07-27 Kieran Mansley * api.h api_msg.h netdb.h sockets.h: add missing #include directives 2009-07-09 Kieran Mansley * api_msg.c, sockets.c, api.h: BUG23240 use signed counters for recv_avail and don't increment counters until message successfully sent to mbox 2009-06-25 Kieran Mansley * api_msg.c api.h: BUG26722: initialise netconn write variables in netconn_alloc 2009-06-25 Kieran Mansley * tcp.h: BUG26879: set ret value in TCP_EVENT macros when function is not set 2009-06-25 Kieran Mansley * tcp.c, tcp_in.c, tcp_out.c, tcp.h: BUG26301 and BUG26267: correct simultaneous close behaviour, and make snd_nxt have the same meaning as in the RFCs. 2009-05-12 Simon Goldschmidt * etharp.h, etharp.c, netif.c: fixed bug #26507: "Gratuitous ARP depends on arp_table / uses etharp_query" by adding etharp_gratuitous() 2009-05-12 Simon Goldschmidt * ip.h, ip.c, igmp.c: bug #26487: Added ip_output_if_opt that can add IP options to the IP header (used by igmp_ip_output_if) 2009-05-06 Simon Goldschmidt * inet_chksum.c: On little endian architectures, use LWIP_PLATFORM_HTONS (if defined) for SWAP_BYTES_IN_WORD to speed up checksumming. 2009-05-05 Simon Goldschmidt * sockets.c: bug #26405: Prematurely released semaphore causes lwip_select() to crash 2009-05-04 Simon Goldschmidt * init.c: snmp was not initialized in lwip_init() 2009-05-04 Frédéric Bernon * dhcp.c, netbios.c: Changes if IP_SOF_BROADCAST is enabled. 2009-05-03 Simon Goldschmidt * tcp.h: bug #26349: Nagle algorithm doesn't send although segment is full (and unsent->next == NULL) 2009-05-02 Simon Goldschmidt * tcpip.h, tcpip.c: fixed tcpip_untimeout (does not need the time, broken after 1.3.0 in CVS only) - fixes compilation of ppp_oe.c 2009-05-02 Simon Goldschmidt * msg_in.c: fixed bug #25636: SNMPSET value is ignored for integer fields 2009-05-01 Simon Goldschmidt * pap.c: bug #21680: PPP upap_rauthnak() drops legal NAK packets 2009-05-01 Simon Goldschmidt * ppp.c: bug #24228: Memory corruption with PPP and DHCP 2009-04-29 Frédéric Bernon * raw.c, udp.c, init.c, opt.h, ip.h, sockets.h: bug #26309: Implement the SO(F)_BROADCAST filter for all API layers. Avoid the unindented reception of broadcast packets even when this option wasn't set. Port maintainers which want to enable this filter have to set IP_SOF_BROADCAST=1 in opt.h. If you want this option also filter broadcast on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1 in opt.h. 2009-04-28 Simon Goldschmidt, Jakob Stoklund Olesen * dhcp.c: patch #6721, bugs #25575, #25576: Some small fixes to DHCP and DHCP/AUTOIP cooperation 2009-04-25 Simon Goldschmidt, Oleg Tyshev * tcp_out.c: bug #24212: Deadlocked tcp_retransmit due to exceeded pcb->cwnd Fixed by sorting the unsent and unacked queues (segments are inserted at the right place in tcp_output and tcp_rexmit). 2009-04-25 Simon Goldschmidt * memp.c, mem.c, memp.h, mem_std.h: bug #26213 "Problem with memory allocation when debugging": memp_sizes contained the wrong sizes (including sanity regions); memp pools for MEM_USE_POOLS were too small 2009-04-24 Simon Goldschmidt, Frédéric Bernon * inet.c: patch #6765: Fix a small problem with the last changes (incorrect behavior, with with ip address string not ended by a '\0', a space or a end of line) 2009-04-19 Simon Goldschmidt * rawapi.txt: Fixed bug #26069: Corrected documentation: if tcp_connect fails, pcb->err is called, not pcb->connected (with an error code). 2009-04-19 Simon Goldschmidt * tcp_out.c: Fixed bug #26236: "TCP options (timestamp) don't work with no-copy-tcpwrite": deallocate option data, only concat segments with same flags 2009-04-19 Simon Goldschmidt * tcp_out.c: Fixed bug #25094: "Zero-length pbuf" (options are now allocated in the header pbuf, not the data pbuf) 2009-04-18 Simon Goldschmidt * api_msg.c: fixed bug #25695: Segmentation fault in do_writemore() 2009-04-15 Simon Goldschmidt * sockets.c: tried to fix bug #23559: lwip_recvfrom problem with tcp 2009-04-15 Simon Goldschmidt * dhcp.c: task #9192: mem_free of dhcp->options_in and dhcp->msg_in 2009-04-15 Simon Goldschmidt * ip.c, ip6.c, tcp_out.c, ip.h: patch #6808: Add a utility function ip_hinted_output() (for smaller code mainly) 2009-04-15 Simon Goldschmidt * inet.c: patch #6765: Supporting new line characters in inet_aton() 2009-04-15 Simon Goldschmidt * dhcp.c: patch #6764: DHCP rebind and renew did not send hostnam option; Converted constant OPTION_MAX_MSG_SIZE to netif->mtu, check if netif->mtu is big enough in dhcp_start 2009-04-15 Simon Goldschmidt * netbuf.c: bug #26027: netbuf_chain resulted in pbuf memory leak 2009-04-15 Simon Goldschmidt * sockets.c, ppp.c: bug #25763: corrected 4 occurrences of SMEMCPY to MEMCPY 2009-04-15 Simon Goldschmidt * sockets.c: bug #26121: set_errno can be overridden 2009-04-09 Kieran Mansley (patch from Luca Ceresoli ) * init.c, opt.h: Patch#6774 TCP_QUEUE_OOSEQ breaks compilation when LWIP_TCP==0 2009-04-09 Kieran Mansley (patch from Roy Lee ) * tcp.h: Patch#6802 Add do-while-clauses to those function like macros in tcp.h 2009-03-31 Kieran Mansley * tcp.c, tcp_in.c, tcp_out.c, tcp.h, opt.h: Rework the way window updates are calculated and sent (BUG20515) * tcp_in.c: cope with SYN packets received during established states, and retransmission of initial SYN. * tcp_out.c: set push bit correctly when tcp segments are merged 2009-03-27 Kieran Mansley * tcp_out.c set window correctly on probes (correcting change made yesterday) 2009-03-26 Kieran Mansley * tcp.c, tcp_in.c, tcp.h: add tcp_abandon() to cope with dropping connections where no reset required (bug #25622) * tcp_out.c: set TCP_ACK flag on keepalive and zero window probes (bug #20779) 2009-02-18 Simon Goldschmidt (Jonathan Larmour and Bill Auerbach) * ip_frag.c: patch #6528: the buffer used for IP_FRAG_USES_STATIC_BUF could be too small depending on MEM_ALIGNMENT 2009-02-16 Simon Goldschmidt * sockets.h/.c, api_*.h/.c: fixed arguments of socket functions to match the standard; converted size argument of netconn_write to 'size_t' 2009-02-16 Simon Goldschmidt * tcp.h, tcp.c: fixed bug #24440: TCP connection close problem on 64-bit host by moving accept callback function pointer to TCP_PCB_COMMON 2009-02-12 Simon Goldschmidt * dhcp.c: fixed bug #25345 (DHCPDECLINE is sent with "Maximum message size" option) 2009-02-11 Simon Goldschmidt * dhcp.c: fixed bug #24480 (releasing old udp_pdb and pbuf in dhcp_start) 2009-02-11 Simon Goldschmidt * opt.h, api_msg.c: added configurable default valud for netconn->recv_bufsize: RECV_BUFSIZE_DEFAULT (fixes bug #23726: pbuf pool exhaustion on slow recv()) 2009-02-10 Simon Goldschmidt * tcp.c: fixed bug #25467: Listen backlog is not reset on timeout in SYN_RCVD: Accepts_pending is decrease on a corresponding listen pcb when a connection in state SYN_RCVD is close. 2009-01-28 Jonathan Larmour * pbuf.c: reclaim pbufs from TCP out-of-sequence segments if we run out of pool pbufs. 2008-12-19 Simon Goldschmidt * many files: patch #6699: fixed some warnings on platform where sizeof(int) == 2 2008-12-10 Tamas Somogyi, Frédéric Bernon * sockets.c: fixed bug #25051: lwip_recvfrom problem with udp: fromaddr and port uses deleted netbuf. 2008-10-18 Simon Goldschmidt * tcp_in.c: fixed bug ##24596: Vulnerability on faulty TCP options length in tcp_parseopt 2008-10-15 Simon Goldschmidt * ip_frag.c: fixed bug #24517: IP reassembly crashes on unaligned IP headers by packing the struct ip_reass_helper. 2008-10-03 David Woodhouse, Jonathan Larmour * etharp.c (etharp_arp_input): Fix type aliasing problem copying ip address. 2008-10-02 Jonathan Larmour * dns.c: Hard-code structure sizes, to avoid issues on some compilers where padding is included. 2008-09-30 Jonathan Larmour * sockets.c (lwip_accept): check addr isn't NULL. If it's valid, do an assertion check that addrlen isn't NULL. 2008-09-30 Jonathan Larmour * tcp.c: Fix bug #24227, wrong error message in tcp_bind. 2008-08-26 Simon Goldschmidt * inet.h, ip_addr.h: fixed bug #24132: Cross-dependency between ip_addr.h and inet.h -> moved declaration of struct in_addr from ip_addr.h to inet.h 2008-08-14 Simon Goldschmidt * api_msg.c: fixed bug #23847: do_close_internal references freed memory (when tcp_close returns != ERR_OK) 2008-07-08 Frédéric Bernon * stats.h: Fix some build bugs introduced with patch #6483 (missing some parameters in macros, mainly if MEM_STATS=0 and MEMP_STATS=0). 2008-06-24 Jonathan Larmour * tcp_in.c: Fix for bug #23693 as suggested by Art R. Ensure cseg is unused if tcp_seg_copy fails. 2008-06-17 Simon Goldschmidt * inet_chksum.c: Checked in some ideas of patch #6460 (loop optimizations) and created defines for swapping bytes and folding u32 to u16. 2008-05-30 Kieran Mansley * tcp_in.c Remove redundant "if" statement, and use real rcv_wnd rather than rcv_ann_wnd when deciding if packets are in-window. Contributed by 2008-05-30 Kieran Mansley * mem.h: Fix BUG#23254. Change macro definition of mem_* to allow passing as function pointers when MEM_LIBC_MALLOC is defined. 2008-05-09 Jonathan Larmour * err.h, err.c, sockets.c: Fix bug #23119: Reorder timeout error code to stop it being treated as a fatal error. 2008-04-15 Simon Goldschmidt * dhcp.c: fixed bug #22804: dhcp_stop doesn't clear NETIF_FLAG_DHCP (flag now cleared) 2008-03-27 Simon Goldschmidt * mem.c, tcpip.c, tcpip.h, opt.h: fixed bug #21433 (Calling mem_free/pbuf_free from interrupt context isn't safe): set LWIP_USE_HEAP_FROM_INTERRUPT to 1 in lwipopts.h or use pbuf_free_callback(p)/mem_free_callback(m) to free pbufs or heap memory from interrupt context 2008-03-26 Simon Goldschmidt * tcp_in.c, tcp.c: fixed bug #22249: division by zero could occur if a remote host sent a zero mss as TCP option. (STABLE-1.3.0) ++ New features: 2008-03-10 Jonathan Larmour * inet_chksum.c: Allow choice of one of the sample algorithms to be made from lwipopts.h. Fix comment on how to override LWIP_CHKSUM. 2008-01-22 Frédéric Bernon * tcp.c, tcp_in.c, tcp.h, opt.h: Rename LWIP_CALCULATE_EFF_SEND_MSS in TCP_CALCULATE_EFF_SEND_MSS to have coherent TCP options names. 2008-01-14 Frédéric Bernon * rawapi.txt, api_msg.c, tcp.c, tcp_in.c, tcp.h: changes for task #7675 "Enable to refuse data on a TCP_EVENT_RECV call". Important, behavior changes for the tcp_recv callback (see rawapi.txt). 2008-01-14 Frédéric Bernon, Marc Chaland * ip.c: Integrate patch #6369" ip_input : checking before realloc". 2008-01-12 Frédéric Bernon * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field netconn::sem per netconn::op_completed like suggested for the task #7490 "Add return value to sys_mbox_post". 2008-01-12 Frédéric Bernon * api_msg.c, opt.h: replace DEFAULT_RECVMBOX_SIZE per DEFAULT_TCP_RECVMBOX_SIZE, DEFAULT_UDP_RECVMBOX_SIZE and DEFAULT_RAW_RECVMBOX_SIZE (to optimize queues sizes), like suggested for the task #7490 "Add return value to sys_mbox_post". 2008-01-10 Frédéric Bernon * tcpip.h, tcpip.c: add tcpip_callback_with_block function for the task #7490 "Add return value to sys_mbox_post". tcpip_callback is always defined as "blocking" ("block" parameter = 1). 2008-01-10 Frédéric Bernon * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field netconn::mbox (sys_mbox_t) per netconn::sem (sys_sem_t) for the task #7490 "Add return value to sys_mbox_post". 2008-01-05 Frédéric Bernon * sys_arch.txt, api.h, api_lib.c, api_msg.h, api_msg.c, tcpip.c, sys.h, opt.h: Introduce changes for task #7490 "Add return value to sys_mbox_post" with some modifications in the sys_mbox api: sys_mbox_new take a "size" parameters which indicate the number of pointers query by the mailbox. There is three defines in opt.h to indicate sizes for tcpip::mbox, netconn::recvmbox, and for the netconn::acceptmbox. Port maintainers, you can decide to just add this new parameter in your implementation, but to ignore it to keep the previous behavior. The new sys_mbox_trypost function return a value to know if the mailbox is full or if the message is posted. Take a look to sys_arch.txt for more details. This new function is used in tcpip_input (so, can be called in an interrupt context since the function is not blocking), and in recv_udp and recv_raw. 2008-01-04 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour * rawapi.txt, api.h, api_lib.c, api_msg.h, api_msg.c, sockets.c, tcp.h, tcp.c, tcp_in.c, init.c, opt.h: rename backlog options with TCP_ prefix, limit the "backlog" parameter in an u8_t, 0 is interpreted as "smallest queue", add documentation in the rawapi.txt file. 2007-12-31 Kieran Mansley (based on patch from Per-Henrik Lundbolm) * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Add TCP persist timer 2007-12-31 Frédéric Bernon, Luca Ceresoli * autoip.c, etharp.c: ip_addr.h: Integrate patch #6348: "Broadcast ARP packets in autoip". The change in etharp_raw could be removed, since all calls to etharp_raw use ethbroadcast for the "ethdst_addr" parameter. But it could be wrong in the future. 2007-12-30 Frédéric Bernon, Tom Evans * ip.c: Fix bug #21846 "LwIP doesn't appear to perform any IP Source Address Filtering" reported by Tom Evans. 2007-12-21 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour * tcp.h, opt.h, api.h, api_msg.h, tcp.c, tcp_in.c, api_lib.c, api_msg.c, sockets.c, init.c: task #7252: Implement TCP listen backlog: Warning: raw API applications have to call 'tcp_accepted(pcb)' in their accept callback to keep accepting new connections. 2007-12-13 Frédéric Bernon * api_msg.c, err.h, err.c, sockets.c, dns.c, dns.h: replace "enum dns_result" by err_t type. Add a new err_t code "ERR_INPROGRESS". 2007-12-12 Frédéric Bernon * dns.h, dns.c, opt.h: move DNS options to the "right" place. Most visibles are the one which have ram usage. 2007-12-05 Frédéric Bernon * netdb.c: add a LWIP_DNS_API_HOSTENT_STORAGE option to decide to use a static set of variables (=0) or a local one (=1). In this last case, your port should provide a function "struct hostent* sys_thread_hostent( struct hostent* h)" which have to do a copy of "h" and return a pointer ont the "per-thread" copy. 2007-12-03 Simon Goldschmidt * ip.c: ip_input: check if a packet is for inp first before checking all other netifs on netif_list (speeds up packet receiving in most cases) 2007-11-30 Simon Goldschmidt * udp.c, raw.c: task #7497: Sort lists (pcb, netif, ...) for faster access UDP: move a (connected) pcb selected for input to the front of the list of pcbs so that it is found faster next time. Same for RAW pcbs that have eaten a packet. 2007-11-28 Simon Goldschmidt * etharp.c, stats.c, stats.h, opt.h: Introduced ETHARP_STATS 2007-11-25 Simon Goldschmidt * dhcp.c: dhcp_unfold_reply() uses pbuf_copy_partial instead of its own copy algorithm. 2007-11-24 Simon Goldschmidt * netdb.h, netdb.c, sockets.h/.c: Moved lwip_gethostbyname from sockets.c to the new file netdb.c; included lwip_getaddrinfo. 2007-11-21 Simon Goldschmidt * tcp.h, opt.h, tcp.c, tcp_in.c: implemented calculating the effective send-mss based on the MTU of the netif used to send. Enabled by default. Disable by setting LWIP_CALCULATE_EFF_SEND_MSS to 0. This fixes bug #21492. 2007-11-19 Frédéric Bernon * api_msg.c, dns.h, dns.c: Implement DNS_DOES_NAME_CHECK option (check if name received match the name query), implement DNS_USES_STATIC_BUF (the place where copy dns payload to parse the response), return an error if there is no place for a new query, and fix some minor problems. 2007-11-16 Simon Goldschmidt * new files: ipv4/inet.c, ipv4/inet_chksum.c, ipv6/inet6.c removed files: core/inet.c, core/inet6.c Moved inet files into ipv4/ipv6 directory; splitted inet.c/inet.h into inet and chksum part; changed includes in all lwIP files as appropriate 2007-11-16 Simon Goldschmidt * api.h, api_msg.h, api_lib.c, api_msg.c, socket.h, socket.c: Added sequential dns resolver function for netconn api (netconn_gethostbyname) and socket api (gethostbyname/gethostbyname_r). 2007-11-15 Jim Pettinato, Frédéric Bernon * opt.h, init.c, tcpip.c, dhcp.c, dns.h, dns.c: add DNS client for simple name requests with RAW api interface. Initialization is done in lwip_init() with build time options. DNS timer is added in tcpip_thread context. DHCP can set DNS server ip addresses when options are received. You need to set LWIP_DNS=1 in your lwipopts.h file (LWIP_DNS=0 in opt.h). DNS_DEBUG can be set to get some traces with LWIP_DEBUGF. Sanity check have been added. There is a "todo" list with points to improve. 2007-11-06 Simon Goldschmidt * opt.h, mib2.c: Patch #6215: added ifAdminStatus write support (if explicitly enabled by defining SNMP_SAFE_REQUESTS to 0); added code to check link status for ifOperStatus if LWIP_NETIF_LINK_CALLBACK is defined. 2007-11-06 Simon Goldschmidt * api.h, api_msg.h and dependent files: Task #7410: Removed the need to include core header files in api.h (ip/tcp/udp/raw.h) to hide the internal implementation from netconn api applications. 2007-11-03 Frédéric Bernon * api.h, api_lib.c, api_msg.c, sockets.c, opt.h: add SO_RCVBUF option for UDP & RAW netconn. You need to set LWIP_SO_RCVBUF=1 in your lwipopts.h (it's disabled by default). Netconn API users can use the netconn_recv_bufsize macro to access it. This is a first release which have to be improve for TCP. Note it used the netconn::recv_avail which need to be more "thread-safe" (note there is already the problem for FIONREAD with lwip_ioctl/ioctlsocket). 2007-11-01 Frédéric Bernon, Marc Chaland * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, tcp.h, tcp_out.c: Integrate "patch #6250 : MSG_MORE flag for send". MSG_MORE is used at socket api layer, NETCONN_MORE at netconn api layer, and TCP_WRITE_FLAG_MORE at raw api layer. This option enable to delayed TCP PUSH flag on multiple "write" calls. Note that previous "copy" parameter for "write" APIs is now called "apiflags". 2007-10-24 Frédéric Bernon * api.h, api_lib.c, api_msg.c: Add macro API_EVENT in the same spirit than TCP_EVENT_xxx macros to get a code more readable. It could also help to remove some code (like we have talk in "patch #5919 : Create compile switch to remove select code"), but it could be done later. 2007-10-08 Simon Goldschmidt * many files: Changed initialization: many init functions are not needed any more since we now rely on the compiler initializing global and static variables to zero! 2007-10-06 Simon Goldschmidt * ip_frag.c, memp.c, mib2.c, ip_frag.h, memp_std.h, opt.h: Changed IP_REASSEMBLY to enqueue the received pbufs so that multiple packets can be reassembled simultaneously and no static reassembly buffer is needed. 2007-10-05 Simon Goldschmidt * tcpip.c, etharp.h, etharp.c: moved ethernet_input from tcpip.c to etharp.c so all netifs (or ports) can use it. 2007-10-05 Frédéric Bernon * netifapi.h, netifapi.c: add function netifapi_netif_set_default. Change the common function to reduce a little bit the footprint (for all functions using only the "netif" parameter). 2007-10-03 Frédéric Bernon * netifapi.h, netifapi.c: add functions netifapi_netif_set_up, netifapi_netif_set_down, netifapi_autoip_start and netifapi_autoip_stop. Use a common function to reduce a little bit the footprint (for all functions using only the "netif" parameter). 2007-09-15 Frédéric Bernon * udp.h, udp.c, sockets.c: Changes for "#20503 IGMP Improvement". Add IP_MULTICAST_IF option in socket API, and a new field "multicast_ip" in "struct udp_pcb" (for netconn and raw API users), only if LWIP_IGMP=1. Add getsockopt processing for IP_MULTICAST_TTL and IP_MULTICAST_IF. 2007-09-10 Frédéric Bernon * snmp.h, mib2.c: enable to remove SNMP timer (which consumne several cycles even when it's not necessary). snmp_agent.txt tell to call snmp_inc_sysuptime() each 10ms (but, it's intrusive if you use sys_timeout feature). Now, you can decide to call snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but call to a lower frequency). Or, you can decide to not call snmp_inc_sysuptime() or snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro. This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only when it's queried (any direct call to "sysuptime" is changed by a call to snmp_get_sysuptime). 2007-09-09 Frédéric Bernon, Bill Florac * igmp.h, igmp.c, netif.h, netif.c, ip.c: To enable to have interfaces with IGMP, and others without it, there is a new NETIF_FLAG_IGMP flag to set in netif->flags if you want IGMP on an interface. igmp_stop() is now called inside netif_remove(). igmp_report_groups() is now called inside netif_set_link_up() (need to have LWIP_NETIF_LINK_CALLBACK=1) to resend reports once the link is up (avoid to wait the next query message to receive the matching multicast streams). 2007-09-08 Frédéric Bernon * sockets.c, ip.h, api.h, tcp.h: declare a "struct ip_pcb" which only contains IP_PCB. Add in the netconn's "pcb" union a "struct ip_pcb *ip;" (no size change). Use this new field to access to common pcb fields (ttl, tos, so_options, etc...). Enable to access to these fields with LWIP_TCP=0. 2007-09-05 Frédéric Bernon * udp.c, ipv4/icmp.c, ipv4/ip.c, ipv6/icmp.c, ipv6/ip6.c, ipv4/icmp.h, ipv6/icmp.h, opt.h: Integrate "task #7272 : LWIP_ICMP option". The new option LWIP_ICMP enable/disable ICMP module inside the IP stack (enable per default). Be careful, disabling ICMP make your product non-compliant to RFC1122, but help to reduce footprint, and to reduce "visibility" on the Internet. 2007-09-05 Frédéric Bernon, Bill Florac * opt.h, sys.h, tcpip.c, slipif.c, ppp.c, sys_arch.txt: Change parameters list for sys_thread_new (see "task #7252 : Create sys_thread_new_ex()"). Two new parameters have to be provided: a task name, and a task stack size. For this one, since it's platform dependant, you could define the best one for you in your lwipopts.h. For port maintainers, you can just add these new parameters in your sys_arch.c file, and but it's not mandatory, use them in your OS specific functions. 2007-09-05 Frédéric Bernon * inet.c, autoip.c, msg_in.c, msg_out.c, init.c: Move some build time checkings inside init.c for task #7142 "Sanity check user-configurable values". 2007-09-04 Frédéric Bernon, Bill Florac * igmp.h, igmp.c, memp_std.h, memp.c, init.c, opt.h: Replace mem_malloc call by memp_malloc, and use a new MEMP_NUM_IGMP_GROUP option (see opt.h to define the value). It will avoid potential fragmentation problems, use a counter to know how many times a group is used on an netif, and free it when all applications leave it. MEMP_NUM_IGMP_GROUP got 8 as default value (and init.c got a sanity check if LWIP_IGMP!=0). 2007-09-03 Frédéric Bernon * igmp.h, igmp.c, sockets.c, api_msg.c: Changes for "#20503 IGMP Improvement". Initialize igmp_mac_filter to NULL in netif_add (this field should be set in the netif's "init" function). Use the "imr_interface" field (for socket layer) and/or the "interface" field (for netconn layer), for join/leave operations. The igmp_join/leavegroup first parameter change from a netif to an ipaddr. This field could be a netif's ipaddr, or "any" (same meaning than ip_addr_isany). 2007-08-30 Frédéric Bernon * Add netbuf.h, netbuf.c, Change api.h, api_lib.c: #7249 "Split netbuf functions from api/api_lib". Now netbuf API is independant of netconn, and can be used with other API (application based on raw API, or future "socket2" API). Ports maintainers just have to add src/api/netbuf.c in their makefile/projects. 2007-08-30 Frédéric Bernon, Jonathan Larmour * init.c: Add first version of lwip_sanity_check for task #7142 "Sanity check user-configurable values". 2007-08-29 Frédéric Bernon * igmp.h, igmp.c, tcpip.c, init.c, netif.c: change igmp_init and add igmp_start. igmp_start is call inside netif_add. Now, igmp initialization is in the same spirit than the others modules. Modify some IGMP debug traces. 2007-08-29 Frédéric Bernon * Add init.h, init.c, Change opt.h, tcpip.c: Task #7213 "Add a lwip_init function" Add lwip_init function to regroup all modules initializations, and to provide a place to add code for task #7142 "Sanity check user-configurable values". Ports maintainers should remove direct initializations calls from their code, and add init.c in their makefiles. Note that lwip_init() function is called inside tcpip_init, but can also be used by raw api users since all calls are disabled when matching options are disabled. Also note that their is new options in opt.h, you should configure in your lwipopts.h (they are enabled per default). 2007-08-26 Marc Boucher * api_msg.c: do_close_internal(): Reset the callbacks and arg (conn) to NULL since they can under certain circumstances be called with an invalid conn pointer after the connection has been closed (and conn has been freed). 2007-08-25 Frédéric Bernon (Artem Migaev's Patch) * netif.h, netif.c: Integrate "patch #6163 : Function to check if link layer is up". Add a netif_is_link_up() function if LWIP_NETIF_LINK_CALLBACK option is set. 2007-08-22 Frédéric Bernon * netif.h, netif.c, opt.h: Rename LWIP_NETIF_CALLBACK in LWIP_NETIF_STATUS_CALLBACK to be coherent with new LWIP_NETIF_LINK_CALLBACK option before next release. 2007-08-22 Frédéric Bernon * tcpip.h, tcpip.c, ethernetif.c, opt.h: remove options ETHARP_TCPIP_INPUT & ETHARP_TCPIP_ETHINPUT, now, only "ethinput" code is supported, even if the name is tcpip_input (we keep the name of 1.2.0 function). 2007-08-17 Jared Grubb * memp_std.h, memp.h, memp.c, mem.c, stats.c: (Task #7136) Centralize mempool settings into new memp_std.h and optional user file lwippools.h. This adds more dynamic mempools, and allows the user to create an arbitrary number of mempools for mem_malloc. 2007-08-16 Marc Boucher * api_msg.c: Initialize newconn->state to NETCONN_NONE in accept_function; otherwise it was left to NETCONN_CLOSE and sent_tcp() could prematurely close the connection. 2007-08-16 Marc Boucher * sockets.c: lwip_accept(): check netconn_peer() error return. 2007-08-16 Marc Boucher * mem.c, mem.h: Added mem_calloc(). 2007-08-16 Marc Boucher * tcpip.c, tcpip.h memp.c, memp.h: Added distinct memp (MEMP_TCPIP_MSG_INPKT) for input packets to prevent floods from consuming all of MEMP_TCPIP_MSG and starving other message types. Renamed MEMP_TCPIP_MSG to MEMP_TCPIP_MSG_API 2007-08-16 Marc Boucher * pbuf.c, pbuf.h, etharp.c, tcp_in.c, sockets.c: Split pbuf flags in pbuf type and flgs (later renamed to flags). Use enum pbuf_flag as pbuf_type. Renumber PBUF_FLAG_*. Improved lwip_recvfrom(). TCP push now propagated. 2007-08-16 Marc Boucher * ethernetif.c, contrib/ports/various: ethbroadcast now a shared global provided by etharp. 2007-08-16 Marc Boucher * ppp_oe.c ppp_oe.h, auth.c chap.c fsm.c lcp.c ppp.c ppp.h, etharp.c ethernetif.c, etharp.h, opt.h tcpip.h, tcpip.c: Added PPPoE support and various PPP improvements. 2007-07-25 Simon Goldschmidt * api_lib.c, ip_frag.c, pbuf.c, api.h, pbuf.h: Introduced pbuf_copy_partial, making netbuf_copy_partial use this function. 2007-07-25 Simon Goldschmidt * tcp_in.c: Fix bug #20506: Slow start / initial congestion window starts with 2 * mss (instead of 1 * mss previously) to comply with some newer RFCs and other stacks. 2007-07-13 Jared Grubb (integrated by Frédéric Bernon) * opt.h, netif.h, netif.c, ethernetif.c: Add new configuration option to add a link callback in the netif struct, and functions to handle it. Be carefull for port maintainers to add the NETIF_FLAG_LINK_UP flag (like in ethernetif.c) if you want to be sure to be compatible with future changes... 2007-06-30 Frédéric Bernon * sockets.h, sockets.c: Implement MSG_PEEK flag for recv/recvfrom functions. 2007-06-21 Simon Goldschmidt * etharp.h, etharp.c: Combined etharp_request with etharp_raw for both LWIP_AUTOIP =0 and =1 to remove redundant code. 2007-06-21 Simon Goldschmidt * mem.c, memp.c, mem.h, memp.h, opt.h: task #6863: Introduced the option MEM_USE_POOLS to use 4 pools with different sized elements instead of a heap. This both prevents memory fragmentation and gives a higher speed at the cost of more memory consumption. Turned off by default. 2007-06-21 Simon Goldschmidt * api_lib.c, api_msg.c, api.h, api_msg.h: Converted the length argument of netconn_write (and therefore also api_msg_msg.msg.w.len) from u16_t into int to be able to send a bigger buffer than 64K with one time (mainly used from lwip_send). 2007-06-21 Simon Goldschmidt * tcp.h, api_msg.c: Moved the nagle algorithm from netconn_write/do_write into a define (tcp_output_nagle) in tcp.h to provide it to raw api users, too. 2007-06-21 Simon Goldschmidt * api.h, api_lib.c, api_msg.c: Fixed bug #20021: Moved sendbuf-processing in netconn_write from api_lib.c to api_msg.c to also prevent multiple context- changes on low memory or empty send-buffer. 2007-06-18 Simon Goldschmidt * etharp.c, etharp.h: Changed etharp to use a defined hardware address length of 6 to avoid loading netif->hwaddr_len every time (since this file is only used for ethernet and struct eth_addr already had a defined length of 6). 2007-06-17 Simon Goldschmidt * sockets.c, sockets.h: Implemented socket options SO_NO_CHECK for UDP sockets to disable UDP checksum generation on transmit. 2007-06-13 Frédéric Bernon, Simon Goldschmidt * debug.h, api_msg.c: change LWIP_ERROR to use it to check errors like invalid pointers or parameters, and let the possibility to redefined it in cc.h. Use this macro to check "conn" parameter in api_msg.c functions. 2007-06-11 Simon Goldschmidt * sockets.c, sockets.h: Added UDP lite support for sockets 2007-06-10 Simon Goldschmidt * udp.h, opt.h, api_msg.c, ip.c, udp.c: Included switch LWIP_UDPLITE (enabled by default) to switch off UDP-Lite support if not needed (reduces udp.c code size) 2007-06-09 Dominik Spies (integrated by Frédéric Bernon) * autoip.h, autoip.c, dhcp.h, dhcp.c, netif.h, netif.c, etharp.h, etharp.c, opt.h: AutoIP implementation available for IPv4, with new options LWIP_AUTOIP and LWIP_DHCP_AUTOIP_COOP if you want to cooperate with DHCP. Some tips to adapt (see TODO mark in the source code). 2007-06-09 Simon Goldschmidt * etharp.h, etharp.c, ethernetif.c: Modified order of parameters for etharp_output() to match netif->output so etharp_output() can be used directly as netif->output to save one function call. 2007-06-08 Simon Goldschmidt * netif.h, ethernetif.c, slipif.c, loopif.c: Added define NETIF_INIT_SNMP(netif, type, speed) to initialize per-netif snmp variables, added initialization of those to ethernetif, slipif and loopif. 2007-05-18 Simon Goldschmidt * opt.h, ip_frag.c, ip_frag.h, ip.c: Added option IP_FRAG_USES_STATIC_BUF (defaulting to off for now) that can be set to 0 to send fragmented packets by passing PBUF_REFs down the stack. 2007-05-23 Frédéric Bernon * api_lib.c: Implement SO_RCVTIMEO for accept and recv on TCP connections, such present in patch #5959. 2007-05-23 Frédéric Bernon * api.h, api_lib.c, api_msg.c, sockets.c: group the different NETCONN_UDPxxx code in only one part... 2007-05-18 Simon Goldschmidt * opt.h, memp.h, memp.c: Added option MEMP_OVERFLOW_CHECK to check for memp elements to overflow. This is achieved by adding some bytes before and after each pool element (increasing their size, of course), filling them with a prominent value and checking them on freeing the element. Set it to 2 to also check every element in every pool each time memp_malloc() or memp_free() is called (slower but more helpful). 2007-05-10 Simon Goldschmidt * opt.h, memp.h, memp.c, pbuf.c (see task #6831): use a new memp pool for PBUF_POOL pbufs instead of the old pool implementation in pbuf.c to reduce code size. 2007-05-11 Frédéric Bernon * sockets.c, api_lib.c, api_msg.h, api_msg.c, netifapi.h, netifapi.c, tcpip.c: Include a function pointer instead of a table index in the message to reduce footprint. Disable some part of lwip_send and lwip_sendto if some options are not set (LWIP_TCP, LWIP_UDP, LWIP_RAW). 2007-05-10 Simon Goldschmidt * *.h (except netif/ppp/*.h): Included patch #5448: include '#ifdef __cplusplus \ extern "C" {' in all header files. Now you can write your application using the lwIP stack in C++ and simply #include the core files. Note I have left out the netif/ppp/*h header files for now, since I don't know which files are included by applications and which are for internal use only. 2007-05-09 Simon Goldschmidt * opt.h, *.c/*.h: Included patch #5920: Create define to override C-library memcpy. 2 Defines are created: MEMCPY() for normal memcpy, SMEMCPY() for situations where some compilers might inline the copy and save a function call. Also replaced all calls to memcpy() with calls to (S)MEMCPY(). 2007-05-08 Simon Goldschmidt * mem.h: If MEM_LIBC_MALLOC==1, allow the defines (e.g. mem_malloc() -> malloc()) to be overriden in case the C-library malloc implementation is not protected against concurrent access. 2007-05-04 Simon Goldschmidt (Atte Kojo) * etharp.c: Introduced fast one-entry-cache to speed up ARP lookup when sending multiple packets to the same host. 2007-05-04 Frédéric Bernon, Jonathan Larmour * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fix bug #19162 "lwip_sento: a possible to corrupt remote addr/port connection state". Reduce problems "not enought memory" with netbuf (if we receive lot of datagrams). Improve lwip_sendto (only one exchange between sockets api and api_msg which run in tcpip_thread context). Add netconn_sento function. Warning, if you directly access to "fromaddr" & "fromport" field from netbuf struct, these fields are now renamed "addr" & "port". 2007-04-11 Jonathan Larmour * sys.h, api_lib.c: Provide new sys_mbox_tryfetch function. Require ports to provide new sys_arch_mbox_tryfetch function to get a message if one is there, otherwise return with SYS_MBOX_EMPTY. sys_arch_mbox_tryfetch can be implemented as a function-like macro by the port in sys_arch.h if desired. 2007-04-06 Frédéric Bernon, Simon Goldschmidt * opt.h, tcpip.h, tcpip.c, netifapi.h, netifapi.c: New configuration option LWIP_NETIF_API allow to use thread-safe functions to add/remove netif in list, and to start/stop dhcp clients, using new functions from netifapi.h. Disable as default (no port change to do). 2007-04-05 Frédéric Bernon * sockets.c: remplace ENOBUFS errors on alloc_socket by ENFILE to be more BSD compliant. 2007-04-04 Simon Goldschmidt * arch.h, api_msg.c, dhcp.c, msg_in.c, sockets.c: Introduced #define LWIP_UNUSED_ARG(x) use this for and architecture-independent form to tell the compiler you intentionally are not using this variable. Can be overriden in cc.h. 2007-03-28 Frédéric Bernon * opt.h, netif.h, dhcp.h, dhcp.c: New configuration option LWIP_NETIF_HOSTNAME allow to define a hostname in netif struct (this is just a pointer, so, you can use a hardcoded string, point on one of your's ethernetif field, or alloc a string you will free yourself). It will be used by DHCP to register a client hostname, but can also be use when you call snmp_set_sysname. 2007-03-28 Frédéric Bernon * netif.h, netif.c: A new NETIF_FLAG_ETHARP flag is defined in netif.h, to allow to initialize a network interface's flag with. It tell this interface is an ethernet device, and we can use ARP with it to do a "gratuitous ARP" (RFC 3220 "IP Mobility Support for IPv4" section 4.6) when interface is "up" with netif_set_up(). 2007-03-26 Frédéric Bernon, Jonathan Larmour * opt.h, tcpip.c: New configuration option LWIP_ARP allow to disable ARP init at build time if you only use PPP or SLIP. The default is enable. Note we don't have to call etharp_init in your port's initilization sequence if you use tcpip.c, because this call is done in tcpip_init function. 2007-03-22 Frédéric Bernon * stats.h, stats.c, msg_in.c: Stats counters can be change to u32_t if necessary with the new option LWIP_STATS_LARGE. If you need this option, define LWIP_STATS_LARGE to 1 in your lwipopts.h. More, unused counters are not defined in the stats structs, and not display by stats_display(). Note that some options (SYS_STATS and RAW_STATS) are defined but never used. Fix msg_in.c with the correct #if test for a stat display. 2007-03-21 Kieran Mansley * netif.c, netif.h: Apply patch#4197 with some changes (originator: rireland@hmgsl.com). Provides callback on netif up/down state change. 2007-03-11 Frédéric Bernon, Mace Gael, Steve Reynolds * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, igmp.h, igmp.c, ip.c, netif.h, tcpip.c, opt.h: New configuration option LWIP_IGMP to enable IGMP processing. Based on only one filter per all network interfaces. Declare a new function in netif to enable to control the MAC filter (to reduce lwIP traffic processing). 2007-03-11 Frédéric Bernon * tcp.h, tcp.c, sockets.c, tcp_out.c, tcp_in.c, opt.h: Keepalive values can be configured at run time with LWIP_TCP_KEEPALIVE, but don't change this unless you know what you're doing (default are RFC1122 compliant). Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set in seconds. 2007-03-08 Frédéric Bernon * tcp.h: Keepalive values can be configured at compile time, but don't change this unless you know what you're doing (default are RFC1122 compliant). 2007-03-08 Frédéric Bernon * sockets.c, api.h, api_lib.c, tcpip.c, sys.h, sys.c, err.c, opt.h: Implement LWIP_SO_RCVTIMEO configuration option to enable/disable SO_RCVTIMEO on UDP sockets/netconn. 2007-03-08 Simon Goldschmidt * snmp_msg.h, msg_in.c: SNMP UDP ports can be configured at compile time. 2007-03-06 Frédéric Bernon * api.h, api_lib.c, sockets.h, sockets.c, tcpip.c, sys.h, sys.c, err.h: Implement SO_RCVTIMEO on UDP sockets/netconn. 2007-02-28 Kieran Mansley (based on patch from Simon Goldschmidt) * api_lib.c, tcpip.c, memp.c, memp.h: make API msg structs allocated on the stack and remove the API msg type from memp 2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt) * sockets.h, sockets.c: Move socket initialization to new lwip_socket_init() function. NOTE: this changes the API with ports. Ports will have to be updated to call lwip_socket_init() now. 2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt) * api_lib.c: Use memcpy in netbuf_copy_partial. ++ Bug fixes: 2008-03-17 Frédéric Bernon, Ed Kerekes * igmp.h, igmp.c: Fix bug #22613 "IGMP iphdr problem" (could have some problems to fill the IP header on some targets, use now the ip.h macros to do it). 2008-03-13 Frédéric Bernon * sockets.c: Fix bug #22435 "lwip_recvfrom with TCP break;". Using (lwip_)recvfrom with valid "from" and "fromlen" parameters, on a TCP connection caused a crash. Note that using (lwip_)recvfrom like this is a bit slow and that using (lwip)getpeername is the good lwip way to do it (so, using recv is faster on tcp sockets). 2008-03-12 Frédéric Bernon, Jonathan Larmour * api_msg.c, contrib/apps/ping.c: Fix bug #22530 "api_msg.c's recv_raw() does not consume data", and the ping sample (with LWIP_SOCKET=1, the code did the wrong supposition that lwip_recvfrom returned the IP payload, without the IP header). 2008-03-04 Jonathan Larmour * mem.c, stats.c, mem.h: apply patch #6414 to avoid compiler errors and/or warnings on some systems where mem_size_t and size_t differ. * pbuf.c, ppp.c: Fix warnings on some systems with mem_malloc. 2008-03-04 Kieran Mansley (contributions by others) * Numerous small compiler error/warning fixes from contributions to mailing list after 1.3.0 release candidate made. 2008-01-25 Cui hengbin (integrated by Frédéric Bernon) * dns.c: Fix bug #22108 "DNS problem" caused by unaligned structures. 2008-01-15 Kieran Mansley * tcp_out.c: BUG20511. Modify persist timer to start when we are prevented from sending by a small send window, not just a zero send window. 2008-01-09 Jonathan Larmour * opt.h, ip.c: Rename IP_OPTIONS define to IP_OPTIONS_ALLOWED to avoid conflict with Linux system headers. 2008-01-06 Jonathan Larmour * dhcp.c: fix bug #19927: "DHCP NACK problem" by clearing any existing set IP address entirely on receiving a DHCPNAK, and restarting discovery. 2007-12-21 Simon Goldschmidt * sys.h, api_lib.c, api_msg.c, sockets.c: fix bug #21698: "netconn->recv_avail is not protected" by using new macros for interlocked access to modify/test netconn->recv_avail. 2007-12-20 Kieran Mansley (based on patch from Oleg Tyshev) * tcp_in.c: fix bug# 21535 (nrtx not reset correctly in SYN_SENT state) 2007-12-20 Kieran Mansley (based on patch from Per-Henrik Lundbolm) * tcp.c, tcp_in.c, tcp_out.c, tcp.h: fix bug #20199 (better handling of silly window avoidance and prevent lwIP from shrinking the window) 2007-12-04 Simon Goldschmidt * tcp.c, tcp_in.c: fix bug #21699 (segment leak in ooseq processing when last data packet was lost): add assert that all segment lists are empty in tcp_pcb_remove before setting pcb to CLOSED state; don't directly set CLOSED state from LAST_ACK in tcp_process 2007-12-02 Simon Goldschmidt * sockets.h: fix bug #21654: exclude definition of struct timeval from #ifndef FD_SET If including for system-struct timeval, LWIP_TIMEVAL_PRIVATE now has to be set to 0 in lwipopts.h 2007-12-02 Simon Goldschmidt * api_msg.c, api_lib.c: fix bug #21656 (recvmbox problem in netconn API): always allocate a recvmbox in netconn_new_with_proto_and_callback. For a tcp-listen netconn, this recvmbox is later freed and a new mbox is allocated for acceptmbox. This is a fix for thread-safety and allocates all items needed for a netconn when the netconn is created. 2007-11-30 Simon Goldschmidt * udp.c: first attempt to fix bug #21655 (DHCP doesn't work reliably with multiple netifs): if LWIP_DHCP is enabled, UDP packets to DHCP_CLIENT_PORT are passed to netif->dhcp->pcb only (if that exists) and not to any other pcb for the same port (only solution to let UDP pcbs 'bind' to a netif instead of an IP address) 2007-11-27 Simon Goldschmidt * ip.c: fixed bug #21643 (udp_send/raw_send don't fail if netif is down) by letting ip_route only use netifs that are up. 2007-11-27 Simon Goldschmidt * err.h, api_lib.c, api_msg.c, sockets.c: Changed error handling: ERR_MEM, ERR_BUF and ERR_RTE are seen as non-fatal, all other errors are fatal. netconns and sockets block most operations once they have seen a fatal error. 2007-11-27 Simon Goldschmidt * udp.h, udp.c, dhcp.c: Implemented new function udp_sendto_if which takes the netif to send as an argument (to be able to send on netifs that are down). 2007-11-26 Simon Goldschmidt * tcp_in.c: Fixed bug #21582: pcb->acked accounting can be wrong when ACKs arrive out-of-order 2007-11-21 Simon Goldschmidt * tcp.h, tcp_out.c, api_msg.c: Fixed bug #20287: tcp_output_nagle sends too early Fixed the nagle algorithm; nagle now also works for all raw API applications and has to be explicitly disabled with 'tcp_pcb->flags |= TF_NODELAY' 2007-11-12 Frédéric Bernon * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fixed bug #20900. Now, most of the netconn_peer and netconn_addr processing is done inside tcpip_thread context in do_getaddr. 2007-11-10 Simon Goldschmidt * etharp.c: Fixed bug: assert fired when MEMP_ARP_QUEUE was empty (which can happen any time). Now the packet simply isn't enqueued when out of memory. 2007-11-01 Simon Goldschmidt * tcp.c, tcp_in.c: Fixed bug #21494: The send mss (pcb->mss) is set to 536 (or TCP_MSS if that is smaller) as long as no MSS option is received from the remote host. 2007-11-01 Simon Goldschmidt * tcp.h, tcp.c, tcp_in.c: Fixed bug #21491: The MSS option sent (with SYN) is now based on TCP_MSS instead of pcb->mss (on passive open now effectively sending our configured TCP_MSS instead of the one received). 2007-11-01 Simon Goldschmidt * tcp_in.c: Fixed bug #21181: On active open, the initial congestion window was calculated based on the configured TCP_MSS, not on the MSS option received with SYN+ACK. 2007-10-09 Simon Goldschmidt * udp.c, inet.c, inet.h: Fixed UDPLite: send: Checksum was always generated too short and also was generated wrong if checksum coverage != tot_len; receive: checksum was calculated wrong if checksum coverage != tot_len 2007-10-08 Simon Goldschmidt * mem.c: lfree was not updated in mem_realloc! 2007-10-07 Frédéric Bernon * sockets.c, api.h, api_lib.c: First step to fix "bug #20900 : Potential crash error problem with netconn_peer & netconn_addr". VERY IMPORTANT: this change cause an API breakage for netconn_addr, since a parameter type change. Any compiler should cause an error without any changes in yours netconn_peer calls (so, it can't be a "silent change"). It also reduce a little bit the footprint for socket layer (lwip_getpeername & lwip_getsockname use now a common lwip_getaddrname function since netconn_peer & netconn_addr have the same parameters). 2007-09-20 Simon Goldschmidt * tcp.c: Fixed bug #21080 (tcp_bind without check pcbs in TIME_WAIT state) by checking tcp_tw_pcbs also 2007-09-19 Simon Goldschmidt * icmp.c: Fixed bug #21107 (didn't reset IP TTL in ICMP echo replies) 2007-09-15 Mike Kleshov * mem.c: Fixed bug #21077 (inaccuracy in calculation of lwip_stat.mem.used) 2007-09-06 Frédéric Bernon * several-files: replace some #include "arch/cc.h" by "lwip/arch.h", or simply remove it as long as "lwip/opt.h" is included before (this one include "lwip/debug.h" which already include "lwip/arch.h"). Like that, default defines are provided by "lwip/arch.h" if they are not defined in cc.h, in the same spirit than "lwip/opt.h" for lwipopts.h. 2007-08-30 Frédéric Bernon * igmp.h, igmp.c: Some changes to remove some redundant code, add some traces, and fix some coding style. 2007-08-28 Frédéric Bernon * tcpip.c: Fix TCPIP_MSG_INPKT processing: now, tcpip_input can be used for any kind of packets. These packets are considered like Ethernet packets (payload pointing to ethhdr) if the netif got the NETIF_FLAG_ETHARP flag. Else, packets are considered like IP packets (payload pointing to iphdr). 2007-08-27 Frédéric Bernon * api.h, api_lib.c, api_msg.c: First fix for "bug #20900 : Potential crash error problem with netconn_peer & netconn_addr". Introduce NETCONN_LISTEN netconn_state and remove obsolete ones (NETCONN_RECV & NETCONN_ACCEPT). 2007-08-24 Kieran Mansley * inet.c Modify (acc >> 16) test to ((acc >> 16) != 0) to help buggy compiler (Paradigm C++) 2007-08-09 Frédéric Bernon, Bill Florac * stats.h, stats.c, igmp.h, igmp.c, opt.h: Fix for bug #20503 : IGMP Improvement. Introduce IGMP_STATS to centralize statistics management. 2007-08-09 Frédéric Bernon, Bill Florac * udp.c: Fix for bug #20503 : IGMP Improvement. Enable to receive a multicast packet on a udp pcb binded on an netif's IP address, and not on "any". 2007-08-09 Frédéric Bernon, Bill Florac * igmp.h, igmp.c, ip.c: Fix minor changes from bug #20503 : IGMP Improvement. This is mainly on using lookup/lookfor, and some coding styles... 2007-07-26 Frédéric Bernon (and "thedoctor") * igmp.c: Fix bug #20595 to accept IGMPv3 "Query" messages. 2007-07-25 Simon Goldschmidt * api_msg.c, tcp.c: Another fix for bug #20021: by not returning an error if tcp_output fails in tcp_close, the code in do_close_internal gets simpler (tcp_output is called again later from tcp timers). 2007-07-25 Simon Goldschmidt * ip_frag.c: Fixed bug #20429: use the new pbuf_copy_partial instead of the old copy_from_pbuf, which illegally modified the given pbuf. 2007-07-25 Simon Goldschmidt * tcp_out.c: tcp_enqueue: pcb->snd_queuelen didn't work for chaine PBUF_RAMs: changed snd_queuelen++ to snd_queuelen += pbuf_clen(p). 2007-07-24 Simon Goldschmidt * api_msg.c, tcp.c: Fix bug #20480: Check the pcb passed to tcp_listen() for the correct state (must be CLOSED). 2007-07-13 Thomas Taranowski (commited by Jared Grubb) * memp.c: Fix bug #20478: memp_malloc returned NULL+MEMP_SIZE on failed allocation. It now returns NULL. 2007-07-13 Frédéric Bernon * api_msg.c: Fix bug #20318: api_msg "recv" callbacks don't call pbuf_free in all error cases. 2007-07-13 Frédéric Bernon * api_msg.c: Fix bug #20315: possible memory leak problem if tcp_listen failed, because current code doesn't follow rawapi.txt documentation. 2007-07-13 Kieran Mansley * src/core/tcp_in.c Apply patch#5741 from Oleg Tyshev to fix bug in out of sequence processing of received packets 2007-07-03 Simon Goldschmidt * nearly-all-files: Added assertions where PBUF_RAM pbufs are used and an assumption is made that this pbuf is in one piece (i.e. not chained). These assumptions clash with the possibility of converting to fully pool-based pbuf implementations, where PBUF_RAM pbufs might be chained. 2007-07-03 Simon Goldschmidt * api.h, api_lib.c, api_msg.c: Final fix for bug #20021 and some other problems when closing tcp netconns: removed conn->sem, less context switches when closing, both netconn_close and netconn_delete should safely close tcp connections. 2007-07-02 Simon Goldschmidt * ipv4/ip.h, ipv6/ip.h, opt.h, netif.h, etharp.h, ipv4/ip.c, netif.c, raw.c, tcp_out.c, udp.c, etharp.c: Added option LWIP_NETIF_HWADDRHINT (default=off) to cache ARP table indices with each pcb instead of single-entry cache for the complete stack. 2007-07-02 Simon Goldschmidt * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Added some ASSERTS and casts to prevent warnings when assigning to smaller types. 2007-06-28 Simon Goldschmidt * tcp_out.c: Added check to prevent tcp_pcb->snd_queuelen from overflowing. 2007-06-28 Simon Goldschmidt * tcp.h: Fixed bug #20287: Fixed nagle algorithm (sending was done too early if a segment contained chained pbufs) 2007-06-28 Frédéric Bernon * autoip.c: replace most of rand() calls by a macro LWIP_AUTOIP_RAND which compute a "pseudo-random" value based on netif's MAC and some autoip fields. It's always possible to define this macro in your own lwipopts.h to always use C library's rand(). Note that autoip_create_rand_addr doesn't use this macro. 2007-06-28 Frédéric Bernon * netifapi.h, netifapi.c, tcpip.h, tcpip.c: Update code to handle the option LWIP_TCPIP_CORE_LOCKING, and do some changes to be coherent with last modifications in api_lib/api_msg (use pointers and not type with table, etc...) 2007-06-26 Simon Goldschmidt * udp.h: Fixed bug #20259: struct udp_hdr was lacking the packin defines. 2007-06-25 Simon Goldschmidt * udp.c: Fixed bug #20253: icmp_dest_unreach was called with a wrong p->payload for udp packets with no matching pcb. 2007-06-25 Simon Goldschmidt * udp.c: Fixed bug #20220: UDP PCB search in udp_input(): a non-local match could get udp input packets if the remote side matched. 2007-06-13 Simon Goldschmidt * netif.c: Fixed bug #20180 (TCP pcbs listening on IP_ADDR_ANY could get changed in netif_set_ipaddr if previous netif->ip_addr.addr was 0. 2007-06-13 Simon Goldschmidt * api_msg.c: pcb_new sets conn->err if protocol is not implemented -> netconn_new_..() does not allocate a new connection for unsupported protocols. 2007-06-13 Frédéric Bernon, Simon Goldschmidt * api_lib.c: change return expression in netconn_addr and netconn_peer, because conn->err was reset to ERR_OK without any reasons (and error was lost)... 2007-06-13 Frédéric Bernon, Matthias Weisser * opt.h, mem.h, mem.c, memp.c, pbuf.c, ip_frag.c, vj.c: Fix bug #20162. Rename MEM_ALIGN in LWIP_MEM_ALIGN and MEM_ALIGN_SIZE in LWIP_MEM_ALIGN_SIZE to avoid some macro names collision with some OS macros. 2007-06-11 Simon Goldschmidt * udp.c: UDP Lite: corrected the use of chksum_len (based on RFC3828: if it's 0, create checksum over the complete packet. On RX, if it's < 8 (and not 0), discard the packet. Also removed the duplicate 'udphdr->chksum = 0' for both UDP & UDP Lite. 2007-06-11 Srinivas Gollakota & Oleg Tyshev * tcp_out.c: Fix for bug #20075 : "A problem with keep-alive timer and TCP flags" where TCP flags wasn't initialized in tcp_keepalive. 2007-06-03 Simon Goldschmidt * udp.c: udp_input(): Input pbuf was not freed if pcb had no recv function registered, p->payload was modified without modifying p->len if sending icmp_dest_unreach() (had no negative effect but was definitively wrong). 2007-06-03 Simon Goldschmidt * icmp.c: Corrected bug #19937: For responding to an icmp echo request, icmp re-used the input pbuf even if that didn't have enough space to include the link headers. Now the space is tested and a new pbuf is allocated for the echo response packet if the echo request pbuf isn't big enough. 2007-06-01 Simon Goldschmidt * sockets.c: Checked in patch #5914: Moved sockopt processing into tcpip_thread. 2007-05-23 Frédéric Bernon * api_lib.c, sockets.c: Fixed bug #5958 for netconn_listen (acceptmbox only allocated by do_listen if success) and netconn_accept errors handling. In most of api_lib functions, we replace some errors checkings like "if (conn==NULL)" by ASSERT, except for netconn_delete. 2007-05-23 Frédéric Bernon * api_lib.c: Fixed bug #5957 "Safe-thread problem inside netconn_recv" to return an error code if it's impossible to fetch a pbuf on a TCP connection (and not directly close the recvmbox). 2007-05-22 Simon Goldschmidt * tcp.c: Fixed bug #1895 (tcp_bind not correct) by introducing a list of bound but unconnected (and non-listening) tcp_pcbs. 2007-05-22 Frédéric Bernon * sys.h, sys.c, api_lib.c, tcpip.c: remove sys_mbox_fetch_timeout() (was only used for LWIP_SO_RCVTIMEO option) and use sys_arch_mbox_fetch() instead of sys_mbox_fetch() in api files. Now, users SHOULD NOT use internal lwIP features like "sys_timeout" in their application threads. 2007-05-22 Frédéric Bernon * api.h, api_lib.c, api_msg.h, api_msg.c: change the struct api_msg_msg to see which parameters are used by which do_xxx function, and to avoid "misusing" parameters (patch #5938). 2007-05-22 Simon Goldschmidt * api_lib.c, api_msg.c, raw.c, api.h, api_msg.h, raw.h: Included patch #5938: changed raw_pcb.protocol from u16_t to u8_t since for IPv4 and IPv6, proto is only 8 bits wide. This affects the api, as there, the protocol was u16_t, too. 2007-05-18 Simon Goldschmidt * memp.c: addition to patch #5913: smaller pointer was returned but memp_memory was the same size -> did not save memory. 2007-05-16 Simon Goldschmidt * loopif.c, slipif.c: Fix bug #19729: free pbuf if netif->input() returns != ERR_OK. 2007-05-16 Simon Goldschmidt * api_msg.c, udp.c: If a udp_pcb has a local_ip set, check if it is the same as the one of the netif used for sending to prevent sending from old addresses after a netif address gets changed (partly fixes bug #3168). 2007-05-16 Frédéric Bernon * tcpip.c, igmp.h, igmp.c: Fixed bug "#19800 : IGMP: igmp_tick() will not work with NO_SYS=1". Note that igmp_init is always in tcpip_thread (and not in tcpip_init) because we have to be sure that network interfaces are already added (mac filter is updated only in igmp_init for the moment). 2007-05-16 Simon Goldschmidt * mem.c, memp.c: Removed semaphores from memp, changed sys_sem_wait calls into sys_arch_sem_wait calls to prevent timers from running while waiting for the heap. This fixes bug #19167. 2007-05-13 Simon Goldschmidt * tcp.h, sockets.h, sockets.c: Fixed bug from patch #5865 by moving the defines for socket options (lwip_set/-getsockopt) used with level IPPROTO_TCP from tcp.h to sockets.h. 2007-05-07 Simon Goldschmidt * mem.c: Another attempt to fix bug #17922. 2007-05-04 Simon Goldschmidt * pbuf.c, pbuf.h, etharp.c: Further update to ARP queueing: Changed pbuf_copy() implementation so that it can be reused (don't allocate the target pbuf inside pbuf_copy()). 2007-05-04 Simon Goldschmidt * memp.c: checked in patch #5913: in memp_malloc() we can return memp as mem to save a little RAM (next pointer of memp is not used while not in pool). 2007-05-03 "maq" * sockets.c: Fix ioctl FIONREAD when some data remains from last recv. (patch #3574). 2007-04-23 Simon Goldschmidt * loopif.c, loopif.h, opt.h, src/netif/FILES: fix bug #2595: "loopif results in NULL reference for incoming TCP packets". Loopif has to be configured (using LWIP_LOOPIF_MULTITHREADING) to directly call netif->input() (multithreading environments, e.g. netif->input() = tcpip_input()) or putting packets on a list that is fed to the stack by calling loopif_poll() (single-thread / NO_SYS / polling environment where e.g. netif->input() = ip_input). 2007-04-17 Jonathan Larmour * pbuf.c: Use s32_t in pbuf_realloc(), as an s16_t can't reliably hold the difference between two u16_t's. * sockets.h: FD_SETSIZE needs to match number of sockets, which is MEMP_NUM_NETCONN in sockets.c right now. 2007-04-12 Jonathan Larmour * icmp.c: Reset IP header TTL in ICMP ECHO responses (bug #19580). 2007-04-12 Kieran Mansley * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Modify way the retransmission timer is reset to fix bug#19434, with help from Oleg Tyshev. 2007-04-11 Simon Goldschmidt * etharp.c, pbuf.c, pbuf.h: 3rd fix for bug #11400 (arp-queuing): More pbufs than previously thought need to be copied (everything but PBUF_ROM!). Cleaned up pbuf.c: removed functions no needed any more (by etharp). 2007-04-11 Kieran Mansley * inet.c, ip_addr.h, sockets.h, sys.h, tcp.h: Apply patch #5745: Fix "Constant is long" warnings with 16bit compilers. Contributed by avatar@mmlab.cse.yzu.edu.tw 2007-04-05 Frédéric Bernon, Jonathan Larmour * api_msg.c: Fix bug #16830: "err_tcp() posts to connection mailbox when no pend on the mailbox is active". Now, the post is only done during a connect, and do_send, do_write and do_join_leave_group don't do anything if a previous error was signaled. 2007-04-03 Frédéric Bernon * ip.c: Don't set the IP_DF ("Don't fragment") flag in the IP header in IP output packets. See patch #5834. 2007-03-30 Frédéric Bernon * api_msg.c: add a "pcb_new" helper function to avoid redundant code, and to add missing pcb allocations checking (in do_bind, and for each raw_new). Fix style. 2007-03-30 Frédéric Bernon * most of files: prefix all debug.h define with "LWIP_" to avoid any conflict with others environment defines (these were too "generic"). 2007-03-28 Frédéric Bernon * api.h, api_lib.c, sockets.c: netbuf_ref doesn't check its internal pbuf_alloc call result and can cause a crash. lwip_send now check netbuf_ref result. 2007-03-28 Simon Goldschmidt * sockets.c Remove "#include " from sockets.c to avoid multiple definition of macros (in errno.h and lwip/arch.h) if LWIP_PROVIDE_ERRNO is defined. This is the way it should have been already (looking at doc/sys_arch.txt) 2007-03-28 Kieran Mansley * opt.h Change default PBUF_POOL_BUFSIZE (again) to accomodate default MSS + IP and TCP headers *and* physical link headers 2007-03-26 Frédéric Bernon (based on patch from Dmitry Potapov) * api_lib.c: patch for netconn_write(), fixes a possible race condition which cause to send some garbage. It is not a definitive solution, but the patch does solve the problem for most cases. 2007-03-22 Frédéric Bernon * api_msg.h, api_msg.c: Remove obsolete API_MSG_ACCEPT and do_accept (never used). 2007-03-22 Frédéric Bernon * api_lib.c: somes resources couldn't be freed if there was errors during netconn_new_with_proto_and_callback. 2007-03-22 Frédéric Bernon * ethernetif.c: update netif->input calls to check return value. In older ports, it's a good idea to upgrade them, even if before, there could be another problem (access to an uninitialized mailbox). 2007-03-21 Simon Goldschmidt * sockets.c: fixed bug #5067 (essentialy a signed/unsigned warning fixed by casting to unsigned). 2007-03-21 Frédéric Bernon * api_lib.c, api_msg.c, tcpip.c: integrate sys_mbox_fetch(conn->mbox, NULL) calls from api_lib.c to tcpip.c's tcpip_apimsg(). Now, use a local variable and not a dynamic one from memp to send tcpip_msg to tcpip_thread in a synchrone call. Free tcpip_msg from tcpip_apimsg is not done in tcpip_thread. This give a faster and more reliable communication between api_lib and tcpip. 2007-03-21 Frédéric Bernon * opt.h: Add LWIP_NETIF_CALLBACK (to avoid compiler warning) and set it to 0. 2007-03-21 Frédéric Bernon * api_msg.c, igmp.c, igmp.h: Fix C++ style comments 2007-03-21 Kieran Mansley * opt.h Change default PBUF_POOL_BUFSIZE to accomodate default MSS + IP and TCP headers 2007-03-21 Kieran Mansley * Fix all uses of pbuf_header to check the return value. In some cases just assert if it fails as I'm not sure how to fix them, but this is no worse than before when they would carry on regardless of the failure. 2007-03-21 Kieran Mansley * sockets.c, igmp.c, igmp.h, memp.h: Fix C++ style comments and comment out missing header include in icmp.c 2007-03-20 Frédéric Bernon * memp.h, stats.c: Fix stats_display function where memp_names table wasn't synchronized with memp.h. 2007-03-20 Frédéric Bernon * tcpip.c: Initialize tcpip's mbox, and verify if initialized in tcpip_input, tcpip_ethinput, tcpip_callback, tcpip_apimsg, to fix a init problem with network interfaces. Also fix a compiler warning. 2007-03-20 Kieran Mansley * udp.c: Only try and use pbuf_header() to make space for headers if not a ROM or REF pbuf. 2007-03-19 Frédéric Bernon * api_msg.h, api_msg.c, tcpip.h, tcpip.c: Add return types to tcpip_apimsg() and api_msg_post(). 2007-03-19 Frédéric Bernon * Remove unimplemented "memp_realloc" function from memp.h. 2007-03-11 Simon Goldschmidt * pbuf.c: checked in patch #5796: pbuf_alloc: len field claculation caused memory corruption. 2007-03-11 Simon Goldschmidt (based on patch from Dmitry Potapov) * api_lib.c, sockets.c, api.h, api_msg.h, sockets.h: Fixed bug #19251 (missing `const' qualifier in socket functions), to get more compatible to standard POSIX sockets. 2007-03-11 Frédéric Bernon (based on patch from Dmitry Potapov) * sockets.c: Add asserts inside bind, connect and sendto to check input parameters. Remove excessive set_errno() calls after get_socket(), because errno is set inside of get_socket(). Move last sock_set_errno() inside lwip_close. 2007-03-09 Simon Goldschmidt * memp.c: Fixed bug #11400: New etharp queueing introduced bug: memp_memory was allocated too small. 2007-03-06 Simon Goldschmidt * tcpip.c: Initialize dhcp timers in tcpip_thread (if LWIP_DHCP) to protect the stack from concurrent access. 2007-03-06 Frédéric Bernon, Dmitry Potapov * tcpip.c, ip_frag.c, ethernetif.c: Fix some build problems, and a redundancy call to "lwip_stats.link.recv++;" in low_level_input() & ethernetif_input(). 2007-03-06 Simon Goldschmidt * ip_frag.c, ip_frag.h: Reduce code size: don't include code in those files if IP_FRAG == 0 and IP_REASSEMBLY == 0 2007-03-06 Frédéric Bernon, Simon Goldschmidt * opt.h, ip_frag.h, tcpip.h, tcpip.c, ethernetif.c: add new configuration option named ETHARP_TCPIP_ETHINPUT, which enable the new tcpip_ethinput. Allow to do ARP processing for incoming packets inside tcpip_thread (protecting ARP layer against concurrent access). You can also disable old code using tcp_input with new define ETHARP_TCPIP_INPUT set to 0. Older ports have to use tcpip_ethinput. 2007-03-06 Simon Goldschmidt (based on patch from Dmitry Potapov) * err.h, err.c: fixed compiler warning "initialization dircards qualifiers from pointer target type" 2007-03-05 Frédéric Bernon * opt.h, sockets.h: add new configuration options (LWIP_POSIX_SOCKETS_IO_NAMES, ETHARP_TRUST_IP_MAC, review SO_REUSE) 2007-03-04 Frédéric Bernon * api_msg.c: Remove some compiler warnings : parameter "pcb" was never referenced. 2007-03-04 Frédéric Bernon * api_lib.c: Fix "[patch #5764] api_lib.c cleanup: after patch #5687" (from Dmitry Potapov). The api_msg struct stay on the stack (not moved to netconn struct). 2007-03-04 Simon Goldschmidt (based on patch from Dmitry Potapov) * pbuf.c: Fix BUG#19168 - pbuf_free can cause deadlock (if SYS_LIGHTWEIGHT_PROT=1 & freeing PBUF_RAM when mem_sem is not available) Also fixed cast warning in pbuf_alloc() 2007-03-04 Simon Goldschmidt * etharp.c, etharp.h, memp.c, memp.h, opt.h: Fix BUG#11400 - don't corrupt existing pbuf chain when enqueuing multiple pbufs to a pending ARP request 2007-03-03 Frédéric Bernon * udp.c: remove obsolete line "static struct udp_pcb *pcb_cache = NULL;" It is static, and never used in udp.c except udp_init(). 2007-03-02 Simon Goldschmidt * tcpip.c: Moved call to ip_init(), udp_init() and tcp_init() from tcpip_thread() to tcpip_init(). This way, raw API connections can be initialized before tcpip_thread is running (e.g. before OS is started) 2007-03-02 Frédéric Bernon * rawapi.txt: Fix documentation mismatch with etharp.h about etharp_tmr's call interval. 2007-02-28 Kieran Mansley * pbuf.c: Fix BUG#17645 - ensure pbuf payload pointer is not moved outside the region of the pbuf by pbuf_header() 2007-02-28 Kieran Mansley * sockets.c: Fix BUG#19161 - ensure milliseconds timeout is non-zero when supplied timeout is also non-zero (STABLE-1.2.0) 2006-12-05 Leon Woestenberg * CHANGELOG: Mention STABLE-1.2.0 release. ++ New features: 2006-12-01 Christiaan Simons * mem.h, opt.h: Added MEM_LIBC_MALLOC option. Note this is a workaround. Currently I have no other options left. 2006-10-26 Christiaan Simons (accepted patch by Jonathan Larmour) * ipv4/ip_frag.c: rename MAX_MTU to IP_FRAG_MAX_MTU and move define to include/lwip/opt.h. * ipv4/lwip/ip_frag.h: Remove unused IP_REASS_INTERVAL. Move IP_REASS_MAXAGE and IP_REASS_BUFSIZE to include/lwip/opt.h. * opt.h: Add above new options. 2006-08-18 Christiaan Simons * tcp_{in,out}.c: added SNMP counters. * ipv4/ip.c: added SNMP counters. * ipv4/ip_frag.c: added SNMP counters. 2006-08-08 Christiaan Simons * etharp.{c,h}: added etharp_find_addr() to read (stable) ethernet/IP address pair from ARP table 2006-07-14 Christiaan Simons * mib_structs.c: added * include/lwip/snmp_structs.h: added * netif.{c,h}, netif/ethernetif.c: added SNMP statistics to netif struct 2006-07-06 Christiaan Simons * snmp/asn1_{enc,dec}.c added * snmp/mib2.c added * snmp/msg_{in,out}.c added * include/lwip/snmp_asn1.h added * include/lwip/snmp_msg.h added * doc/snmp_agent.txt added 2006-03-29 Christiaan Simons * inet.c, inet.h: Added platform byteswap support. Added LWIP_PLATFORM_BYTESWAP define (defaults to 0) and optional LWIP_PLATFORM_HTONS(), LWIP_PLATFORM_HTONL() macros. ++ Bug fixes: 2006-11-30 Christiaan Simons * dhcp.c: Fixed false triggers of request_timeout. 2006-11-28 Christiaan Simons * netif.c: In netif_add() fixed missing clear of ip_addr, netmask, gw and flags. 2006-10-11 Christiaan Simons * api_lib.c etharp.c, ip.c, memp.c, stats.c, sys.{c,h} tcp.h: Partially accepted patch #5449 for ANSI C compatibility / build fixes. * ipv4/lwip/ip.h ipv6/lwip/ip.h: Corrected UDP-Lite protocol identifier from 170 to 136 (bug #17574). 2006-10-10 Christiaan Simons * api_msg.c: Fixed Nagle algorithm as reported by Bob Grice. 2006-08-17 Christiaan Simons * udp.c: Fixed bug #17200, added check for broadcast destinations for PCBs bound to a unicast address. 2006-08-07 Christiaan Simons * api_msg.c: Flushing TCP output in do_close() (bug #15926). 2006-06-27 Christiaan Simons * api_msg.c: Applied patch for cold case (bug #11135). In accept_function() ensure newconn->callback is always initialized. 2006-06-15 Christiaan Simons * mem.h: added MEM_SIZE_F alias to fix an ancient cold case (bug #1748), facilitate printing of mem_size_t and u16_t statistics. 2006-06-14 Christiaan Simons * api_msg.c: Applied patch #5146 to handle allocation failures in accept() by Kevin Lawson. 2006-05-26 Christiaan Simons * api_lib.c: Removed conn->sem creation and destruction from netconn_write() and added sys_sem_new to netconn_new_*. (STABLE-1_1_1) 2006-03-03 Christiaan Simons * ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap access and added pbuf_alloc() return value checks. 2006-01-01 Leon Woestenberg * tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is now handled by the checksum routine properly. 2006-02-27 Leon Woestenberg * pbuf.c: Fix alignment; pbuf_init() would not work unless pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.) 2005-12-20 Leon Woestenberg * tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch submitted by Mitrani Hiroshi. 2005-12-15 Christiaan Simons * inet.c: Disabled the added summing routine to preserve code space. 2005-12-14 Leon Woestenberg * tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson. Added Curt McDowell's optimized checksumming routine for future inclusion. Need to create test case for unaliged, aligned, odd, even length combination of cases on various endianess machines. 2005-12-09 Christiaan Simons * inet.c: Rewrote standard checksum routine in proper portable C. 2005-11-25 Christiaan Simons * udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only. * *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t, u32_t, s32_t typedefs. This solves most debug word-length assumes. 2005-07-17 Leon Woestenberg * inet.c: Fixed unaligned 16-bit access in the standard checksum routine by Peter Jolasson. * slipif.c: Fixed implementation assumption of single-pbuf datagrams. 2005-02-04 Leon Woestenberg * tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch. * tcp_{out|in}.c: Applied patch fixing unaligned access. 2005-01-04 Leon Woestenberg * pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement. 2005-01-03 Leon Woestenberg * udp.c: UDP pcb->recv() was called even when it was NULL. (STABLE-1_1_0) 2004-12-28 Leon Woestenberg * etharp.*: Disabled multiple packets on the ARP queue. This clashes with TCP queueing. 2004-11-28 Leon Woestenberg * etharp.*: Fixed race condition from ARP request to ARP timeout. Halved the ARP period, doubled the period counts. ETHARP_MAX_PENDING now should be at least 2. This prevents the counter from reaching 0 right away (which would allow too little time for ARP responses to be received). 2004-11-25 Leon Woestenberg * dhcp.c: Decline messages were not multicast but unicast. * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD. Do not try hard to insert arbitrary packet's source address, etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. etharp_query() now always DOES call ETHARP_TRY_HARD so that users querying an address will see it appear in the cache (DHCP could suffer from this when a server invalidly gave an in-use address.) * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are comparing network addresses (identifiers), not the network masks themselves. * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given IP address actually belongs to the network of the given interface. 2004-11-24 Kieran Mansley * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state. (STABLE-1_1_0-RC1) 2004-10-16 Kieran Mansley * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately, even if one is already pending, if the rcv_wnd is above a threshold (currently TCP_WND/2). This avoids waiting for a timer to expire to send a delayed ACK in order to open the window if the stack is only receiving data. 2004-09-12 Kieran Mansley * tcp*.*: Retransmit time-out handling improvement by Sam Jansen. 2004-08-20 Tony Mountifield * etharp.c: Make sure the first pbuf queued on an ARP entry is properly ref counted. 2004-07-27 Tony Mountifield * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler warnings about comparison. * pbuf.c: Stopped compiler complaining of empty if statement when LWIP_DEBUGF() empty. Closed an unclosed comment. * tcp.c: Stopped compiler complaining of empty if statement when LWIP_DEBUGF() empty. * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons(). * inet.c: Added a couple of casts to quiet the compiler. No need to test isascii(c) before isdigit(c) or isxdigit(c). 2004-07-22 Tony Mountifield * inet.c: Made data types consistent in inet_ntoa(). Added casts for return values of checksum routines, to pacify compiler. * ip_frag.c, tcp_out.c, sockets.c, pbuf.c Small corrections to some debugging statements, to pacify compiler. 2004-07-21 Tony Mountifield * etharp.c: Removed spurious semicolon and added missing end-of-comment. * ethernetif.c Updated low_level_output() to match prototype for netif->linkoutput and changed low_level_input() similarly for consistency. * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype of raw_recv() in raw.h and so avoid compiler error. * sockets.c: Added trivial (int) cast to keep compiler happier. * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros. (STABLE-1_0_0) ++ Changes: 2004-07-05 Leon Woestenberg * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure your cc.h file defines this either 1 or 0. If non-defined, defaults to 1. * .c: Added and includes where used. * etharp.c: Made some array indices unsigned. 2004-06-27 Leon Woestenberg * netif.*: Added netif_set_up()/down(). * dhcp.c: Changes to restart program flow. 2004-05-07 Leon Woestenberg * etharp.c: In find_entry(), instead of a list traversal per candidate, do a single-pass lookup for different candidates. Should exploit locality. 2004-04-29 Leon Woestenberg * tcp*.c: Cleaned up source comment documentation for Doxygen processing. * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC. * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option. ++ Bug fixes: 2004-04-27 Leon Woestenberg * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution suggested by Timmy Brolin. Fix for 32-bit processors that cannot access non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix is to prefix the 14-bit Ethernet headers with two padding bytes. 2004-04-23 Leon Woestenberg * ip_addr.c: Fix in the ip_addr_isbroadcast() check. * etharp.c: Fixed the case where the packet that initiates the ARP request is not queued, and gets lost. Fixed the case where the packets destination address is already known; we now always queue the packet and perform an ARP request. (STABLE-0_7_0) ++ Bug fixes: * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition. * Fixed TCP bug in dequeueing of FIN from out of order segment queue. * Fixed two possible NULL references in rare cases. (STABLE-0_6_6) ++ Bug fixes: * Fixed DHCP which did not include the IP address in DECLINE messages. ++ Changes: * etharp.c has been hauled over a bit. (STABLE-0_6_5) ++ Bug fixes: * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic. * Packets sent from ARP queue had invalid source hardware address. ++ Changes: * Pass-by ARP requests do now update the cache. ++ New features: * No longer dependent on ctype.h. * New socket options. * Raw IP pcb support. (STABLE-0_6_4) ++ Bug fixes: * Some debug formatters and casts fixed. * Numereous fixes in PPP. ++ Changes: * DEBUGF now is LWIP_DEBUGF * pbuf_dechain() has been re-enabled. * Mentioned the changed use of CVS branches in README. (STABLE-0_6_3) ++ Bug fixes: * Fixed pool pbuf memory leak in pbuf_alloc(). Occured if not enough PBUF_POOL pbufs for a packet pbuf chain. Reported by Savin Zlobec. * PBUF_POOL chains had their tot_len field not set for non-first pbufs. Fixed in pbuf_alloc(). ++ New features: * Added PPP stack contributed by Marc Boucher ++ Changes: * Now drops short packets for ICMP/UDP/TCP protocols. More robust. * ARP queueuing now queues the latest packet instead of the first. This is the RFC recommended behaviour, but can be overridden in lwipopts.h. (0.6.2) ++ Bugfixes: * TCP has been fixed to deal with the new use of the pbuf->ref counter. * DHCP dhcp_inform() crash bug fixed. ++ Changes: * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed pbuf_refresh(). This has sped up pbuf pool operations considerably. Implemented by David Haas. (0.6.1) ++ New features: * The packet buffer implementation has been enhanced to support zero-copy and copy-on-demand for packet buffers which have their payloads in application-managed memory. Implemented by David Haas. Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy if an outgoing packet can be directly sent on the link, or perform a copy-on-demand when necessary. The application can safely assume the packet is sent, and the RAM is available to the application directly after calling udp_send() or similar function. ++ Bugfixes: * ARP_QUEUEING should now correctly work for all cases, including PBUF_REF. Implemented by Leon Woestenberg. ++ Changes: * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer to a '0.0.0.0' IP address. * The packet buffer implementation is changed. The pbuf->ref counter meaning has changed, and several pbuf functions have been adapted accordingly. * netif drivers have to be changed to set the hardware address length field that must be initialized correctly by the driver (hint: 6 for Ethernet MAC). See the contrib/ports/c16x cs8900 driver as a driver example. * netif's have a dhcp field that must be initialized to NULL by the driver. See the contrib/ports/c16x cs8900 driver as a driver example. (0.5.x) This file has been unmaintained up to 0.6.1. All changes are logged in CVS but have not been explained here. (0.5.3) Changes since version 0.5.2 ++ Bugfixes: * memp_malloc(MEMP_API_MSG) could fail with multiple application threads because it wasn't protected by semaphores. ++ Other changes: * struct ip_addr now packed. * The name of the time variable in arp.c has been changed to ctime to avoid conflicts with the time() function. (0.5.2) Changes since version 0.5.1 ++ New features: * A new TCP function, tcp_tmr(), now handles both TCP timers. ++ Bugfixes: * A bug in tcp_parseopt() could cause the stack to hang because of a malformed TCP option. * The address of new connections in the accept() function in the BSD socket library was not handled correctly. * pbuf_dechain() did not update the ->tot_len field of the tail. * Aborted TCP connections were not handled correctly in all situations. ++ Other changes: * All protocol header structs are now packed. * The ->len field in the tcp_seg structure now counts the actual amount of data, and does not add one for SYN and FIN segments. (0.5.1) Changes since version 0.5.0 ++ New features: * Possible to run as a user process under Linux. * Preliminary support for cross platform packed structs. * ARP timer now implemented. ++ Bugfixes: * TCP output queue length was badly initialized when opening connections. * TCP delayed ACKs were not sent correctly. * Explicit initialization of BSS segment variables. * read() in BSD socket library could drop data. * Problems with memory alignment. * Situations when all TCP buffers were used could lead to starvation. * TCP MSS option wasn't parsed correctly. * Problems with UDP checksum calculation. * IP multicast address tests had endianess problems. * ARP requests had wrong destination hardware address. ++ Other changes: * struct eth_addr changed from u16_t[3] array to u8_t[6]. * A ->linkoutput() member was added to struct netif. * TCP and UDP ->dest_* struct members where changed to ->remote_*. * ntoh* macros are now null definitions for big endian CPUs. (0.5.0) Changes since version 0.4.2 ++ New features: * Redesigned operating system emulation layer to make porting easier. * Better control over TCP output buffers. * Documenation added. ++ Bugfixes: * Locking issues in buffer management. * Bugfixes in the sequential API. * IP forwarding could cause memory leakage. This has been fixed. ++ Other changes: * Directory structure somewhat changed; the core/ tree has been collapsed. (0.4.2) Changes since version 0.4.1 ++ New features: * Experimental ARP implementation added. * Skeleton Ethernet driver added. * Experimental BSD socket API library added. ++ Bugfixes: * In very intense situations, memory leakage could occur. This has been fixed. ++ Other changes: * Variables named "data" and "code" have been renamed in order to avoid name conflicts in certain compilers. * Variable++ have in appliciable cases been translated to ++variable since some compilers generate better code in the latter case. (0.4.1) Changes since version 0.4 ++ New features: * TCP: Connection attempts time out earlier than data transmissions. Nagle algorithm implemented. Push flag set on the last segment in a burst. * UDP: experimental support for UDP-Lite extensions. ++ Bugfixes: * TCP: out of order segments were in some cases handled incorrectly, and this has now been fixed. Delayed acknowledgements was broken in 0.4, has now been fixed. Binding to an address that is in use now results in an error. Reset connections sometimes hung an application; this has been fixed. * Checksum calculation sometimes failed for chained pbufs with odd lengths. This has been fixed. * API: a lot of bug fixes in the API. The UDP API has been improved and tested. Error reporting and handling has been improved. Logical flaws and race conditions for incoming TCP connections has been found and removed. * Memory manager: alignment issues. Reallocating memory sometimes failed, this has been fixed. * Generic library: bcopy was flawed and has been fixed. ++ Other changes: * API: all datatypes has been changed from generic ones such as ints, to specified ones such as u16_t. Functions that return errors now have the correct type (err_t). * General: A lot of code cleaned up and debugging code removed. Many portability issues have been fixed. * The license was changed; the advertising clause was removed. * C64 port added. * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri Kosunen, Mikael Caleres, and Frits Wilmink for reporting and fixing bugs! (0.4) Changes since version 0.3.1 * Memory management has been radically changed; instead of allocating memory from a shared heap, memory for objects that are rapidly allocated and deallocated is now kept in pools. Allocation and deallocation from those memory pools is very fast. The shared heap is still present but is used less frequently. * The memory, memory pool, and packet buffer subsystems now support 4-, 2-, or 1-byte alignment. * "Out of memory" situations are handled in a more robust way. * Stack usage has been reduced. * Easier configuration of lwIP parameters such as memory usage, TTLs, statistics gathering, etc. All configuration parameters are now kept in a single header file "lwipopts.h". * The directory structure has been changed slightly so that all architecture specific files are kept under the src/arch hierarchy. * Error propagation has been improved, both in the protocol modules and in the API. * The code for the RTXC architecture has been implemented, tested and put to use. * Bugs have been found and corrected in the TCP, UDP, IP, API, and the Internet checksum modules. * Bugs related to porting between a 32-bit and a 16-bit architecture have been found and corrected. * The license has been changed slightly to conform more with the original BSD license, including the advertisement clause. (0.3.1) Changes since version 0.3 * Fix of a fatal bug in the buffer management. Pbufs with allocated RAM never returned the RAM when the pbuf was deallocated. * TCP congestion control, window updates and retransmissions did not work correctly. This has now been fixed. * Bugfixes in the API. (0.3) Changes since version 0.2 * New and improved directory structure. All include files are now kept in a dedicated include/ directory. * The API now has proper error handling. A new function, netconn_err(), now returns an error code for the connection in case of errors. * Improvements in the memory management subsystem. The system now keeps a pointer to the lowest free memory block. A new function, mem_malloc2() tries to allocate memory once, and if it fails tries to free some memory and retry the allocation. * Much testing has been done with limited memory configurations. lwIP now does a better job when overloaded. * Some bugfixes and improvements to the buffer (pbuf) subsystem. * Many bugfixes in the TCP code: - Fixed a bug in tcp_close(). - The TCP receive window was incorrectly closed when out of sequence segments was received. This has been fixed. - Connections are now timed-out of the FIN-WAIT-2 state. - The initial congestion window could in some cases be too large. This has been fixed. - The retransmission queue could in some cases be screwed up. This has been fixed. - TCP RST flag now handled correctly. - Out of sequence data was in some cases never delivered to the application. This has been fixed. - Retransmitted segments now contain the correct acknowledgment number and advertised window. - TCP retransmission timeout backoffs are not correctly computed (ala BSD). After a number of retransmissions, TCP now gives up the connection. * TCP connections now are kept on three lists, one for active connections, one for listening connections, and one for connections that are in TIME-WAIT. This greatly speeds up the fast timeout processing for sending delayed ACKs. * TCP now provides proper feedback to the application when a connection has been successfully set up. * More comments have been added to the code. The code has also been somewhat cleaned up. (0.2) Initial public release. ================================================ FILE: Huawei_LiteOS/components/net/lwip/lwip-2.0.3/COPYING ================================================ /* * Copyright (c) 2001, 2002 Swedish Institute of Computer Science. * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * OF SUCH DAMAGE. * * This file is part of the lwIP TCP/IP stack. * * Author: Adam Dunkels * */ ================================================ FILE: Huawei_LiteOS/components/net/lwip/lwip-2.0.3/FILES ================================================ src/ - The source code for the lwIP TCP/IP stack. doc/ - The documentation for lwIP. test/ - Some code to test whether the sources do what they should. See also the FILES file in each subdirectory. ================================================ FILE: Huawei_LiteOS/components/net/lwip/lwip-2.0.3/README ================================================ INTRODUCTION lwIP is a small independent implementation of the TCP/IP protocol suite that has been developed by Adam Dunkels at the Computer and Networks Architectures (CNA) lab at the Swedish Institute of Computer Science (SICS). The focus of the lwIP TCP/IP implementation is to reduce the RAM usage while still having a full scale TCP. This making lwIP suitable for use in embedded systems with tens of kilobytes of free RAM and room for around 40 kilobytes of code ROM. FEATURES * IP (Internet Protocol, IPv4 and IPv6) including packet forwarding over multiple network interfaces * ICMP (Internet Control Message Protocol) for network maintenance and debugging * IGMP (Internet Group Management Protocol) for multicast traffic management * MLD (Multicast listener discovery for IPv6). Aims to be compliant with RFC 2710. No support for MLDv2 * ND (Neighbor discovery and stateless address autoconfiguration for IPv6). Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862 (Address autoconfiguration) * UDP (User Datagram Protocol) including experimental UDP-lite extensions * TCP (Transmission Control Protocol) with congestion control, RTT estimation and fast recovery/fast retransmit * raw/native API for enhanced performance * Optional Berkeley-like socket API * DNS (Domain names resolver) APPLICATIONS * HTTP server with SSI and CGI * SNMPv2c agent with MIB compiler (Simple Network Management Protocol) * SNTP (Simple network time protocol) * NetBIOS name service responder * MDNS (Multicast DNS) responder * iPerf server implementation LICENSE lwIP is freely available under a BSD license. DEVELOPMENT lwIP has grown into an excellent TCP/IP stack for embedded devices, and developers using the stack often submit bug fixes, improvements, and additions to the stack to further increase its usefulness. Development of lwIP is hosted on Savannah, a central point for software development, maintenance and distribution. Everyone can help improve lwIP by use of Savannah's interface, Git and the mailing list. A core team of developers will commit changes to the Git source tree. The lwIP TCP/IP stack is maintained in the 'lwip' Git module and contributions (such as platform ports) are in the 'contrib' Git module. See doc/savannah.txt for details on Git server access for users and developers. The current Git trees are web-browsable: http://git.savannah.gnu.org/cgit/lwip.git http://git.savannah.gnu.org/cgit/lwip/lwip-contrib.git Submit patches and bugs via the lwIP project page: http://savannah.nongnu.org/projects/lwip/ Continuous integration builds (GCC, clang): https://travis-ci.org/yarrick/lwip-merged DOCUMENTATION Self documentation of the source code is regularly extracted from the current Git sources and is available from this web page: http://www.nongnu.org/lwip/ There is now a constantly growing wiki about lwIP at http://lwip.wikia.com/wiki/LwIP_Wiki Also, there are mailing lists you can subscribe at http://savannah.nongnu.org/mail/?group=lwip plus searchable archives: http://lists.nongnu.org/archive/html/lwip-users/ http://lists.nongnu.org/archive/html/lwip-devel/ lwIP was originally written by Adam Dunkels: http://dunkels.com/adam/ Reading Adam's papers, the files in docs/, browsing the source code documentation and browsing the mailing list archives is a good way to become familiar with the design of lwIP. Adam Dunkels Leon Woestenberg ================================================ FILE: Huawei_LiteOS/components/net/lwip/lwip-2.0.3/UPGRADING ================================================ This file lists major changes between release versions that require ports or applications to be changed. Use it to update a port or an application written for an older version of lwIP to correctly work with newer versions. (git master) * [Enter new changes just after this line - do not remove this line] (2.0.2) ++ Application changes: * slipif: The way to pass serial port number has changed. netif->num is not supported any more, netif->state is interpreted as an u8_t port number now (it's not a POINTER to an u8_t any more!) (2.0.1) ++ Application changes: * UDP does NOT receive multicast traffic from ALL netifs on an UDP PCB bound to a specific netif any more. Users need to bind to IP_ADDR_ANY to receive multicast traffic and compare ip_current_netif() to the desired netif for every packet. See bug #49662 for an explanation. (2.0.0) ++ Application changes: * Changed netif "up" flag handling to be an administrative flag (as opposed to the previous meaning of "ip4-address-valid", a netif will now not be used for transmission if not up) -> even a DHCP netif has to be set "up" before starting the DHCP client * Added IPv6 support (dual-stack or IPv4/IPv6 only) * Changed ip_addr_t to be a union in dual-stack mode (use ip4_addr_t where referring to IPv4 only). * Major rewrite of SNMP (added MIB parser that creates code stubs for custom MIBs); supports SNMPv2c (experimental v3 support) * Moved some core applications from contrib repository to src/apps (and include/lwip/apps) +++ Raw API: * Changed TCP listen backlog: removed tcp_accepted(), added the function pair tcp_backlog_delayed()/ tcp_backlog_accepted() to explicitly delay backlog handling on a connection pcb +++ Socket API: * Added an implementation for posix sendmsg() * Added LWIP_FIONREAD_LINUXMODE that makes ioctl/FIONREAD return the size of the next pending datagram ++ Port changes +++ new files: * MANY new and moved files! * Added src/Filelists.mk for use in Makefile projects * Continued moving stack-internal parts from abc.h to abc_priv.h in sub-folder "priv" to let abc.h only contain the actual application programmer's API +++ sys layer: * Made LWIP_TCPIP_CORE_LOCKING==1 the default as it usually performs better than the traditional message passing (although with LWIP_COMPAT_MUTEX you are still open to priority inversion, so this is not recommended any more) * Added LWIP_NETCONN_SEM_PER_THREAD to use one "op_completed" semaphore per thread instead of using one per netconn (these semaphores are used even with core locking enabled as some longer lasting functions like big writes still need to delay) * Added generalized abstraction for itoa(), strnicmp(), stricmp() and strnstr() in def.h (to be overridden in cc.h) instead of config options for netbiosns, httpd, dns, etc. ... * New abstraction for hton* and ntoh* functions in def.h. To override them, use the following in cc.h: #define lwip_htons(x) #define lwip_htonl(x) +++ new options: * TODO +++ new pools: * Added LWIP_MEMPOOL_* (declare/init/alloc/free) to declare private memp pools that share memp.c code but do not have to be made global via lwippools.h * Added pools for IPv6, MPU_COMPATIBLE, dns-api, netif-api, etc. * added hook LWIP_HOOK_MEMP_AVAILABLE() to get informed when a memp pool was empty and an item is now available * Signature of LWIP_HOOK_VLAN_SET macro was changed * LWIP_DECLARE_MEMORY_ALIGNED() may be used to declare aligned memory buffers (mem/memp) or to move buffers to dedicated memory using compiler attributes * Standard C headers are used to define sized types and printf formatters (disable by setting LWIP_NO_STDINT_H=1 or LWIP_NO_INTTYPES_H=1 if your compiler does not support these) ++ Major bugfixes/improvements * Added IPv6 support (dual-stack or IPv4/IPv6 only) * Major rewrite of PPP (incl. keep-up with apache pppd) see doc/ppp.txt for an upgrading how-to * Major rewrite of SNMP (incl. MIB parser) * Fixed timing issues that might have lead to losing a DHCP lease * Made rx processing path more robust against crafted errors * TCP window scaling support * modification of api modules to support FreeRTOS-MPU (don't pass stack-pointers to other threads) * made DNS client more robust * support PBUF_REF for RX packets * LWIP_NETCONN_FULLDUPLEX allows netconn/sockets to be used for reading/writing from separate threads each (needs LWIP_NETCONN_SEM_PER_THREAD) * Moved and reordered stats (mainly memp/mib2) (1.4.0) ++ Application changes: * Replaced struct ip_addr by typedef ip_addr_t (struct ip_addr is kept for compatibility to old applications, but will be removed in the future). * Renamed mem_realloc() to mem_trim() to prevent confusion with realloc() +++ Raw API: * Changed the semantics of tcp_close() (since it was rather a shutdown before): Now the application does *NOT* get any calls to the recv callback (aside from NULL/closed) after calling tcp_close() * When calling tcp_abort() from a raw API TCP callback function, make sure you return ERR_ABRT to prevent accessing unallocated memory. (ERR_ABRT now means the applicaiton has called tcp_abort!) +++ Netconn API: * Changed netconn_receive() and netconn_accept() to return err_t, not a pointer to new data/netconn. +++ Socket API: * LWIP_SO_RCVTIMEO: when accept() or recv() time out, they now set errno to EWOULDBLOCK/EAGAIN, not ETIMEDOUT. * Added a minimal version of posix fctl() to have a standardised way to set O_NONBLOCK for nonblocking sockets. +++ all APIs: * correctly implemented SO(F)_REUSEADDR ++ Port changes +++ new files: * Added 4 new files: def.c, timers.c, timers.h, tcp_impl.h: * Moved stack-internal parts of tcp.h to tcp_impl.h, tcp.h now only contains the actual application programmer's API * Separated timer implementation from sys.h/.c, moved to timers.h/.c; Added timer implementation for NO_SYS==1, set NO_SYS_NO_TIMERS==1 if you still want to use your own timer implementation for NO_SYS==0 (as before). +++ sys layer: * Converted mbox- and semaphore-functions to take pointers to sys_mbox_t/ sys_sem_t; * Converted sys_mbox_new/sys_sem_new to take pointers and return err_t; * Added Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX to let sys.h use binary semaphores instead of mutexes - as before) +++ new options: * Don't waste memory when chaining segments, added option TCP_OVERSIZE to prevent creating many small pbufs when calling tcp_write with many small blocks of data. Instead, pbufs are allocated larger than needed and the space is used for later calls to tcp_write. * Added LWIP_NETIF_TX_SINGLE_PBUF to always copy to try to create single pbufs in tcp_write/udp_send. * Added an additional option LWIP_ETHERNET to support ethernet without ARP (necessary for pure PPPoE) * Add MEMP_SEPARATE_POOLS to place memory pools in separate arrays. This may be used to place these pools into user-defined memory by using external declaration. * Added TCP_SNDQUEUELOWAT corresponding to TCP_SNDLOWAT +++ new pools: * Netdb uses a memp pool for allocating memory when getaddrinfo() is called, so MEMP_NUM_NETDB has to be set accordingly. * DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses a memp pool instead of the heap, so MEMP_NUM_LOCALHOSTLIST has to be set accordingly. * Snmp-agent uses a memp pools instead of the heap, so MEMP_NUM_SNMP_* have to be set accordingly. * PPPoE uses a MEMP pool instead of the heap, so MEMP_NUM_PPPOE_INTERFACES has to be set accordingly * Integrated loopif into netif.c - loopif does not have to be created by the port any more, just define LWIP_HAVE_LOOPIF to 1. * Added define LWIP_RAND() for lwip-wide randomization (needs to be defined in cc.h, e.g. used by igmp) * Added printf-formatter X8_F to printf u8_t as hex * The heap now may be moved to user-defined memory by defining LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address * added autoip_set_struct() and dhcp_set_struct() to let autoip and dhcp work with user-allocated structs instead of calling mem_malloc * Added const char* name to mem- and memp-stats for easier debugging. * Calculate the TCP/UDP checksum while copying to only fetch data once: Define LWIP_CHKSUM_COPY to a memcpy-like function that returns the checksum * Added SO_REUSE_RXTOALL to pass received UDP broadcast/multicast packets to more than one pcb. * Changed the semantics of ARP_QUEUEING==0: ARP_QUEUEING now cannot be turned off any more, if this is set to 0, only one packet (the most recent one) is queued (like demanded by RFC 1122). ++ Major bugfixes/improvements * Implemented tcp_shutdown() to only shut down one end of a connection * Implemented shutdown() at socket- and netconn-level * Added errorset support to select() + improved select speed overhead * Merged pppd to v2.3.11 (including some backported bugfixes from 2.4.x) * Added timer implementation for NO_SYS==1 (may be disabled with NO_SYS_NO_TIMERS==1 * Use macros defined in ip_addr.h to work with IP addresses * Implemented many nonblocking socket/netconn functions * Fixed ARP input processing: only add a new entry if a request was directed as us * mem_realloc() to mem_trim() to prevent confusion with realloc() * Some improvements for AutoIP (don't route/forward link-local addresses, don't break existing connections when assigning a routable address) * Correctly handle remote side overrunning our rcv_wnd in ooseq case * Removed packing from ip_addr_t, the packed version is now only used in protocol headers * Corrected PBUF_POOL_BUFSIZE for ports where ETH_PAD_SIZE > 0 * Added support for static ARP table entries (STABLE-1.3.2) * initial version of this file ================================================ FILE: Huawei_LiteOS/components/net/lwip/lwip-2.0.3/doc/FILES ================================================ doxygen/ - Configuration files and scripts to create the lwIP doxygen source documentation (found at http://www.nongnu.org/lwip/) savannah.txt - How to obtain the current development source code. contrib.txt - How to contribute to lwIP as a developer. rawapi.txt - The documentation for the core API of lwIP. Also provides an overview about the other APIs and multithreading. sys_arch.txt - The documentation for a system abstraction layer of lwIP. ppp.txt - Documentation of the PPP interface for lwIP. ================================================ FILE: Huawei_LiteOS/components/net/lwip/lwip-2.0.3/doc/NO_SYS_SampleCode.c ================================================ void eth_mac_irq() { /* Service MAC IRQ here */ /* Allocate pbuf from pool (avoid using heap in interrupts) */ struct pbuf* p = pbuf_alloc(PBUF_RAW, eth_data_count, PBUF_POOL); if(p != NULL) { /* Copy ethernet frame into pbuf */ pbuf_take(p, eth_data, eth_data_count); /* Put in a queue which is processed in main loop */ if(!queue_try_put(&queue, p)) { /* queue is full -> packet loss */ pbuf_free(p); } } } static err_t netif_output(struct netif *netif, struct pbuf *p) { LINK_STATS_INC(link.xmit); /* Update SNMP stats (only if you use SNMP) */ MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p->tot_len); int unicast = ((p->payload[0] & 0x01) == 0); if (unicast) { MIB2_STATS_NETIF_INC(netif, ifoutucastpkts); } else { MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts); } lock_interrupts(); pbuf_copy_partial(p, mac_send_buffer, p->tot_len, 0); /* Start MAC transmit here */ unlock_interrupts(); return ERR_OK; } static void netif_status_callback(struct netif *netif) { printf("netif status changed %s\n", ip4addr_ntoa(netif_ip4_addr(netif))); } static err_t netif_init(struct netif *netif) { netif->linkoutput = netif_output; netif->output = etharp_output; netif->output_ip6 = ethip6_output; netif->mtu = ETHERNET_MTU; netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP | NETIF_FLAG_MLD6; MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, 100000000); SMEMCPY(netif->hwaddr, your_mac_address_goes_here, sizeof(netif->hwaddr)); netif->hwaddr_len = sizeof(netif->hwaddr); return ERR_OK; } void main(void) { struct netif netif; lwip_init(); netif_add(&netif, IP4_ADDR_ANY, IP4_ADDR_ANY, IP4_ADDR_ANY, NULL, netif_init, netif_input); netif.name[0] = 'e'; netif.name[1] = '0'; netif_create_ip6_linklocal_address(&netif, 1); netif.ip6_autoconfig_enabled = 1; netif_set_status_callback(&netif, netif_status_callback); netif_set_default(&netif); netif_set_up(&netif); /* Start DHCP and HTTPD */ dhcp_start(&netif ); httpd_init(); while(1) { /* Check link state, e.g. via MDIO communication with PHY */ if(link_state_changed()) { if(link_is_up()) { netif_set_link_up(&netif); } else { netif_set_link_down(&netif); } } /* Check for received frames, feed them to lwIP */ lock_interrupts(); struct pbuf* p = queue_try_get(&queue); unlock_interrupts(); if(p != NULL) { LINK_STATS_INC(link.recv); /* Update SNMP stats (only if you use SNMP) */ MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len); int unicast = ((p->payload[0] & 0x01) == 0); if (unicast) { MIB2_STATS_NETIF_INC(netif, ifinucastpkts); } else { MIB2_STATS_NETIF_INC(netif, ifinnucastpkts); } if(netif.input(p, &netif) != ERR_OK) { pbuf_free(p); } } /* Cyclic lwIP timers check */ sys_check_timeouts(); /* your application goes here */ } } ================================================ FILE: Huawei_LiteOS/components/net/lwip/lwip-2.0.3/doc/contrib.txt ================================================ 1 Introduction This document describes some guidelines for people participating in lwIP development. 2 How to contribute to lwIP Here is a short list of suggestions to anybody working with lwIP and trying to contribute bug reports, fixes, enhancements, platform ports etc. First of all as you may already know lwIP is a volunteer project so feedback to fixes or questions might often come late. Hopefully the bug and patch tracking features of Savannah help us not lose users' input. 2.1 Source code style: 1. do not use tabs. 2. indentation is two spaces per level (i.e. per tab). 3. end debug messages with a trailing newline (\n). 4. one space between keyword and opening bracket. 5. no space between function and opening bracket. 6. one space and no newline before opening curly braces of a block. 7. closing curly brace on a single line. 8. spaces surrounding assignment and comparisons. 9. don't initialize static and/or global variables to zero, the compiler takes care of that. 10. use current source code style as further reference. 2.2 Source code documentation style: 1. JavaDoc compliant and Doxygen compatible. 2. Function documentation above functions in .c files, not .h files. (This forces you to synchronize documentation and implementation.) 3. Use current documentation style as further reference. 2.3 Bug reports and patches: 1. Make sure you are reporting bugs or send patches against the latest sources. (From the latest release and/or the current Git sources.) 2. If you think you found a bug make sure it's not already filed in the bugtracker at Savannah. 3. If you have a fix put the patch on Savannah. If it is a patch that affects both core and arch specific stuff please separate them so that the core can be applied separately while leaving the other patch 'open'. The preferred way is to NOT touch archs you can't test and let maintainers take care of them. This is a good way to see if they are used at all - the same goes for unix netifs except tapif. 4. Do not file a bug and post a fix to it to the patch area. Either a bug report or a patch will be enough. If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area. 5. Patches should be specific to a single change or to related changes. Do not mix bugfixes with spelling and other trivial fixes unless the bugfix is trivial too. Do not reorganize code and rename identifiers in the same patch you change behaviour if not necessary. A patch is easier to read and understand if it's to the point and short than if it's not to the point and long :) so the chances for it to be applied are greater. 2.4 Platform porters: 1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and you think it could benefit others[1] you might want discuss this on the mailing list. You can also ask for Git access to submit and maintain your port in the contrib Git module. ================================================ FILE: Huawei_LiteOS/components/net/lwip/lwip-2.0.3/doc/doxygen/generate.bat ================================================ doxygen lwip.Doxyfile ================================================ FILE: Huawei_LiteOS/components/net/lwip/lwip-2.0.3/doc/doxygen/generate.sh ================================================ #!/bin/sh doxygen lwip.Doxyfile ================================================ FILE: Huawei_LiteOS/components/net/lwip/lwip-2.0.3/doc/doxygen/lwip.Doxyfile ================================================ # Doxyfile 1.8.11 # This file describes the settings to be used by the documentation system # doxygen (www.doxygen.org) for a project. # # All text after a double hash (##) is considered a comment and is placed in # front of the TAG it is preceding. # # All text after a single hash (#) is considered a comment and will be ignored. # The format is: # TAG = value [value, ...] # For lists, items can also be appended using: # TAG += value [value, ...] # Values that contain spaces should be placed between quotes (\" \"). #--------------------------------------------------------------------------- # Project related configuration options #--------------------------------------------------------------------------- # This tag specifies the encoding used for all characters in the config file # that follow. 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INHERIT_DOCS = YES # If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new # page for each member. If set to NO, the documentation of a member will be part # of the file/class/namespace that contains it. # The default value is: NO. SEPARATE_MEMBER_PAGES = NO # The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen # uses this value to replace tabs by spaces in code fragments. # Minimum value: 1, maximum value: 16, default value: 4. TAB_SIZE = 8 # This tag can be used to specify a number of aliases that act as commands in # the documentation. An alias has the form: # name=value # For example adding # "sideeffect=@par Side Effects:\n" # will allow you to put the command \sideeffect (or @sideeffect) in the # documentation, which will result in a user-defined paragraph with heading # "Side Effects:". You can put \n's in the value part of an alias to insert # newlines. ALIASES = # This tag can be used to specify a number of word-keyword mappings (TCL only). # A mapping has the form "name=value". For example adding "class=itcl::class" # will allow you to use the command class in the itcl::class meaning. TCL_SUBST = # Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources # only. Doxygen will then generate output that is more tailored for C. For # instance, some of the names that are used will be different. The list of all # members will be omitted, etc. # The default value is: NO. OPTIMIZE_OUTPUT_FOR_C = YES # Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or # Python sources only. Doxygen will then generate output that is more tailored # for that language. For instance, namespaces will be presented as packages, # qualified scopes will look different, etc. # The default value is: NO. OPTIMIZE_OUTPUT_JAVA = NO # Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran # sources. Doxygen will then generate output that is tailored for Fortran. # The default value is: NO. OPTIMIZE_FOR_FORTRAN = NO # Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL # sources. Doxygen will then generate output that is tailored for VHDL. # The default value is: NO. OPTIMIZE_OUTPUT_VHDL = NO # Doxygen selects the parser to use depending on the extension of the files it # parses. With this tag you can assign which parser to use for a given # extension. Doxygen has a built-in mapping, but you can override or extend it # using this tag. The format is ext=language, where ext is a file extension, and # language is one of the parsers supported by doxygen: IDL, Java, Javascript, # C#, C, C++, D, PHP, Objective-C, Python, Fortran (fixed format Fortran: # FortranFixed, free formatted Fortran: FortranFree, unknown formatted Fortran: # Fortran. In the later case the parser tries to guess whether the code is fixed # or free formatted code, this is the default for Fortran type files), VHDL. For # instance to make doxygen treat .inc files as Fortran files (default is PHP), # and .f files as C (default is Fortran), use: inc=Fortran f=C. # # Note: For files without extension you can use no_extension as a placeholder. # # Note that for custom extensions you also need to set FILE_PATTERNS otherwise # the files are not read by doxygen. EXTENSION_MAPPING = # If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments # according to the Markdown format, which allows for more readable # documentation. See http://daringfireball.net/projects/markdown/ for details. # The output of markdown processing is further processed by doxygen, so you can # mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in # case of backward compatibilities issues. # The default value is: YES. MARKDOWN_SUPPORT = YES # When enabled doxygen tries to link words that correspond to documented # classes, or namespaces to their corresponding documentation. Such a link can # be prevented in individual cases by putting a % sign in front of the word or # globally by setting AUTOLINK_SUPPORT to NO. # The default value is: YES. AUTOLINK_SUPPORT = YES # If you use STL classes (i.e. std::string, std::vector, etc.) but do not want # to include (a tag file for) the STL sources as input, then you should set this # tag to YES in order to let doxygen match functions declarations and # definitions whose arguments contain STL classes (e.g. func(std::string); # versus func(std::string) {}). This also make the inheritance and collaboration # diagrams that involve STL classes more complete and accurate. # The default value is: NO. BUILTIN_STL_SUPPORT = NO # If you use Microsoft's C++/CLI language, you should set this option to YES to # enable parsing support. # The default value is: NO. CPP_CLI_SUPPORT = NO # Set the SIP_SUPPORT tag to YES if your project consists of sip (see: # http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen # will parse them like normal C++ but will assume all classes use public instead # of private inheritance when no explicit protection keyword is present. # The default value is: NO. SIP_SUPPORT = NO # For Microsoft's IDL there are propget and propput attributes to indicate # getter and setter methods for a property. Setting this option to YES will make # doxygen to replace the get and set methods by a property in the documentation. # This will only work if the methods are indeed getting or setting a simple # type. If this is not the case, or you want to show the methods anyway, you # should set this option to NO. # The default value is: YES. IDL_PROPERTY_SUPPORT = YES # If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC # tag is set to YES then doxygen will reuse the documentation of the first # member in the group (if any) for the other members of the group. By default # all members of a group must be documented explicitly. # The default value is: NO. DISTRIBUTE_GROUP_DOC = NO # If one adds a struct or class to a group and this option is enabled, then also # any nested class or struct is added to the same group. By default this option # is disabled and one has to add nested compounds explicitly via \ingroup. # The default value is: NO. GROUP_NESTED_COMPOUNDS = NO # Set the SUBGROUPING tag to YES to allow class member groups of the same type # (for instance a group of public functions) to be put as a subgroup of that # type (e.g. under the Public Functions section). Set it to NO to prevent # subgrouping. Alternatively, this can be done per class using the # \nosubgrouping command. # The default value is: YES. SUBGROUPING = YES # When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions # are shown inside the group in which they are included (e.g. using \ingroup) # instead of on a separate page (for HTML and Man pages) or section (for LaTeX # and RTF). # # Note that this feature does not work in combination with # SEPARATE_MEMBER_PAGES. # The default value is: NO. INLINE_GROUPED_CLASSES = NO # When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions # with only public data fields or simple typedef fields will be shown inline in # the documentation of the scope in which they are defined (i.e. file, # namespace, or group documentation), provided this scope is documented. If set # to NO, structs, classes, and unions are shown on a separate page (for HTML and # Man pages) or section (for LaTeX and RTF). # The default value is: NO. INLINE_SIMPLE_STRUCTS = NO # When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or # enum is documented as struct, union, or enum with the name of the typedef. So # typedef struct TypeS {} TypeT, will appear in the documentation as a struct # with name TypeT. When disabled the typedef will appear as a member of a file, # namespace, or class. And the struct will be named TypeS. This can typically be # useful for C code in case the coding convention dictates that all compound # types are typedef'ed and only the typedef is referenced, never the tag name. # The default value is: NO. TYPEDEF_HIDES_STRUCT = NO # The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This # cache is used to resolve symbols given their name and scope. Since this can be # an expensive process and often the same symbol appears multiple times in the # code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small # doxygen will become slower. If the cache is too large, memory is wasted. The # cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range # is 0..9, the default is 0, corresponding to a cache size of 2^16=65536 # symbols. At the end of a run doxygen will report the cache usage and suggest # the optimal cache size from a speed point of view. # Minimum value: 0, maximum value: 9, default value: 0. LOOKUP_CACHE_SIZE = 0 #--------------------------------------------------------------------------- # Build related configuration options #--------------------------------------------------------------------------- # If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in # documentation are documented, even if no documentation was available. Private # class members and static file members will be hidden unless the # EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES. # Note: This will also disable the warnings about undocumented members that are # normally produced when WARNINGS is set to YES. # The default value is: NO. EXTRACT_ALL = NO # If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will # be included in the documentation. # The default value is: NO. EXTRACT_PRIVATE = NO # If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal # scope will be included in the documentation. # The default value is: NO. EXTRACT_PACKAGE = NO # If the EXTRACT_STATIC tag is set to YES, all static members of a file will be # included in the documentation. # The default value is: NO. EXTRACT_STATIC = NO # If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined # locally in source files will be included in the documentation. If set to NO, # only classes defined in header files are included. Does not have any effect # for Java sources. # The default value is: YES. EXTRACT_LOCAL_CLASSES = YES # This flag is only useful for Objective-C code. If set to YES, local methods, # which are defined in the implementation section but not in the interface are # included in the documentation. If set to NO, only methods in the interface are # included. # The default value is: NO. EXTRACT_LOCAL_METHODS = NO # If this flag is set to YES, the members of anonymous namespaces will be # extracted and appear in the documentation as a namespace called # 'anonymous_namespace{file}', where file will be replaced with the base name of # the file that contains the anonymous namespace. By default anonymous namespace # are hidden. # The default value is: NO. EXTRACT_ANON_NSPACES = NO # If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all # undocumented members inside documented classes or files. If set to NO these # members will be included in the various overviews, but no documentation # section is generated. This option has no effect if EXTRACT_ALL is enabled. # The default value is: NO. HIDE_UNDOC_MEMBERS = YES # If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all # undocumented classes that are normally visible in the class hierarchy. If set # to NO, these classes will be included in the various overviews. This option # has no effect if EXTRACT_ALL is enabled. # The default value is: NO. HIDE_UNDOC_CLASSES = YES # If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend # (class|struct|union) declarations. If set to NO, these declarations will be # included in the documentation. # The default value is: NO. HIDE_FRIEND_COMPOUNDS = NO # If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any # documentation blocks found inside the body of a function. If set to NO, these # blocks will be appended to the function's detailed documentation block. # The default value is: NO. HIDE_IN_BODY_DOCS = NO # The INTERNAL_DOCS tag determines if documentation that is typed after a # \internal command is included. If the tag is set to NO then the documentation # will be excluded. Set it to YES to include the internal documentation. # The default value is: NO. INTERNAL_DOCS = NO # If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file # names in lower-case letters. If set to YES, upper-case letters are also # allowed. This is useful if you have classes or files whose names only differ # in case and if your file system supports case sensitive file names. Windows # and Mac users are advised to set this option to NO. # The default value is: system dependent. CASE_SENSE_NAMES = NO # If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with # their full class and namespace scopes in the documentation. If set to YES, the # scope will be hidden. # The default value is: NO. HIDE_SCOPE_NAMES = NO # If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will # append additional text to a page's title, such as Class Reference. If set to # YES the compound reference will be hidden. # The default value is: NO. HIDE_COMPOUND_REFERENCE= NO # If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of # the files that are included by a file in the documentation of that file. # The default value is: YES. SHOW_INCLUDE_FILES = YES # If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each # grouped member an include statement to the documentation, telling the reader # which file to include in order to use the member. # The default value is: NO. SHOW_GROUPED_MEMB_INC = NO # If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include # files with double quotes in the documentation rather than with sharp brackets. # The default value is: NO. FORCE_LOCAL_INCLUDES = NO # If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the # documentation for inline members. # The default value is: YES. INLINE_INFO = YES # If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the # (detailed) documentation of file and class members alphabetically by member # name. If set to NO, the members will appear in declaration order. # The default value is: YES. SORT_MEMBER_DOCS = YES # If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief # descriptions of file, namespace and class members alphabetically by member # name. If set to NO, the members will appear in declaration order. Note that # this will also influence the order of the classes in the class list. # The default value is: NO. SORT_BRIEF_DOCS = NO # If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the # (brief and detailed) documentation of class members so that constructors and # destructors are listed first. If set to NO the constructors will appear in the # respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS. # Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief # member documentation. # Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting # detailed member documentation. # The default value is: NO. SORT_MEMBERS_CTORS_1ST = NO # If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy # of group names into alphabetical order. If set to NO the group names will # appear in their defined order. # The default value is: NO. SORT_GROUP_NAMES = NO # If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by # fully-qualified names, including namespaces. If set to NO, the class list will # be sorted only by class name, not including the namespace part. # Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. # Note: This option applies only to the class list, not to the alphabetical # list. # The default value is: NO. SORT_BY_SCOPE_NAME = NO # If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper # type resolution of all parameters of a function it will reject a match between # the prototype and the implementation of a member function even if there is # only one candidate or it is obvious which candidate to choose by doing a # simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still # accept a match between prototype and implementation in such cases. # The default value is: NO. STRICT_PROTO_MATCHING = NO # The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo # list. This list is created by putting \todo commands in the documentation. # The default value is: YES. GENERATE_TODOLIST = NO # The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test # list. This list is created by putting \test commands in the documentation. # The default value is: YES. GENERATE_TESTLIST = YES # The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug # list. This list is created by putting \bug commands in the documentation. # The default value is: YES. GENERATE_BUGLIST = YES # The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO) # the deprecated list. This list is created by putting \deprecated commands in # the documentation. # The default value is: YES. GENERATE_DEPRECATEDLIST= YES # The ENABLED_SECTIONS tag can be used to enable conditional documentation # sections, marked by \if ... \endif and \cond # ... \endcond blocks. ENABLED_SECTIONS = # The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the # initial value of a variable or macro / define can have for it to appear in the # documentation. If the initializer consists of more lines than specified here # it will be hidden. Use a value of 0 to hide initializers completely. The # appearance of the value of individual variables and macros / defines can be # controlled using \showinitializer or \hideinitializer command in the # documentation regardless of this setting. # Minimum value: 0, maximum value: 10000, default value: 30. MAX_INITIALIZER_LINES = 30 # Set the SHOW_USED_FILES tag to NO to disable the list of files generated at # the bottom of the documentation of classes and structs. If set to YES, the # list will mention the files that were used to generate the documentation. # The default value is: YES. SHOW_USED_FILES = YES # Set the SHOW_FILES tag to NO to disable the generation of the Files page. This # will remove the Files entry from the Quick Index and from the Folder Tree View # (if specified). # The default value is: YES. SHOW_FILES = YES # Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces # page. This will remove the Namespaces entry from the Quick Index and from the # Folder Tree View (if specified). # The default value is: YES. SHOW_NAMESPACES = YES # The FILE_VERSION_FILTER tag can be used to specify a program or script that # doxygen should invoke to get the current version for each file (typically from # the version control system). Doxygen will invoke the program by executing (via # popen()) the command command input-file, where command is the value of the # FILE_VERSION_FILTER tag, and input-file is the name of an input file provided # by doxygen. Whatever the program writes to standard output is used as the file # version. For an example see the documentation. FILE_VERSION_FILTER = # The LAYOUT_FILE tag can be used to specify a layout file which will be parsed # by doxygen. The layout file controls the global structure of the generated # output files in an output format independent way. To create the layout file # that represents doxygen's defaults, run doxygen with the -l option. You can # optionally specify a file name after the option, if omitted DoxygenLayout.xml # will be used as the name of the layout file. # # Note that if you run doxygen from a directory containing a file called # DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE # tag is left empty. LAYOUT_FILE = # The CITE_BIB_FILES tag can be used to specify one or more bib files containing # the reference definitions. This must be a list of .bib files. The .bib # extension is automatically appended if omitted. This requires the bibtex tool # to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info. # For LaTeX the style of the bibliography can be controlled using # LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the # search path. See also \cite for info how to create references. CITE_BIB_FILES = #--------------------------------------------------------------------------- # Configuration options related to warning and progress messages #--------------------------------------------------------------------------- # The QUIET tag can be used to turn on/off the messages that are generated to # standard output by doxygen. If QUIET is set to YES this implies that the # messages are off. # The default value is: NO. QUIET = NO # The WARNINGS tag can be used to turn on/off the warning messages that are # generated to standard error (stderr) by doxygen. If WARNINGS is set to YES # this implies that the warnings are on. # # Tip: Turn warnings on while writing the documentation. # The default value is: YES. WARNINGS = YES # If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate # warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag # will automatically be disabled. # The default value is: YES. WARN_IF_UNDOCUMENTED = YES # If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for # potential errors in the documentation, such as not documenting some parameters # in a documented function, or documenting parameters that don't exist or using # markup commands wrongly. # The default value is: YES. WARN_IF_DOC_ERROR = YES # This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that # are documented, but have no documentation for their parameters or return # value. If set to NO, doxygen will only warn about wrong or incomplete # parameter documentation, but not about the absence of documentation. # The default value is: NO. WARN_NO_PARAMDOC = NO # If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when # a warning is encountered. # The default value is: NO. WARN_AS_ERROR = NO # The WARN_FORMAT tag determines the format of the warning messages that doxygen # can produce. The string should contain the $file, $line, and $text tags, which # will be replaced by the file and line number from which the warning originated # and the warning text. Optionally the format may contain $version, which will # be replaced by the version of the file (if it could be obtained via # FILE_VERSION_FILTER) # The default value is: $file:$line: $text. WARN_FORMAT = "$file:$line: $text " # The WARN_LOGFILE tag can be used to specify a file to which warning and error # messages should be written. If left blank the output is written to standard # error (stderr). WARN_LOGFILE = #--------------------------------------------------------------------------- # Configuration options related to the input files #--------------------------------------------------------------------------- # The INPUT tag is used to specify the files and/or directories that contain # documented source files. You may enter file names like myfile.cpp or # directories like /usr/src/myproject. Separate the files or directories with # spaces. See also FILE_PATTERNS and EXTENSION_MAPPING # Note: If this tag is empty the current directory is searched. INPUT = main_page.h ../../src # This tag can be used to specify the character encoding of the source files # that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses # libiconv (or the iconv built into libc) for the transcoding. See the libiconv # documentation (see: http://www.gnu.org/software/libiconv) for the list of # possible encodings. # The default value is: UTF-8. INPUT_ENCODING = UTF-8 # If the value of the INPUT tag contains directories, you can use the # FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and # *.h) to filter out the source-files in the directories. # # Note that for custom extensions or not directly supported extensions you also # need to set EXTENSION_MAPPING for the extension otherwise the files are not # read by doxygen. # # If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp, # *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, # *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, # *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f, *.for, *.tcl, # *.vhd, *.vhdl, *.ucf, *.qsf, *.as and *.js. FILE_PATTERNS = *.c \ *.cc \ *.cxx \ *.cpp \ *.c++ \ *.java \ *.ii \ *.ixx \ *.ipp \ *.i++ \ *.inl \ *.h \ *.hh \ *.hxx \ *.hpp \ *.h++ \ *.idl \ *.odl \ *.inc \ *.m \ *.mm \ *.dox # The RECURSIVE tag can be used to specify whether or not subdirectories should # be searched for input files as well. # The default value is: NO. RECURSIVE = YES # The EXCLUDE tag can be used to specify files and/or directories that should be # excluded from the INPUT source files. This way you can easily exclude a # subdirectory from a directory tree whose root is specified with the INPUT tag. # # Note that relative paths are relative to the directory from which doxygen is # run. EXCLUDE = ../../src/include/netif/ppp/polarssl # The EXCLUDE_SYMLINKS tag can be used to select whether or not files or # directories that are symbolic links (a Unix file system feature) are excluded # from the input. # The default value is: NO. EXCLUDE_SYMLINKS = NO # If the value of the INPUT tag contains directories, you can use the # EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude # certain files from those directories. # # Note that the wildcards are matched against the file with absolute path, so to # exclude all test directories for example use the pattern */test/* EXCLUDE_PATTERNS = # The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names # (namespaces, classes, functions, etc.) that should be excluded from the # output. The symbol name can be a fully qualified name, a word, or if the # wildcard * is used, a substring. Examples: ANamespace, AClass, # AClass::ANamespace, ANamespace::*Test # # Note that the wildcards are matched against the file with absolute path, so to # exclude all test directories use the pattern */test/* EXCLUDE_SYMBOLS = # The EXAMPLE_PATH tag can be used to specify one or more files or directories # that contain example code fragments that are included (see the \include # command). EXAMPLE_PATH = ../ ../../ # If the value of the EXAMPLE_PATH tag contains directories, you can use the # EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and # *.h) to filter out the source-files in the directories. If left blank all # files are included. EXAMPLE_PATTERNS = * # If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be # searched for input files to be used with the \include or \dontinclude commands # irrespective of the value of the RECURSIVE tag. # The default value is: NO. EXAMPLE_RECURSIVE = NO # The IMAGE_PATH tag can be used to specify one or more files or directories # that contain images that are to be included in the documentation (see the # \image command). IMAGE_PATH = # The INPUT_FILTER tag can be used to specify a program that doxygen should # invoke to filter for each input file. Doxygen will invoke the filter program # by executing (via popen()) the command: # # # # where is the value of the INPUT_FILTER tag, and is the # name of an input file. Doxygen will then use the output that the filter # program writes to standard output. If FILTER_PATTERNS is specified, this tag # will be ignored. # # Note that the filter must not add or remove lines; it is applied before the # code is scanned, but not when the output code is generated. If lines are added # or removed, the anchors will not be placed correctly. # # Note that for custom extensions or not directly supported extensions you also # need to set EXTENSION_MAPPING for the extension otherwise the files are not # properly processed by doxygen. INPUT_FILTER = # The FILTER_PATTERNS tag can be used to specify filters on a per file pattern # basis. Doxygen will compare the file name with each pattern and apply the # filter if there is a match. The filters are a list of the form: pattern=filter # (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how # filters are used. If the FILTER_PATTERNS tag is empty or if none of the # patterns match the file name, INPUT_FILTER is applied. # # Note that for custom extensions or not directly supported extensions you also # need to set EXTENSION_MAPPING for the extension otherwise the files are not # properly processed by doxygen. FILTER_PATTERNS = # If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using # INPUT_FILTER) will also be used to filter the input files that are used for # producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES). # The default value is: NO. FILTER_SOURCE_FILES = NO # The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file # pattern. A pattern will override the setting for FILTER_PATTERN (if any) and # it is also possible to disable source filtering for a specific pattern using # *.ext= (so without naming a filter). # This tag requires that the tag FILTER_SOURCE_FILES is set to YES. FILTER_SOURCE_PATTERNS = # If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that # is part of the input, its contents will be placed on the main page # (index.html). This can be useful if you have a project on for instance GitHub # and want to reuse the introduction page also for the doxygen output. USE_MDFILE_AS_MAINPAGE = main_page.h #--------------------------------------------------------------------------- # Configuration options related to source browsing #--------------------------------------------------------------------------- # If the SOURCE_BROWSER tag is set to YES then a list of source files will be # generated. Documented entities will be cross-referenced with these sources. # # Note: To get rid of all source code in the generated output, make sure that # also VERBATIM_HEADERS is set to NO. # The default value is: NO. SOURCE_BROWSER = NO # Setting the INLINE_SOURCES tag to YES will include the body of functions, # classes and enums directly into the documentation. # The default value is: NO. INLINE_SOURCES = NO # Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any # special comment blocks from generated source code fragments. Normal C, C++ and # Fortran comments will always remain visible. # The default value is: YES. STRIP_CODE_COMMENTS = YES # If the REFERENCED_BY_RELATION tag is set to YES then for each documented # function all documented functions referencing it will be listed. # The default value is: NO. REFERENCED_BY_RELATION = NO # If the REFERENCES_RELATION tag is set to YES then for each documented function # all documented entities called/used by that function will be listed. # The default value is: NO. REFERENCES_RELATION = NO # If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set # to YES then the hyperlinks from functions in REFERENCES_RELATION and # REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will # link to the documentation. # The default value is: YES. REFERENCES_LINK_SOURCE = YES # If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the # source code will show a tooltip with additional information such as prototype, # brief description and links to the definition and documentation. Since this # will make the HTML file larger and loading of large files a bit slower, you # can opt to disable this feature. # The default value is: YES. # This tag requires that the tag SOURCE_BROWSER is set to YES. SOURCE_TOOLTIPS = YES # If the USE_HTAGS tag is set to YES then the references to source code will # point to the HTML generated by the htags(1) tool instead of doxygen built-in # source browser. The htags tool is part of GNU's global source tagging system # (see http://www.gnu.org/software/global/global.html). You will need version # 4.8.6 or higher. # # To use it do the following: # - Install the latest version of global # - Enable SOURCE_BROWSER and USE_HTAGS in the config file # - Make sure the INPUT points to the root of the source tree # - Run doxygen as normal # # Doxygen will invoke htags (and that will in turn invoke gtags), so these # tools must be available from the command line (i.e. in the search path). # # The result: instead of the source browser generated by doxygen, the links to # source code will now point to the output of htags. # The default value is: NO. # This tag requires that the tag SOURCE_BROWSER is set to YES. USE_HTAGS = NO # If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a # verbatim copy of the header file for each class for which an include is # specified. Set to NO to disable this. # See also: Section \class. # The default value is: YES. VERBATIM_HEADERS = NO # If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the # clang parser (see: http://clang.llvm.org/) for more accurate parsing at the # cost of reduced performance. This can be particularly helpful with template # rich C++ code for which doxygen's built-in parser lacks the necessary type # information. # Note: The availability of this option depends on whether or not doxygen was # generated with the -Duse-libclang=ON option for CMake. # The default value is: NO. CLANG_ASSISTED_PARSING = NO # If clang assisted parsing is enabled you can provide the compiler with command # line options that you would normally use when invoking the compiler. Note that # the include paths will already be set by doxygen for the files and directories # specified with INPUT and INCLUDE_PATH. # This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES. CLANG_OPTIONS = #--------------------------------------------------------------------------- # Configuration options related to the alphabetical class index #--------------------------------------------------------------------------- # If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all # compounds will be generated. Enable this if the project contains a lot of # classes, structs, unions or interfaces. # The default value is: YES. ALPHABETICAL_INDEX = NO # The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in # which the alphabetical index list will be split. # Minimum value: 1, maximum value: 20, default value: 5. # This tag requires that the tag ALPHABETICAL_INDEX is set to YES. COLS_IN_ALPHA_INDEX = 5 # In case all classes in a project start with a common prefix, all classes will # be put under the same header in the alphabetical index. The IGNORE_PREFIX tag # can be used to specify a prefix (or a list of prefixes) that should be ignored # while generating the index headers. # This tag requires that the tag ALPHABETICAL_INDEX is set to YES. IGNORE_PREFIX = #--------------------------------------------------------------------------- # Configuration options related to the HTML output #--------------------------------------------------------------------------- # If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output # The default value is: YES. GENERATE_HTML = YES # The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a # relative path is entered the value of OUTPUT_DIRECTORY will be put in front of # it. # The default directory is: html. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_OUTPUT = html # The HTML_FILE_EXTENSION tag can be used to specify the file extension for each # generated HTML page (for example: .htm, .php, .asp). # The default value is: .html. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_FILE_EXTENSION = .html # The HTML_HEADER tag can be used to specify a user-defined HTML header file for # each generated HTML page. If the tag is left blank doxygen will generate a # standard header. # # To get valid HTML the header file that includes any scripts and style sheets # that doxygen needs, which is dependent on the configuration options used (e.g. # the setting GENERATE_TREEVIEW). It is highly recommended to start with a # default header using # doxygen -w html new_header.html new_footer.html new_stylesheet.css # YourConfigFile # and then modify the file new_header.html. See also section "Doxygen usage" # for information on how to generate the default header that doxygen normally # uses. # Note: The header is subject to change so you typically have to regenerate the # default header when upgrading to a newer version of doxygen. For a description # of the possible markers and block names see the documentation. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_HEADER = # The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each # generated HTML page. If the tag is left blank doxygen will generate a standard # footer. See HTML_HEADER for more information on how to generate a default # footer and what special commands can be used inside the footer. See also # section "Doxygen usage" for information on how to generate the default footer # that doxygen normally uses. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_FOOTER = # The HTML_STYLESHEET tag can be used to specify a user-defined cascading style # sheet that is used by each HTML page. It can be used to fine-tune the look of # the HTML output. If left blank doxygen will generate a default style sheet. # See also section "Doxygen usage" for information on how to generate the style # sheet that doxygen normally uses. # Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as # it is more robust and this tag (HTML_STYLESHEET) will in the future become # obsolete. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_STYLESHEET = # The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined # cascading style sheets that are included after the standard style sheets # created by doxygen. Using this option one can overrule certain style aspects. # This is preferred over using HTML_STYLESHEET since it does not replace the # standard style sheet and is therefore more robust against future updates. # Doxygen will copy the style sheet files to the output directory. # Note: The order of the extra style sheet files is of importance (e.g. the last # style sheet in the list overrules the setting of the previous ones in the # list). For an example see the documentation. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_EXTRA_STYLESHEET = # The HTML_EXTRA_FILES tag can be used to specify one or more extra images or # other source files which should be copied to the HTML output directory. Note # that these files will be copied to the base HTML output directory. Use the # $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these # files. In the HTML_STYLESHEET file, use the file name only. Also note that the # files will be copied as-is; there are no commands or markers available. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_EXTRA_FILES = # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen # will adjust the colors in the style sheet and background images according to # this color. Hue is specified as an angle on a colorwheel, see # http://en.wikipedia.org/wiki/Hue for more information. For instance the value # 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300 # purple, and 360 is red again. # Minimum value: 0, maximum value: 359, default value: 220. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_COLORSTYLE_HUE = 220 # The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors # in the HTML output. For a value of 0 the output will use grayscales only. A # value of 255 will produce the most vivid colors. # Minimum value: 0, maximum value: 255, default value: 100. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_COLORSTYLE_SAT = 100 # The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the # luminance component of the colors in the HTML output. Values below 100 # gradually make the output lighter, whereas values above 100 make the output # darker. The value divided by 100 is the actual gamma applied, so 80 represents # a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not # change the gamma. # Minimum value: 40, maximum value: 240, default value: 80. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_COLORSTYLE_GAMMA = 80 # If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML # page will contain the date and time when the page was generated. Setting this # to YES can help to show when doxygen was last run and thus if the # documentation is up to date. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_TIMESTAMP = NO # If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML # documentation will contain sections that can be hidden and shown after the # page has loaded. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_DYNAMIC_SECTIONS = NO # With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries # shown in the various tree structured indices initially; the user can expand # and collapse entries dynamically later on. Doxygen will expand the tree to # such a level that at most the specified number of entries are visible (unless # a fully collapsed tree already exceeds this amount). So setting the number of # entries 1 will produce a full collapsed tree by default. 0 is a special value # representing an infinite number of entries and will result in a full expanded # tree by default. # Minimum value: 0, maximum value: 9999, default value: 100. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_INDEX_NUM_ENTRIES = 100 # If the GENERATE_DOCSET tag is set to YES, additional index files will be # generated that can be used as input for Apple's Xcode 3 integrated development # environment (see: http://developer.apple.com/tools/xcode/), introduced with # OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a # Makefile in the HTML output directory. Running make will produce the docset in # that directory and running make install will install the docset in # ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at # startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html # for more information. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. GENERATE_DOCSET = NO # This tag determines the name of the docset feed. A documentation feed provides # an umbrella under which multiple documentation sets from a single provider # (such as a company or product suite) can be grouped. # The default value is: Doxygen generated docs. # This tag requires that the tag GENERATE_DOCSET is set to YES. DOCSET_FEEDNAME = "Doxygen generated docs" # This tag specifies a string that should uniquely identify the documentation # set bundle. This should be a reverse domain-name style string, e.g. # com.mycompany.MyDocSet. Doxygen will append .docset to the name. # The default value is: org.doxygen.Project. # This tag requires that the tag GENERATE_DOCSET is set to YES. DOCSET_BUNDLE_ID = org.doxygen.Project # The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify # the documentation publisher. This should be a reverse domain-name style # string, e.g. com.mycompany.MyDocSet.documentation. # The default value is: org.doxygen.Publisher. # This tag requires that the tag GENERATE_DOCSET is set to YES. DOCSET_PUBLISHER_ID = org.doxygen.Publisher # The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher. # The default value is: Publisher. # This tag requires that the tag GENERATE_DOCSET is set to YES. DOCSET_PUBLISHER_NAME = Publisher # If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three # additional HTML index files: index.hhp, index.hhc, and index.hhk. The # index.hhp is a project file that can be read by Microsoft's HTML Help Workshop # (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on # Windows. # # The HTML Help Workshop contains a compiler that can convert all HTML output # generated by doxygen into a single compiled HTML file (.chm). Compiled HTML # files are now used as the Windows 98 help format, and will replace the old # Windows help format (.hlp) on all Windows platforms in the future. Compressed # HTML files also contain an index, a table of contents, and you can search for # words in the documentation. The HTML workshop also contains a viewer for # compressed HTML files. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. GENERATE_HTMLHELP = NO # The CHM_FILE tag can be used to specify the file name of the resulting .chm # file. You can add a path in front of the file if the result should not be # written to the html output directory. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. CHM_FILE = lwip.chm # The HHC_LOCATION tag can be used to specify the location (absolute path # including file name) of the HTML help compiler (hhc.exe). If non-empty, # doxygen will try to run the HTML help compiler on the generated index.hhp. # The file has to be specified with full path. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. HHC_LOCATION = # The GENERATE_CHI flag controls if a separate .chi index file is generated # (YES) or that it should be included in the master .chm file (NO). # The default value is: NO. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. GENERATE_CHI = NO # The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc) # and project file content. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. CHM_INDEX_ENCODING = # The BINARY_TOC flag controls whether a binary table of contents is generated # (YES) or a normal table of contents (NO) in the .chm file. Furthermore it # enables the Previous and Next buttons. # The default value is: NO. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. BINARY_TOC = NO # The TOC_EXPAND flag can be set to YES to add extra items for group members to # the table of contents of the HTML help documentation and to the tree view. # The default value is: NO. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. TOC_EXPAND = NO # If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and # QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that # can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help # (.qch) of the generated HTML documentation. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. GENERATE_QHP = NO # If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify # the file name of the resulting .qch file. The path specified is relative to # the HTML output folder. # This tag requires that the tag GENERATE_QHP is set to YES. QCH_FILE = # The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help # Project output. For more information please see Qt Help Project / Namespace # (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace). # The default value is: org.doxygen.Project. # This tag requires that the tag GENERATE_QHP is set to YES. QHP_NAMESPACE = org.doxygen.Project # The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt # Help Project output. For more information please see Qt Help Project / Virtual # Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual- # folders). # The default value is: doc. # This tag requires that the tag GENERATE_QHP is set to YES. QHP_VIRTUAL_FOLDER = doc # If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom # filter to add. For more information please see Qt Help Project / Custom # Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- # filters). # This tag requires that the tag GENERATE_QHP is set to YES. QHP_CUST_FILTER_NAME = # The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the # custom filter to add. For more information please see Qt Help Project / Custom # Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- # filters). # This tag requires that the tag GENERATE_QHP is set to YES. QHP_CUST_FILTER_ATTRS = # The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this # project's filter section matches. Qt Help Project / Filter Attributes (see: # http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes). # This tag requires that the tag GENERATE_QHP is set to YES. QHP_SECT_FILTER_ATTRS = # The QHG_LOCATION tag can be used to specify the location of Qt's # qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the # generated .qhp file. # This tag requires that the tag GENERATE_QHP is set to YES. QHG_LOCATION = # If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be # generated, together with the HTML files, they form an Eclipse help plugin. To # install this plugin and make it available under the help contents menu in # Eclipse, the contents of the directory containing the HTML and XML files needs # to be copied into the plugins directory of eclipse. The name of the directory # within the plugins directory should be the same as the ECLIPSE_DOC_ID value. # After copying Eclipse needs to be restarted before the help appears. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. GENERATE_ECLIPSEHELP = NO # A unique identifier for the Eclipse help plugin. When installing the plugin # the directory name containing the HTML and XML files should also have this # name. Each documentation set should have its own identifier. # The default value is: org.doxygen.Project. # This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES. ECLIPSE_DOC_ID = org.doxygen.Project # If you want full control over the layout of the generated HTML pages it might # be necessary to disable the index and replace it with your own. The # DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top # of each HTML page. A value of NO enables the index and the value YES disables # it. Since the tabs in the index contain the same information as the navigation # tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. DISABLE_INDEX = NO # The GENERATE_TREEVIEW tag is used to specify whether a tree-like index # structure should be generated to display hierarchical information. If the tag # value is set to YES, a side panel will be generated containing a tree-like # index structure (just like the one that is generated for HTML Help). For this # to work a browser that supports JavaScript, DHTML, CSS and frames is required # (i.e. any modern browser). Windows users are probably better off using the # HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can # further fine-tune the look of the index. As an example, the default style # sheet generated by doxygen has an example that shows how to put an image at # the root of the tree instead of the PROJECT_NAME. Since the tree basically has # the same information as the tab index, you could consider setting # DISABLE_INDEX to YES when enabling this option. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. GENERATE_TREEVIEW = YES # The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that # doxygen will group on one line in the generated HTML documentation. # # Note that a value of 0 will completely suppress the enum values from appearing # in the overview section. # Minimum value: 0, maximum value: 20, default value: 4. # This tag requires that the tag GENERATE_HTML is set to YES. ENUM_VALUES_PER_LINE = 4 # If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used # to set the initial width (in pixels) of the frame in which the tree is shown. # Minimum value: 0, maximum value: 1500, default value: 250. # This tag requires that the tag GENERATE_HTML is set to YES. TREEVIEW_WIDTH = 250 # If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to # external symbols imported via tag files in a separate window. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. EXT_LINKS_IN_WINDOW = NO # Use this tag to change the font size of LaTeX formulas included as images in # the HTML documentation. When you change the font size after a successful # doxygen run you need to manually remove any form_*.png images from the HTML # output directory to force them to be regenerated. # Minimum value: 8, maximum value: 50, default value: 10. # This tag requires that the tag GENERATE_HTML is set to YES. FORMULA_FONTSIZE = 10 # Use the FORMULA_TRANPARENT tag to determine whether or not the images # generated for formulas are transparent PNGs. Transparent PNGs are not # supported properly for IE 6.0, but are supported on all modern browsers. # # Note that when changing this option you need to delete any form_*.png files in # the HTML output directory before the changes have effect. # The default value is: YES. # This tag requires that the tag GENERATE_HTML is set to YES. FORMULA_TRANSPARENT = YES # Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see # http://www.mathjax.org) which uses client side Javascript for the rendering # instead of using pre-rendered bitmaps. Use this if you do not have LaTeX # installed or if you want to formulas look prettier in the HTML output. When # enabled you may also need to install MathJax separately and configure the path # to it using the MATHJAX_RELPATH option. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. USE_MATHJAX = NO # When MathJax is enabled you can set the default output format to be used for # the MathJax output. See the MathJax site (see: # http://docs.mathjax.org/en/latest/output.html) for more details. # Possible values are: HTML-CSS (which is slower, but has the best # compatibility), NativeMML (i.e. MathML) and SVG. # The default value is: HTML-CSS. # This tag requires that the tag USE_MATHJAX is set to YES. MATHJAX_FORMAT = HTML-CSS # When MathJax is enabled you need to specify the location relative to the HTML # output directory using the MATHJAX_RELPATH option. The destination directory # should contain the MathJax.js script. For instance, if the mathjax directory # is located at the same level as the HTML output directory, then # MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax # Content Delivery Network so you can quickly see the result without installing # MathJax. However, it is strongly recommended to install a local copy of # MathJax from http://www.mathjax.org before deployment. # The default value is: http://cdn.mathjax.org/mathjax/latest. # This tag requires that the tag USE_MATHJAX is set to YES. MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest # The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax # extension names that should be enabled during MathJax rendering. For example # MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols # This tag requires that the tag USE_MATHJAX is set to YES. MATHJAX_EXTENSIONS = # The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces # of code that will be used on startup of the MathJax code. See the MathJax site # (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an # example see the documentation. # This tag requires that the tag USE_MATHJAX is set to YES. MATHJAX_CODEFILE = # When the SEARCHENGINE tag is enabled doxygen will generate a search box for # the HTML output. The underlying search engine uses javascript and DHTML and # should work on any modern browser. Note that when using HTML help # (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) # there is already a search function so this one should typically be disabled. # For large projects the javascript based search engine can be slow, then # enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to # search using the keyboard; to jump to the search box use + S # (what the is depends on the OS and browser, but it is typically # , /