[ { "path": "LICENSE", "content": "Copyright (c) [2017] [SAFARI Research Group at Carnegie Mellon University and ETH Zurich]\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n" }, { "path": "README.md", "content": "## [DRAM Bender](https://github.com/CMU-SAFARI/DRAM-Bender) (a.k.a. SoftMC v2) supersedes SoftMC. We suggest that you use DRAM Bender instead of SoftMC.\n\n# SoftMC v1.0\n\nSoftMC is an experimental FPGA-based memory controller design that could be used to develop tests for DDR3 SODIMMs. SoftMC currently supports only the *Xilinx ML605* board. Soon, we will port SoftMC on other popularly used boards (e.g., *Xilinx VC709*). \n\nA paper describing SoftMC in detail is published at HPCA 2017 and is available here: \n>*Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, and Onur Mutlu,*\n**\"[SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies](https://people.inf.ethz.ch/omutlu/projects.htm)\"**\n*Proceedings of the 23rd International Symposium on High-Performance Computer Architecture (HPCA), Austin, TX, USA, February 2017.*\n\nIf you use or build on SoftMC, please cite that paper. \n\nWe provide a) prebuilt binaries for quick installation and b) the source\ncode (both in Verilog and C++) that you could modify as you wish.\n\n## Prerequisites:\n- A Xilinx ML605 FPGA or other compatible board (We only tested ML605)\n- A Linux Host Machine, (We have tested on Ubuntu 12.04/14.04)\n- SoftMC uses an 8-lane PCIe interface to communicate with the Host Machine.\n So, you would also need to attach the board to the 8x/16x PCIe slot on the\nmotherboard of the Host Machine\n- Single Rank DDR3 SODIMM attached to your FPGA board\n- Xilinx ISE 14.6 (in case you want to build your own bitfile from the\n source)\n\n\n## Installation Guide:\n\n### 1) Installing the RIFFA driver:\n\nYou need to have [RIFFA](http://riffa.ucsd.edu) driver installed on your system to enable\nthe communication with the FPGA via the PCIe bus. Do not forget to attach\nyour FPGA board to a PCIe slot.\n\nFirst switch to the directory of the source files of the RIFFA driver:\n\n```$ cd sw/riffa_2.1/driver/linux```\n\nThen run make to build the driver\n\n```$ make```\n\nThen install the driver to your system\n\n```$ sudo make install```\n\n### 2) Creating and Downloading the SoftMC bitfile to the FPGA:\n\n**a) Quick Installation using Prebuilt Binaries**\n\nYou will find all that you need inside \"prebuilt\" folder\n(including an executable for the Retention Time test).\n\n- You need to download the bitfile into your FPGA using an appropriate tool\n(Xilinx *Impact* does the job for ML605)\n- After restarting the machine that the FPGA is connected to via PCIe, you\n should be able to run the Retention Time test application by typing to\ncommand below:\n\n```$ ./SoftMC_RetentionTime [Target Retention Time in milliseconds]```\n\n**b) Installation from the Source Code**\n\nGenerating the SoftMC bitfile is straightforward:\n\n- Use Xilinx ISE 14.6 to open the project, which is located located at *hw/boards/ML605/SoftMC.xise*. Ignore *missing files* pop-up windows by clicking the \"Cancel\" button. The missing files will be generated once the steps below are followed. \n- Double-click on *xilinx_mig* IPCore file to open Memory Interface Generator's (MIG) configuration window. Keep clicking the \"Next\" button until the windows closes. Doing this will generate the necessary files required by SoftMC in ```hw/boards/ML605/ipcore_dir/xilinx_mig```.\n- Open a terminal and go to hw/boards/ML605. Run:\n\n```$ sh apply_patches.sh```\n\nThis will apply modifications to the files generated by MIG.\n\n- Go back to Xilinx ISE and click \"Generate Programming File\" and then click \"Yes\" on the dialogs\n that ask for IPCore to be compiled\n - If you get the following error during synthesis:\n `hw/boards/ML605/ipcore_dir/pcie_endpoint/source/gtx_wrapper_v6.v\" Line\n277: Instantiating from unknown module\n`\n 1. Add `` `include \"gtx_drp_chanalign_fix_3752_v6.v\" `` before the module\ndeclaration in `` \"gtx_wrapper_v6.v\" ``. Save the file.\n 2. Comment-out the line that you have just added. Save the file again.\n 3. Click Synthesize again\n\n The error occurs due to a bug in Xilinx ISE software. A workaround for it\nis doing the steps that we listed above.\n\n- After the operation completes successfully, you will find the generated\n bitfile in the project folder\n- Then follow the steps in **a)**\n\n*(Where necessary to simulate the SoftMC hardware, we provide a sample testbench module (\"tb_softMC_top.v\") that you can start with. To enable simulation, you will need to uncomment the SIM definition in \"softMC.inc\". This will change the I/O interface of the top module to exclude the PCIe signals and let you easily issue instructions to SoftMC)*\n\nTo compile the sample application (retention time test) that we provide:\n\n```\n$ cd sw/RetentionTest\n$ make\n$ ./SoftMC_RetentionTest [Target Retention Time in milliseconds]\n``` \n\n## Known Issues:\n- Multi Rank SODIMMs are currently not supported.\n- An instruction sequence could consist maximum of 8192 instructions (see our HPCA 2017 paper for details).\n- Motherboards with B75 Chipset seems to be incompatible with ML605's PCIe endpoint.\n\nYou are welcome to contribute to the project. If you find/solve any issues\nor port SoftMC to a new FPGA board, please contact the people below.\n\n## Contacts:\nHasan Hassan (hhasan [at] inf [dot] ethz [dot] ch)\n\n" }, { "path": "hw/boards/ML605/SoftMC.xise", "content": "\n\n\n
\n \n \n \n \n \n \n \n \n
\n\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \" xil_pn:valueState=\"default\"/>\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n\n \n\n \n \n \n \n \n \n \n \n \n \n \n\n\n" }, { "path": "hw/boards/ML605/apply_patches.sh", "content": "for f in ./patches/*.patch\ndo\n patch -p0 < $f\ndone\n" }, { "path": "hw/boards/ML605/autoref_config.v", "content": "`timescale 1ns / 1ps\n//Hasan\n\nmodule autoref_config(\n\t\tinput clk,\n\t\tinput rst,\n\t\t\n\t\tinput set_interval,\n\t\tinput[27:0] interval_in,\n\t\tinput set_trfc,\n\t\tinput[27:0] trfc_in,\n\t\t\n\t\t\n\t\toutput reg aref_en,\n\t\toutput reg[27:0] aref_interval,\n\t\toutput reg[27:0] trfc\n );\n\t \n\t \n\t always@(posedge clk) begin\n\t\tif(rst) begin\n\t\t\taref_en <= 0;\n\t\t\taref_interval <= 0;\n\t\t\ttrfc <= 0;\n\t\tend\n\t\telse begin\n\t\t\tif(set_interval) begin\n\t\t\t\taref_en <= |interval_in;\n\t\t\t\taref_interval <= interval_in;\n\t\t\tend //set_interval\n\t\t\t\n\t\t\tif(set_trfc) begin\n\t\t\t\ttrfc <= trfc_in;\n\t\t\tend\n\t\tend\n\t end\n\nendmodule\n" }, { "path": "hw/boards/ML605/instr_decoder.v", "content": "`timescale 1ns / 1ps\n\n`include \"softMC.inc\"\n\nmodule instr_decoder #(parameter ROW_WIDTH = 15, BANK_WIDTH = 3, CS_WIDTH = 1)(\n\tinput en,\n\tinput[31:0] instr,\n\t\n\toutput reg[ROW_WIDTH - 1:0] dfi_address,\n\toutput reg[BANK_WIDTH - 1:0] dfi_bank,\n\toutput reg dfi_cas_n,\n\toutput reg[CS_WIDTH - 1:0] dfi_cs_n,\n\toutput reg dfi_ras_n,\n\toutput reg dfi_we_n\n);\n\t\n\tlocalparam LOW = 1'b0;\n\tlocalparam HIGH = 1'b1;\n\n\talways@* begin\r\n\t\tdfi_address = {ROW_WIDTH{1'bx}};\r\n\t\tdfi_bank = {BANK_WIDTH{1'bx}};\r\n\t\t\r\n\t\tdfi_cas_n = HIGH;\r\n\t\tdfi_cs_n = {CS_WIDTH{HIGH}};\r\n\t\tdfi_ras_n = HIGH;\r\n\t\tdfi_we_n = HIGH;\n\t\t\n\t\tif(en) begin\n\t\t\tdfi_address = instr[ROW_WIDTH - 1:0];\n\t\t\tdfi_bank = instr[`ROW_OFFSET +: BANK_WIDTH];\n\t\t\tdfi_we_n = instr[`WE_OFFSET];\n\t\t\tdfi_cas_n = instr[`CAS_OFFSET];\n\t\t\tdfi_ras_n = instr[`RAS_OFFSET];\n\t\t\tdfi_cs_n = instr[`CS_OFFSET +: CS_WIDTH];\n\t\tend //en\r\n\tend\nendmodule\n" }, { "path": "hw/boards/ML605/instr_dispatcher.v", "content": "`timescale 1ns / 1ps\n\n`include \"softMC.inc\"\n\nmodule instr_dispatcher #(parameter ROW_WIDTH = 15, BANK_WIDTH = 3, CKE_WIDTH = 1, RANK_WIDTH = 1,\r\n\t\t\t\t\t\t\t\t\t\tCS_WIDTH = 1, nCS_PER_RANK = 1, DQ_WIDTH = 64) (\r\n\tinput clk,\r\n\tinput rst,\r\n\t\n\tinput periodic_read_lock,\n\t\n\t//There are two instructions queues to fetch from. Since PHY issues DDR commands at both pos and neg edges, \n\t//we dispatch two instructions in the same cycle, running at half of the frequency of the DDR bus\r\n\tinput en_in0,\r\n\toutput en_ack0,\r\n\tinput[31:0] instr_in0,\n\t\n\tinput en_in1,\n\toutput en_ack1,\n\tinput[31:0] instr_in1,\r\n\t\r\n\t//DFI Interface\r\n\t// DFI Control/Address\n\tinput \t\t\t\t\t\t\t\t\t\t\tdfi_ready,\n\toutput[ROW_WIDTH-1:0] dfi_address0,\n\toutput[ROW_WIDTH-1:0] dfi_address1,\n\toutput[BANK_WIDTH-1:0] dfi_bank0,\n\toutput[BANK_WIDTH-1:0] dfi_bank1,\n\toutput\t\t\t\t\t\t\t\t\t dfi_cke0,\n\toutput \t\t\t\t\t\t\t\t\t dfi_cke1,\n\toutput\t\t\t\t\t\t\t\t\t dfi_cas_n0,\n\toutput\t\t\t\t\t\t\t\t\t\tdfi_cas_n1,\n\toutput[CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n0,\n\toutput[CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n1,\r\n\toutput[CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt0,\n\toutput[CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt1,\n\toutput\t\t\t\t\t\t\t\t\t\tdfi_ras_n0,\n\toutput\t\t\t\t\t\t\t\t\t\tdfi_ras_n1,\n\toutput\t\t\t\t\t\t\t\t\t\tdfi_we_n0,\n\toutput\t\t\t\t\t\t\t\t\t\tdfi_we_n1,\n\t// DFI Write\n\toutput reg dfi_wrdata_en,\n\toutput [4*DQ_WIDTH-1:0] dfi_wrdata,\n\toutput [4*(DQ_WIDTH/8)-1:0] dfi_wrdata_mask,\n\t// DFI Read\n\toutput reg dfi_rddata_en,\n\toutput reg\t\t\t\t\t\t\t\t\t\tdfi_rddata_en_even,\n\toutput reg \t\t\t\t\t\t\t\t\t\tdfi_rddata_en_odd,\r\n\t\r\n\t//Bus Command\r\n\toutput reg io_config_strobe,\r\n\toutput reg[1:0] io_config,\n\t\n\t//Misc.\n\toutput pr_rd_ack,\n\t\n\t//auto-refresh\n output reg aref_set_interval,\n output reg[27:0] aref_interval, \n output reg aref_set_trfc,\n output reg[27:0] aref_trfc\r\n);\r\n\t\r\n\tlocalparam ONE = 1;\n\tlocalparam TWO = 2;\r\n\t\r\n\tlocalparam HIGH = 1'b1;\r\n\tlocalparam LOW = 1'b0;\r\n\t\r\n\treg[9:0] wait_cycles_r = ONE[0 +: 10], wait_cycles_ns;\r\n\t\r\n\treg read_burst_r, read_burst_ns;\n\treg read_burst_even_r, read_burst_even_ns;\n\treg read_burst_odd_r, read_burst_odd_ns;\r\n\treg write_burst_r, write_burst_ns;\r\n\treg[7:0] write_burst_data_r, write_burst_data_ns;\r\n\t\r\n\treg bus_write, bus_write_r;\n\t\n\treg pr_rd_ack_r, pr_rd_ack_ns;\n\t\n\treg ack0, ack1;\n\treg instr_src_r, instr_src_ns;\n\t\n\treg dec0_en;\n\twire[31:0] dec0_instr;\n\t\n\treg dec1_en;\n\twire[31:0] dec1_instr;\n\t\n\twire en0 = instr_src_r ? en_in1 : en_in0;\n\twire[31:0] instr0 = instr_src_r ? instr_in1 : instr_in0;\n\tassign en_ack0 = instr_src_r ? ack1 : ack0;\n\t\n\twire en1 = instr_src_r ? en_in0 : en_in1;\n\twire[31:0] instr1 = instr_src_r ? instr_in0 : instr_in1;\n\tassign en_ack1 = instr_src_r ? ack0 : ack1;\n\t\n\tassign dec0_instr = instr0;\n\tassign dec1_instr = instr1;\n\t\n\treg block_other_slot;\n\t\n\treg cke0, cke0_r, cke1, cke1_r;\n\t\n\t//auto-refresh\n\treg aref_set_interval_ns, aref_set_trfc_ns;\n\treg[27:0] aref_interval_ns, aref_trfc_ns;\n\t\n\t//Counter saturating at zero\n\treg load_counter;\n\talways@(posedge clk) begin\n\t\tif(rst)\n\t\t\twait_cycles_r <= 10'd0;\n\t\telse begin\n\t\t\tif(load_counter) begin\n\t\t\t\twait_cycles_r <= wait_cycles_ns;\n\t\t\tend //load_counter\n\t\t\telse begin\n\t\t\t\tif(|wait_cycles_r[9:1])\n\t\t\t\t\twait_cycles_r <= wait_cycles_r - TWO[0 +: 10];\n\t\t\t\telse\n\t\t\t\t\twait_cycles_r <= 10'd0;\n\t\t\tend\n\t\tend\n\tend\n\t\n\talways@* begin\n\t\tio_config_strobe = LOW;\r\n\t\tio_config = 2'b00;\n\t\tbus_write = bus_write_r;\n\t\t\n\t\tinstr_src_ns = ~(en_in0 | en_in1) ? LOW : instr_src_r;\n\t\t\n\t\tack0 = HIGH;\n\t\tack1 = HIGH;\n\t\t\n\t\tdec0_en = LOW;\n\t\tdec1_en = LOW;\n\t\t\n\t\tread_burst_ns = LOW;\n\t\tread_burst_even_ns = LOW;\n\t\tread_burst_odd_ns = LOW;\r\n\t\twrite_burst_ns = LOW;\n\t\twrite_burst_data_ns = write_burst_data_r;\n\t\t\n\t\tdfi_rddata_en = read_burst_r;\n\t\tdfi_rddata_en_even = read_burst_even_r;\n\t\tdfi_rddata_en_odd = read_burst_odd_r;\r\n\t\tdfi_wrdata_en = write_burst_r;\n\t\t\n\t\tpr_rd_ack_ns = LOW;\n\t\t\n\t\taref_set_interval_ns = 1'b0;\n\t\taref_interval_ns = {28{1'bx}};\n\t\taref_set_trfc_ns = 1'b0;\n\t\taref_trfc_ns = {28{1'bx}};\n\t\t\n\t\twait_cycles_ns = 10'dx;\n\t\tload_counter = LOW;\n\t\t\n\t\tblock_other_slot = LOW;\n\t\t\n\t\tcke0 = cke0_r;\n\t\tcke1 = cke1_r;\n\t\t\n\t\tif(dfi_ready & (wait_cycles_r <= 10'd1)) begin\n\t\t\tif(en0) begin\n\t\t\t\tcasex(instr0[31:28])\n\t\t\t\t\t`SET_BUSDIR: begin\n\t\t\t\t\t\tio_config_strobe = HIGH;\r\n\t\t\t\t\t\tio_config = instr0[1:0];\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(instr0[1:0] == `BUS_DIR_WRITE)\r\n\t\t\t\t\t\t\tbus_write = 1'b1;\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\tbus_write = 1'b0;\n\t\t\t\t\tend //SET_BUSDIR\n\t\t\t\t\t\n\t\t\t\t\t`DDR_INSTR: begin\n\t\t\t\t\t\tdec0_en = HIGH;\n\t\t\t\t\t\tcke0 = instr0[`CKE_OFFSET];\n\t\t\t\t\t\t\n\t\t\t\t\t\tif(~|instr0[`CS_OFFSET +: CS_WIDTH] && instr0[`RAS_OFFSET] && ~instr0[`CAS_OFFSET] &&\n\t\t\t\t\t\t\t\t\tinstr0[`WE_OFFSET] && cke0 && cke0_r) begin //check whether we have a read instruction\n\t\t\t\t\t\t\tdfi_rddata_en = HIGH;\n\t\t\t\t\t\t\tdfi_rddata_en_even = HIGH;\r\n\t\t\t\t\t\t\tread_burst_ns = HIGH;\n\t\t\t\t\t\t\tread_burst_even_ns = HIGH;\n\t\t\t\t\t\t\t\n\t\t\t\t\t\t\tdfi_rddata_en_odd = periodic_read_lock; //to indicate periodic read response\n\t\t\t\t\t\t\tread_burst_odd_ns = periodic_read_lock;\n\t\t\t\t\t\t\t\n\t\t\t\t\t\t\tpr_rd_ack_ns = HIGH;\n\t\t\t\t\t\tend\n\t\t\t\t\t\t\n\t\t\t\t\t\tif(~|instr0[`CS_OFFSET +: CS_WIDTH] && instr0[`RAS_OFFSET] && ~instr0[`CAS_OFFSET] &&\n\t\t\t\t\t\t\t\t\t~instr0[`WE_OFFSET] && cke0 && cke0_r) begin //check whether we have a write instruction\n\t\t\t\t\t\t\tdfi_wrdata_en = HIGH;\r\n\t\t\t\t\t\t\twrite_burst_ns = HIGH;\n\t\t\t\t\t\t\t\n\t\t\t\t\t\t\twrite_burst_data_ns = {instr0[30:25], instr0[(`ROW_OFFSET - 1) -:2]};\n\t\t\t\t\t\t\tend\n\t\t\t\t\tend //DDR_INSTR\n\t\t\t\t\t\n\t\t\t\t\t`WAIT: begin\n\t\t\t\t\t\tload_counter = HIGH;\n\t\t\t\t\t\twait_cycles_ns = instr0[9:0] - 10'd1; //reducing by one for the second slot\n\t\t\t\t\t\t\n\t\t\t\t\t\tif(instr0[9:0] > 10'd1)\n\t\t\t\t\t\t\tblock_other_slot = HIGH;\n\t\t\t\t\t\t\n\t\t\t\t\t\tif(~instr0[0])\n\t\t\t\t\t\t\tinstr_src_ns = ~instr_src_r;\n\t\t\t\t\tend //WAIT\n\t\t\t\t\t\n\t\t\t\t\t`SET_TREFI: begin\n\t\t\t\t\t\taref_set_interval_ns = 1'b1;\n\t\t\t\t\t\taref_interval_ns = instr0[27:0];\n\t\t\t\t\tend //SET_TREFI\n\t\t\t\t\t\n\t\t\t\t\t`SET_TRFC: begin\n\t\t\t\t\t\taref_set_trfc_ns = 1'b1;\n\t\t\t\t\t\taref_trfc_ns = instr0[27:0];\n\t\t\t\t\tend //SET_TRFC\n\t\t\t\t\n\t\t\t\tendcase //instr0\n\t\t\tend //en0\n\t\tend\n\t\telse begin\n\t\t\tack0 = LOW;\n\t\tend\n\t\t\n\t\tif(~(en0 & block_other_slot) & dfi_ready & (wait_cycles_r <= 10'd2)) begin\n\t\t\tif(en1) begin\n\t\t\t\tcasex(instr1[31:28])\n\t\t\t\t\t`SET_BUSDIR: begin\n\t\t\t\t\t\tio_config_strobe = HIGH;\r\n\t\t\t\t\t\tio_config = instr1[1:0];\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(instr1[1:0] == `BUS_DIR_WRITE)\r\n\t\t\t\t\t\t\tbus_write = 1'b1;\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\tbus_write = 1'b0;\n\t\t\t\t\tend //SET_BUSDIR\n\t\t\t\t\t\n\t\t\t\t\t`DDR_INSTR: begin\n\t\t\t\t\t\tdec1_en = HIGH;\n\t\t\t\t\t\tcke1 = instr1[`CKE_OFFSET];\n\t\t\t\t\t\t\n\t\t\t\t\t\tif(~|instr1[`CS_OFFSET +: CS_WIDTH] && instr1[`RAS_OFFSET] && ~instr1[`CAS_OFFSET] &&\n\t\t\t\t\t\t\t\t\tinstr1[`WE_OFFSET] && cke1 && cke1_r) begin //check whether we have a read command\n\t\t\t\t\t\t\tdfi_rddata_en = HIGH;\r\n\t\t\t\t\t\t\tread_burst_ns = HIGH;\n\t\t\t\t\t\t\t\n\t\t\t\t\t\t\tdfi_rddata_en_odd = periodic_read_lock; //to indicate periodic read response\n\t\t\t\t\t\t\tread_burst_odd_ns = periodic_read_lock;\n\t\t\t\t\t\t\t\n\t\t\t\t\t\t\tpr_rd_ack_ns = HIGH;\n\t\t\t\t\t\tend\n\t\t\t\t\t\t\n\t\t\t\t\t\tif(~|instr1[`CS_OFFSET +: CS_WIDTH] && instr1[`RAS_OFFSET] && ~instr1[`CAS_OFFSET] &&\n\t\t\t\t\t\t\t\t\t~instr1[`WE_OFFSET] && cke1 && cke1_r) begin //check whether we have a write command\n\t\t\t\t\t\t\tdfi_wrdata_en = HIGH;\r\n\t\t\t\t\t\t\twrite_burst_ns = HIGH;\n\t\t\t\t\t\t\t\n\t\t\t\t\t\t\twrite_burst_data_ns = {instr1[30:25], instr1[(`ROW_OFFSET - 1) -:2]};\n\t\t\t\t\t\t\tend\n\t\t\t\t\tend //DDR_INSTR\n\t\t\t\t\t\n\t\t\t\t\t`WAIT: begin\n\t\t\t\t\t\twait_cycles_ns = instr1[9:0];\n\t\t\t\t\t\tload_counter = HIGH;\n\t\t\t\t\t\t\n\t\t\t\t\t\tif(~instr1[0])\n\t\t\t\t\t\t\tinstr_src_ns = ~instr_src_r;\n\t\t\t\t\tend //WAIT\n\t\t\t\t\t\n\t\t\t\t\t`SET_TREFI: begin\n\t\t\t\t\t\taref_set_interval_ns = 1'b1;\n\t\t\t\t\t\taref_interval_ns = instr1[27:0];\n\t\t\t\t\tend //SET_TREFI\n\t\t\t\t\t\n\t\t\t\t\t`SET_TRFC: begin\n\t\t\t\t\t\taref_set_trfc_ns = 1'b1;\n\t\t\t\t\t\taref_trfc_ns = instr1[27:0];\n\t\t\t\t\tend //SET_TRFC\n\t\t\t\t\t\n\t\t\t\tendcase //instr1\n\t\t\tend //en1\n\t\tend\n\t\telse begin\n\t\t\tack1 = LOW;\n\t\tend\n\tend\n\t\n\tinstr_decoder #(.ROW_WIDTH(ROW_WIDTH), .BANK_WIDTH(BANK_WIDTH), .CS_WIDTH(CS_WIDTH)) instr_dec0(\n\t\t.en(dec0_en),\n\t\t.instr(dec0_instr),\n\t\t\n\t\t.dfi_address(dfi_address0),\n\t\t.dfi_bank(dfi_bank0),\n\t\t.dfi_cas_n(dfi_cas_n0),\n\t\t.dfi_cs_n(dfi_cs_n0),\n\t\t.dfi_ras_n(dfi_ras_n0),\n\t\t.dfi_we_n(dfi_we_n0)\n\t);\n\t\n\tinstr_decoder #(.ROW_WIDTH(ROW_WIDTH), .BANK_WIDTH(BANK_WIDTH), .CS_WIDTH(CS_WIDTH)) i_instr_dec1(\n\t\t.en(dec1_en),\n\t\t.instr(dec1_instr),\n\t\t\n\t\t.dfi_address(dfi_address1),\n\t\t.dfi_bank(dfi_bank1),\n\t\t.dfi_cas_n(dfi_cas_n1),\n\t\t.dfi_cs_n(dfi_cs_n1),\n\t\t.dfi_ras_n(dfi_ras_n1),\n\t\t.dfi_we_n(dfi_we_n1)\n\t);\r\n\t\r\n\tassign dfi_wrdata_mask = 0;\r\n\tassign dfi_wrdata = dfi_cas_n0 ? {4*(DQ_WIDTH/8){write_burst_data_r}} : {4*(DQ_WIDTH/8){write_burst_data_ns}};\n\t\n\talways@(posedge clk) begin\n\t\tpr_rd_ack_r <= pr_rd_ack_ns;\n\tend\n\tassign pr_rd_ack = pr_rd_ack_r;\n\t\n\talways@(posedge clk) begin\n\t\tif(rst) begin\n\t\t\taref_set_interval <= 0;\n\t\t\taref_set_trfc <= 0;\n\t\t\taref_interval <= 0;\n\t\t\taref_trfc <= 0;\n\t\t\t\n\t\t\tcke0_r <= 1'b1; //not sure what would happen if the clock is disabled on reset\n\t\t\tcke1_r <= 1'b1;\n\t\tend\n\t\telse begin\n\t\t\taref_set_interval <= aref_set_interval_ns;\n\t\t\taref_set_trfc <= aref_set_trfc_ns;\n\t\t\taref_interval <= aref_interval_ns;\n\t\t\taref_trfc <= aref_trfc_ns;\n\t\t\t\n\t\t\tcke0_r <= cke0;\n\t\t\tcke1_r <= cke1;\n\t\tend\n\tend\r\n\t\r\n\t\r\n\talways@(posedge clk) begin\r\n\t\tif(rst) begin\r\n\t\t\tread_burst_r <= LOW;\n\t\t\tread_burst_even_r <= LOW;\n\t\t\tread_burst_odd_r <= LOW;\r\n\t\t\twrite_burst_r <= LOW;\r\n\t\t\twrite_burst_data_r <= 0;\r\n\t\t\t\r\n\t\t\tbus_write_r <= LOW;\n\t\t\t\n\t\t\tinstr_src_r <= LOW;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tread_burst_r <= read_burst_ns;\n\t\t\tread_burst_even_r <= read_burst_even_ns;\n\t\t\tread_burst_odd_r <= read_burst_odd_ns;\r\n\t\t\twrite_burst_r <= write_burst_ns;\r\n\t\t\twrite_burst_data_r <= write_burst_data_ns;\r\n\t\t\t\r\n\t\t\tbus_write_r <= bus_write;\n\t\t\t\n\t\t\tinstr_src_r <= instr_src_ns;\r\n\t\tend //!rst\r\n\tend\r\n\t\r\n\tassign dfi_odt0 = bus_write_r;\r\n\tassign dfi_odt1 = bus_write_r;\n\t\n\tassign dfi_cke0 = cke0_r;\n\tassign dfi_cke1 = cke1_r;\r\nendmodule\n" }, { "path": "hw/boards/ML605/instr_receiver.v", "content": "`timescale 1ns / 1ps\n\n`include \"softMC.inc\"\n\nmodule instr_receiver (\r\n\tinput clk,\r\n\tinput rst,\n\t\n\tinput dispatcher_ready,\r\n\t\r\n\tinput app_en,\n\toutput reg app_ack,\r\n\tinput[31:0] app_instr,\n\t\n\tinput maint_en,\n\toutput reg maint_ack,\r\n\tinput[31:0] maint_instr,\r\n\t\r\n\toutput instr0_fifo_en,\r\n\toutput[31:0] instr0_fifo_data,\n\t\n\toutput instr1_fifo_en,\r\n\toutput[31:0] instr1_fifo_data,\r\n\t\r\n\toutput process_iseq\r\n);\r\n\r\nreg process_iseq_r = 1'b0, process_iseq_ns;\n\nlocalparam STATE_IDLE = 2'b00;\nlocalparam STATE_APP = 2'b01;\nlocalparam STATE_MAINT = 2'b10;\n\nreg[1:0] state_ns, state_r;\r\n\nreg sel_fifo = 1'b0;\n\nreg instr_en_ns, instr_en_r;\nreg[31:0] instr_ns, instr_r;\r\n\r\nalways@* begin\r\n\tprocess_iseq_ns = 1'b0;\r\n\t\n\tstate_ns = state_r;\n\t\n\tinstr_en_ns = 1'b0;\n\tinstr_ns = instr_r;\n\t\n\tapp_ack = 1'b0;\n\tmaint_ack = 1'b0;\n\t\n\tcase(state_r)\n\t\tSTATE_IDLE: begin\n\t\t\tif(dispatcher_ready & ~process_iseq_r) begin\n\t\t\t\tif(app_en) begin\n\t\t\t\t\tstate_ns = STATE_APP;\n\t\t\t\t\tinstr_en_ns = app_en;\n\t\t\t\t\tinstr_ns = app_instr;\n\t\t\t\t\t\n\t\t\t\t\tapp_ack = 1'b1;\n\t\t\t\tend\n\t\t\t\telse if(maint_en) begin\n\t\t\t\t\tstate_ns = STATE_MAINT;\n\t\t\t\t\tinstr_en_ns = maint_en;\n\t\t\t\t\tinstr_ns = maint_instr;\n\t\t\t\t\t\n\t\t\t\t\tmaint_ack = 1'b1;\n\t\t\t\tend\n\t\t\tend //dispatcher_ready\n\t\tend //STATE_IDLE\n\t\t\n\t\tSTATE_APP: begin\n\t\t\tapp_ack = 1'b1;\n\t\t\t\n\t\t\tinstr_en_ns = app_en;\n\t\t\tinstr_ns = app_instr;\n\t\t\t\n\t\t\tif(instr_en_ns & (instr_ns[31:28] == `END_ISEQ)) begin\n\t\t\t\tprocess_iseq_ns = 1'b1;\n\t\t\t\tstate_ns = STATE_IDLE;\n\t\t\tend\n\t\tend //STATE_APP\n\t\t\n\t\tSTATE_MAINT: begin\n\t\t\tmaint_ack = 1'b1;\n\t\t\t\n\t\t\tinstr_en_ns = maint_en;\n\t\t\tinstr_ns = maint_instr;\n\t\t\t\n\t\t\tif(instr_en_ns & (instr_ns[31:28] == `END_ISEQ)) begin\n\t\t\t\tinstr_en_ns = 1'b0;\n\t\t\t\tprocess_iseq_ns = 1'b1;\n\t\t\t\tstate_ns = STATE_IDLE;\n\t\t\tend\n\t\tend //STATE_MAINT\n\t\n\tendcase //state_r\nend //always\n\nassign instr0_fifo_en = ~sel_fifo & instr_en_r;\nassign instr0_fifo_data = instr_r;\nassign instr1_fifo_en = sel_fifo & instr_en_r;\nassign instr1_fifo_data = instr_r;\r\n\r\nalways@(posedge clk) begin\r\n\tif(rst) begin\r\n\t\tprocess_iseq_r <= 1'b0;\n\t\tsel_fifo <= 1'b0;\n\t\tstate_r <= STATE_IDLE; \n\t\t\n\t\tinstr_en_r <= 1'b0;\n\t\tinstr_r <= 0;\r\n\tend\r\n\telse begin\n\t\tstate_r <= state_ns;\r\n\t\tprocess_iseq_r <= process_iseq_ns;\n\t\t\n\t\tinstr_en_r <= instr_en_ns;\n\t\tinstr_r <= instr_ns;\n\t\t\n\t\tif(process_iseq_r)\n\t\t\tsel_fifo <= 1'b0;\n\t\telse if(instr_en_r)\n\t\t\tsel_fifo <= ~sel_fifo;\r\n\tend //!rst\r\nend\r\n\r\nassign process_iseq = process_iseq_r;\r\n\r\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/instr_fifo.xco", "content": "##############################################################\n#\n# Xilinx Core Generator version 14.6\n# Date: Fri Feb 3 17:08:40 2017\n#\n##############################################################\n#\n# This file contains the customisation parameters for a\n# Xilinx CORE Generator IP GUI. It is strongly recommended\n# that you do not manually alter this file as it may cause\n# unexpected and unsupported behavior.\n#\n##############################################################\n#\n# Generated from component: xilinx.com:ip:fifo_generator:9.3\n#\n##############################################################\n#\n# BEGIN Project Options\nSET addpads = false\nSET asysymbol = true\nSET busformat = BusFormatAngleBracketNotRipped\nSET createndf = false\nSET designentry = Verilog\nSET device = xc6vlx240t\nSET devicefamily = virtex6\nSET flowvendor = Other\nSET formalverification = false\nSET foundationsym = false\nSET implementationfiletype = Ngc\nSET package = ff1156\nSET removerpms = false\nSET simulationfiles = Behavioral\nSET speedgrade = -1\nSET verilogsim = true\nSET vhdlsim = false\n# END Project Options\n# BEGIN Select\nSELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3\n# END Select\n# BEGIN Parameters\nCSET add_ngc_constraint_axi=false\nCSET almost_empty_flag=false\nCSET almost_full_flag=false\nCSET aruser_width=1\nCSET awuser_width=1\nCSET axi_address_width=32\nCSET axi_data_width=64\nCSET axi_type=AXI4_Stream\nCSET axis_type=FIFO\nCSET buser_width=1\nCSET clock_enable_type=Slave_Interface_Clock_Enable\nCSET clock_type_axi=Common_Clock\nCSET component_name=instr_fifo\nCSET data_count=false\nCSET data_count_width=11\nCSET disable_timing_violations=false\nCSET disable_timing_violations_axi=false\nCSET dout_reset_value=0\nCSET empty_threshold_assert_value=4\nCSET empty_threshold_assert_value_axis=1022\nCSET empty_threshold_assert_value_rach=1022\nCSET empty_threshold_assert_value_rdch=1022\nCSET empty_threshold_assert_value_wach=1022\nCSET empty_threshold_assert_value_wdch=1022\nCSET empty_threshold_assert_value_wrch=1022\nCSET empty_threshold_negate_value=5\nCSET enable_aruser=false\nCSET enable_awuser=false\nCSET enable_buser=false\nCSET enable_common_overflow=false\nCSET enable_common_underflow=false\nCSET enable_data_counts_axis=false\nCSET enable_data_counts_rach=false\nCSET enable_data_counts_rdch=false\nCSET enable_data_counts_wach=false\nCSET enable_data_counts_wdch=false\nCSET enable_data_counts_wrch=false\nCSET enable_ecc=false\nCSET enable_ecc_axis=false\nCSET enable_ecc_rach=false\nCSET enable_ecc_rdch=false\nCSET enable_ecc_wach=false\nCSET enable_ecc_wdch=false\nCSET enable_ecc_wrch=false\nCSET enable_read_channel=false\nCSET enable_read_pointer_increment_by2=false\nCSET enable_reset_synchronization=true\nCSET enable_ruser=false\nCSET enable_tdata=false\nCSET enable_tdest=false\nCSET enable_tid=false\nCSET enable_tkeep=false\nCSET enable_tlast=false\nCSET enable_tready=true\nCSET enable_tstrobe=false\nCSET enable_tuser=false\nCSET enable_write_channel=false\nCSET enable_wuser=false\nCSET fifo_application_type_axis=Data_FIFO\nCSET fifo_application_type_rach=Data_FIFO\nCSET fifo_application_type_rdch=Data_FIFO\nCSET fifo_application_type_wach=Data_FIFO\nCSET fifo_application_type_wdch=Data_FIFO\nCSET fifo_application_type_wrch=Data_FIFO\nCSET fifo_implementation=Common_Clock_Block_RAM\nCSET fifo_implementation_axis=Common_Clock_Block_RAM\nCSET fifo_implementation_rach=Common_Clock_Block_RAM\nCSET fifo_implementation_rdch=Common_Clock_Block_RAM\nCSET fifo_implementation_wach=Common_Clock_Block_RAM\nCSET fifo_implementation_wdch=Common_Clock_Block_RAM\nCSET fifo_implementation_wrch=Common_Clock_Block_RAM\nCSET full_flags_reset_value=0\nCSET full_threshold_assert_value=1023\nCSET full_threshold_assert_value_axis=1023\nCSET full_threshold_assert_value_rach=1023\nCSET full_threshold_assert_value_rdch=1023\nCSET full_threshold_assert_value_wach=1023\nCSET full_threshold_assert_value_wdch=1023\nCSET full_threshold_assert_value_wrch=1023\nCSET full_threshold_negate_value=1022\nCSET id_width=4\nCSET inject_dbit_error=false\nCSET inject_dbit_error_axis=false\nCSET inject_dbit_error_rach=false\nCSET inject_dbit_error_rdch=false\nCSET inject_dbit_error_wach=false\nCSET inject_dbit_error_wdch=false\nCSET inject_dbit_error_wrch=false\nCSET inject_sbit_error=false\nCSET inject_sbit_error_axis=false\nCSET inject_sbit_error_rach=false\nCSET inject_sbit_error_rdch=false\nCSET inject_sbit_error_wach=false\nCSET inject_sbit_error_wdch=false\nCSET inject_sbit_error_wrch=false\nCSET input_data_width=32\nCSET input_depth=1024\nCSET input_depth_axis=1024\nCSET input_depth_rach=16\nCSET input_depth_rdch=1024\nCSET input_depth_wach=16\nCSET input_depth_wdch=1024\nCSET input_depth_wrch=16\nCSET interface_type=Native\nCSET output_data_width=32\nCSET output_depth=1024\nCSET overflow_flag=false\nCSET overflow_flag_axi=false\nCSET overflow_sense=Active_High\nCSET overflow_sense_axi=Active_High\nCSET performance_options=First_Word_Fall_Through\nCSET programmable_empty_type=No_Programmable_Empty_Threshold\nCSET programmable_empty_type_axis=No_Programmable_Empty_Threshold\nCSET programmable_empty_type_rach=No_Programmable_Empty_Threshold\nCSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold\nCSET programmable_empty_type_wach=No_Programmable_Empty_Threshold\nCSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold\nCSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold\nCSET programmable_full_type=No_Programmable_Full_Threshold\nCSET programmable_full_type_axis=No_Programmable_Full_Threshold\nCSET programmable_full_type_rach=No_Programmable_Full_Threshold\nCSET programmable_full_type_rdch=No_Programmable_Full_Threshold\nCSET programmable_full_type_wach=No_Programmable_Full_Threshold\nCSET programmable_full_type_wdch=No_Programmable_Full_Threshold\nCSET programmable_full_type_wrch=No_Programmable_Full_Threshold\nCSET rach_type=FIFO\nCSET rdch_type=FIFO\nCSET read_clock_frequency=1\nCSET read_data_count=false\nCSET read_data_count_width=11\nCSET register_slice_mode_axis=Fully_Registered\nCSET register_slice_mode_rach=Fully_Registered\nCSET register_slice_mode_rdch=Fully_Registered\nCSET register_slice_mode_wach=Fully_Registered\nCSET register_slice_mode_wdch=Fully_Registered\nCSET register_slice_mode_wrch=Fully_Registered\nCSET reset_pin=true\nCSET reset_type=Synchronous_Reset\nCSET ruser_width=1\nCSET synchronization_stages=2\nCSET synchronization_stages_axi=2\nCSET tdata_width=64\nCSET tdest_width=4\nCSET tid_width=8\nCSET tkeep_width=4\nCSET tstrb_width=4\nCSET tuser_width=4\nCSET underflow_flag=false\nCSET underflow_flag_axi=false\nCSET underflow_sense=Active_High\nCSET underflow_sense_axi=Active_High\nCSET use_clock_enable=false\nCSET use_dout_reset=true\nCSET use_embedded_registers=true\nCSET use_extra_logic=true\nCSET valid_flag=false\nCSET valid_sense=Active_High\nCSET wach_type=FIFO\nCSET wdch_type=FIFO\nCSET wrch_type=FIFO\nCSET write_acknowledge_flag=false\nCSET write_acknowledge_sense=Active_High\nCSET write_clock_frequency=1\nCSET write_data_count=false\nCSET write_data_count_width=11\nCSET wuser_width=1\n# END Parameters\n# BEGIN Extra information\nMISC pkg_timestamp=2012-11-19T12:39:56Z\n# END Extra information\nGENERATE\n# CRC: 944578b5\n" }, { "path": "hw/boards/ML605/ipcore_dir/instr_fifo.xise", "content": "\n\n\n
\n \n \n \n \n \n \n \n \n
\n\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n \n\n \n \n \n \n \n \n \n \n\n\n" }, { "path": "hw/boards/ML605/ipcore_dir/pcie_endpoint.xco", "content": "##############################################################\n#\n# Xilinx Core Generator version 14.6\n# Date: Fri Feb 3 17:11:58 2017\n#\n##############################################################\n#\n# This file contains the customisation parameters for a\n# Xilinx CORE Generator IP GUI. It is strongly recommended\n# that you do not manually alter this file as it may cause\n# unexpected and unsupported behavior.\n#\n##############################################################\n#\n# Generated from component: xilinx.com:ip:v6_pcie:2.5\n#\n##############################################################\n#\n# BEGIN Project Options\nSET addpads = false\nSET asysymbol = true\nSET busformat = BusFormatAngleBracketNotRipped\nSET createndf = false\nSET designentry = Verilog\nSET device = xc6vlx240t\nSET devicefamily = virtex6\nSET flowvendor = Other\nSET formalverification = false\nSET foundationsym = false\nSET implementationfiletype = Ngc\nSET package = ff1156\nSET removerpms = false\nSET simulationfiles = Behavioral\nSET speedgrade = -1\nSET verilogsim = true\nSET vhdlsim = false\n# END Project Options\n# BEGIN Select\nSELECT Virtex-6_Integrated_Block_for_PCI_Express xilinx.com:ip:v6_pcie:2.5\n# END Select\n# BEGIN Parameters\nCSET acceptable_l0s_latency=Maximum_of_64_ns\nCSET acceptable_l1_latency=No_limit\nCSET ack_nak_timeout_func=Absolute\nCSET ack_nak_timeout_value=0000\nCSET bar0_64bit=false\nCSET bar0_enabled=true\nCSET bar0_prefetchable=false\nCSET bar0_scale=Kilobytes\nCSET bar0_size=1\nCSET bar0_type=Memory\nCSET bar1_64bit=false\nCSET bar1_enabled=false\nCSET bar1_prefetchable=false\nCSET bar1_scale=Kilobytes\nCSET bar1_size=2\nCSET bar1_type=N/A\nCSET bar2_64bit=false\nCSET bar2_enabled=false\nCSET bar2_prefetchable=false\nCSET bar2_scale=Bytes\nCSET bar2_size=128\nCSET bar2_type=N/A\nCSET bar3_64bit=false\nCSET bar3_enabled=false\nCSET bar3_prefetchable=false\nCSET bar3_scale=Kilobytes\nCSET bar3_size=2\nCSET bar3_type=N/A\nCSET bar4_64bit=false\nCSET bar4_enabled=false\nCSET bar4_prefetchable=false\nCSET bar4_scale=Kilobytes\nCSET bar4_size=2\nCSET bar4_type=N/A\nCSET bar5_enabled=false\nCSET bar5_prefetchable=false\nCSET bar5_scale=Kilobytes\nCSET bar5_size=2\nCSET bar5_type=N/A\nCSET base_class_menu=Simple_communication_controllers\nCSET buf_opt_bma=true\nCSET cardbus_cis_pointer=00000000\nCSET class_code_base=05\nCSET class_code_interface=00\nCSET class_code_sub=00\nCSET component_name=pcie_endpoint\nCSET cost_table=1\nCSET cpl_finite=false\nCSET cpl_timeout_disable_sup=false\nCSET cpl_timeout_range=Range_B\nCSET d0_pme_support=true\nCSET d0_power_consumed=0\nCSET d0_power_consumed_factor=0\nCSET d0_power_dissipated=0\nCSET d0_power_dissipated_factor=0\nCSET d1_pme_support=true\nCSET d1_power_consumed=0\nCSET d1_power_consumed_factor=0\nCSET d1_power_dissipated=0\nCSET d1_power_dissipated_factor=0\nCSET d1_support=false\nCSET d2_pme_support=true\nCSET d2_power_consumed=0\nCSET d2_power_consumed_factor=0\nCSET d2_power_dissipated=0\nCSET d2_power_dissipated_factor=0\nCSET d2_support=false\nCSET d3_power_consumed=0\nCSET d3_power_consumed_factor=0\nCSET d3_power_dissipated=0\nCSET d3_power_dissipated_factor=0\nCSET d3cold_pme_support=false\nCSET d3hot_pme_support=true\nCSET de_emph=0\nCSET device_id=6018\nCSET device_port_type=PCI_Express_Endpoint_device\nCSET device_specific_initialization=false\nCSET disable_tx_aspm_l0s=false\nCSET dll_link_active_cap=false\nCSET downstream_link_num=00\nCSET dsn_enabled=true\nCSET en_route_err_cor=false\nCSET en_route_err_ftl=false\nCSET en_route_err_nfl=false\nCSET en_route_inta=false\nCSET en_route_intb=false\nCSET en_route_intc=false\nCSET en_route_intd=false\nCSET en_route_pm_pme=false\nCSET en_route_pme_to=false\nCSET en_route_pme_to_ack=false\nCSET en_route_unlock=false\nCSET enable_ack_nak_timer=false\nCSET enable_lane_reversal=false\nCSET enable_replay_timer=true\nCSET enable_slot_clock_cfg=false\nCSET expansion_rom_enabled=false\nCSET expansion_rom_scale=Kilobytes\nCSET expansion_rom_size=2\nCSET ext_pci_cfg_space=false\nCSET ext_pci_cfg_space_addr=3FF\nCSET extended_tag_field=false\nCSET force_no_scrambling=false\nCSET hw_auton_spd_disable=false\nCSET intx_generation=true\nCSET io_base_limit_registers=Disabled\nCSET legacy_interrupt=INTA\nCSET link_speed=2.5_GT/s\nCSET max_payload_size=512_bytes\nCSET maximum_link_width=X8\nCSET msi_64b=true\nCSET msi_enabled=true\nCSET msi_vec_mask=false\nCSET msix_enabled=false\nCSET msix_pba_bir=BAR_0\nCSET msix_pba_offset=0\nCSET msix_table_bir=BAR_0\nCSET msix_table_offset=0\nCSET msix_table_size=1\nCSET multiple_message_capable=1_vector\nCSET no_soft_reset=true\nCSET pci_cfg_space=false\nCSET pci_cfg_space_addr=3F\nCSET pcie_blk_locn=X0Y0\nCSET pcie_cap_slot_implemented=false\nCSET pcie_debug_ports=false\nCSET perf_level=High\nCSET phantom_functions=No_function_number_bits_used\nCSET pipe_pipeline=None\nCSET prefetchable_memory_base_limit_registers=Disabled\nCSET rcb=64_byte\nCSET ref_clk_freq=100_MHz\nCSET replay_timeout_func=Add\nCSET replay_timeout_value=0026\nCSET revision_id=00\nCSET root_cap_crs=false\nCSET slot_cap_attn_butn=false\nCSET slot_cap_attn_ind=false\nCSET slot_cap_elec_interlock=false\nCSET slot_cap_hotplug_cap=false\nCSET slot_cap_hotplug_surprise=false\nCSET slot_cap_mrl=false\nCSET slot_cap_no_cmd_comp_sup=false\nCSET slot_cap_physical_slot_num=0\nCSET slot_cap_pwr_ctrl=false\nCSET slot_cap_pwr_ind=false\nCSET slot_cap_pwr_limit_scale=0\nCSET slot_cap_pwr_limit_value=0\nCSET sub_class_interface_menu=Generic_XT_compatible_serial_controller\nCSET subsystem_id=0007\nCSET subsystem_vendor_id=10EE\nCSET trans_buf_pipeline=None\nCSET trgt_link_speed=4'h1\nCSET trim_tlp_digest=false\nCSET upconfigure_capable=true\nCSET user_clk_freq=250_default\nCSET vc_cap_enabled=false\nCSET vc_cap_reject_snoop=false\nCSET vendor_id=10EE\nCSET vsec_enabled=false\nCSET xlnx_ref_board=ML_605\n# END Parameters\n# BEGIN Extra information\nMISC pkg_timestamp=2013-06-08T22:50:04Z\n# END Extra information\nGENERATE\n# CRC: 2cdb8933\n" }, { "path": "hw/boards/ML605/ipcore_dir/pcie_endpoint.xise", "content": "\n\n\n
\n \n \n \n \n \n \n \n \n
\n\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n \n\n \n \n \n \n \n \n \n \n\n\n" }, { "path": "hw/boards/ML605/ipcore_dir/rdback_fifo.xco", "content": "##############################################################\n#\n# Xilinx Core Generator version 14.6\n# Date: Fri Feb 3 17:12:17 2017\n#\n##############################################################\n#\n# This file contains the customisation parameters for a\n# Xilinx CORE Generator IP GUI. It is strongly recommended\n# that you do not manually alter this file as it may cause\n# unexpected and unsupported behavior.\n#\n##############################################################\n#\n# Generated from component: xilinx.com:ip:fifo_generator:9.3\n#\n##############################################################\n#\n# BEGIN Project Options\nSET addpads = false\nSET asysymbol = true\nSET busformat = BusFormatAngleBracketNotRipped\nSET createndf = false\nSET designentry = Verilog\nSET device = xc6vlx240t\nSET devicefamily = virtex6\nSET flowvendor = Other\nSET formalverification = false\nSET foundationsym = false\nSET implementationfiletype = Ngc\nSET package = ff1156\nSET removerpms = false\nSET simulationfiles = Behavioral\nSET speedgrade = -1\nSET verilogsim = true\nSET vhdlsim = false\n# END Project Options\n# BEGIN Select\nSELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3\n# END Select\n# BEGIN Parameters\nCSET add_ngc_constraint_axi=false\nCSET almost_empty_flag=false\nCSET almost_full_flag=true\nCSET aruser_width=1\nCSET awuser_width=1\nCSET axi_address_width=32\nCSET axi_data_width=64\nCSET axi_type=AXI4_Stream\nCSET axis_type=FIFO\nCSET buser_width=1\nCSET clock_enable_type=Slave_Interface_Clock_Enable\nCSET clock_type_axi=Common_Clock\nCSET component_name=rdback_fifo\nCSET data_count=false\nCSET data_count_width=11\nCSET disable_timing_violations=false\nCSET disable_timing_violations_axi=false\nCSET dout_reset_value=0\nCSET empty_threshold_assert_value=4\nCSET empty_threshold_assert_value_axis=1022\nCSET empty_threshold_assert_value_rach=1022\nCSET empty_threshold_assert_value_rdch=1022\nCSET empty_threshold_assert_value_wach=1022\nCSET empty_threshold_assert_value_wdch=1022\nCSET empty_threshold_assert_value_wrch=1022\nCSET empty_threshold_negate_value=5\nCSET enable_aruser=false\nCSET enable_awuser=false\nCSET enable_buser=false\nCSET enable_common_overflow=false\nCSET enable_common_underflow=false\nCSET enable_data_counts_axis=false\nCSET enable_data_counts_rach=false\nCSET enable_data_counts_rdch=false\nCSET enable_data_counts_wach=false\nCSET enable_data_counts_wdch=false\nCSET enable_data_counts_wrch=false\nCSET enable_ecc=false\nCSET enable_ecc_axis=false\nCSET enable_ecc_rach=false\nCSET enable_ecc_rdch=false\nCSET enable_ecc_wach=false\nCSET enable_ecc_wdch=false\nCSET enable_ecc_wrch=false\nCSET enable_read_channel=false\nCSET enable_read_pointer_increment_by2=false\nCSET enable_reset_synchronization=true\nCSET enable_ruser=false\nCSET enable_tdata=false\nCSET enable_tdest=false\nCSET enable_tid=false\nCSET enable_tkeep=false\nCSET enable_tlast=false\nCSET enable_tready=true\nCSET enable_tstrobe=false\nCSET enable_tuser=false\nCSET enable_write_channel=false\nCSET enable_wuser=false\nCSET fifo_application_type_axis=Data_FIFO\nCSET fifo_application_type_rach=Data_FIFO\nCSET fifo_application_type_rdch=Data_FIFO\nCSET fifo_application_type_wach=Data_FIFO\nCSET fifo_application_type_wdch=Data_FIFO\nCSET fifo_application_type_wrch=Data_FIFO\nCSET fifo_implementation=Common_Clock_Block_RAM\nCSET fifo_implementation_axis=Common_Clock_Block_RAM\nCSET fifo_implementation_rach=Common_Clock_Block_RAM\nCSET fifo_implementation_rdch=Common_Clock_Block_RAM\nCSET fifo_implementation_wach=Common_Clock_Block_RAM\nCSET fifo_implementation_wdch=Common_Clock_Block_RAM\nCSET fifo_implementation_wrch=Common_Clock_Block_RAM\nCSET full_flags_reset_value=0\nCSET full_threshold_assert_value=1023\nCSET full_threshold_assert_value_axis=1023\nCSET full_threshold_assert_value_rach=1023\nCSET full_threshold_assert_value_rdch=1023\nCSET full_threshold_assert_value_wach=1023\nCSET full_threshold_assert_value_wdch=1023\nCSET full_threshold_assert_value_wrch=1023\nCSET full_threshold_negate_value=1022\nCSET id_width=4\nCSET inject_dbit_error=false\nCSET inject_dbit_error_axis=false\nCSET inject_dbit_error_rach=false\nCSET inject_dbit_error_rdch=false\nCSET inject_dbit_error_wach=false\nCSET inject_dbit_error_wdch=false\nCSET inject_dbit_error_wrch=false\nCSET inject_sbit_error=false\nCSET inject_sbit_error_axis=false\nCSET inject_sbit_error_rach=false\nCSET inject_sbit_error_rdch=false\nCSET inject_sbit_error_wach=false\nCSET inject_sbit_error_wdch=false\nCSET inject_sbit_error_wrch=false\nCSET input_data_width=256\nCSET input_depth=1024\nCSET input_depth_axis=1024\nCSET input_depth_rach=16\nCSET input_depth_rdch=1024\nCSET input_depth_wach=16\nCSET input_depth_wdch=1024\nCSET input_depth_wrch=16\nCSET interface_type=Native\nCSET output_data_width=256\nCSET output_depth=1024\nCSET overflow_flag=false\nCSET overflow_flag_axi=false\nCSET overflow_sense=Active_High\nCSET overflow_sense_axi=Active_High\nCSET performance_options=First_Word_Fall_Through\nCSET programmable_empty_type=No_Programmable_Empty_Threshold\nCSET programmable_empty_type_axis=No_Programmable_Empty_Threshold\nCSET programmable_empty_type_rach=No_Programmable_Empty_Threshold\nCSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold\nCSET programmable_empty_type_wach=No_Programmable_Empty_Threshold\nCSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold\nCSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold\nCSET programmable_full_type=No_Programmable_Full_Threshold\nCSET programmable_full_type_axis=No_Programmable_Full_Threshold\nCSET programmable_full_type_rach=No_Programmable_Full_Threshold\nCSET programmable_full_type_rdch=No_Programmable_Full_Threshold\nCSET programmable_full_type_wach=No_Programmable_Full_Threshold\nCSET programmable_full_type_wdch=No_Programmable_Full_Threshold\nCSET programmable_full_type_wrch=No_Programmable_Full_Threshold\nCSET rach_type=FIFO\nCSET rdch_type=FIFO\nCSET read_clock_frequency=1\nCSET read_data_count=false\nCSET read_data_count_width=11\nCSET register_slice_mode_axis=Fully_Registered\nCSET register_slice_mode_rach=Fully_Registered\nCSET register_slice_mode_rdch=Fully_Registered\nCSET register_slice_mode_wach=Fully_Registered\nCSET register_slice_mode_wdch=Fully_Registered\nCSET register_slice_mode_wrch=Fully_Registered\nCSET reset_pin=true\nCSET reset_type=Synchronous_Reset\nCSET ruser_width=1\nCSET synchronization_stages=2\nCSET synchronization_stages_axi=2\nCSET tdata_width=64\nCSET tdest_width=4\nCSET tid_width=8\nCSET tkeep_width=4\nCSET tstrb_width=4\nCSET tuser_width=4\nCSET underflow_flag=false\nCSET underflow_flag_axi=false\nCSET underflow_sense=Active_High\nCSET underflow_sense_axi=Active_High\nCSET use_clock_enable=false\nCSET use_dout_reset=true\nCSET use_embedded_registers=false\nCSET use_extra_logic=true\nCSET valid_flag=false\nCSET valid_sense=Active_High\nCSET wach_type=FIFO\nCSET wdch_type=FIFO\nCSET wrch_type=FIFO\nCSET write_acknowledge_flag=false\nCSET write_acknowledge_sense=Active_High\nCSET write_clock_frequency=1\nCSET write_data_count=false\nCSET write_data_count_width=11\nCSET wuser_width=1\n# END Parameters\n# BEGIN Extra information\nMISC pkg_timestamp=2012-11-19T12:39:56Z\n# END Extra information\nGENERATE\n# CRC: 38434af1\n" }, { "path": "hw/boards/ML605/ipcore_dir/rdback_fifo.xise", "content": "\n\n\n
\n \n \n \n \n \n \n \n \n
\n\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n\n \n\n \n \n \n \n \n \n \n \n\n\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/async_fifo.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tasync_fifo.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tAsynchronous capable parameterized FIFO. As with all\n// traditional FIFOs, the RD_DATA will be valid one cycle following a RD_EN \n// assertion. RD_EMPTY will remain low until the cycle following the last RD_EN \n// assertion. Note, that RD_EMPTY may actually be high on the same cycle that \n// RD_DATA contains valid data.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: Based on design by CE Cummings in Simulation and \n// Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer \n// Comparisons\n//-----------------------------------------------------------------------------\n\nmodule async_fifo #(\n\tparameter C_WIDTH = 32,\t// Data bus width\n\tparameter C_DEPTH = 1024,\t// Depth of the FIFO\n\t// Local parameters\n\tparameter C_REAL_DEPTH = 2**clog2(C_DEPTH),\n\tparameter C_DEPTH_BITS = clog2(C_REAL_DEPTH),\n\tparameter C_DEPTH_P1_BITS = clog2(C_REAL_DEPTH+1)\n)\n(\n\tinput RD_CLK,\t\t\t\t\t\t\t// Read clock\n\tinput RD_RST,\t\t\t\t\t\t\t// Read synchronous reset\n\tinput WR_CLK,\t\t\t\t\t\t \t// Write clock\n\tinput WR_RST,\t\t\t\t\t\t\t// Write synchronous reset\n\tinput [C_WIDTH-1:0] WR_DATA, \t\t\t// Write data input (WR_CLK)\n\tinput WR_EN, \t\t\t\t\t\t\t// Write enable, high active (WR_CLK)\n\toutput [C_WIDTH-1:0] RD_DATA, \t\t\t// Read data output (RD_CLK)\n\tinput RD_EN,\t\t\t\t\t\t\t// Read enable, high active (RD_CLK)\n\toutput WR_FULL, \t\t\t\t\t\t// Full condition (WR_CLK)\n\toutput RD_EMPTY \t\t\t\t\t\t// Empty condition (RD_CLK)\n);\n\n`include \"common_functions.v\"\n\nwire\t\t\t\t\t\twCmpEmpty;\nwire\t\t\t\t\t\twCmpFull;\nwire\t[C_DEPTH_BITS-1:0]\twWrPtr;\nwire\t[C_DEPTH_BITS-1:0]\twRdPtr;\nwire\t[C_DEPTH_BITS-1:0]\twWrPtrP1;\nwire\t[C_DEPTH_BITS-1:0]\twRdPtrP1;\n\n\n// Memory block (synthesis attributes applied to this module will\n// determine the memory option).\nram_2clk_1w_1r #(.C_RAM_WIDTH(C_WIDTH), .C_RAM_DEPTH(C_REAL_DEPTH)) mem (\n\t.CLKA(WR_CLK),\n\t.ADDRA(wWrPtr),\n\t.WEA(WR_EN & !WR_FULL),\n\t.DINA(WR_DATA),\n\t.CLKB(RD_CLK),\n\t.ADDRB(wRdPtr),\n\t.DOUTB(RD_DATA)\n);\n\n\n// Compare the pointers.\nasync_cmp #(.C_DEPTH_BITS(C_DEPTH_BITS)) asyncCompare (\n\t.WR_RST(WR_RST),\n\t.WR_CLK(WR_CLK),\n\t.RD_RST(RD_RST),\n\t.RD_CLK(RD_CLK),\n\t.RD_VALID(RD_EN & !RD_EMPTY),\n\t.WR_VALID(WR_EN & !WR_FULL),\n\t.EMPTY(wCmpEmpty), \n\t.FULL(wCmpFull),\n\t.WR_PTR(wWrPtr), \n\t.WR_PTR_P1(wWrPtrP1), \n\t.RD_PTR(wRdPtr), \n\t.RD_PTR_P1(wRdPtrP1)\n);\n\n\n// Calculate empty\nrd_ptr_empty #(.C_DEPTH_BITS(C_DEPTH_BITS)) rdPtrEmpty (\n\t.RD_EMPTY(RD_EMPTY), \n\t.RD_PTR(wRdPtr),\n\t.RD_PTR_P1(wRdPtrP1),\n\t.CMP_EMPTY(wCmpEmpty), \n\t.RD_EN(RD_EN),\n\t.RD_CLK(RD_CLK), \n\t.RD_RST(RD_RST)\n);\n\n\n// Calculate full\nwr_ptr_full #(.C_DEPTH_BITS(C_DEPTH_BITS)) wrPtrFull (\n\t.WR_CLK(WR_CLK), \n\t.WR_RST(WR_RST),\n\t.WR_EN(WR_EN),\n\t.WR_FULL(WR_FULL), \n\t.WR_PTR(wWrPtr),\n\t.WR_PTR_P1(wWrPtrP1),\n\t.CMP_FULL(wCmpFull)\n);\n \nendmodule\n\n\nmodule async_cmp #(\n parameter C_DEPTH_BITS = 4,\n // Local parameters\n parameter N = C_DEPTH_BITS-1\n)\n(\n\tinput WR_RST,\n\tinput WR_CLK,\n\tinput RD_RST,\n\tinput RD_CLK,\n\tinput RD_VALID,\n\tinput WR_VALID,\n\toutput EMPTY, \n\toutput FULL, \n\tinput [C_DEPTH_BITS-1:0] WR_PTR, \n\tinput [C_DEPTH_BITS-1:0] RD_PTR, \n\tinput [C_DEPTH_BITS-1:0] WR_PTR_P1, \n\tinput [C_DEPTH_BITS-1:0] RD_PTR_P1\n);\n \nreg\t\t\t\trDir=0;\nwire\t\t\twDirSet = ( (WR_PTR[N]^RD_PTR[N-1]) & ~(WR_PTR[N-1]^RD_PTR[N]));\nwire\t\t\twDirClr = ((~(WR_PTR[N]^RD_PTR[N-1]) & (WR_PTR[N-1]^RD_PTR[N])) | WR_RST);\n\nreg\t\t\t\trRdValid=0;\nreg\t\t\t\trEmpty=1;\nreg\t\t\t\trFull=0;\nwire\t\t\twATBEmpty = ((WR_PTR == RD_PTR_P1) && (RD_VALID | rRdValid));\nwire\t\t\twATBFull = ((WR_PTR_P1 == RD_PTR) && WR_VALID);\nwire\t\t\twEmpty = ((WR_PTR == RD_PTR) && !rDir);\nwire\t\t\twFull = ((WR_PTR == RD_PTR) && rDir);\n\nassign EMPTY = wATBEmpty || rEmpty;\nassign FULL = wATBFull || rFull;\n\nalways @(posedge wDirSet or posedge wDirClr)\nif (wDirClr) \n\trDir <= 1'b0;\nelse\n\trDir <= 1'b1;\n\nalways @(posedge RD_CLK) begin\n\trEmpty <= (RD_RST ? 1'd1 : wEmpty);\n\trRdValid <= (RD_RST ? 1'd0 : RD_VALID);\nend\n\nalways @(posedge WR_CLK) begin\n\trFull <= (WR_RST ? 1'd0 : wFull);\nend\n\nendmodule \n \n \nmodule rd_ptr_empty #(\n\tparameter C_DEPTH_BITS = 4\n)\n(\n\tinput RD_CLK, \n\tinput RD_RST,\n\tinput RD_EN, \n\toutput RD_EMPTY,\n\toutput [C_DEPTH_BITS-1:0] RD_PTR,\n\toutput [C_DEPTH_BITS-1:0] RD_PTR_P1,\n\tinput CMP_EMPTY \n);\n\nreg\t\t\t\t\t\t\trEmpty=1;\nreg\t\t\t\t\t\t\trEmpty2=1;\nreg\t\t[C_DEPTH_BITS-1:0]\trRdPtr=0;\nreg\t\t[C_DEPTH_BITS-1:0]\trRdPtrP1=0;\nreg\t\t[C_DEPTH_BITS-1:0]\trBin=0;\nreg\t\t[C_DEPTH_BITS-1:0]\trBinP1=1;\nwire\t[C_DEPTH_BITS-1:0]\twGrayNext;\nwire\t[C_DEPTH_BITS-1:0]\twGrayNextP1;\nwire\t[C_DEPTH_BITS-1:0]\twBinNext;\nwire\t[C_DEPTH_BITS-1:0]\twBinNextP1;\n\nassign RD_EMPTY = rEmpty;\nassign RD_PTR = rRdPtr;\nassign RD_PTR_P1 = rRdPtrP1;\n\n// Gray coded pointer\nalways @(posedge RD_CLK or posedge RD_RST) begin\n\tif (RD_RST) begin\n\t\trBin <= #1 0;\n\t\trBinP1 <= #1 1;\n\t\trRdPtr <= #1 0;\n\t\trRdPtrP1 <= #1 0;\n\tend\n\telse begin\n\t\trBin <= #1 wBinNext;\n\t\trBinP1 <= #1 wBinNextP1;\n\t\trRdPtr <= #1 wGrayNext;\n\t\trRdPtrP1 <= #1 wGrayNextP1;\n\tend\nend\n\n// Increment the binary count if not empty\nassign wBinNext = (!rEmpty ? rBin + RD_EN : rBin);\nassign wBinNextP1 = (!rEmpty ? rBinP1 + RD_EN : rBinP1);\nassign wGrayNext = ((wBinNext>>1) ^ wBinNext); // binary-to-gray conversion\nassign wGrayNextP1 = ((wBinNextP1>>1) ^ wBinNextP1); // binary-to-gray conversion\n\nalways @(posedge RD_CLK) begin\n\tif (CMP_EMPTY)\n\t\t{rEmpty, rEmpty2} <= #1 2'b11;\n\telse\n\t\t{rEmpty, rEmpty2} <= #1 {rEmpty2, CMP_EMPTY};\nend\n\nendmodule\n \n \nmodule wr_ptr_full #(\n\tparameter C_DEPTH_BITS = 4\n)\n(\n\tinput WR_CLK, \n\tinput WR_RST,\n\tinput WR_EN,\n\toutput WR_FULL, \n\toutput [C_DEPTH_BITS-1:0] WR_PTR, \n\toutput [C_DEPTH_BITS-1:0] WR_PTR_P1, \n\tinput CMP_FULL\n);\n\nreg\t\t\t\t\t\t\trFull=0;\nreg\t\t\t\t\t\t\trFull2=0;\nreg\t\t[C_DEPTH_BITS-1:0]\trPtr=0;\nreg\t\t[C_DEPTH_BITS-1:0]\trPtrP1=0;\nreg\t\t[C_DEPTH_BITS-1:0]\trBin=0;\nreg\t\t[C_DEPTH_BITS-1:0]\trBinP1=1;\nwire\t[C_DEPTH_BITS-1:0]\twGrayNext;\nwire\t[C_DEPTH_BITS-1:0]\twGrayNextP1;\nwire\t[C_DEPTH_BITS-1:0]\twBinNext;\nwire\t[C_DEPTH_BITS-1:0]\twBinNextP1;\n\nassign WR_FULL = rFull;\nassign WR_PTR = rPtr;\nassign WR_PTR_P1 = rPtrP1;\n\n// Gray coded pointer\nalways @(posedge WR_CLK or posedge WR_RST) begin\n\tif (WR_RST) begin\n\t\trBin <= #1 0;\n\t\trBinP1 <= #1 1;\n\t\trPtr <= #1 0;\n\t\trPtrP1 <= #1 0;\n\tend\n\telse begin\n\t\trBin <= #1 wBinNext;\n\t\trBinP1 <= #1 wBinNextP1;\n\t\trPtr <= #1 wGrayNext;\n\t\trPtrP1 <= #1 wGrayNextP1;\n\tend\nend\n\n// Increment the binary count if not full\nassign wBinNext = (!rFull ? rBin + WR_EN : rBin);\nassign wBinNextP1 = (!rFull ? rBinP1 + WR_EN : rBinP1);\nassign wGrayNext = ((wBinNext>>1) ^ wBinNext); // binary-to-gray conversion\nassign wGrayNextP1 = ((wBinNextP1>>1) ^ wBinNextP1); // binary-to-gray conversion\n\nalways @(posedge WR_CLK) begin\n\tif (WR_RST) \n\t\t{rFull, rFull2} <= #1 2'b00;\n\telse if (CMP_FULL) \n\t\t{rFull, rFull2} <= #1 2'b11;\n\telse\n\t\t{rFull, rFull2} <= #1 {rFull2, CMP_FULL};\nend\n\nendmodule\n\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/async_fifo_fwft.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tasync_fifo_fwft.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tAn asynchronous capable parameterized FIFO. As with all\n// first word fall through FIFOs, the RD_DATA will be valid when RD_EMPTY is \n// low. Asserting RD_EN will consume the current RD_DATA value and cause the \n// next value (if it exists) to appear on RD_DATA on the following cycle. Be sure \n// to check if RD_EMPTY is low each cycle to determine if RD_DATA is valid.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n\nmodule async_fifo_fwft #(\n\tparameter C_WIDTH = 32,\t// Data bus width\n\tparameter C_DEPTH = 1024,\t// Depth of the FIFO\n\t// Local parameters\n\tparameter C_REAL_DEPTH = 2**clog2(C_DEPTH),\n\tparameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),\n\tparameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1)\n)\n(\n\tinput RD_CLK,\t\t\t\t\t\t\t// Read clock\n\tinput RD_RST,\t\t\t\t\t\t\t// Read synchronous reset\n\tinput WR_CLK,\t\t\t\t\t\t \t// Write clock\n\tinput WR_RST,\t\t\t\t\t\t\t// Write synchronous reset\n\tinput [C_WIDTH-1:0] WR_DATA, \t\t\t// Write data input (WR_CLK)\n\tinput WR_EN, \t\t\t\t\t\t\t// Write enable, high active (WR_CLK)\n\toutput [C_WIDTH-1:0] RD_DATA, \t\t\t// Read data output (RD_CLK)\n\tinput RD_EN,\t\t\t\t\t\t\t// Read enable, high active (RD_CLK)\n\toutput WR_FULL, \t\t\t\t\t\t// Full condition (WR_CLK)\n\toutput RD_EMPTY \t\t\t\t\t\t// Empty condition (RD_CLK)\n);\n\n`include \"common_functions.v\"\n\nreg\t\t[C_WIDTH-1:0]\t\t\trData=0;\nreg\t\t[C_WIDTH-1:0]\t\t\trCache=0;\nreg\t\t[1:0]\t\t\t\t\trCount=0;\nreg\t\t\t\t\t\t\t\trFifoDataValid=0;\nreg\t\t\t\t\t\t\t\trDataValid=0;\nreg\t\t\t\t\t\t\t\trCacheValid=0;\nwire\t[C_WIDTH-1:0]\t\t\twData;\nwire\t\t\t\t\t\t\twEmpty;\nwire\t\t\t\t\t\t\twRen = RD_EN || (rCount < 2'd2);\n\n\nassign RD_DATA = rData;\nassign RD_EMPTY = !rDataValid;\n\n\n// Wrapped non-FWFT FIFO (synthesis attributes applied to this module will\n// determine the memory option).\nasync_fifo #(.C_WIDTH(C_WIDTH), .C_DEPTH(C_DEPTH)) fifo (\n\t.WR_CLK(WR_CLK),\n\t.WR_RST(WR_RST),\n\t.RD_CLK(RD_CLK),\n\t.RD_RST(RD_RST),\n\t.WR_EN(WR_EN),\n\t.WR_DATA(WR_DATA),\n\t.WR_FULL(WR_FULL),\n\t.RD_EN(wRen),\n\t.RD_DATA(wData),\n\t.RD_EMPTY(wEmpty)\n);\n\nalways @ (posedge RD_CLK) begin\n\tif (RD_RST) begin\n\t\trCount <= #1 0;\n\t\trDataValid <= #1 0;\n\t\trCacheValid <= #1 0;\n\t\trFifoDataValid <= #1 0;\n\tend\n\telse begin\n\t\t// Keep track of the count\n\t\trCount <= #1 rCount + (wRen & !wEmpty) - (!RD_EMPTY & RD_EN);\n\n\t\t// Signals when wData from FIFO is valid\n\t\trFifoDataValid <= #1 (wRen & !wEmpty);\n\n\t\t// Keep rData up to date\n\t\tif (rFifoDataValid) begin\n\t\t\tif (RD_EN | !rDataValid) begin\n\t\t\t\trData <= #1 wData;\n\t\t\t\trDataValid <= #1 1'd1;\n\t\t\t\trCacheValid <= #1 1'd0;\n\t\t\tend\n\t\t\telse begin\n\t\t\t\trCacheValid <= #1 1'd1;\n\t\t\tend\n\t\t\trCache <= #1 wData;\n\t\tend\n\t\telse begin\n\t\t\tif (RD_EN | !rDataValid) begin\n\t\t\t\trData <= #1 rCache;\n\t\t\t\trDataValid <= #1 rCacheValid;\n\t\t\t\trCacheValid <= #1 1'd0;\n\t\t\tend\n\t\tend\n\tend\nend\n \nendmodule\n " }, { "path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_rx.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : axi_basic_rx.v\n// Version : 2.4\n//----------------------------------------------------------------------------//\n// File: axi_basic_rx.v //\n// //\n// Description: //\n// TRN to AXI RX module. Instantiates pipeline and null generator RX //\n// submodules. //\n// //\n// Notes: //\n// Optional notes section. //\n// //\n// Hierarchical: //\n// axi_basic_top //\n// axi_basic_rx //\n// //\n//----------------------------------------------------------------------------//\n\n`timescale 1ps/1ps\n\nmodule axi_basic_rx #(\n parameter C_DATA_WIDTH = 128, // RX/TX interface data width\n parameter C_FAMILY = \"X7\", // Targeted FPGA family\n parameter C_ROOT_PORT = \"FALSE\", // PCIe block is in root port mode\n parameter C_PM_PRIORITY = \"FALSE\", // Disable TX packet boundary thrtl\n parameter TCQ = 1, // Clock to Q time\n\n // Do not override parameters below this line\n parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width\n parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width\n ) (\n //---------------------------------------------//\n // User Design I/O //\n //---------------------------------------------//\n\n // AXI RX\n //-----------\n output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user\n output m_axis_rx_tvalid, // RX data is valid\n input m_axis_rx_tready, // RX ready for data\n output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables\n output m_axis_rx_tlast, // RX data is last\n output [21:0] m_axis_rx_tuser, // RX user signals\n\n //---------------------------------------------//\n // PCIe Block I/O //\n //---------------------------------------------//\n\n // TRN RX\n //-----------\n input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block\n input trn_rsof, // RX start of packet\n input trn_reof, // RX end of packet\n input trn_rsrc_rdy, // RX source ready\n output trn_rdst_rdy, // RX destination ready\n input trn_rsrc_dsc, // RX source discontinue\n input [REM_WIDTH-1:0] trn_rrem, // RX remainder\n input trn_rerrfwd, // RX error forward\n input [6:0] trn_rbar_hit, // RX BAR hit\n input trn_recrc_err, // RX ECRC error\n\n // System\n //-----------\n output [2:0] np_counter, // Non-posted counter\n input user_clk, // user clock from block\n input user_rst // user reset from block\n);\n\n\n// Wires\nwire null_rx_tvalid;\nwire null_rx_tlast;\nwire [KEEP_WIDTH-1:0] null_rx_tkeep;\nwire null_rdst_rdy;\nwire [4:0] null_is_eof;\n\n//---------------------------------------------//\n// RX Data Pipeline //\n//---------------------------------------------//\n\naxi_basic_rx_pipeline #(\n .C_DATA_WIDTH( C_DATA_WIDTH ),\n .C_FAMILY( C_FAMILY ),\n .TCQ( TCQ ),\n\n .REM_WIDTH( REM_WIDTH ),\n .KEEP_WIDTH( KEEP_WIDTH )\n\n) rx_pipeline_inst (\n\n // Outgoing AXI TX\n //-----------\n .m_axis_rx_tdata( m_axis_rx_tdata ),\n .m_axis_rx_tvalid( m_axis_rx_tvalid ),\n .m_axis_rx_tready( m_axis_rx_tready ),\n .m_axis_rx_tkeep( m_axis_rx_tkeep ),\n .m_axis_rx_tlast( m_axis_rx_tlast ),\n .m_axis_rx_tuser( m_axis_rx_tuser ),\n\n // Incoming TRN RX\n //-----------\n .trn_rd( trn_rd ),\n .trn_rsof( trn_rsof ),\n .trn_reof( trn_reof ),\n .trn_rsrc_rdy( trn_rsrc_rdy ),\n .trn_rdst_rdy( trn_rdst_rdy ),\n .trn_rsrc_dsc( trn_rsrc_dsc ),\n .trn_rrem( trn_rrem ),\n .trn_rerrfwd( trn_rerrfwd ),\n .trn_rbar_hit( trn_rbar_hit ),\n .trn_recrc_err( trn_recrc_err ),\n\n // Null Inputs\n //-----------\n .null_rx_tvalid( null_rx_tvalid ),\n .null_rx_tlast( null_rx_tlast ),\n .null_rx_tkeep( null_rx_tkeep ),\n .null_rdst_rdy( null_rdst_rdy ),\n .null_is_eof( null_is_eof ),\n\n // System\n //-----------\n .np_counter( np_counter ),\n .user_clk( user_clk ),\n .user_rst( user_rst )\n);\n\n\n //---------------------------------------------//\n // RX Null Packet Generator //\n //---------------------------------------------//\n\n axi_basic_rx_null_gen #(\n .C_DATA_WIDTH( C_DATA_WIDTH ),\n .TCQ( TCQ ),\n\n .KEEP_WIDTH( KEEP_WIDTH )\n\n ) rx_null_gen_inst (\n\n // Inputs\n //-----------\n .m_axis_rx_tdata( m_axis_rx_tdata ),\n .m_axis_rx_tvalid( m_axis_rx_tvalid ),\n .m_axis_rx_tready( m_axis_rx_tready ),\n .m_axis_rx_tlast( m_axis_rx_tlast ),\n .m_axis_rx_tuser( m_axis_rx_tuser ),\n\n // Null Outputs\n //-----------\n .null_rx_tvalid( null_rx_tvalid ),\n .null_rx_tlast( null_rx_tlast ),\n .null_rx_tkeep( null_rx_tkeep ),\n .null_rdst_rdy( null_rdst_rdy ),\n .null_is_eof( null_is_eof ),\n\n // System\n //-----------\n .user_clk( user_clk ),\n .user_rst( user_rst )\n );\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_rx_null_gen.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : axi_basic_rx_null_gen.v\n// Version : 2.4\n//----------------------------------------------------------------------------//\n// File: axi_basic_rx_null_gen.v //\n// //\n// Description: //\n// TRN to AXI RX null generator. Generates null packets for use in //\n// discontinue situations. //\n// //\n// Notes: //\n// Optional notes section. //\n// //\n// Hierarchical: //\n// axi_basic_top //\n// axi_basic_rx //\n// axi_basic_rx_null_gen //\n// //\n//----------------------------------------------------------------------------//\n\n`timescale 1ps/1ps\n\nmodule axi_basic_rx_null_gen # (\n parameter C_DATA_WIDTH = 128, // RX/TX interface data width\n parameter TCQ = 1, // Clock to Q time\n\n // Do not override parameters below this line\n parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width\n ) (\n\n // AXI RX\n //-----------\n input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user\n input m_axis_rx_tvalid, // RX data is valid\n input m_axis_rx_tready, // RX ready for data\n input m_axis_rx_tlast, // RX data is last\n input [21:0] m_axis_rx_tuser, // RX user signals\n\n // Null Inputs\n //-----------\n output null_rx_tvalid, // NULL generated tvalid\n output null_rx_tlast, // NULL generated tlast\n output [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep\n output null_rdst_rdy, // NULL generated rdst_rdy\n output reg [4:0] null_is_eof, // NULL generated is_eof\n\n // System\n //-----------\n input user_clk, // user clock from block\n input user_rst // user reset from block\n);\n\n\nlocalparam INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 :\n (C_DATA_WIDTH == 64) ? 11'd2 : 11'd1;\n\n//----------------------------------------------------------------------------//\n// NULL packet generator state machine //\n// This state machine shadows the AXI RX interface, tracking each packet as //\n// it's passed to the AXI user. When a multi-cycle packet is detected, the //\n// state machine automatically generates a \"null\" packet. In the event of a //\n// discontinue, the RX pipeline can switch over to this null packet as //\n// necessary. //\n//----------------------------------------------------------------------------//\n\n// State machine variables and states\nlocalparam IDLE = 0;\nlocalparam IN_PACKET = 1;\nreg cur_state;\nreg next_state;\n\n// Signals for tracking a packet on the AXI interface\nreg [11:0] reg_pkt_len_counter;\nreg [11:0] pkt_len_counter;\nwire [11:0] pkt_len_counter_dec;\nwire pkt_done;\n\n// Calculate packet fields, which are needed to determine total packet length.\nwire [11:0] new_pkt_len;\nwire [9:0] payload_len;\nwire [1:0] packet_fmt;\nwire packet_td;\nreg [3:0] packet_overhead;\n\n// Misc.\nwire [KEEP_WIDTH-1:0] eof_tkeep;\nwire straddle_sof;\nwire eof;\n\n\n// Create signals to detect sof and eof situations. These signals vary depending\n// on data width.\nassign eof = m_axis_rx_tuser[21];\ngenerate\n if(C_DATA_WIDTH == 128) begin : sof_eof_128\n assign straddle_sof = (m_axis_rx_tuser[14:13] == 2'b11);\n end\n else begin : sof_eof_64_32\n assign straddle_sof = 1'b0;\n end\nendgenerate\n\n\n//----------------------------------------------------------------------------//\n// Calculate the length of the packet being presented on the RX interface. To //\n// do so, we need the relevent packet fields that impact total packet length. //\n// These are: //\n// - Header length: obtained from bit 1 of FMT field in 1st DWORD of header //\n// - Payload length: obtained from LENGTH field in 1st DWORD of header //\n// - TLP digist: obtained from TD field in 1st DWORD of header //\n// - Current data: the number of bytes that have already been presented //\n// on the data interface //\n// //\n// packet length = header + payload + tlp digest - # of DWORDS already //\n// transmitted //\n// //\n// packet_overhead is where we calculate everything except payload. //\n//----------------------------------------------------------------------------//\ngenerate\n if(C_DATA_WIDTH == 128) begin : len_calc_128\n assign packet_fmt = straddle_sof ?\n m_axis_rx_tdata[94:93] : m_axis_rx_tdata[30:29];\n assign packet_td = straddle_sof ?\n m_axis_rx_tdata[79] : m_axis_rx_tdata[15];\n assign payload_len = packet_fmt[1] ?\n (straddle_sof ? m_axis_rx_tdata[73:64] : m_axis_rx_tdata[9:0]) : 10'h0;\n\n always @(*) begin\n // In 128-bit mode, the amount of data currently on the interface\n // depends on whether we're straddling or not. If so, 2 DWORDs have been\n // seen. If not, 4 DWORDs.\n case({packet_fmt[0], packet_td, straddle_sof})\n // Header + TD - Data currently on interface\n 3'b0_0_0: packet_overhead = 4'd3 + 4'd0 - 4'd4;\n 3'b0_0_1: packet_overhead = 4'd3 + 4'd0 - 4'd2;\n 3'b0_1_0: packet_overhead = 4'd3 + 4'd1 - 4'd4;\n 3'b0_1_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;\n 3'b1_0_0: packet_overhead = 4'd4 + 4'd0 - 4'd4;\n 3'b1_0_1: packet_overhead = 4'd4 + 4'd0 - 4'd2;\n 3'b1_1_0: packet_overhead = 4'd4 + 4'd1 - 4'd4;\n 3'b1_1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;\n endcase\n end\n end\n else if(C_DATA_WIDTH == 64) begin : len_calc_64\n assign packet_fmt = m_axis_rx_tdata[30:29];\n assign packet_td = m_axis_rx_tdata[15];\n assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;\n\n always @(*) begin\n // 64-bit mode: no straddling, so always 2 DWORDs\n case({packet_fmt[0], packet_td})\n // Header + TD - Data currently on interface\n 2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd2;\n 2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;\n 2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd2;\n 2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;\n endcase\n end\n end\n else begin : len_calc_32\n assign packet_fmt = m_axis_rx_tdata[30:29];\n assign packet_td = m_axis_rx_tdata[15];\n assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;\n\n always @(*) begin\n // 32-bit mode: no straddling, so always 1 DWORD\n case({packet_fmt[0], packet_td})\n // Header + TD - Data currently on interface\n 2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd1;\n 2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd1;\n 2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd1;\n 2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd1;\n endcase\n end\n end\nendgenerate\n\n// Now calculate actual packet length, adding the packet overhead and the\n// payload length. This is signed math, so sign-extend packet_overhead.\n// NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this\n// behavior isn't supported in our block.\nassign new_pkt_len =\n {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};\n\n\n// Math signals needed in the state machine below. These are seperate wires to\n// help ensure synthesis tools sre smart about optimizing them.\nassign pkt_len_counter_dec = reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS;\nassign pkt_done = (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS);\n\n//----------------------------------------------------------------------------//\n// Null generator Mealy state machine. Determine outputs based on: //\n// 1) current st //\n// 2) current inp //\n//----------------------------------------------------------------------------//\nalways @(*) begin\n case (cur_state)\n\n // IDLE state: the interface is IDLE and we're waiting for a packet to\n // start. If a packet starts, move to state IN_PACKET and begin tracking\n // it as long as it's NOT a single cycle packet (indicated by assertion of\n // eof at packet start)\n IDLE: begin\n if(m_axis_rx_tvalid && m_axis_rx_tready && !eof) begin\n next_state = IN_PACKET;\n end\n else begin\n next_state = IDLE;\n end\n\n pkt_len_counter = new_pkt_len;\n end\n\n // IN_PACKET: a mutli-cycle packet is in progress and we're tracking it. We\n // are in lock-step with the AXI interface decrementing our packet length\n // tracking reg, and waiting for the packet to finish.\n //\n // * If packet finished and a new one starts, this is a straddle situation.\n // Next state is IN_PACKET (128-bit only).\n // * If the current packet is done, next state is IDLE.\n // * Otherwise, next state is IN_PACKET.\n IN_PACKET: begin\n // Straddle packet\n if((C_DATA_WIDTH == 128) && straddle_sof && m_axis_rx_tvalid) begin\n pkt_len_counter = new_pkt_len;\n next_state = IN_PACKET;\n end\n\n // Current packet finished\n else if(m_axis_rx_tready && pkt_done)\n begin\n pkt_len_counter = new_pkt_len;\n next_state = IDLE;\n end\n\n // Packet in progress\n else begin\n if(m_axis_rx_tready) begin\n // Not throttled\n pkt_len_counter = pkt_len_counter_dec;\n end\n else begin\n // Throttled\n pkt_len_counter = reg_pkt_len_counter;\n end\n\n next_state = IN_PACKET;\n end\n end\n\n default: begin\n pkt_len_counter = reg_pkt_len_counter;\n next_state = IDLE;\n end\n endcase\nend\n\n\n// Synchronous NULL packet generator state machine logic\nalways @(posedge user_clk) begin\n if(user_rst) begin\n cur_state <= #TCQ IDLE;\n reg_pkt_len_counter <= #TCQ 12'h0;\n end\n else begin\n cur_state <= #TCQ next_state;\n reg_pkt_len_counter <= #TCQ pkt_len_counter;\n end\nend\n\n\n// Generate tkeep/is_eof for an end-of-packet situation.\ngenerate\n if(C_DATA_WIDTH == 128) begin : strb_calc_128\n always @(*) begin\n // Assign null_is_eof depending on how many DWORDs are left in the\n // packet.\n case(pkt_len_counter)\n 10'd1: null_is_eof = 5'b10011;\n 10'd2: null_is_eof = 5'b10111;\n 10'd3: null_is_eof = 5'b11011;\n 10'd4: null_is_eof = 5'b11111;\n default: null_is_eof = 5'b00011;\n endcase\n end\n\n // tkeep not used in 128-bit interface\n assign eof_tkeep = {KEEP_WIDTH{1'b0}};\n end\n else if(C_DATA_WIDTH == 64) begin : strb_calc_64\n always @(*) begin\n // Assign null_is_eof depending on how many DWORDs are left in the\n // packet.\n case(pkt_len_counter)\n 10'd1: null_is_eof = 5'b10011;\n 10'd2: null_is_eof = 5'b10111;\n default: null_is_eof = 5'b00011;\n endcase\n end\n\n // Assign tkeep to 0xFF or 0x0F depending on how many DWORDs are left in\n // the current packet.\n assign eof_tkeep = { ((pkt_len_counter == 12'd2) ? 4'hF:4'h0), 4'hF };\n end\n else begin : strb_calc_32\n always @(*) begin\n // is_eof is either on or off for 32-bit\n if(pkt_len_counter == 12'd1) begin\n null_is_eof = 5'b10011;\n end\n else begin\n null_is_eof = 5'b00011;\n end\n end\n\n // The entire DWORD is always valid in 32-bit mode, so tkeep is always 0xF\n assign eof_tkeep = 4'hF;\n end\nendgenerate\n\n\n// Finally, use everything we've generated to calculate our NULL outputs\nassign null_rx_tvalid = 1'b1;\nassign null_rx_tlast = (pkt_len_counter <= INTERFACE_WIDTH_DWORDS);\nassign null_rx_tkeep = null_rx_tlast ? eof_tkeep : {KEEP_WIDTH{1'b1}};\nassign null_rdst_rdy = null_rx_tlast;\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_rx_pipeline.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : axi_basic_rx_pipeline.v\n// Version : 2.4\n//----------------------------------------------------------------------------//\n// File: axi_basic_rx_pipeline.v //\n// //\n// Description: //\n// TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI. //\n// //\n// Notes: //\n// Optional notes section. //\n// //\n// Hierarchical: //\n// axi_basic_top //\n// axi_basic_rx //\n// axi_basic_rx_pipeline //\n// //\n//----------------------------------------------------------------------------//\n\n`timescale 1ps/1ps\n\nmodule axi_basic_rx_pipeline #(\n parameter C_DATA_WIDTH = 128, // RX/TX interface data width\n parameter C_FAMILY = \"X7\", // Targeted FPGA family\n parameter TCQ = 1, // Clock to Q time\n\n // Do not override parameters below this line\n parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width\n parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width\n ) (\n\n // AXI RX\n //-----------\n output reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user\n output reg m_axis_rx_tvalid, // RX data is valid\n input m_axis_rx_tready, // RX ready for data\n output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables\n output m_axis_rx_tlast, // RX data is last\n output reg [21:0] m_axis_rx_tuser, // RX user signals\n\n // TRN RX\n //-----------\n input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block\n input trn_rsof, // RX start of packet\n input trn_reof, // RX end of packet\n input trn_rsrc_rdy, // RX source ready\n output reg trn_rdst_rdy, // RX destination ready\n input trn_rsrc_dsc, // RX source discontinue\n input [REM_WIDTH-1:0] trn_rrem, // RX remainder\n input trn_rerrfwd, // RX error forward\n input [6:0] trn_rbar_hit, // RX BAR hit\n input trn_recrc_err, // RX ECRC error\n\n // Null Inputs\n //-----------\n input null_rx_tvalid, // NULL generated tvalid\n input null_rx_tlast, // NULL generated tlast\n input [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep\n input null_rdst_rdy, // NULL generated rdst_rdy\n input [4:0] null_is_eof, // NULL generated is_eof\n\n // System\n //-----------\n output [2:0] np_counter, // Non-posted counter\n input user_clk, // user clock from block\n input user_rst // user reset from block\n);\n\n\n// Wires and regs for creating AXI signals\nwire [4:0] is_sof;\nwire [4:0] is_sof_prev;\n\nwire [4:0] is_eof;\nwire [4:0] is_eof_prev;\n\nreg [KEEP_WIDTH-1:0] reg_tkeep;\nwire [KEEP_WIDTH-1:0] tkeep;\nwire [KEEP_WIDTH-1:0] tkeep_prev;\n\nreg reg_tlast;\nwire rsrc_rdy_filtered;\n\n// Wires and regs for previous value buffer\nwire [C_DATA_WIDTH-1:0] trn_rd_DW_swapped;\nreg [C_DATA_WIDTH-1:0] trn_rd_prev;\n\nwire data_hold;\nreg data_prev;\n\nreg trn_reof_prev;\nreg [REM_WIDTH-1:0] trn_rrem_prev;\nreg trn_rsrc_rdy_prev;\nreg trn_rsrc_dsc_prev;\nreg trn_rsof_prev;\nreg [6:0] trn_rbar_hit_prev;\nreg trn_rerrfwd_prev;\nreg trn_recrc_err_prev;\n\n// Null packet handling signals\nreg null_mux_sel;\nreg trn_in_packet;\nwire dsc_flag;\nwire dsc_detect;\nreg reg_dsc_detect;\nreg trn_rsrc_dsc_d;\n\n\n// Create \"filtered\" version of rsrc_rdy, where discontinued SOFs are removed.\nassign rsrc_rdy_filtered = trn_rsrc_rdy &&\n (trn_in_packet || (trn_rsof && !trn_rsrc_dsc));\n\n//----------------------------------------------------------------------------//\n// Previous value buffer //\n// --------------------- //\n// We are inserting a pipeline stage in between TRN and AXI, which causes //\n// some issues with handshaking signals m_axis_rx_tready/trn_rdst_rdy. The //\n// added cycle of latency in the path causes the user design to fall behind //\n// the TRN interface whenever it throttles. //\n// //\n// To avoid loss of data, we must keep the previous value of all trn_r* //\n// signals in case the user throttles. //\n//----------------------------------------------------------------------------//\nalways @(posedge user_clk) begin\n if(user_rst) begin\n trn_rd_prev <= #TCQ {C_DATA_WIDTH{1'b0}};\n trn_rsof_prev <= #TCQ 1'b0;\n trn_rrem_prev <= #TCQ {REM_WIDTH{1'b0}};\n trn_rsrc_rdy_prev <= #TCQ 1'b0;\n trn_rbar_hit_prev <= #TCQ 7'h00;\n trn_rerrfwd_prev <= #TCQ 1'b0;\n trn_recrc_err_prev <= #TCQ 1'b0;\n trn_reof_prev <= #TCQ 1'b0;\n trn_rsrc_dsc_prev <= #TCQ 1'b0;\n end\n else begin\n // prev buffer works by checking trn_rdst_rdy. When trn_rdst_rdy is\n // asserted, a new value is present on the interface.\n if(trn_rdst_rdy) begin\n trn_rd_prev <= #TCQ trn_rd_DW_swapped;\n trn_rsof_prev <= #TCQ trn_rsof;\n trn_rrem_prev <= #TCQ trn_rrem;\n trn_rbar_hit_prev <= #TCQ trn_rbar_hit;\n trn_rerrfwd_prev <= #TCQ trn_rerrfwd;\n trn_recrc_err_prev <= #TCQ trn_recrc_err;\n trn_rsrc_rdy_prev <= #TCQ rsrc_rdy_filtered;\n trn_reof_prev <= #TCQ trn_reof;\n trn_rsrc_dsc_prev <= #TCQ trn_rsrc_dsc || dsc_flag;\n end\n end\nend\n\n\n//----------------------------------------------------------------------------//\n// Create TDATA //\n//----------------------------------------------------------------------------//\n\n// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN\n// 128-bit: 64-bit: 32-bit:\n// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0\n// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0\n// TRN DW2 maps to AXI DW1\n// TRN DW3 maps to AXI DW0\ngenerate\n if(C_DATA_WIDTH == 128) begin : rd_DW_swap_128\n assign trn_rd_DW_swapped = {trn_rd[31:0],\n trn_rd[63:32],\n trn_rd[95:64],\n trn_rd[127:96]};\n end\n else if(C_DATA_WIDTH == 64) begin : rd_DW_swap_64\n assign trn_rd_DW_swapped = {trn_rd[31:0], trn_rd[63:32]};\n end\n else begin : rd_DW_swap_32\n assign trn_rd_DW_swapped = trn_rd;\n end\nendgenerate\n\n\n// Create special buffer which locks in the proper value of TDATA depending\n// on whether the user is throttling or not. This buffer has three states:\n//\n// HOLD state: TDATA maintains its current value\n// - the user has throttled the PCIe block\n// PREVIOUS state: the buffer provides the previous value on trn_rd\n// - the user has finished throttling, and is a little behind\n// the PCIe block\n// CURRENT state: the buffer passes the current value on trn_rd\n// - the user is caught up and ready to receive the latest\n// data from the PCIe block\nalways @(posedge user_clk) begin\n if(user_rst) begin\n m_axis_rx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};\n end\n else begin\n if(!data_hold) begin\n // PREVIOUS state\n if(data_prev) begin\n m_axis_rx_tdata <= #TCQ trn_rd_prev;\n end\n\n // CURRENT state\n else begin\n m_axis_rx_tdata <= #TCQ trn_rd_DW_swapped;\n end\n end\n // else HOLD state\n end\nend\n\n// Logic to instruct pipeline to hold its value\nassign data_hold = (!m_axis_rx_tready && m_axis_rx_tvalid);\n\n// Logic to instruct pipeline to use previous bus values. Always use previous\n// value after holding a value.\nalways @(posedge user_clk) begin\n if(user_rst) begin\n data_prev <= #TCQ 1'b0;\n end\n else begin\n data_prev <= #TCQ data_hold;\n end\nend\n\n\n//----------------------------------------------------------------------------//\n// Create TVALID, TLAST, tkeep, TUSER //\n// ----------------------------------- //\n// Use the same strategy for these signals as for TDATA, except here we need //\n// an extra provision for null packets. //\n//----------------------------------------------------------------------------//\nalways @(posedge user_clk) begin\n if(user_rst) begin\n m_axis_rx_tvalid <= #TCQ 1'b0;\n reg_tlast <= #TCQ 1'b0;\n reg_tkeep <= #TCQ {KEEP_WIDTH{1'b1}};\n m_axis_rx_tuser <= #TCQ 22'h0;\n end\n else begin\n if(!data_hold) begin\n // If in a null packet, use null generated value\n if(null_mux_sel) begin\n m_axis_rx_tvalid <= #TCQ null_rx_tvalid;\n reg_tlast <= #TCQ null_rx_tlast;\n reg_tkeep <= #TCQ null_rx_tkeep;\n m_axis_rx_tuser <= #TCQ {null_is_eof, 17'h0000};\n end\n\n // PREVIOUS state\n else if(data_prev) begin\n m_axis_rx_tvalid <= #TCQ (trn_rsrc_rdy_prev || dsc_flag);\n reg_tlast <= #TCQ trn_reof_prev;\n reg_tkeep <= #TCQ tkeep_prev;\n m_axis_rx_tuser <= #TCQ {is_eof_prev, // TUSER bits [21:17]\n 2'b00, // TUSER bits [16:15]\n is_sof_prev, // TUSER bits [14:10]\n 1'b0, // TUSER bit [9]\n trn_rbar_hit_prev, // TUSER bits [8:2]\n trn_rerrfwd_prev, // TUSER bit [1]\n trn_recrc_err_prev}; // TUSER bit [0]\n end\n\n // CURRENT state\n else begin\n m_axis_rx_tvalid <= #TCQ (rsrc_rdy_filtered || dsc_flag);\n reg_tlast <= #TCQ trn_reof;\n reg_tkeep <= #TCQ tkeep;\n m_axis_rx_tuser <= #TCQ {is_eof, // TUSER bits [21:17]\n 2'b00, // TUSER bits [16:15]\n is_sof, // TUSER bits [14:10]\n 1'b0, // TUSER bit [9]\n trn_rbar_hit, // TUSER bits [8:2]\n trn_rerrfwd, // TUSER bit [1]\n trn_recrc_err}; // TUSER bit [0]\n end\n end\n // else HOLD state\n end\nend\n\n// Hook up TLAST and tkeep depending on interface width\ngenerate\n // For 128-bit interface, don't pass TLAST and tkeep to user (is_eof and\n // is_data passed to user instead). reg_tlast is still used internally.\n if(C_DATA_WIDTH == 128) begin : tlast_tkeep_hookup_128\n assign m_axis_rx_tlast = 1'b0;\n assign m_axis_rx_tkeep = {KEEP_WIDTH{1'b1}};\n end\n\n // For 64/32-bit interface, pass TLAST to user.\n else begin : tlast_tkeep_hookup_64_32\n assign m_axis_rx_tlast = reg_tlast;\n assign m_axis_rx_tkeep = reg_tkeep;\n end\nendgenerate\n\n\n//----------------------------------------------------------------------------//\n// Create tkeep //\n// ------------ //\n// Convert RREM to STRB. Here, we are converting the encoding method for the //\n// location of the EOF from TRN flavor (rrem) to AXI (tkeep). //\n// //\n// NOTE: for each configuration, we need two values of tkeep, the current and //\n// previous values. The need for these two values is described below. //\n//----------------------------------------------------------------------------//\ngenerate\n if(C_DATA_WIDTH == 128) begin : rrem_to_tkeep_128\n // TLAST and tkeep not used in 128-bit interface. is_sof and is_eof used\n // instead.\n assign tkeep = 16'h0000;\n assign tkeep_prev = 16'h0000;\n end\n else if(C_DATA_WIDTH == 64) begin : rrem_to_tkeep_64\n // 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes\n // - tkeep has only two possible values here, 0xFF or 0x0F\n assign tkeep = trn_rrem ? 8'hFF : 8'h0F;\n assign tkeep_prev = trn_rrem_prev ? 8'hFF : 8'h0F;\n end\n else begin : rrem_to_tkeep_32\n // 32-bit interface: contains 1 DWORD per cycle, for a total of 4 bytes\n // - tkeep is always 0xF in this case, due to the nature of the PCIe block\n assign tkeep = 4'hF;\n assign tkeep_prev = 4'hF;\n end\nendgenerate\n\n\n//----------------------------------------------------------------------------//\n// Create is_sof //\n// ------------- //\n// is_sof is a signal to the user indicating the location of SOF in TDATA . //\n// Due to inherent 64-bit alignment of packets from the block, the only //\n// possible values are: //\n// Value Valid data widths //\n// 5'b11000 (sof @ byte 8) 128 //\n// 5'b10000 (sof @ byte 0) 128, 64, 32 //\n// 5'b00000 (sof not present) 128, 64, 32 //\n//----------------------------------------------------------------------------//\ngenerate\n if(C_DATA_WIDTH == 128) begin : is_sof_128\n assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable\n (trn_rsof && !trn_rrem[1]), // bit 3: sof @ byte 8?\n 3'b000}; // bit 2-0: hardwired 0\n\n assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4\n (trn_rsof_prev && !trn_rrem_prev[1]), // bit 3\n 3'b000}; // bit 2-0\n end\n else begin : is_sof_64_32\n assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable\n 4'b0000}; // bit 3-0: hardwired 0\n\n assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4\n 4'b0000}; // bit 3-0\n end\nendgenerate\n\n\n//----------------------------------------------------------------------------//\n// Create is_eof //\n// ------------- //\n// is_eof is a signal to the user indicating the location of EOF in TDATA . //\n// Due to DWORD granularity of packets from the block, the only //\n// possible values are: //\n// Value Valid data widths //\n// 5'b11111 (eof @ byte 15) 128 //\n// 5'b11011 (eof @ byte 11) 128 //\n// 5'b10111 (eof @ byte 7) 128, 64 //\n// 5'b10011 (eof @ byte 3)` 128, 64, 32 //\n// 5'b00011 (eof not present) 128, 64, 32 //\n//----------------------------------------------------------------------------//\ngenerate\n if(C_DATA_WIDTH == 128) begin : is_eof_128\n assign is_eof = {trn_reof, // bit 4: enable\n trn_rrem, // bit 3-2: encoded eof loc rom block\n 2'b11}; // bit 1-0: hardwired 1\n\n assign is_eof_prev = {trn_reof_prev, // bit 4: enable\n trn_rrem_prev, // bit 3-2: encoded eof loc from block\n 2'b11}; // bit 1-0: hardwired 1\n end\n else if(C_DATA_WIDTH == 64) begin : is_eof_64\n assign is_eof = {trn_reof, // bit 4: enable\n 1'b0, // bit 3: hardwired 0\n trn_rrem, // bit 2: encoded eof loc from block\n 2'b11}; // bit 1-0: hardwired 1\n\n assign is_eof_prev = {trn_reof_prev, // bit 4: enable\n 1'b0, // bit 3: hardwired 0\n trn_rrem_prev, // bit 2: encoded eof loc from block\n 2'b11}; // bit 1-0: hardwired 1\n end\n else begin : is_eof_32\n assign is_eof = {trn_reof, // bit 4: enable\n 4'b0011}; // bit 3-0: hardwired to byte 3\n\n assign is_eof_prev = {trn_reof_prev, // bit 4: enable\n 4'b0011}; // bit 3-0: hardwired to byte 3\n end\nendgenerate\n\n\n\n//----------------------------------------------------------------------------//\n// Create trn_rdst_rdy //\n//----------------------------------------------------------------------------//\nalways @(posedge user_clk) begin\n if(user_rst) begin\n trn_rdst_rdy <= #TCQ 1'b0;\n end\n else begin\n // If in a null packet, use null generated value\n if(null_mux_sel && m_axis_rx_tready) begin\n trn_rdst_rdy <= #TCQ null_rdst_rdy;\n end\n\n // If a discontinue needs to be serviced, throttle the block until we are\n // ready to pad out the packet.\n else if(dsc_flag) begin\n trn_rdst_rdy <= #TCQ 1'b0;\n end\n\n // If in a packet, pass user back-pressure directly to block\n else if(m_axis_rx_tvalid) begin\n trn_rdst_rdy <= #TCQ m_axis_rx_tready;\n end\n\n // If idle, default to no back-pressure. We need to default to the\n // \"ready to accept data\" state to make sure we catch the first\n // clock of data of a new packet.\n else begin\n trn_rdst_rdy <= #TCQ 1'b1;\n end\n end\nend\n\n//----------------------------------------------------------------------------//\n// Create null_mux_sel //\n// null_mux_sel is the signal used to detect a discontinue situation and //\n// mux in the null packet generated in rx_null_gen. Only mux in null data //\n// when not at the beginningof a packet. SOF discontinues do not require //\n// padding, as the whole packet is simply squashed instead. //\n//----------------------------------------------------------------------------//\nalways @(posedge user_clk) begin\n if(user_rst) begin\n null_mux_sel <= #TCQ 1'b0;\n end\n else begin\n // NULL packet done\n if(null_mux_sel && null_rx_tlast && m_axis_rx_tready)\n begin\n null_mux_sel <= #TCQ 1'b0;\n end\n\n // Discontinue detected and we're in packet, so switch to NULL packet\n else if(dsc_flag && !data_hold) begin\n null_mux_sel <= #TCQ 1'b1;\n end\n end\nend\n\n\n//----------------------------------------------------------------------------//\n// Create discontinue tracking signals //\n//----------------------------------------------------------------------------//\n// Create signal trn_in_packet, which is needed to validate trn_rsrc_dsc. We\n// should ignore trn_rsrc_dsc when it's asserted out-of-packet.\nalways @(posedge user_clk) begin\n if(user_rst) begin\n trn_in_packet <= #TCQ 1'b0;\n end\n else begin\n if(trn_rsof && !trn_reof && rsrc_rdy_filtered && trn_rdst_rdy)\n begin\n trn_in_packet <= #TCQ 1'b1;\n end\n else if(trn_rsrc_dsc) begin\n trn_in_packet <= #TCQ 1'b0;\n end\n else if(trn_reof && !trn_rsof && trn_rsrc_rdy && trn_rdst_rdy) begin\n trn_in_packet <= #TCQ 1'b0;\n end\n end\nend\n\n\n// Create dsc_flag, which identifies and stores mid-packet discontinues that\n// require null packet padding. This signal is edge sensitive to trn_rsrc_dsc,\n// to make sure we don't service the same dsc twice in the event that\n// trn_rsrc_dsc stays asserted for longer than it takes to pad out the packet.\nassign dsc_detect = trn_rsrc_dsc && !trn_rsrc_dsc_d && trn_in_packet &&\n (!trn_rsof || trn_reof) && !(trn_rdst_rdy && trn_reof);\n\nalways @(posedge user_clk) begin\n if(user_rst) begin\n reg_dsc_detect <= #TCQ 1'b0;\n trn_rsrc_dsc_d <= #TCQ 1'b0;\n end\n else begin\n if(dsc_detect) begin\n reg_dsc_detect <= #TCQ 1'b1;\n end\n else if(null_mux_sel) begin\n reg_dsc_detect <= #TCQ 1'b0;\n end\n\n trn_rsrc_dsc_d <= #TCQ trn_rsrc_dsc;\n end\nend\n\nassign dsc_flag = dsc_detect || reg_dsc_detect;\n\n\n\n//----------------------------------------------------------------------------//\n// Create np_counter (V6 128-bit only). This counter tells the V6 128-bit //\n// interface core how many NP packets have left the RX pipeline. The V6 //\n// 128-bit interface uses this count to perform rnp_ok modulation. //\n//----------------------------------------------------------------------------//\ngenerate\n if(C_FAMILY == \"V6\" && C_DATA_WIDTH == 128) begin : np_cntr_to_128_enabled\n reg [2:0] reg_np_counter;\n\n // Look for NP packets beginning on lower (i.e. unaligned) start\n wire mrd_lower = (!(|m_axis_rx_tdata[92:88]) && !m_axis_rx_tdata[94]);\n wire mrd_lk_lower = (m_axis_rx_tdata[92:88] == 5'b00001);\n wire io_rdwr_lower = (m_axis_rx_tdata[92:88] == 5'b00010);\n wire cfg_rdwr_lower = (m_axis_rx_tdata[92:89] == 4'b0010);\n wire atomic_lower = ((&m_axis_rx_tdata[91:90]) && m_axis_rx_tdata[94]);\n\n wire np_pkt_lower = (mrd_lower ||\n mrd_lk_lower ||\n io_rdwr_lower ||\n cfg_rdwr_lower ||\n atomic_lower) && m_axis_rx_tuser[13];\n\n // Look for NP packets beginning on upper (i.e. aligned) start\n wire mrd_upper = (!(|m_axis_rx_tdata[28:24]) && !m_axis_rx_tdata[30]);\n wire mrd_lk_upper = (m_axis_rx_tdata[28:24] == 5'b00001);\n wire io_rdwr_upper = (m_axis_rx_tdata[28:24] == 5'b00010);\n wire cfg_rdwr_upper = (m_axis_rx_tdata[28:25] == 4'b0010);\n wire atomic_upper = ((&m_axis_rx_tdata[27:26]) && m_axis_rx_tdata[30]);\n\n wire np_pkt_upper = (mrd_upper ||\n mrd_lk_upper ||\n io_rdwr_upper ||\n cfg_rdwr_upper ||\n atomic_upper) && !m_axis_rx_tuser[13];\n\n wire pkt_accepted =\n m_axis_rx_tuser[14] && m_axis_rx_tready && m_axis_rx_tvalid;\n\n // Increment counter whenever an NP packet leaves the RX pipeline\n always @(posedge user_clk) begin\n if (user_rst) begin\n reg_np_counter <= #TCQ 0;\n end\n else begin\n if((np_pkt_lower || np_pkt_upper) && pkt_accepted)\n begin\n reg_np_counter <= #TCQ reg_np_counter + 3'h1;\n end\n end\n end\n\n assign np_counter = reg_np_counter;\n end\n else begin : np_cntr_to_128_disabled\n assign np_counter = 3'h0;\n end\nendgenerate\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_top.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : axi_basic_top.v\n// Version : 2.4\n//----------------------------------------------------------------------------//\n// File: axi_basic_top.v //\n// //\n// Description: //\n// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //\n// //\n// Notes: //\n// Optional notes section. //\n// //\n// Hierarchical: //\n// axi_basic_top //\n// //\n//----------------------------------------------------------------------------//\n\n`timescale 1ps/1ps\n\nmodule axi_basic_top #(\n parameter C_DATA_WIDTH = 128, // RX/TX interface data width\n parameter C_FAMILY = \"X7\", // Targeted FPGA family\n parameter C_ROOT_PORT = \"FALSE\", // PCIe block is in root port mode\n parameter C_PM_PRIORITY = \"FALSE\", // Disable TX packet boundary thrtl\n parameter TCQ = 1, // Clock to Q time\n\n // Do not override parameters below this line\n parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width\n parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width\n ) (\n //---------------------------------------------//\n // User Design I/O //\n //---------------------------------------------//\n\n // AXI TX\n //-----------\n input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user\n input s_axis_tx_tvalid, // TX data is valid\n output s_axis_tx_tready, // TX ready for data\n input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables\n input s_axis_tx_tlast, // TX data is last\n input [3:0] s_axis_tx_tuser, // TX user signals\n\n // AXI RX\n //-----------\n output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user\n output m_axis_rx_tvalid, // RX data is valid\n input m_axis_rx_tready, // RX ready for data\n output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables\n output m_axis_rx_tlast, // RX data is last\n output [21:0] m_axis_rx_tuser, // RX user signals\n\n // User Misc.\n //-----------\n input user_turnoff_ok, // Turnoff OK from user\n input user_tcfg_gnt, // Send cfg OK from user\n\n //---------------------------------------------//\n // PCIe Block I/O //\n //---------------------------------------------//\n\n // TRN TX\n //-----------\n output [C_DATA_WIDTH-1:0] trn_td, // TX data from block\n output trn_tsof, // TX start of packet\n output trn_teof, // TX end of packet\n output trn_tsrc_rdy, // TX source ready\n input trn_tdst_rdy, // TX destination ready\n output trn_tsrc_dsc, // TX source discontinue\n output [REM_WIDTH-1:0] trn_trem, // TX remainder\n output trn_terrfwd, // TX error forward\n output trn_tstr, // TX streaming enable\n input [5:0] trn_tbuf_av, // TX buffers available\n output trn_tecrc_gen, // TX ECRC generate\n\n // TRN RX\n //-----------\n input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block\n input trn_rsof, // RX start of packet\n input trn_reof, // RX end of packet\n input trn_rsrc_rdy, // RX source ready\n output trn_rdst_rdy, // RX destination ready\n input trn_rsrc_dsc, // RX source discontinue\n input [REM_WIDTH-1:0] trn_rrem, // RX remainder\n input trn_rerrfwd, // RX error forward\n input [6:0] trn_rbar_hit, // RX BAR hit\n input trn_recrc_err, // RX ECRC error\n\n // TRN Misc.\n //-----------\n input trn_tcfg_req, // TX config request\n output trn_tcfg_gnt, // RX config grant\n input trn_lnk_up, // PCIe link up\n\n // 7 Series/Virtex6 PM\n //-----------\n input [2:0] cfg_pcie_link_state, // Encoded PCIe link state\n\n // Virtex6 PM\n //-----------\n input cfg_pm_send_pme_to, // PM send PME turnoff msg\n input [1:0] cfg_pmcsr_powerstate, // PMCSR power state\n input [31:0] trn_rdllp_data, // RX DLLP data\n input trn_rdllp_src_rdy, // RX DLLP source ready\n\n // Virtex6/Spartan6 PM\n //-----------\n input cfg_to_turnoff, // Turnoff request\n output cfg_turnoff_ok, // Turnoff grant\n\n // System\n //-----------\n output [2:0] np_counter, // Non-posted counter\n input user_clk, // user clock from block\n input user_rst // user reset from block\n);\n\n\n//---------------------------------------------//\n// RX Data Pipeline //\n//---------------------------------------------//\n\naxi_basic_rx #(\n .C_DATA_WIDTH( C_DATA_WIDTH ),\n .C_FAMILY( C_FAMILY ),\n\n .TCQ( TCQ ),\n .REM_WIDTH( REM_WIDTH ),\n .KEEP_WIDTH( KEEP_WIDTH )\n) rx_inst (\n\n // Outgoing AXI TX\n //-----------\n .m_axis_rx_tdata( m_axis_rx_tdata ),\n .m_axis_rx_tvalid( m_axis_rx_tvalid ),\n .m_axis_rx_tready( m_axis_rx_tready ),\n .m_axis_rx_tkeep( m_axis_rx_tkeep ),\n .m_axis_rx_tlast( m_axis_rx_tlast ),\n .m_axis_rx_tuser( m_axis_rx_tuser ),\n\n // Incoming TRN RX\n //-----------\n .trn_rd( trn_rd ),\n .trn_rsof( trn_rsof ),\n .trn_reof( trn_reof ),\n .trn_rsrc_rdy( trn_rsrc_rdy ),\n .trn_rdst_rdy( trn_rdst_rdy ),\n .trn_rsrc_dsc( trn_rsrc_dsc ),\n .trn_rrem( trn_rrem ),\n .trn_rerrfwd( trn_rerrfwd ),\n .trn_rbar_hit( trn_rbar_hit ),\n .trn_recrc_err( trn_recrc_err ),\n\n // System\n //-----------\n .np_counter( np_counter ),\n .user_clk( user_clk ),\n .user_rst( user_rst )\n);\n\n\n\n//---------------------------------------------//\n// TX Data Pipeline //\n//---------------------------------------------//\n\naxi_basic_tx #(\n .C_DATA_WIDTH( C_DATA_WIDTH ),\n .C_FAMILY( C_FAMILY ),\n .C_ROOT_PORT( C_ROOT_PORT ),\n .C_PM_PRIORITY( C_PM_PRIORITY ),\n\n .TCQ( TCQ ),\n .REM_WIDTH( REM_WIDTH ),\n .KEEP_WIDTH( KEEP_WIDTH )\n) tx_inst (\n\n // Incoming AXI RX\n //-----------\n .s_axis_tx_tdata( s_axis_tx_tdata ),\n .s_axis_tx_tvalid( s_axis_tx_tvalid ),\n .s_axis_tx_tready( s_axis_tx_tready ),\n .s_axis_tx_tkeep( s_axis_tx_tkeep ),\n .s_axis_tx_tlast( s_axis_tx_tlast ),\n .s_axis_tx_tuser( s_axis_tx_tuser ),\n\n // User Misc.\n //-----------\n .user_turnoff_ok( user_turnoff_ok ),\n .user_tcfg_gnt( user_tcfg_gnt ),\n\n // Outgoing TRN TX\n //-----------\n .trn_td( trn_td ),\n .trn_tsof( trn_tsof ),\n .trn_teof( trn_teof ),\n .trn_tsrc_rdy( trn_tsrc_rdy ),\n .trn_tdst_rdy( trn_tdst_rdy ),\n .trn_tsrc_dsc( trn_tsrc_dsc ),\n .trn_trem( trn_trem ),\n .trn_terrfwd( trn_terrfwd ),\n .trn_tstr( trn_tstr ),\n .trn_tbuf_av( trn_tbuf_av ),\n .trn_tecrc_gen( trn_tecrc_gen ),\n\n // TRN Misc.\n //-----------\n .trn_tcfg_req( trn_tcfg_req ),\n .trn_tcfg_gnt( trn_tcfg_gnt ),\n .trn_lnk_up( trn_lnk_up ),\n\n // 7 Series/Virtex6 PM\n //-----------\n .cfg_pcie_link_state( cfg_pcie_link_state ),\n\n // Virtex6 PM\n //-----------\n .cfg_pm_send_pme_to( cfg_pm_send_pme_to ),\n .cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),\n .trn_rdllp_data( trn_rdllp_data ),\n .trn_rdllp_src_rdy( trn_rdllp_src_rdy ),\n\n // Spartan6 PM\n //-----------\n .cfg_to_turnoff( cfg_to_turnoff ),\n .cfg_turnoff_ok( cfg_turnoff_ok ),\n\n // System\n //-----------\n .user_clk( user_clk ),\n .user_rst( user_rst )\n);\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_tx.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : axi_basic_tx.v\n// Version : 2.4\n//----------------------------------------------------------------------------//\n// File: axi_basic_tx.v //\n// //\n// Description: //\n// AXI to TRN TX module. Instantiates pipeline and throttle control TX //\n// submodules. //\n// //\n// Notes: //\n// Optional notes section. //\n// //\n// Hierarchical: //\n// axi_basic_top //\n// axi_basic_tx //\n// //\n//----------------------------------------------------------------------------//\n\n`timescale 1ps/1ps\n\nmodule axi_basic_tx #(\n parameter C_DATA_WIDTH = 128, // RX/TX interface data width\n parameter C_FAMILY = \"X7\", // Targeted FPGA family\n parameter C_ROOT_PORT = \"FALSE\", // PCIe block is in root port mode\n parameter C_PM_PRIORITY = \"FALSE\", // Disable TX packet boundary thrtl\n parameter TCQ = 1, // Clock to Q time\n\n // Do not override parameters below this line\n parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width\n parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width\n ) (\n //---------------------------------------------//\n // User Design I/O //\n //---------------------------------------------//\n\n // AXI TX\n //-----------\n input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user\n input s_axis_tx_tvalid, // TX data is valid\n output s_axis_tx_tready, // TX ready for data\n input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables\n input s_axis_tx_tlast, // TX data is last\n input [3:0] s_axis_tx_tuser, // TX user signals\n\n // User Misc.\n //-----------\n input user_turnoff_ok, // Turnoff OK from user\n input user_tcfg_gnt, // Send cfg OK from user\n\n //---------------------------------------------//\n // PCIe Block I/O //\n //---------------------------------------------//\n\n // TRN TX\n //-----------\n output [C_DATA_WIDTH-1:0] trn_td, // TX data from block\n output trn_tsof, // TX start of packet\n output trn_teof, // TX end of packet\n output trn_tsrc_rdy, // TX source ready\n input trn_tdst_rdy, // TX destination ready\n output trn_tsrc_dsc, // TX source discontinue\n output [REM_WIDTH-1:0] trn_trem, // TX remainder\n output trn_terrfwd, // TX error forward\n output trn_tstr, // TX streaming enable\n input [5:0] trn_tbuf_av, // TX buffers available\n output trn_tecrc_gen, // TX ECRC generate\n\n // TRN Misc.\n //-----------\n input trn_tcfg_req, // TX config request\n output trn_tcfg_gnt, // RX config grant\n input trn_lnk_up, // PCIe link up\n\n // 7 Series/Virtex6 PM\n //-----------\n input [2:0] cfg_pcie_link_state, // Encoded PCIe link state\n\n // Virtex6 PM\n //-----------\n input cfg_pm_send_pme_to, // PM send PME turnoff msg\n input [1:0] cfg_pmcsr_powerstate, // PMCSR power state\n input [31:0] trn_rdllp_data, // RX DLLP data\n input trn_rdllp_src_rdy, // RX DLLP source ready\n\n // Virtex6/Spartan6 PM\n //-----------\n input cfg_to_turnoff, // Turnoff request\n output cfg_turnoff_ok, // Turnoff grant\n\n // System\n //-----------\n input user_clk, // user clock from block\n input user_rst // user reset from block\n);\n\n\nwire tready_thrtl;\n\n//---------------------------------------------//\n// TX Data Pipeline //\n//---------------------------------------------//\n\naxi_basic_tx_pipeline #(\n .C_DATA_WIDTH( C_DATA_WIDTH ),\n .C_PM_PRIORITY( C_PM_PRIORITY ),\n .TCQ( TCQ ),\n\n .REM_WIDTH( REM_WIDTH ),\n .KEEP_WIDTH( KEEP_WIDTH )\n) tx_pipeline_inst (\n\n // Incoming AXI RX\n //-----------\n .s_axis_tx_tdata( s_axis_tx_tdata ),\n .s_axis_tx_tready( s_axis_tx_tready ),\n .s_axis_tx_tvalid( s_axis_tx_tvalid ),\n .s_axis_tx_tkeep( s_axis_tx_tkeep ),\n .s_axis_tx_tlast( s_axis_tx_tlast ),\n .s_axis_tx_tuser( s_axis_tx_tuser ),\n\n // Outgoing TRN TX\n //-----------\n .trn_td( trn_td ),\n .trn_tsof( trn_tsof ),\n .trn_teof( trn_teof ),\n .trn_tsrc_rdy( trn_tsrc_rdy ),\n .trn_tdst_rdy( trn_tdst_rdy ),\n .trn_tsrc_dsc( trn_tsrc_dsc ),\n .trn_trem( trn_trem ),\n .trn_terrfwd( trn_terrfwd ),\n .trn_tstr( trn_tstr ),\n .trn_tecrc_gen( trn_tecrc_gen ),\n .trn_lnk_up( trn_lnk_up ),\n\n // System\n //-----------\n .tready_thrtl( tready_thrtl ),\n .user_clk( user_clk ),\n .user_rst( user_rst )\n);\n\n\n//---------------------------------------------//\n// TX Throttle Controller //\n//---------------------------------------------//\n\ngenerate\n if(C_PM_PRIORITY == \"FALSE\") begin : thrtl_ctl_enabled\n axi_basic_tx_thrtl_ctl #(\n .C_DATA_WIDTH( C_DATA_WIDTH ),\n .C_FAMILY( C_FAMILY ),\n .C_ROOT_PORT( C_ROOT_PORT ),\n .TCQ( TCQ )\n\n ) tx_thrl_ctl_inst (\n\n // Outgoing AXI TX\n //-----------\n .s_axis_tx_tdata( s_axis_tx_tdata ),\n .s_axis_tx_tvalid( s_axis_tx_tvalid ),\n .s_axis_tx_tuser( s_axis_tx_tuser ),\n .s_axis_tx_tlast( s_axis_tx_tlast ),\n\n // User Misc.\n //-----------\n .user_turnoff_ok( user_turnoff_ok ),\n .user_tcfg_gnt( user_tcfg_gnt ),\n\n // Incoming TRN RX\n //-----------\n .trn_tbuf_av( trn_tbuf_av ),\n .trn_tdst_rdy( trn_tdst_rdy ),\n\n // TRN Misc.\n //-----------\n .trn_tcfg_req( trn_tcfg_req ),\n .trn_tcfg_gnt( trn_tcfg_gnt ),\n .trn_lnk_up( trn_lnk_up ),\n\n // 7 Seriesq/Virtex6 PM\n //-----------\n .cfg_pcie_link_state( cfg_pcie_link_state ),\n\n // Virtex6 PM\n //-----------\n .cfg_pm_send_pme_to( cfg_pm_send_pme_to ),\n .cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),\n .trn_rdllp_data( trn_rdllp_data ),\n .trn_rdllp_src_rdy( trn_rdllp_src_rdy ),\n\n // Spartan6 PM\n //-----------\n .cfg_to_turnoff( cfg_to_turnoff ),\n .cfg_turnoff_ok( cfg_turnoff_ok ),\n\n // System\n //-----------\n .tready_thrtl( tready_thrtl ),\n .user_clk( user_clk ),\n .user_rst( user_rst )\n );\n end\n else begin : thrtl_ctl_disabled\n assign tready_thrtl = 1'b0;\n\n assign cfg_turnoff_ok = user_turnoff_ok;\n assign trn_tcfg_gnt = user_tcfg_gnt;\n end\nendgenerate\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_tx_pipeline.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : axi_basic_tx_pipeline.v\n// Version : 2.4\n//----------------------------------------------------------------------------//\n// File: axi_basic_tx_pipeline.v //\n// //\n// Description: //\n// AXI to TRN TX pipeline. Converts transmitted data from AXI protocol to //\n// TRN. //\n// //\n// Notes: //\n// Optional notes section. //\n// //\n// Hierarchical: //\n// axi_basic_top //\n// axi_basic_tx //\n// axi_basic_tx_pipeline //\n// //\n//----------------------------------------------------------------------------//\n\n`timescale 1ps/1ps\n\nmodule axi_basic_tx_pipeline #(\n parameter C_DATA_WIDTH = 128, // RX/TX interface data width\n parameter C_PM_PRIORITY = \"FALSE\", // Disable TX packet boundary thrtl\n parameter TCQ = 1, // Clock to Q time\n\n // Do not override parameters below this line\n parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width\n parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width\n ) (\n //---------------------------------------------//\n // User Design I/O //\n //---------------------------------------------//\n\n // AXI TX\n //-----------\n input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user\n input s_axis_tx_tvalid, // TX data is valid\n output s_axis_tx_tready, // TX ready for data\n input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables\n input s_axis_tx_tlast, // TX data is last\n input [3:0] s_axis_tx_tuser, // TX user signals\n\n //---------------------------------------------//\n // PCIe Block I/O //\n //---------------------------------------------//\n\n // TRN TX\n //-----------\n output [C_DATA_WIDTH-1:0] trn_td, // TX data from block\n output trn_tsof, // TX start of packet\n output trn_teof, // TX end of packet\n output trn_tsrc_rdy, // TX source ready\n input trn_tdst_rdy, // TX destination ready\n output trn_tsrc_dsc, // TX source discontinue\n output [REM_WIDTH-1:0] trn_trem, // TX remainder\n output trn_terrfwd, // TX error forward\n output trn_tstr, // TX streaming enable\n output trn_tecrc_gen, // TX ECRC generate\n input trn_lnk_up, // PCIe link up\n\n // System\n //-----------\n input tready_thrtl, // TREADY from thrtl ctl\n input user_clk, // user clock from block\n input user_rst // user reset from block\n);\n\n\n// Input register stage\nreg [C_DATA_WIDTH-1:0] reg_tdata;\nreg reg_tvalid;\nreg [KEEP_WIDTH-1:0] reg_tkeep;\nreg [3:0] reg_tuser;\nreg reg_tlast;\nreg reg_tready;\n\n// Pipeline utility signals\nreg trn_in_packet;\nreg axi_in_packet;\nreg flush_axi;\nwire disable_trn;\nreg reg_disable_trn;\n\nwire axi_beat_live = s_axis_tx_tvalid && s_axis_tx_tready;\nwire axi_end_packet = axi_beat_live && s_axis_tx_tlast;\n\n\n//----------------------------------------------------------------------------//\n// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN. //\n// 128-bit: 64-bit: 32-bit: //\n// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0 //\n// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0 //\n// TRN DW2 maps to AXI DW1 //\n// TRN DW3 maps to AXI DW0 //\n//----------------------------------------------------------------------------//\ngenerate\n if(C_DATA_WIDTH == 128) begin : td_DW_swap_128\n assign trn_td = {reg_tdata[31:0],\n reg_tdata[63:32],\n reg_tdata[95:64],\n reg_tdata[127:96]};\n end\n else if(C_DATA_WIDTH == 64) begin : td_DW_swap_64\n assign trn_td = {reg_tdata[31:0], reg_tdata[63:32]};\n end\n else begin : td_DW_swap_32\n assign trn_td = reg_tdata;\n end\nendgenerate\n\n\n//----------------------------------------------------------------------------//\n// Create trn_tsof. If we're not currently in a packet and TVALID goes high, //\n// assert TSOF. //\n//----------------------------------------------------------------------------//\nassign trn_tsof = reg_tvalid && !trn_in_packet;\n\n\n//----------------------------------------------------------------------------//\n// Create trn_in_packet. This signal tracks if the TRN interface is currently //\n// in the middle of a packet, which is needed to generate trn_tsof //\n//----------------------------------------------------------------------------//\nalways @(posedge user_clk) begin\n if(user_rst) begin\n trn_in_packet <= #TCQ 1'b0;\n end\n else begin\n if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof) begin\n trn_in_packet <= #TCQ 1'b1;\n end\n else if((trn_in_packet && trn_teof && trn_tsrc_rdy) || !trn_lnk_up) begin\n trn_in_packet <= #TCQ 1'b0;\n end\n end\nend\n\n\n//----------------------------------------------------------------------------//\n// Create axi_in_packet. This signal tracks if the AXI interface is currently //\n// in the middle of a packet, which is needed in case the link goes down. //\n//----------------------------------------------------------------------------//\nalways @(posedge user_clk) begin\n if(user_rst) begin\n axi_in_packet <= #TCQ 1'b0;\n end\n else begin\n if(axi_beat_live && !s_axis_tx_tlast) begin\n axi_in_packet <= #TCQ 1'b1;\n end\n else if(axi_beat_live) begin\n axi_in_packet <= #TCQ 1'b0;\n end\n end\nend\n\n\n//----------------------------------------------------------------------------//\n// Create disable_trn. This signal asserts when the link goes down and //\n// triggers the deassertiong of trn_tsrc_rdy. The deassertion of disable_trn //\n// depends on C_PM_PRIORITY, as described below. //\n//----------------------------------------------------------------------------//\ngenerate\n // In the C_PM_PRIORITY pipeline, we disable the TRN interfacefrom the time\n // the link goes down until the the AXI interface is ready to accept packets\n // again (via assertion of TREADY). By waiting for TREADY, we allow the\n // previous value buffer to fill, so we're ready for any throttling by the\n // user or the block.\n if(C_PM_PRIORITY == \"TRUE\") begin : pm_priority_trn_flush\n always @(posedge user_clk) begin\n if(user_rst) begin\n reg_disable_trn <= #TCQ 1'b1;\n end\n else begin\n // When the link goes down, disable the TRN interface.\n if(!trn_lnk_up)\n begin\n reg_disable_trn <= #TCQ 1'b1;\n end\n\n // When the link comes back up and the AXI interface is ready, we can\n // release the pipeline and return to normal operation.\n else if(!flush_axi && s_axis_tx_tready) begin\n reg_disable_trn <= #TCQ 1'b0;\n end\n end\n end\n\n assign disable_trn = reg_disable_trn;\n end\n\n // In the throttle-controlled pipeline, we don't have a previous value buffer.\n // The throttle control mechanism handles TREADY, so all we need to do is\n // detect when the link goes down and disable the TRN interface until the link\n // comes back up and the AXI interface is finished flushing any packets.\n else begin : thrtl_ctl_trn_flush\n always @(posedge user_clk) begin\n if(user_rst) begin\n reg_disable_trn <= #TCQ 1'b0;\n end\n else begin\n // If the link is down and AXI is in packet, disable TRN and look for\n // the end of the packet\n if(axi_in_packet && !trn_lnk_up && !axi_end_packet)\n begin\n reg_disable_trn <= #TCQ 1'b1;\n end\n\n // AXI packet is ending, so we're done flushing\n else if(axi_end_packet) begin\n reg_disable_trn <= #TCQ 1'b0;\n end\n end\n end\n\n // Disable the TRN interface if link is down or we're still flushing the AXI\n // interface.\n assign disable_trn = reg_disable_trn || !trn_lnk_up;\n end\nendgenerate\n\n\n//----------------------------------------------------------------------------//\n// Convert STRB to RREM. Here, we are converting the encoding method for the //\n// location of the EOF from AXI (tkeep) to TRN flavor (rrem). //\n//----------------------------------------------------------------------------//\ngenerate\n if(C_DATA_WIDTH == 128) begin : tkeep_to_trem_128\n //---------------------------------------//\n // Conversion table: //\n // trem | tkeep //\n // [1] [0] | [15:12] [11:8] [7:4] [3:0] //\n // ------------------------------------- //\n // 1 1 | D3 D2 D1 D0 //\n // 1 0 | -- D2 D1 D0 //\n // 0 1 | -- -- D1 D0 //\n // 0 0 | -- -- -- D0 //\n //---------------------------------------//\n\n wire axi_DW_1 = reg_tkeep[7];\n wire axi_DW_2 = reg_tkeep[11];\n wire axi_DW_3 = reg_tkeep[15];\n assign trn_trem[1] = axi_DW_2;\n assign trn_trem[0] = axi_DW_3 || (axi_DW_1 && !axi_DW_2);\n end\n else if(C_DATA_WIDTH == 64) begin : tkeep_to_trem_64\n assign trn_trem = reg_tkeep[7];\n end\n else begin : tkeep_to_trem_32\n assign trn_trem = 1'b0;\n end\nendgenerate\n\n\n//----------------------------------------------------------------------------//\n// Create remaining TRN signals //\n//----------------------------------------------------------------------------//\nassign trn_teof = reg_tlast;\nassign trn_tecrc_gen = reg_tuser[0];\nassign trn_terrfwd = reg_tuser[1];\nassign trn_tstr = reg_tuser[2];\nassign trn_tsrc_dsc = reg_tuser[3];\n\n\n//----------------------------------------------------------------------------//\n// Pipeline stage //\n//----------------------------------------------------------------------------//\n// We need one of two approaches for the pipeline stage depending on the\n// C_PM_PRIORITY parameter.\ngenerate\n reg reg_tsrc_rdy;\n\n // If set to FALSE, that means the user wants to use the TX packet boundary\n // throttling feature. Since all Block throttling will now be predicted, we\n // can use a simple straight-through pipeline.\n if(C_PM_PRIORITY == \"FALSE\") begin : throttle_ctl_pipeline\n always @(posedge user_clk) begin\n if(user_rst) begin\n reg_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};\n reg_tvalid <= #TCQ 1'b0;\n reg_tkeep <= #TCQ {KEEP_WIDTH{1'b0}};\n reg_tlast <= #TCQ 1'b0;\n reg_tuser <= #TCQ 4'h0;\n reg_tsrc_rdy <= #TCQ 1'b0;\n end\n else begin\n reg_tdata <= #TCQ s_axis_tx_tdata;\n reg_tvalid <= #TCQ s_axis_tx_tvalid;\n reg_tkeep <= #TCQ s_axis_tx_tkeep;\n reg_tlast <= #TCQ s_axis_tx_tlast;\n reg_tuser <= #TCQ s_axis_tx_tuser;\n\n // Hold trn_tsrc_rdy low when flushing a packet.\n reg_tsrc_rdy <= #TCQ axi_beat_live && !disable_trn;\n end\n end\n\n assign trn_tsrc_rdy = reg_tsrc_rdy;\n\n // With TX packet boundary throttling, TREADY is pipelined in\n // axi_basic_tx_thrtl_ctl and wired through here.\n assign s_axis_tx_tready = tready_thrtl;\n end\n\n //**************************************************************************//\n\n // If C_PM_PRIORITY is set to TRUE, that means the user prefers to have all PM\n // functionality intact isntead of TX packet boundary throttling. Now the\n // Block could back-pressure at any time, which creates the standard problem\n // of potential data loss due to the handshaking latency. Here we need a\n // previous value buffer, just like the RX data path.\n else begin : pm_prioity_pipeline\n reg [C_DATA_WIDTH-1:0] tdata_prev;\n reg tvalid_prev;\n reg [KEEP_WIDTH-1:0] tkeep_prev;\n reg tlast_prev;\n reg [3:0] tuser_prev;\n reg reg_tdst_rdy;\n\n wire data_hold;\n reg data_prev;\n\n\n //------------------------------------------------------------------------//\n // Previous value buffer //\n // --------------------- //\n // We are inserting a pipeline stage in between AXI and TRN, which causes //\n // some issues with handshaking signals trn_tsrc_rdy/s_axis_tx_tready. //\n // The added cycle of latency in the path causes the Block to fall behind //\n // the AXI interface whenever it throttles. //\n // //\n // To avoid loss of data, we must keep the previous value of all //\n // s_axis_tx_* signals in case the Block throttles. //\n //------------------------------------------------------------------------//\n always @(posedge user_clk) begin\n if(user_rst) begin\n tdata_prev <= #TCQ {C_DATA_WIDTH{1'b0}};\n tvalid_prev <= #TCQ 1'b0;\n tkeep_prev <= #TCQ {KEEP_WIDTH{1'b0}};\n tlast_prev <= #TCQ 1'b0;\n tuser_prev <= #TCQ 4'h 0;\n end\n else begin\n // prev buffer works by checking s_axis_tx_tready. When\n // s_axis_tx_tready is asserted, a new value is present on the\n // interface.\n if(!s_axis_tx_tready) begin\n tdata_prev <= #TCQ tdata_prev;\n tvalid_prev <= #TCQ tvalid_prev;\n tkeep_prev <= #TCQ tkeep_prev;\n tlast_prev <= #TCQ tlast_prev;\n tuser_prev <= #TCQ tuser_prev;\n end\n else begin\n tdata_prev <= #TCQ s_axis_tx_tdata;\n tvalid_prev <= #TCQ s_axis_tx_tvalid;\n tkeep_prev <= #TCQ s_axis_tx_tkeep;\n tlast_prev <= #TCQ s_axis_tx_tlast;\n tuser_prev <= #TCQ s_axis_tx_tuser;\n end\n end\n end\n\n // Create special buffer which locks in the proper value of TDATA depending\n // on whether the user is throttling or not. This buffer has three states:\n //\n // HOLD state: TDATA maintains its current value\n // - the Block has throttled the PCIe block\n // PREVIOUS state: the buffer provides the previous value on TDATA\n // - the Block has finished throttling, and is a little\n // behind the user\n // CURRENT state: the buffer passes the current value on TDATA\n // - the Block is caught up and ready to receive the\n // latest data from the user\n always @(posedge user_clk) begin\n if(user_rst) begin\n reg_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};\n reg_tvalid <= #TCQ 1'b0;\n reg_tkeep <= #TCQ {KEEP_WIDTH{1'b0}};\n reg_tlast <= #TCQ 1'b0;\n reg_tuser <= #TCQ 4'h0;\n\n reg_tdst_rdy <= #TCQ 1'b0;\n end\n else begin\n reg_tdst_rdy <= #TCQ trn_tdst_rdy;\n\n if(!data_hold) begin\n // PREVIOUS state\n if(data_prev) begin\n reg_tdata <= #TCQ tdata_prev;\n reg_tvalid <= #TCQ tvalid_prev;\n reg_tkeep <= #TCQ tkeep_prev;\n reg_tlast <= #TCQ tlast_prev;\n reg_tuser <= #TCQ tuser_prev;\n end\n\n // CURRENT state\n else begin\n reg_tdata <= #TCQ s_axis_tx_tdata;\n reg_tvalid <= #TCQ s_axis_tx_tvalid;\n reg_tkeep <= #TCQ s_axis_tx_tkeep;\n reg_tlast <= #TCQ s_axis_tx_tlast;\n reg_tuser <= #TCQ s_axis_tx_tuser;\n end\n end\n // else HOLD state\n end\n end\n\n\n // Logic to instruct pipeline to hold its value\n assign data_hold = trn_tsrc_rdy && !trn_tdst_rdy;\n\n\n // Logic to instruct pipeline to use previous bus values. Always use\n // previous value after holding a value.\n always @(posedge user_clk) begin\n if(user_rst) begin\n data_prev <= #TCQ 1'b0;\n end\n else begin\n data_prev <= #TCQ data_hold;\n end\n end\n\n\n //------------------------------------------------------------------------//\n // Create trn_tsrc_rdy. If we're flushing the TRN hold trn_tsrc_rdy low. //\n //------------------------------------------------------------------------//\n assign trn_tsrc_rdy = reg_tvalid && !disable_trn;\n\n\n //------------------------------------------------------------------------//\n // Create TREADY //\n //------------------------------------------------------------------------//\n always @(posedge user_clk) begin\n if(user_rst) begin\n reg_tready <= #TCQ 1'b0;\n end\n else begin\n // If the link went down and we need to flush a packet in flight, hold\n // TREADY high\n if(flush_axi && !axi_end_packet) begin\n reg_tready <= #TCQ 1'b1;\n end\n\n // If the link is up, TREADY is as follows:\n // TREADY = 1 when trn_tsrc_rdy == 0\n // - While idle, keep the pipeline primed and ready for the next\n // packet\n //\n // TREADY = trn_tdst_rdy when trn_tsrc_rdy == 1\n // - While in packet, throttle pipeline based on state of TRN\n else if(trn_lnk_up) begin\n reg_tready <= #TCQ trn_tdst_rdy || !trn_tsrc_rdy;\n end\n\n // If the link is down and we're not flushing a packet, hold TREADY low\n // wait for link to come back up\n else begin\n reg_tready <= #TCQ 1'b0;\n end\n end\n end\n\n assign s_axis_tx_tready = reg_tready;\n end\n\n\n //--------------------------------------------------------------------------//\n // Create flush_axi. This signal detects if the link goes down while the //\n // AXI interface is in packet. In this situation, we need to flush the //\n // packet through the AXI interface and discard it. //\n //--------------------------------------------------------------------------//\n always @(posedge user_clk) begin\n if(user_rst) begin\n flush_axi <= #TCQ 1'b0;\n end\n else begin\n // If the AXI interface is in packet and the link goes down, purge it.\n if(axi_in_packet && !trn_lnk_up && !axi_end_packet) begin\n flush_axi <= #TCQ 1'b1;\n end\n\n // The packet is finished, so we're done flushing.\n else if(axi_end_packet) begin\n flush_axi <= #TCQ 1'b0;\n end\n end\n end\nendgenerate\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_tx_thrtl_ctl.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : axi_basic_tx_thrtl_ctl.v\n// Version : 2.4\n//----------------------------------------------------------------------------//\n// File: axi_basic_tx_thrtl_ctl.v //\n// //\n// Description: //\n// TX throttle controller. Anticipates back-pressure from PCIe block and //\n// preemptively back-pressures user design (packet boundary throttling). //\n// //\n// Notes: //\n// Optional notes section. //\n// //\n// Hierarchical: //\n// axi_basic_top //\n// axi_basic_tx //\n// axi_basic_tx_thrtl_ctl //\n// //\n//----------------------------------------------------------------------------//\n\n`timescale 1ps/1ps\n\nmodule axi_basic_tx_thrtl_ctl #(\n parameter C_DATA_WIDTH = 128, // RX/TX interface data width\n parameter C_FAMILY = \"X7\", // Targeted FPGA family\n parameter C_ROOT_PORT = \"FALSE\", // PCIe block is in root port mode\n parameter TCQ = 1 // Clock to Q time\n ) (\n\n // AXI TX\n //-----------\n input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user\n input s_axis_tx_tvalid, // TX data is valid\n input [3:0] s_axis_tx_tuser, // TX user signals\n input s_axis_tx_tlast, // TX data is last\n\n // User Misc.\n //-----------\n input user_turnoff_ok, // Turnoff OK from user\n input user_tcfg_gnt, // Send cfg OK from user\n\n // TRN TX\n //-----------\n input [5:0] trn_tbuf_av, // TX buffers available\n input trn_tdst_rdy, // TX destination ready\n\n // TRN Misc.\n //-----------\n input trn_tcfg_req, // TX config request\n output trn_tcfg_gnt, // TX config grant\n input trn_lnk_up, // PCIe link up\n\n // 7 Series/Virtex6 PM\n //-----------\n input [2:0] cfg_pcie_link_state, // Encoded PCIe link state\n\n // Virtex6 PM\n //-----------\n input cfg_pm_send_pme_to, // PM send PME turnoff msg\n input [1:0] cfg_pmcsr_powerstate, // PMCSR power state\n input [31:0] trn_rdllp_data, // RX DLLP data\n input trn_rdllp_src_rdy, // RX DLLP source ready\n\n // Virtex6/Spartan6 PM\n //-----------\n input cfg_to_turnoff, // Turnoff request\n output reg cfg_turnoff_ok, // Turnoff grant\n\n // System\n //-----------\n output reg tready_thrtl, // TREADY to pipeline\n input user_clk, // user clock from block\n input user_rst // user reset from block\n);\n\n\n// Thrtl user when TBUF hits this val\nlocalparam TBUF_AV_MIN = (C_DATA_WIDTH == 128) ? 5 :\n (C_DATA_WIDTH == 64) ? 1 : 0;\n\n// Pause user when TBUF hits this val\nlocalparam TBUF_AV_GAP = TBUF_AV_MIN + 1;\n\n// GAP pause time - the latency from the time a packet is accepted on the TRN\n// interface to the time trn_tbuf_av from the Block will decrement.\nlocalparam TBUF_GAP_TIME = (C_DATA_WIDTH == 128) ? 4 : 1;\n\n// Latency time from when tcfg_gnt is asserted to when PCIe block will throttle\nlocalparam TCFG_LATENCY_TIME = 2'd2;\n\n// Number of pipeline stages to delay trn_tcfg_gnt. For V6 128-bit only\nlocalparam TCFG_GNT_PIPE_STAGES = 3;\n\n// Throttle condition registers and constants\nreg lnk_up_thrtl;\nwire lnk_up_trig;\nwire lnk_up_exit;\n\nreg tbuf_av_min_thrtl;\nwire tbuf_av_min_trig;\n\nreg tbuf_av_gap_thrtl;\nreg [2:0] tbuf_gap_cnt;\nwire tbuf_av_gap_trig;\nwire tbuf_av_gap_exit;\nwire gap_trig_tlast;\nwire gap_trig_decr;\nreg [5:0] tbuf_av_d;\n\nreg tcfg_req_thrtl;\nreg [1:0] tcfg_req_cnt;\nreg trn_tdst_rdy_d;\nwire tcfg_req_trig;\nwire tcfg_req_exit;\nreg tcfg_gnt_log;\n\nwire pre_throttle;\nwire reg_throttle;\nwire exit_crit;\nreg reg_tcfg_gnt;\nreg trn_tcfg_req_d;\nreg tcfg_gnt_pending;\nwire wire_to_turnoff;\nreg reg_turnoff_ok;\n\nreg tready_thrtl_mux;\n\nlocalparam LINKSTATE_L0 = 3'b000;\nlocalparam LINKSTATE_PPM_L1 = 3'b001;\nlocalparam LINKSTATE_PPM_L1_TRANS = 3'b101;\nlocalparam LINKSTATE_PPM_L23R_TRANS = 3'b110;\nlocalparam PM_ENTER_L1 = 8'h20;\nlocalparam POWERSTATE_D0 = 2'b00;\n\nreg ppm_L1_thrtl;\nwire ppm_L1_trig;\nwire ppm_L1_exit;\nreg [2:0] cfg_pcie_link_state_d;\nreg trn_rdllp_src_rdy_d;\n\nreg ppm_L23_thrtl;\nwire ppm_L23_trig;\nreg cfg_turnoff_ok_pending;\n\nreg reg_tlast;\n\n// Throttle control state machine states and registers\nlocalparam IDLE = 0;\nlocalparam THROTTLE = 1;\nreg cur_state;\nreg next_state;\n\nreg reg_axi_in_pkt;\nwire axi_in_pkt;\nwire axi_pkt_ending;\nwire axi_throttled;\nwire axi_thrtl_ok;\nwire tx_ecrc_pause;\n\n//----------------------------------------------------------------------------//\n// THROTTLE REASON: PCIe link is down //\n// - When to throttle: trn_lnk_up deasserted //\n// - When to stop: trn_tdst_rdy assesrted //\n//----------------------------------------------------------------------------//\nassign lnk_up_trig = !trn_lnk_up;\nassign lnk_up_exit = trn_tdst_rdy;\n\nalways @(posedge user_clk) begin\n if(user_rst) begin\n lnk_up_thrtl <= #TCQ 1'b1;\n end\n else begin\n if(lnk_up_trig) begin\n lnk_up_thrtl <= #TCQ 1'b1;\n end\n else if(lnk_up_exit) begin\n lnk_up_thrtl <= #TCQ 1'b0;\n end\n end\nend\n\n\n//----------------------------------------------------------------------------//\n// THROTTLE REASON: Transmit buffers depleted //\n// - When to throttle: trn_tbuf_av falls to 0 //\n// - When to stop: trn_tbuf_av rises above 0 again //\n//----------------------------------------------------------------------------//\nassign tbuf_av_min_trig = (trn_tbuf_av <= TBUF_AV_MIN);\n\nalways @(posedge user_clk) begin\n if(user_rst) begin\n tbuf_av_min_thrtl <= #TCQ 1'b0;\n end\n else begin\n if(tbuf_av_min_trig) begin\n tbuf_av_min_thrtl <= #TCQ 1'b1;\n end\n\n // The exit condition for tbuf_av_min_thrtl is !tbuf_av_min_trig\n else begin\n tbuf_av_min_thrtl <= #TCQ 1'b0;\n end\n end\nend\n\n\n//----------------------------------------------------------------------------//\n// THROTTLE REASON: Transmit buffers getting low //\n// - When to throttle: trn_tbuf_av falls below \"gap\" threshold TBUF_AV_GAP //\n// - When to stop: after TBUF_GAP_TIME cycles elapse //\n// //\n// If we're about to run out of transmit buffers, throttle the user for a //\n// few clock cycles to give the PCIe block time to catch up. This is //\n// needed to compensate for latency in decrementing trn_tbuf_av in the PCIe //\n// Block transmit path. //\n//----------------------------------------------------------------------------//\n\n// Detect two different scenarios for buffers getting low:\n// 1) If we see a TLAST. a new packet has been inserted into the buffer, and\n// we need to pause and let that packet \"soak in\"\nassign gap_trig_tlast = (trn_tbuf_av <= TBUF_AV_GAP) &&\n s_axis_tx_tvalid && tready_thrtl && s_axis_tx_tlast;\n\n// 2) Any time tbug_avail decrements to the TBUF_AV_GAP threshold, we need to\n// pause and make sure no other packets are about to soak in and cause the\n// buffer availability to drop further.\nassign gap_trig_decr = (trn_tbuf_av == (TBUF_AV_GAP)) &&\n (tbuf_av_d == (TBUF_AV_GAP+1));\n\nassign gap_trig_tcfg = (tcfg_req_thrtl && tcfg_req_exit);\nassign tbuf_av_gap_trig = gap_trig_tlast || gap_trig_decr || gap_trig_tcfg;\nassign tbuf_av_gap_exit = (tbuf_gap_cnt == 0);\n\nalways @(posedge user_clk) begin\n if(user_rst) begin\n tbuf_av_gap_thrtl <= #TCQ 1'b0;\n tbuf_gap_cnt <= #TCQ 3'h0;\n tbuf_av_d <= #TCQ 6'h00;\n end\n else begin\n if(tbuf_av_gap_trig) begin\n tbuf_av_gap_thrtl <= #TCQ 1'b1;\n end\n else if(tbuf_av_gap_exit) begin\n tbuf_av_gap_thrtl <= #TCQ 1'b0;\n end\n\n // tbuf gap counter:\n // This logic controls the length of the throttle condition when tbufs are\n // getting low.\n if(tbuf_av_gap_thrtl && (cur_state == THROTTLE)) begin\n if(tbuf_gap_cnt > 0) begin\n tbuf_gap_cnt <= #TCQ tbuf_gap_cnt - 3'd1;\n end\n end\n else begin\n tbuf_gap_cnt <= #TCQ TBUF_GAP_TIME;\n end\n\n tbuf_av_d <= #TCQ trn_tbuf_av;\n end\nend\n\n\n//----------------------------------------------------------------------------//\n// THROTTLE REASON: Block needs to send a CFG response //\n// - When to throttle: trn_tcfg_req and user_tcfg_gnt asserted //\n// - When to stop: after trn_tdst_rdy transitions to unasserted //\n// //\n// If the block needs to send a response to a CFG packet, this will cause //\n// the subsequent deassertion of trn_tdst_rdy. When the user design permits, //\n// grant permission to the block to service request and throttle the user. //\n//----------------------------------------------------------------------------//\nassign tcfg_req_trig = trn_tcfg_req && reg_tcfg_gnt;\nassign tcfg_req_exit = (tcfg_req_cnt == 2'd0) && !trn_tdst_rdy_d &&\n trn_tdst_rdy;\nalways @(posedge user_clk) begin\n if(user_rst) begin\n tcfg_req_thrtl <= #TCQ 1'b0;\n trn_tcfg_req_d <= #TCQ 1'b0;\n trn_tdst_rdy_d <= #TCQ 1'b1;\n reg_tcfg_gnt <= #TCQ 1'b0;\n tcfg_req_cnt <= #TCQ 2'd0;\n tcfg_gnt_pending <= #TCQ 1'b0;\n end\n else begin\n if(tcfg_req_trig) begin\n tcfg_req_thrtl <= #TCQ 1'b1;\n end\n else if(tcfg_req_exit) begin\n tcfg_req_thrtl <= #TCQ 1'b0;\n end\n\n // We need to wait the appropriate amount of time for the tcfg_gnt to\n // \"sink in\" to the PCIe block. After that, we know that the PCIe block will\n // not reassert trn_tdst_rdy until the CFG request has been serviced. If a\n // new request is being service (tcfg_gnt_log == 1), then reset the timer.\n if((trn_tcfg_req && !trn_tcfg_req_d) || tcfg_gnt_pending) begin\n tcfg_req_cnt <= #TCQ TCFG_LATENCY_TIME;\n end\n else begin\n if(tcfg_req_cnt > 0) begin\n tcfg_req_cnt <= #TCQ tcfg_req_cnt - 2'd1;\n end\n end\n\n // Make sure tcfg_gnt_log pulses once for one clock cycle for every\n // cfg packet request.\n if(trn_tcfg_req && !trn_tcfg_req_d) begin\n tcfg_gnt_pending <= #TCQ 1'b1;\n end\n else if(tcfg_gnt_log) begin\n tcfg_gnt_pending <= #TCQ 1'b0;\n end\n\n trn_tcfg_req_d <= #TCQ trn_tcfg_req;\n trn_tdst_rdy_d <= #TCQ trn_tdst_rdy;\n reg_tcfg_gnt <= #TCQ user_tcfg_gnt;\n end\nend\n\n\n//----------------------------------------------------------------------------//\n// THROTTLE REASON: Block needs to transition to low power state PPM L1 //\n// - When to throttle: appropriate low power state signal asserted //\n// (architecture dependent) //\n// - When to stop: cfg_pcie_link_state goes to proper value (C_ROOT_PORT //\n// dependent) //\n// //\n// If the block needs to transition to PM state PPM L1, we need to finish //\n// up what we're doing and throttle immediately. //\n//----------------------------------------------------------------------------//\ngenerate\n // PPM L1 signals for 7 Series in RC mode\n if((C_FAMILY == \"X7\") && (C_ROOT_PORT == \"TRUE\")) begin : x7_L1_thrtl_rp\n assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&\n (cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);\n assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;\n end\n\n // PPM L1 signals for 7 Series in EP mode\n else if((C_FAMILY == \"X7\") && (C_ROOT_PORT == \"FALSE\")) begin : x7_L1_thrtl_ep\n assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&\n (cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);\n assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;\n end\n\n // PPM L1 signals for V6 in RC mode\n else if((C_FAMILY == \"V6\") && (C_ROOT_PORT == \"TRUE\")) begin : v6_L1_thrtl_rp\n assign ppm_L1_trig = (trn_rdllp_data[31:24] == PM_ENTER_L1) &&\n trn_rdllp_src_rdy && !trn_rdllp_src_rdy_d;\n assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;\n end\n\n // PPM L1 signals for V6 in EP mode\n else if((C_FAMILY == \"V6\") && (C_ROOT_PORT == \"FALSE\")) begin : v6_L1_thrtl_ep\n assign ppm_L1_trig = (cfg_pmcsr_powerstate != POWERSTATE_D0);\n assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;\n end\n\n // PPM L1 detection not supported for S6\n else begin : s6_L1_thrtl\n assign ppm_L1_trig = 1'b0;\n assign ppm_L1_exit = 1'b1;\n end\nendgenerate\n\nalways @(posedge user_clk) begin\n if(user_rst) begin\n ppm_L1_thrtl <= #TCQ 1'b0;\n cfg_pcie_link_state_d <= #TCQ 3'b0;\n trn_rdllp_src_rdy_d <= #TCQ 1'b0;\n end\n else begin\n if(ppm_L1_trig) begin\n ppm_L1_thrtl <= #TCQ 1'b1;\n end\n else if(ppm_L1_exit) begin\n ppm_L1_thrtl <= #TCQ 1'b0;\n end\n cfg_pcie_link_state_d <= #TCQ cfg_pcie_link_state;\n trn_rdllp_src_rdy_d <= #TCQ trn_rdllp_src_rdy;\n end\nend\n\n\n//----------------------------------------------------------------------------//\n// THROTTLE REASON: Block needs to transition to low power state PPM L2/3 //\n// - When to throttle: appropriate PM signal indicates a transition to //\n// L2/3 is pending or in progress (family and role dependent) //\n// - When to stop: never (the only path out of L2/3 is a full reset) //\n// //\n// If the block needs to transition to PM state PPM L2/3, we need to finish //\n// up what we're doing and throttle when the user gives permission. //\n//----------------------------------------------------------------------------//\ngenerate\n // PPM L2/3 signals for 7 Series in RC mode\n if((C_FAMILY == \"X7\") && (C_ROOT_PORT == \"TRUE\")) begin : x7_L23_thrtl_rp\n assign ppm_L23_trig = (cfg_pcie_link_state_d == LINKSTATE_PPM_L23R_TRANS);\n assign wire_to_turnoff = 1'b0;\n end\n\n // PPM L2/3 signals for V6 in RC mode\n else if((C_FAMILY == \"V6\") && (C_ROOT_PORT == \"TRUE\")) begin : v6_L23_thrtl_rp\n assign ppm_L23_trig = cfg_pm_send_pme_to;\n assign wire_to_turnoff = 1'b0;\n end\n\n // PPM L2/3 signals in EP mode\n else begin : L23_thrtl_ep\n assign ppm_L23_trig = wire_to_turnoff && reg_turnoff_ok;\n\n // PPM L2/3 signals for 7 Series in EP mode\n // For 7 Series, cfg_to_turnoff pulses once when a turnoff request is\n // outstanding, so we need a \"sticky\" register that grabs the request.\n if(C_FAMILY == \"X7\") begin : x7_L23_thrtl_ep\n reg reg_to_turnoff;\n\n always @(posedge user_clk) begin\n if(user_rst) begin\n reg_to_turnoff <= #TCQ 1'b0;\n end\n else begin\n if(cfg_to_turnoff) begin\n reg_to_turnoff <= #TCQ 1'b1;\n end\n end\n end\n\n assign wire_to_turnoff = reg_to_turnoff;\n end\n\n // PPM L2/3 signals for V6/S6 in EP mode\n // In V6 and S6, the to_turnoff signal asserts and remains asserted until\n // turnoff_ok is asserted, so a sticky reg is not necessary.\n else begin : v6_s6_L23_thrtl_ep\n assign wire_to_turnoff = cfg_to_turnoff;\n end\n\n always @(posedge user_clk) begin\n if(user_rst) begin\n reg_turnoff_ok <= #TCQ 1'b0;\n end\n else begin\n reg_turnoff_ok <= #TCQ user_turnoff_ok;\n end\n end\n end\nendgenerate\n\nalways @(posedge user_clk) begin\n if(user_rst) begin\n ppm_L23_thrtl <= #TCQ 1'b0;\n cfg_turnoff_ok_pending <= #TCQ 1'b0;\n end\n else begin\n if(ppm_L23_trig) begin\n ppm_L23_thrtl <= #TCQ 1'b1;\n end\n\n // Make sure cfg_turnoff_ok pulses once for one clock cycle for every\n // turnoff request.\n if(ppm_L23_trig && !ppm_L23_thrtl) begin\n cfg_turnoff_ok_pending <= #TCQ 1'b1;\n end\n else if(cfg_turnoff_ok) begin\n cfg_turnoff_ok_pending <= #TCQ 1'b0;\n end\n end\nend\n\n\n//----------------------------------------------------------------------------//\n// Create axi_thrtl_ok. This signal determines if it's OK to throttle the //\n// user design on the AXI interface. Since TREADY is registered, this signal //\n// needs to assert on the cycle ~before~ we actually intend to throttle. //\n// The only time it's OK to throttle when TVALID is asserted is on the first //\n// beat of a new packet. Therefore, assert axi_thrtl_ok if one of the //\n// is true: //\n// 1) The user is not in a packet and is not starting one //\n// 2) The user is just finishing a packet //\n// 3) We're already throttled, so it's OK to continue throttling //\n//----------------------------------------------------------------------------//\nalways @(posedge user_clk) begin\n if(user_rst) begin\n reg_axi_in_pkt <= #TCQ 1'b0;\n end\n else begin\n if(s_axis_tx_tvalid && s_axis_tx_tlast) begin\n reg_axi_in_pkt <= #TCQ 1'b0;\n end\n else if(tready_thrtl && s_axis_tx_tvalid) begin\n reg_axi_in_pkt <= #TCQ 1'b1;\n end\n end\nend\n\nassign axi_in_pkt = s_axis_tx_tvalid || reg_axi_in_pkt;\nassign axi_pkt_ending = s_axis_tx_tvalid && s_axis_tx_tlast;\nassign axi_throttled = !tready_thrtl;\nassign axi_thrtl_ok = !axi_in_pkt || axi_pkt_ending || axi_throttled;\n\n\n//----------------------------------------------------------------------------//\n// Throttle CTL State Machine: //\n// Throttle user design when a throttle trigger (or triggers) occur. //\n// Keep user throttled until all exit criteria have been met. //\n//----------------------------------------------------------------------------//\n\n// Immediate throttle signal. Used to \"pounce\" on a throttle opportunity when\n// we're seeking one\nassign pre_throttle = tbuf_av_min_trig || tbuf_av_gap_trig || lnk_up_trig\n || tcfg_req_trig || ppm_L1_trig || ppm_L23_trig;\n\n\n// Registered throttle signals. Used to control throttle state machine\nassign reg_throttle = tbuf_av_min_thrtl || tbuf_av_gap_thrtl || lnk_up_thrtl\n || tcfg_req_thrtl || ppm_L1_thrtl || ppm_L23_thrtl;\n\nassign exit_crit = !tbuf_av_min_thrtl && !tbuf_av_gap_thrtl && !lnk_up_thrtl\n && !tcfg_req_thrtl && !ppm_L1_thrtl && !ppm_L23_thrtl;\n\nalways @(*) begin\n case(cur_state)\n // IDLE: in this state we're waiting for a trigger event to occur. As\n // soon as an event occurs and the user isn't transmitting a packet, we\n // throttle the PCIe block and the user and next state is THROTTLE.\n IDLE: begin\n if(reg_throttle && axi_thrtl_ok) begin\n // Throttle user\n tready_thrtl_mux = 1'b0;\n next_state = THROTTLE;\n\n // Assert appropriate grant signal depending on the throttle type.\n if(tcfg_req_thrtl) begin\n tcfg_gnt_log = 1'b1; // For cfg request, grant the request\n cfg_turnoff_ok = 1'b0; //\n end\n else if(ppm_L23_thrtl) begin\n tcfg_gnt_log = 1'b0; //\n cfg_turnoff_ok = 1'b1; // For PM request, permit transition\n end\n else begin\n tcfg_gnt_log = 1'b0; // Otherwise do nothing\n cfg_turnoff_ok = 1'b0; //\n end\n end\n\n // If there's not throttle event, do nothing\n else begin\n // Throttle user as soon as possible\n tready_thrtl_mux = !(axi_thrtl_ok && pre_throttle);\n next_state = IDLE;\n\n tcfg_gnt_log = 1'b0;\n cfg_turnoff_ok = 1'b0;\n end\n end\n\n // THROTTLE: in this state the user is throttle and we're waiting for\n // exit criteria, which tells us that the throttle event is over. When\n // the exit criteria is satisfied, de-throttle the user and next state\n // is IDLE.\n THROTTLE: begin\n if(exit_crit) begin\n // Dethrottle user\n tready_thrtl_mux = !pre_throttle;\n next_state = IDLE;\n end\n else begin\n // Throttle user\n tready_thrtl_mux = 1'b0;\n next_state = THROTTLE;\n end\n\n // Assert appropriate grant signal depending on the throttle type.\n if(tcfg_req_thrtl && tcfg_gnt_pending) begin\n tcfg_gnt_log = 1'b1; // For cfg request, grant the request\n cfg_turnoff_ok = 1'b0; //\n end\n else if(cfg_turnoff_ok_pending) begin\n tcfg_gnt_log = 1'b0; //\n cfg_turnoff_ok = 1'b1; // For PM request, permit transition\n end\n else begin\n tcfg_gnt_log = 1'b0; // Otherwise do nothing\n cfg_turnoff_ok = 1'b0; //\n end\n end\n\n default: begin\n tready_thrtl_mux = 1'b0;\n next_state = IDLE;\n tcfg_gnt_log = 1'b0;\n cfg_turnoff_ok = 1'b0;\n end\n endcase\nend\n\n// Synchronous logic\nalways @(posedge user_clk) begin\n if(user_rst) begin\n // Throttle user by default until link comes up\n cur_state <= #TCQ THROTTLE;\n\n reg_tlast <= #TCQ 1'b0;\n\n tready_thrtl <= #TCQ 1'b0;\n end\n else begin\n cur_state <= #TCQ next_state;\n\n tready_thrtl <= #TCQ tready_thrtl_mux && !tx_ecrc_pause;\n reg_tlast <= #TCQ s_axis_tx_tlast;\n end\nend\n\n// For X7, the PCIe block will generate the ECRC for a packet if trn_tecrc_gen\n// is asserted at SOF. In this case, the Block needs an extra data beat to\n// calculate the ECRC, but only if the following conditions are met:\n// 1) there is no empty DWORDS at the end of the packet\n// (i.e. packet length % C_DATA_WIDTH == 0)\n//\n// 2) There isn't a ECRC in the TLP already, as indicated by the TD bit in the\n// TLP header\n//\n// If both conditions are met, the Block will stall the TRN interface for one\n// data beat after EOF. We need to predict this stall and preemptively stall the\n// User for one beat.\ngenerate\n if(C_FAMILY == \"X7\") begin : ecrc_pause_enabled\n wire tx_ecrc_pkt;\n reg reg_tx_ecrc_pkt;\n\n wire [1:0] packet_fmt;\n wire packet_td;\n wire [2:0] header_len;\n wire [9:0] payload_len;\n wire [13:0] packet_len;\n wire pause_needed;\n\n // Grab necessary packet fields\n assign packet_fmt = s_axis_tx_tdata[30:29];\n assign packet_td = s_axis_tx_tdata[15];\n\n // Calculate total packet length\n assign header_len = packet_fmt[0] ? 3'd4 : 3'd3;\n assign payload_len = packet_fmt[1] ? s_axis_tx_tdata[9:0] : 10'h0;\n assign packet_len = {10'h000, header_len} + {4'h0, payload_len};\n\n\n // Determine if packet a ECRC pause is needed\n if(C_DATA_WIDTH == 128) begin : packet_len_check_128\n assign pause_needed = (packet_len[1:0] == 2'b00) && !packet_td;\n end\n else begin : packet_len_check_64\n assign pause_needed = (packet_len[0] == 1'b0) && !packet_td;\n end\n\n\n // Create flag to alert TX pipeline to insert a stall\n assign tx_ecrc_pkt = s_axis_tx_tuser[0] && pause_needed &&\n tready_thrtl && s_axis_tx_tvalid && !reg_axi_in_pkt;\n\n always @(posedge user_clk) begin\n if(user_rst) begin\n reg_tx_ecrc_pkt <= #TCQ 1'b0;\n end\n else begin\n if(tx_ecrc_pkt && !s_axis_tx_tlast) begin\n reg_tx_ecrc_pkt <= #TCQ 1'b1;\n end\n else if(tready_thrtl && s_axis_tx_tvalid && s_axis_tx_tlast) begin\n reg_tx_ecrc_pkt <= #TCQ 1'b0;\n end\n end\n end\n\n\n // Insert the stall now\n assign tx_ecrc_pause = ((tx_ecrc_pkt || reg_tx_ecrc_pkt) &&\n s_axis_tx_tlast && s_axis_tx_tvalid && tready_thrtl);\n\n end\n else begin : ecrc_pause_disabled\n assign tx_ecrc_pause = 1'b0;\n end\nendgenerate\n\n\n// Logic for 128-bit single cycle bug fix.\n// This tcfg_gnt pipeline addresses an issue with 128-bit V6 designs where a\n// single cycle packet transmitted simultaneously with an assertion of tcfg_gnt\n// from AXI Basic causes the packet to be dropped. The packet drop occurs\n// because the 128-bit shim doesn't know about the tcfg_req/gnt, and therefor\n// isn't expecting trn_tdst_rdy to go low. Since the 128-bit shim does throttle\n// prediction just as we do, it ignores the value of trn_tdst_rdy, and\n// ultimately drops the packet when transmitting the packet to the block.\ngenerate\n if(C_DATA_WIDTH == 128 && C_FAMILY == \"V6\") begin : tcfg_gnt_pipeline\n genvar stage;\n reg tcfg_gnt_pipe [TCFG_GNT_PIPE_STAGES:0];\n\n // Create a configurable depth FF delay pipeline\n for(stage = 0; stage < TCFG_GNT_PIPE_STAGES; stage = stage + 1)\n begin : tcfg_gnt_pipeline_stage\n\n always @(posedge user_clk) begin\n if(user_rst) begin\n tcfg_gnt_pipe[stage] <= #TCQ 1'b0;\n end\n else begin\n // For stage 0, insert the actual tcfg_gnt signal from logic\n if(stage == 0) begin\n tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_log;\n end\n\n // For stages 1+, chain together\n else begin\n tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_pipe[stage - 1];\n end\n end\n end\n\n // tcfg_gnt output to block assigned the last pipeline stage\n assign trn_tcfg_gnt = tcfg_gnt_pipe[TCFG_GNT_PIPE_STAGES-1];\n end\n end\n else begin : tcfg_gnt_no_pipeline\n\n // For all other architectures, no pipeline delay needed for tcfg_gnt\n assign trn_tcfg_gnt = tcfg_gnt_log;\n end\nendgenerate\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/channel_128.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tchannel_128.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tRepresents a RIFFA channel. Contains a RX port and a \n// TX port.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule channel_128 #(\n\tparameter C_DATA_WIDTH = 9'd128,\n\tparameter C_MAX_READ_REQ = 2,\t\t\t\t\t// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t// Local parameters\n\tparameter C_RX_FIFO_DEPTH = 1024,\n\tparameter C_TX_FIFO_DEPTH = 512,\n\tparameter C_SG_FIFO_DEPTH = 1024,\n\tparameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [2:0] CONFIG_MAX_READ_REQUEST_SIZE,\t\t// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\tinput [2:0] CONFIG_MAX_PAYLOAD_SIZE,\t\t\t// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B\n\n\tinput [31:0] PIO_DATA,\t\t\t\t\t\t\t// Single word programmed I/O data\n\tinput [C_DATA_WIDTH-1:0] ENG_DATA,\t\t\t\t// Main incoming data \n\n\toutput SG_RX_BUF_RECVD,\t\t\t\t\t\t\t// Scatter gather RX buffer completely read (ready for next if applicable)\n\tinput SG_RX_BUF_LEN_VALID,\t\t\t\t\t\t// Scatter gather RX buffer length valid\n\tinput SG_RX_BUF_ADDR_HI_VALID,\t\t\t\t\t// Scatter gather RX buffer high address valid\n\tinput SG_RX_BUF_ADDR_LO_VALID,\t\t\t\t\t// Scatter gather RX buffer low address valid\n\n\toutput SG_TX_BUF_RECVD,\t\t\t\t\t\t\t// Scatter gather TX buffer completely read (ready for next if applicable)\n\tinput SG_TX_BUF_LEN_VALID,\t\t\t\t\t\t// Scatter gather TX buffer length valid\n\tinput SG_TX_BUF_ADDR_HI_VALID,\t\t\t\t\t// Scatter gather TX buffer high address valid\n\tinput SG_TX_BUF_ADDR_LO_VALID,\t\t\t\t\t// Scatter gather TX buffer low address valid\n\n\tinput TXN_RX_LEN_VALID,\t\t\t\t\t\t\t// Read transaction length valid\n\tinput TXN_RX_OFF_LAST_VALID,\t\t\t\t\t// Read transaction offset/last valid\n\toutput [31:0] TXN_RX_DONE_LEN,\t\t\t\t\t// Read transaction actual transfer length\n\toutput TXN_RX_DONE,\t\t\t\t\t\t\t\t// Read transaction done\n\tinput TXN_RX_DONE_ACK,\t\t\t\t\t\t\t// Read transaction actual transfer length read\n\n\toutput TXN_TX,\t\t\t\t\t\t\t\t\t// Write transaction notification\n\tinput TXN_TX_ACK,\t\t\t\t\t\t\t\t// Write transaction acknowledged\n\toutput [31:0] TXN_TX_LEN,\t\t\t\t\t\t// Write transaction length\n\toutput [31:0] TXN_TX_OFF_LAST,\t\t\t\t\t// Write transaction offset/last\n\toutput [31:0] TXN_TX_DONE_LEN,\t\t\t\t\t// Write transaction actual transfer length\n\toutput TXN_TX_DONE,\t\t\t\t\t\t\t\t// Write transaction done\n\tinput TXN_TX_DONE_ACK,\t\t\t\t\t\t\t// Write transaction actual transfer length read\n\n\toutput RX_REQ,\t\t\t\t\t\t\t\t\t// Read request\n\tinput RX_REQ_ACK,\t\t\t\t\t\t\t\t// Read request accepted\n\toutput [1:0] RX_REQ_TAG,\t\t\t\t\t\t// Read request data tag \n\toutput [63:0] RX_REQ_ADDR,\t\t\t\t\t\t// Read request address\n\toutput [9:0] RX_REQ_LEN,\t\t\t\t\t\t// Read request length\n\n\toutput TX_REQ,\t\t\t\t\t\t\t\t\t// Outgoing write request\n\tinput TX_REQ_ACK,\t\t\t\t\t\t\t\t// Outgoing write request acknowledged\n\toutput [63:0] TX_ADDR,\t\t\t\t\t\t\t// Outgoing write high address\n\toutput [9:0] TX_LEN,\t\t\t\t\t\t\t// Outgoing write length (in 32 bit words)\n\toutput [C_DATA_WIDTH-1:0] TX_DATA,\t\t\t\t// Outgoing write data\n\tinput TX_DATA_REN,\t\t\t\t\t\t\t\t// Outgoing write data read enable\n\tinput TX_SENT,\t\t\t\t\t\t\t\t\t// Outgoing write complete\n\n\tinput [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,\t\t// Main incoming data enable\n\tinput MAIN_DONE,\t\t\t\t\t\t\t\t// Main incoming data complete\n\tinput MAIN_ERR,\t\t\t\t\t\t\t\t\t// Main incoming data completed with error\n\n\tinput [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,\t// Scatter gather for RX incoming data enable\n\tinput SG_RX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for RX incoming data complete\n\tinput SG_RX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for RX incoming data completed with error\n\n\tinput [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,\t// Scatter gather for TX incoming data enable\n\tinput SG_TX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for TX incoming data complete\n\tinput SG_TX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for TX incoming data completed with error\n\n\tinput CHNL_RX_CLK,\t\t\t\t\t\t\t\t\t// Channel read clock\n\toutput CHNL_RX,\t\t\t\t\t\t\t\t\t// Channel read receive signal\n\tinput CHNL_RX_ACK,\t\t\t\t\t\t\t\t// Channle read received signal\n\toutput CHNL_RX_LAST,\t\t\t\t\t\t\t// Channel last read\n\toutput [31:0] CHNL_RX_LEN,\t\t\t\t\t\t// Channel read length\n\toutput [30:0] CHNL_RX_OFF,\t\t\t\t\t\t// Channel read offset\n\toutput [C_DATA_WIDTH-1:0] CHNL_RX_DATA,\t\t\t// Channel read data\n\toutput CHNL_RX_DATA_VALID,\t\t\t\t\t\t// Channel read data valid\n\tinput CHNL_RX_DATA_REN, \t\t\t\t\t\t// Channel read data has been recieved\n\n\tinput CHNL_TX_CLK,\t\t\t\t\t\t\t\t// Channel write clock\n\tinput CHNL_TX,\t\t\t\t\t\t\t\t\t// Channel write receive signal\n\toutput CHNL_TX_ACK,\t\t\t\t\t\t\t\t// Channel write acknowledgement signal\n\tinput CHNL_TX_LAST,\t\t\t\t\t\t\t\t// Channel last write\n\tinput [31:0] CHNL_TX_LEN,\t\t\t\t\t\t// Channel write length (in 32 bit words)\n\tinput [30:0] CHNL_TX_OFF,\t\t\t\t\t\t// Channel write offset\n\tinput [C_DATA_WIDTH-1:0] CHNL_TX_DATA,\t\t\t// Channel write data\n\tinput CHNL_TX_DATA_VALID,\t\t\t\t\t\t// Channel write data valid\n\toutput CHNL_TX_DATA_REN\t\t\t\t\t\t\t// Channel write data has been recieved\n);\n\n`include \"common_functions.v\"\n\n\nwire\t[C_DATA_WIDTH-1:0]\twTxSgData;\nwire\t\t\t\t\t\twTxSgDataEmpty;\nwire\t\t\t\t\t\twTxSgDataRen;\nwire\t\t\t\t\t\twTxSgDataErr;\nwire\t\t\t\t\t\twTxSgDataRst;\n\n\n// Receiving port (data to the channel)\nrx_port_128 #(\n\t.C_DATA_WIDTH(C_DATA_WIDTH), \n\t.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH), \n\t.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),\n\t.C_MAX_READ_REQ(C_MAX_READ_REQ)\n) rxPort (\n\t.RST(RST), \n\t.CLK(CLK), \n\t.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE), \n\t\n\t.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),\n\t.SG_RX_BUF_DATA(PIO_DATA),\n\t.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),\n\t.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),\n\t.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),\n\t\n\t.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),\n\t.SG_TX_BUF_DATA(PIO_DATA),\n\t.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),\n\t.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),\n\t.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),\n\t\n\t.SG_DATA(wTxSgData),\n\t.SG_DATA_EMPTY(wTxSgDataEmpty),\n\t.SG_DATA_REN(wTxSgDataRen),\n\t.SG_RST(wTxSgDataRst),\n\t.SG_ERR(wTxSgDataErr),\n\t\n\t.TXN_DATA(PIO_DATA), \n\t.TXN_LEN_VALID(TXN_RX_LEN_VALID), \n\t.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID), \n\t.TXN_DONE_LEN(TXN_RX_DONE_LEN),\n\t.TXN_DONE(TXN_RX_DONE),\n\t.TXN_DONE_ACK(TXN_RX_DONE_ACK),\n\t\n\t.RX_REQ(RX_REQ),\n\t.RX_REQ_ACK(RX_REQ_ACK),\n\t.RX_REQ_TAG(RX_REQ_TAG),\n\t.RX_REQ_ADDR(RX_REQ_ADDR),\n\t.RX_REQ_LEN(RX_REQ_LEN),\n\n\t.MAIN_DATA(ENG_DATA),\n\t.MAIN_DATA_EN(MAIN_DATA_EN), \n\t.MAIN_DONE(MAIN_DONE), \n\t.MAIN_ERR(MAIN_ERR),\n\t\n\t.SG_RX_DATA(ENG_DATA),\n\t.SG_RX_DATA_EN(SG_RX_DATA_EN), \n\t.SG_RX_DONE(SG_RX_DONE), \n\t.SG_RX_ERR(SG_RX_ERR),\n\n\t.SG_TX_DATA(ENG_DATA),\n\t.SG_TX_DATA_EN(SG_TX_DATA_EN), \n\t.SG_TX_DONE(SG_TX_DONE), \n\t.SG_TX_ERR(SG_TX_ERR),\n\n\t.CHNL_CLK(CHNL_RX_CLK), \n\t.CHNL_RX(CHNL_RX), \n\t.CHNL_RX_ACK(CHNL_RX_ACK), \n\t.CHNL_RX_LAST(CHNL_RX_LAST), \n\t.CHNL_RX_LEN(CHNL_RX_LEN), \n\t.CHNL_RX_OFF(CHNL_RX_OFF), \n\t.CHNL_RX_DATA(CHNL_RX_DATA), \n\t.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), \n\t.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)\n);\n\n\n// Sending port (data from the channel)\ntx_port_128 #(\n\t.C_DATA_WIDTH(C_DATA_WIDTH), \n\t.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)\n) txPort (\n\t.CLK(CLK), \n\t.RST(RST), \n\t.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE), \n\t\n\t.TXN(TXN_TX),\n\t.TXN_ACK(TXN_TX_ACK),\n\t.TXN_LEN(TXN_TX_LEN),\n\t.TXN_OFF_LAST(TXN_TX_OFF_LAST),\n\t.TXN_DONE_LEN(TXN_TX_DONE_LEN),\n\t.TXN_DONE(TXN_TX_DONE),\n\t.TXN_DONE_ACK(TXN_TX_DONE_ACK),\n\t\n\t.SG_DATA(wTxSgData),\n\t.SG_DATA_EMPTY(wTxSgDataEmpty),\n\t.SG_DATA_REN(wTxSgDataRen),\n\t.SG_RST(wTxSgDataRst),\n\t.SG_ERR(wTxSgDataErr),\n\t\n\t.TX_REQ(TX_REQ), \n\t.TX_REQ_ACK(TX_REQ_ACK),\n\t.TX_ADDR(TX_ADDR), \n\t.TX_LEN(TX_LEN), \n\t.TX_DATA(TX_DATA),\n\t.TX_DATA_REN(TX_DATA_REN), \n\t.TX_SENT(TX_SENT),\n\n\t.CHNL_CLK(CHNL_TX_CLK), \n\t.CHNL_TX(CHNL_TX), \n\t.CHNL_TX_ACK(CHNL_TX_ACK),\n\t.CHNL_TX_LAST(CHNL_TX_LAST), \n\t.CHNL_TX_LEN(CHNL_TX_LEN), \n\t.CHNL_TX_OFF(CHNL_TX_OFF), \n\t.CHNL_TX_DATA(CHNL_TX_DATA), \n\t.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID), \n\t.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)\n);\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/channel_32.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tchannel_32.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tRepresents a RIFFA channel. Contains a RX port and a \n// TX port.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule channel_32 #(\n\tparameter C_DATA_WIDTH = 9'd32,\n\tparameter C_MAX_READ_REQ = 2,\t\t\t\t\t// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t// Local parameters\n\tparameter C_RX_FIFO_DEPTH = 1024,\n\tparameter C_TX_FIFO_DEPTH = 512,\n\tparameter C_SG_FIFO_DEPTH = 1024,\n\tparameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [2:0] CONFIG_MAX_READ_REQUEST_SIZE,\t\t// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\tinput [2:0] CONFIG_MAX_PAYLOAD_SIZE,\t\t\t// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B\n\n\tinput [31:0] PIO_DATA,\t\t\t\t\t\t\t// Single word programmed I/O data\n\tinput [C_DATA_WIDTH-1:0] ENG_DATA,\t\t\t\t// Main incoming data \n\n\toutput SG_RX_BUF_RECVD,\t\t\t\t\t\t\t// Scatter gather RX buffer completely read (ready for next if applicable)\n\tinput SG_RX_BUF_LEN_VALID,\t\t\t\t\t\t// Scatter gather RX buffer length valid\n\tinput SG_RX_BUF_ADDR_HI_VALID,\t\t\t\t\t// Scatter gather RX buffer high address valid\n\tinput SG_RX_BUF_ADDR_LO_VALID,\t\t\t\t\t// Scatter gather RX buffer low address valid\n\n\toutput SG_TX_BUF_RECVD,\t\t\t\t\t\t\t// Scatter gather TX buffer completely read (ready for next if applicable)\n\tinput SG_TX_BUF_LEN_VALID,\t\t\t\t\t\t// Scatter gather TX buffer length valid\n\tinput SG_TX_BUF_ADDR_HI_VALID,\t\t\t\t\t// Scatter gather TX buffer high address valid\n\tinput SG_TX_BUF_ADDR_LO_VALID,\t\t\t\t\t// Scatter gather TX buffer low address valid\n\n\tinput TXN_RX_LEN_VALID,\t\t\t\t\t\t\t// Read transaction length valid\n\tinput TXN_RX_OFF_LAST_VALID,\t\t\t\t\t// Read transaction offset/last valid\n\toutput [31:0] TXN_RX_DONE_LEN,\t\t\t\t\t// Read transaction actual transfer length\n\toutput TXN_RX_DONE,\t\t\t\t\t\t\t\t// Read transaction done\n\tinput TXN_RX_DONE_ACK,\t\t\t\t\t\t\t// Read transaction actual transfer length read\n\n\toutput TXN_TX,\t\t\t\t\t\t\t\t\t// Write transaction notification\n\tinput TXN_TX_ACK,\t\t\t\t\t\t\t\t// Write transaction acknowledged\n\toutput [31:0] TXN_TX_LEN,\t\t\t\t\t\t// Write transaction length\n\toutput [31:0] TXN_TX_OFF_LAST,\t\t\t\t\t// Write transaction offset/last\n\toutput [31:0] TXN_TX_DONE_LEN,\t\t\t\t\t// Write transaction actual transfer length\n\toutput TXN_TX_DONE,\t\t\t\t\t\t\t\t// Write transaction done\n\tinput TXN_TX_DONE_ACK,\t\t\t\t\t\t\t// Write transaction actual transfer length read\n\n\toutput RX_REQ,\t\t\t\t\t\t\t\t\t// Read request\n\tinput RX_REQ_ACK,\t\t\t\t\t\t\t\t// Read request accepted\n\toutput [1:0] RX_REQ_TAG,\t\t\t\t\t\t// Read request data tag \n\toutput [63:0] RX_REQ_ADDR,\t\t\t\t\t\t// Read request address\n\toutput [9:0] RX_REQ_LEN,\t\t\t\t\t\t// Read request length\n\n\toutput TX_REQ,\t\t\t\t\t\t\t\t\t// Outgoing write request\n\tinput TX_REQ_ACK,\t\t\t\t\t\t\t\t// Outgoing write request acknowledged\n\toutput [63:0] TX_ADDR,\t\t\t\t\t\t\t// Outgoing write high address\n\toutput [9:0] TX_LEN,\t\t\t\t\t\t\t// Outgoing write length (in 32 bit words)\n\toutput [C_DATA_WIDTH-1:0] TX_DATA,\t\t\t\t// Outgoing write data\n\tinput TX_DATA_REN,\t\t\t\t\t\t\t\t// Outgoing write data read enable\n\tinput TX_SENT,\t\t\t\t\t\t\t\t\t// Outgoing write complete\n\n\tinput [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,\t\t// Main incoming data enable\n\tinput MAIN_DONE,\t\t\t\t\t\t\t\t// Main incoming data complete\n\tinput MAIN_ERR,\t\t\t\t\t\t\t\t\t// Main incoming data completed with error\n\n\tinput [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,\t// Scatter gather for RX incoming data enable\n\tinput SG_RX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for RX incoming data complete\n\tinput SG_RX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for RX incoming data completed with error\n\n\tinput [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,\t// Scatter gather for TX incoming data enable\n\tinput SG_TX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for TX incoming data complete\n\tinput SG_TX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for TX incoming data completed with error\n\n\tinput CHNL_RX_CLK,\t\t\t\t\t\t\t\t\t// Channel read clock\n\toutput CHNL_RX,\t\t\t\t\t\t\t\t\t// Channel read receive signal\n\tinput CHNL_RX_ACK,\t\t\t\t\t\t\t\t// Channle read received signal\n\toutput CHNL_RX_LAST,\t\t\t\t\t\t\t// Channel last read\n\toutput [31:0] CHNL_RX_LEN,\t\t\t\t\t\t// Channel read length\n\toutput [30:0] CHNL_RX_OFF,\t\t\t\t\t\t// Channel read offset\n\toutput [C_DATA_WIDTH-1:0] CHNL_RX_DATA,\t\t\t// Channel read data\n\toutput CHNL_RX_DATA_VALID,\t\t\t\t\t\t// Channel read data valid\n\tinput CHNL_RX_DATA_REN, \t\t\t\t\t\t// Channel read data has been recieved\n\n\tinput CHNL_TX_CLK,\t\t\t\t\t\t\t\t// Channel write clock\n\tinput CHNL_TX,\t\t\t\t\t\t\t\t\t// Channel write receive signal\n\toutput CHNL_TX_ACK,\t\t\t\t\t\t\t\t// Channel write acknowledgement signal\n\tinput CHNL_TX_LAST,\t\t\t\t\t\t\t\t// Channel last write\n\tinput [31:0] CHNL_TX_LEN,\t\t\t\t\t\t// Channel write length (in 32 bit words)\n\tinput [30:0] CHNL_TX_OFF,\t\t\t\t\t\t// Channel write offset\n\tinput [C_DATA_WIDTH-1:0] CHNL_TX_DATA,\t\t\t// Channel write data\n\tinput CHNL_TX_DATA_VALID,\t\t\t\t\t\t// Channel write data valid\n\toutput CHNL_TX_DATA_REN\t\t\t\t\t\t\t// Channel write data has been recieved\n);\n\n`include \"common_functions.v\"\n\n\nwire\t[C_DATA_WIDTH-1:0]\twTxSgData;\nwire\t\t\t\t\t\twTxSgDataEmpty;\nwire\t\t\t\t\t\twTxSgDataRen;\nwire\t\t\t\t\t\twTxSgDataErr;\nwire\t\t\t\t\t\twTxSgDataRst;\n\n\n// Receiving port (data to the channel)\nrx_port_32 #(\n\t.C_DATA_WIDTH(C_DATA_WIDTH), \n\t.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH), \n\t.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),\n\t.C_MAX_READ_REQ(C_MAX_READ_REQ)\n) rxPort (\n\t.RST(RST), \n\t.CLK(CLK), \n\t.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE), \n\t\n\t.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),\n\t.SG_RX_BUF_DATA(PIO_DATA),\n\t.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),\n\t.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),\n\t.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),\n\t\n\t.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),\n\t.SG_TX_BUF_DATA(PIO_DATA),\n\t.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),\n\t.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),\n\t.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),\n\t\n\t.SG_DATA(wTxSgData),\n\t.SG_DATA_EMPTY(wTxSgDataEmpty),\n\t.SG_DATA_REN(wTxSgDataRen),\n\t.SG_RST(wTxSgDataRst),\n\t.SG_ERR(wTxSgDataErr),\n\t\n\t.TXN_DATA(PIO_DATA), \n\t.TXN_LEN_VALID(TXN_RX_LEN_VALID), \n\t.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID), \n\t.TXN_DONE_LEN(TXN_RX_DONE_LEN),\n\t.TXN_DONE(TXN_RX_DONE),\n\t.TXN_DONE_ACK(TXN_RX_DONE_ACK),\n\t\n\t.RX_REQ(RX_REQ),\n\t.RX_REQ_ACK(RX_REQ_ACK),\n\t.RX_REQ_TAG(RX_REQ_TAG),\n\t.RX_REQ_ADDR(RX_REQ_ADDR),\n\t.RX_REQ_LEN(RX_REQ_LEN),\n\n\t.MAIN_DATA(ENG_DATA),\n\t.MAIN_DATA_EN(MAIN_DATA_EN), \n\t.MAIN_DONE(MAIN_DONE), \n\t.MAIN_ERR(MAIN_ERR),\n\t\n\t.SG_RX_DATA(ENG_DATA),\n\t.SG_RX_DATA_EN(SG_RX_DATA_EN), \n\t.SG_RX_DONE(SG_RX_DONE), \n\t.SG_RX_ERR(SG_RX_ERR),\n\n\t.SG_TX_DATA(ENG_DATA),\n\t.SG_TX_DATA_EN(SG_TX_DATA_EN), \n\t.SG_TX_DONE(SG_TX_DONE), \n\t.SG_TX_ERR(SG_TX_ERR),\n\n\t.CHNL_CLK(CHNL_RX_CLK), \n\t.CHNL_RX(CHNL_RX), \n\t.CHNL_RX_ACK(CHNL_RX_ACK), \n\t.CHNL_RX_LAST(CHNL_RX_LAST), \n\t.CHNL_RX_LEN(CHNL_RX_LEN), \n\t.CHNL_RX_OFF(CHNL_RX_OFF), \n\t.CHNL_RX_DATA(CHNL_RX_DATA), \n\t.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), \n\t.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)\n);\n\n\n// Sending port (data from the channel)\ntx_port_32 #(\n\t.C_DATA_WIDTH(C_DATA_WIDTH), \n\t.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)\n) txPort (\n\t.CLK(CLK), \n\t.RST(RST), \n\t.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE), \n\t\n\t.TXN(TXN_TX),\n\t.TXN_ACK(TXN_TX_ACK),\n\t.TXN_LEN(TXN_TX_LEN),\n\t.TXN_OFF_LAST(TXN_TX_OFF_LAST),\n\t.TXN_DONE_LEN(TXN_TX_DONE_LEN),\n\t.TXN_DONE(TXN_TX_DONE),\n\t.TXN_DONE_ACK(TXN_TX_DONE_ACK),\n\t\n\t.SG_DATA(wTxSgData),\n\t.SG_DATA_EMPTY(wTxSgDataEmpty),\n\t.SG_DATA_REN(wTxSgDataRen),\n\t.SG_RST(wTxSgDataRst),\n\t.SG_ERR(wTxSgDataErr),\n\t\n\t.TX_REQ(TX_REQ), \n\t.TX_REQ_ACK(TX_REQ_ACK),\n\t.TX_ADDR(TX_ADDR), \n\t.TX_LEN(TX_LEN), \n\t.TX_DATA(TX_DATA),\n\t.TX_DATA_REN(TX_DATA_REN), \n\t.TX_SENT(TX_SENT),\n\n\t.CHNL_CLK(CHNL_TX_CLK), \n\t.CHNL_TX(CHNL_TX), \n\t.CHNL_TX_ACK(CHNL_TX_ACK),\n\t.CHNL_TX_LAST(CHNL_TX_LAST), \n\t.CHNL_TX_LEN(CHNL_TX_LEN), \n\t.CHNL_TX_OFF(CHNL_TX_OFF), \n\t.CHNL_TX_DATA(CHNL_TX_DATA), \n\t.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID), \n\t.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)\n);\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/channel_64.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tchannel_64.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tRepresents a RIFFA channel. Contains a RX port and a \n// TX port.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule channel_64 #(\n\tparameter C_DATA_WIDTH = 9'd64,\n\tparameter C_MAX_READ_REQ = 2,\t\t\t\t\t// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t// Local parameters\n\tparameter C_RX_FIFO_DEPTH = 1024,\n\tparameter C_TX_FIFO_DEPTH = 512,\n\tparameter C_SG_FIFO_DEPTH = 1024,\n\tparameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [2:0] CONFIG_MAX_READ_REQUEST_SIZE,\t\t// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\tinput [2:0] CONFIG_MAX_PAYLOAD_SIZE,\t\t\t// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B\n\n\tinput [31:0] PIO_DATA,\t\t\t\t\t\t\t// Single word programmed I/O data\n\tinput [C_DATA_WIDTH-1:0] ENG_DATA,\t\t\t\t// Main incoming data \n\n\toutput SG_RX_BUF_RECVD,\t\t\t\t\t\t\t// Scatter gather RX buffer completely read (ready for next if applicable)\n\tinput SG_RX_BUF_LEN_VALID,\t\t\t\t\t\t// Scatter gather RX buffer length valid\n\tinput SG_RX_BUF_ADDR_HI_VALID,\t\t\t\t\t// Scatter gather RX buffer high address valid\n\tinput SG_RX_BUF_ADDR_LO_VALID,\t\t\t\t\t// Scatter gather RX buffer low address valid\n\n\toutput SG_TX_BUF_RECVD,\t\t\t\t\t\t\t// Scatter gather TX buffer completely read (ready for next if applicable)\n\tinput SG_TX_BUF_LEN_VALID,\t\t\t\t\t\t// Scatter gather TX buffer length valid\n\tinput SG_TX_BUF_ADDR_HI_VALID,\t\t\t\t\t// Scatter gather TX buffer high address valid\n\tinput SG_TX_BUF_ADDR_LO_VALID,\t\t\t\t\t// Scatter gather TX buffer low address valid\n\n\tinput TXN_RX_LEN_VALID,\t\t\t\t\t\t\t// Read transaction length valid\n\tinput TXN_RX_OFF_LAST_VALID,\t\t\t\t\t// Read transaction offset/last valid\n\toutput [31:0] TXN_RX_DONE_LEN,\t\t\t\t\t// Read transaction actual transfer length\n\toutput TXN_RX_DONE,\t\t\t\t\t\t\t\t// Read transaction done\n\tinput TXN_RX_DONE_ACK,\t\t\t\t\t\t\t// Read transaction actual transfer length read\n\n\toutput TXN_TX,\t\t\t\t\t\t\t\t\t// Write transaction notification\n\tinput TXN_TX_ACK,\t\t\t\t\t\t\t\t// Write transaction acknowledged\n\toutput [31:0] TXN_TX_LEN,\t\t\t\t\t\t// Write transaction length\n\toutput [31:0] TXN_TX_OFF_LAST,\t\t\t\t\t// Write transaction offset/last\n\toutput [31:0] TXN_TX_DONE_LEN,\t\t\t\t\t// Write transaction actual transfer length\n\toutput TXN_TX_DONE,\t\t\t\t\t\t\t\t// Write transaction done\n\tinput TXN_TX_DONE_ACK,\t\t\t\t\t\t\t// Write transaction actual transfer length read\n\n\toutput RX_REQ,\t\t\t\t\t\t\t\t\t// Read request\n\tinput RX_REQ_ACK,\t\t\t\t\t\t\t\t// Read request accepted\n\toutput [1:0] RX_REQ_TAG,\t\t\t\t\t\t// Read request data tag \n\toutput [63:0] RX_REQ_ADDR,\t\t\t\t\t\t// Read request address\n\toutput [9:0] RX_REQ_LEN,\t\t\t\t\t\t// Read request length\n\n\toutput TX_REQ,\t\t\t\t\t\t\t\t\t// Outgoing write request\n\tinput TX_REQ_ACK,\t\t\t\t\t\t\t\t// Outgoing write request acknowledged\n\toutput [63:0] TX_ADDR,\t\t\t\t\t\t\t// Outgoing write high address\n\toutput [9:0] TX_LEN,\t\t\t\t\t\t\t// Outgoing write length (in 32 bit words)\n\toutput [C_DATA_WIDTH-1:0] TX_DATA,\t\t\t\t// Outgoing write data\n\tinput TX_DATA_REN,\t\t\t\t\t\t\t\t// Outgoing write data read enable\n\tinput TX_SENT,\t\t\t\t\t\t\t\t\t// Outgoing write complete\n\n\tinput [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,\t\t// Main incoming data enable\n\tinput MAIN_DONE,\t\t\t\t\t\t\t\t// Main incoming data complete\n\tinput MAIN_ERR,\t\t\t\t\t\t\t\t\t// Main incoming data completed with error\n\n\tinput [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,\t// Scatter gather for RX incoming data enable\n\tinput SG_RX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for RX incoming data complete\n\tinput SG_RX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for RX incoming data completed with error\n\n\tinput [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,\t// Scatter gather for TX incoming data enable\n\tinput SG_TX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for TX incoming data complete\n\tinput SG_TX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for TX incoming data completed with error\n\n\tinput CHNL_RX_CLK,\t\t\t\t\t\t\t\t\t// Channel read clock\n\toutput CHNL_RX,\t\t\t\t\t\t\t\t\t// Channel read receive signal\n\tinput CHNL_RX_ACK,\t\t\t\t\t\t\t\t// Channle read received signal\n\toutput CHNL_RX_LAST,\t\t\t\t\t\t\t// Channel last read\n\toutput [31:0] CHNL_RX_LEN,\t\t\t\t\t\t// Channel read length\n\toutput [30:0] CHNL_RX_OFF,\t\t\t\t\t\t// Channel read offset\n\toutput [C_DATA_WIDTH-1:0] CHNL_RX_DATA,\t\t\t// Channel read data\n\toutput CHNL_RX_DATA_VALID,\t\t\t\t\t\t// Channel read data valid\n\tinput CHNL_RX_DATA_REN, \t\t\t\t\t\t// Channel read data has been recieved\n\n\tinput CHNL_TX_CLK,\t\t\t\t\t\t\t\t// Channel write clock\n\tinput CHNL_TX,\t\t\t\t\t\t\t\t\t// Channel write receive signal\n\toutput CHNL_TX_ACK,\t\t\t\t\t\t\t\t// Channel write acknowledgement signal\n\tinput CHNL_TX_LAST,\t\t\t\t\t\t\t\t// Channel last write\n\tinput [31:0] CHNL_TX_LEN,\t\t\t\t\t\t// Channel write length (in 32 bit words)\n\tinput [30:0] CHNL_TX_OFF,\t\t\t\t\t\t// Channel write offset\n\tinput [C_DATA_WIDTH-1:0] CHNL_TX_DATA,\t\t\t// Channel write data\n\tinput CHNL_TX_DATA_VALID,\t\t\t\t\t\t// Channel write data valid\n\toutput CHNL_TX_DATA_REN\t\t\t\t\t\t\t// Channel write data has been recieved\n);\n\n`include \"common_functions.v\"\n\n\nwire\t[C_DATA_WIDTH-1:0]\twTxSgData;\nwire\t\t\t\t\t\twTxSgDataEmpty;\nwire\t\t\t\t\t\twTxSgDataRen;\nwire\t\t\t\t\t\twTxSgDataErr;\nwire\t\t\t\t\t\twTxSgDataRst;\n\n\n// Receiving port (data to the channel)\nrx_port_64 #(\n\t.C_DATA_WIDTH(C_DATA_WIDTH), \n\t.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH), \n\t.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),\n\t.C_MAX_READ_REQ(C_MAX_READ_REQ)\n) rxPort (\n\t.RST(RST), \n\t.CLK(CLK), \n\t.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE), \n\t\n\t.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),\n\t.SG_RX_BUF_DATA(PIO_DATA),\n\t.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),\n\t.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),\n\t.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),\n\t\n\t.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),\n\t.SG_TX_BUF_DATA(PIO_DATA),\n\t.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),\n\t.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),\n\t.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),\n\t\n\t.SG_DATA(wTxSgData),\n\t.SG_DATA_EMPTY(wTxSgDataEmpty),\n\t.SG_DATA_REN(wTxSgDataRen),\n\t.SG_RST(wTxSgDataRst),\n\t.SG_ERR(wTxSgDataErr),\n\t\n\t.TXN_DATA(PIO_DATA), \n\t.TXN_LEN_VALID(TXN_RX_LEN_VALID), \n\t.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID), \n\t.TXN_DONE_LEN(TXN_RX_DONE_LEN),\n\t.TXN_DONE(TXN_RX_DONE),\n\t.TXN_DONE_ACK(TXN_RX_DONE_ACK),\n\t\n\t.RX_REQ(RX_REQ),\n\t.RX_REQ_ACK(RX_REQ_ACK),\n\t.RX_REQ_TAG(RX_REQ_TAG),\n\t.RX_REQ_ADDR(RX_REQ_ADDR),\n\t.RX_REQ_LEN(RX_REQ_LEN),\n\n\t.MAIN_DATA(ENG_DATA),\n\t.MAIN_DATA_EN(MAIN_DATA_EN), \n\t.MAIN_DONE(MAIN_DONE), \n\t.MAIN_ERR(MAIN_ERR),\n\t\n\t.SG_RX_DATA(ENG_DATA),\n\t.SG_RX_DATA_EN(SG_RX_DATA_EN), \n\t.SG_RX_DONE(SG_RX_DONE), \n\t.SG_RX_ERR(SG_RX_ERR),\n\n\t.SG_TX_DATA(ENG_DATA),\n\t.SG_TX_DATA_EN(SG_TX_DATA_EN), \n\t.SG_TX_DONE(SG_TX_DONE), \n\t.SG_TX_ERR(SG_TX_ERR),\n\n\t.CHNL_CLK(CHNL_RX_CLK), \n\t.CHNL_RX(CHNL_RX), \n\t.CHNL_RX_ACK(CHNL_RX_ACK), \n\t.CHNL_RX_LAST(CHNL_RX_LAST), \n\t.CHNL_RX_LEN(CHNL_RX_LEN), \n\t.CHNL_RX_OFF(CHNL_RX_OFF), \n\t.CHNL_RX_DATA(CHNL_RX_DATA), \n\t.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), \n\t.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)\n);\n\n\n// Sending port (data from the channel)\ntx_port_64 #(\n\t.C_DATA_WIDTH(C_DATA_WIDTH), \n\t.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)\n) txPort (\n\t.CLK(CLK), \n\t.RST(RST), \n\t.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE), \n\t\n\t.TXN(TXN_TX),\n\t.TXN_ACK(TXN_TX_ACK),\n\t.TXN_LEN(TXN_TX_LEN),\n\t.TXN_OFF_LAST(TXN_TX_OFF_LAST),\n\t.TXN_DONE_LEN(TXN_TX_DONE_LEN),\n\t.TXN_DONE(TXN_TX_DONE),\n\t.TXN_DONE_ACK(TXN_TX_DONE_ACK),\n\t\n\t.SG_DATA(wTxSgData),\n\t.SG_DATA_EMPTY(wTxSgDataEmpty),\n\t.SG_DATA_REN(wTxSgDataRen),\n\t.SG_RST(wTxSgDataRst),\n\t.SG_ERR(wTxSgDataErr),\n\t\n\t.TX_REQ(TX_REQ), \n\t.TX_REQ_ACK(TX_REQ_ACK),\n\t.TX_ADDR(TX_ADDR), \n\t.TX_LEN(TX_LEN), \n\t.TX_DATA(TX_DATA),\n\t.TX_DATA_REN(TX_DATA_REN), \n\t.TX_SENT(TX_SENT),\n\n\t.CHNL_CLK(CHNL_TX_CLK), \n\t.CHNL_TX(CHNL_TX), \n\t.CHNL_TX_ACK(CHNL_TX_ACK),\n\t.CHNL_TX_LAST(CHNL_TX_LAST), \n\t.CHNL_TX_LEN(CHNL_TX_LEN), \n\t.CHNL_TX_OFF(CHNL_TX_OFF), \n\t.CHNL_TX_DATA(CHNL_TX_DATA), \n\t.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID), \n\t.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)\n);\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/chnl_tester.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tchnl_tester.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tSample RIFFA channel user module. Designed to exercise\n// \t\t\t\t\t\tthe RIFFA TX and RX interfaces. Receives data on the\n//\t\t\t\t\t\tRX interface and saves the last value received. Sends\n//\t\t\t\t\t\tthe same amount of data back on the TX interface. The\n//\t\t\t\t\t\treturned data starts with the last value received, \n//\t\t\t\t\t\tresets and increments to end with a value equal to the\n//\t\t\t\t\t\tnumber of (4 byte) words sent back on the TX interface.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule chnl_tester #(\n\tparameter C_PCI_DATA_WIDTH = 9'd32\n)\n(\n\tinput CLK,\n\tinput RST,\n\toutput CHNL_RX_CLK, \n\tinput CHNL_RX, \n\toutput CHNL_RX_ACK, \n\tinput CHNL_RX_LAST, \n\tinput [31:0] CHNL_RX_LEN, \n\tinput [30:0] CHNL_RX_OFF, \n\tinput [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA, \n\tinput CHNL_RX_DATA_VALID, \n\toutput CHNL_RX_DATA_REN,\n\t\n\toutput CHNL_TX_CLK, \n\toutput CHNL_TX, \n\tinput CHNL_TX_ACK, \n\toutput CHNL_TX_LAST, \n\toutput [31:0] CHNL_TX_LEN, \n\toutput [30:0] CHNL_TX_OFF, \n\toutput [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA, \n\toutput CHNL_TX_DATA_VALID, \n\tinput CHNL_TX_DATA_REN\n);\n\nreg [C_PCI_DATA_WIDTH-1:0] rData={C_PCI_DATA_WIDTH{1'b0}};\nreg [31:0] rLen=0;\nreg [31:0] rCount=0;\nreg [1:0] rState=0;\n\nassign CHNL_RX_CLK = CLK;\nassign CHNL_RX_ACK = (rState == 2'd1);\nassign CHNL_RX_DATA_REN = (rState == 2'd1);\n\nassign CHNL_TX_CLK = CLK;\nassign CHNL_TX = (rState == 2'd3);\nassign CHNL_TX_LAST = 1'd1;\nassign CHNL_TX_LEN = rLen; // in words\nassign CHNL_TX_OFF = 0;\nassign CHNL_TX_DATA = rData;\nassign CHNL_TX_DATA_VALID = (rState == 2'd3);\n\nalways @(posedge CLK or posedge RST) begin\n\tif (RST) begin\n\t\trLen <= #1 0;\n\t\trCount <= #1 0;\n\t\trState <= #1 0;\n\t\trData <= #1 0;\n\tend\n\telse begin\n\t\tcase (rState)\n\t\t\n\t\t2'd0: begin // Wait for start of RX, save length\n\t\t\tif (CHNL_RX) begin\n\t\t\t\trLen <= #1 CHNL_RX_LEN;\n\t\t\t\trCount <= #1 0;\n\t\t\t\trState <= #1 2'd1;\n\t\t\tend\n\t\tend\n\t\t\n\t\t2'd1: begin // Wait for last data in RX, save value\n\t\t\tif (CHNL_RX_DATA_VALID) begin\n\t\t\t\trData <= #1 CHNL_RX_DATA;\n\t\t\t\trCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);\n\t\t\tend\n\t\t\tif (rCount >= rLen)\n\t\t\t\trState <= #1 2'd2;\n\t\tend\n\n\t\t2'd2: begin // Prepare for TX\n\t\t\trCount <= #1 (C_PCI_DATA_WIDTH/32);\n\t\t\trState <= #1 2'd3;\n\t\tend\n\n\t\t2'd3: begin // Start TX with save length and data value\n\t\t\tif (CHNL_TX_DATA_REN & CHNL_TX_DATA_VALID) begin\n\t\t\t\trData <= #1 {rCount + 4, rCount + 3, rCount + 2, rCount + 1};\n\t\t\t\trCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);\n\t\t\t\tif (rCount >= rLen)\n\t\t\t\t\trState <= #1 2'd0;\n\t\t\tend\n\t\tend\n\t\t\n\t\tendcase\n\tend\nend\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/common_functions.v", "content": "//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tcommon_functions.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tCommonly used functions in the design. Mostly used in\n//\t\t\t\t\t\tparameter values. Many of these functions are supported\n//\t\t\t\t\t\tin System Verilog, but Xilinx tools do not fully\n// \t\t\t\t\t\tsupport System Verilog.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n\n// clog2 -- calculate the ceiling log2 value.\nfunction integer clog2;\n\tinput [31:0] v;\n\treg [31:0] value;\n\tbegin\n\t\tvalue = v;\n\t\tif (value == 1) begin\n\t\t\tclog2 = 0;\n\t\tend\n\t\telse begin\n\t\t\tvalue = value-1;\n\t\t\tfor (clog2=0; value>0; clog2=clog2+1)\n\t\t\t\tvalue = value>>1;\n\t\tend\n\tend\nendfunction\n\n\n// clog2s -- calculate the ceiling log2 value, min return is 1 (safe).\nfunction integer clog2s;\n\tinput [31:0] v;\n\treg [31:0] value;\n\tbegin\n\t\tvalue = v;\n\t\tif (value == 1) begin\n\t\t\tclog2s = 1;\n\t\tend\n\t\telse begin\n\t\t\tvalue = value-1;\n\t\t\tfor (clog2s=0; value>0; clog2s=clog2s+1)\n\t\t\t\tvalue = value>>1;\n\t\tend\n\tend\nendfunction\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/cross_domain_signal.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tcross_domain_signal.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tSend a signal from clock domain A into clock domain B\n// and get the signal back into clock domain A. Domain A can know roughly when \n// the signal is received domain B. \n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n\nmodule cross_domain_signal (\n\tinput CLK_A,\t\t// Clock for domain A\n\tinput CLK_A_SEND,\t// Signal from domain A to domain B\n\toutput CLK_A_RECV,\t// Signal from domain B received in domain A \n\tinput CLK_B,\t\t// Clock for domain B\n\toutput CLK_B_RECV,\t// Signal from domain A received in domain B\n\tinput CLK_B_SEND\t// Signal from domain B to domain A\n);\n\n\n// Sync level signals across domains.\nsyncff sigAtoB (.CLK(CLK_B), .IN_ASYNC(CLK_A_SEND), .OUT_SYNC(CLK_B_RECV));\nsyncff sigBtoA (.CLK(CLK_A), .IN_ASYNC(CLK_B_SEND), .OUT_SYNC(CLK_A_RECV));\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/demux_1_to_n.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tdemux_1_to_n.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tStatically sized 1 to n demultiplexer.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule demux_1_to_n #(\n\tparameter C_FACTOR = 12,\n\tparameter C_WIDTH = 1,\n\t// Local parameters\n\tparameter C_SEL_WIDTH = clog2s(C_FACTOR)\n)\n(\n\tinput [C_WIDTH-1:0] IN,\t\t\t\t\t// Inputs\n\toutput [(C_FACTOR*C_WIDTH)-1:0] OUT,\t// Outputs\n\tinput [C_SEL_WIDTH-1:0] SEL\t\t\t\t// Selector\n);\n\n`include \"common_functions.v\"\n\n//assign OUT = (IN<<(C_WIDTH*SEL));\n\ngenvar i;\ngenerate\n\tfor(i = 0; i < C_FACTOR; i = i + 1) begin: assignments\n\t\tassign OUT[(i*C_WIDTH) +:C_WIDTH] = (SEL == i ? IN : {C_WIDTH{1'b0}});\n\tend\nendgenerate\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/ff.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tff.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tA D/Q flip flop.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule ff(\n\tCLK,\n\tD,\n\tQ\n);\n\ninput \t\t\t\t\tCLK;\ninput \t\t\t\t\tD;\noutput \t\t\t\tQ;\n\nreg\t\t\t\t\t\tQ;\n\nalways @ (posedge CLK) begin \n\tQ <= #1 D; \nend\n\t\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/fifo_packer_128.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tfifo_packer_128.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tPacks 32, 64, or 96 bit received data into a 128 bit wide \n// FIFO. Assumes the FIFO always has room to accommodate the data.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: \n//-----------------------------------------------------------------------------\n\nmodule fifo_packer_128 (\n\tinput CLK,\n\tinput RST,\n\tinput [127:0] DATA_IN,\t\t// Incoming data\n\tinput [2:0] DATA_IN_EN,\t\t// Incoming data enable\n\tinput DATA_IN_DONE,\t\t\t// Incoming data packet end\n\tinput DATA_IN_ERR,\t\t\t// Incoming data error\n\tinput DATA_IN_FLUSH,\t\t// End of incoming data\n\toutput [127:0] PACKED_DATA,\t// Outgoing data\n\toutput PACKED_WEN,\t\t\t// Outgoing data write enable\n\toutput PACKED_DATA_DONE,\t// End of outgoing data packet\n\toutput PACKED_DATA_ERR,\t\t// Error in outgoing data\n\toutput PACKED_DATA_FLUSHED\t// End of outgoing data\n);\n\nreg\t\t[2:0]\t\trPackedCount=0, _rPackedCount=0;\nreg\t\t\t\t\trPackedDone=0, _rPackedDone=0;\nreg\t\t\t\t\trPackedErr=0, _rPackedErr=0;\nreg\t\t\t\t\trPackedFlush=0, _rPackedFlush=0;\nreg\t\t\t\t\trPackedFlushed=0, _rPackedFlushed=0;\nreg\t\t[223:0]\t\trPackedData=224'd0, _rPackedData=224'd0;\nreg\t\t[127:0]\t\trDataIn=128'd0, _rDataIn=128'd0;\nreg\t\t[2:0]\t\trDataInEn=0, _rDataInEn=0;\nreg\t\t[127:0]\t\trDataMasked=128'd0, _rDataMasked=128'd0;\nreg\t\t[2:0]\t\trDataMaskedEn=0, _rDataMaskedEn=0;\n\n\nassign PACKED_DATA = rPackedData[127:0];\nassign PACKED_WEN = rPackedCount[2];\nassign PACKED_DATA_DONE = rPackedDone;\nassign PACKED_DATA_ERR = rPackedErr;\nassign PACKED_DATA_FLUSHED = rPackedFlushed;\n\n\n// Buffers input data until 4 words are available, then writes 4 words out.\nwire [127:0] wMask = {128{1'b1}}<<(32*rDataInEn);\nwire [127:0] wDataMasked = ~wMask & rDataIn;\nalways @ (posedge CLK) begin\n\trPackedCount <= #1 (RST ? 3'd0 : _rPackedCount);\n\trPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);\n\trPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);\n\trPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);\n\trPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);\n\trPackedData <= #1 (RST ? 224'd0 : _rPackedData);\n\trDataIn <= #1 _rDataIn;\n\trDataInEn <= #1 (RST ? 3'd0 : _rDataInEn);\n\trDataMasked <= #1 _rDataMasked;\n\trDataMaskedEn <= #1 (RST ? 3'd0 : _rDataMaskedEn);\nend\n\nalways @ (*) begin\n\t// Buffer and mask the input data.\n\t_rDataIn = DATA_IN;\n\t_rDataInEn = DATA_IN_EN;\n\t_rDataMasked = wDataMasked;\n\t_rDataMaskedEn = rDataInEn;\n\n\t// Count what's in our buffer. When we reach 4 words, 4 words will be written\n\t// out. If flush is requested, write out whatever remains.\n\tif (rPackedFlush && (rPackedCount[1] | rPackedCount[0]))\n\t\t_rPackedCount = 4;\n\telse\n\t\t_rPackedCount = rPackedCount + rDataMaskedEn - {rPackedCount[2], 2'd0};\n\t\n\t// Shift data into and out of our buffer as we receive and write out data.\n\tif (rDataMaskedEn != 3'd0)\n\t\t_rPackedData = ((rPackedData>>(32*{rPackedCount[2], 2'd0})) | (rDataMasked<<(32*rPackedCount[1:0])));\n\telse\n\t\t_rPackedData = (rPackedData>>(32*{rPackedCount[2], 2'd0}));\n\n\t// Track done/error/flush signals.\n\t_rPackedDone = DATA_IN_DONE;\n\t_rPackedErr = DATA_IN_ERR;\n\t_rPackedFlush = DATA_IN_FLUSH;\n\t_rPackedFlushed = rPackedFlush;\nend\n\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/fifo_packer_32.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tfifo_packer_32.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tPacks 32 bit received data into a 32 bit wide FIFO. \n// Assumes the FIFO always has room to accommodate the data.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: \n//-----------------------------------------------------------------------------\n\nmodule fifo_packer_32 (\n\tinput CLK,\n\tinput RST,\n\tinput [31:0] DATA_IN,\t\t// Incoming data\n\tinput DATA_IN_EN,\t\t\t// Incoming data enable\n\tinput DATA_IN_DONE,\t\t\t// Incoming data packet end\n\tinput DATA_IN_ERR,\t\t\t// Incoming data error\n\tinput DATA_IN_FLUSH,\t\t// End of incoming data\n\toutput [31:0] PACKED_DATA,\t// Outgoing data\n\toutput PACKED_WEN,\t\t\t// Outgoing data write enable\n\toutput PACKED_DATA_DONE,\t// End of outgoing data packet\n\toutput PACKED_DATA_ERR,\t\t// Error in outgoing data\n\toutput PACKED_DATA_FLUSHED\t// End of outgoing data\n);\n\nreg\t\t\t\t\trPackedDone=0, _rPackedDone=0;\nreg\t\t\t\t\trPackedErr=0, _rPackedErr=0;\nreg\t\t\t\t\trPackedFlush=0, _rPackedFlush=0;\nreg\t\t\t\t\trPackedFlushed=0, _rPackedFlushed=0;\nreg\t\t[31:0]\t\trDataIn=64'd0, _rDataIn=64'd0;\nreg\t\t\t\t\trDataInEn=0, _rDataInEn=0;\n\n\nassign PACKED_DATA = rDataIn;\nassign PACKED_WEN = rDataInEn;\nassign PACKED_DATA_DONE = rPackedDone;\nassign PACKED_DATA_ERR = rPackedErr;\nassign PACKED_DATA_FLUSHED = rPackedFlushed;\n\n\n// Buffers input data to ease timing.\nalways @ (posedge CLK) begin\n\trPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);\n\trPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);\n\trPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);\n\trPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);\n\trDataIn <= #1 _rDataIn;\n\trDataInEn <= #1 (RST ? 1'd0 : _rDataInEn);\nend\n\nalways @ (*) begin\n\t// Buffer and mask the input data.\n\t_rDataIn = DATA_IN;\n\t_rDataInEn = DATA_IN_EN;\n\n\t// Track done/error/flush signals.\n\t_rPackedDone = DATA_IN_DONE;\n\t_rPackedErr = DATA_IN_ERR;\n\t_rPackedFlush = DATA_IN_FLUSH;\n\t_rPackedFlushed = rPackedFlush;\nend\n\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/fifo_packer_64.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tfifo_packer_64.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tPacks 32 or 64 bit received data into a 64 bit wide FIFO. \n// Assumes the FIFO always has room to accommodate the data.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: \n//-----------------------------------------------------------------------------\n\nmodule fifo_packer_64 (\n\tinput CLK,\n\tinput RST,\n\tinput [63:0] DATA_IN,\t\t// Incoming data\n\tinput [1:0] DATA_IN_EN,\t\t// Incoming data enable\n\tinput DATA_IN_DONE,\t\t\t// Incoming data packet end\n\tinput DATA_IN_ERR,\t\t\t// Incoming data error\n\tinput DATA_IN_FLUSH,\t\t// End of incoming data\n\toutput [63:0] PACKED_DATA,\t// Outgoing data\n\toutput PACKED_WEN,\t\t\t// Outgoing data write enable\n\toutput PACKED_DATA_DONE,\t// End of outgoing data packet\n\toutput PACKED_DATA_ERR,\t\t// Error in outgoing data\n\toutput PACKED_DATA_FLUSHED\t// End of outgoing data\n);\n\nreg\t\t[1:0]\t\trPackedCount=0, _rPackedCount=0;\nreg\t\t\t\t\trPackedDone=0, _rPackedDone=0;\nreg\t\t\t\t\trPackedErr=0, _rPackedErr=0;\nreg\t\t\t\t\trPackedFlush=0, _rPackedFlush=0;\nreg\t\t\t\t\trPackedFlushed=0, _rPackedFlushed=0;\nreg\t\t[95:0]\t\trPackedData=96'd0, _rPackedData=96'd0;\nreg\t\t[63:0]\t\trDataIn=64'd0, _rDataIn=64'd0;\nreg\t\t[1:0]\t\trDataInEn=0, _rDataInEn=0;\nreg\t\t[63:0]\t\trDataMasked=64'd0, _rDataMasked=64'd0;\nreg\t\t[1:0]\t\trDataMaskedEn=0, _rDataMaskedEn=0;\n\n\nassign PACKED_DATA = rPackedData[63:0];\nassign PACKED_WEN = rPackedCount[1];\nassign PACKED_DATA_DONE = rPackedDone;\nassign PACKED_DATA_ERR = rPackedErr;\nassign PACKED_DATA_FLUSHED = rPackedFlushed;\n\n\n// Buffers input data until 2 words are available, then writes 2 words out.\nwire [63:0] wMask = {64{1'b1}}<<(32*rDataInEn);\nwire [63:0]\twDataMasked = ~wMask & rDataIn;\nalways @ (posedge CLK) begin\n\trPackedCount <= #1 (RST ? 2'd0 : _rPackedCount);\n\trPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);\n\trPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);\n\trPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);\n\trPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);\n\trPackedData <= #1 (RST ? 96'd0 : _rPackedData);\n\trDataIn <= #1 _rDataIn;\n\trDataInEn <= #1 (RST ? 2'd0 : _rDataInEn);\n\trDataMasked <= #1 _rDataMasked;\n\trDataMaskedEn <= #1 (RST ? 2'd0 : _rDataMaskedEn);\nend\n\nalways @ (*) begin\n\t// Buffer and mask the input data.\n\t_rDataIn = DATA_IN;\n\t_rDataInEn = DATA_IN_EN;\n\t_rDataMasked = wDataMasked;\n\t_rDataMaskedEn = rDataInEn;\n\n\t// Count what's in our buffer. When we reach 2 words, 2 words will be written\n\t// out. If flush is requested, write out whatever remains.\n\tif (rPackedFlush && rPackedCount[0])\n\t\t_rPackedCount = 2;\n\telse\n\t\t_rPackedCount = rPackedCount + rDataMaskedEn - {rPackedCount[1], 1'd0};\n\t\n\t// Shift data into and out of our buffer as we receive and write out data.\n\tif (rDataMaskedEn != 2'd0)\n\t\t_rPackedData = ((rPackedData>>(32*{rPackedCount[1], 1'd0})) | (rDataMasked<<(32*rPackedCount[0])));\n\telse\n\t\t_rPackedData = (rPackedData>>(32*{rPackedCount[1], 1'd0}));\n\n\t// Track done/error/flush signals.\n\t_rPackedDone = DATA_IN_DONE;\n\t_rPackedErr = DATA_IN_ERR;\n\t_rPackedFlush = DATA_IN_FLUSH;\n\t_rPackedFlushed = rPackedFlush;\nend\n\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/gtx_drp_chanalign_fix_3752_v6.v", "content": "\n//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : gtx_drp_chanalign_fix_3752_v6.v\n// Version : 2.4\n//--\n//-- Description: Virtex6 Workaround for deadlock due lane-lane skew Bug\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns / 1ps\nmodule GTX_DRP_CHANALIGN_FIX_3752_V6\n#(\n parameter TCQ = 1,\n parameter C_SIMULATION = 0 // Set to 1 for simulation\n)\n(\n output reg dwe,\n output reg [15:0] din, //THIS IS THE INPUT TO THE DRP\n output reg den,\n output reg [7:0] daddr,\n output reg [3:0] drpstate,\n input write_ts1,\n input write_fts,\n input [15:0] dout, //THIS IS THE OUTPUT OF THE DRP\n input drdy,\n input Reset_n,\n input drp_clk\n\n);\n\n\n reg [7:0] next_daddr;\n reg [3:0] next_drpstate;\n\n\n\n reg write_ts1_gated;\n reg write_fts_gated;\n\n\n localparam DRP_IDLE_FTS = 1;\n localparam DRP_IDLE_TS1 = 2;\n localparam DRP_RESET = 3;\n localparam DRP_WRITE_FTS = 6;\n localparam DRP_WRITE_DONE_FTS = 7;\n localparam DRP_WRITE_TS1 = 8;\n localparam DRP_WRITE_DONE_TS1 = 9;\n localparam DRP_COM = 10'b0110111100;\n localparam DRP_FTS = 10'b0100111100;\n localparam DRP_TS1 = 10'b0001001010;\n\n\n always @(posedge drp_clk) begin\n\n if ( ~Reset_n ) begin\n\n daddr <= #(TCQ) 8'h8;\n drpstate <= #(TCQ) DRP_RESET;\n\n\n write_ts1_gated <= #(TCQ) 0;\n write_fts_gated <= #(TCQ) 0;\n\n end else begin\n\n daddr <= #(TCQ) next_daddr;\n drpstate <= #(TCQ) next_drpstate;\n\n\n\n write_ts1_gated <= #(TCQ) write_ts1;\n write_fts_gated <= #(TCQ) write_fts;\n\n end\n\n end\n\n\n always @(*) begin\n\n // DEFAULT CONDITIONS\n next_drpstate=drpstate;\n next_daddr=daddr;\n den=0;\n din=0;\n dwe=0;\n\n case(drpstate)\n\n // RESET CONDITION, WE NEED TO READ THE TOP 6 BITS OF THE DRP REGISTER WHEN WE GET THE WRITE FTS TRIGGER\n DRP_RESET : begin\n\n next_drpstate= DRP_WRITE_TS1;\n next_daddr=8'h8;\n\n end\n\n\n\n // WRITE FTS SEQUENCE\n DRP_WRITE_FTS : begin\n\n den=1;\n dwe=1;\n case (daddr)\n 8'h8 : din = 16'hFD3C;\n 8'h9 : din = 16'hC53C;\n 8'hA : din = 16'hFDBC;\n 8'hB : din = 16'h853C;\n endcase\n next_drpstate=DRP_WRITE_DONE_FTS;\n\n end\n\n // WAIT FOR FTS SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO FTS IDLE\n DRP_WRITE_DONE_FTS : begin\n\n if(drdy) begin\n\n if(daddr==8'hB) begin\n\n next_drpstate=DRP_IDLE_FTS;\n next_daddr=8'h8;\n\n end else begin\n\n next_drpstate=DRP_WRITE_FTS;\n next_daddr=daddr+1'b1;\n\n end\n\n end\n\n end\n\n // FTS IDLE: WAIT HERE UNTIL WE NEED TO WRITE TS1\n DRP_IDLE_FTS : begin\n\n if(write_ts1_gated) begin\n\n next_drpstate=DRP_WRITE_TS1;\n next_daddr=8'h8;\n\n end\n\n end\n\n // WRITE TS1 SEQUENCE\n DRP_WRITE_TS1 : begin\n den=1;\n dwe=1;\n case (daddr)\n 8'h8 : din = 16'hFC4A;\n 8'h9 : din = 16'hDC4A;\n 8'hA : din = 16'hC04A;\n 8'hB : din = 16'h85BC;\n endcase\n next_drpstate=DRP_WRITE_DONE_TS1;\n\n end\n\n // WAIT FOR TS1 SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO TS1 IDLE\n DRP_WRITE_DONE_TS1 : begin\n\n if(drdy) begin\n\n if(daddr==8'hB) begin\n\n next_drpstate=DRP_IDLE_TS1;\n next_daddr=8'h8;\n\n end else begin\n\n next_drpstate=DRP_WRITE_TS1;\n next_daddr=daddr+1'b1;\n\n end\n\n end\n\n end\n\n // TS1 IDLE: WAIT HERE UNTIL WE NEED TO WRITE FTS\n DRP_IDLE_TS1 : begin\n\n if(write_fts_gated) begin\n\n next_drpstate=DRP_WRITE_FTS;\n next_daddr=8'h8;\n\n end\n\n end\n\n endcase\n\n end\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/gtx_rx_valid_filter_v6.v", "content": "\n//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : gtx_rx_valid_filter_v6.v\n// Version : 2.4\n\n`timescale 1ns / 1ns\n\nmodule GTX_RX_VALID_FILTER_V6 #(\n\n parameter CLK_COR_MIN_LAT = 28,\n parameter TCQ = 1\n\n)\n(\n output [1:0] USER_RXCHARISK,\n output [15:0] USER_RXDATA,\n output USER_RXVALID,\n output USER_RXELECIDLE,\n output [ 2:0] USER_RX_STATUS,\n output USER_RX_PHY_STATUS,\n\n input [1:0] GT_RXCHARISK,\n input [15:0] GT_RXDATA,\n input GT_RXVALID,\n input GT_RXELECIDLE,\n input [ 2:0] GT_RX_STATUS,\n input GT_RX_PHY_STATUS,\n\n input PLM_IN_L0,\n input PLM_IN_RS,\n\n input USER_CLK,\n input RESET\n\n);\n\n\n\n localparam EIOS_DET_IDL = 5'b00001;\n localparam EIOS_DET_NO_STR0 = 5'b00010;\n localparam EIOS_DET_STR0 = 5'b00100;\n localparam EIOS_DET_STR1 = 5'b01000;\n localparam EIOS_DET_DONE = 5'b10000;\n\n localparam EIOS_COM = 8'hBC;\n localparam EIOS_IDL = 8'h7C;\n localparam FTSOS_COM = 8'hBC;\n localparam FTSOS_FTS = 8'h3C;\n\n reg [4:0] reg_state_eios_det;\n wire [4:0] state_eios_det;\n\n reg reg_eios_detected;\n wire eios_detected;\n\n reg reg_symbol_after_eios;\n wire symbol_after_eios;\n\n localparam USER_RXVLD_IDL = 4'b0001;\n localparam USER_RXVLD_EI = 4'b0010;\n localparam USER_RXVLD_EI_DB0 = 4'b0100;\n localparam USER_RXVLD_EI_DB1 = 4'b1000;\n\n reg [3:0] reg_state_rxvld_ei;\n wire [3:0] state_rxvld_ei;\n\n reg [4:0] reg_rxvld_count;\n wire [4:0] rxvld_count;\n\n reg [3:0] reg_rxvld_fallback;\n wire [3:0] rxvld_fallback;\n\n reg [1:0] gt_rxcharisk_q;\n reg [15:0] gt_rxdata_q;\n reg gt_rxvalid_q;\n reg gt_rxelecidle_q;\n reg gt_rxelecidle_qq;\n\n reg [ 2:0] gt_rx_status_q;\n reg gt_rx_phy_status_q;\n reg gt_rx_is_skp0_q;\n reg gt_rx_is_skp1_q;\n\n // EIOS detector\n\n always @(posedge USER_CLK) begin\n\n if (RESET) begin\n\n reg_eios_detected <= #TCQ 1'b0;\n reg_state_eios_det <= #TCQ EIOS_DET_IDL;\n reg_symbol_after_eios <= #TCQ 1'b0;\n gt_rxcharisk_q <= #TCQ 2'b00;\n gt_rxdata_q <= #TCQ 16'h0;\n gt_rxvalid_q <= #TCQ 1'b0;\n gt_rxelecidle_q <= #TCQ 1'b0;\n gt_rxelecidle_qq <= #TCQ 1'b0;\n gt_rx_status_q <= #TCQ 3'b000;\n gt_rx_phy_status_q <= #TCQ 1'b0;\n gt_rx_is_skp0_q <= #TCQ 1'b0;\n gt_rx_is_skp1_q <= #TCQ 1'b0;\n\n end else begin\n\n reg_eios_detected <= #TCQ 1'b0;\n reg_symbol_after_eios <= #TCQ 1'b0;\n gt_rxcharisk_q <= #TCQ GT_RXCHARISK;\n gt_rxdata_q <= #TCQ GT_RXDATA;\n gt_rxvalid_q <= #TCQ GT_RXVALID;\n gt_rxelecidle_q <= #TCQ GT_RXELECIDLE;\n gt_rxelecidle_qq <= #TCQ gt_rxelecidle_q;\n gt_rx_status_q <= #TCQ GT_RX_STATUS;\n gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS;\n\n if (GT_RXCHARISK[0] && GT_RXDATA[7:0] == FTSOS_FTS)\n gt_rx_is_skp0_q <= #TCQ 1'b1;\n else\n gt_rx_is_skp0_q <= #TCQ 1'b0;\n\n if (GT_RXCHARISK[1] && GT_RXDATA[15:8] == FTSOS_FTS)\n gt_rx_is_skp1_q <= #TCQ 1'b1;\n else\n gt_rx_is_skp1_q <= #TCQ 1'b0;\n\n case ( state_eios_det )\n\n EIOS_DET_IDL : begin\n\n if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) &&\n (gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin\n\n reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0;\n reg_eios_detected <= #TCQ 1'b1;\n\n end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM))\n reg_state_eios_det <= #TCQ EIOS_DET_STR0;\n else\n reg_state_eios_det <= #TCQ EIOS_DET_IDL;\n\n end\n\n EIOS_DET_NO_STR0 : begin\n\n if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&\n (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL)))\n reg_state_eios_det <= #TCQ EIOS_DET_DONE;\n else\n reg_state_eios_det <= #TCQ EIOS_DET_IDL;\n\n end\n\n EIOS_DET_STR0 : begin\n\n if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&\n (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin\n\n reg_state_eios_det <= #TCQ EIOS_DET_STR1;\n reg_eios_detected <= #TCQ 1'b1;\n reg_symbol_after_eios <= #TCQ 1'b1;\n\n end else\n reg_state_eios_det <= #TCQ EIOS_DET_IDL;\n\n end\n\n EIOS_DET_STR1 : begin\n\n if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL))\n reg_state_eios_det <= #TCQ EIOS_DET_DONE;\n else\n reg_state_eios_det <= #TCQ EIOS_DET_IDL;\n\n end\n\n EIOS_DET_DONE : begin\n\n reg_state_eios_det <= #TCQ EIOS_DET_IDL;\n\n end\n\n endcase\n\n end\n\n end\n assign state_eios_det = reg_state_eios_det;\n assign eios_detected = reg_eios_detected;\n assign symbol_after_eios = reg_symbol_after_eios;\n\n // user_rxvalid generation\n\n always @(posedge USER_CLK) begin\n\n if (RESET) begin\n\n reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;\n\n end else begin\n\n case ( state_rxvld_ei )\n\n USER_RXVLD_IDL : begin\n\n if (eios_detected)\n reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI;\n else\n reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;\n\n end\n\n USER_RXVLD_EI : begin\n\n if (!gt_rxvalid_q)\n reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB0;\n else if (rxvld_fallback == 4'b1111)\n reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;\n else\n reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI;\n\n end\n\n USER_RXVLD_EI_DB0 : begin\n\n if (gt_rxvalid_q)\n reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB1;\n else if (!PLM_IN_L0)\n reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;\n else\n reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB0;\n\n end\n\n USER_RXVLD_EI_DB1 : begin\n\n if (rxvld_count > CLK_COR_MIN_LAT)\n reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;\n else\n reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB1;\n\n end\n\n endcase\n\n end\n\n end\n assign state_rxvld_ei = reg_state_rxvld_ei;\n\n // RxValid counter\n\n always @(posedge USER_CLK) begin\n\n if (RESET) begin\n\n reg_rxvld_count <= #TCQ 5'b00000;\n\n end else begin\n\n if ((gt_rxvalid_q) && (state_rxvld_ei == USER_RXVLD_EI_DB1))\n reg_rxvld_count <= #TCQ reg_rxvld_count + 1'b1;\n else\n reg_rxvld_count <= #TCQ 5'b00000;\n\n end\n\n end\n assign rxvld_count = reg_rxvld_count;\n\n // RxValid fallback\n\n always @(posedge USER_CLK) begin\n\n if (RESET) begin\n\n reg_rxvld_fallback <= #TCQ 4'b0000;\n\n end else begin\n\n if (state_rxvld_ei == USER_RXVLD_EI)\n reg_rxvld_fallback <= #TCQ reg_rxvld_fallback + 1'b1;\n else\n reg_rxvld_fallback <= #TCQ 4'b0000;\n\n end\n\n end\n assign rxvld_fallback = reg_rxvld_fallback;\n\n // Delay pipe_rx_elec_idle\n\n SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE),\n .D(gt_rxelecidle_q),\n .CLK(USER_CLK),\n .CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));\n\n\nreg awake_in_progress_q = 1'b0;\nreg awake_see_com_q = 1'b0;\nreg [3:0] awake_com_count_q = 4'b0000;\n\nwire awake_see_com_0 = gt_rxvalid_q & (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_COM));\nwire awake_see_com_1 = gt_rxvalid_q & (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_COM));\nwire awake_see_com = (awake_see_com_0 || awake_see_com_1) && ~awake_see_com_q;\n\n// Count 8 COMs, (not back-to-back), when waking up from electrical idle\n// but not for L0s (which is L0).\n\nwire awake_done = awake_in_progress_q && (awake_com_count_q[3:0] >= 4'hb);\nwire awake_start = (~gt_rxelecidle_q && gt_rxelecidle_qq) || PLM_IN_RS;\n\nwire awake_in_progress = awake_start || (~awake_done && awake_in_progress_q);\nwire [3:0] awake_com_count_inced = awake_com_count_q[3:0] + 4'b0001;\nwire [3:0] awake_com_count = (~awake_in_progress_q) ? 4'b0000 :\n (awake_start) ? 4'b0000 :\n (awake_see_com_q) ? awake_com_count_inced[3:0] :\n awake_com_count_q[3:0];\n\nwire rst_l = ~RESET;\nalways @(posedge USER_CLK) begin\n awake_see_com_q <= #TCQ (rst_l) ? awake_see_com : 1'b0;\n awake_in_progress_q <= #TCQ (rst_l) ? awake_in_progress : 1'b0;\n awake_com_count_q[3:0] <= #TCQ (rst_l) ? awake_com_count[3:0] : 4'h0;\nend\n\n\n assign USER_RXVALID = ((state_rxvld_ei == USER_RXVLD_IDL) && ~awake_in_progress_q) ? gt_rxvalid_q : 1'b0;\n assign USER_RXCHARISK[0] = USER_RXVALID ? gt_rxcharisk_q[0] : 1'b0;\n assign USER_RXCHARISK[1] = (USER_RXVALID && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0;\n assign USER_RXDATA[7:0] = (gt_rx_is_skp0_q) ? FTSOS_COM : gt_rxdata_q[7:0];\n assign USER_RXDATA[15:8] = (gt_rx_is_skp1_q) ? FTSOS_COM : gt_rxdata_q[15:8];\n assign USER_RX_STATUS = (state_rxvld_ei == USER_RXVLD_IDL) ? gt_rx_status_q : 3'b000;\n assign USER_RX_PHY_STATUS = gt_rx_phy_status_q;\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/gtx_tx_sync_rate_v6.v", "content": "\n//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : gtx_tx_sync_rate_v6.v\n// Version : 2.4\n// Module TX_SYNC\n\n`timescale 1ns / 1ps\n\nmodule GTX_TX_SYNC_RATE_V6\n#(\n parameter TCQ = 1,\n parameter C_SIMULATION = 0 // Set to 1 for simulation\n)\n(\n output reg ENPMAPHASEALIGN = 1'b0,\n output reg PMASETPHASE = 1'b0,\n output reg SYNC_DONE = 1'b0,\n output reg OUT_DIV_RESET = 1'b0,\n output reg PCS_RESET = 1'b0,\n output reg USER_PHYSTATUS = 1'b0,\n output reg TXALIGNDISABLE = 1'b0,\n output reg DELAYALIGNRESET = 1'b0,\n input USER_CLK,\n input RESET,\n input RATE,\n input RATEDONE,\n input GT_PHYSTATUS,\n input RESETDONE\n\n);\n\n reg ENPMAPHASEALIGN_c;\n reg PMASETPHASE_c;\n reg SYNC_DONE_c;\n reg OUT_DIV_RESET_c;\n reg PCS_RESET_c;\n reg USER_PHYSTATUS_c;\n reg DELAYALIGNRESET_c;\n reg TXALIGNDISABLE_c;\n\n\n reg [7:0] waitcounter2;\n reg [7:0] nextwaitcounter2;\n reg [7:0] waitcounter;\n reg [7:0] nextwaitcounter;\n reg [24:0] state;\n reg [24:0] nextstate;\n reg ratedone_r, ratedone_r2;\n wire ratedone_pulse_i;\n reg gt_phystatus_q;\n\n\n localparam IDLE = 25'b0000000000000000000000001;\n localparam PHASEALIGN = 25'b0000000000000000000000010;\n localparam RATECHANGE_DIVRESET = 25'b0000000000000000000000100;\n localparam RATECHANGE_DIVRESET_POST = 25'b0000000000000000000001000;\n localparam RATECHANGE_ENPMADISABLE = 25'b0000000000000000000010000;\n localparam RATECHANGE_ENPMADISABLE_POST = 25'b0000000000000000000100000;\n localparam RATECHANGE_PMARESET = 25'b0000000000000000001000000;\n localparam RATECHANGE_IDLE = 25'b0000000000000000010000000;\n localparam RATECHANGE_PCSRESET = 25'b0000000000000000100000000;\n localparam RATECHANGE_PCSRESET_POST = 25'b0000000000000001000000000;\n localparam RATECHANGE_ASSERTPHY = 25'b0000000000000010000000000;\n localparam RESET_STATE = 25'b0000000000000100000000000;\n localparam WAIT_PHYSTATUS = 25'b0000000000010000000000000;\n localparam RATECHANGE_PMARESET_POST = 25'b0000000000100000000000000;\n localparam RATECHANGE_DISABLEPHASE = 25'b0000000001000000000000000;\n localparam DELAYALIGNRST = 25'b0000000010000000000000000;\n localparam SETENPMAPHASEALIGN = 25'b0000000100000000000000000;\n localparam TXALIGNDISABLEDEASSERT = 25'b0000001000000000000000000;\n localparam RATECHANGE_TXDLYALIGNDISABLE = 25'b0000010000000000000000000;\n localparam GTXTEST_PULSE_1 = 25'b0000100000000000000000000;\n localparam RATECHANGE_DISABLE_TXALIGNDISABLE = 25'b0001000000000000000000000;\n localparam BEFORE_GTXTEST_PULSE1_1024CLKS = 25'b0010000000000000000000000;\n localparam BETWEEN_GTXTEST_PULSES = 25'b0100000000000000000000000;\n localparam GTXTEST_PULSE_2 = 25'b1000000000000000000000000;\n\n\n\n localparam SYNC_IDX = C_SIMULATION ? 0 : 2;\n localparam PMARESET_IDX = C_SIMULATION ? 0: 7;\n\n always @(posedge USER_CLK) begin\n\n if(RESET) begin\n\n state <= #(TCQ) RESET_STATE;\n waitcounter2 <= #(TCQ) 8'b0;\n waitcounter <= #(TCQ) 8'b0;\n USER_PHYSTATUS <= #(TCQ) GT_PHYSTATUS;\n SYNC_DONE <= #(TCQ) 1'b0;\n ENPMAPHASEALIGN <= #(TCQ) 1'b1;\n PMASETPHASE <= #(TCQ) 1'b0;\n OUT_DIV_RESET <= #(TCQ) 1'b0;\n PCS_RESET <= #(TCQ) 1'b0;\n DELAYALIGNRESET <= #(TCQ) 1'b0;\n TXALIGNDISABLE <= #(TCQ) 1'b1;\n\n end else begin\n\n state <= #(TCQ) nextstate;\n waitcounter2 <= #(TCQ) nextwaitcounter2;\n waitcounter <= #(TCQ) nextwaitcounter;\n USER_PHYSTATUS <= #(TCQ) USER_PHYSTATUS_c;\n SYNC_DONE <= #(TCQ) SYNC_DONE_c;\n ENPMAPHASEALIGN <= #(TCQ) ENPMAPHASEALIGN_c;\n PMASETPHASE <= #(TCQ) PMASETPHASE_c;\n OUT_DIV_RESET <= #(TCQ) OUT_DIV_RESET_c;\n PCS_RESET <= #(TCQ) PCS_RESET_c;\n DELAYALIGNRESET <= #(TCQ) DELAYALIGNRESET_c;\n TXALIGNDISABLE <= #(TCQ) TXALIGNDISABLE_c;\n\n end\n\n end\n\n always @(*) begin\n\n // DEFAULT CONDITIONS\n\n DELAYALIGNRESET_c=0;\n SYNC_DONE_c=0;\n ENPMAPHASEALIGN_c=1;\n PMASETPHASE_c=0;\n OUT_DIV_RESET_c=0;\n PCS_RESET_c=0;\n TXALIGNDISABLE_c=0;\n nextstate=state;\n USER_PHYSTATUS_c=GT_PHYSTATUS;\n nextwaitcounter=waitcounter+1'b1;\n nextwaitcounter2= (waitcounter ==8'hff)? waitcounter2 + 1'b1 : waitcounter2 ;\n\n case(state)\n\n // START IN RESET\n RESET_STATE : begin\n\n TXALIGNDISABLE_c=1;\n ENPMAPHASEALIGN_c=0;\n nextstate=BEFORE_GTXTEST_PULSE1_1024CLKS;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n \n // Have to hold for 1024 clocks before asserting GTXTEST[1]\n BEFORE_GTXTEST_PULSE1_1024CLKS : begin\n\n OUT_DIV_RESET_c=0;\n TXALIGNDISABLE_c=1;\n ENPMAPHASEALIGN_c=0;\n\n if(waitcounter2[1]) begin\n\n nextstate=GTXTEST_PULSE_1;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // Assert GTXTEST[1] for 256 clocks. Figure 3-9 UG366\n GTXTEST_PULSE_1: begin\n\n OUT_DIV_RESET_c=1;\n TXALIGNDISABLE_c=1;\n ENPMAPHASEALIGN_c=0;\n\n if(waitcounter[7]) begin\n\n nextstate=BETWEEN_GTXTEST_PULSES;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // De-assert GTXTEST[1] for 256 clocks. Figure 3-9 UG366\n BETWEEN_GTXTEST_PULSES: begin\n\n OUT_DIV_RESET_c=0;\n TXALIGNDISABLE_c=1;\n ENPMAPHASEALIGN_c=0;\n\n if(waitcounter[7]) begin\n\n nextstate=GTXTEST_PULSE_2;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // Assert GTXTEST[1] for 256 clocks a second time. Figure 3-9 UG366 \n GTXTEST_PULSE_2: begin\n\n OUT_DIV_RESET_c=1;\n TXALIGNDISABLE_c=1;\n ENPMAPHASEALIGN_c=0;\n\n if(waitcounter[7]) begin\n\n nextstate=DELAYALIGNRST;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n\n\n // ASSERT TXDLYALIGNRESET FOR 16 CLOCK CYCLES\n DELAYALIGNRST : begin\n\n DELAYALIGNRESET_c=1;\n ENPMAPHASEALIGN_c=0;\n TXALIGNDISABLE_c=1;\n\n if(waitcounter[4]) begin\n\n nextstate=SETENPMAPHASEALIGN;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // ASSERT ENPMAPHASEALIGN FOR 32 CLOCK CYCLES\n SETENPMAPHASEALIGN : begin\n\n TXALIGNDISABLE_c=1;\n\n if(waitcounter[5]) begin\n\n nextstate=PHASEALIGN;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // ASSERT PMASETPHASE OUT OF RESET for 32K CYCLES\n PHASEALIGN : begin\n\n PMASETPHASE_c=1;\n TXALIGNDISABLE_c=1;\n\n if(waitcounter2[PMARESET_IDX]) begin\n\n nextstate=TXALIGNDISABLEDEASSERT;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // KEEP TXALIGNDISABLE ASSERTED for 64 CYCLES\n TXALIGNDISABLEDEASSERT : begin\n\n TXALIGNDISABLE_c=1;\n\n if(waitcounter[6]) begin\n\n nextwaitcounter=0;\n nextstate=IDLE;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // NOW IN IDLE, ASSERT SYNC DONE, WAIT FOR RATECHANGE\n IDLE : begin\n\n SYNC_DONE_c=1;\n\n if(ratedone_pulse_i) begin\n\n USER_PHYSTATUS_c=0;\n nextstate=WAIT_PHYSTATUS;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // WAIT FOR PHYSTATUS\n WAIT_PHYSTATUS : begin\n\n USER_PHYSTATUS_c=0;\n\n if(gt_phystatus_q) begin\n\n nextstate=RATECHANGE_IDLE;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // WAIT 64 CYCLES BEFORE WE START THE RATE CHANGE\n RATECHANGE_IDLE : begin\n\n USER_PHYSTATUS_c=0;\n\n if(waitcounter[6]) begin\n\n nextstate=RATECHANGE_TXDLYALIGNDISABLE;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // ASSERT TXALIGNDISABLE FOR 32 CYCLES\n RATECHANGE_TXDLYALIGNDISABLE : begin\n\n USER_PHYSTATUS_c=0;\n TXALIGNDISABLE_c=1;\n\n if(waitcounter[5]) begin\n\n nextstate=RATECHANGE_DIVRESET;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // ASSERT DIV RESET FOR 16 CLOCK CYCLES\n RATECHANGE_DIVRESET : begin\n\n OUT_DIV_RESET_c=1;\n USER_PHYSTATUS_c=0;\n TXALIGNDISABLE_c=1;\n\n if(waitcounter[4]) begin\n\n nextstate=RATECHANGE_DIVRESET_POST;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // WAIT FOR 32 CLOCK CYCLES BEFORE NEXT STEP\n RATECHANGE_DIVRESET_POST : begin\n\n USER_PHYSTATUS_c=0;\n TXALIGNDISABLE_c=1;\n\n if(waitcounter[5]) begin\n\n nextstate=RATECHANGE_PMARESET;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // ASSERT PMA RESET FOR 32K CYCLES\n RATECHANGE_PMARESET : begin\n\n PMASETPHASE_c=1;\n USER_PHYSTATUS_c=0;\n TXALIGNDISABLE_c=1;\n\n if(waitcounter2[PMARESET_IDX]) begin\n\n nextstate=RATECHANGE_PMARESET_POST;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n\n // WAIT FOR 32 CYCLES BEFORE DISABLING TXALIGNDISABLE\n RATECHANGE_PMARESET_POST : begin\n\n USER_PHYSTATUS_c=0;\n TXALIGNDISABLE_c=1;\n\n if(waitcounter[5]) begin\n\n nextstate=RATECHANGE_DISABLE_TXALIGNDISABLE;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // DISABLE TXALIGNDISABLE FOR 32 CYCLES\n RATECHANGE_DISABLE_TXALIGNDISABLE : begin\n\n USER_PHYSTATUS_c=0;\n\n if(waitcounter[5]) begin\n\n nextstate=RATECHANGE_PCSRESET;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n end\n\n // NOW ASSERT PCS RESET FOR 32 CYCLES\n RATECHANGE_PCSRESET : begin\n\n PCS_RESET_c=1;\n\n USER_PHYSTATUS_c=0;\n\n if(waitcounter[5]) begin\n\n nextstate=RATECHANGE_PCSRESET_POST;\n nextwaitcounter=0;\n nextwaitcounter2=0;\n\n end\n\n end\n\n // WAIT FOR RESETDONE BEFORE ASSERTING PHY_STATUS_OUT\n RATECHANGE_PCSRESET_POST : begin\n\n USER_PHYSTATUS_c=0;\n\n if(RESETDONE) begin\n\n nextstate=RATECHANGE_ASSERTPHY;\n\n end\n\n end\n\n // ASSERT PHYSTATUSOUT MEANING RATECHANGE IS DONE AND GO BACK TO IDLE\n RATECHANGE_ASSERTPHY : begin\n\n USER_PHYSTATUS_c=1;\n nextstate=IDLE;\n\n end\n\n endcase\n\n end\n\n // Generate Ratechange Pulse\n\n always @(posedge USER_CLK) begin\n\n if (RESET) begin\n\n ratedone_r <= #(TCQ) 1'b0;\n ratedone_r2 <= #(TCQ) 1'b0;\n gt_phystatus_q <= #(TCQ) 1'b0;\n\n\n end else begin\n\n ratedone_r <= #(TCQ) RATE;\n ratedone_r2 <= #(TCQ) ratedone_r;\n gt_phystatus_q <= #(TCQ) GT_PHYSTATUS;\n\n end\n\n end\n\n assign ratedone_pulse_i = (ratedone_r != ratedone_r2);\n\nendmodule\n\n\n\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/gtx_wrapper_v6.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : gtx_wrapper_v6.v\n// Version : 2.4\n\n//-- Description: GTX module for Virtex6 PCIe Block\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns/1ns\n\nmodule gtx_wrapper_v6 (\n\n // TX\n TX,\n TX_,\n TxData,\n TxDataK,\n TxElecIdle,\n TxCompliance,\n\n // RX\n RX,\n RX_,\n RxData,\n RxDataK,\n RxPolarity,\n RxValid,\n RxElecIdle,\n RxStatus,\n\n // other\n GTRefClkout,\n plm_in_l0,\n plm_in_rl,\n plm_in_dt,\n plm_in_rs,\n RxPLLLkDet,\n TxDetectRx,\n PhyStatus,\n TXPdownAsynch,\n PowerDown,\n Rate,\n Reset_n,\n GTReset_n,\n PCLK,\n REFCLK,\n TxDeemph,\n TxMargin,\n TxSwing,\n ChanIsAligned,\n local_pcs_reset,\n RxResetDone,\n SyncDone,\n DRPCLK,\n TxOutClk\n\n );\n\n parameter NO_OF_LANES = 1;\n parameter REF_CLK_FREQ = 0;\n parameter PL_FAST_TRAIN = \"FALSE\";\n\n localparam GTX_PLL_DIVSEL_FB = (REF_CLK_FREQ == 0) ? 5 :\n (REF_CLK_FREQ == 1) ? 4 :\n (REF_CLK_FREQ == 2) ? 2 : 0;\n localparam SIMULATION = (PL_FAST_TRAIN == \"TRUE\") ? 1 : 0;\n\n localparam RXPLL_CP_CFG = (REF_CLK_FREQ == 0) ? 8'h05 :\n (REF_CLK_FREQ == 1) ? 8'h05 :\n (REF_CLK_FREQ == 2) ? 8'h05 : 8'h05;\n\n localparam TXPLL_CP_CFG = (REF_CLK_FREQ == 0) ? 8'h05 :\n (REF_CLK_FREQ == 1) ? 8'h05 :\n (REF_CLK_FREQ == 2) ? 8'h05 : 8'h05;\n\n localparam RX_CLK25_DIVIDER = (REF_CLK_FREQ == 0) ? 4 :\n (REF_CLK_FREQ == 1) ? 5 :\n (REF_CLK_FREQ == 2) ? 10 : 10 ;\n\n localparam TX_CLK25_DIVIDER = (REF_CLK_FREQ == 0) ? 4 :\n (REF_CLK_FREQ == 1) ? 5 :\n (REF_CLK_FREQ == 2) ? 10 : 10 ;\n\n // TX\n output [NO_OF_LANES-1:0] TX;\n output [NO_OF_LANES-1:0] TX_;\n input [(NO_OF_LANES*16)-1:0] TxData;\n input [(NO_OF_LANES*2)-1:0] TxDataK;\n input [NO_OF_LANES-1:0] TxElecIdle;\n input [NO_OF_LANES-1:0] TxCompliance;\n\n // RX\n input [NO_OF_LANES-1:0] RX;\n input [NO_OF_LANES-1:0] RX_;\n output [(NO_OF_LANES*16)-1:0] RxData;\n output [(NO_OF_LANES*2)-1:0] RxDataK;\n input [NO_OF_LANES-1:0] RxPolarity;\n output [NO_OF_LANES-1:0] RxValid;\n output [NO_OF_LANES-1:0] RxElecIdle;\n output [(NO_OF_LANES*3)-1:0] RxStatus;\n // other\n output [NO_OF_LANES-1:0] GTRefClkout;\n input plm_in_l0;\n input plm_in_rl;\n input plm_in_dt;\n input plm_in_rs;\n output [NO_OF_LANES-1:0] RxPLLLkDet;\n input TxDetectRx;\n output [NO_OF_LANES-1:0] PhyStatus;\n input PCLK;\n output [NO_OF_LANES-1:0] ChanIsAligned;\n input TXPdownAsynch;\n\n input [(NO_OF_LANES*2)-1:0] PowerDown;\n input Rate;\n input Reset_n;\n input GTReset_n;\n input REFCLK;\n input TxDeemph;\n input TxMargin;\n input TxSwing;\n input local_pcs_reset;\n output RxResetDone;\n output SyncDone;\n input DRPCLK;\n output TxOutClk;\n genvar i;\n\n // dummy signals to avoid port mismatch with DUAL_GTX\n wire [15:0] RxData_dummy;\n wire [1:0] RxDataK_dummy;\n wire [15:0] TxData_dummy;\n wire [1:0] TxDataK_dummy;\n\n // inputs\n wire [(NO_OF_LANES*16)-1:0] GTX_TxData = TxData;\n wire [(NO_OF_LANES*2)-1:0] GTX_TxDataK = TxDataK;\n wire [(NO_OF_LANES)-1:0] GTX_TxElecIdle = TxElecIdle;\n wire [(NO_OF_LANES-1):0] GTX_TxCompliance = TxCompliance;\n wire [(NO_OF_LANES)-1:0] GTX_RXP = RX[(NO_OF_LANES)-1:0];\n wire [(NO_OF_LANES)-1:0] GTX_RXN = RX_[(NO_OF_LANES)-1:0];\n\n // outputs\n wire [(NO_OF_LANES)-1:0] GTX_TXP;\n wire [(NO_OF_LANES)-1:0] GTX_TXN;\n wire [(NO_OF_LANES*16)-1:0] GTX_RxData;\n wire [(NO_OF_LANES*2)-1:0] GTX_RxDataK;\n wire [(NO_OF_LANES)-1:0] GTX_RxPolarity = RxPolarity ;\n wire [(NO_OF_LANES)-1:0] GTX_RxValid;\n wire [(NO_OF_LANES)-1:0] GTX_RxElecIdle;\n wire [(NO_OF_LANES-1):0] GTX_RxResetDone;\n wire [(NO_OF_LANES*3)-1:0] GTX_RxChbondLevel;\n wire [(NO_OF_LANES*3)-1:0] GTX_RxStatus;\n\n\n wire [3:0] RXCHBOND [NO_OF_LANES+1:0];\n wire [3:0] TXBYPASS8B10B = 4'b0000;\n wire RXDEC8B10BUSE = 1'b1;\n wire [NO_OF_LANES-1:0] GTX_PhyStatus;\n wire RESETDONE [NO_OF_LANES-1:0];\n wire REFCLK;\n wire GTXRESET = 1'b0;\n\n wire [NO_OF_LANES-1:0] SYNC_DONE;\n wire [NO_OF_LANES-1:0] OUT_DIV_RESET;\n wire [NO_OF_LANES-1:0] PCS_RESET;\n wire [NO_OF_LANES-1:0] TXENPMAPHASEALIGN;\n wire [NO_OF_LANES-1:0] TXPMASETPHASE;\n wire [NO_OF_LANES-1:0] TXRESETDONE;\n wire [NO_OF_LANES-1:0] TXRATEDONE;\n wire [NO_OF_LANES-1:0] PHYSTATUS;\n wire [NO_OF_LANES-1:0] RXVALID;\n wire [NO_OF_LANES-1:0] RATE_CLK_SEL;\n wire [NO_OF_LANES-1:0] TXOCLK;\n wire [NO_OF_LANES-1:0] TXDLYALIGNDISABLE;\n wire [NO_OF_LANES-1:0] TXDLYALIGNRESET;\n\n\n reg [(NO_OF_LANES-1):0] GTX_RxResetDone_q;\n reg [(NO_OF_LANES-1):0] TXRESETDONE_q;\n\n wire [NO_OF_LANES-1:0] RxValid;\n\n\n wire [(NO_OF_LANES*8-1):0] daddr;\n wire [NO_OF_LANES-1:0] den;\n wire [(NO_OF_LANES*16-1):0] din;\n wire [NO_OF_LANES-1:0] dwe;\n\n wire [(NO_OF_LANES*4-1):0] drpstate;\n wire [NO_OF_LANES-1:0] drdy;\n wire [(NO_OF_LANES*16-1):0] dout;\n\n wire write_drp_cb_fts;\n wire write_drp_cb_ts1;\n\n assign RxResetDone = &(GTX_RxResetDone_q[(NO_OF_LANES)-1:0]);\n assign TX[(NO_OF_LANES)-1:0] = GTX_TXP[(NO_OF_LANES)-1:0];\n assign TX_[(NO_OF_LANES)-1:0] = GTX_TXN[(NO_OF_LANES)-1:0];\n assign RXCHBOND[0] = 4'b0000;\n assign TxData_dummy = 16'b0;\n assign TxDataK_dummy = 2'b0;\n assign SyncDone = &(SYNC_DONE[(NO_OF_LANES)-1:0]);\n assign TxOutClk = TXOCLK[0];\n\n assign write_drp_cb_fts = plm_in_l0;\n assign write_drp_cb_ts1 = plm_in_rl | plm_in_dt;\n\n // pipeline to improve timing\n always @ (posedge PCLK) begin\n\n GTX_RxResetDone_q[(NO_OF_LANES)-1:0] <= GTX_RxResetDone[(NO_OF_LANES)-1:0];\n TXRESETDONE_q[(NO_OF_LANES)-1:0] <= TXRESETDONE[(NO_OF_LANES)-1:0];\n\n end\n\n generate\n begin: no_of_lanes\n\n for (i=0; i < NO_OF_LANES; i=i+1) begin: GTXD\n\n assign GTX_RxChbondLevel[(3*i)+2:(3*i)] = (NO_OF_LANES-(i+1));\n\n GTX_DRP_CHANALIGN_FIX_3752_V6 # (\n .C_SIMULATION(SIMULATION)\n ) GTX_DRP_CHANALIGN_FIX_3752 (\n\n .dwe(dwe[i]),\n .din(din[(16*i)+15:(16*i)]),\n .den(den[i]),\n .daddr(daddr[(8*i)+7:(8*i)]),\n .drpstate(drpstate[(4*i)+3:(4*i)]),\n .write_ts1(write_drp_cb_ts1),\n .write_fts(write_drp_cb_fts),\n .dout(dout[(16*i)+15:(16*i)]),\n .drdy(drdy[i]),\n .Reset_n(Reset_n),\n .drp_clk(DRPCLK)\n\n );\n\n GTX_RX_VALID_FILTER_V6 # (\n .CLK_COR_MIN_LAT(28)\n )\n GTX_RX_VALID_FILTER (\n\n .USER_RXCHARISK ( RxDataK[(2*i)+1:2*i] ), //O\n .USER_RXDATA ( RxData[(16*i)+15:(16*i)+0] ), //O\n .USER_RXVALID ( RxValid[i] ), //O\n .USER_RXELECIDLE ( RxElecIdle[i] ), //O\n .USER_RX_STATUS ( RxStatus[(3*i)+2:(3*i)] ), //O\n .USER_RX_PHY_STATUS ( PhyStatus[i] ), //O\n\n\n .GT_RXCHARISK ( GTX_RxDataK[(2*i)+1:2*i] ), //I\n .GT_RXDATA ( GTX_RxData[(16*i)+15:(16*i)+0] ), //I\n .GT_RXVALID ( GTX_RxValid[i] ), //I\n .GT_RXELECIDLE ( GTX_RxElecIdle[i] ), //I\n .GT_RX_STATUS ( GTX_RxStatus[(3*i)+2:(3*i)] ), //I\n .GT_RX_PHY_STATUS ( PHYSTATUS[i] ),\n\n .PLM_IN_L0 ( plm_in_l0 ), //I\n .PLM_IN_RS ( plm_in_rs ), //I\n .USER_CLK ( PCLK ), //I\n .RESET ( !Reset_n ) //I\n\n );\n\n GTX_TX_SYNC_RATE_V6 # (\n .C_SIMULATION(SIMULATION)\n )\n GTX_TX_SYNC (\n\n .ENPMAPHASEALIGN ( TXENPMAPHASEALIGN[i] ), //O\n .PMASETPHASE ( TXPMASETPHASE[i] ), //O\n .SYNC_DONE ( SYNC_DONE[i] ), //O\n .OUT_DIV_RESET ( OUT_DIV_RESET[i] ), //O\n .PCS_RESET ( PCS_RESET[i] ), //O\n .USER_PHYSTATUS ( PHYSTATUS[i] ), //O\n .TXALIGNDISABLE ( TXDLYALIGNDISABLE[i] ), //O\n .DELAYALIGNRESET ( TXDLYALIGNRESET[i] ), //O\n\n .USER_CLK ( PCLK), //I\n .RESET ( !Reset_n ), //I\n .RATE ( Rate ), //I\n .RATEDONE ( TXRATEDONE[i] ), //I\n .GT_PHYSTATUS ( GTX_PhyStatus[i] ), //I\n .RESETDONE ( TXRESETDONE_q[i] & GTX_RxResetDone_q[i] ) //I\n\n );\n\n GTXE1 # (\n\n .TX_DRIVE_MODE(\"PIPE\"),\n .TX_DEEMPH_1(5'b10010),\n .TX_MARGIN_FULL_0(7'b100_1101),\n\n .TX_CLK_SOURCE(\"RXPLL\"),\n .POWER_SAVE(10'b0000110100),\n .CM_TRIM ( 2'b01 ),\n .PMA_CDR_SCAN ( 27'h640404C ),\n .PMA_CFG( 76'h0040000040000000003 ),\n .RCV_TERM_GND (\"TRUE\"),\n .RCV_TERM_VTTRX (\"FALSE\"),\n .RX_DLYALIGN_EDGESET(5'b00010),\n .RX_DLYALIGN_LPFINC(4'b0110),\n .RX_DLYALIGN_OVRDSETTING(8'b10000000),\n .TERMINATION_CTRL(5'b00000),\n .TERMINATION_OVRD(\"FALSE\"),\n .TX_DLYALIGN_LPFINC(4'b0110),\n .TX_DLYALIGN_OVRDSETTING(8'b10000000),\n .TXPLL_CP_CFG( TXPLL_CP_CFG ),\n .OOBDETECT_THRESHOLD( 3'b011 ),\n .RXPLL_CP_CFG ( RXPLL_CP_CFG ),\n //.TX_DETECT_RX_CFG( 14'h1832 ),\n .TX_TDCC_CFG ( 2'b11 ),\n .BIAS_CFG ( 17'h00000 ),\n .AC_CAP_DIS ( \"FALSE\" ),\n .DFE_CFG ( 8'b00011011 ),\n .SIM_TX_ELEC_IDLE_LEVEL(\"1\"),\n .SIM_RECEIVER_DETECT_PASS(\"TRUE\"),\n .RX_EN_REALIGN_RESET_BUF(\"FALSE\"),\n .TX_IDLE_ASSERT_DELAY(3'b100), // TX-idle-set-to-idle (13 UI)\n .TX_IDLE_DEASSERT_DELAY(3'b010), // TX-idle-to-diff (7 UI)\n .CHAN_BOND_SEQ_2_CFG(5'b11111), // 5'b11111 for PCIE mode, 5'b00000 for other modes\n .CHAN_BOND_KEEP_ALIGN(\"TRUE\"),\n .RX_IDLE_HI_CNT(4'b1000),\n .RX_IDLE_LO_CNT(4'b0000),\n .RX_EN_IDLE_RESET_BUF(\"TRUE\"),\n .TX_DATA_WIDTH(20),\n .RX_DATA_WIDTH(20),\n .ALIGN_COMMA_WORD(1),\n .CHAN_BOND_1_MAX_SKEW(7),\n .CHAN_BOND_2_MAX_SKEW(1),\n .CHAN_BOND_SEQ_1_1(10'b0001000101), // D5.2 (end TS2)\n .CHAN_BOND_SEQ_1_2(10'b0001000101), // D5.2 (end TS2)\n .CHAN_BOND_SEQ_1_3(10'b0001000101), // D5.2 (end TS2)\n .CHAN_BOND_SEQ_1_4(10'b0110111100), // K28.5 (COM)\n .CHAN_BOND_SEQ_1_ENABLE(4'b1111), // order is 4321\n .CHAN_BOND_SEQ_2_1(10'b0100111100), // K28.1 (FTS)\n .CHAN_BOND_SEQ_2_2(10'b0100111100), // K28.1 (FTS)\n .CHAN_BOND_SEQ_2_3(10'b0110111100), // K28.5 (COM)\n .CHAN_BOND_SEQ_2_4(10'b0100111100), // K28.1 (FTS)\n .CHAN_BOND_SEQ_2_ENABLE(4'b1111), // order is 4321\n .CHAN_BOND_SEQ_2_USE(\"TRUE\"),\n .CHAN_BOND_SEQ_LEN(4), // 1..4\n .RX_CLK25_DIVIDER(RX_CLK25_DIVIDER),\n .TX_CLK25_DIVIDER(TX_CLK25_DIVIDER),\n .CLK_COR_ADJ_LEN(1), // 1..4\n .CLK_COR_DET_LEN(1), // 1..4\n .CLK_COR_INSERT_IDLE_FLAG(\"FALSE\"),\n .CLK_COR_KEEP_IDLE(\"FALSE\"),\n .CLK_COR_MAX_LAT(30),\n .CLK_COR_MIN_LAT(28),\n .CLK_COR_PRECEDENCE(\"TRUE\"),\n .CLK_CORRECT_USE(\"TRUE\"),\n .CLK_COR_REPEAT_WAIT(0),\n .CLK_COR_SEQ_1_1(10'b0100011100), // K28.0 (SKP)\n .CLK_COR_SEQ_1_2(10'b0000000000),\n .CLK_COR_SEQ_1_3(10'b0000000000),\n .CLK_COR_SEQ_1_4(10'b0000000000),\n .CLK_COR_SEQ_1_ENABLE(4'b1111),\n .CLK_COR_SEQ_2_1(10'b0000000000),\n .CLK_COR_SEQ_2_2(10'b0000000000),\n .CLK_COR_SEQ_2_3(10'b0000000000),\n .CLK_COR_SEQ_2_4(10'b0000000000),\n .CLK_COR_SEQ_2_ENABLE(4'b1111),\n .CLK_COR_SEQ_2_USE(\"FALSE\"),\n .COMMA_10B_ENABLE(10'b1111111111),\n .COMMA_DOUBLE(\"FALSE\"),\n .DEC_MCOMMA_DETECT(\"TRUE\"),\n .DEC_PCOMMA_DETECT(\"TRUE\"),\n .DEC_VALID_COMMA_ONLY(\"TRUE\"),\n .MCOMMA_10B_VALUE(10'b1010000011),\n .MCOMMA_DETECT(\"TRUE\"),\n .PCI_EXPRESS_MODE(\"TRUE\"),\n .PCOMMA_10B_VALUE(10'b0101111100),\n .PCOMMA_DETECT(\"TRUE\"),\n .RXPLL_DIVSEL_FB(GTX_PLL_DIVSEL_FB), // 1..5, 8, 10\n .TXPLL_DIVSEL_FB(GTX_PLL_DIVSEL_FB), // 1..5, 8, 10\n .RXPLL_DIVSEL_REF(1), // 1..6, 8, 10, 12, 16, 20\n .TXPLL_DIVSEL_REF(1), // 1..6, 8, 10, 12, 16, 20\n .RXPLL_DIVSEL_OUT(2), // 1, 2, 4\n .TXPLL_DIVSEL_OUT(2), // 1, 2, 4\n .RXPLL_DIVSEL45_FB(5),\n .TXPLL_DIVSEL45_FB(5),\n .RX_BUFFER_USE(\"TRUE\"),\n .RX_DECODE_SEQ_MATCH(\"TRUE\"),\n .RX_LOS_INVALID_INCR(8), // power of 2: 1..128\n .RX_LOSS_OF_SYNC_FSM(\"FALSE\"),\n .RX_LOS_THRESHOLD(128), // power of 2: 4..512\n .RX_SLIDE_MODE(\"OFF\"), // 00=OFF 01=AUTO 10=PCS 11=PMA\n .RX_XCLK_SEL (\"RXREC\"),\n .TX_BUFFER_USE(\"FALSE\"), // Must be set to FALSE for use by PCIE\n .TX_XCLK_SEL (\"TXUSR\"), // Must be set to TXUSR for use by PCIE\n .TXPLL_LKDET_CFG (3'b101),\n .RX_EYE_SCANMODE (2'b00),\n .RX_EYE_OFFSET (8'h4C),\n .PMA_RX_CFG ( 25'h05ce049 ),\n .TRANS_TIME_NON_P2(8'h2), // Reduced simulation time\n .TRANS_TIME_FROM_P2(12'h03c), // Reduced simulation time\n .TRANS_TIME_TO_P2(10'h064), // Reduced simulation time\n .TRANS_TIME_RATE(8'hD7), // Reduced simulation time\n .SHOW_REALIGN_COMMA(\"FALSE\"),\n .TX_PMADATA_OPT(1'b1), // Lockup latch between PCS and PMA\n .PMA_TX_CFG( 20'h80082 ), // Aligns posedge of USRCLK\n .TXOUTCLK_CTRL(\"TXPLLREFCLK_DIV1\")\n\n )\n GTX (\n\n .COMFINISH (),\n .COMINITDET (),\n .COMSASDET (),\n .COMWAKEDET (),\n .DADDR (daddr[(8*i)+7:(8*i)]),\n .DCLK (DRPCLK),\n .DEN (den[i]),\n .DFECLKDLYADJ ( 6'h0 ),\n .DFECLKDLYADJMON (),\n .DFEDLYOVRD ( 1'b0 ),\n .DFEEYEDACMON (),\n .DFESENSCAL (),\n .DFETAP1 (0),\n .DFETAP1MONITOR (),\n .DFETAP2 (5'h0),\n .DFETAP2MONITOR (),\n .DFETAP3 (4'h0),\n .DFETAP3MONITOR (),\n .DFETAP4 (4'h0),\n .DFETAP4MONITOR (),\n .DFETAPOVRD ( 1'b1 ),\n .DI (din[(16*i)+15:(16*i)]),\n .DRDY (drdy[i]),\n .DRPDO (dout[(16*i)+15:(16*i)]),\n .DWE (dwe[i]),\n .GATERXELECIDLE ( 1'b0 ),\n .GREFCLKRX (0),\n .GREFCLKTX (0),\n .GTXRXRESET ( ~GTReset_n ),\n .GTXTEST ( {11'b10000000000,OUT_DIV_RESET[i],1'b0} ),\n .GTXTXRESET ( ~GTReset_n ),\n .LOOPBACK ( 3'b000 ),\n .MGTREFCLKFAB (),\n .MGTREFCLKRX ( {1'b0,REFCLK} ),\n .MGTREFCLKTX ( {1'b0,REFCLK} ),\n .NORTHREFCLKRX (0),\n .NORTHREFCLKTX (0),\n .PHYSTATUS ( GTX_PhyStatus[i] ),\n .PLLRXRESET ( 1'b0 ),\n .PLLTXRESET ( 1'b0 ),\n .PRBSCNTRESET ( 1'b0 ),\n .RXBUFRESET ( 1'b0 ),\n .RXBUFSTATUS (),\n .RXBYTEISALIGNED (),\n .RXBYTEREALIGN (),\n .RXCDRRESET ( 1'b0 ),\n .RXCHANBONDSEQ (),\n .RXCHANISALIGNED ( ChanIsAligned[i] ),\n .RXCHANREALIGN (),\n .RXCHARISCOMMA (),\n .RXCHARISK ( {RxDataK_dummy[1:0], GTX_RxDataK[(2*i)+1:2*i]} ),\n .RXCHBONDI ( RXCHBOND[i] ),\n .RXCHBONDLEVEL ( GTX_RxChbondLevel[(3*i)+2:(3*i)] ),\n .RXCHBONDMASTER ( (i == 0) ),\n .RXCHBONDO ( RXCHBOND[i+1] ),\n .RXCHBONDSLAVE ( (i > 0) ),\n .RXCLKCORCNT (),\n .RXCOMMADET (),\n .RXCOMMADETUSE ( 1'b1 ),\n .RXDATA ( {RxData_dummy[15:0],GTX_RxData[(16*i)+15:(16*i)+0]} ),\n .RXDATAVALID (),\n .RXDEC8B10BUSE ( RXDEC8B10BUSE ),\n .RXDISPERR (),\n .RXDLYALIGNDISABLE ( 1'b1),\n .RXELECIDLE ( GTX_RxElecIdle[i] ),\n .RXENCHANSYNC ( 1'b1 ),\n .RXENMCOMMAALIGN ( 1'b1 ),\n .RXENPCOMMAALIGN ( 1'b1 ),\n .RXENPMAPHASEALIGN ( 1'b0 ),\n .RXENPRBSTST ( 3'b0 ),\n .RXENSAMPLEALIGN ( 1'b0 ),\n .RXDLYALIGNMONENB ( 1'b1 ),\n .RXEQMIX ( 10'b0110000011 ),\n .RXGEARBOXSLIP ( 1'b0 ),\n .RXHEADER (),\n .RXHEADERVALID (),\n .RXLOSSOFSYNC (),\n .RXN ( GTX_RXN[i] ),\n .RXNOTINTABLE (),\n .RXOVERSAMPLEERR (),\n .RXP ( GTX_RXP[i] ),\n .RXPLLLKDET ( RxPLLLkDet[i] ),\n .RXPLLLKDETEN ( 1'b1 ),\n .RXPLLPOWERDOWN ( 1'b0 ),\n .RXPLLREFSELDY ( 3'b000 ),\n .RXPMASETPHASE ( 1'b0 ),\n .RXPOLARITY ( GTX_RxPolarity[i] ),\n .RXPOWERDOWN ( PowerDown[(2*i)+1:(2*i)] ),\n .RXPRBSERR (),\n .RXRATE ( {1'b1, Rate} ),\n .RXRATEDONE ( ),\n .RXRECCLK ( RXRECCLK ),\n .RXRECCLKPCS ( ),\n .RXRESET ( ~GTReset_n | local_pcs_reset | PCS_RESET[i] ),\n .RXRESETDONE ( GTX_RxResetDone[i] ),\n .RXRUNDISP (),\n .RXSLIDE ( 1'b0 ),\n .RXSTARTOFSEQ (),\n .RXSTATUS ( GTX_RxStatus[(3*i)+2:(3*i)] ),\n .RXUSRCLK ( PCLK ),\n .RXUSRCLK2 ( PCLK ),\n .RXVALID (GTX_RxValid[i]),\n .SOUTHREFCLKRX (0),\n .SOUTHREFCLKTX (0),\n .TSTCLK0 ( 1'b0 ),\n .TSTCLK1 ( 1'b0 ),\n .TSTIN ( {20{1'b1}} ),\n .TSTOUT (),\n .TXBUFDIFFCTRL ( 3'b111 ),\n .TXBUFSTATUS (),\n .TXBYPASS8B10B ( TXBYPASS8B10B[3:0] ),\n .TXCHARDISPMODE ( {3'b000, GTX_TxCompliance[i]} ),\n .TXCHARDISPVAL ( 4'b0000 ),\n .TXCHARISK ( {TxDataK_dummy[1:0], GTX_TxDataK[(2*i)+1:2*i]} ),\n .TXCOMINIT ( 1'b0 ),\n .TXCOMSAS ( 1'b0 ),\n .TXCOMWAKE ( 1'b0 ),\n .TXDATA ( {TxData_dummy[15:0], GTX_TxData[(16*i)+15:(16*i)+0]} ),\n .TXDEEMPH ( TxDeemph ),\n .TXDETECTRX ( TxDetectRx ),\n .TXDIFFCTRL ( 4'b1111 ),\n .TXDLYALIGNDISABLE ( TXDLYALIGNDISABLE[i] ),\n .TXDLYALIGNRESET ( TXDLYALIGNRESET[i] ),\n .TXELECIDLE ( GTX_TxElecIdle[i] ),\n .TXENC8B10BUSE ( 1'b1 ),\n .TXENPMAPHASEALIGN ( TXENPMAPHASEALIGN[i] ),\n .TXENPRBSTST (),\n .TXGEARBOXREADY (),\n .TXHEADER (0),\n .TXINHIBIT ( 1'b0 ),\n .TXKERR (),\n .TXMARGIN ( {TxMargin, 2'b00} ),\n .TXN ( GTX_TXN[i] ),\n .TXOUTCLK ( TXOCLK[i] ),\n .TXOUTCLKPCS (),\n .TXP ( GTX_TXP[i] ),\n .TXPDOWNASYNCH ( TXPdownAsynch ),\n .TXPLLLKDET ( ),\n .TXPLLLKDETEN ( 1'b0 ),\n .TXPLLPOWERDOWN ( 1'b0 ),\n .TXPLLREFSELDY ( 3'b000 ),\n .TXPMASETPHASE ( TXPMASETPHASE[i] ),\n .TXPOLARITY ( 1'b0 ),\n .TXPOSTEMPHASIS (0),\n .TXPOWERDOWN ( PowerDown[(2*i)+1:(2*i)] ),\n .TXPRBSFORCEERR (0),\n .TXPREEMPHASIS (0),\n .TXRATE ( {1'b1, Rate} ),\n .TXRESET ( ~GTReset_n | local_pcs_reset | PCS_RESET[i] ),\n .TXRESETDONE ( TXRESETDONE[i] ),\n .TXRUNDISP (),\n .TXSEQUENCE (0),\n .TXSTARTSEQ (0),\n .TXSWING ( TxSwing ),\n .TXUSRCLK ( PCLK ),\n .TXUSRCLK2 ( PCLK ),\n .USRCODEERR (0),\n .IGNORESIGDET (0),\n .PERFCLKRX (0),\n .PERFCLKTX (0),\n .RXDLYALIGNMONITOR (),\n .RXDLYALIGNOVERRIDE ( 1'b0 ),\n .RXDLYALIGNRESET (0),\n .RXDLYALIGNSWPPRECURB ( 1'b1 ),\n .RXDLYALIGNUPDSW ( 1'b0 ),\n .TXDLYALIGNMONITOR (),\n .TXDLYALIGNOVERRIDE ( 1'b0 ),\n .TXDLYALIGNUPDSW ( 1'b0 ),\n .TXDLYALIGNMONENB ( 1'b1 ),\n .TXRATEDONE ( TXRATEDONE[i] )\n\n\n );\n end\n\n end\n endgenerate\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/interrupt.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tinterrupt.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tManages the interrupt vector and sends interrupts.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_INTR_IDLE\t\t2'd0\n`define S_INTR_INTR\t\t2'd1\n`define S_INTR_CLR_0\t2'd2\n`define S_INTR_CLR_1\t2'd3\n\nmodule interrupt #(\n\tparameter C_NUM_CHNL = 4'd12\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [C_NUM_CHNL-1:0] RX_SG_BUF_RECVD,\t// The scatter gather data for a rx_port transaction has been read\n\tinput [C_NUM_CHNL-1:0] RX_TXN_DONE,\t\t// The rx_port transaction is done\n\tinput [C_NUM_CHNL-1:0] TX_TXN,\t\t\t// New tx_port transaction\n\tinput [C_NUM_CHNL-1:0] TX_SG_BUF_RECVD,\t// The scatter gather data for a tx_port transaction has been read\n\tinput [C_NUM_CHNL-1:0] TX_TXN_DONE,\t\t// The tx_port transaction is done\n\tinput VECT_0_RST,\t\t\t\t\t\t// Interrupt vector 0 reset\n\tinput VECT_1_RST,\t\t\t\t\t\t// Interrupt vector 1 reset\n\tinput [31:0] VECT_RST,\t\t\t\t\t// Interrupt vector reset value\n\toutput [31:0] VECT_0,\t\t\t\t\t// Interrupt vector 0\n\toutput [31:0] VECT_1,\t\t\t\t\t// Interrupt vector 1\n\tinput INTR_LEGACY_CLR,\t\t\t\t\t// Pulsed high to ack the legacy interrupt and clear it\n\tinput CONFIG_INTERRUPT_MSIENABLE,\t\t// 1 if MSI interrupts are enable, 0 if only legacy are supported\n\tinput INTR_MSI_RDY,\t\t \t\t\t\t// High when interrupt is able to be sent\n\toutput INTR_MSI_REQUEST\t\t\t\t\t// High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent\n);\n\nreg\t\t[1:0]\t\trState=0;\nreg\t\t[31:0]\t\trVect0=0;\nreg\t\t[31:0]\t\trVect1=0;\nwire\t[31:0]\t\twVect0;\nwire\t[31:0]\t\twVect1;\nwire\t\t\t\twIntr = (rState == `S_INTR_INTR);\nwire\t\t\t\twIntrDone;\n\nassign VECT_0 = rVect0;\nassign VECT_1 = rVect1;\n\n// Align the input signals to the interrupt vector. \n// VECT_0/VECT_1 are organized from right to left (LSB to MSB) as:\n// [ 0] TX_TXN\t\t\tfor channel 0 in VECT_0, channel 6 in VECT_1\n// [ 1] TX_SG_BUF_RECVD\tfor channel 0 in VECT_0, channel 6 in VECT_1\n// [ 2] TX_TXN_DONE\t\tfor channel 0 in VECT_0, channel 6 in VECT_1\n// [ 3] RX_SG_BUF_RECVD\tfor channel 0 in VECT_0, channel 6 in VECT_1\n// [ 4] RX_TXN_DONE\t\tfor channel 0 in VECT_0, channel 6 in VECT_1\n// ...\n// [25] TX_TXN\t\t\tfor channel 5 in VECT_0, channel 11 in VECT_1\n// [26] TX_SG_BUF_RECVD\tfor channel 5 in VECT_0, channel 11 in VECT_1\n// [27] TX_TXN_DONE\t\tfor channel 5 in VECT_0, channel 11 in VECT_1\n// [28] RX_SG_BUF_RECVD\tfor channel 5 in VECT_0, channel 11 in VECT_1\n// [29] RX_TXN_DONE\t\tfor channel 5 in VECT_0, channel 11 in VECT_1\n// Positions 30 - 31 in both VECT_0 and VECT_1 are zero.\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < C_NUM_CHNL; i = i + 1) begin: vectMap\n\t\tif (i < 6) begin : vectMap0\n\t\t\tassign wVect0[(5*i)+0] = TX_TXN[i];\n\t\t\tassign wVect0[(5*i)+1] = TX_SG_BUF_RECVD[i];\n\t\t\tassign wVect0[(5*i)+2] = TX_TXN_DONE[i];\n\t\t\tassign wVect0[(5*i)+3] = RX_SG_BUF_RECVD[i];\n\t\t\tassign wVect0[(5*i)+4] = RX_TXN_DONE[i];\n\t\tend\n\t\telse begin : vectMap1\n\t\t\tassign wVect1[(5*(i-6))+0] = TX_TXN[i];\n\t\t\tassign wVect1[(5*(i-6))+1] = TX_SG_BUF_RECVD[i];\n\t\t\tassign wVect1[(5*(i-6))+2] = TX_TXN_DONE[i];\n\t\t\tassign wVect1[(5*(i-6))+3] = RX_SG_BUF_RECVD[i];\n\t\t\tassign wVect1[(5*(i-6))+4] = RX_TXN_DONE[i];\n\t\tend\t\n\tend\n\tfor (i = C_NUM_CHNL; i < 12; i = i + 1) begin: vectZero\n\t\tif (i < 6) begin : vectZero0\n\t\t\tassign wVect0[(5*i)+0] = 1'b0;\n\t\t\tassign wVect0[(5*i)+1] = 1'b0;\n\t\t\tassign wVect0[(5*i)+2] = 1'b0;\n\t\t\tassign wVect0[(5*i)+3] = 1'b0;\n\t\t\tassign wVect0[(5*i)+4] = 1'b0;\n\t\tend\n\t\telse begin : vectZero1\n\t\t\tassign wVect1[(5*(i-6))+0] = 1'b0;\n\t\t\tassign wVect1[(5*(i-6))+1] = 1'b0;\n\t\t\tassign wVect1[(5*(i-6))+2] = 1'b0;\n\t\t\tassign wVect1[(5*(i-6))+3] = 1'b0;\n\t\t\tassign wVect1[(5*(i-6))+4] = 1'b0;\n\t\tend\t\n\tend\n\tassign wVect0[30] = 1'b0;\n\tassign wVect0[31] = 1'b0;\n\tassign wVect1[30] = 1'b0;\n\tassign wVect1[31] = 1'b0;\nendgenerate\n\n// Interrupt controller\ninterrupt_controller intrCtlr (\n\t.CLK(CLK),\n\t.RST(RST),\n\t.INTR(wIntr),\n\t.INTR_LEGACY_CLR(INTR_LEGACY_CLR),\n\t.INTR_DONE(wIntrDone),\n\t.CFG_INTERRUPT_ASSERT(),\n\t.CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),\n\t.INTR_MSI_RDY(INTR_MSI_RDY),\n\t.INTR_MSI_REQUEST(INTR_MSI_REQUEST)\n);\n\n// Update the interrupt vector when new signals come in (pulse in) and on reset.\nalways @(posedge CLK) begin\n\tif (RST) begin\n\t\trVect0 <= #1 0;\n\t\trVect1 <= #1 0;\n\tend \n\telse begin\n\t\tif (VECT_0_RST) begin\n\t\t\trVect0 <= #1 (wVect0 | (rVect0 & ~VECT_RST));\n\t\t\trVect1 <= #1 (wVect1 | rVect1);\n\t\tend\n\t\telse if (VECT_1_RST) begin\n\t\t\trVect0 <= #1 (wVect0 | rVect0);\n\t\t\trVect1 <= #1 (wVect1 | (rVect1 & ~VECT_RST));\n\t\tend\n\t\telse begin\n\t\t\trVect0 <= #1 (wVect0 | rVect0);\n\t\t\trVect1 <= #1 (wVect1 | rVect1);\n\t\tend\n\tend\nend\t\n\n// Fire the interrupt when we have a non-zero vector.\nalways @(posedge CLK) begin\n\tif (RST) begin\n\t\trState <= #1 `S_INTR_IDLE;\n\tend\n\telse begin\n\t\tcase (rState)\n\t\t`S_INTR_IDLE :\trState <= #1 ((rVect0 | rVect1) == 0 ? `S_INTR_IDLE : `S_INTR_INTR);\n\t\t`S_INTR_INTR :\trState <= #1 (wIntrDone ? `S_INTR_CLR_0 : `S_INTR_INTR);\n\t\t`S_INTR_CLR_0 :\trState <= #1 (VECT_0_RST ? (C_NUM_CHNL > 6 ? `S_INTR_CLR_1 : `S_INTR_IDLE) : `S_INTR_CLR_0);\n\t\t`S_INTR_CLR_1 :\trState <= #1 (VECT_1_RST ? `S_INTR_IDLE : `S_INTR_CLR_1);\n\t\tendcase\n\tend\nend\t\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/interrupt_controller.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tinterrupt_controller.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tSignals an interrupt on the Xilnx PCIe Endpoint \n// \t\t\t\t\t\tinterface. Supports single vector MSI or legacy based\n// \t\t\t\t\t\tinterrupts. \n//\t\t\t\t\t\tWhen INTR is pulsed high, the interrupt will be issued\n//\t\t\t\t\t\tas soon as possible. If using legacy interrupts, the \n//\t\t\t\t\t\tinitial interrupt must be cleared by another request\n//\t\t\t\t\t\t(typically a PIO read or write request to the \n//\t\t\t\t\t\tendpoint at some predetermined BAR address). Receipt of\n//\t\t\t\t\t\tthe \"clear\" acknowledgment should cause INTR_LEGACY_CLR \n// \t\t\t\t\t\tinput to pulse high. Thus completing the legacy \n//\t\t\t\t\t\tinterrupt cycle. If using MSI interrupts, no such\n//\t\t\t\t\t\tacknowldegment is necessary.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_INTRCTLR_IDLE\t\t\t\t3'd0\n`define S_INTRCLTR_WORKING\t\t\t3'd1\n`define S_INTRCLTR_COMPLETE\t\t\t3'd2\n`define S_INTRCLTR_CLEAR_LEGACY\t\t3'd3\n`define S_INTRCLTR_CLEARING_LEGACY\t3'd4\n`define S_INTRCLTR_DONE\t\t\t\t3'd5\n\nmodule interrupt_controller (\n\tinput CLK,\t\t\t\t\t\t// System clock\n\tinput RST,\t\t\t\t\t\t// Async reset\n\tinput INTR,\t\t\t\t\t\t// Pulsed high to request an interrupt\n\tinput INTR_LEGACY_CLR,\t\t\t// Pulsed high to ack the legacy interrupt and clear it\n\toutput INTR_DONE,\t\t\t\t// Pulsed high to signal interrupt sent\n\tinput CONFIG_INTERRUPT_MSIENABLE,\t// 1 if MSI interrupts are enable, 0 if only legacy are supported\n\toutput CFG_INTERRUPT_ASSERT,\t// Legacy interrupt message type\n\tinput INTR_MSI_RDY,\t\t// High when interrupt is able to be sent\n\toutput INTR_MSI_REQUEST\t\t\t// High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent\n);\n\nreg\t\t[2:0]\trState=`S_INTRCTLR_IDLE;\nreg\t\t[2:0]\trStateNext=`S_INTRCTLR_IDLE;\nreg\t\t\t\trIntr=0;\nreg\t\t\t\trIntrAssert=0;\n\nassign INTR_DONE = (rState == `S_INTRCLTR_DONE);\nassign INTR_MSI_REQUEST = rIntr;\nassign CFG_INTERRUPT_ASSERT = rIntrAssert;\n\n// Control sending interrupts.\nalways @(*) begin\n\tcase (rState)\n\n\t`S_INTRCTLR_IDLE : begin\n\t\tif (INTR) begin\n\t\t\trIntr = 1;\n\t\t\trIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;\n\t\t\trStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);\n\t\tend \n\t\telse begin\n\t\t\trIntr = 0;\n\t\t\trIntrAssert = 0;\n\t\t\trStateNext = `S_INTRCTLR_IDLE;\n\t\tend\n\tend\n\n\t`S_INTRCLTR_WORKING : begin\n\t\trIntr = 1;\n\t\trIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;\n\t\trStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);\n\tend\n\n\t`S_INTRCLTR_COMPLETE : begin\n\t\trIntr = 0;\n\t\trIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;\n\t\trStateNext = (CONFIG_INTERRUPT_MSIENABLE ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEAR_LEGACY);\n\tend\n\n\t`S_INTRCLTR_CLEAR_LEGACY : begin\n\t\tif (INTR_LEGACY_CLR) begin\n\t\t\trIntr = 1;\n\t\t\trIntrAssert = 0;\n\t\t\trStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);\n\t\tend \n\t\telse begin\n\t\t\trIntr = 0;\n\t\t\trIntrAssert = 1;\n\t\t\trStateNext = `S_INTRCLTR_CLEAR_LEGACY;\n\t\tend\n\tend\n\n\t`S_INTRCLTR_CLEARING_LEGACY : begin\n\t\trIntr = 1;\n\t\trIntrAssert = 0;\n\t\trStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);\n\tend\n\n\t`S_INTRCLTR_DONE : begin\n\t\trIntr = 0;\n\t\trIntrAssert = 0;\n\t\trStateNext = `S_INTRCTLR_IDLE;\n\tend\n\t\n\tdefault: begin\n\t\trIntr = 0;\n\t\trIntrAssert = 0;\n\t\trStateNext = `S_INTRCTLR_IDLE;\n\tend\n\t\n\tendcase\nend\n\n// Update the state.\nalways @(posedge CLK) begin\n\tif (RST)\n\t\trState <= #1 `S_INTRCTLR_IDLE;\n\telse\n\t\trState <= #1 rStateNext;\nend\n\nendmodule\n\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/pcie_2_0_v6.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : pcie_2_0_v6.v\n// Version : 2.4\n//-- Description: Solution wrapper for Virtex6 Hard Block for PCI Express\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n`timescale 1ps/1ps\n\nmodule pcie_2_0_v6 #(\n parameter TCQ = 1,\n parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz\n parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages\n parameter AER_BASE_PTR = 12'h128,\n parameter AER_CAP_ECRC_CHECK_CAPABLE = \"FALSE\",\n parameter AER_CAP_ECRC_GEN_CAPABLE = \"FALSE\",\n parameter AER_CAP_ID = 16'h0001,\n parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a,\n parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15,\n parameter AER_CAP_NEXTPTR = 12'h160,\n parameter AER_CAP_ON = \"FALSE\",\n parameter AER_CAP_PERMIT_ROOTERR_UPDATE = \"TRUE\",\n parameter AER_CAP_VERSION = 4'h1,\n parameter ALLOW_X8_GEN2 = \"TRUE\",\n parameter BAR0 = 32'hffffff00,\n parameter BAR1 = 32'hffff0000,\n parameter BAR2 = 32'hffff000c,\n parameter BAR3 = 32'hffffffff,\n parameter BAR4 = 32'h00000000,\n parameter BAR5 = 32'h00000000,\n parameter CAPABILITIES_PTR = 8'h40,\n parameter CARDBUS_CIS_POINTER = 32'h00000000,\n parameter CLASS_CODE = 24'h000000,\n parameter CMD_INTX_IMPLEMENTED = \"TRUE\",\n parameter CPL_TIMEOUT_DISABLE_SUPPORTED = \"FALSE\",\n parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,\n parameter CRM_MODULE_RSTS = 7'h00,\n parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = \"TRUE\",\n parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = \"TRUE\",\n parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 0,\n parameter DEV_CAP_ENDPOINT_L1_LATENCY = 0,\n parameter DEV_CAP_EXT_TAG_SUPPORTED = \"TRUE\",\n parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = \"FALSE\",\n parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,\n parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,\n parameter DEV_CAP_ROLE_BASED_ERROR = \"TRUE\",\n parameter DEV_CAP_RSVD_14_12 = 0,\n parameter DEV_CAP_RSVD_17_16 = 0,\n parameter DEV_CAP_RSVD_31_29 = 0,\n parameter DEV_CONTROL_AUX_POWER_SUPPORTED = \"FALSE\",\n parameter DEVICE_ID = 16'h0007,\n parameter DISABLE_ASPM_L1_TIMER = \"FALSE\",\n parameter DISABLE_BAR_FILTERING = \"FALSE\",\n parameter DISABLE_ID_CHECK = \"FALSE\",\n parameter DISABLE_LANE_REVERSAL = \"FALSE\",\n parameter DISABLE_RX_TC_FILTER = \"FALSE\",\n parameter DISABLE_SCRAMBLING = \"FALSE\",\n parameter DNSTREAM_LINK_NUM = 8'h00,\n parameter DSN_BASE_PTR = 12'h100,\n parameter DSN_CAP_ID = 16'h0003,\n parameter DSN_CAP_NEXTPTR = 12'h000,\n parameter DSN_CAP_ON = \"TRUE\",\n parameter DSN_CAP_VERSION = 4'h1,\n parameter ENABLE_MSG_ROUTE = 11'h000,\n parameter ENABLE_RX_TD_ECRC_TRIM = \"FALSE\",\n parameter ENTER_RVRY_EI_L0 = \"TRUE\",\n parameter EXPANSION_ROM = 32'hfffff001,\n parameter EXT_CFG_CAP_PTR = 6'h3f,\n parameter EXT_CFG_XP_CAP_PTR = 10'h3ff,\n parameter HEADER_TYPE = 8'h00,\n parameter INFER_EI = 5'h00,\n parameter INTERRUPT_PIN = 8'h01,\n parameter IS_SWITCH = \"FALSE\",\n parameter LAST_CONFIG_DWORD = 10'h042,\n parameter LINK_CAP_ASPM_SUPPORT = 1,\n parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = \"FALSE\",\n parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = \"FALSE\",\n parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = \"FALSE\",\n parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,\n parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,\n parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,\n parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,\n parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,\n parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,\n parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,\n parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,\n parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,\n parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08,\n parameter LINK_CAP_RSVD_23_22 = 0,\n parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = \"FALSE\",\n parameter LINK_CONTROL_RCB = 0,\n parameter LINK_CTRL2_DEEMPHASIS = \"FALSE\",\n parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = \"FALSE\",\n parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h0,\n parameter LINK_STATUS_SLOT_CLOCK_CONFIG = \"TRUE\",\n parameter LL_ACK_TIMEOUT = 15'h0204,\n parameter LL_ACK_TIMEOUT_EN = \"FALSE\",\n parameter LL_ACK_TIMEOUT_FUNC = 0,\n parameter LL_REPLAY_TIMEOUT = 15'h060d,\n parameter LL_REPLAY_TIMEOUT_EN = \"FALSE\",\n parameter LL_REPLAY_TIMEOUT_FUNC = 0,\n parameter LTSSM_MAX_LINK_WIDTH = LINK_CAP_MAX_LINK_WIDTH,\n parameter MSI_BASE_PTR = 8'h48,\n parameter MSI_CAP_ID = 8'h05,\n parameter MSI_CAP_MULTIMSGCAP = 0,\n parameter MSI_CAP_MULTIMSG_EXTENSION = 0,\n parameter MSI_CAP_NEXTPTR = 8'h60,\n parameter MSI_CAP_ON = \"FALSE\",\n parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = \"TRUE\",\n parameter MSI_CAP_64_BIT_ADDR_CAPABLE = \"TRUE\",\n parameter MSIX_BASE_PTR = 8'h9c,\n parameter MSIX_CAP_ID = 8'h11,\n parameter MSIX_CAP_NEXTPTR = 8'h00,\n parameter MSIX_CAP_ON = \"FALSE\",\n parameter MSIX_CAP_PBA_BIR = 0,\n parameter MSIX_CAP_PBA_OFFSET = 29'h00000050,\n parameter MSIX_CAP_TABLE_BIR = 0,\n parameter MSIX_CAP_TABLE_OFFSET = 29'h00000040,\n parameter MSIX_CAP_TABLE_SIZE = 11'h000,\n parameter N_FTS_COMCLK_GEN1 = 255,\n parameter N_FTS_COMCLK_GEN2 = 255,\n parameter N_FTS_GEN1 = 255,\n parameter N_FTS_GEN2 = 255,\n parameter PCIE_BASE_PTR = 8'h60,\n parameter PCIE_CAP_CAPABILITY_ID = 8'h10,\n parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2,\n parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,\n parameter PCIE_CAP_INT_MSG_NUM = 5'h00,\n parameter PCIE_CAP_NEXTPTR = 8'h00,\n parameter PCIE_CAP_ON = \"TRUE\",\n parameter PCIE_CAP_RSVD_15_14 = 0,\n parameter PCIE_CAP_SLOT_IMPLEMENTED = \"FALSE\",\n parameter PCIE_REVISION = 2,\n parameter PGL0_LANE = 0,\n parameter PGL1_LANE = 1,\n parameter PGL2_LANE = 2,\n parameter PGL3_LANE = 3,\n parameter PGL4_LANE = 4,\n parameter PGL5_LANE = 5,\n parameter PGL6_LANE = 6,\n parameter PGL7_LANE = 7,\n parameter PL_AUTO_CONFIG = 0,\n parameter PL_FAST_TRAIN = \"FALSE\",\n parameter PM_BASE_PTR = 8'h40,\n parameter PM_CAP_AUXCURRENT = 0,\n parameter PM_CAP_DSI = \"FALSE\",\n parameter PM_CAP_D1SUPPORT = \"TRUE\",\n parameter PM_CAP_D2SUPPORT = \"TRUE\",\n parameter PM_CAP_ID = 8'h01,\n parameter PM_CAP_NEXTPTR = 8'h48,\n parameter PM_CAP_ON = \"TRUE\",\n parameter PM_CAP_PME_CLOCK = \"FALSE\",\n parameter PM_CAP_PMESUPPORT = 5'h0f,\n parameter PM_CAP_RSVD_04 = 0,\n parameter PM_CAP_VERSION = 3,\n parameter PM_CSR_BPCCEN = \"FALSE\",\n parameter PM_CSR_B2B3 = \"FALSE\",\n parameter PM_CSR_NOSOFTRST = \"TRUE\",\n parameter PM_DATA_SCALE0 = 2'h1,\n parameter PM_DATA_SCALE1 = 2'h1,\n parameter PM_DATA_SCALE2 = 2'h1,\n parameter PM_DATA_SCALE3 = 2'h1,\n parameter PM_DATA_SCALE4 = 2'h1,\n parameter PM_DATA_SCALE5 = 2'h1,\n parameter PM_DATA_SCALE6 = 2'h1,\n parameter PM_DATA_SCALE7 = 2'h1,\n parameter PM_DATA0 = 8'h01,\n parameter PM_DATA1 = 8'h01,\n parameter PM_DATA2 = 8'h01,\n parameter PM_DATA3 = 8'h01,\n parameter PM_DATA4 = 8'h01,\n parameter PM_DATA5 = 8'h01,\n parameter PM_DATA6 = 8'h01,\n parameter PM_DATA7 = 8'h01,\n parameter RECRC_CHK = 0,\n parameter RECRC_CHK_TRIM = \"FALSE\",\n parameter REVISION_ID = 8'h00,\n parameter ROOT_CAP_CRS_SW_VISIBILITY = \"FALSE\",\n parameter SELECT_DLL_IF = \"FALSE\",\n parameter SLOT_CAP_ATT_BUTTON_PRESENT = \"FALSE\",\n parameter SLOT_CAP_ATT_INDICATOR_PRESENT = \"FALSE\",\n parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = \"FALSE\",\n parameter SLOT_CAP_HOTPLUG_CAPABLE = \"FALSE\",\n parameter SLOT_CAP_HOTPLUG_SURPRISE = \"FALSE\",\n parameter SLOT_CAP_MRL_SENSOR_PRESENT = \"FALSE\",\n parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = \"FALSE\",\n parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,\n parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = \"FALSE\",\n parameter SLOT_CAP_POWER_INDICATOR_PRESENT = \"FALSE\",\n parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,\n parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,\n parameter SPARE_BIT0 = 0,\n parameter SPARE_BIT1 = 0,\n parameter SPARE_BIT2 = 0,\n parameter SPARE_BIT3 = 0,\n parameter SPARE_BIT4 = 0,\n parameter SPARE_BIT5 = 0,\n parameter SPARE_BIT6 = 0,\n parameter SPARE_BIT7 = 0,\n parameter SPARE_BIT8 = 0,\n parameter SPARE_BYTE0 = 8'h00,\n parameter SPARE_BYTE1 = 8'h00,\n parameter SPARE_BYTE2 = 8'h00,\n parameter SPARE_BYTE3 = 8'h00,\n parameter SPARE_WORD0 = 32'h00000000,\n parameter SPARE_WORD1 = 32'h00000000,\n parameter SPARE_WORD2 = 32'h00000000,\n parameter SPARE_WORD3 = 32'h00000000,\n parameter SUBSYSTEM_ID = 16'h0007,\n parameter SUBSYSTEM_VENDOR_ID = 16'h10ee,\n parameter TL_RBYPASS = \"FALSE\",\n parameter TL_RX_RAM_RADDR_LATENCY = 0,\n parameter TL_RX_RAM_RDATA_LATENCY = 2,\n parameter TL_RX_RAM_WRITE_LATENCY = 0,\n parameter TL_TFC_DISABLE = \"FALSE\",\n parameter TL_TX_CHECKS_DISABLE = \"FALSE\",\n parameter TL_TX_RAM_RADDR_LATENCY = 0,\n parameter TL_TX_RAM_RDATA_LATENCY = 2,\n parameter TL_TX_RAM_WRITE_LATENCY = 0,\n parameter UPCONFIG_CAPABLE = \"TRUE\",\n parameter UPSTREAM_FACING = \"TRUE\",\n parameter EXIT_LOOPBACK_ON_EI = \"TRUE\",\n parameter UR_INV_REQ = \"TRUE\",\n parameter USER_CLK_FREQ = 3,\n parameter VC_BASE_PTR = 12'h10c,\n parameter VC_CAP_ID = 16'h0002,\n parameter VC_CAP_NEXTPTR = 12'h000,\n parameter VC_CAP_ON = \"FALSE\",\n parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = \"FALSE\",\n parameter VC_CAP_VERSION = 4'h1,\n parameter VC0_CPL_INFINITE = \"TRUE\",\n parameter VC0_RX_RAM_LIMIT = 13'h03ff,\n parameter VC0_TOTAL_CREDITS_CD = 127,\n parameter VC0_TOTAL_CREDITS_CH = 31,\n parameter VC0_TOTAL_CREDITS_NPH = 12,\n parameter VC0_TOTAL_CREDITS_PD = 288,\n parameter VC0_TOTAL_CREDITS_PH = 32,\n parameter VC0_TX_LASTPACKET = 31,\n parameter VENDOR_ID = 16'h10ee,\n parameter VSEC_BASE_PTR = 12'h160,\n parameter VSEC_CAP_HDR_ID = 16'h1234,\n parameter VSEC_CAP_HDR_LENGTH = 12'h018,\n parameter VSEC_CAP_HDR_REVISION = 4'h1,\n parameter VSEC_CAP_ID = 16'h000b,\n parameter VSEC_CAP_IS_LINK_VISIBLE = \"TRUE\",\n parameter VSEC_CAP_NEXTPTR = 12'h000,\n parameter VSEC_CAP_ON = \"FALSE\",\n parameter VSEC_CAP_VERSION = 4'h1\n\n)\n(\n\n input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPRXN,\n input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPRXP,\n output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPTXN,\n output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPTXP,\n\n input SYSCLK,\n input FUNDRSTN,\n\n output TRNLNKUPN,\n\n output PHYRDYN,\n output USERRSTN,\n output RECEIVEDFUNCLVLRSTN,\n output LNKCLKEN,\n input SYSRSTN,\n input PLRSTN,\n input DLRSTN,\n input TLRSTN,\n input FUNCLVLRSTN,\n input CMRSTN,\n input CMSTICKYRSTN,\n\n output [6:0] TRNRBARHITN,\n output [63:0] TRNRD,\n output TRNRECRCERRN,\n output TRNREOFN,\n output TRNRERRFWDN,\n output TRNRREMN,\n output TRNRSOFN,\n output TRNRSRCDSCN,\n output TRNRSRCRDYN,\n input TRNRDSTRDYN,\n input TRNRNPOKN,\n\n output [5:0] TRNTBUFAV,\n output TRNTCFGREQN,\n\n output TRNTDLLPDSTRDYN,\n output TRNTDSTRDYN,\n output TRNTERRDROPN,\n\n input TRNTCFGGNTN,\n\n input [63:0] TRNTD,\n input [31:0] TRNTDLLPDATA,\n input TRNTDLLPSRCRDYN,\n input TRNTECRCGENN,\n input TRNTEOFN,\n input TRNTERRFWDN,\n input TRNTREMN,\n\n\n input TRNTSOFN,\n input TRNTSRCDSCN,\n input TRNTSRCRDYN,\n input TRNTSTRN,\n\n output [11:0] TRNFCCPLD,\n output [7:0] TRNFCCPLH,\n output [11:0] TRNFCNPD,\n output [7:0] TRNFCNPH,\n output [11:0] TRNFCPD,\n output [7:0] TRNFCPH,\n input [2:0] TRNFCSEL,\n\n output CFGAERECRCCHECKEN,\n output CFGAERECRCGENEN,\n output CFGCOMMANDBUSMASTERENABLE,\n output CFGCOMMANDINTERRUPTDISABLE,\n output CFGCOMMANDIOENABLE,\n output CFGCOMMANDMEMENABLE,\n output CFGCOMMANDSERREN,\n output CFGDEVCONTROLAUXPOWEREN,\n output CFGDEVCONTROLCORRERRREPORTINGEN,\n output CFGDEVCONTROLENABLERO,\n output CFGDEVCONTROLEXTTAGEN,\n output CFGDEVCONTROLFATALERRREPORTINGEN,\n output [2:0] CFGDEVCONTROLMAXPAYLOAD,\n output [2:0] CFGDEVCONTROLMAXREADREQ,\n output CFGDEVCONTROLNONFATALREPORTINGEN,\n output CFGDEVCONTROLNOSNOOPEN,\n output CFGDEVCONTROLPHANTOMEN,\n output CFGDEVCONTROLURERRREPORTINGEN,\n output CFGDEVCONTROL2CPLTIMEOUTDIS,\n output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL,\n output CFGDEVSTATUSCORRERRDETECTED,\n output CFGDEVSTATUSFATALERRDETECTED,\n output CFGDEVSTATUSNONFATALERRDETECTED,\n output CFGDEVSTATUSURDETECTED,\n output [31:0] CFGDO,\n output CFGERRAERHEADERLOGSETN,\n output CFGERRCPLRDYN,\n output [7:0] CFGINTERRUPTDO,\n output [2:0] CFGINTERRUPTMMENABLE,\n output CFGINTERRUPTMSIENABLE,\n output CFGINTERRUPTMSIXENABLE,\n output CFGINTERRUPTMSIXFM,\n output CFGINTERRUPTRDYN,\n output CFGLINKCONTROLRCB,\n output [1:0] CFGLINKCONTROLASPMCONTROL,\n output CFGLINKCONTROLAUTOBANDWIDTHINTEN,\n output CFGLINKCONTROLBANDWIDTHINTEN,\n output CFGLINKCONTROLCLOCKPMEN,\n output CFGLINKCONTROLCOMMONCLOCK,\n output CFGLINKCONTROLEXTENDEDSYNC,\n output CFGLINKCONTROLHWAUTOWIDTHDIS,\n output CFGLINKCONTROLLINKDISABLE,\n output CFGLINKCONTROLRETRAINLINK,\n output CFGLINKSTATUSAUTOBANDWIDTHSTATUS,\n output CFGLINKSTATUSBANDWITHSTATUS,\n output [1:0] CFGLINKSTATUSCURRENTSPEED,\n output CFGLINKSTATUSDLLACTIVE,\n output CFGLINKSTATUSLINKTRAINING,\n output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH,\n output [15:0] CFGMSGDATA,\n output CFGMSGRECEIVED,\n output CFGMSGRECEIVEDASSERTINTA,\n output CFGMSGRECEIVEDASSERTINTB,\n output CFGMSGRECEIVEDASSERTINTC,\n output CFGMSGRECEIVEDASSERTINTD,\n output CFGMSGRECEIVEDDEASSERTINTA,\n output CFGMSGRECEIVEDDEASSERTINTB,\n output CFGMSGRECEIVEDDEASSERTINTC,\n output CFGMSGRECEIVEDDEASSERTINTD,\n output CFGMSGRECEIVEDERRCOR,\n output CFGMSGRECEIVEDERRFATAL,\n output CFGMSGRECEIVEDERRNONFATAL,\n output CFGMSGRECEIVEDPMASNAK,\n output CFGMSGRECEIVEDPMETO,\n output CFGMSGRECEIVEDPMETOACK,\n output CFGMSGRECEIVEDPMPME,\n output CFGMSGRECEIVEDSETSLOTPOWERLIMIT,\n output CFGMSGRECEIVEDUNLOCK,\n output [2:0] CFGPCIELINKSTATE,\n output CFGPMCSRPMEEN,\n output CFGPMCSRPMESTATUS,\n output [1:0] CFGPMCSRPOWERSTATE,\n output CFGPMRCVASREQL1N,\n output CFGPMRCVENTERL1N,\n output CFGPMRCVENTERL23N,\n output CFGPMRCVREQACKN,\n output CFGRDWRDONEN,\n output CFGSLOTCONTROLELECTROMECHILCTLPULSE,\n output CFGTRANSACTION,\n output [6:0] CFGTRANSACTIONADDR,\n output CFGTRANSACTIONTYPE,\n output [6:0] CFGVCTCVCMAP,\n input [3:0] CFGBYTEENN,\n input [31:0] CFGDI,\n input [7:0] CFGDSBUSNUMBER,\n input [4:0] CFGDSDEVICENUMBER,\n input [2:0] CFGDSFUNCTIONNUMBER,\n input [63:0] CFGDSN,\n input [9:0] CFGDWADDR,\n input CFGERRACSN,\n input [127:0] CFGERRAERHEADERLOG,\n input CFGERRCORN,\n input CFGERRCPLABORTN,\n input CFGERRCPLTIMEOUTN,\n input CFGERRCPLUNEXPECTN,\n input CFGERRECRCN,\n input CFGERRLOCKEDN,\n input CFGERRPOSTEDN,\n input [47:0] CFGERRTLPCPLHEADER,\n input CFGERRURN,\n input CFGINTERRUPTASSERTN,\n input [7:0] CFGINTERRUPTDI,\n input CFGINTERRUPTN,\n input CFGPMDIRECTASPML1N,\n input CFGPMSENDPMACKN,\n input CFGPMSENDPMETON,\n input CFGPMSENDPMNAKN,\n input CFGPMTURNOFFOKN,\n input CFGPMWAKEN,\n input [7:0] CFGPORTNUMBER,\n input CFGRDENN,\n input CFGTRNPENDINGN,\n input CFGWRENN,\n input CFGWRREADONLYN,\n input CFGWRRW1CASRWN,\n\n output [2:0] PLINITIALLINKWIDTH,\n output [1:0] PLLANEREVERSALMODE,\n output PLLINKGEN2CAP,\n output PLLINKPARTNERGEN2SUPPORTED,\n output PLLINKUPCFGCAP,\n output [5:0] PLLTSSMSTATE,\n output PLPHYLNKUPN,\n output PLRECEIVEDHOTRST,\n output [1:0] PLRXPMSTATE,\n output PLSELLNKRATE,\n output [1:0] PLSELLNKWIDTH,\n output [2:0] PLTXPMSTATE,\n input PLDIRECTEDLINKAUTON,\n input [1:0] PLDIRECTEDLINKCHANGE,\n input PLDIRECTEDLINKSPEED,\n input [1:0] PLDIRECTEDLINKWIDTH,\n input PLDOWNSTREAMDEEMPHSOURCE,\n input PLUPSTREAMPREFERDEEMPH,\n input PLTRANSMITHOTRST,\n\n output DBGSCLRA,\n output DBGSCLRB,\n output DBGSCLRC,\n output DBGSCLRD,\n output DBGSCLRE,\n output DBGSCLRF,\n output DBGSCLRG,\n output DBGSCLRH,\n output DBGSCLRI,\n output DBGSCLRJ,\n output DBGSCLRK,\n output [63:0] DBGVECA,\n output [63:0] DBGVECB,\n output [11:0] DBGVECC,\n output [11:0] PLDBGVEC,\n input [1:0] DBGMODE,\n input DBGSUBMODE,\n input [2:0] PLDBGMODE,\n output [15:0] PCIEDRPDO,\n output PCIEDRPDRDY,\n input PCIEDRPCLK,\n input [8:0] PCIEDRPDADDR,\n input PCIEDRPDEN,\n input [15:0] PCIEDRPDI,\n input PCIEDRPDWE,\n\n output GTPLLLOCK,\n input PIPECLK,\n input USERCLK,\n input DRPCLK,\n input CLOCKLOCKED,\n output TxOutClk,\n\n output [31:0] TRNRDLLPDATA,\n output TRNRDLLPSRCRDYN\n\n\n\n );\n\n // wire declarations\n\n wire LL2BADDLLPERRN;\n wire LL2BADTLPERRN;\n wire LL2PROTOCOLERRN;\n wire LL2REPLAYROERRN;\n wire LL2REPLAYTOERRN;\n wire LL2SUSPENDOKN;\n wire LL2TFCINIT1SEQN;\n wire LL2TFCINIT2SEQN;\n wire [12:0] MIMRXRADDR;\n wire MIMRXRCE;\n wire MIMRXREN;\n wire [12:0] MIMRXWADDR;\n wire [67:0] MIMRXWDATA;\n wire MIMRXWEN;\n wire [12:0] MIMTXRADDR;\n wire MIMTXRCE;\n wire MIMTXREN;\n wire [12:0] MIMTXWADDR;\n wire [68:0] MIMTXWDATA;\n wire MIMTXWEN;\n wire PIPERX0POLARITY;\n wire PIPERX1POLARITY;\n wire PIPERX2POLARITY;\n wire PIPERX3POLARITY;\n wire PIPERX4POLARITY;\n wire PIPERX5POLARITY;\n wire PIPERX6POLARITY;\n wire PIPERX7POLARITY;\n wire PIPETXDEEMPH;\n wire [2:0] PIPETXMARGIN;\n wire PIPETXRATE;\n wire PIPETXRCVRDET;\n wire PIPETXRESET;\n wire [1:0] PIPETX0CHARISK;\n wire PIPETX0COMPLIANCE;\n wire [15:0] PIPETX0DATA;\n wire PIPETX0ELECIDLE;\n wire [1:0] PIPETX0POWERDOWN;\n wire [1:0] PIPETX1CHARISK;\n wire PIPETX1COMPLIANCE;\n wire [15:0] PIPETX1DATA;\n wire PIPETX1ELECIDLE;\n wire [1:0] PIPETX1POWERDOWN;\n wire [1:0] PIPETX2CHARISK;\n wire PIPETX2COMPLIANCE;\n wire [15:0] PIPETX2DATA;\n wire PIPETX2ELECIDLE;\n wire [1:0] PIPETX2POWERDOWN;\n wire [1:0] PIPETX3CHARISK;\n wire PIPETX3COMPLIANCE;\n wire [15:0] PIPETX3DATA;\n wire PIPETX3ELECIDLE;\n wire [1:0] PIPETX3POWERDOWN;\n wire [1:0] PIPETX4CHARISK;\n wire PIPETX4COMPLIANCE;\n wire [15:0] PIPETX4DATA;\n wire PIPETX4ELECIDLE;\n wire [1:0] PIPETX4POWERDOWN;\n wire [1:0] PIPETX5CHARISK;\n wire PIPETX5COMPLIANCE;\n wire [15:0] PIPETX5DATA;\n wire PIPETX5ELECIDLE;\n wire [1:0] PIPETX5POWERDOWN;\n wire [1:0] PIPETX6CHARISK;\n wire PIPETX6COMPLIANCE;\n wire [15:0] PIPETX6DATA;\n wire PIPETX6ELECIDLE;\n wire [1:0] PIPETX6POWERDOWN;\n wire [1:0] PIPETX7CHARISK;\n wire PIPETX7COMPLIANCE;\n wire [15:0] PIPETX7DATA;\n wire PIPETX7ELECIDLE;\n wire [1:0] PIPETX7POWERDOWN;\n wire PL2LINKUPN;\n wire PL2RECEIVERERRN;\n wire PL2RECOVERYN;\n wire PL2RXELECIDLE;\n wire PL2SUSPENDOK;\n wire TL2ASPMSUSPENDCREDITCHECKOKN;\n wire TL2ASPMSUSPENDREQN;\n wire TL2PPMSUSPENDOKN;\n wire LL2SENDASREQL1N = 1'b1;\n wire LL2SENDENTERL1N = 1'b1;\n wire LL2SENDENTERL23N = 1'b1;\n wire LL2SUSPENDNOWN = 1'b1;\n wire LL2TLPRCVN = 1'b1;\n wire [71:0] MIMRXRDATA;\n wire [71:0] MIMTXRDATA;\n wire [4:0] PL2DIRECTEDLSTATE = 5'b0;\n wire TL2ASPMSUSPENDCREDITCHECKN;\n wire TL2PPMSUSPENDREQN;\n wire PIPERX0CHANISALIGNED;\n wire [1:0] PIPERX0CHARISK;\n wire [15:0] PIPERX0DATA;\n wire PIPERX0ELECIDLE;\n wire PIPERX0PHYSTATUS;\n wire [2:0] PIPERX0STATUS;\n wire PIPERX0VALID;\n wire PIPERX1CHANISALIGNED;\n wire [1:0] PIPERX1CHARISK;\n wire [15:0] PIPERX1DATA;\n wire PIPERX1ELECIDLE;\n wire PIPERX1PHYSTATUS;\n wire [2:0] PIPERX1STATUS;\n wire PIPERX1VALID;\n wire PIPERX2CHANISALIGNED;\n wire [1:0] PIPERX2CHARISK;\n wire [15:0] PIPERX2DATA;\n wire PIPERX2ELECIDLE;\n wire PIPERX2PHYSTATUS;\n wire [2:0] PIPERX2STATUS;\n wire PIPERX2VALID;\n wire PIPERX3CHANISALIGNED;\n wire [1:0] PIPERX3CHARISK;\n wire [15:0] PIPERX3DATA;\n wire PIPERX3ELECIDLE;\n wire PIPERX3PHYSTATUS;\n wire [2:0] PIPERX3STATUS;\n wire PIPERX3VALID;\n wire PIPERX4CHANISALIGNED;\n wire [1:0] PIPERX4CHARISK;\n wire [15:0] PIPERX4DATA;\n wire PIPERX4ELECIDLE;\n wire PIPERX4PHYSTATUS;\n wire [2:0] PIPERX4STATUS;\n wire PIPERX4VALID;\n wire PIPERX5CHANISALIGNED;\n wire [1:0] PIPERX5CHARISK;\n wire [15:0] PIPERX5DATA;\n wire PIPERX5ELECIDLE;\n wire PIPERX5PHYSTATUS;\n wire [2:0] PIPERX5STATUS;\n wire PIPERX5VALID;\n wire PIPERX6CHANISALIGNED;\n wire [1:0] PIPERX6CHARISK;\n wire [15:0] PIPERX6DATA;\n wire PIPERX6ELECIDLE;\n wire PIPERX6PHYSTATUS;\n wire [2:0] PIPERX6STATUS;\n wire PIPERX6VALID;\n wire PIPERX7CHANISALIGNED;\n wire [1:0] PIPERX7CHARISK;\n wire [15:0] PIPERX7DATA;\n wire PIPERX7ELECIDLE;\n wire PIPERX7PHYSTATUS;\n wire [2:0] PIPERX7STATUS;\n wire PIPERX7VALID;\n\n wire PIPERX0POLARITYGT;\n wire PIPERX1POLARITYGT;\n wire PIPERX2POLARITYGT;\n wire PIPERX3POLARITYGT;\n wire PIPERX4POLARITYGT;\n wire PIPERX5POLARITYGT;\n wire PIPERX6POLARITYGT;\n wire PIPERX7POLARITYGT;\n wire PIPETXDEEMPHGT;\n wire [2:0] PIPETXMARGINGT;\n wire PIPETXRATEGT;\n wire PIPETXRCVRDETGT;\n wire [1:0] PIPETX0CHARISKGT;\n wire PIPETX0COMPLIANCEGT;\n wire [15:0] PIPETX0DATAGT;\n wire PIPETX0ELECIDLEGT;\n wire [1:0] PIPETX0POWERDOWNGT;\n wire [1:0] PIPETX1CHARISKGT;\n wire PIPETX1COMPLIANCEGT;\n wire [15:0] PIPETX1DATAGT;\n wire PIPETX1ELECIDLEGT;\n wire [1:0] PIPETX1POWERDOWNGT;\n wire [1:0] PIPETX2CHARISKGT;\n wire PIPETX2COMPLIANCEGT;\n wire [15:0] PIPETX2DATAGT;\n wire PIPETX2ELECIDLEGT;\n wire [1:0] PIPETX2POWERDOWNGT;\n wire [1:0] PIPETX3CHARISKGT;\n wire PIPETX3COMPLIANCEGT;\n wire [15:0] PIPETX3DATAGT;\n wire PIPETX3ELECIDLEGT;\n wire [1:0] PIPETX3POWERDOWNGT;\n wire [1:0] PIPETX4CHARISKGT;\n wire PIPETX4COMPLIANCEGT;\n wire [15:0] PIPETX4DATAGT;\n wire PIPETX4ELECIDLEGT;\n wire [1:0] PIPETX4POWERDOWNGT;\n wire [1:0] PIPETX5CHARISKGT;\n wire PIPETX5COMPLIANCEGT;\n wire [15:0] PIPETX5DATAGT;\n wire PIPETX5ELECIDLEGT;\n wire [1:0] PIPETX5POWERDOWNGT;\n wire [1:0] PIPETX6CHARISKGT;\n wire PIPETX6COMPLIANCEGT;\n wire [15:0] PIPETX6DATAGT;\n wire PIPETX6ELECIDLEGT;\n wire [1:0] PIPETX6POWERDOWNGT;\n wire [1:0] PIPETX7CHARISKGT;\n wire PIPETX7COMPLIANCEGT;\n wire [15:0] PIPETX7DATAGT;\n wire PIPETX7ELECIDLEGT;\n wire [1:0] PIPETX7POWERDOWNGT;\n\n wire PIPERX0CHANISALIGNEDGT;\n wire [1:0] PIPERX0CHARISKGT;\n wire [15:0] PIPERX0DATAGT;\n wire PIPERX0ELECIDLEGT;\n wire PIPERX0PHYSTATUSGT;\n wire [2:0] PIPERX0STATUSGT;\n wire PIPERX0VALIDGT;\n wire PIPERX1CHANISALIGNEDGT;\n wire [1:0] PIPERX1CHARISKGT;\n wire [15:0] PIPERX1DATAGT;\n wire PIPERX1ELECIDLEGT;\n wire PIPERX1PHYSTATUSGT;\n wire [2:0] PIPERX1STATUSGT;\n wire PIPERX1VALIDGT;\n wire PIPERX2CHANISALIGNEDGT;\n wire [1:0] PIPERX2CHARISKGT;\n wire [15:0] PIPERX2DATAGT;\n wire PIPERX2ELECIDLEGT;\n wire PIPERX2PHYSTATUSGT;\n wire [2:0] PIPERX2STATUSGT;\n wire PIPERX2VALIDGT;\n wire PIPERX3CHANISALIGNEDGT;\n wire [1:0] PIPERX3CHARISKGT;\n wire [15:0] PIPERX3DATAGT;\n wire PIPERX3ELECIDLEGT;\n wire PIPERX3PHYSTATUSGT;\n wire [2:0] PIPERX3STATUSGT;\n wire PIPERX3VALIDGT;\n wire PIPERX4CHANISALIGNEDGT;\n wire [1:0] PIPERX4CHARISKGT;\n wire [15:0] PIPERX4DATAGT;\n wire PIPERX4ELECIDLEGT;\n wire PIPERX4PHYSTATUSGT;\n wire [2:0] PIPERX4STATUSGT;\n wire PIPERX4VALIDGT;\n wire PIPERX5CHANISALIGNEDGT;\n wire [1:0] PIPERX5CHARISKGT;\n wire [15:0] PIPERX5DATAGT;\n wire PIPERX5ELECIDLEGT;\n wire PIPERX5PHYSTATUSGT;\n wire [2:0] PIPERX5STATUSGT;\n wire PIPERX5VALIDGT;\n wire PIPERX6CHANISALIGNEDGT;\n wire [1:0] PIPERX6CHARISKGT;\n wire [15:0] PIPERX6DATAGT;\n wire PIPERX6ELECIDLEGT;\n wire PIPERX6PHYSTATUSGT;\n wire [2:0] PIPERX6STATUSGT;\n wire PIPERX6VALIDGT;\n wire PIPERX7CHANISALIGNEDGT;\n wire [1:0] PIPERX7CHARISKGT;\n wire [15:0] PIPERX7DATAGT;\n wire PIPERX7ELECIDLEGT;\n wire PIPERX7PHYSTATUSGT;\n wire [2:0] PIPERX7STATUSGT;\n wire PIPERX7VALIDGT;\n\n wire filter_pipe_upconfig_fix_3451;\n\n\n\n\n\n\n//-------------------------------------------------------\n// Virtex6 PCI Express Block Module\n//-------------------------------------------------------\nPCIE_2_0 #(\n\n .AER_BASE_PTR ( AER_BASE_PTR ),\n .AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),\n .AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),\n .AER_CAP_ID ( AER_CAP_ID ),\n .AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ),\n .AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ),\n .AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),\n .AER_CAP_ON ( AER_CAP_ON ),\n .AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),\n .AER_CAP_VERSION ( AER_CAP_VERSION ),\n .ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),\n .BAR0 ( BAR0 ),\n .BAR1 ( BAR1 ),\n .BAR2 ( BAR2 ),\n .BAR3 ( BAR3 ),\n .BAR4 ( BAR4 ),\n .BAR5 ( BAR5 ),\n .CAPABILITIES_PTR ( CAPABILITIES_PTR ),\n .CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),\n .CLASS_CODE ( CLASS_CODE ),\n .CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),\n .CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),\n .CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),\n .CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),\n .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),\n .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),\n .DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),\n .DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),\n .DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),\n .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),\n .DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),\n .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),\n .DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),\n .DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),\n .DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),\n .DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),\n .DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),\n .DEVICE_ID ( DEVICE_ID ),\n .DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),\n .DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),\n .DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),\n .DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),\n .DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),\n .DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),\n .DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),\n .DSN_BASE_PTR ( DSN_BASE_PTR ),\n .DSN_CAP_ID ( DSN_CAP_ID ),\n .DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),\n .DSN_CAP_ON ( DSN_CAP_ON ),\n .DSN_CAP_VERSION ( DSN_CAP_VERSION ),\n .ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),\n .ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),\n .ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),\n .EXPANSION_ROM ( EXPANSION_ROM ),\n .EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),\n .EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),\n .HEADER_TYPE ( HEADER_TYPE ),\n .INFER_EI ( INFER_EI ),\n .INTERRUPT_PIN ( INTERRUPT_PIN ),\n .IS_SWITCH ( IS_SWITCH ),\n .LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),\n .LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),\n .LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),\n .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),\n .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),\n .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),\n .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),\n .LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),\n .LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),\n .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),\n .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),\n .LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),\n .LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),\n .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),\n .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),\n .LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ),\n .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),\n .LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),\n .LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),\n .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),\n .LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),\n .LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),\n .LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),\n .LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),\n .LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),\n .LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),\n .LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),\n .LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),\n .LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),\n .MSI_BASE_PTR ( MSI_BASE_PTR ),\n .MSI_CAP_ID ( MSI_CAP_ID ),\n .MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),\n .MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),\n .MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),\n .MSI_CAP_ON ( MSI_CAP_ON ),\n .MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),\n .MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),\n .MSIX_BASE_PTR ( MSIX_BASE_PTR ),\n .MSIX_CAP_ID ( MSIX_CAP_ID ),\n .MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),\n .MSIX_CAP_ON ( MSIX_CAP_ON ),\n .MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),\n .MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),\n .MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),\n .MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),\n .MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),\n .N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),\n .N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),\n .N_FTS_GEN1 ( N_FTS_GEN1 ),\n .N_FTS_GEN2 ( N_FTS_GEN2 ),\n .PCIE_BASE_PTR ( PCIE_BASE_PTR ),\n .PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),\n .PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),\n .PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),\n .PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ),\n .PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),\n .PCIE_CAP_ON ( PCIE_CAP_ON ),\n .PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),\n .PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),\n .PCIE_REVISION ( PCIE_REVISION ),\n .PGL0_LANE ( PGL0_LANE ),\n .PGL1_LANE ( PGL1_LANE ),\n .PGL2_LANE ( PGL2_LANE ),\n .PGL3_LANE ( PGL3_LANE ),\n .PGL4_LANE ( PGL4_LANE ),\n .PGL5_LANE ( PGL5_LANE ),\n .PGL6_LANE ( PGL6_LANE ),\n .PGL7_LANE ( PGL7_LANE ),\n .PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),\n .PL_FAST_TRAIN ( PL_FAST_TRAIN ),\n .PM_BASE_PTR ( PM_BASE_PTR ),\n .PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),\n .PM_CAP_DSI ( PM_CAP_DSI ),\n .PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),\n .PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),\n .PM_CAP_ID ( PM_CAP_ID ),\n .PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),\n .PM_CAP_ON ( PM_CAP_ON ),\n .PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),\n .PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),\n .PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),\n .PM_CAP_VERSION ( PM_CAP_VERSION ),\n .PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),\n .PM_CSR_B2B3 ( PM_CSR_B2B3 ),\n .PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),\n .PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),\n .PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),\n .PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),\n .PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),\n .PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),\n .PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),\n .PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),\n .PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),\n .PM_DATA0 ( PM_DATA0 ),\n .PM_DATA1 ( PM_DATA1 ),\n .PM_DATA2 ( PM_DATA2 ),\n .PM_DATA3 ( PM_DATA3 ),\n .PM_DATA4 ( PM_DATA4 ),\n .PM_DATA5 ( PM_DATA5 ),\n .PM_DATA6 ( PM_DATA6 ),\n .PM_DATA7 ( PM_DATA7 ),\n .RECRC_CHK ( RECRC_CHK ),\n .RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),\n .REVISION_ID ( REVISION_ID ),\n .ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),\n .SELECT_DLL_IF ( SELECT_DLL_IF ),\n .SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),\n .SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),\n .SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),\n .SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),\n .SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),\n .SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),\n .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),\n .SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),\n .SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),\n .SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),\n .SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),\n .SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),\n .SPARE_BIT0 ( SPARE_BIT0 ),\n .SPARE_BIT1 ( SPARE_BIT1 ),\n .SPARE_BIT2 ( SPARE_BIT2 ),\n .SPARE_BIT3 ( SPARE_BIT3 ),\n .SPARE_BIT4 ( SPARE_BIT4 ),\n .SPARE_BIT5 ( SPARE_BIT5 ),\n .SPARE_BIT6 ( SPARE_BIT6 ),\n .SPARE_BIT7 ( SPARE_BIT7 ),\n .SPARE_BIT8 ( SPARE_BIT8 ),\n .SPARE_BYTE0 ( SPARE_BYTE0 ),\n .SPARE_BYTE1 ( SPARE_BYTE1 ),\n .SPARE_BYTE2 ( SPARE_BYTE2 ),\n .SPARE_BYTE3 ( SPARE_BYTE3 ),\n .SPARE_WORD0 ( SPARE_WORD0 ),\n .SPARE_WORD1 ( SPARE_WORD1 ),\n .SPARE_WORD2 ( SPARE_WORD2 ),\n .SPARE_WORD3 ( SPARE_WORD3 ),\n .SUBSYSTEM_ID ( SUBSYSTEM_ID ),\n .SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ),\n .TL_RBYPASS ( TL_RBYPASS ),\n .TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),\n .TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),\n .TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),\n .TL_TFC_DISABLE ( TL_TFC_DISABLE ),\n .TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),\n .TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),\n .TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),\n .TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),\n .UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),\n .UPSTREAM_FACING ( UPSTREAM_FACING ),\n .EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),\n .UR_INV_REQ ( UR_INV_REQ ),\n .USER_CLK_FREQ ( USER_CLK_FREQ ),\n .VC_BASE_PTR ( VC_BASE_PTR ),\n .VC_CAP_ID ( VC_CAP_ID ),\n .VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),\n .VC_CAP_ON ( VC_CAP_ON ),\n .VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),\n .VC_CAP_VERSION ( VC_CAP_VERSION ),\n .VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),\n .VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),\n .VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),\n .VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),\n .VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),\n .VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),\n .VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),\n .VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),\n .VENDOR_ID ( VENDOR_ID ),\n .VSEC_BASE_PTR ( VSEC_BASE_PTR ),\n .VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),\n .VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),\n .VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),\n .VSEC_CAP_ID ( VSEC_CAP_ID ),\n .VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),\n .VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),\n .VSEC_CAP_ON ( VSEC_CAP_ON ),\n .VSEC_CAP_VERSION ( VSEC_CAP_VERSION )\n\n)\npcie_block_i (\n\n .CFGAERECRCCHECKEN ( CFGAERECRCCHECKEN ),\n .CFGAERECRCGENEN ( CFGAERECRCGENEN ),\n .CFGCOMMANDBUSMASTERENABLE ( CFGCOMMANDBUSMASTERENABLE ),\n .CFGCOMMANDINTERRUPTDISABLE ( CFGCOMMANDINTERRUPTDISABLE ),\n .CFGCOMMANDIOENABLE ( CFGCOMMANDIOENABLE ),\n .CFGCOMMANDMEMENABLE ( CFGCOMMANDMEMENABLE ),\n .CFGCOMMANDSERREN ( CFGCOMMANDSERREN ),\n .CFGDEVCONTROLAUXPOWEREN ( CFGDEVCONTROLAUXPOWEREN ),\n .CFGDEVCONTROLCORRERRREPORTINGEN ( CFGDEVCONTROLCORRERRREPORTINGEN ),\n .CFGDEVCONTROLENABLERO ( CFGDEVCONTROLENABLERO ),\n .CFGDEVCONTROLEXTTAGEN ( CFGDEVCONTROLEXTTAGEN ),\n .CFGDEVCONTROLFATALERRREPORTINGEN ( CFGDEVCONTROLFATALERRREPORTINGEN ),\n .CFGDEVCONTROLMAXPAYLOAD ( CFGDEVCONTROLMAXPAYLOAD ),\n .CFGDEVCONTROLMAXREADREQ ( CFGDEVCONTROLMAXREADREQ ),\n .CFGDEVCONTROLNONFATALREPORTINGEN ( CFGDEVCONTROLNONFATALREPORTINGEN ),\n .CFGDEVCONTROLNOSNOOPEN ( CFGDEVCONTROLNOSNOOPEN ),\n .CFGDEVCONTROLPHANTOMEN ( CFGDEVCONTROLPHANTOMEN ),\n .CFGDEVCONTROLURERRREPORTINGEN ( CFGDEVCONTROLURERRREPORTINGEN ),\n .CFGDEVCONTROL2CPLTIMEOUTDIS ( CFGDEVCONTROL2CPLTIMEOUTDIS ),\n .CFGDEVCONTROL2CPLTIMEOUTVAL ( CFGDEVCONTROL2CPLTIMEOUTVAL ),\n .CFGDEVSTATUSCORRERRDETECTED ( CFGDEVSTATUSCORRERRDETECTED ),\n .CFGDEVSTATUSFATALERRDETECTED ( CFGDEVSTATUSFATALERRDETECTED ),\n .CFGDEVSTATUSNONFATALERRDETECTED ( CFGDEVSTATUSNONFATALERRDETECTED ),\n .CFGDEVSTATUSURDETECTED ( CFGDEVSTATUSURDETECTED ),\n .CFGDO ( CFGDO ),\n .CFGERRAERHEADERLOGSETN ( CFGERRAERHEADERLOGSETN ),\n\n .CFGERRCPLRDYN ( CFGERRCPLRDYN ),\n .CFGINTERRUPTDO ( CFGINTERRUPTDO ),\n .CFGINTERRUPTMMENABLE ( CFGINTERRUPTMMENABLE ),\n .CFGINTERRUPTMSIENABLE ( CFGINTERRUPTMSIENABLE ),\n .CFGINTERRUPTMSIXENABLE ( CFGINTERRUPTMSIXENABLE ),\n .CFGINTERRUPTMSIXFM ( CFGINTERRUPTMSIXFM ),\n .CFGINTERRUPTRDYN ( CFGINTERRUPTRDYN ),\n .CFGLINKCONTROLRCB ( CFGLINKCONTROLRCB ),\n .CFGLINKCONTROLASPMCONTROL ( CFGLINKCONTROLASPMCONTROL ),\n .CFGLINKCONTROLAUTOBANDWIDTHINTEN ( CFGLINKCONTROLAUTOBANDWIDTHINTEN ),\n .CFGLINKCONTROLBANDWIDTHINTEN ( CFGLINKCONTROLBANDWIDTHINTEN ),\n .CFGLINKCONTROLCLOCKPMEN ( CFGLINKCONTROLCLOCKPMEN ),\n .CFGLINKCONTROLCOMMONCLOCK ( CFGLINKCONTROLCOMMONCLOCK ),\n .CFGLINKCONTROLEXTENDEDSYNC ( CFGLINKCONTROLEXTENDEDSYNC ),\n .CFGLINKCONTROLHWAUTOWIDTHDIS ( CFGLINKCONTROLHWAUTOWIDTHDIS ),\n .CFGLINKCONTROLLINKDISABLE ( CFGLINKCONTROLLINKDISABLE ),\n .CFGLINKCONTROLRETRAINLINK ( CFGLINKCONTROLRETRAINLINK ),\n .CFGLINKSTATUSAUTOBANDWIDTHSTATUS ( CFGLINKSTATUSAUTOBANDWIDTHSTATUS ),\n .CFGLINKSTATUSBANDWITHSTATUS ( CFGLINKSTATUSBANDWITHSTATUS ),\n .CFGLINKSTATUSCURRENTSPEED ( CFGLINKSTATUSCURRENTSPEED ),\n .CFGLINKSTATUSDLLACTIVE ( CFGLINKSTATUSDLLACTIVE ),\n .CFGLINKSTATUSLINKTRAINING ( CFGLINKSTATUSLINKTRAINING ),\n .CFGLINKSTATUSNEGOTIATEDWIDTH ( CFGLINKSTATUSNEGOTIATEDWIDTH ),\n .CFGMSGDATA ( CFGMSGDATA ),\n .CFGMSGRECEIVED ( CFGMSGRECEIVED ),\n\n .CFGMSGRECEIVEDASSERTINTA ( CFGMSGRECEIVEDASSERTINTA ),\n .CFGMSGRECEIVEDASSERTINTB ( CFGMSGRECEIVEDASSERTINTB ),\n .CFGMSGRECEIVEDASSERTINTC ( CFGMSGRECEIVEDASSERTINTC ),\n .CFGMSGRECEIVEDASSERTINTD ( CFGMSGRECEIVEDASSERTINTD ),\n .CFGMSGRECEIVEDDEASSERTINTA ( CFGMSGRECEIVEDDEASSERTINTA ),\n .CFGMSGRECEIVEDDEASSERTINTB ( CFGMSGRECEIVEDDEASSERTINTB ),\n .CFGMSGRECEIVEDDEASSERTINTC ( CFGMSGRECEIVEDDEASSERTINTC ),\n .CFGMSGRECEIVEDDEASSERTINTD ( CFGMSGRECEIVEDDEASSERTINTD ),\n .CFGMSGRECEIVEDERRCOR ( CFGMSGRECEIVEDERRCOR ),\n .CFGMSGRECEIVEDERRFATAL ( CFGMSGRECEIVEDERRFATAL ),\n .CFGMSGRECEIVEDERRNONFATAL ( CFGMSGRECEIVEDERRNONFATAL ),\n\n .CFGMSGRECEIVEDPMASNAK ( CFGMSGRECEIVEDPMASNAK ),\n .CFGMSGRECEIVEDPMETO ( CFGMSGRECEIVEDPMETO ),\n\n\n .CFGMSGRECEIVEDPMETOACK ( CFGMSGRECEIVEDPMETOACK ),\n .CFGMSGRECEIVEDPMPME ( CFGMSGRECEIVEDPMPME ),\n\n\n .CFGMSGRECEIVEDSETSLOTPOWERLIMIT ( CFGMSGRECEIVEDSETSLOTPOWERLIMIT ),\n .CFGMSGRECEIVEDUNLOCK ( CFGMSGRECEIVEDUNLOCK ),\n .CFGPCIELINKSTATE ( CFGPCIELINKSTATE ),\n\n\n .CFGPMRCVASREQL1N ( CFGPMRCVASREQL1N ),\n .CFGPMRCVENTERL1N ( CFGPMRCVENTERL1N ),\n .CFGPMRCVENTERL23N ( CFGPMRCVENTERL23N ),\n\n .CFGPMRCVREQACKN ( CFGPMRCVREQACKN ),\n .CFGPMCSRPMEEN( CFGPMCSRPMEEN ),\n .CFGPMCSRPMESTATUS( CFGPMCSRPMESTATUS ),\n .CFGPMCSRPOWERSTATE( CFGPMCSRPOWERSTATE ),\n .CFGRDWRDONEN ( CFGRDWRDONEN ),\n\n .CFGSLOTCONTROLELECTROMECHILCTLPULSE ( CFGSLOTCONTROLELECTROMECHILCTLPULSE ),\n\n .CFGTRANSACTION ( CFGTRANSACTION ),\n .CFGTRANSACTIONADDR ( CFGTRANSACTIONADDR ),\n .CFGTRANSACTIONTYPE ( CFGTRANSACTIONTYPE ),\n\n .CFGVCTCVCMAP ( CFGVCTCVCMAP ),\n .DBGSCLRA ( DBGSCLRA ),\n .DBGSCLRB ( DBGSCLRB ),\n .DBGSCLRC ( DBGSCLRC ),\n .DBGSCLRD ( DBGSCLRD ),\n .DBGSCLRE ( DBGSCLRE ),\n .DBGSCLRF ( DBGSCLRF ),\n .DBGSCLRG ( DBGSCLRG ),\n .DBGSCLRH ( DBGSCLRH ),\n .DBGSCLRI ( DBGSCLRI ),\n .DBGSCLRJ ( DBGSCLRJ ),\n .DBGSCLRK ( DBGSCLRK ),\n .DBGVECA ( DBGVECA ),\n .DBGVECB ( DBGVECB ),\n .DBGVECC ( DBGVECC ),\n .DRPDO ( PCIEDRPDO ),\n .DRPDRDY ( PCIEDRPDRDY ),\n .LL2BADDLLPERRN ( LL2BADDLLPERRN ),\n .LL2BADTLPERRN ( LL2BADTLPERRN ),\n .LL2PROTOCOLERRN ( LL2PROTOCOLERRN ),\n .LL2REPLAYROERRN ( LL2REPLAYROERRN ),\n .LL2REPLAYTOERRN ( LL2REPLAYTOERRN ),\n .LL2SUSPENDOKN ( LL2SUSPENDOKN ),\n .LL2TFCINIT1SEQN ( LL2TFCINIT1SEQN ),\n .LL2TFCINIT2SEQN ( LL2TFCINIT2SEQN ),\n .MIMRXRADDR ( MIMRXRADDR ),\n .MIMRXRCE ( MIMRXRCE ),\n .MIMRXREN ( MIMRXREN ),\n .MIMRXWADDR ( MIMRXWADDR ),\n .MIMRXWDATA ( MIMRXWDATA ),\n .MIMRXWEN ( MIMRXWEN ),\n .MIMTXRADDR ( MIMTXRADDR ),\n .MIMTXRCE ( MIMTXRCE ),\n .MIMTXREN ( MIMTXREN ),\n .MIMTXWADDR ( MIMTXWADDR ),\n .MIMTXWDATA ( MIMTXWDATA ),\n .MIMTXWEN ( MIMTXWEN ),\n .PIPERX0POLARITY ( PIPERX0POLARITY ),\n .PIPERX1POLARITY ( PIPERX1POLARITY ),\n .PIPERX2POLARITY ( PIPERX2POLARITY ),\n .PIPERX3POLARITY ( PIPERX3POLARITY ),\n .PIPERX4POLARITY ( PIPERX4POLARITY ),\n .PIPERX5POLARITY ( PIPERX5POLARITY ),\n .PIPERX6POLARITY ( PIPERX6POLARITY ),\n .PIPERX7POLARITY ( PIPERX7POLARITY ),\n .PIPETXDEEMPH ( PIPETXDEEMPH ),\n .PIPETXMARGIN ( PIPETXMARGIN ),\n .PIPETXRATE ( PIPETXRATE ),\n .PIPETXRCVRDET ( PIPETXRCVRDET ),\n .PIPETXRESET ( PIPETXRESET ),\n .PIPETX0CHARISK ( PIPETX0CHARISK ),\n .PIPETX0COMPLIANCE ( PIPETX0COMPLIANCE ),\n .PIPETX0DATA ( PIPETX0DATA ),\n .PIPETX0ELECIDLE ( PIPETX0ELECIDLE ),\n .PIPETX0POWERDOWN ( PIPETX0POWERDOWN ),\n .PIPETX1CHARISK ( PIPETX1CHARISK ),\n .PIPETX1COMPLIANCE ( PIPETX1COMPLIANCE ),\n .PIPETX1DATA ( PIPETX1DATA ),\n .PIPETX1ELECIDLE ( PIPETX1ELECIDLE ),\n .PIPETX1POWERDOWN ( PIPETX1POWERDOWN ),\n .PIPETX2CHARISK ( PIPETX2CHARISK ),\n .PIPETX2COMPLIANCE ( PIPETX2COMPLIANCE ),\n .PIPETX2DATA ( PIPETX2DATA ),\n .PIPETX2ELECIDLE ( PIPETX2ELECIDLE ),\n .PIPETX2POWERDOWN ( PIPETX2POWERDOWN ),\n .PIPETX3CHARISK ( PIPETX3CHARISK ),\n .PIPETX3COMPLIANCE ( PIPETX3COMPLIANCE ),\n .PIPETX3DATA ( PIPETX3DATA ),\n .PIPETX3ELECIDLE ( PIPETX3ELECIDLE ),\n .PIPETX3POWERDOWN ( PIPETX3POWERDOWN ),\n .PIPETX4CHARISK ( PIPETX4CHARISK ),\n .PIPETX4COMPLIANCE ( PIPETX4COMPLIANCE ),\n .PIPETX4DATA ( PIPETX4DATA ),\n .PIPETX4ELECIDLE ( PIPETX4ELECIDLE ),\n .PIPETX4POWERDOWN ( PIPETX4POWERDOWN ),\n .PIPETX5CHARISK ( PIPETX5CHARISK ),\n .PIPETX5COMPLIANCE ( PIPETX5COMPLIANCE ),\n .PIPETX5DATA ( PIPETX5DATA ),\n .PIPETX5ELECIDLE ( PIPETX5ELECIDLE ),\n .PIPETX5POWERDOWN ( PIPETX5POWERDOWN ),\n .PIPETX6CHARISK ( PIPETX6CHARISK ),\n .PIPETX6COMPLIANCE ( PIPETX6COMPLIANCE ),\n .PIPETX6DATA ( PIPETX6DATA ),\n .PIPETX6ELECIDLE ( PIPETX6ELECIDLE ),\n .PIPETX6POWERDOWN ( PIPETX6POWERDOWN ),\n .PIPETX7CHARISK ( PIPETX7CHARISK ),\n .PIPETX7COMPLIANCE ( PIPETX7COMPLIANCE ),\n .PIPETX7DATA ( PIPETX7DATA ),\n .PIPETX7ELECIDLE ( PIPETX7ELECIDLE ),\n .PIPETX7POWERDOWN ( PIPETX7POWERDOWN ),\n .PLDBGVEC ( PLDBGVEC ),\n .PLINITIALLINKWIDTH ( PLINITIALLINKWIDTH ),\n .PLLANEREVERSALMODE ( PLLANEREVERSALMODE ),\n .PLLINKGEN2CAP ( PLLINKGEN2CAP ),\n .PLLINKPARTNERGEN2SUPPORTED ( PLLINKPARTNERGEN2SUPPORTED ),\n .PLLINKUPCFGCAP ( PLLINKUPCFGCAP ),\n .PLLTSSMSTATE ( PLLTSSMSTATE ),\n .PLPHYLNKUPN ( PLPHYLNKUPN ),\n .PLRECEIVEDHOTRST ( PLRECEIVEDHOTRST ),\n .PLRXPMSTATE ( PLRXPMSTATE ),\n .PLSELLNKRATE ( PLSELLNKRATE ),\n .PLSELLNKWIDTH ( PLSELLNKWIDTH ),\n .PLTXPMSTATE ( PLTXPMSTATE ),\n .PL2LINKUPN ( PL2LINKUPN ),\n .PL2RECEIVERERRN ( PL2RECEIVERERRN ),\n .PL2RECOVERYN ( PL2RECOVERYN ),\n .PL2RXELECIDLE ( PL2RXELECIDLE ),\n .PL2SUSPENDOK ( PL2SUSPENDOK ),\n .RECEIVEDFUNCLVLRSTN ( RECEIVEDFUNCLVLRSTN ),\n .LNKCLKEN ( LNKCLKEN ),\n .TL2ASPMSUSPENDCREDITCHECKOKN ( TL2ASPMSUSPENDCREDITCHECKOKN ),\n .TL2ASPMSUSPENDREQN ( TL2ASPMSUSPENDREQN ),\n .TL2PPMSUSPENDOKN ( TL2PPMSUSPENDOKN ),\n .TRNFCCPLD ( TRNFCCPLD ),\n .TRNFCCPLH ( TRNFCCPLH ),\n .TRNFCNPD ( TRNFCNPD ),\n .TRNFCNPH ( TRNFCNPH ),\n .TRNFCPD ( TRNFCPD ),\n .TRNFCPH ( TRNFCPH ),\n .TRNLNKUPN ( TRNLNKUPN ),\n .TRNRBARHITN ( TRNRBARHITN ),\n .TRNRD ( TRNRD ),\n\n .TRNRDLLPDATA ( TRNRDLLPDATA ),\n .TRNRDLLPSRCRDYN ( TRNRDLLPSRCRDYN ),\n .TRNRECRCERRN ( TRNRECRCERRN ),\n .TRNREOFN ( TRNREOFN ),\n .TRNRERRFWDN ( TRNRERRFWDN ),\n .TRNRREMN ( TRNRREMN ),\n .TRNRSOFN ( TRNRSOFN ),\n .TRNRSRCDSCN ( TRNRSRCDSCN ),\n .TRNRSRCRDYN ( TRNRSRCRDYN ),\n .TRNTBUFAV ( TRNTBUFAV ),\n .TRNTCFGREQN ( TRNTCFGREQN ),\n .TRNTDLLPDSTRDYN ( TRNTDLLPDSTRDYN ),\n .TRNTDSTRDYN ( TRNTDSTRDYN ),\n .TRNTERRDROPN ( TRNTERRDROPN ),\n .USERRSTN ( USERRSTN ),\n .CFGBYTEENN ( CFGBYTEENN ),\n .CFGDI ( CFGDI ),\n .CFGDSBUSNUMBER ( CFGDSBUSNUMBER ),\n .CFGDSDEVICENUMBER ( CFGDSDEVICENUMBER ),\n .CFGDSFUNCTIONNUMBER ( CFGDSFUNCTIONNUMBER ),\n .CFGDSN ( CFGDSN ),\n .CFGDWADDR ( CFGDWADDR ),\n .CFGERRACSN ( CFGERRACSN ),\n .CFGERRAERHEADERLOG ( CFGERRAERHEADERLOG ),\n .CFGERRCORN ( CFGERRCORN ),\n .CFGERRCPLABORTN ( CFGERRCPLABORTN ),\n .CFGERRCPLTIMEOUTN ( CFGERRCPLTIMEOUTN ),\n .CFGERRCPLUNEXPECTN ( CFGERRCPLUNEXPECTN ),\n .CFGERRECRCN ( CFGERRECRCN ),\n .CFGERRLOCKEDN ( CFGERRLOCKEDN ),\n .CFGERRPOSTEDN ( CFGERRPOSTEDN ),\n .CFGERRTLPCPLHEADER ( CFGERRTLPCPLHEADER ),\n .CFGERRURN ( CFGERRURN ),\n .CFGINTERRUPTASSERTN ( CFGINTERRUPTASSERTN ),\n .CFGINTERRUPTDI ( CFGINTERRUPTDI ),\n .CFGINTERRUPTN ( CFGINTERRUPTN ),\n .CFGPMDIRECTASPML1N ( CFGPMDIRECTASPML1N ),\n .CFGPMSENDPMACKN ( CFGPMSENDPMACKN ),\n .CFGPMSENDPMETON ( CFGPMSENDPMETON ),\n .CFGPMSENDPMNAKN ( CFGPMSENDPMNAKN ),\n .CFGPMTURNOFFOKN ( CFGPMTURNOFFOKN ),\n .CFGPMWAKEN ( CFGPMWAKEN ),\n .CFGPORTNUMBER ( CFGPORTNUMBER ),\n .CFGRDENN ( CFGRDENN ),\n .CFGTRNPENDINGN ( CFGTRNPENDINGN ),\n .CFGWRENN ( CFGWRENN ),\n .CFGWRREADONLYN ( CFGWRREADONLYN ),\n .CFGWRRW1CASRWN ( CFGWRRW1CASRWN ),\n .CMRSTN ( CMRSTN ),\n .CMSTICKYRSTN ( CMSTICKYRSTN ),\n .DBGMODE ( DBGMODE ),\n .DBGSUBMODE ( DBGSUBMODE ),\n .DLRSTN ( DLRSTN ),\n .DRPCLK ( PCIEDRPCLK ),\n .DRPDADDR ( PCIEDRPDADDR ),\n .DRPDEN ( PCIEDRPDEN ),\n .DRPDI ( PCIEDRPDI ),\n .DRPDWE ( PCIEDRPDWE ),\n .FUNCLVLRSTN ( FUNCLVLRSTN ),\n .LL2SENDASREQL1N ( LL2SENDASREQL1N ),\n .LL2SENDENTERL1N ( LL2SENDENTERL1N ),\n .LL2SENDENTERL23N ( LL2SENDENTERL23N ),\n .LL2SUSPENDNOWN ( LL2SUSPENDNOWN ),\n .LL2TLPRCVN ( LL2TLPRCVN ),\n .MIMRXRDATA ( MIMRXRDATA[67:0] ),\n .MIMTXRDATA ( MIMTXRDATA[68:0] ),\n .PIPECLK ( PIPECLK ),\n .PIPERX0CHANISALIGNED ( PIPERX0CHANISALIGNED ),\n .PIPERX0CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX0CHARISK ),\n .PIPERX0DATA ( PIPERX0DATA ),\n .PIPERX0ELECIDLE ( PIPERX0ELECIDLE ),\n .PIPERX0PHYSTATUS ( PIPERX0PHYSTATUS ),\n .PIPERX0STATUS ( PIPERX0STATUS ),\n .PIPERX0VALID ( PIPERX0VALID ),\n .PIPERX1CHANISALIGNED ( PIPERX1CHANISALIGNED ),\n .PIPERX1CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX1CHARISK ),\n .PIPERX1DATA ( PIPERX1DATA ),\n .PIPERX1ELECIDLE ( PIPERX1ELECIDLE ),\n .PIPERX1PHYSTATUS ( PIPERX1PHYSTATUS ),\n .PIPERX1STATUS ( PIPERX1STATUS ),\n .PIPERX1VALID ( PIPERX1VALID ),\n .PIPERX2CHANISALIGNED ( PIPERX2CHANISALIGNED ),\n .PIPERX2CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX2CHARISK ),\n .PIPERX2DATA ( PIPERX2DATA ),\n .PIPERX2ELECIDLE ( PIPERX2ELECIDLE ),\n .PIPERX2PHYSTATUS ( PIPERX2PHYSTATUS ),\n .PIPERX2STATUS ( PIPERX2STATUS ),\n .PIPERX2VALID ( PIPERX2VALID ),\n .PIPERX3CHANISALIGNED ( PIPERX3CHANISALIGNED ),\n .PIPERX3CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX3CHARISK ),\n .PIPERX3DATA ( PIPERX3DATA ),\n .PIPERX3ELECIDLE ( PIPERX3ELECIDLE ),\n .PIPERX3PHYSTATUS ( PIPERX3PHYSTATUS ),\n .PIPERX3STATUS ( PIPERX3STATUS ),\n .PIPERX3VALID ( PIPERX3VALID ),\n .PIPERX4CHANISALIGNED ( PIPERX4CHANISALIGNED ),\n .PIPERX4CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX4CHARISK ),\n .PIPERX4DATA ( PIPERX4DATA ),\n .PIPERX4ELECIDLE ( PIPERX4ELECIDLE ),\n .PIPERX4PHYSTATUS ( PIPERX4PHYSTATUS ),\n .PIPERX4STATUS ( PIPERX4STATUS ),\n .PIPERX4VALID ( PIPERX4VALID ),\n .PIPERX5CHANISALIGNED ( PIPERX5CHANISALIGNED ),\n .PIPERX5CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX5CHARISK ),\n .PIPERX5DATA ( PIPERX5DATA ),\n .PIPERX5ELECIDLE ( PIPERX5ELECIDLE ),\n .PIPERX5PHYSTATUS ( PIPERX5PHYSTATUS ),\n .PIPERX5STATUS ( PIPERX5STATUS ),\n .PIPERX5VALID ( PIPERX5VALID ),\n .PIPERX6CHANISALIGNED ( PIPERX6CHANISALIGNED ),\n .PIPERX6CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX6CHARISK ),\n .PIPERX6DATA ( PIPERX6DATA ),\n .PIPERX6ELECIDLE ( PIPERX6ELECIDLE ),\n .PIPERX6PHYSTATUS ( PIPERX6PHYSTATUS ),\n .PIPERX6STATUS ( PIPERX6STATUS ),\n .PIPERX6VALID ( PIPERX6VALID ),\n .PIPERX7CHANISALIGNED ( PIPERX7CHANISALIGNED ),\n .PIPERX7CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX7CHARISK ),\n .PIPERX7DATA ( PIPERX7DATA ),\n .PIPERX7ELECIDLE ( PIPERX7ELECIDLE ),\n .PIPERX7PHYSTATUS ( PIPERX7PHYSTATUS ),\n .PIPERX7STATUS ( PIPERX7STATUS ),\n .PIPERX7VALID ( PIPERX7VALID ),\n .PLDBGMODE ( PLDBGMODE ),\n .PLDIRECTEDLINKAUTON ( PLDIRECTEDLINKAUTON ),\n .PLDIRECTEDLINKCHANGE ( PLDIRECTEDLINKCHANGE ),\n .PLDIRECTEDLINKSPEED ( PLDIRECTEDLINKSPEED ),\n .PLDIRECTEDLINKWIDTH ( PLDIRECTEDLINKWIDTH ),\n .PLDOWNSTREAMDEEMPHSOURCE ( PLDOWNSTREAMDEEMPHSOURCE ),\n .PLRSTN ( PLRSTN ),\n .PLTRANSMITHOTRST ( PLTRANSMITHOTRST ),\n .PLUPSTREAMPREFERDEEMPH ( PLUPSTREAMPREFERDEEMPH ),\n .PL2DIRECTEDLSTATE ( PL2DIRECTEDLSTATE ),\n .SYSRSTN ( SYSRSTN ),\n .TLRSTN ( TLRSTN ),\n .TL2ASPMSUSPENDCREDITCHECKN ( 1'b1),\n .TL2PPMSUSPENDREQN ( 1'b1 ),\n .TRNFCSEL ( TRNFCSEL ),\n .TRNRDSTRDYN ( TRNRDSTRDYN ),\n .TRNRNPOKN ( TRNRNPOKN ),\n .TRNTCFGGNTN ( TRNTCFGGNTN ),\n .TRNTD ( TRNTD ),\n .TRNTDLLPDATA ( TRNTDLLPDATA ),\n .TRNTDLLPSRCRDYN ( TRNTDLLPSRCRDYN ),\n .TRNTECRCGENN ( TRNTECRCGENN ),\n .TRNTEOFN ( TRNTEOFN ),\n .TRNTERRFWDN ( TRNTERRFWDN ),\n .TRNTREMN ( TRNTREMN ),\n .TRNTSOFN ( TRNTSOFN ),\n .TRNTSRCDSCN ( TRNTSRCDSCN ),\n .TRNTSRCRDYN ( TRNTSRCRDYN ),\n .TRNTSTRN ( TRNTSTRN ),\n .USERCLK ( USERCLK )\n\n);\n\n//-------------------------------------------------------\n// Virtex6 PIPE Module\n//-------------------------------------------------------\n\npcie_pipe_v6 # (\n\n .NO_OF_LANES(LINK_CAP_MAX_LINK_WIDTH),\n .LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),\n .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)\n\n)\npcie_pipe_i (\n\n // Pipe Per-Link Signals\n .pipe_tx_rcvr_det_i (PIPETXRCVRDET),\n .pipe_tx_reset_i (PIPETXRESET),\n .pipe_tx_rate_i (PIPETXRATE),\n .pipe_tx_deemph_i (PIPETXDEEMPH),\n .pipe_tx_margin_i (PIPETXMARGIN),\n .pipe_tx_swing_i (1'b0),\n\n .pipe_tx_rcvr_det_o (PIPETXRCVRDETGT),\n .pipe_tx_reset_o ( ),\n .pipe_tx_rate_o (PIPETXRATEGT),\n .pipe_tx_deemph_o (PIPETXDEEMPHGT),\n .pipe_tx_margin_o (PIPETXMARGINGT),\n .pipe_tx_swing_o ( ),\n\n // Pipe Per-Lane Signals - Lane 0\n .pipe_rx0_char_is_k_o (PIPERX0CHARISK ),\n .pipe_rx0_data_o (PIPERX0DATA ),\n .pipe_rx0_valid_o (PIPERX0VALID ),\n .pipe_rx0_chanisaligned_o (PIPERX0CHANISALIGNED ),\n .pipe_rx0_status_o (PIPERX0STATUS ),\n .pipe_rx0_phy_status_o (PIPERX0PHYSTATUS ),\n .pipe_rx0_elec_idle_i (PIPERX0ELECIDLEGT ),\n .pipe_rx0_polarity_i (PIPERX0POLARITY ),\n .pipe_tx0_compliance_i (PIPETX0COMPLIANCE ),\n .pipe_tx0_char_is_k_i (PIPETX0CHARISK ),\n .pipe_tx0_data_i (PIPETX0DATA ),\n .pipe_tx0_elec_idle_i (PIPETX0ELECIDLE ),\n .pipe_tx0_powerdown_i (PIPETX0POWERDOWN ),\n\n .pipe_rx0_char_is_k_i (PIPERX0CHARISKGT ),\n .pipe_rx0_data_i (PIPERX0DATAGT ),\n .pipe_rx0_valid_i (PIPERX0VALIDGT ),\n .pipe_rx0_chanisaligned_i (PIPERX0CHANISALIGNEDGT ),\n .pipe_rx0_status_i (PIPERX0STATUSGT ),\n .pipe_rx0_phy_status_i (PIPERX0PHYSTATUSGT ),\n .pipe_rx0_elec_idle_o (PIPERX0ELECIDLE ),\n .pipe_rx0_polarity_o (PIPERX0POLARITYGT ),\n .pipe_tx0_compliance_o (PIPETX0COMPLIANCEGT ),\n .pipe_tx0_char_is_k_o (PIPETX0CHARISKGT ),\n .pipe_tx0_data_o (PIPETX0DATAGT ),\n .pipe_tx0_elec_idle_o (PIPETX0ELECIDLEGT ),\n .pipe_tx0_powerdown_o (PIPETX0POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 1\n .pipe_rx1_char_is_k_o (PIPERX1CHARISK ),\n .pipe_rx1_data_o (PIPERX1DATA ),\n .pipe_rx1_valid_o (PIPERX1VALID ),\n .pipe_rx1_chanisaligned_o (PIPERX1CHANISALIGNED ),\n .pipe_rx1_status_o (PIPERX1STATUS ),\n .pipe_rx1_phy_status_o (PIPERX1PHYSTATUS ),\n .pipe_rx1_elec_idle_i (PIPERX1ELECIDLEGT ),\n .pipe_rx1_polarity_i (PIPERX1POLARITY ),\n .pipe_tx1_compliance_i (PIPETX1COMPLIANCE ),\n .pipe_tx1_char_is_k_i (PIPETX1CHARISK ),\n .pipe_tx1_data_i (PIPETX1DATA ),\n .pipe_tx1_elec_idle_i (PIPETX1ELECIDLE ),\n .pipe_tx1_powerdown_i (PIPETX1POWERDOWN ),\n\n .pipe_rx1_char_is_k_i (PIPERX1CHARISKGT ),\n .pipe_rx1_data_i (PIPERX1DATAGT ),\n .pipe_rx1_valid_i (PIPERX1VALIDGT ),\n .pipe_rx1_chanisaligned_i (PIPERX1CHANISALIGNEDGT ),\n .pipe_rx1_status_i (PIPERX1STATUSGT ),\n .pipe_rx1_phy_status_i (PIPERX1PHYSTATUSGT ),\n .pipe_rx1_elec_idle_o (PIPERX1ELECIDLE ),\n .pipe_rx1_polarity_o (PIPERX1POLARITYGT ),\n .pipe_tx1_compliance_o (PIPETX1COMPLIANCEGT ),\n .pipe_tx1_char_is_k_o (PIPETX1CHARISKGT ),\n .pipe_tx1_data_o (PIPETX1DATAGT ),\n .pipe_tx1_elec_idle_o (PIPETX1ELECIDLEGT ),\n .pipe_tx1_powerdown_o (PIPETX1POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 2\n .pipe_rx2_char_is_k_o (PIPERX2CHARISK ),\n .pipe_rx2_data_o (PIPERX2DATA ),\n .pipe_rx2_valid_o (PIPERX2VALID ),\n .pipe_rx2_chanisaligned_o (PIPERX2CHANISALIGNED ),\n .pipe_rx2_status_o (PIPERX2STATUS ),\n .pipe_rx2_phy_status_o (PIPERX2PHYSTATUS ),\n .pipe_rx2_elec_idle_i (PIPERX2ELECIDLEGT ),\n .pipe_rx2_polarity_i (PIPERX2POLARITY ),\n .pipe_tx2_compliance_i (PIPETX2COMPLIANCE ),\n .pipe_tx2_char_is_k_i (PIPETX2CHARISK ),\n .pipe_tx2_data_i (PIPETX2DATA ),\n .pipe_tx2_elec_idle_i (PIPETX2ELECIDLE ),\n .pipe_tx2_powerdown_i (PIPETX2POWERDOWN ),\n\n .pipe_rx2_char_is_k_i (PIPERX2CHARISKGT ),\n .pipe_rx2_data_i (PIPERX2DATAGT ),\n .pipe_rx2_valid_i (PIPERX2VALIDGT ),\n .pipe_rx2_chanisaligned_i (PIPERX2CHANISALIGNEDGT ),\n .pipe_rx2_status_i (PIPERX2STATUSGT ),\n .pipe_rx2_phy_status_i (PIPERX2PHYSTATUSGT ),\n .pipe_rx2_elec_idle_o (PIPERX2ELECIDLE ),\n .pipe_rx2_polarity_o (PIPERX2POLARITYGT ),\n .pipe_tx2_compliance_o (PIPETX2COMPLIANCEGT ),\n .pipe_tx2_char_is_k_o (PIPETX2CHARISKGT ),\n .pipe_tx2_data_o (PIPETX2DATAGT ),\n .pipe_tx2_elec_idle_o (PIPETX2ELECIDLEGT ),\n .pipe_tx2_powerdown_o (PIPETX2POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 3\n .pipe_rx3_char_is_k_o (PIPERX3CHARISK ),\n .pipe_rx3_data_o (PIPERX3DATA ),\n .pipe_rx3_valid_o (PIPERX3VALID ),\n .pipe_rx3_chanisaligned_o (PIPERX3CHANISALIGNED ),\n .pipe_rx3_status_o (PIPERX3STATUS ),\n .pipe_rx3_phy_status_o (PIPERX3PHYSTATUS ),\n .pipe_rx3_elec_idle_i (PIPERX3ELECIDLEGT ),\n .pipe_rx3_polarity_i (PIPERX3POLARITY ),\n .pipe_tx3_compliance_i (PIPETX3COMPLIANCE ),\n .pipe_tx3_char_is_k_i (PIPETX3CHARISK ),\n .pipe_tx3_data_i (PIPETX3DATA ),\n .pipe_tx3_elec_idle_i (PIPETX3ELECIDLE ),\n .pipe_tx3_powerdown_i (PIPETX3POWERDOWN ),\n\n .pipe_rx3_char_is_k_i (PIPERX3CHARISKGT ),\n .pipe_rx3_data_i (PIPERX3DATAGT ),\n .pipe_rx3_valid_i (PIPERX3VALIDGT ),\n .pipe_rx3_chanisaligned_i (PIPERX3CHANISALIGNEDGT ),\n .pipe_rx3_status_i (PIPERX3STATUSGT ),\n .pipe_rx3_phy_status_i (PIPERX3PHYSTATUSGT ),\n .pipe_rx3_elec_idle_o (PIPERX3ELECIDLE ),\n .pipe_rx3_polarity_o (PIPERX3POLARITYGT ),\n .pipe_tx3_compliance_o (PIPETX3COMPLIANCEGT ),\n .pipe_tx3_char_is_k_o (PIPETX3CHARISKGT ),\n .pipe_tx3_data_o (PIPETX3DATAGT ),\n .pipe_tx3_elec_idle_o (PIPETX3ELECIDLEGT ),\n .pipe_tx3_powerdown_o (PIPETX3POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 4\n .pipe_rx4_char_is_k_o (PIPERX4CHARISK ),\n .pipe_rx4_data_o (PIPERX4DATA ),\n .pipe_rx4_valid_o (PIPERX4VALID ),\n .pipe_rx4_chanisaligned_o (PIPERX4CHANISALIGNED ),\n .pipe_rx4_status_o (PIPERX4STATUS ),\n .pipe_rx4_phy_status_o (PIPERX4PHYSTATUS ),\n .pipe_rx4_elec_idle_i (PIPERX4ELECIDLEGT ),\n .pipe_rx4_polarity_i (PIPERX4POLARITY ),\n .pipe_tx4_compliance_i (PIPETX4COMPLIANCE ),\n .pipe_tx4_char_is_k_i (PIPETX4CHARISK ),\n .pipe_tx4_data_i (PIPETX4DATA ),\n .pipe_tx4_elec_idle_i (PIPETX4ELECIDLE ),\n .pipe_tx4_powerdown_i (PIPETX4POWERDOWN ),\n\n .pipe_rx4_char_is_k_i (PIPERX4CHARISKGT ),\n .pipe_rx4_data_i (PIPERX4DATAGT ),\n .pipe_rx4_valid_i (PIPERX4VALIDGT ),\n .pipe_rx4_chanisaligned_i (PIPERX4CHANISALIGNEDGT ),\n .pipe_rx4_status_i (PIPERX4STATUSGT ),\n .pipe_rx4_phy_status_i (PIPERX4PHYSTATUSGT ),\n .pipe_rx4_elec_idle_o (PIPERX4ELECIDLE ),\n .pipe_rx4_polarity_o (PIPERX4POLARITYGT ),\n .pipe_tx4_compliance_o (PIPETX4COMPLIANCEGT ),\n .pipe_tx4_char_is_k_o (PIPETX4CHARISKGT ),\n .pipe_tx4_data_o (PIPETX4DATAGT ),\n .pipe_tx4_elec_idle_o (PIPETX4ELECIDLEGT ),\n .pipe_tx4_powerdown_o (PIPETX4POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 5\n .pipe_rx5_char_is_k_o (PIPERX5CHARISK ),\n .pipe_rx5_data_o (PIPERX5DATA ),\n .pipe_rx5_valid_o (PIPERX5VALID ),\n .pipe_rx5_chanisaligned_o (PIPERX5CHANISALIGNED ),\n .pipe_rx5_status_o (PIPERX5STATUS ),\n .pipe_rx5_phy_status_o (PIPERX5PHYSTATUS ),\n .pipe_rx5_elec_idle_i (PIPERX5ELECIDLEGT ),\n .pipe_rx5_polarity_i (PIPERX5POLARITY ),\n .pipe_tx5_compliance_i (PIPETX5COMPLIANCE ),\n .pipe_tx5_char_is_k_i (PIPETX5CHARISK ),\n .pipe_tx5_data_i (PIPETX5DATA ),\n .pipe_tx5_elec_idle_i (PIPETX5ELECIDLE ),\n .pipe_tx5_powerdown_i (PIPETX5POWERDOWN ),\n\n .pipe_rx5_char_is_k_i (PIPERX5CHARISKGT ),\n .pipe_rx5_data_i (PIPERX5DATAGT ),\n .pipe_rx5_valid_i (PIPERX5VALIDGT ),\n .pipe_rx5_chanisaligned_i (PIPERX5CHANISALIGNEDGT ),\n .pipe_rx5_status_i (PIPERX5STATUSGT ),\n .pipe_rx5_phy_status_i (PIPERX5PHYSTATUSGT ),\n .pipe_rx5_elec_idle_o (PIPERX5ELECIDLE ),\n .pipe_rx5_polarity_o (PIPERX5POLARITYGT ),\n .pipe_tx5_compliance_o (PIPETX5COMPLIANCEGT ),\n .pipe_tx5_char_is_k_o (PIPETX5CHARISKGT ),\n .pipe_tx5_data_o (PIPETX5DATAGT ),\n .pipe_tx5_elec_idle_o (PIPETX5ELECIDLEGT ),\n .pipe_tx5_powerdown_o (PIPETX5POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 6\n .pipe_rx6_char_is_k_o (PIPERX6CHARISK ),\n .pipe_rx6_data_o (PIPERX6DATA ),\n .pipe_rx6_valid_o (PIPERX6VALID ),\n .pipe_rx6_chanisaligned_o (PIPERX6CHANISALIGNED ),\n .pipe_rx6_status_o (PIPERX6STATUS ),\n .pipe_rx6_phy_status_o (PIPERX6PHYSTATUS ),\n .pipe_rx6_elec_idle_i (PIPERX6ELECIDLEGT ),\n .pipe_rx6_polarity_i (PIPERX6POLARITY ),\n .pipe_tx6_compliance_i (PIPETX6COMPLIANCE ),\n .pipe_tx6_char_is_k_i (PIPETX6CHARISK ),\n .pipe_tx6_data_i (PIPETX6DATA ),\n .pipe_tx6_elec_idle_i (PIPETX6ELECIDLE ),\n .pipe_tx6_powerdown_i (PIPETX6POWERDOWN ),\n\n .pipe_rx6_char_is_k_i (PIPERX6CHARISKGT ),\n .pipe_rx6_data_i (PIPERX6DATAGT ),\n .pipe_rx6_valid_i (PIPERX6VALIDGT ),\n .pipe_rx6_chanisaligned_i (PIPERX6CHANISALIGNEDGT ),\n .pipe_rx6_status_i (PIPERX6STATUSGT ),\n .pipe_rx6_phy_status_i (PIPERX6PHYSTATUSGT ),\n .pipe_rx6_elec_idle_o (PIPERX6ELECIDLE ),\n .pipe_rx6_polarity_o (PIPERX6POLARITYGT ),\n .pipe_tx6_compliance_o (PIPETX6COMPLIANCEGT ),\n .pipe_tx6_char_is_k_o (PIPETX6CHARISKGT ),\n .pipe_tx6_data_o (PIPETX6DATAGT ),\n .pipe_tx6_elec_idle_o (PIPETX6ELECIDLEGT ),\n .pipe_tx6_powerdown_o (PIPETX6POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 7\n .pipe_rx7_char_is_k_o (PIPERX7CHARISK ),\n .pipe_rx7_data_o (PIPERX7DATA ),\n .pipe_rx7_valid_o (PIPERX7VALID ),\n .pipe_rx7_chanisaligned_o (PIPERX7CHANISALIGNED ),\n .pipe_rx7_status_o (PIPERX7STATUS ),\n .pipe_rx7_phy_status_o (PIPERX7PHYSTATUS ),\n .pipe_rx7_elec_idle_i (PIPERX7ELECIDLEGT ),\n .pipe_rx7_polarity_i (PIPERX7POLARITY ),\n .pipe_tx7_compliance_i (PIPETX7COMPLIANCE ),\n .pipe_tx7_char_is_k_i (PIPETX7CHARISK ),\n .pipe_tx7_data_i (PIPETX7DATA ),\n .pipe_tx7_elec_idle_i (PIPETX7ELECIDLE ),\n .pipe_tx7_powerdown_i (PIPETX7POWERDOWN ),\n\n .pipe_rx7_char_is_k_i (PIPERX7CHARISKGT ),\n .pipe_rx7_data_i (PIPERX7DATAGT ),\n .pipe_rx7_valid_i (PIPERX7VALIDGT ),\n .pipe_rx7_chanisaligned_i (PIPERX7CHANISALIGNEDGT ),\n .pipe_rx7_status_i (PIPERX7STATUSGT ),\n .pipe_rx7_phy_status_i (PIPERX7PHYSTATUSGT ),\n .pipe_rx7_elec_idle_o (PIPERX7ELECIDLE ),\n .pipe_rx7_polarity_o (PIPERX7POLARITYGT ),\n .pipe_tx7_compliance_o (PIPETX7COMPLIANCEGT ),\n .pipe_tx7_char_is_k_o (PIPETX7CHARISKGT ),\n .pipe_tx7_data_o (PIPETX7DATAGT ),\n .pipe_tx7_elec_idle_o (PIPETX7ELECIDLEGT ),\n .pipe_tx7_powerdown_o (PIPETX7POWERDOWNGT ),\n\n // Non PIPE signals\n .pl_ltssm_state (PLLTSSMSTATE ),\n .pipe_clk (PIPECLK ),\n .rst_n (PHYRDYN )\n);\n\n//-------------------------------------------------------\n// Virtex6 GTX Module\n//-------------------------------------------------------\n\npcie_gtx_v6 #(\n\n .NO_OF_LANES(LINK_CAP_MAX_LINK_WIDTH),\n .LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),\n .REF_CLK_FREQ(REF_CLK_FREQ),\n .PL_FAST_TRAIN(PL_FAST_TRAIN)\n\n)\npcie_gt_i (\n\n // Pipe Common Signals\n .pipe_tx_rcvr_det (PIPETXRCVRDETGT ),\n .pipe_tx_reset (1'b0 ),\n .pipe_tx_rate (PIPETXRATEGT ),\n .pipe_tx_deemph (PIPETXDEEMPHGT ),\n .pipe_tx_margin (PIPETXMARGINGT ),\n .pipe_tx_swing (1'b0),\n\n // Pipe Per-Lane Signals - Lane 0\n .pipe_rx0_char_is_k (PIPERX0CHARISKGT ),\n .pipe_rx0_data (PIPERX0DATAGT ),\n .pipe_rx0_valid (PIPERX0VALIDGT ),\n .pipe_rx0_chanisaligned (PIPERX0CHANISALIGNEDGT ),\n .pipe_rx0_status (PIPERX0STATUSGT ),\n .pipe_rx0_phy_status (PIPERX0PHYSTATUSGT ),\n .pipe_rx0_elec_idle (PIPERX0ELECIDLEGT ),\n .pipe_rx0_polarity (PIPERX0POLARITYGT ),\n .pipe_tx0_compliance (PIPETX0COMPLIANCEGT ),\n .pipe_tx0_char_is_k (PIPETX0CHARISKGT ),\n .pipe_tx0_data (PIPETX0DATAGT ),\n .pipe_tx0_elec_idle (PIPETX0ELECIDLEGT ),\n .pipe_tx0_powerdown (PIPETX0POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 1\n .pipe_rx1_char_is_k (PIPERX1CHARISKGT ),\n .pipe_rx1_data (PIPERX1DATAGT ),\n .pipe_rx1_valid (PIPERX1VALIDGT ),\n .pipe_rx1_chanisaligned (PIPERX1CHANISALIGNEDGT ),\n .pipe_rx1_status (PIPERX1STATUSGT ),\n .pipe_rx1_phy_status (PIPERX1PHYSTATUSGT ),\n .pipe_rx1_elec_idle (PIPERX1ELECIDLEGT ),\n .pipe_rx1_polarity (PIPERX1POLARITYGT ),\n .pipe_tx1_compliance (PIPETX1COMPLIANCEGT ),\n .pipe_tx1_char_is_k (PIPETX1CHARISKGT ),\n .pipe_tx1_data (PIPETX1DATAGT ),\n .pipe_tx1_elec_idle (PIPETX1ELECIDLEGT ),\n .pipe_tx1_powerdown (PIPETX1POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 2\n .pipe_rx2_char_is_k (PIPERX2CHARISKGT ),\n .pipe_rx2_data (PIPERX2DATAGT ),\n .pipe_rx2_valid (PIPERX2VALIDGT ),\n .pipe_rx2_chanisaligned (PIPERX2CHANISALIGNEDGT ),\n .pipe_rx2_status (PIPERX2STATUSGT ),\n .pipe_rx2_phy_status (PIPERX2PHYSTATUSGT ),\n .pipe_rx2_elec_idle (PIPERX2ELECIDLEGT ),\n .pipe_rx2_polarity (PIPERX2POLARITYGT ),\n .pipe_tx2_compliance (PIPETX2COMPLIANCEGT ),\n .pipe_tx2_char_is_k (PIPETX2CHARISKGT ),\n .pipe_tx2_data (PIPETX2DATAGT ),\n .pipe_tx2_elec_idle (PIPETX2ELECIDLEGT ),\n .pipe_tx2_powerdown (PIPETX2POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 3\n .pipe_rx3_char_is_k (PIPERX3CHARISKGT ),\n .pipe_rx3_data (PIPERX3DATAGT ),\n .pipe_rx3_valid (PIPERX3VALIDGT ),\n .pipe_rx3_chanisaligned (PIPERX3CHANISALIGNEDGT ),\n .pipe_rx3_status (PIPERX3STATUSGT ),\n .pipe_rx3_phy_status (PIPERX3PHYSTATUSGT ),\n .pipe_rx3_elec_idle (PIPERX3ELECIDLEGT ),\n .pipe_rx3_polarity (PIPERX3POLARITYGT ),\n .pipe_tx3_compliance (PIPETX3COMPLIANCEGT ),\n .pipe_tx3_char_is_k (PIPETX3CHARISKGT ),\n .pipe_tx3_data (PIPETX3DATAGT ),\n .pipe_tx3_elec_idle (PIPETX3ELECIDLEGT ),\n .pipe_tx3_powerdown (PIPETX3POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 4\n .pipe_rx4_char_is_k (PIPERX4CHARISKGT ),\n .pipe_rx4_data (PIPERX4DATAGT ),\n .pipe_rx4_valid (PIPERX4VALIDGT ),\n .pipe_rx4_chanisaligned (PIPERX4CHANISALIGNEDGT ),\n .pipe_rx4_status (PIPERX4STATUSGT ),\n .pipe_rx4_phy_status (PIPERX4PHYSTATUSGT ),\n .pipe_rx4_elec_idle (PIPERX4ELECIDLEGT ),\n .pipe_rx4_polarity (PIPERX4POLARITYGT ),\n .pipe_tx4_compliance (PIPETX4COMPLIANCEGT ),\n .pipe_tx4_char_is_k (PIPETX4CHARISKGT ),\n .pipe_tx4_data (PIPETX4DATAGT ),\n .pipe_tx4_elec_idle (PIPETX4ELECIDLEGT ),\n .pipe_tx4_powerdown (PIPETX4POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 5\n .pipe_rx5_char_is_k (PIPERX5CHARISKGT ),\n .pipe_rx5_data (PIPERX5DATAGT ),\n .pipe_rx5_valid (PIPERX5VALIDGT ),\n .pipe_rx5_chanisaligned (PIPERX5CHANISALIGNEDGT ),\n .pipe_rx5_status (PIPERX5STATUSGT ),\n .pipe_rx5_phy_status (PIPERX5PHYSTATUSGT ),\n .pipe_rx5_elec_idle (PIPERX5ELECIDLEGT ),\n .pipe_rx5_polarity (PIPERX5POLARITYGT ),\n .pipe_tx5_compliance (PIPETX5COMPLIANCEGT ),\n .pipe_tx5_char_is_k (PIPETX5CHARISKGT ),\n .pipe_tx5_data (PIPETX5DATAGT ),\n .pipe_tx5_elec_idle (PIPETX5ELECIDLEGT ),\n .pipe_tx5_powerdown (PIPETX5POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 6\n .pipe_rx6_char_is_k (PIPERX6CHARISKGT ),\n .pipe_rx6_data (PIPERX6DATAGT ),\n .pipe_rx6_valid (PIPERX6VALIDGT ),\n .pipe_rx6_chanisaligned (PIPERX6CHANISALIGNEDGT ),\n .pipe_rx6_status (PIPERX6STATUSGT ),\n .pipe_rx6_phy_status (PIPERX6PHYSTATUSGT ),\n .pipe_rx6_elec_idle (PIPERX6ELECIDLEGT ),\n .pipe_rx6_polarity (PIPERX6POLARITYGT ),\n .pipe_tx6_compliance (PIPETX6COMPLIANCEGT ),\n .pipe_tx6_char_is_k (PIPETX6CHARISKGT ),\n .pipe_tx6_data (PIPETX6DATAGT ),\n .pipe_tx6_elec_idle (PIPETX6ELECIDLEGT ),\n .pipe_tx6_powerdown (PIPETX6POWERDOWNGT ),\n\n // Pipe Per-Lane Signals - Lane 7\n .pipe_rx7_char_is_k (PIPERX7CHARISKGT ),\n .pipe_rx7_data (PIPERX7DATAGT ),\n .pipe_rx7_valid (PIPERX7VALIDGT ),\n .pipe_rx7_chanisaligned (PIPERX7CHANISALIGNEDGT ),\n .pipe_rx7_status (PIPERX7STATUSGT ),\n .pipe_rx7_phy_status (PIPERX7PHYSTATUSGT ),\n .pipe_rx7_elec_idle (PIPERX7ELECIDLEGT ),\n .pipe_rx7_polarity (PIPERX7POLARITYGT ),\n .pipe_tx7_compliance (PIPETX7COMPLIANCEGT ),\n .pipe_tx7_char_is_k (PIPETX7CHARISKGT ),\n .pipe_tx7_data (PIPETX7DATAGT ),\n .pipe_tx7_elec_idle (PIPETX7ELECIDLEGT ),\n .pipe_tx7_powerdown (PIPETX7POWERDOWNGT ),\n\n // PCI Express Signals\n .pci_exp_txn (PCIEXPTXN ),\n .pci_exp_txp (PCIEXPTXP ),\n .pci_exp_rxn (PCIEXPRXN ),\n .pci_exp_rxp (PCIEXPRXP ),\n\n // Non PIPE Signals\n .sys_clk (SYSCLK ),\n .sys_rst_n (FUNDRSTN ),\n .pipe_clk (PIPECLK ),\n .drp_clk (DRPCLK ),\n .clock_locked (CLOCKLOCKED ),\n .pl_ltssm_state (PLLTSSMSTATE ),\n\n .gt_pll_lock (GTPLLLOCK ),\n .phy_rdy_n (PHYRDYN ),\n .TxOutClk (TxOutClk )\n\n);\n\n//-------------------------------------------------------\n// PCI Express BRAM Module\n//-------------------------------------------------------\n\npcie_bram_top_v6 #(\n\n .DEV_CAP_MAX_PAYLOAD_SUPPORTED(DEV_CAP_MAX_PAYLOAD_SUPPORTED),\n\n .VC0_TX_LASTPACKET(VC0_TX_LASTPACKET),\n .TL_TX_RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),\n .TL_TX_RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),\n .TL_TX_RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY),\n\n .VC0_RX_LIMIT(VC0_RX_RAM_LIMIT),\n .TL_RX_RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),\n .TL_RX_RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),\n .TL_RX_RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY)\n\n)\npcie_bram_i (\n\n .user_clk_i( USERCLK ),\n .reset_i( PHYRDYN ),\n\n .mim_tx_waddr( MIMTXWADDR ),\n .mim_tx_wen( MIMTXWEN ),\n .mim_tx_ren( MIMTXREN ),\n .mim_tx_rce( MIMTXRCE ),\n .mim_tx_wdata( {3'b0, MIMTXWDATA} ),\n .mim_tx_raddr( MIMTXRADDR ),\n .mim_tx_rdata( MIMTXRDATA ),\n\n .mim_rx_waddr( MIMRXWADDR ),\n .mim_rx_wen( MIMRXWEN ),\n .mim_rx_ren( MIMRXREN ),\n .mim_rx_rce( MIMRXRCE ),\n .mim_rx_wdata( {4'h0, MIMRXWDATA} ),\n .mim_rx_raddr( MIMRXRADDR ),\n .mim_rx_rdata( MIMRXRDATA )\n\n);\n\n\n//-------------------------------------------------------\n// PCI Express Port Workarounds\n//-------------------------------------------------------\n\npcie_upconfig_fix_3451_v6 # (\n\n .UPSTREAM_FACING ( UPSTREAM_FACING ),\n .PL_FAST_TRAIN ( PL_FAST_TRAIN ),\n .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH )\n\n)\npcie_upconfig_fix_3451_v6_i (\n\n .pipe_clk(PIPECLK),\n .pl_phy_lnkup_n(PLPHYLNKUPN),\n\n .pl_ltssm_state(PLLTSSMSTATE),\n .pl_sel_lnk_rate(PLSELLNKRATE),\n .pl_directed_link_change(PLDIRECTEDLINKCHANGE),\n\n .cfg_link_status_negotiated_width(CFGLINKSTATUSNEGOTIATEDWIDTH),\n .pipe_rx0_data(PIPERX0DATAGT[15:0]),\n .pipe_rx0_char_isk(PIPERX0CHARISKGT[1:0]),\n\n .filter_pipe(filter_pipe_upconfig_fix_3451)\n\n);\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/pcie_bram_top_v6.v", "content": "\n//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : pcie_bram_top_v6.v\n// Version : 2.4\n//--\n//-- Description: BlockRAM top level module for Virtex6 PCIe Block\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns/1ns\n\nmodule pcie_bram_top_v6\n#(\n parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0,\n\n parameter VC0_TX_LASTPACKET = 31,\n parameter TLM_TX_OVERHEAD = 24,\n parameter TL_TX_RAM_RADDR_LATENCY = 1,\n parameter TL_TX_RAM_RDATA_LATENCY = 2,\n parameter TL_TX_RAM_WRITE_LATENCY = 1,\n\n parameter VC0_RX_LIMIT = 'h1FFF,\n parameter TL_RX_RAM_RADDR_LATENCY = 1,\n parameter TL_RX_RAM_RDATA_LATENCY = 2,\n parameter TL_RX_RAM_WRITE_LATENCY = 1\n)\n (\n input user_clk_i,\n input reset_i,\n\n input mim_tx_wen,\n input [12:0] mim_tx_waddr,\n input [71:0] mim_tx_wdata,\n input mim_tx_ren,\n input mim_tx_rce,\n input [12:0] mim_tx_raddr,\n output [71:0] mim_tx_rdata,\n\n input mim_rx_wen,\n input [12:0] mim_rx_waddr,\n input [71:0] mim_rx_wdata,\n input mim_rx_ren,\n input mim_rx_rce,\n input [12:0] mim_rx_raddr,\n output [71:0] mim_rx_rdata\n );\n\n // TX calculations\n localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :\n (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :\n (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :\n 1024 );\n\n localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);\n\n localparam ROWS_TX = 1;\n localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 :\n (BYTES_TX <= 8192) ? 2 :\n (BYTES_TX <= 16384) ? 4 :\n (BYTES_TX <= 32768) ? 8 :\n 18\n );\n\n // RX calculations\n localparam ROWS_RX = 1;\n\n localparam COLS_RX = ((VC0_RX_LIMIT < 'h0200) ? 1 :\n (VC0_RX_LIMIT < 'h0400) ? 2 :\n (VC0_RX_LIMIT < 'h0800) ? 4 :\n (VC0_RX_LIMIT < 'h1000) ? 8 :\n 18\n );\n\n initial begin\n $display(\"[%t] %m ROWS_TX %0d COLS_TX %0d\", $time, ROWS_TX, COLS_TX);\n $display(\"[%t] %m ROWS_RX %0d COLS_RX %0d\", $time, ROWS_RX, COLS_RX);\n end\n\n pcie_brams_v6 #(.NUM_BRAMS (COLS_TX),\n .RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),\n .RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),\n .RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY))\n pcie_brams_tx\n (\n .user_clk_i(user_clk_i),\n .reset_i(reset_i),\n\n .waddr(mim_tx_waddr),\n .wen(mim_tx_wen),\n .ren(mim_tx_ren),\n .rce(mim_tx_rce),\n .wdata(mim_tx_wdata),\n .raddr(mim_tx_raddr),\n .rdata(mim_tx_rdata)\n );\n\n pcie_brams_v6 #(.NUM_BRAMS (COLS_RX),\n .RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),\n .RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),\n .RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY))\n pcie_brams_rx\n (\n .user_clk_i(user_clk_i),\n .reset_i(reset_i),\n\n .waddr(mim_rx_waddr),\n .wen(mim_rx_wen),\n .ren(mim_rx_ren),\n .rce(mim_rx_rce),\n .wdata(mim_rx_wdata),\n .raddr(mim_rx_raddr),\n .rdata(mim_rx_rdata)\n );\n\nendmodule // pcie_bram_top\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/pcie_bram_v6.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : pcie_bram_v6.v\n// Version : 2.4\n//--\n//-- Description: BlockRAM module for Virtex6 PCIe Block\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns/1ns\n\nmodule pcie_bram_v6\n #(\n parameter DOB_REG = 0,// 1 use the output register 0 don't use the output register\n parameter WIDTH = 0 // supported WIDTH's are: 4, 9, 18, 36 (uses RAMB36) and 72 (uses RAMB36SDP)\n )\n (\n input user_clk_i,// user clock\n input reset_i, // bram reset\n\n input wen_i, // write enable\n input [12:0] waddr_i, // write address\n input [WIDTH - 1:0] wdata_i, // write data\n\n input ren_i, // read enable\n input rce_i, // output register clock enable\n input [12:0] raddr_i, // read address\n\n output [WIDTH - 1:0] rdata_o // read data\n );\n\n // map the address bits\n localparam ADDR_MSB = ((WIDTH == 4) ? 12 :\n (WIDTH == 9) ? 11 :\n (WIDTH == 18) ? 10 :\n (WIDTH == 36) ? 9 :\n 8\n );\n\n // set the width of the tied off low address bits\n localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :\n (WIDTH == 9) ? 3 :\n (WIDTH == 18) ? 4 :\n (WIDTH == 36) ? 5 :\n 0 // for WIDTH 72 use RAMB36SDP\n );\n\n // map the data bits\n localparam D_MSB = ((WIDTH == 4) ? 3 :\n (WIDTH == 9) ? 7 :\n (WIDTH == 18) ? 15 :\n (WIDTH == 36) ? 31 :\n 63\n );\n\n // map the data parity bits\n localparam DP_LSB = D_MSB + 1;\n\n localparam DP_MSB = ((WIDTH == 4) ? 4 :\n (WIDTH == 9) ? 8 :\n (WIDTH == 18) ? 17 :\n (WIDTH == 36) ? 35 :\n 71\n );\n\n localparam DPW = DP_MSB - DP_LSB + 1;\n\n localparam WRITE_MODE = \"NO_CHANGE\";\n\n //synthesis translate_off\n initial begin\n //$display(\"[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d\",\n // $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);\n\n case (WIDTH)\n 4,9,18,36,72:;\n default:\n begin\n $display(\"[%t] %m Error WIDTH %0d not supported\", $time, WIDTH);\n $finish;\n end\n endcase // case (WIDTH)\n end\n //synthesis translate_on\n\n generate\n if (WIDTH == 72) begin : use_ramb36sdp\n\n // use RAMB36SDP if the width is 72\n RAMB36SDP #(\n .DO_REG (DOB_REG)\n )\n ramb36sdp(\n .WRCLK (user_clk_i),\n .SSR (1'b0),\n .WRADDR (waddr_i[ADDR_MSB:0]),\n .DI (wdata_i[D_MSB:0]),\n .DIP (wdata_i[DP_MSB:DP_LSB]),\n .WREN (wen_i),\n .WE ({8{wen_i}}),\n .DBITERR (),\n .ECCPARITY (),\n .SBITERR (),\n\n .RDCLK (user_clk_i),\n .RDADDR (raddr_i[ADDR_MSB:0]),\n .DO (rdata_o[D_MSB:0]),\n .DOP (rdata_o[DP_MSB:DP_LSB]),\n .RDEN (ren_i),\n .REGCE (rce_i)\n );\n\n // use RAMB36's if the width is 4, 9, 18, or 36\n end else if (WIDTH == 36) begin : use_ramb36\n\n RAMB36 #(\n .DOA_REG (0),\n .DOB_REG (DOB_REG),\n .READ_WIDTH_A (0),\n .READ_WIDTH_B (WIDTH),\n .WRITE_WIDTH_A (WIDTH),\n .WRITE_WIDTH_B (0),\n .WRITE_MODE_A (WRITE_MODE)\n )\n ramb36(\n .CLKA (user_clk_i),\n .SSRA (1'b0),\n .REGCEA (1'b0),\n .CASCADEINLATA (1'b0),\n .CASCADEINREGA (1'b0),\n .CASCADEOUTLATA (),\n .CASCADEOUTREGA (),\n .DOA (),\n .DOPA (),\n .ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),\n .DIA (wdata_i[D_MSB:0]),\n .DIPA (wdata_i[DP_MSB:DP_LSB]),\n .ENA (wen_i),\n .WEA ({4{wen_i}}),\n\n .CLKB (user_clk_i),\n .SSRB (1'b0),\n .WEB (4'b0),\n .CASCADEINLATB (1'b0),\n .CASCADEINREGB (1'b0),\n .CASCADEOUTLATB (),\n .CASCADEOUTREGB (),\n .DIB (32'b0),\n .DIPB ( 4'b0),\n .ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),\n .DOB (rdata_o[D_MSB:0]),\n .DOPB (rdata_o[DP_MSB:DP_LSB]),\n .ENB (ren_i),\n .REGCEB (rce_i)\n );\n\n end else if (WIDTH < 36 && WIDTH > 4) begin : use_ramb36\n\n wire [31 - D_MSB - 1 : 0] dob_unused;\n wire [ 4 - DPW - 1 : 0] dopb_unused;\n\n RAMB36 #(\n .DOA_REG (0),\n .DOB_REG (DOB_REG),\n .READ_WIDTH_A (0),\n .READ_WIDTH_B (WIDTH),\n .WRITE_WIDTH_A (WIDTH),\n .WRITE_WIDTH_B (0),\n .WRITE_MODE_A (WRITE_MODE)\n )\n ramb36(\n .CLKA (user_clk_i),\n .SSRA (1'b0),\n .REGCEA (1'b0),\n .CASCADEINLATA (1'b0),\n .CASCADEINREGA (1'b0),\n .CASCADEOUTLATA (),\n .CASCADEOUTREGA (),\n .DOA (),\n .DOPA (),\n .ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),\n .DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}),\n .DIPA ({{ 4 - DPW {1'b0}},wdata_i[DP_MSB:DP_LSB]}),\n .ENA (wen_i),\n .WEA ({4{wen_i}}),\n\n .CLKB (user_clk_i),\n .SSRB (1'b0),\n .WEB (4'b0),\n .CASCADEINLATB (1'b0),\n .CASCADEINREGB (1'b0),\n .CASCADEOUTLATB (),\n .CASCADEOUTREGB (),\n .DIB (32'b0),\n .DIPB ( 4'b0),\n .ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),\n .DOB ({dob_unused, rdata_o[D_MSB:0]}),\n .DOPB ({dopb_unused, rdata_o[DP_MSB:DP_LSB]}),\n .ENB (ren_i),\n .REGCEB (rce_i)\n );\n\n end else if (WIDTH == 4) begin : use_ramb36\n\n wire [31 - D_MSB - 1 : 0] dob_unused;\n\n RAMB36 #(\n .DOB_REG (DOB_REG),\n .READ_WIDTH_A (0),\n .READ_WIDTH_B (WIDTH),\n .WRITE_WIDTH_A (WIDTH),\n .WRITE_WIDTH_B (0),\n .WRITE_MODE_A (WRITE_MODE)\n )\n ramb36(\n .CLKA (user_clk_i),\n .SSRA (1'b0),\n .REGCEA (1'b0),\n .CASCADEINLATA (1'b0),\n .CASCADEINREGA (1'b0),\n .CASCADEOUTLATA (),\n .CASCADEOUTREGA (),\n .DOA (),\n .DOPA (),\n .ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),\n .DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}),\n //.DIPA (wdata_i[DP_MSB:DP_LSB]),\n .ENA (wen_i),\n .WEA ({4{wen_i}}),\n\n .CLKB (user_clk_i),\n .SSRB (1'b0),\n .WEB (4'b0),\n .CASCADEINLATB (1'b0),\n .CASCADEINREGB (1'b0),\n .CASCADEOUTLATB (),\n .CASCADEOUTREGB (),\n .ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),\n .DOB ({dob_unused,rdata_o[D_MSB:0]}),\n //.DOPB (rdata_o[DP_MSB:DP_LSB]),\n .ENB (ren_i),\n .REGCEB (rce_i)\n );\n\n end // block: use_ramb36\n endgenerate\n\nendmodule // pcie_bram_v6\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/pcie_brams_v6.v", "content": "\n//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : pcie_brams_v6.v\n// Version : 2.4\n//--\n//-- Description: BlockRAM module for Virtex6 PCIe Block\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns/1ns\n\nmodule pcie_brams_v6\n#(\n // the number of BRAMs to use\n // supported values are:\n // 1,2,4,8,18\n parameter NUM_BRAMS = 0,\n \n // BRAM read address latency\n //\n // value meaning\n // ====================================================\n // 0 BRAM read address port sample\n // 1 BRAM read address port sample and a pipeline stage on the address port\n parameter RAM_RADDR_LATENCY = 1,\n\n // BRAM read data latency\n //\n // value meaning\n // ====================================================\n // 1 no BRAM OREG\n // 2 use BRAM OREG\n // 3 use BRAM OREG and a pipeline stage on the data port\n parameter RAM_RDATA_LATENCY = 1,\n\n // BRAM write latency\n // The BRAM write port is synchronous\n //\n // value meaning\n // ====================================================\n // 0 BRAM write port sample\n // 1 BRAM write port sample plus pipeline stage\n parameter RAM_WRITE_LATENCY = 1,\n\n parameter TCQ = 1\n )\n (\n input user_clk_i,\n input reset_i,\n \n input wen,\n input [12:0] waddr,\n input [71:0] wdata,\n input ren,\n input rce,\n input [12:0] raddr,\n output [71:0] rdata\n );\n\n // turn on the bram output register\n localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;\n\n // calculate the data width of the individual brams\n localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 :\n (NUM_BRAMS == 2) ? 36 :\n (NUM_BRAMS == 4) ? 18 :\n (NUM_BRAMS == 8) ? 9 :\n 4\n );\n \n \n //synthesis translate_off\n initial begin\n $display(\"[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d\",\n $time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY);\n\n case (NUM_BRAMS)\n 1,2,4,8,18:;\n default: \n begin\n $display(\"[%t] %m Error NUM_BRAMS %0d not supported\", $time, NUM_BRAMS);\n $finish;\n end\n endcase // case(NUM_BRAMS)\n\n case (RAM_RADDR_LATENCY)\n 0,1:;\n default: \n begin \n $display(\"[%t] %m Error RAM_READ_LATENCY %0d not supported\", $time, RAM_RADDR_LATENCY);\n $finish;\n end\n endcase // case (RAM_RADDR_LATENCY)\n\n case (RAM_RDATA_LATENCY)\n 1,2,3:;\n default: \n begin \n $display(\"[%t] %m Error RAM_READ_LATENCY %0d not supported\", $time, RAM_RDATA_LATENCY);\n $finish;\n end\n endcase // case (RAM_RDATA_LATENCY)\n\n case (RAM_WRITE_LATENCY)\n 0,1:;\n default:\n begin\n $display(\"[%t] %m Error RAM_WRITE_LATENCY %0d not supported\", $time, RAM_WRITE_LATENCY);\n $finish;\n end\n endcase // case(RAM_WRITE_LATENCY)\n\n end\n //synthesis translate_on\n\n // model the delays for ram write latency\n\n wire wen_int;\n wire [12:0] waddr_int;\n wire [71:0] wdata_int;\n \n generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2\n reg wen_dly;\n reg [12:0] waddr_dly;\n reg [71:0] wdata_dly;\n\n always @(posedge user_clk_i) begin\n if (reset_i) begin\n wen_dly <= #TCQ 1'b0;\n waddr_dly <= #TCQ 13'b0;\n wdata_dly <= #TCQ 72'b0;\n end else begin\n wen_dly <= #TCQ wen;\n waddr_dly <= #TCQ waddr;\n wdata_dly <= #TCQ wdata;\n end\n end\n\n assign wen_int = wen_dly;\n assign waddr_int = waddr_dly;\n assign wdata_int = wdata_dly;\n end // if (RAM_WRITE_LATENCY == 1)\n \n else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1\n assign wen_int = wen;\n assign waddr_int = waddr;\n assign wdata_int = wdata;\n end\n endgenerate\n\n // model the delays for ram read latency\n \n wire ren_int;\n wire [12:0] raddr_int;\n wire [71:0] rdata_int;\n\n generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2\n reg ren_dly;\n reg [12:0] raddr_dly;\n\n always @(posedge user_clk_i) begin\n if (reset_i) begin\n ren_dly <= #TCQ 1'b0;\n raddr_dly <= #TCQ 13'b0;\n end else begin\n ren_dly <= #TCQ ren;\n raddr_dly <= #TCQ raddr;\n end // else: !if(reset_i)\n end\n\n assign ren_int = ren_dly;\n assign raddr_int = raddr_dly;\n end // block: rd_lat_addr_2\n\n else begin : raddr_lat_1\n assign ren_int = ren;\n assign raddr_int = raddr;\n end\n endgenerate\n\n generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3\n reg [71:0] rdata_dly;\n\n always @(posedge user_clk_i) begin\n if (reset_i) begin\n rdata_dly <= #TCQ 72'b0;\n end else begin\n rdata_dly <= #TCQ rdata_int;\n end // else: !if(reset_i)\n end\n\n assign rdata = rdata_dly;\n\n end // block: rd_lat_data_3\n\n else begin : rdata_lat_1_2\n assign #TCQ rdata = rdata_int;\n end\n endgenerate\n\n // instantiate the brams\n generate\n begin: num_brams\n genvar i;\n for (i = 0; i < NUM_BRAMS; i = i + 1) begin : brams\n pcie_bram_v6 #(.DOB_REG(DOB_REG), .WIDTH(WIDTH))\n ram (.user_clk_i(user_clk_i), .reset_i(reset_i), \n .wen_i(wen_int), .waddr_i(waddr_int), .wdata_i(wdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]), \n .ren_i(ren_int), .raddr_i(raddr_int), .rdata_o(rdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]), .rce_i(rce));\n end\n end\n endgenerate\nendmodule // pcie_brams_v6\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/pcie_clocking_v6.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : pcie_clocking_v6.v\n// Version : 2.4\n//-- Description: Clocking module for Virtex6 PCIe Block\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns/1ns\n\nmodule pcie_clocking_v6 # (\n\n parameter IS_ENDPOINT = \"TRUE\",\n parameter CAP_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8\n parameter CAP_LINK_SPEED = 4'h1, // 1 - Gen1 , 2 - Gen2\n parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz\n parameter USER_CLK_FREQ = 3 // 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz\n\n)\n(\n\n input wire sys_clk,\n input wire gt_pll_lock,\n input wire sel_lnk_rate,\n input wire [1:0] sel_lnk_width, \n\n output wire sys_clk_bufg,\n output wire pipe_clk,\n output wire user_clk,\n output wire block_clk,\n output wire drp_clk,\n output wire clock_locked\n \n);\n\n parameter TCQ = 1;\n\n wire mmcm_locked;\n wire mmcm_clkfbin;\n wire mmcm_clkfbout;\n wire mmcm_reset;\n wire clk_500;\n wire clk_250;\n wire clk_125;\n wire user_clk_prebuf;\n wire sel_lnk_rate_d; \n\n reg [1:0] reg_clock_locked = 2'b11;\n\n\n // MMCM Configuration\n\n localparam mmcm_clockin_period = (REF_CLK_FREQ == 0) ? 10 : \n (REF_CLK_FREQ == 1) ? 8 : \n (REF_CLK_FREQ == 2) ? 4 : 0;\n\n localparam mmcm_clockfb_mult = (REF_CLK_FREQ == 0) ? 10 : \n (REF_CLK_FREQ == 1) ? 8 : \n (REF_CLK_FREQ == 2) ? 8 : 0;\n\n \n localparam mmcm_divclk_divide = (REF_CLK_FREQ == 0) ? 1 : \n (REF_CLK_FREQ == 1) ? 1 : \n (REF_CLK_FREQ == 2) ? 2 : 0;\n\n localparam mmcm_clock0_div = 4;\n localparam mmcm_clock1_div = 8;\n localparam mmcm_clock2_div = ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 0)) ? 32 :\n ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) ? 16 :\n ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 1)) ? 16 :\n ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) ? 16 : 2;\n localparam mmcm_clock3_div = 2;\n\n // MMCM Reset\n\n assign mmcm_reset = 1'b0; \n\n generate\n\n\n // PIPE Clock BUFG.\n\n if (CAP_LINK_SPEED == 4'h1) begin : GEN1_LINK\n\n BUFG pipe_clk_bufg (.O(pipe_clk),.I(clk_125));\n\n end else if (CAP_LINK_SPEED == 4'h2) begin : GEN2_LINK \n\n SRL16E #(.INIT(0)) sel_lnk_rate_delay (.Q(sel_lnk_rate_d),\n .D(sel_lnk_rate), .CLK(pipe_clk),.CE(clock_locked), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));\n\n BUFGMUX pipe_clk_bufgmux (.O(pipe_clk), .I0(clk_125),.I1(clk_250),.S(sel_lnk_rate_d));\n\n end else begin : ILLEGAL_LINK_SPEED\n\n //$display(\"Confiuration Error : CAP_LINK_SPEED = %d, must be either 1 or 2.\", CAP_LINK_SPEED);\n //$finish;\n\n end\n\n // User Clock BUFG.\n\n if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 0)) begin : x1_GEN1_31_25\n\n BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));\n\n end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) begin : x1_GEN1_62_50\n\n BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));\n\n end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x1_GEN1_125_00\n\n BUFG user_clk_bufg (.O(user_clk),.I(clk_125));\n\n end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x1_GEN1_250_00\n \n BUFG user_clk_bufg (.O(user_clk),.I(clk_250));\n\n end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 1)) begin : x1_GEN2_62_50\n\n BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));\n \n end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 2)) begin : x1_GEN2_125_00\n \n BUFG user_clk_bufg (.O(user_clk),.I(clk_125));\n\n end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x1_GEN2_250_00\n \n BUFG user_clk_bufg (.O(user_clk),.I(clk_250));\n\n end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) begin : x2_GEN1_62_50\n\n BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));\n \n end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x2_GEN1_125_00\n \n BUFG user_clk_bufg (.O(user_clk),.I(clk_125));\n\n end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x2_GEN1_250_00\n\n BUFG user_clk_bufg (.O(user_clk),.I(clk_250));\n \n end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 2)) begin : x2_GEN2_125_00\n\n BUFG user_clk_bufg (.O(user_clk),.I(clk_125));\n \n end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x2_GEN2_250_00\n \n BUFG user_clk_bufg (.O(user_clk),.I(clk_250));\n\n end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x4_GEN1_125_00\n \n BUFG user_clk_bufg (.O(user_clk),.I(clk_125));\n\n end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x4_GEN1_250_00\n \n BUFG user_clk_bufg (.O(user_clk),.I(clk_250));\n\n end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x4_GEN2_250_00\n \n BUFG user_clk_bufg (.O(user_clk),.I(clk_250));\n\n end else if ((CAP_LINK_WIDTH == 6'h08) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x8_GEN1_250_00\n \n BUFG user_clk_bufg (.O(user_clk),.I(clk_250));\n\n end else if ((CAP_LINK_WIDTH == 6'h08) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 4)) begin : x8_GEN2_250_00\n \n BUFG user_clk_bufg (.O(user_clk),.I(clk_250));\n BUFG block_clk_bufg (.O(block_clk),.I(clk_500));\n\n end else begin : ILLEGAL_CONFIGURATION\n\n //$display(\"Confiuration Error : Unsupported Link Width, Link Speed and User Clock Frequency Combination\");\n //$finish;\n\n end\n\n endgenerate\n\n // DRP clk\n BUFG drp_clk_bufg_i (.O(drp_clk), .I(clk_125));\n\n // Feedback BUFG. Required for Temp Compensation\n BUFG clkfbin_bufg_i (.O(mmcm_clkfbin), .I(mmcm_clkfbout));\n\n // sys_clk BUFG.\n BUFG sys_clk_bufg_i (.O(sys_clk_bufg), .I(sys_clk));\n\n MMCM_ADV # (\n\n // 5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz\n .CLKFBOUT_MULT_F (mmcm_clockfb_mult),\n .DIVCLK_DIVIDE (mmcm_divclk_divide),\n .CLKFBOUT_PHASE(0),\n\n // 10 for 100 MHz, 4 for 250 MHz\n .CLKIN1_PERIOD (mmcm_clockin_period),\n .CLKIN2_PERIOD (mmcm_clockin_period),\n\n // 500 MHz / mmcm_clockx_div \n .CLKOUT0_DIVIDE_F (mmcm_clock0_div),\n .CLKOUT0_PHASE (0),\n\n .CLKOUT1_DIVIDE (mmcm_clock1_div),\n .CLKOUT1_PHASE (0),\n\n .CLKOUT2_DIVIDE (mmcm_clock2_div),\n .CLKOUT2_PHASE (0),\n\n .CLKOUT3_DIVIDE (mmcm_clock3_div),\n .CLKOUT3_PHASE (0)\n\n ) mmcm_adv_i (\n\n .CLKFBOUT (mmcm_clkfbout),\n .CLKOUT0 (clk_250), // 250 MHz for pipe_clk\n .CLKOUT1 (clk_125), // 125 MHz for pipe_clk\n .CLKOUT2 (user_clk_prebuf), // user clk\n .CLKOUT3 (clk_500),\n .CLKOUT4 (),\n .CLKOUT5 (),\n .CLKOUT6 (),\n .DO (),\n .DRDY (),\n .CLKFBOUTB (),\n .CLKFBSTOPPED (),\n .CLKINSTOPPED (),\n .CLKOUT0B (),\n .CLKOUT1B (),\n .CLKOUT2B (),\n .CLKOUT3B (),\n .PSDONE (),\n .LOCKED (mmcm_locked),\n .CLKFBIN (mmcm_clkfbin),\n .CLKIN1 (sys_clk),\n .CLKIN2 (1'b0),\n .CLKINSEL (1'b1),\n .DADDR (7'b0),\n .DCLK (1'b0),\n .DEN (1'b0),\n .DI (16'b0),\n .DWE (1'b0),\n .PSEN (1'b0),\n .PSINCDEC (1'b0),\n .PWRDWN (1'b0),\n .PSCLK (1'b0),\n .RST (mmcm_reset)\n );\n\n // Synchronize MMCM locked output\n always @ (posedge pipe_clk or negedge gt_pll_lock) begin\n\n if (!gt_pll_lock)\n reg_clock_locked[1:0] <= #TCQ 2'b11;\n else\n reg_clock_locked[1:0] <= #TCQ {reg_clock_locked[0], 1'b0};\n\n end\n assign clock_locked = !reg_clock_locked[1] & mmcm_locked;\n\nendmodule\n\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/pcie_endpoint.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : pcie_endpoint.v\n// Version : 2.4\n//--\n//-- Description: Virtex6 solution wrapper : Endpoint for PCI Express\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns/1ns\n\n(* CORE_GENERATION_INFO = \"pcie_endpoint,v6_pcie_v2_5,{LINK_CAP_MAX_LINK_SPEED=1,LINK_CAP_MAX_LINK_WIDTH=08,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=2,USER_CLK_FREQ=3,REF_CLK_FREQ=2,MSI_CAP_ON=TRUE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=29,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=4,VC0_TOTAL_CREDITS_PD=64,VC0_TOTAL_CREDITS_NPH=4,VC0_TOTAL_CREDITS_CH=72,VC0_TOTAL_CREDITS_CD=850,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=FALSE,ENABLE_RX_TD_ECRC_TRIM=FALSE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,PIPE_PIPELINE_STAGES=0,REVISION_ID=00,VC_CAP_ON=FALSE}\" *)\nmodule pcie_endpoint # (\n parameter ALLOW_X8_GEN2 = \"FALSE\",\n parameter BAR0 = 32'hFFFFFC00,\n parameter BAR1 = 32'h00000000,\n parameter BAR2 = 32'h00000000,\n parameter BAR3 = 32'h00000000,\n parameter BAR4 = 32'h00000000,\n parameter BAR5 = 32'h00000000,\n\n parameter CARDBUS_CIS_POINTER = 32'h00000000,\n parameter CLASS_CODE = 24'h050000,\n parameter CMD_INTX_IMPLEMENTED = \"TRUE\",\n parameter CPL_TIMEOUT_DISABLE_SUPPORTED = \"FALSE\",\n parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2,\n\n parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 0,\n parameter DEV_CAP_ENDPOINT_L1_LATENCY = 7,\n parameter DEV_CAP_EXT_TAG_SUPPORTED = \"FALSE\",\n parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,\n parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,\n parameter DEVICE_ID = 16'h6018,\n\n parameter DISABLE_LANE_REVERSAL = \"TRUE\",\n parameter DISABLE_SCRAMBLING = \"FALSE\",\n parameter DSN_BASE_PTR = 12'h100,\n parameter DSN_CAP_NEXTPTR = 12'h000,\n parameter DSN_CAP_ON = \"TRUE\",\n\n parameter ENABLE_MSG_ROUTE = 11'b00000000000,\n parameter ENABLE_RX_TD_ECRC_TRIM = \"FALSE\",\n parameter EXPANSION_ROM = 32'h00000000,\n parameter EXT_CFG_CAP_PTR = 6'h3F,\n parameter EXT_CFG_XP_CAP_PTR = 10'h3FF,\n parameter HEADER_TYPE = 8'h00,\n parameter INTERRUPT_PIN = 8'h1,\n\n parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = \"FALSE\",\n parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = \"FALSE\",\n parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,\n parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08,\n parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = \"FALSE\",\n\n parameter LINK_CTRL2_DEEMPHASIS = \"FALSE\",\n parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = \"FALSE\",\n parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h0,\n parameter LINK_STATUS_SLOT_CLOCK_CONFIG = \"FALSE\",\n\n parameter LL_ACK_TIMEOUT = 15'h0000,\n parameter LL_ACK_TIMEOUT_EN = \"FALSE\",\n parameter LL_ACK_TIMEOUT_FUNC = 0,\n parameter LL_REPLAY_TIMEOUT = 15'h0026,\n parameter LL_REPLAY_TIMEOUT_EN = \"TRUE\",\n parameter LL_REPLAY_TIMEOUT_FUNC = 1,\n\n parameter LTSSM_MAX_LINK_WIDTH = 6'h08,\n parameter MSI_CAP_MULTIMSGCAP = 0,\n parameter MSI_CAP_MULTIMSG_EXTENSION = 0,\n parameter MSI_CAP_ON = \"TRUE\",\n parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = \"FALSE\",\n parameter MSI_CAP_64_BIT_ADDR_CAPABLE = \"TRUE\",\n\n parameter MSIX_CAP_ON = \"FALSE\",\n parameter MSIX_CAP_PBA_BIR = 0,\n parameter MSIX_CAP_PBA_OFFSET = 29'h0,\n parameter MSIX_CAP_TABLE_BIR = 0,\n parameter MSIX_CAP_TABLE_OFFSET = 29'h0,\n parameter MSIX_CAP_TABLE_SIZE = 11'h0,\n\n parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'b0000,\n parameter PCIE_CAP_INT_MSG_NUM = 5'h1,\n parameter PCIE_CAP_NEXTPTR = 8'h00,\n parameter PCIE_DRP_ENABLE = \"FALSE\",\n parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages\n\n parameter PM_CAP_DSI = \"FALSE\",\n parameter PM_CAP_D1SUPPORT = \"FALSE\",\n parameter PM_CAP_D2SUPPORT = \"FALSE\",\n parameter PM_CAP_NEXTPTR = 8'h48,\n parameter PM_CAP_PMESUPPORT = 5'h0F,\n parameter PM_CSR_NOSOFTRST = \"TRUE\",\n\n parameter PM_DATA_SCALE0 = 2'h0,\n parameter PM_DATA_SCALE1 = 2'h0,\n parameter PM_DATA_SCALE2 = 2'h0,\n parameter PM_DATA_SCALE3 = 2'h0,\n parameter PM_DATA_SCALE4 = 2'h0,\n parameter PM_DATA_SCALE5 = 2'h0,\n parameter PM_DATA_SCALE6 = 2'h0,\n parameter PM_DATA_SCALE7 = 2'h0,\n\n parameter PM_DATA0 = 8'h00,\n parameter PM_DATA1 = 8'h00,\n parameter PM_DATA2 = 8'h00,\n parameter PM_DATA3 = 8'h00,\n parameter PM_DATA4 = 8'h00,\n parameter PM_DATA5 = 8'h00,\n parameter PM_DATA6 = 8'h00,\n parameter PM_DATA7 = 8'h00,\n\n parameter REF_CLK_FREQ = 2, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz\n parameter REVISION_ID = 8'h00,\n parameter SPARE_BIT0 = 0,\n parameter SUBSYSTEM_ID = 16'h0007,\n parameter SUBSYSTEM_VENDOR_ID = 16'h10EE,\n\n parameter TL_RX_RAM_RADDR_LATENCY = 0,\n parameter TL_RX_RAM_RDATA_LATENCY = 2,\n parameter TL_RX_RAM_WRITE_LATENCY = 0,\n parameter TL_TX_RAM_RADDR_LATENCY = 0,\n parameter TL_TX_RAM_RDATA_LATENCY = 2,\n parameter TL_TX_RAM_WRITE_LATENCY = 0,\n\n parameter UPCONFIG_CAPABLE = \"TRUE\",\n parameter USER_CLK_FREQ = 3,\n parameter VC_BASE_PTR = 12'h0,\n parameter VC_CAP_NEXTPTR = 12'h000,\n parameter VC_CAP_ON = \"FALSE\",\n parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = \"FALSE\",\n\n parameter VC0_CPL_INFINITE = \"TRUE\",\n parameter VC0_RX_RAM_LIMIT = 13'h7FF,\n parameter VC0_TOTAL_CREDITS_CD = 850,\n parameter VC0_TOTAL_CREDITS_CH = 72,\n parameter VC0_TOTAL_CREDITS_NPH = 4,\n parameter VC0_TOTAL_CREDITS_PD = 64,\n parameter VC0_TOTAL_CREDITS_PH = 4,\n parameter VC0_TX_LASTPACKET = 29,\n\n parameter VENDOR_ID = 16'h10EE,\n parameter VSEC_BASE_PTR = 12'h0,\n parameter VSEC_CAP_NEXTPTR = 12'h000,\n parameter VSEC_CAP_ON = \"FALSE\",\n\n parameter AER_BASE_PTR = 12'h128,\n parameter AER_CAP_ECRC_CHECK_CAPABLE = \"FALSE\",\n parameter AER_CAP_ECRC_GEN_CAPABLE = \"FALSE\",\n parameter AER_CAP_ID = 16'h0001,\n parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a,\n parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15,\n parameter AER_CAP_NEXTPTR = 12'h160,\n parameter AER_CAP_ON = \"FALSE\",\n parameter AER_CAP_PERMIT_ROOTERR_UPDATE = \"TRUE\",\n parameter AER_CAP_VERSION = 4'h1,\n\n parameter CAPABILITIES_PTR = 8'h40,\n parameter CRM_MODULE_RSTS = 7'h00,\n parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = \"TRUE\",\n parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = \"TRUE\",\n parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = \"FALSE\",\n parameter DEV_CAP_ROLE_BASED_ERROR = \"TRUE\",\n parameter DEV_CAP_RSVD_14_12 = 0,\n parameter DEV_CAP_RSVD_17_16 = 0,\n parameter DEV_CAP_RSVD_31_29 = 0,\n parameter DEV_CONTROL_AUX_POWER_SUPPORTED = \"FALSE\",\n\n parameter DISABLE_ASPM_L1_TIMER = \"FALSE\",\n parameter DISABLE_BAR_FILTERING = \"FALSE\",\n parameter DISABLE_ID_CHECK = \"FALSE\",\n parameter DISABLE_RX_TC_FILTER = \"FALSE\",\n parameter DNSTREAM_LINK_NUM = 8'h00,\n\n parameter DSN_CAP_ID = 16'h0003,\n parameter DSN_CAP_VERSION = 4'h1,\n parameter ENTER_RVRY_EI_L0 = \"TRUE\",\n parameter INFER_EI = 5'h0c,\n parameter IS_SWITCH = \"FALSE\",\n\n parameter LAST_CONFIG_DWORD = 10'h3FF,\n parameter LINK_CAP_ASPM_SUPPORT = 1,\n parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = \"FALSE\",\n parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,\n parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,\n parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,\n parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,\n parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,\n parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,\n parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,\n parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,\n parameter LINK_CAP_RSVD_23_22 = 0,\n parameter LINK_CONTROL_RCB = 0,\n\n parameter MSI_BASE_PTR = 8'h48,\n parameter MSI_CAP_ID = 8'h05,\n parameter MSI_CAP_NEXTPTR = 8'h60,\n parameter MSIX_BASE_PTR = 8'h9c,\n parameter MSIX_CAP_ID = 8'h11,\n parameter MSIX_CAP_NEXTPTR = 8'h00,\n parameter N_FTS_COMCLK_GEN1 = 255,\n parameter N_FTS_COMCLK_GEN2 = 254,\n parameter N_FTS_GEN1 = 255,\n parameter N_FTS_GEN2 = 255,\n\n parameter PCIE_BASE_PTR = 8'h60,\n parameter PCIE_CAP_CAPABILITY_ID = 8'h10,\n parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2,\n parameter PCIE_CAP_ON = \"TRUE\",\n parameter PCIE_CAP_RSVD_15_14 = 0,\n parameter PCIE_CAP_SLOT_IMPLEMENTED = \"FALSE\",\n parameter PCIE_REVISION = 2,\n parameter PGL0_LANE = 0,\n parameter PGL1_LANE = 1,\n parameter PGL2_LANE = 2,\n parameter PGL3_LANE = 3,\n parameter PGL4_LANE = 4,\n parameter PGL5_LANE = 5,\n parameter PGL6_LANE = 6,\n parameter PGL7_LANE = 7,\n parameter PL_AUTO_CONFIG = 0,\n parameter PL_FAST_TRAIN = \"FALSE\",\n\n parameter PM_BASE_PTR = 8'h40,\n parameter PM_CAP_AUXCURRENT = 0,\n parameter PM_CAP_ID = 8'h01,\n parameter PM_CAP_ON = \"TRUE\",\n parameter PM_CAP_PME_CLOCK = \"FALSE\",\n parameter PM_CAP_RSVD_04 = 0,\n parameter PM_CAP_VERSION = 3,\n parameter PM_CSR_BPCCEN = \"FALSE\",\n parameter PM_CSR_B2B3 = \"FALSE\",\n\n parameter RECRC_CHK = 0,\n parameter RECRC_CHK_TRIM = \"FALSE\",\n parameter ROOT_CAP_CRS_SW_VISIBILITY = \"FALSE\",\n parameter SELECT_DLL_IF = \"FALSE\",\n parameter SLOT_CAP_ATT_BUTTON_PRESENT = \"FALSE\",\n parameter SLOT_CAP_ATT_INDICATOR_PRESENT = \"FALSE\",\n parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = \"FALSE\",\n parameter SLOT_CAP_HOTPLUG_CAPABLE = \"FALSE\",\n parameter SLOT_CAP_HOTPLUG_SURPRISE = \"FALSE\",\n parameter SLOT_CAP_MRL_SENSOR_PRESENT = \"FALSE\",\n parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = \"FALSE\",\n parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,\n parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = \"FALSE\",\n parameter SLOT_CAP_POWER_INDICATOR_PRESENT = \"FALSE\",\n parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,\n parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,\n parameter SPARE_BIT1 = 0,\n parameter SPARE_BIT2 = 0,\n parameter SPARE_BIT3 = 0,\n parameter SPARE_BIT4 = 0,\n parameter SPARE_BIT5 = 0,\n parameter SPARE_BIT6 = 0,\n parameter SPARE_BIT7 = 0,\n parameter SPARE_BIT8 = 0,\n parameter SPARE_BYTE0 = 8'h00,\n parameter SPARE_BYTE1 = 8'h00,\n parameter SPARE_BYTE2 = 8'h00,\n parameter SPARE_BYTE3 = 8'h00,\n parameter SPARE_WORD0 = 32'h00000000,\n parameter SPARE_WORD1 = 32'h00000000,\n parameter SPARE_WORD2 = 32'h00000000,\n parameter SPARE_WORD3 = 32'h00000000,\n\n parameter TL_RBYPASS = \"FALSE\",\n parameter TL_TFC_DISABLE = \"FALSE\",\n parameter TL_TX_CHECKS_DISABLE = \"FALSE\",\n parameter EXIT_LOOPBACK_ON_EI = \"TRUE\",\n parameter UPSTREAM_FACING = \"TRUE\",\n parameter UR_INV_REQ = \"TRUE\",\n\n parameter VC_CAP_ID = 16'h0002,\n parameter VC_CAP_VERSION = 4'h1,\n parameter VSEC_CAP_HDR_ID = 16'h1234,\n parameter VSEC_CAP_HDR_LENGTH = 12'h018,\n parameter VSEC_CAP_HDR_REVISION = 4'h1,\n parameter VSEC_CAP_ID = 16'h000b,\n parameter VSEC_CAP_IS_LINK_VISIBLE = \"TRUE\",\n parameter VSEC_CAP_VERSION = 4'h1\n)\n(\n //-------------------------------------------------------\n // 1. PCI Express (pci_exp) Interface\n //-------------------------------------------------------\n\n // Tx\n output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txp,\n output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txn,\n\n // Rx\n input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxp,\n input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxn,\n\n //-------------------------------------------------------\n // 2. AXI-S Interface\n //-------------------------------------------------------\n\n // Common\n output user_clk_out,\n output user_reset_out,\n output user_lnk_up,\n\n // Tx\n output [5:0] tx_buf_av,\n output tx_err_drop,\n output tx_cfg_req,\n output s_axis_tx_tready,\n input [63:0] s_axis_tx_tdata,\n input [7:0] s_axis_tx_tkeep,\n input [3:0] s_axis_tx_tuser,\n input s_axis_tx_tlast,\n input s_axis_tx_tvalid,\n input tx_cfg_gnt,\n\n // Rx\n output [63:0] m_axis_rx_tdata,\n output [7:0] m_axis_rx_tkeep,\n output m_axis_rx_tlast,\n output m_axis_rx_tvalid,\n input m_axis_rx_tready,\n output [21:0] m_axis_rx_tuser,\n input rx_np_ok,\n\n // Flow Control\n output [11:0] fc_cpld,\n output [7:0] fc_cplh,\n output [11:0] fc_npd,\n output [7:0] fc_nph,\n output [11:0] fc_pd,\n output [7:0] fc_ph,\n input [2:0] fc_sel,\n\n\n //-------------------------------------------------------\n // 3. Configuration (CFG) Interface\n //-------------------------------------------------------\n\n output [31:0] cfg_do,\n output cfg_rd_wr_done,\n input [31:0] cfg_di,\n input [3:0] cfg_byte_en,\n input [9:0] cfg_dwaddr,\n input cfg_wr_en,\n input cfg_rd_en,\n\n input cfg_err_cor,\n input cfg_err_ur,\n input cfg_err_ecrc,\n input cfg_err_cpl_timeout,\n input cfg_err_cpl_abort,\n input cfg_err_cpl_unexpect,\n input cfg_err_posted,\n input cfg_err_locked,\n input [47:0] cfg_err_tlp_cpl_header,\n output cfg_err_cpl_rdy,\n input cfg_interrupt,\n output cfg_interrupt_rdy,\n input cfg_interrupt_assert,\n input [7:0] cfg_interrupt_di,\n output [7:0] cfg_interrupt_do,\n output [2:0] cfg_interrupt_mmenable,\n output cfg_interrupt_msienable,\n output cfg_interrupt_msixenable,\n output cfg_interrupt_msixfm,\n input cfg_turnoff_ok,\n output cfg_to_turnoff,\n input cfg_trn_pending,\n input cfg_pm_wake,\n output [7:0] cfg_bus_number,\n output [4:0] cfg_device_number,\n output [2:0] cfg_function_number,\n output [15:0] cfg_status,\n output [15:0] cfg_command,\n output [15:0] cfg_dstatus,\n output [15:0] cfg_dcommand,\n output [15:0] cfg_lstatus,\n output [15:0] cfg_lcommand,\n output [15:0] cfg_dcommand2,\n output [2:0] cfg_pcie_link_state,\n input [63:0] cfg_dsn,\n output cfg_pmcsr_pme_en,\n output cfg_pmcsr_pme_status,\n output [1:0] cfg_pmcsr_powerstate,\n\n //-------------------------------------------------------\n // 4. Physical Layer Control and Status (PL) Interface\n //-------------------------------------------------------\n\n output [2:0] pl_initial_link_width,\n output [1:0] pl_lane_reversal_mode,\n output pl_link_gen2_capable,\n output pl_link_partner_gen2_supported,\n output pl_link_upcfg_capable,\n output [5:0] pl_ltssm_state,\n output pl_received_hot_rst,\n output pl_sel_link_rate,\n output [1:0] pl_sel_link_width,\n input pl_directed_link_auton,\n input [1:0] pl_directed_link_change,\n input pl_directed_link_speed,\n input [1:0] pl_directed_link_width,\n input pl_upstream_prefer_deemph,\n\n //-------------------------------------------------------\n // 5. System (SYS) Interface\n //-------------------------------------------------------\n\n input sys_clk,\n input sys_reset\n\n\n);\n\n\n wire [63:0] trn_td;\n wire trn_trem;\n wire trn_tsof;\n wire trn_teof;\n wire trn_tsrc_rdy;\n wire trn_tdst_rdy_n;\n wire trn_terr_drop_n;\n wire trn_tsrc_dsc;\n wire trn_terrfwd;\n wire trn_tstr;\n wire trn_tecrc_gen;\n\n wire [63:0] trn_rd;\n wire trn_rrem_n;\n wire trn_rsof_n;\n wire trn_reof_n;\n wire trn_rsrc_rdy_n;\n wire trn_rdst_rdy;\n wire trn_rsrc_dsc_n;\n wire trn_rerrfwd_n;\n wire [6:0] trn_rbar_hit_n;\n\n wire trn_tcfg_gnt;\n\n wire [31:0] trn_rdllp_data;\n wire trn_rdllp_src_rdy_n;\n\n\n wire rx_func_level_reset_n;\n wire cfg_msg_received;\n wire cfg_msg_received_pme_to;\n\n wire cfg_cmd_bme;\n wire cfg_cmd_intdis;\n wire cfg_cmd_io_en;\n wire cfg_cmd_mem_en;\n wire cfg_cmd_serr_en;\n wire cfg_dev_control_aux_power_en ;\n wire cfg_dev_control_corr_err_reporting_en ;\n wire cfg_dev_control_enable_relaxed_order ;\n wire cfg_dev_control_ext_tag_en ;\n wire cfg_dev_control_fatal_err_reporting_en ;\n wire [2:0] cfg_dev_control_maxpayload ;\n wire [2:0] cfg_dev_control_max_read_req ;\n wire cfg_dev_control_non_fatal_reporting_en ;\n wire cfg_dev_control_nosnoop_en ;\n wire cfg_dev_control_phantom_en ;\n wire cfg_dev_control_ur_err_reporting_en ;\n wire cfg_dev_control2_cpltimeout_dis ;\n wire [3:0] cfg_dev_control2_cpltimeout_val ;\n wire cfg_dev_status_corr_err_detected ;\n wire cfg_dev_status_fatal_err_detected ;\n wire cfg_dev_status_nonfatal_err_detected ;\n wire cfg_dev_status_ur_detected ;\n wire cfg_link_control_auto_bandwidth_int_en ;\n wire cfg_link_control_bandwidth_int_en ;\n wire cfg_link_control_hw_auto_width_dis ;\n wire cfg_link_control_clock_pm_en ;\n wire cfg_link_control_extended_sync ;\n wire cfg_link_control_common_clock ;\n wire cfg_link_control_retrain_link ;\n wire cfg_link_control_linkdisable ;\n wire cfg_link_control_rcb ;\n wire [1:0] cfg_link_control_aspm_control ;\n wire cfg_link_status_autobandwidth_status ;\n wire cfg_link_status_bandwidth_status ;\n wire cfg_link_status_dll_active ;\n wire cfg_link_status_link_training ;\n wire [3:0] cfg_link_status_negotiated_link_width ;\n wire [1:0] cfg_link_status_current_speed ;\n wire [15:0] cfg_msg_data;\n\n wire sys_reset_n_d;\n wire phy_rdy_n;\n\n wire trn_lnk_up_n_int;\n wire trn_lnk_up_n_int1;\n\n wire trn_reset_n_int;\n wire trn_reset_n_int1;\n\n wire TxOutClk;\n wire TxOutClk_bufg;\n\n reg [7:0] cfg_bus_number_d;\n reg [4:0] cfg_device_number_d;\n reg [2:0] cfg_function_number_d;\n\n wire cfg_rd_wr_done_n;\n wire cfg_interrupt_rdy_n;\n wire cfg_turnoff_ok_w;\n wire trn_recrc_err_n;\n wire cfg_err_cpl_rdy_n;\n wire trn_tcfg_req_n;\n\n\n // Inversion logic\n assign cfg_rd_wr_done = !cfg_rd_wr_done_n ;\n wire [3:0] cfg_byte_en_n = ~cfg_byte_en ;\n wire cfg_wr_en_n = !cfg_wr_en ;\n wire cfg_rd_en_n = !cfg_rd_en ;\n wire cfg_trn_pending_n = !cfg_trn_pending ;\n wire cfg_turnoff_ok_n = !cfg_turnoff_ok_w ;\n wire cfg_pm_wake_n = !cfg_pm_wake ;\n wire cfg_interrupt_n = !cfg_interrupt ;\n assign cfg_interrupt_rdy = !cfg_interrupt_rdy_n ;\n wire cfg_interrupt_assert_n = !cfg_interrupt_assert ;\n wire cfg_err_ecrc_n = !cfg_err_ecrc ;\n wire cfg_err_ur_n = !cfg_err_ur ;\n wire cfg_err_cpl_timeout_n = !cfg_err_cpl_timeout ;\n wire cfg_err_cpl_unexpect_n = !cfg_err_cpl_unexpect ;\n wire cfg_err_cpl_abort_n = !cfg_err_cpl_abort ;\n wire cfg_err_posted_n = !cfg_err_posted ;\n wire cfg_err_cor_n = !cfg_err_cor ;\n assign cfg_err_cpl_rdy = !cfg_err_cpl_rdy_n ;\n wire cfg_err_locked_n = !cfg_err_locked ;\n wire trn_recrc_err = !trn_recrc_err_n;\n assign tx_err_drop = !trn_terr_drop_n;\n assign tx_cfg_req = !trn_tcfg_req_n;\n\n\n\n // assigns to outputs\n\n assign cfg_to_turnoff = cfg_msg_received_pme_to;\n\n assign cfg_status = {16'b0};\n\n assign cfg_command = {5'b0,\n cfg_cmd_intdis,\n 1'b0,\n cfg_cmd_serr_en,\n 5'b0,\n cfg_cmd_bme,\n cfg_cmd_mem_en,\n cfg_cmd_io_en};\n\n assign cfg_dstatus = {10'h0,\n cfg_trn_pending,\n 1'b0,\n cfg_dev_status_ur_detected,\n cfg_dev_status_fatal_err_detected,\n cfg_dev_status_nonfatal_err_detected,\n cfg_dev_status_corr_err_detected};\n\n assign cfg_dcommand = {1'b0,\n cfg_dev_control_max_read_req,\n cfg_dev_control_nosnoop_en,\n cfg_dev_control_aux_power_en,\n cfg_dev_control_phantom_en,\n cfg_dev_control_ext_tag_en,\n cfg_dev_control_maxpayload,\n cfg_dev_control_enable_relaxed_order,\n cfg_dev_control_ur_err_reporting_en,\n cfg_dev_control_fatal_err_reporting_en,\n cfg_dev_control_non_fatal_reporting_en,\n cfg_dev_control_corr_err_reporting_en };\n\n assign cfg_lstatus = {cfg_link_status_autobandwidth_status,\n cfg_link_status_bandwidth_status,\n cfg_link_status_dll_active,\n (LINK_STATUS_SLOT_CLOCK_CONFIG == \"TRUE\") ? 1'b1 : 1'b0,\n cfg_link_status_link_training,\n 1'b0,\n {2'b00, cfg_link_status_negotiated_link_width},\n {2'b00, cfg_link_status_current_speed} };\n\n assign cfg_lcommand = {4'b0,\n cfg_link_control_auto_bandwidth_int_en,\n cfg_link_control_bandwidth_int_en,\n cfg_link_control_hw_auto_width_dis,\n cfg_link_control_clock_pm_en,\n cfg_link_control_extended_sync,\n cfg_link_control_common_clock,\n cfg_link_control_retrain_link,\n cfg_link_control_linkdisable,\n cfg_link_control_rcb,\n 1'b0,\n cfg_link_control_aspm_control };\n\n assign cfg_bus_number = cfg_bus_number_d;\n\n assign cfg_device_number = cfg_device_number_d;\n\n assign cfg_function_number = cfg_function_number_d;\n\n assign cfg_dcommand2 = {11'b0,\n cfg_dev_control2_cpltimeout_dis,\n cfg_dev_control2_cpltimeout_val};\n\n\n // Capture Bus/Device/Function number\n\n always @(posedge user_clk_out) begin\n if (!user_lnk_up) cfg_bus_number_d <= 8'b0;\n else if (~cfg_msg_received) cfg_bus_number_d <= cfg_msg_data[15:8];\n end\n\n always @(posedge user_clk_out) begin\n if (!user_lnk_up) cfg_device_number_d <= 5'b0;\n else if (~cfg_msg_received) cfg_device_number_d <= cfg_msg_data[7:3];\n end\n\n always @(posedge user_clk_out) begin\n if (!user_lnk_up) cfg_function_number_d <= 3'b0;\n else if (~cfg_msg_received) cfg_function_number_d <= cfg_msg_data[2:0];\n end\n\n // Generate user_lnk_up\n\nFDCP #(\n\n .INIT(1'b0)\n\n) trn_lnk_up_n_i (\n\n .Q (user_lnk_up),\n .D (!trn_lnk_up_n_int1),\n .C (user_clk_out),\n .CLR (1'b0),\n .PRE (1'b0)\n\n);\n\nFDCP #(\n\n .INIT(1'b1)\n\n) trn_lnk_up_n_int_i (\n\n .Q (trn_lnk_up_n_int1),\n .D (trn_lnk_up_n_int),\n .C (user_clk_out),\n .CLR (1'b0),\n .PRE (1'b0)\n\n);\n\n // Generate user_reset_out\n\nFDCP #(\n\n .INIT(1'b1)\n\n) trn_reset_n_i (\n\n .Q (user_reset_out),\n .D (!(trn_reset_n_int1 & ~phy_rdy_n)),\n .C (user_clk_out),\n .CLR (~sys_reset_n_d),\n .PRE (1'b0)\n\n);\n\nFDCP #(\n\n .INIT(1'b0)\n\n) trn_reset_n_int_i (\n\n .Q (trn_reset_n_int1 ),\n .D (trn_reset_n_int & ~phy_rdy_n),\n .C (user_clk_out),\n .CLR (~sys_reset_n_d),\n .PRE (1'b0)\n\n);\n\n// AXI Basic Bridge\n// Converts between TRN and AXI\n\naxi_basic_top #(\n .C_DATA_WIDTH (64), // RX/TX interface data width\n\n .C_FAMILY (\"V6\"), // Targeted FPGA family\n .C_ROOT_PORT (\"FALSE\"), // PCIe block is in root port mode\n .C_PM_PRIORITY (\"FALSE\") // Disable TX packet boundary thrtl\n\n ) axi_basic_top (\n //---------------------------------------------//\n // User Design I/O //\n //---------------------------------------------//\n\n // AXI TX\n //-----------\n .s_axis_tx_tdata (s_axis_tx_tdata), // input\n .s_axis_tx_tvalid (s_axis_tx_tvalid), // input\n .s_axis_tx_tready (s_axis_tx_tready), // output\n .s_axis_tx_tkeep (s_axis_tx_tkeep), // input\n .s_axis_tx_tlast (s_axis_tx_tlast), // input\n .s_axis_tx_tuser (s_axis_tx_tuser), // input\n\n // AXI RX\n //-----------\n .m_axis_rx_tdata (m_axis_rx_tdata), // output\n .m_axis_rx_tvalid (m_axis_rx_tvalid), // output\n .m_axis_rx_tready (m_axis_rx_tready), // input\n .m_axis_rx_tkeep (m_axis_rx_tkeep), // output\n .m_axis_rx_tlast (m_axis_rx_tlast), // output\n .m_axis_rx_tuser (m_axis_rx_tuser), // output\n\n // User Misc.\n //-----------\n .user_turnoff_ok (cfg_turnoff_ok), // input\n .user_tcfg_gnt (tx_cfg_gnt), // input\n\n //---------------------------------------------//\n // PCIe Block I/O //\n //---------------------------------------------//\n\n // TRN TX\n //-----------\n .trn_td (trn_td), // output\n .trn_tsof (trn_tsof), // output\n .trn_teof (trn_teof), // output\n .trn_tsrc_rdy (trn_tsrc_rdy), // output\n .trn_tdst_rdy (!trn_tdst_rdy_n), // input\n .trn_tsrc_dsc (trn_tsrc_dsc), // output\n .trn_trem (trn_trem), // output\n .trn_terrfwd (trn_terrfwd), // output\n .trn_tstr (trn_tstr), // output\n .trn_tbuf_av (tx_buf_av), // input\n .trn_tecrc_gen (trn_tecrc_gen), // output\n\n // TRN RX\n //-----------\n .trn_rd (trn_rd), // input\n .trn_rsof (!trn_rsof_n), // input\n .trn_reof (!trn_reof_n), // input\n .trn_rsrc_rdy (!trn_rsrc_rdy_n), // input\n .trn_rdst_rdy (trn_rdst_rdy), // output\n .trn_rsrc_dsc (!trn_rsrc_dsc_n), // input\n .trn_rrem (~trn_rrem_n), // input\n .trn_rerrfwd (!trn_rerrfwd_n), // input\n .trn_rbar_hit (~trn_rbar_hit_n), // input\n .trn_recrc_err (trn_recrc_err), // input\n\n // TRN Misc.\n //-----------\n .trn_tcfg_req (tx_cfg_req), // input\n .trn_tcfg_gnt (trn_tcfg_gnt), // output\n .trn_lnk_up (user_lnk_up), // input\n\n // Artix/Kintex/Virtex PM\n //-----------\n .cfg_pcie_link_state (cfg_pcie_link_state), // input\n\n // Virtex6 PM\n //-----------\n .cfg_pm_send_pme_to (1'b0), // input NOT USED FOR EP\n .cfg_pmcsr_powerstate (cfg_pmcsr_powerstate), // input\n .trn_rdllp_data (trn_rdllp_data), // input\n .trn_rdllp_src_rdy (!trn_rdllp_src_rdy_n), // input\n\n // Power Mgmt for S6/V6\n //-----------\n .cfg_to_turnoff (cfg_to_turnoff), // input\n .cfg_turnoff_ok (cfg_turnoff_ok_w), // output\n\n // System\n //-----------\n .user_clk (user_clk_out), // input\n .user_rst (user_reset_out), // input\n .np_counter () // output\n);\n\n\n\n//-------------------------------------------------------\n// PCI Express Reset Delay Module\n//-------------------------------------------------------\n\npcie_reset_delay_v6 #(\n\n .PL_FAST_TRAIN ( PL_FAST_TRAIN ),\n .REF_CLK_FREQ ( REF_CLK_FREQ )\n\n)\npcie_reset_delay_i (\n\n .ref_clk ( TxOutClk_bufg ),\n .sys_reset_n ( !sys_reset ),\n .delayed_sys_reset_n ( sys_reset_n_d )\n\n);\n\n//-------------------------------------------------------\n// PCI Express Clocking Module\n//-------------------------------------------------------\n\npcie_clocking_v6 #(\n\n .CAP_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),\n .CAP_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),\n .REF_CLK_FREQ(REF_CLK_FREQ),\n .USER_CLK_FREQ(USER_CLK_FREQ)\n\n)\npcie_clocking_i (\n\n .sys_clk ( TxOutClk ),\n .gt_pll_lock ( gt_pll_lock ),\n .sel_lnk_rate ( pl_sel_link_rate ),\n .sel_lnk_width ( pl_sel_link_width ),\n\n .sys_clk_bufg ( TxOutClk_bufg ),\n .pipe_clk ( pipe_clk ),\n .user_clk ( user_clk_out ),\n .block_clk ( block_clk ),\n .drp_clk ( drp_clk ),\n .clock_locked ( clock_locked )\n\n);\n\n//-------------------------------------------------------\n// Virtex6 PCI Express Block Module\n//-------------------------------------------------------\n\npcie_2_0_v6 #(\n\n .REF_CLK_FREQ ( REF_CLK_FREQ ),\n .PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),\n .AER_BASE_PTR ( AER_BASE_PTR ),\n .AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),\n .AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),\n .AER_CAP_ID ( AER_CAP_ID ),\n .AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ),\n .AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ),\n .AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),\n .AER_CAP_ON ( AER_CAP_ON ),\n .AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),\n .AER_CAP_VERSION ( AER_CAP_VERSION ),\n .ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),\n .BAR0 ( BAR0 ),\n .BAR1 ( BAR1 ),\n .BAR2 ( BAR2 ),\n .BAR3 ( BAR3 ),\n .BAR4 ( BAR4 ),\n .BAR5 ( BAR5 ),\n .CAPABILITIES_PTR ( CAPABILITIES_PTR ),\n .CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),\n .CLASS_CODE ( CLASS_CODE ),\n .CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),\n .CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),\n .CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),\n .CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),\n .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),\n .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),\n .DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),\n .DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),\n .DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),\n .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),\n .DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),\n .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),\n .DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),\n .DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),\n .DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),\n .DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),\n .DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),\n .DEVICE_ID ( DEVICE_ID ),\n .DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),\n .DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),\n .DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),\n .DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),\n .DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),\n .DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),\n .DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),\n .DSN_BASE_PTR ( DSN_BASE_PTR ),\n .DSN_CAP_ID ( DSN_CAP_ID ),\n .DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),\n .DSN_CAP_ON ( DSN_CAP_ON ),\n .DSN_CAP_VERSION ( DSN_CAP_VERSION ),\n .ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),\n .ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),\n .ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),\n .EXPANSION_ROM ( EXPANSION_ROM ),\n .EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),\n .EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),\n .HEADER_TYPE ( HEADER_TYPE ),\n .INFER_EI ( INFER_EI ),\n .INTERRUPT_PIN ( INTERRUPT_PIN ),\n .IS_SWITCH ( IS_SWITCH ),\n .LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),\n .LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),\n .LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),\n .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),\n .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),\n .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),\n .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),\n .LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),\n .LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),\n .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),\n .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),\n .LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),\n .LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),\n .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),\n .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),\n .LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ),\n .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),\n .LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),\n .LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),\n .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),\n .LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),\n .LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),\n .LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),\n .LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),\n .LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),\n .LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),\n .LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),\n .LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),\n .LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),\n .MSI_BASE_PTR ( MSI_BASE_PTR ),\n .MSI_CAP_ID ( MSI_CAP_ID ),\n .MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),\n .MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),\n .MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),\n .MSI_CAP_ON ( MSI_CAP_ON ),\n .MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),\n .MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),\n .MSIX_BASE_PTR ( MSIX_BASE_PTR ),\n .MSIX_CAP_ID ( MSIX_CAP_ID ),\n .MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),\n .MSIX_CAP_ON ( MSIX_CAP_ON ),\n .MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),\n .MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),\n .MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),\n .MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),\n .MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),\n .N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),\n .N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),\n .N_FTS_GEN1 ( N_FTS_GEN1 ),\n .N_FTS_GEN2 ( N_FTS_GEN2 ),\n .PCIE_BASE_PTR ( PCIE_BASE_PTR ),\n .PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),\n .PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),\n .PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),\n .PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ),\n .PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),\n .PCIE_CAP_ON ( PCIE_CAP_ON ),\n .PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),\n .PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),\n .PCIE_REVISION ( PCIE_REVISION ),\n .PGL0_LANE ( PGL0_LANE ),\n .PGL1_LANE ( PGL1_LANE ),\n .PGL2_LANE ( PGL2_LANE ),\n .PGL3_LANE ( PGL3_LANE ),\n .PGL4_LANE ( PGL4_LANE ),\n .PGL5_LANE ( PGL5_LANE ),\n .PGL6_LANE ( PGL6_LANE ),\n .PGL7_LANE ( PGL7_LANE ),\n .PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),\n .PL_FAST_TRAIN ( PL_FAST_TRAIN ),\n .PM_BASE_PTR ( PM_BASE_PTR ),\n .PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),\n .PM_CAP_DSI ( PM_CAP_DSI ),\n .PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),\n .PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),\n .PM_CAP_ID ( PM_CAP_ID ),\n .PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),\n .PM_CAP_ON ( PM_CAP_ON ),\n .PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),\n .PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),\n .PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),\n .PM_CAP_VERSION ( PM_CAP_VERSION ),\n .PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),\n .PM_CSR_B2B3 ( PM_CSR_B2B3 ),\n .PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),\n .PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),\n .PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),\n .PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),\n .PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),\n .PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),\n .PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),\n .PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),\n .PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),\n .PM_DATA0 ( PM_DATA0 ),\n .PM_DATA1 ( PM_DATA1 ),\n .PM_DATA2 ( PM_DATA2 ),\n .PM_DATA3 ( PM_DATA3 ),\n .PM_DATA4 ( PM_DATA4 ),\n .PM_DATA5 ( PM_DATA5 ),\n .PM_DATA6 ( PM_DATA6 ),\n .PM_DATA7 ( PM_DATA7 ),\n .RECRC_CHK ( RECRC_CHK ),\n .RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),\n .REVISION_ID ( REVISION_ID ),\n .ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),\n .SELECT_DLL_IF ( SELECT_DLL_IF ),\n .SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),\n .SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),\n .SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),\n .SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),\n .SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),\n .SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),\n .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),\n .SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),\n .SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),\n .SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),\n .SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),\n .SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),\n .SPARE_BIT0 ( SPARE_BIT0 ),\n .SPARE_BIT1 ( SPARE_BIT1 ),\n .SPARE_BIT2 ( SPARE_BIT2 ),\n .SPARE_BIT3 ( SPARE_BIT3 ),\n .SPARE_BIT4 ( SPARE_BIT4 ),\n .SPARE_BIT5 ( SPARE_BIT5 ),\n .SPARE_BIT6 ( SPARE_BIT6 ),\n .SPARE_BIT7 ( SPARE_BIT7 ),\n .SPARE_BIT8 ( SPARE_BIT8 ),\n .SPARE_BYTE0 ( SPARE_BYTE0 ),\n .SPARE_BYTE1 ( SPARE_BYTE1 ),\n .SPARE_BYTE2 ( SPARE_BYTE2 ),\n .SPARE_BYTE3 ( SPARE_BYTE3 ),\n .SPARE_WORD0 ( SPARE_WORD0 ),\n .SPARE_WORD1 ( SPARE_WORD1 ),\n .SPARE_WORD2 ( SPARE_WORD2 ),\n .SPARE_WORD3 ( SPARE_WORD3 ),\n .SUBSYSTEM_ID ( SUBSYSTEM_ID ),\n .SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ),\n .TL_RBYPASS ( TL_RBYPASS ),\n .TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),\n .TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),\n .TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),\n .TL_TFC_DISABLE ( TL_TFC_DISABLE ),\n .TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),\n .TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),\n .TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),\n .TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),\n .UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),\n .UPSTREAM_FACING ( UPSTREAM_FACING ),\n .EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),\n .UR_INV_REQ ( UR_INV_REQ ),\n .USER_CLK_FREQ ( USER_CLK_FREQ ),\n .VC_BASE_PTR ( VC_BASE_PTR ),\n .VC_CAP_ID ( VC_CAP_ID ),\n .VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),\n .VC_CAP_ON ( VC_CAP_ON ),\n .VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),\n .VC_CAP_VERSION ( VC_CAP_VERSION ),\n .VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),\n .VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),\n .VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),\n .VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),\n .VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),\n .VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),\n .VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),\n .VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),\n .VENDOR_ID ( VENDOR_ID ),\n .VSEC_BASE_PTR ( VSEC_BASE_PTR ),\n .VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),\n .VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),\n .VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),\n .VSEC_CAP_ID ( VSEC_CAP_ID ),\n .VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),\n .VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),\n .VSEC_CAP_ON ( VSEC_CAP_ON ),\n .VSEC_CAP_VERSION ( VSEC_CAP_VERSION )\n\n)\npcie_2_0_i (\n\n .PCIEXPRXN( pci_exp_rxn ),\n .PCIEXPRXP( pci_exp_rxp ),\n .PCIEXPTXN( pci_exp_txn ),\n .PCIEXPTXP( pci_exp_txp ),\n\n .SYSCLK( sys_clk ),\n .TRNLNKUPN( trn_lnk_up_n_int ),\n\n .FUNDRSTN (sys_reset_n_d),\n .PHYRDYN( phy_rdy_n ),\n\n .LNKCLKEN ( ),\n .USERRSTN( trn_reset_n_int ),\n .RECEIVEDFUNCLVLRSTN( rx_func_level_reset_n ),\n .SYSRSTN( ~phy_rdy_n ),\n .PLRSTN( 1'b1 ),\n .DLRSTN( 1'b1 ),\n .TLRSTN( 1'b1 ),\n .FUNCLVLRSTN( 1'b1 ),\n .CMRSTN( 1'b1 ),\n .CMSTICKYRSTN( 1'b1 ),\n\n .TRNRBARHITN( trn_rbar_hit_n ),\n .TRNRD( trn_rd ),\n .TRNRECRCERRN( trn_recrc_err_n ),\n .TRNREOFN( trn_reof_n ),\n .TRNRERRFWDN( trn_rerrfwd_n ),\n .TRNRREMN( trn_rrem_n ),\n .TRNRSOFN( trn_rsof_n ),\n .TRNRSRCDSCN( trn_rsrc_dsc_n ),\n .TRNRSRCRDYN( trn_rsrc_rdy_n ),\n .TRNRDSTRDYN( !trn_rdst_rdy ),\n .TRNRNPOKN( !rx_np_ok ),\n\n .TRNTBUFAV( tx_buf_av ),\n .TRNTCFGREQN( trn_tcfg_req_n ),\n .TRNTDLLPDSTRDYN( ),\n .TRNTDSTRDYN( trn_tdst_rdy_n ),\n .TRNTERRDROPN( trn_terr_drop_n ),\n .TRNTCFGGNTN( !trn_tcfg_gnt ),\n .TRNTD( trn_td ),\n .TRNTDLLPDATA( 32'b0 ),\n .TRNTDLLPSRCRDYN( 1'b1 ),\n .TRNTECRCGENN( 1'b1 ),\n .TRNTEOFN( !trn_teof ),\n .TRNTERRFWDN( !trn_terrfwd ),\n .TRNTREMN( ~trn_trem ),\n .TRNTSOFN( !trn_tsof ),\n .TRNTSRCDSCN( !trn_tsrc_dsc ),\n .TRNTSRCRDYN( !trn_tsrc_rdy ),\n .TRNTSTRN( !trn_tstr ),\n\n .TRNFCCPLD( fc_cpld ),\n .TRNFCCPLH( fc_cplh ),\n .TRNFCNPD( fc_npd ),\n .TRNFCNPH( fc_nph ),\n .TRNFCPD( fc_pd ),\n .TRNFCPH( fc_ph ),\n .TRNFCSEL( fc_sel ),\n\n .CFGAERECRCCHECKEN(),\n .CFGAERECRCGENEN(),\n .CFGCOMMANDBUSMASTERENABLE( cfg_cmd_bme ),\n .CFGCOMMANDINTERRUPTDISABLE( cfg_cmd_intdis ),\n .CFGCOMMANDIOENABLE( cfg_cmd_io_en ),\n .CFGCOMMANDMEMENABLE( cfg_cmd_mem_en ),\n .CFGCOMMANDSERREN( cfg_cmd_serr_en ),\n .CFGDEVCONTROLAUXPOWEREN( cfg_dev_control_aux_power_en ),\n .CFGDEVCONTROLCORRERRREPORTINGEN( cfg_dev_control_corr_err_reporting_en ),\n .CFGDEVCONTROLENABLERO( cfg_dev_control_enable_relaxed_order ),\n .CFGDEVCONTROLEXTTAGEN( cfg_dev_control_ext_tag_en ),\n .CFGDEVCONTROLFATALERRREPORTINGEN( cfg_dev_control_fatal_err_reporting_en ),\n .CFGDEVCONTROLMAXPAYLOAD( cfg_dev_control_maxpayload ),\n .CFGDEVCONTROLMAXREADREQ( cfg_dev_control_max_read_req ),\n .CFGDEVCONTROLNONFATALREPORTINGEN( cfg_dev_control_non_fatal_reporting_en ),\n .CFGDEVCONTROLNOSNOOPEN( cfg_dev_control_nosnoop_en ),\n .CFGDEVCONTROLPHANTOMEN( cfg_dev_control_phantom_en ),\n .CFGDEVCONTROLURERRREPORTINGEN( cfg_dev_control_ur_err_reporting_en ),\n .CFGDEVCONTROL2CPLTIMEOUTDIS( cfg_dev_control2_cpltimeout_dis ),\n .CFGDEVCONTROL2CPLTIMEOUTVAL( cfg_dev_control2_cpltimeout_val ),\n .CFGDEVSTATUSCORRERRDETECTED( cfg_dev_status_corr_err_detected ),\n .CFGDEVSTATUSFATALERRDETECTED( cfg_dev_status_fatal_err_detected ),\n .CFGDEVSTATUSNONFATALERRDETECTED( cfg_dev_status_nonfatal_err_detected ),\n .CFGDEVSTATUSURDETECTED( cfg_dev_status_ur_detected ),\n .CFGDO( cfg_do ),\n .CFGERRAERHEADERLOGSETN(),\n .CFGERRCPLRDYN( cfg_err_cpl_rdy_n ),\n .CFGINTERRUPTDO( cfg_interrupt_do ),\n .CFGINTERRUPTMMENABLE( cfg_interrupt_mmenable ),\n .CFGINTERRUPTMSIENABLE( cfg_interrupt_msienable ),\n .CFGINTERRUPTMSIXENABLE( cfg_interrupt_msixenable ),\n .CFGINTERRUPTMSIXFM( cfg_interrupt_msixfm ),\n .CFGINTERRUPTRDYN( cfg_interrupt_rdy_n ),\n .CFGLINKCONTROLRCB( cfg_link_control_rcb ),\n .CFGLINKCONTROLASPMCONTROL( cfg_link_control_aspm_control ),\n .CFGLINKCONTROLAUTOBANDWIDTHINTEN( cfg_link_control_auto_bandwidth_int_en ),\n .CFGLINKCONTROLBANDWIDTHINTEN( cfg_link_control_bandwidth_int_en ),\n .CFGLINKCONTROLCLOCKPMEN( cfg_link_control_clock_pm_en ),\n .CFGLINKCONTROLCOMMONCLOCK( cfg_link_control_common_clock ),\n .CFGLINKCONTROLEXTENDEDSYNC( cfg_link_control_extended_sync ),\n .CFGLINKCONTROLHWAUTOWIDTHDIS( cfg_link_control_hw_auto_width_dis ),\n .CFGLINKCONTROLLINKDISABLE( cfg_link_control_linkdisable ),\n .CFGLINKCONTROLRETRAINLINK( cfg_link_control_retrain_link ),\n .CFGLINKSTATUSAUTOBANDWIDTHSTATUS( cfg_link_status_autobandwidth_status ),\n .CFGLINKSTATUSBANDWITHSTATUS( cfg_link_status_bandwidth_status ),\n .CFGLINKSTATUSCURRENTSPEED( cfg_link_status_current_speed ),\n .CFGLINKSTATUSDLLACTIVE( cfg_link_status_dll_active ),\n .CFGLINKSTATUSLINKTRAINING( cfg_link_status_link_training ),\n .CFGLINKSTATUSNEGOTIATEDWIDTH( cfg_link_status_negotiated_link_width ),\n .CFGMSGDATA( cfg_msg_data ),\n .CFGMSGRECEIVED( cfg_msg_received ),\n .CFGMSGRECEIVEDASSERTINTA(),\n .CFGMSGRECEIVEDASSERTINTB(),\n .CFGMSGRECEIVEDASSERTINTC(),\n .CFGMSGRECEIVEDASSERTINTD(),\n .CFGMSGRECEIVEDDEASSERTINTA(),\n .CFGMSGRECEIVEDDEASSERTINTB(),\n .CFGMSGRECEIVEDDEASSERTINTC(),\n .CFGMSGRECEIVEDDEASSERTINTD(),\n .CFGMSGRECEIVEDERRCOR(),\n .CFGMSGRECEIVEDERRFATAL(),\n .CFGMSGRECEIVEDERRNONFATAL(),\n .CFGMSGRECEIVEDPMASNAK(),\n .CFGMSGRECEIVEDPMETO( cfg_msg_received_pme_to ),\n .CFGMSGRECEIVEDPMETOACK(),\n .CFGMSGRECEIVEDPMPME(),\n .CFGMSGRECEIVEDSETSLOTPOWERLIMIT(),\n .CFGMSGRECEIVEDUNLOCK(),\n .CFGPCIELINKSTATE( cfg_pcie_link_state ),\n .CFGPMCSRPMEEN ( cfg_pmcsr_pme_en ),\n .CFGPMCSRPMESTATUS ( cfg_pmcsr_pme_status ),\n .CFGPMCSRPOWERSTATE ( cfg_pmcsr_powerstate ),\n .CFGPMRCVASREQL1N(),\n .CFGPMRCVENTERL1N(),\n .CFGPMRCVENTERL23N(),\n .CFGPMRCVREQACKN(),\n .CFGRDWRDONEN( cfg_rd_wr_done_n ),\n .CFGSLOTCONTROLELECTROMECHILCTLPULSE(),\n .CFGTRANSACTION(),\n .CFGTRANSACTIONADDR(),\n .CFGTRANSACTIONTYPE(),\n .CFGVCTCVCMAP(),\n .CFGBYTEENN( cfg_byte_en_n ),\n .CFGDI( cfg_di ),\n .CFGDSBUSNUMBER( 8'b0 ),\n .CFGDSDEVICENUMBER( 5'b0 ),\n .CFGDSFUNCTIONNUMBER( 3'b0 ),\n .CFGDSN( cfg_dsn ),\n .CFGDWADDR( cfg_dwaddr ),\n .CFGERRACSN( 1'b1 ),\n .CFGERRAERHEADERLOG( 128'h0 ),\n .CFGERRCORN( cfg_err_cor_n ),\n .CFGERRCPLABORTN( cfg_err_cpl_abort_n ),\n .CFGERRCPLTIMEOUTN( cfg_err_cpl_timeout_n ),\n .CFGERRCPLUNEXPECTN( cfg_err_cpl_unexpect_n ),\n .CFGERRECRCN( cfg_err_ecrc_n ),\n .CFGERRLOCKEDN( cfg_err_locked_n ),\n .CFGERRPOSTEDN( cfg_err_posted_n ),\n .CFGERRTLPCPLHEADER( cfg_err_tlp_cpl_header ),\n .CFGERRURN( cfg_err_ur_n ),\n .CFGINTERRUPTASSERTN( cfg_interrupt_assert_n ),\n .CFGINTERRUPTDI( cfg_interrupt_di ),\n .CFGINTERRUPTN( cfg_interrupt_n ),\n .CFGPMDIRECTASPML1N( 1'b1 ),\n .CFGPMSENDPMACKN( 1'b1 ),\n .CFGPMSENDPMETON( 1'b1 ),\n .CFGPMSENDPMNAKN( 1'b1 ),\n .CFGPMTURNOFFOKN( cfg_turnoff_ok_n ),\n .CFGPMWAKEN( cfg_pm_wake_n ),\n .CFGPORTNUMBER( 8'h0 ),\n .CFGRDENN( cfg_rd_en_n ),\n .CFGTRNPENDINGN( cfg_trn_pending_n ),\n .CFGWRENN( cfg_wr_en_n ),\n .CFGWRREADONLYN( 1'b1 ),\n .CFGWRRW1CASRWN( 1'b1 ),\n\n .PLINITIALLINKWIDTH( pl_initial_link_width ),\n .PLLANEREVERSALMODE( pl_lane_reversal_mode ),\n .PLLINKGEN2CAP( pl_link_gen2_capable ),\n .PLLINKPARTNERGEN2SUPPORTED( pl_link_partner_gen2_supported ),\n .PLLINKUPCFGCAP( pl_link_upcfg_capable ),\n .PLLTSSMSTATE( pl_ltssm_state ),\n .PLPHYLNKUPN( ), // Debug\n .PLRECEIVEDHOTRST( pl_received_hot_rst ),\n .PLRXPMSTATE(), // Debug\n .PLSELLNKRATE( pl_sel_link_rate ),\n .PLSELLNKWIDTH( pl_sel_link_width ),\n .PLTXPMSTATE(), // Debug\n .PLDIRECTEDLINKAUTON( pl_directed_link_auton ),\n .PLDIRECTEDLINKCHANGE( pl_directed_link_change ),\n .PLDIRECTEDLINKSPEED( pl_directed_link_speed ),\n .PLDIRECTEDLINKWIDTH( pl_directed_link_width ),\n .PLDOWNSTREAMDEEMPHSOURCE( 1'b1 ),\n .PLUPSTREAMPREFERDEEMPH( pl_upstream_prefer_deemph ),\n .PLTRANSMITHOTRST( 1'b0 ),\n\n .DBGSCLRA(),\n .DBGSCLRB(),\n .DBGSCLRC(),\n .DBGSCLRD(),\n .DBGSCLRE(),\n .DBGSCLRF(),\n .DBGSCLRG(),\n .DBGSCLRH(),\n .DBGSCLRI(),\n .DBGSCLRJ(),\n .DBGSCLRK(),\n .DBGVECA(),\n .DBGVECB(),\n .DBGVECC(),\n .PLDBGVEC(),\n .DBGMODE( 2'b0 ),\n .DBGSUBMODE( 1'b0 ),\n .PLDBGMODE( 3'b0 ),\n\n .PCIEDRPDO(),\n .PCIEDRPDRDY(),\n .PCIEDRPCLK(1'b0),\n .PCIEDRPDADDR(9'b0),\n .PCIEDRPDEN(1'b0),\n .PCIEDRPDI(16'b0),\n .PCIEDRPDWE(1'b0),\n\n .GTPLLLOCK( gt_pll_lock ),\n .PIPECLK( pipe_clk ),\n .USERCLK( user_clk_out ),\n .DRPCLK(drp_clk),\n .CLOCKLOCKED( clock_locked ),\n .TxOutClk(TxOutClk),\n .TRNRDLLPDATA(trn_rdllp_data),\n .TRNRDLLPSRCRDYN(trn_rdllp_src_rdy_n)\n\n\n\n);\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/pcie_gtx_v6.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : pcie_gtx_v6.v\n// Version : 2.4\n//-- Description: GTX module for Virtex6 PCIe Block\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns/1ns\n\nmodule pcie_gtx_v6 #\n(\n\n parameter TCQ = 1, // clock to out delay model\n parameter NO_OF_LANES = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8\n parameter LINK_CAP_MAX_LINK_SPEED = 4'h1, // 1 - Gen1, 2 - Gen2\n parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz\n parameter PL_FAST_TRAIN = \"FALSE\"\n)\n(\n // Pipe Per-Link Signals\n input wire pipe_tx_rcvr_det ,\n input wire pipe_tx_reset ,\n input wire pipe_tx_rate ,\n input wire pipe_tx_deemph ,\n input wire [2:0] pipe_tx_margin ,\n input wire pipe_tx_swing ,\n\n // Pipe Per-Lane Signals - Lane 0\n output wire [ 1:0] pipe_rx0_char_is_k ,\n output wire [15:0] pipe_rx0_data ,\n output wire pipe_rx0_valid ,\n output wire pipe_rx0_chanisaligned ,\n output wire [ 2:0] pipe_rx0_status ,\n output wire pipe_rx0_phy_status ,\n output wire pipe_rx0_elec_idle ,\n input wire pipe_rx0_polarity ,\n input wire pipe_tx0_compliance ,\n input wire [ 1:0] pipe_tx0_char_is_k ,\n input wire [15:0] pipe_tx0_data ,\n input wire pipe_tx0_elec_idle ,\n input wire [ 1:0] pipe_tx0_powerdown ,\n\n // Pipe Per-Lane Signals - Lane 1\n output wire [ 1:0] pipe_rx1_char_is_k ,\n output wire [15:0] pipe_rx1_data ,\n output wire pipe_rx1_valid ,\n output wire pipe_rx1_chanisaligned ,\n output wire [ 2:0] pipe_rx1_status ,\n output wire pipe_rx1_phy_status ,\n output wire pipe_rx1_elec_idle ,\n input wire pipe_rx1_polarity ,\n input wire pipe_tx1_compliance ,\n input wire [ 1:0] pipe_tx1_char_is_k ,\n input wire [15:0] pipe_tx1_data ,\n input wire pipe_tx1_elec_idle ,\n input wire [ 1:0] pipe_tx1_powerdown ,\n\n // Pipe Per-Lane Signals - Lane 2\n output wire [ 1:0] pipe_rx2_char_is_k ,\n output wire [15:0] pipe_rx2_data ,\n output wire pipe_rx2_valid ,\n output wire pipe_rx2_chanisaligned ,\n output wire [ 2:0] pipe_rx2_status ,\n output wire pipe_rx2_phy_status ,\n output wire pipe_rx2_elec_idle ,\n input wire pipe_rx2_polarity ,\n input wire pipe_tx2_compliance ,\n input wire [ 1:0] pipe_tx2_char_is_k ,\n input wire [15:0] pipe_tx2_data ,\n input wire pipe_tx2_elec_idle ,\n input wire [ 1:0] pipe_tx2_powerdown ,\n\n // Pipe Per-Lane Signals - Lane 3\n output wire [ 1:0] pipe_rx3_char_is_k ,\n output wire [15:0] pipe_rx3_data ,\n output wire pipe_rx3_valid ,\n output wire pipe_rx3_chanisaligned ,\n output wire [ 2:0] pipe_rx3_status ,\n output wire pipe_rx3_phy_status ,\n output wire pipe_rx3_elec_idle ,\n input wire pipe_rx3_polarity ,\n input wire pipe_tx3_compliance ,\n input wire [ 1:0] pipe_tx3_char_is_k ,\n input wire [15:0] pipe_tx3_data ,\n input wire pipe_tx3_elec_idle ,\n input wire [ 1:0] pipe_tx3_powerdown ,\n\n // Pipe Per-Lane Signals - Lane 4\n output wire [ 1:0] pipe_rx4_char_is_k ,\n output wire [15:0] pipe_rx4_data ,\n output wire pipe_rx4_valid ,\n output wire pipe_rx4_chanisaligned ,\n output wire [ 2:0] pipe_rx4_status ,\n output wire pipe_rx4_phy_status ,\n output wire pipe_rx4_elec_idle ,\n input wire pipe_rx4_polarity ,\n input wire pipe_tx4_compliance ,\n input wire [ 1:0] pipe_tx4_char_is_k ,\n input wire [15:0] pipe_tx4_data ,\n input wire pipe_tx4_elec_idle ,\n input wire [ 1:0] pipe_tx4_powerdown ,\n\n // Pipe Per-Lane Signals - Lane 5\n output wire [ 1:0] pipe_rx5_char_is_k ,\n output wire [15:0] pipe_rx5_data ,\n output wire pipe_rx5_valid ,\n output wire pipe_rx5_chanisaligned ,\n output wire [ 2:0] pipe_rx5_status ,\n output wire pipe_rx5_phy_status ,\n output wire pipe_rx5_elec_idle ,\n input wire pipe_rx5_polarity ,\n input wire pipe_tx5_compliance ,\n input wire [ 1:0] pipe_tx5_char_is_k ,\n input wire [15:0] pipe_tx5_data ,\n input wire pipe_tx5_elec_idle ,\n input wire [ 1:0] pipe_tx5_powerdown ,\n\n // Pipe Per-Lane Signals - Lane 6\n output wire [ 1:0] pipe_rx6_char_is_k ,\n output wire [15:0] pipe_rx6_data ,\n output wire pipe_rx6_valid ,\n output wire pipe_rx6_chanisaligned ,\n output wire [ 2:0] pipe_rx6_status ,\n output wire pipe_rx6_phy_status ,\n output wire pipe_rx6_elec_idle ,\n input wire pipe_rx6_polarity ,\n input wire pipe_tx6_compliance ,\n input wire [ 1:0] pipe_tx6_char_is_k ,\n input wire [15:0] pipe_tx6_data ,\n input wire pipe_tx6_elec_idle ,\n input wire [ 1:0] pipe_tx6_powerdown ,\n\n // Pipe Per-Lane Signals - Lane 7\n output wire [ 1:0] pipe_rx7_char_is_k ,\n output wire [15:0] pipe_rx7_data ,\n output wire pipe_rx7_valid ,\n output wire pipe_rx7_chanisaligned ,\n output wire [ 2:0] pipe_rx7_status ,\n output wire pipe_rx7_phy_status ,\n output wire pipe_rx7_elec_idle ,\n input wire pipe_rx7_polarity ,\n input wire pipe_tx7_compliance ,\n input wire [ 1:0] pipe_tx7_char_is_k ,\n input wire [15:0] pipe_tx7_data ,\n input wire pipe_tx7_elec_idle ,\n input wire [ 1:0] pipe_tx7_powerdown ,\n\n // PCI Express signals\n output wire [ (NO_OF_LANES-1):0] pci_exp_txn ,\n output wire [ (NO_OF_LANES-1):0] pci_exp_txp ,\n input wire [ (NO_OF_LANES-1):0] pci_exp_rxn ,\n input wire [ (NO_OF_LANES-1):0] pci_exp_rxp ,\n\n // Non PIPE signals\n input wire sys_clk ,\n input wire sys_rst_n ,\n input wire pipe_clk ,\n input wire drp_clk ,\n input wire clock_locked ,\n\n output wire gt_pll_lock ,\n input wire [ 5:0] pl_ltssm_state ,\n output reg phy_rdy_n ,\n output wire TxOutClk\n);\n\n\n wire [ 7:0] gt_rx_phy_status_wire ;\n wire [ 7:0] gt_rxchanisaligned_wire ;\n wire [127:0] gt_rx_data_k_wire ;\n wire [127:0] gt_rx_data_wire ;\n wire [ 7:0] gt_rx_elec_idle_wire ;\n wire [ 23:0] gt_rx_status_wire ;\n wire [ 7:0] gt_rx_valid_wire ;\n wire [ 7:0] gt_rx_polarity ;\n wire [ 15:0] gt_power_down ;\n wire [ 7:0] gt_tx_char_disp_mode ;\n wire [ 15:0] gt_tx_data_k ;\n wire [127:0] gt_tx_data ;\n wire gt_tx_detect_rx_loopback ;\n wire [ 7:0] gt_tx_elec_idle ;\n wire [ 7:0] gt_rx_elec_idle_reset ;\n wire [NO_OF_LANES-1:0] plllkdet;\n wire RxResetDone;\n\n reg local_pcs_reset;\n reg local_pcs_reset_done;\n reg [3:0] cnt_local_pcs_reset;\n reg [4:0] phy_rdy_pre_cnt;\n reg [5:0] pl_ltssm_state_q;\n\n wire plm_in_l0 = (pl_ltssm_state_q == 6'h16);\n wire plm_in_rl = (pl_ltssm_state_q == 6'h1c);\n wire plm_in_dt = (pl_ltssm_state_q == 6'h2d);\n wire plm_in_rs = (pl_ltssm_state_q == 6'h1f);\n\ngtx_wrapper_v6 #(\n\n .NO_OF_LANES(NO_OF_LANES),\n .REF_CLK_FREQ(REF_CLK_FREQ),\n .PL_FAST_TRAIN(PL_FAST_TRAIN)\n\n)\ngtx_v6_i (\n\n // TX\n\n .TX(pci_exp_txp[((NO_OF_LANES)-1):0]),\n .TX_(pci_exp_txn[((NO_OF_LANES)-1):0]),\n .TxData(gt_tx_data[((16*NO_OF_LANES)-1):0]),\n .TxDataK(gt_tx_data_k[((2*NO_OF_LANES)-1):0]),\n .TxElecIdle(gt_tx_elec_idle[((NO_OF_LANES)-1):0]),\n .TxCompliance(gt_tx_char_disp_mode[((NO_OF_LANES)-1):0]),\n\n // RX\n\n .RX(pci_exp_rxp[((NO_OF_LANES)-1):0]),\n .RX_(pci_exp_rxn[((NO_OF_LANES)-1):0]),\n .RxData(gt_rx_data_wire[((16*NO_OF_LANES)-1):0]),\n .RxDataK(gt_rx_data_k_wire[((2*NO_OF_LANES)-1):0]),\n .RxPolarity(gt_rx_polarity[((NO_OF_LANES)-1):0]),\n .RxValid(gt_rx_valid_wire[((NO_OF_LANES)-1):0]),\n .RxElecIdle(gt_rx_elec_idle_wire[((NO_OF_LANES)-1):0]),\n .RxStatus(gt_rx_status_wire[((3*NO_OF_LANES)-1):0]),\n\n // other\n .GTRefClkout(),\n .plm_in_l0(plm_in_l0),\n .plm_in_rl(plm_in_rl),\n .plm_in_dt(plm_in_dt),\n .plm_in_rs(plm_in_rs),\n .RxPLLLkDet(plllkdet),\n .ChanIsAligned(gt_rxchanisaligned_wire[((NO_OF_LANES)-1):0]),\n .TxDetectRx(gt_tx_detect_rx_loopback),\n .PhyStatus(gt_rx_phy_status_wire[((NO_OF_LANES)-1):0]),\n .TXPdownAsynch(~clock_locked),\n .PowerDown(gt_power_down[((2*NO_OF_LANES)-1):0]),\n .Rate(pipe_tx_rate),\n .Reset_n(clock_locked),\n .GTReset_n(sys_rst_n),\n .PCLK(pipe_clk),\n .REFCLK(sys_clk),\n .DRPCLK(drp_clk),\n .TxDeemph(pipe_tx_deemph),\n .TxMargin(pipe_tx_margin[2]),\n .TxSwing(pipe_tx_swing),\n .local_pcs_reset(local_pcs_reset),\n .RxResetDone(RxResetDone),\n .SyncDone(SyncDone),\n .TxOutClk(TxOutClk)\n);\n\nassign pipe_rx0_phy_status = gt_rx_phy_status_wire[0] ;\nassign pipe_rx1_phy_status = (NO_OF_LANES >= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0;\nassign pipe_rx2_phy_status = (NO_OF_LANES >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0;\nassign pipe_rx3_phy_status = (NO_OF_LANES >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0;\nassign pipe_rx4_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0;\nassign pipe_rx5_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0;\nassign pipe_rx6_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0;\nassign pipe_rx7_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0;\n\nassign pipe_rx0_chanisaligned = gt_rxchanisaligned_wire[0];\nassign pipe_rx1_chanisaligned = (NO_OF_LANES >= 2 ) ? gt_rxchanisaligned_wire[1] : 1'b0 ;\nassign pipe_rx2_chanisaligned = (NO_OF_LANES >= 4 ) ? gt_rxchanisaligned_wire[2] : 1'b0 ;\nassign pipe_rx3_chanisaligned = (NO_OF_LANES >= 4 ) ? gt_rxchanisaligned_wire[3] : 1'b0 ;\nassign pipe_rx4_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[4] : 1'b0 ;\nassign pipe_rx5_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[5] : 1'b0 ;\nassign pipe_rx6_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[6] : 1'b0 ;\nassign pipe_rx7_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[7] : 1'b0 ;\n\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n\nassign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]};\nassign pipe_rx1_char_is_k = (NO_OF_LANES >= 2 ) ? {gt_rx_data_k_wire[3], gt_rx_data_k_wire[2]} : 2'b0 ;\nassign pipe_rx2_char_is_k = (NO_OF_LANES >= 4 ) ? {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]} : 2'b0 ;\nassign pipe_rx3_char_is_k = (NO_OF_LANES >= 4 ) ? {gt_rx_data_k_wire[7], gt_rx_data_k_wire[6]} : 2'b0 ;\nassign pipe_rx4_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]} : 2'b0 ;\nassign pipe_rx5_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[11], gt_rx_data_k_wire[10]} : 2'b0 ;\nassign pipe_rx6_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]} : 2'b0 ;\nassign pipe_rx7_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[15], gt_rx_data_k_wire[14]} : 2'b0 ;\n\nassign pipe_rx0_data = {gt_rx_data_wire[ 15: 8], gt_rx_data_wire[ 7: 0]};\nassign pipe_rx1_data = (NO_OF_LANES >= 2 ) ? {gt_rx_data_wire[31:24], gt_rx_data_wire[23:16]} : 16'h0 ;\nassign pipe_rx2_data = (NO_OF_LANES >= 4 ) ? {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]} : 16'h0 ;\nassign pipe_rx3_data = (NO_OF_LANES >= 4 ) ? {gt_rx_data_wire[63:56], gt_rx_data_wire[55:48]} : 16'h0 ;\nassign pipe_rx4_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]} : 16'h0 ;\nassign pipe_rx5_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[95:88], gt_rx_data_wire[87:80]} : 16'h0 ;\nassign pipe_rx6_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]} : 16'h0 ;\nassign pipe_rx7_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[127:120], gt_rx_data_wire[119:112]} : 16'h0 ;\n\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n\nassign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0];\nassign pipe_rx1_elec_idle = (NO_OF_LANES >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1 ;\nassign pipe_rx2_elec_idle = (NO_OF_LANES >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1 ;\nassign pipe_rx3_elec_idle = (NO_OF_LANES >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1 ;\nassign pipe_rx4_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1 ;\nassign pipe_rx5_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1 ;\nassign pipe_rx6_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1 ;\nassign pipe_rx7_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1 ;\n\nassign pipe_rx0_status = gt_rx_status_wire[ 2: 0];\nassign pipe_rx1_status = (NO_OF_LANES >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0 ;\nassign pipe_rx2_status = (NO_OF_LANES >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0 ;\nassign pipe_rx3_status = (NO_OF_LANES >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0 ;\nassign pipe_rx4_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0 ;\nassign pipe_rx5_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0 ;\nassign pipe_rx6_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0 ;\nassign pipe_rx7_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0 ;\n\nassign pipe_rx0_valid = gt_rx_valid_wire[0];\nassign pipe_rx1_valid = (NO_OF_LANES >= 2 ) ? gt_rx_valid_wire[1] : 1'b0 ;\nassign pipe_rx2_valid = (NO_OF_LANES >= 4 ) ? gt_rx_valid_wire[2] : 1'b0 ;\nassign pipe_rx3_valid = (NO_OF_LANES >= 4 ) ? gt_rx_valid_wire[3] : 1'b0 ;\nassign pipe_rx4_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[4] : 1'b0 ;\nassign pipe_rx5_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[5] : 1'b0 ;\nassign pipe_rx6_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[6] : 1'b0 ;\nassign pipe_rx7_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[7] : 1'b0 ;\n\nassign gt_rx_polarity[0] = pipe_rx0_polarity;\nassign gt_rx_polarity[1] = pipe_rx1_polarity;\nassign gt_rx_polarity[2] = pipe_rx2_polarity;\nassign gt_rx_polarity[3] = pipe_rx3_polarity;\nassign gt_rx_polarity[4] = pipe_rx4_polarity;\nassign gt_rx_polarity[5] = pipe_rx5_polarity;\nassign gt_rx_polarity[6] = pipe_rx6_polarity;\nassign gt_rx_polarity[7] = pipe_rx7_polarity;\n\nassign gt_power_down[ 1: 0] = pipe_tx0_powerdown;\nassign gt_power_down[ 3: 2] = pipe_tx1_powerdown;\nassign gt_power_down[ 5: 4] = pipe_tx2_powerdown;\nassign gt_power_down[ 7: 6] = pipe_tx3_powerdown;\nassign gt_power_down[ 9: 8] = pipe_tx4_powerdown;\nassign gt_power_down[11:10] = pipe_tx5_powerdown;\nassign gt_power_down[13:12] = pipe_tx6_powerdown;\nassign gt_power_down[15:14] = pipe_tx7_powerdown;\n\nassign gt_tx_char_disp_mode = {pipe_tx7_compliance,\n pipe_tx6_compliance,\n pipe_tx5_compliance,\n pipe_tx4_compliance,\n pipe_tx3_compliance,\n pipe_tx2_compliance,\n pipe_tx1_compliance,\n pipe_tx0_compliance};\n\n\nassign gt_tx_data_k = {pipe_tx7_char_is_k,\n pipe_tx6_char_is_k,\n pipe_tx5_char_is_k,\n pipe_tx4_char_is_k,\n pipe_tx3_char_is_k,\n pipe_tx2_char_is_k,\n pipe_tx1_char_is_k,\n pipe_tx0_char_is_k};\n\nassign gt_tx_data = {pipe_tx7_data,\n pipe_tx6_data,\n pipe_tx5_data,\n pipe_tx4_data,\n pipe_tx3_data,\n pipe_tx2_data,\n pipe_tx1_data,\n pipe_tx0_data};\n\nassign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det;\n\nassign gt_tx_elec_idle = {pipe_tx7_elec_idle,\n pipe_tx6_elec_idle,\n pipe_tx5_elec_idle,\n pipe_tx4_elec_idle,\n pipe_tx3_elec_idle,\n pipe_tx2_elec_idle,\n pipe_tx1_elec_idle,\n pipe_tx0_elec_idle};\n\nassign gt_pll_lock = &plllkdet[NO_OF_LANES-1:0] | ~phy_rdy_pre_cnt[4];\n\n// Asserted after all workarounds have completed.\n\nalways @(posedge pipe_clk or negedge clock_locked) begin\n\n if (!clock_locked) begin\n\n phy_rdy_n <= #TCQ 1'b1;\n\n end else begin\n\n if (~&plllkdet[NO_OF_LANES-1:0])\n phy_rdy_n <= #TCQ 1'b1;\n else if (local_pcs_reset_done && RxResetDone && phy_rdy_n && SyncDone)\n phy_rdy_n <= #TCQ 1'b0;\n\n end\n\nend\n\n// Handle the warm reset case, where sys_rst_n is asseted when\n// phy_rdy_n is asserted. phy_rdy_n is to be de-asserted\n// before gt_pll_lock is de-asserted so that synnchronous\n// logic see reset de-asset before clock is lost.\n\nalways @(posedge pipe_clk or negedge clock_locked) begin\n\n if (!clock_locked) begin\n\n phy_rdy_pre_cnt <= #TCQ 5'b11111;\n\n end else begin\n\n if (gt_pll_lock && phy_rdy_n)\n phy_rdy_pre_cnt <= #TCQ phy_rdy_pre_cnt + 1'b1;\n\n end\n\nend\n\nalways @(posedge pipe_clk or negedge clock_locked) begin\n\n if (!clock_locked) begin\n\n cnt_local_pcs_reset <= #TCQ 4'hF;\n local_pcs_reset <= #TCQ 1'b0;\n local_pcs_reset_done <= #TCQ 1'b0;\n\n end else begin\n\n if ((local_pcs_reset == 1'b0) && (cnt_local_pcs_reset == 4'hF))\n local_pcs_reset <= #TCQ 1'b1;\n else if ((local_pcs_reset == 1'b1) && (cnt_local_pcs_reset != 4'h0)) begin\n local_pcs_reset <= #TCQ 1'b1;\n cnt_local_pcs_reset <= #TCQ cnt_local_pcs_reset - 1'b1;\n end else if ((local_pcs_reset == 1'b1) && (cnt_local_pcs_reset == 4'h0)) begin\n local_pcs_reset <= #TCQ 1'b0;\n local_pcs_reset_done <= #TCQ 1'b1;\n end\n\n end\n\nend\n\nalways @(posedge pipe_clk or negedge clock_locked) begin\n\n if (!clock_locked)\n pl_ltssm_state_q <= #TCQ 6'b0;\n else\n pl_ltssm_state_q <= #TCQ pl_ltssm_state;\n\nend\n\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/pcie_pipe_lane_v6.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : pcie_pipe_lane_v6.v\n// Version : 2.4\n//--\n//-- Description: PIPE per lane module for Virtex6 PCIe Block\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns/1ns\n\nmodule pcie_pipe_lane_v6 #\n(\n parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages\n parameter TCQ = 1 // clock to out delay model\n)\n(\n output wire [ 1:0] pipe_rx_char_is_k_o ,\n output wire [15:0] pipe_rx_data_o ,\n output wire pipe_rx_valid_o ,\n output wire pipe_rx_chanisaligned_o ,\n output wire [ 2:0] pipe_rx_status_o ,\n output wire pipe_rx_phy_status_o ,\n output wire pipe_rx_elec_idle_o ,\n input wire pipe_rx_polarity_i ,\n input wire pipe_tx_compliance_i ,\n input wire [ 1:0] pipe_tx_char_is_k_i ,\n input wire [15:0] pipe_tx_data_i ,\n input wire pipe_tx_elec_idle_i ,\n input wire [ 1:0] pipe_tx_powerdown_i , \n\n input wire [ 1:0] pipe_rx_char_is_k_i ,\n input wire [15:0] pipe_rx_data_i ,\n input wire pipe_rx_valid_i ,\n input wire pipe_rx_chanisaligned_i ,\n input wire [ 2:0] pipe_rx_status_i ,\n input wire pipe_rx_phy_status_i ,\n input wire pipe_rx_elec_idle_i ,\n output wire pipe_rx_polarity_o ,\n output wire pipe_tx_compliance_o ,\n output wire [ 1:0] pipe_tx_char_is_k_o ,\n output wire [15:0] pipe_tx_data_o ,\n output wire pipe_tx_elec_idle_o ,\n output wire [ 1:0] pipe_tx_powerdown_o , \n \n input wire pipe_clk , \n input wire rst_n \n);\n\n//******************************************************************//\n// Reality check. //\n//******************************************************************//\n\n\n reg [ 1:0] pipe_rx_char_is_k_q ;\n reg [15:0] pipe_rx_data_q ;\n reg pipe_rx_valid_q ;\n reg pipe_rx_chanisaligned_q ;\n reg [ 2:0] pipe_rx_status_q ;\n reg pipe_rx_phy_status_q ;\n reg pipe_rx_elec_idle_q ;\n \n reg pipe_rx_polarity_q ;\n reg pipe_tx_compliance_q ;\n reg [ 1:0] pipe_tx_char_is_k_q ;\n reg [15:0] pipe_tx_data_q ;\n reg pipe_tx_elec_idle_q ;\n reg [ 1:0] pipe_tx_powerdown_q ; \n \n reg [ 1:0] pipe_rx_char_is_k_qq ;\n reg [15:0] pipe_rx_data_qq ;\n reg pipe_rx_valid_qq ;\n reg pipe_rx_chanisaligned_qq;\n reg [ 2:0] pipe_rx_status_qq ;\n reg pipe_rx_phy_status_qq ;\n reg pipe_rx_elec_idle_qq ;\n\n reg pipe_rx_polarity_qq ;\n reg pipe_tx_compliance_qq ;\n reg [ 1:0] pipe_tx_char_is_k_qq ;\n reg [15:0] pipe_tx_data_qq ;\n reg pipe_tx_elec_idle_qq ;\n reg [ 1:0] pipe_tx_powerdown_qq ; \n\n generate\n\n if (PIPE_PIPELINE_STAGES == 0) begin\n\n assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i;\n assign pipe_rx_data_o = pipe_rx_data_i;\n assign pipe_rx_valid_o = pipe_rx_valid_i;\n assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_i;\n assign pipe_rx_status_o = pipe_rx_status_i;\n assign pipe_rx_phy_status_o = pipe_rx_phy_status_i;\n assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i;\n \n assign pipe_rx_polarity_o = pipe_rx_polarity_i;\n assign pipe_tx_compliance_o = pipe_tx_compliance_i;\n assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i;\n assign pipe_tx_data_o = pipe_tx_data_i;\n assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i;\n assign pipe_tx_powerdown_o = pipe_tx_powerdown_i;\n\n end else if (PIPE_PIPELINE_STAGES == 1) begin\n\n always @(posedge pipe_clk) begin\n\n if (rst_n) begin\n\n pipe_rx_char_is_k_q <= #TCQ 0;\n pipe_rx_data_q <= #TCQ 0;\n pipe_rx_valid_q <= #TCQ 0;\n pipe_rx_chanisaligned_q <= #TCQ 0;\n pipe_rx_status_q <= #TCQ 0;\n pipe_rx_phy_status_q <= #TCQ 0;\n pipe_rx_elec_idle_q <= #TCQ 0;\n \n pipe_rx_polarity_q <= #TCQ 0;\n pipe_tx_compliance_q <= #TCQ 0;\n pipe_tx_char_is_k_q <= #TCQ 0;\n pipe_tx_data_q <= #TCQ 0;\n pipe_tx_elec_idle_q <= #TCQ 1'b1;\n pipe_tx_powerdown_q <= #TCQ 2'b10;\n\n end else begin\n \n pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i;\n pipe_rx_data_q <= #TCQ pipe_rx_data_i;\n pipe_rx_valid_q <= #TCQ pipe_rx_valid_i;\n pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i;\n pipe_rx_status_q <= #TCQ pipe_rx_status_i;\n pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i;\n pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i;\n \n pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i;\n pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i;\n pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i;\n pipe_tx_data_q <= #TCQ pipe_tx_data_i;\n pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i;\n pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i;\n\n end\n \n end\n\n assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_q;\n assign pipe_rx_data_o = pipe_rx_data_q;\n assign pipe_rx_valid_o = pipe_rx_valid_q;\n assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_q;\n assign pipe_rx_status_o = pipe_rx_status_q;\n assign pipe_rx_phy_status_o = pipe_rx_phy_status_q;\n assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_q;\n\n assign pipe_rx_polarity_o = pipe_rx_polarity_q;\n assign pipe_tx_compliance_o = pipe_tx_compliance_q;\n assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_q;\n assign pipe_tx_data_o = pipe_tx_data_q;\n assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_q;\n assign pipe_tx_powerdown_o = pipe_tx_powerdown_q;\n\n end else if (PIPE_PIPELINE_STAGES == 2) begin\n\n always @(posedge pipe_clk) begin\n\n if (rst_n) begin\n\n pipe_rx_char_is_k_q <= #TCQ 0;\n pipe_rx_data_q <= #TCQ 0;\n pipe_rx_valid_q <= #TCQ 0;\n pipe_rx_chanisaligned_q <= #TCQ 0;\n pipe_rx_status_q <= #TCQ 0;\n pipe_rx_phy_status_q <= #TCQ 0;\n pipe_rx_elec_idle_q <= #TCQ 0;\n \n pipe_rx_polarity_q <= #TCQ 0;\n pipe_tx_compliance_q <= #TCQ 0;\n pipe_tx_char_is_k_q <= #TCQ 0;\n pipe_tx_data_q <= #TCQ 0;\n pipe_tx_elec_idle_q <= #TCQ 1'b1;\n pipe_tx_powerdown_q <= #TCQ 2'b10;\n \n pipe_rx_char_is_k_qq <= #TCQ 0;\n pipe_rx_data_qq <= #TCQ 0;\n pipe_rx_valid_qq <= #TCQ 0;\n pipe_rx_chanisaligned_qq <= #TCQ 0;\n pipe_rx_status_qq <= #TCQ 0;\n pipe_rx_phy_status_qq <= #TCQ 0;\n pipe_rx_elec_idle_qq <= #TCQ 0;\n \n pipe_rx_polarity_qq <= #TCQ 0;\n pipe_tx_compliance_qq <= #TCQ 0;\n pipe_tx_char_is_k_qq <= #TCQ 0;\n pipe_tx_data_qq <= #TCQ 0;\n pipe_tx_elec_idle_qq <= #TCQ 1'b1;\n pipe_tx_powerdown_qq <= #TCQ 2'b10;\n\n end else begin\n \n pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i;\n pipe_rx_data_q <= #TCQ pipe_rx_data_i;\n pipe_rx_valid_q <= #TCQ pipe_rx_valid_i;\n pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i;\n pipe_rx_status_q <= #TCQ pipe_rx_status_i;\n pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i;\n pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i;\n \n pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i;\n pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i;\n pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i;\n pipe_tx_data_q <= #TCQ pipe_tx_data_i;\n pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i;\n pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i;\n \n pipe_rx_char_is_k_qq <= #TCQ pipe_rx_char_is_k_q;\n pipe_rx_data_qq <= #TCQ pipe_rx_data_q;\n pipe_rx_valid_qq <= #TCQ pipe_rx_valid_q;\n pipe_rx_chanisaligned_qq <= #TCQ pipe_rx_chanisaligned_q;\n pipe_rx_status_qq <= #TCQ pipe_rx_status_q;\n pipe_rx_phy_status_qq <= #TCQ pipe_rx_phy_status_q;\n pipe_rx_elec_idle_qq <= #TCQ pipe_rx_elec_idle_q;\n \n pipe_rx_polarity_qq <= #TCQ pipe_rx_polarity_q;\n pipe_tx_compliance_qq <= #TCQ pipe_tx_compliance_q;\n pipe_tx_char_is_k_qq <= #TCQ pipe_tx_char_is_k_q;\n pipe_tx_data_qq <= #TCQ pipe_tx_data_q;\n pipe_tx_elec_idle_qq <= #TCQ pipe_tx_elec_idle_q;\n pipe_tx_powerdown_qq <= #TCQ pipe_tx_powerdown_q;\n\n end\n \n end\n\n assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_qq;\n assign pipe_rx_data_o = pipe_rx_data_qq;\n assign pipe_rx_valid_o = pipe_rx_valid_qq;\n assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_qq;\n assign pipe_rx_status_o = pipe_rx_status_qq;\n assign pipe_rx_phy_status_o = pipe_rx_phy_status_qq;\n assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_qq;\n\n assign pipe_rx_polarity_o = pipe_rx_polarity_qq;\n assign pipe_tx_compliance_o = pipe_tx_compliance_qq;\n assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_qq;\n assign pipe_tx_data_o = pipe_tx_data_qq;\n assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_qq;\n assign pipe_tx_powerdown_o = pipe_tx_powerdown_qq;\n\n end\n\n endgenerate\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/pcie_pipe_misc_v6.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : pcie_pipe_misc_v6.v\n// Version : 2.4\n//--\n//-- Description: Misc PIPE module for Virtex6 PCIe Block\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns/1ns\n\nmodule pcie_pipe_misc_v6 #\n(\n parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages\n)\n(\n\n input wire pipe_tx_rcvr_det_i ,\n input wire pipe_tx_reset_i ,\n input wire pipe_tx_rate_i ,\n input wire pipe_tx_deemph_i ,\n input wire [2:0] pipe_tx_margin_i ,\n input wire pipe_tx_swing_i ,\n\n output wire pipe_tx_rcvr_det_o ,\n output wire pipe_tx_reset_o ,\n output wire pipe_tx_rate_o ,\n output wire pipe_tx_deemph_o ,\n output wire [2:0] pipe_tx_margin_o ,\n output wire pipe_tx_swing_o ,\n \n input wire pipe_clk , \n input wire rst_n \n);\n\n//******************************************************************//\n// Reality check. //\n//******************************************************************//\n\n localparam TCQ = 1; // clock to out delay model\n\n reg pipe_tx_rcvr_det_q ;\n reg pipe_tx_reset_q ;\n reg pipe_tx_rate_q ;\n reg pipe_tx_deemph_q ;\n reg [2:0] pipe_tx_margin_q ;\n reg pipe_tx_swing_q ;\n\n reg pipe_tx_rcvr_det_qq ;\n reg pipe_tx_reset_qq ;\n reg pipe_tx_rate_qq ;\n reg pipe_tx_deemph_qq ;\n reg [2:0] pipe_tx_margin_qq ;\n reg pipe_tx_swing_qq ;\n\n generate\n\n if (PIPE_PIPELINE_STAGES == 0) begin\n\n\n assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;\n assign pipe_tx_reset_o = pipe_tx_reset_i;\n assign pipe_tx_rate_o = pipe_tx_rate_i;\n assign pipe_tx_deemph_o = pipe_tx_deemph_i;\n assign pipe_tx_margin_o = pipe_tx_margin_i;\n assign pipe_tx_swing_o = pipe_tx_swing_i;\n\n end else if (PIPE_PIPELINE_STAGES == 1) begin\n\n always @(posedge pipe_clk) begin\n\n if (rst_n) begin\n\n pipe_tx_rcvr_det_q <= #TCQ 0;\n pipe_tx_reset_q <= #TCQ 1'b1;\n pipe_tx_rate_q <= #TCQ 0;\n pipe_tx_deemph_q <= #TCQ 1'b1;\n pipe_tx_margin_q <= #TCQ 0;\n pipe_tx_swing_q <= #TCQ 0;\n\n end else begin\n \n pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;\n pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;\n pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;\n pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;\n pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;\n pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;\n\n end\n \n end\n\n assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;\n assign pipe_tx_reset_o = pipe_tx_reset_q;\n assign pipe_tx_rate_o = pipe_tx_rate_q;\n assign pipe_tx_deemph_o = pipe_tx_deemph_q;\n assign pipe_tx_margin_o = pipe_tx_margin_q;\n assign pipe_tx_swing_o = pipe_tx_swing_q;\n\n end else if (PIPE_PIPELINE_STAGES == 2) begin\n\n always @(posedge pipe_clk) begin\n\n if (rst_n) begin\n\n pipe_tx_rcvr_det_q <= #TCQ 0;\n pipe_tx_reset_q <= #TCQ 1'b1;\n pipe_tx_rate_q <= #TCQ 0;\n pipe_tx_deemph_q <= #TCQ 1'b1;\n pipe_tx_margin_q <= #TCQ 0;\n pipe_tx_swing_q <= #TCQ 0;\n\n pipe_tx_rcvr_det_qq <= #TCQ 0;\n pipe_tx_reset_qq <= #TCQ 1'b1;\n pipe_tx_rate_qq <= #TCQ 0;\n pipe_tx_deemph_qq <= #TCQ 1'b1;\n pipe_tx_margin_qq <= #TCQ 0;\n pipe_tx_swing_qq <= #TCQ 0;\n\n end else begin\n \n pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;\n pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;\n pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;\n pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;\n pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;\n pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;\n\n pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;\n pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;\n pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;\n pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;\n pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;\n pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;\n\n end\n \n end\n\n assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;\n assign pipe_tx_reset_o = pipe_tx_reset_qq;\n assign pipe_tx_rate_o = pipe_tx_rate_qq;\n assign pipe_tx_deemph_o = pipe_tx_deemph_qq;\n assign pipe_tx_margin_o = pipe_tx_margin_qq;\n assign pipe_tx_swing_o = pipe_tx_swing_qq;\n\n end\n\n endgenerate\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/pcie_pipe_v6.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : pcie_pipe_v6.v\n// Version : 2.4\n//-- Description: PIPE module for Virtex6 PCIe Block\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns/1ns\n\nmodule pcie_pipe_v6 #\n(\n parameter NO_OF_LANES = 8, \n parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,\n parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages\n)\n(\n // Pipe Per-Link Signals\n input wire pipe_tx_rcvr_det_i ,\n input wire pipe_tx_reset_i , \n input wire pipe_tx_rate_i , \n input wire pipe_tx_deemph_i , \n input wire [2:0] pipe_tx_margin_i , \n input wire pipe_tx_swing_i , \n\n output wire pipe_tx_rcvr_det_o ,\n output wire pipe_tx_reset_o , \n output wire pipe_tx_rate_o , \n output wire pipe_tx_deemph_o , \n output wire [2:0] pipe_tx_margin_o , \n output wire pipe_tx_swing_o , \n \n // Pipe Per-Lane Signals - Lane 0\n output wire [ 1:0] pipe_rx0_char_is_k_o ,\n output wire [15:0] pipe_rx0_data_o ,\n output wire pipe_rx0_valid_o ,\n output wire pipe_rx0_chanisaligned_o ,\n output wire [ 2:0] pipe_rx0_status_o ,\n output wire pipe_rx0_phy_status_o ,\n output wire pipe_rx0_elec_idle_o ,\n input wire pipe_rx0_polarity_i ,\n input wire pipe_tx0_compliance_i ,\n input wire [ 1:0] pipe_tx0_char_is_k_i ,\n input wire [15:0] pipe_tx0_data_i ,\n input wire pipe_tx0_elec_idle_i ,\n input wire [ 1:0] pipe_tx0_powerdown_i , \n\n input wire [ 1:0] pipe_rx0_char_is_k_i ,\n input wire [15:0] pipe_rx0_data_i ,\n input wire pipe_rx0_valid_i ,\n input wire pipe_rx0_chanisaligned_i ,\n input wire [ 2:0] pipe_rx0_status_i ,\n input wire pipe_rx0_phy_status_i ,\n input wire pipe_rx0_elec_idle_i ,\n output wire pipe_rx0_polarity_o ,\n output wire pipe_tx0_compliance_o ,\n output wire [ 1:0] pipe_tx0_char_is_k_o ,\n output wire [15:0] pipe_tx0_data_o ,\n output wire pipe_tx0_elec_idle_o ,\n output wire [ 1:0] pipe_tx0_powerdown_o , \n \n // Pipe Per-Lane Signals - Lane 1\n output wire [ 1:0] pipe_rx1_char_is_k_o ,\n output wire [15:0] pipe_rx1_data_o ,\n output wire pipe_rx1_valid_o ,\n output wire pipe_rx1_chanisaligned_o ,\n output wire [ 2:0] pipe_rx1_status_o ,\n output wire pipe_rx1_phy_status_o ,\n output wire pipe_rx1_elec_idle_o ,\n input wire pipe_rx1_polarity_i ,\n input wire pipe_tx1_compliance_i ,\n input wire [ 1:0] pipe_tx1_char_is_k_i ,\n input wire [15:0] pipe_tx1_data_i ,\n input wire pipe_tx1_elec_idle_i ,\n input wire [ 1:0] pipe_tx1_powerdown_i , \n\n input wire [ 1:0] pipe_rx1_char_is_k_i ,\n input wire [15:0] pipe_rx1_data_i ,\n input wire pipe_rx1_valid_i ,\n input wire pipe_rx1_chanisaligned_i ,\n input wire [ 2:0] pipe_rx1_status_i ,\n input wire pipe_rx1_phy_status_i ,\n input wire pipe_rx1_elec_idle_i ,\n output wire pipe_rx1_polarity_o ,\n output wire pipe_tx1_compliance_o ,\n output wire [ 1:0] pipe_tx1_char_is_k_o ,\n output wire [15:0] pipe_tx1_data_o ,\n output wire pipe_tx1_elec_idle_o ,\n output wire [ 1:0] pipe_tx1_powerdown_o , \n\n // Pipe Per-Lane Signals - Lane 2\n output wire [ 1:0] pipe_rx2_char_is_k_o ,\n output wire [15:0] pipe_rx2_data_o ,\n output wire pipe_rx2_valid_o ,\n output wire pipe_rx2_chanisaligned_o ,\n output wire [ 2:0] pipe_rx2_status_o ,\n output wire pipe_rx2_phy_status_o ,\n output wire pipe_rx2_elec_idle_o ,\n input wire pipe_rx2_polarity_i ,\n input wire pipe_tx2_compliance_i ,\n input wire [ 1:0] pipe_tx2_char_is_k_i ,\n input wire [15:0] pipe_tx2_data_i ,\n input wire pipe_tx2_elec_idle_i ,\n input wire [ 1:0] pipe_tx2_powerdown_i , \n\n input wire [ 1:0] pipe_rx2_char_is_k_i ,\n input wire [15:0] pipe_rx2_data_i ,\n input wire pipe_rx2_valid_i ,\n input wire pipe_rx2_chanisaligned_i ,\n input wire [ 2:0] pipe_rx2_status_i ,\n input wire pipe_rx2_phy_status_i ,\n input wire pipe_rx2_elec_idle_i ,\n output wire pipe_rx2_polarity_o ,\n output wire pipe_tx2_compliance_o ,\n output wire [ 1:0] pipe_tx2_char_is_k_o ,\n output wire [15:0] pipe_tx2_data_o ,\n output wire pipe_tx2_elec_idle_o ,\n output wire [ 1:0] pipe_tx2_powerdown_o , \n\n // Pipe Per-Lane Signals - Lane 3\n output wire [ 1:0] pipe_rx3_char_is_k_o ,\n output wire [15:0] pipe_rx3_data_o ,\n output wire pipe_rx3_valid_o ,\n output wire pipe_rx3_chanisaligned_o ,\n output wire [ 2:0] pipe_rx3_status_o ,\n output wire pipe_rx3_phy_status_o ,\n output wire pipe_rx3_elec_idle_o ,\n input wire pipe_rx3_polarity_i ,\n input wire pipe_tx3_compliance_i ,\n input wire [ 1:0] pipe_tx3_char_is_k_i ,\n input wire [15:0] pipe_tx3_data_i ,\n input wire pipe_tx3_elec_idle_i ,\n input wire [ 1:0] pipe_tx3_powerdown_i , \n\n input wire [ 1:0] pipe_rx3_char_is_k_i ,\n input wire [15:0] pipe_rx3_data_i ,\n input wire pipe_rx3_valid_i ,\n input wire pipe_rx3_chanisaligned_i ,\n input wire [ 2:0] pipe_rx3_status_i ,\n input wire pipe_rx3_phy_status_i ,\n input wire pipe_rx3_elec_idle_i ,\n output wire pipe_rx3_polarity_o ,\n output wire pipe_tx3_compliance_o ,\n output wire [ 1:0] pipe_tx3_char_is_k_o ,\n output wire [15:0] pipe_tx3_data_o ,\n output wire pipe_tx3_elec_idle_o ,\n output wire [ 1:0] pipe_tx3_powerdown_o , \n \n // Pipe Per-Lane Signals - Lane 4\n output wire [ 1:0] pipe_rx4_char_is_k_o ,\n output wire [15:0] pipe_rx4_data_o ,\n output wire pipe_rx4_valid_o ,\n output wire pipe_rx4_chanisaligned_o ,\n output wire [ 2:0] pipe_rx4_status_o ,\n output wire pipe_rx4_phy_status_o ,\n output wire pipe_rx4_elec_idle_o ,\n input wire pipe_rx4_polarity_i ,\n input wire pipe_tx4_compliance_i ,\n input wire [ 1:0] pipe_tx4_char_is_k_i ,\n input wire [15:0] pipe_tx4_data_i ,\n input wire pipe_tx4_elec_idle_i ,\n input wire [ 1:0] pipe_tx4_powerdown_i , \n\n input wire [ 1:0] pipe_rx4_char_is_k_i ,\n input wire [15:0] pipe_rx4_data_i ,\n input wire pipe_rx4_valid_i ,\n input wire pipe_rx4_chanisaligned_i ,\n input wire [ 2:0] pipe_rx4_status_i ,\n input wire pipe_rx4_phy_status_i ,\n input wire pipe_rx4_elec_idle_i ,\n output wire pipe_rx4_polarity_o ,\n output wire pipe_tx4_compliance_o ,\n output wire [ 1:0] pipe_tx4_char_is_k_o ,\n output wire [15:0] pipe_tx4_data_o ,\n output wire pipe_tx4_elec_idle_o ,\n output wire [ 1:0] pipe_tx4_powerdown_o , \n \n // Pipe Per-Lane Signals - Lane 5\n output wire [ 1:0] pipe_rx5_char_is_k_o ,\n output wire [15:0] pipe_rx5_data_o ,\n output wire pipe_rx5_valid_o ,\n output wire pipe_rx5_chanisaligned_o ,\n output wire [ 2:0] pipe_rx5_status_o ,\n output wire pipe_rx5_phy_status_o ,\n output wire pipe_rx5_elec_idle_o ,\n input wire pipe_rx5_polarity_i ,\n input wire pipe_tx5_compliance_i ,\n input wire [ 1:0] pipe_tx5_char_is_k_i ,\n input wire [15:0] pipe_tx5_data_i ,\n input wire pipe_tx5_elec_idle_i ,\n input wire [ 1:0] pipe_tx5_powerdown_i , \n\n input wire [ 1:0] pipe_rx5_char_is_k_i ,\n input wire [15:0] pipe_rx5_data_i ,\n input wire pipe_rx5_valid_i ,\n input wire pipe_rx5_chanisaligned_i ,\n input wire [ 2:0] pipe_rx5_status_i ,\n input wire pipe_rx5_phy_status_i ,\n input wire pipe_rx5_elec_idle_i ,\n output wire pipe_rx5_polarity_o ,\n output wire pipe_tx5_compliance_o ,\n output wire [ 1:0] pipe_tx5_char_is_k_o ,\n output wire [15:0] pipe_tx5_data_o ,\n output wire pipe_tx5_elec_idle_o ,\n output wire [ 1:0] pipe_tx5_powerdown_o , \n \n // Pipe Per-Lane Signals - Lane 6\n output wire [ 1:0] pipe_rx6_char_is_k_o ,\n output wire [15:0] pipe_rx6_data_o ,\n output wire pipe_rx6_valid_o ,\n output wire pipe_rx6_chanisaligned_o ,\n output wire [ 2:0] pipe_rx6_status_o ,\n output wire pipe_rx6_phy_status_o ,\n output wire pipe_rx6_elec_idle_o ,\n input wire pipe_rx6_polarity_i ,\n input wire pipe_tx6_compliance_i ,\n input wire [ 1:0] pipe_tx6_char_is_k_i ,\n input wire [15:0] pipe_tx6_data_i ,\n input wire pipe_tx6_elec_idle_i ,\n input wire [ 1:0] pipe_tx6_powerdown_i , \n\n input wire [ 1:0] pipe_rx6_char_is_k_i ,\n input wire [15:0] pipe_rx6_data_i ,\n input wire pipe_rx6_valid_i ,\n input wire pipe_rx6_chanisaligned_i ,\n input wire [ 2:0] pipe_rx6_status_i ,\n input wire pipe_rx6_phy_status_i ,\n input wire pipe_rx6_elec_idle_i ,\n output wire pipe_rx6_polarity_o ,\n output wire pipe_tx6_compliance_o ,\n output wire [ 1:0] pipe_tx6_char_is_k_o ,\n output wire [15:0] pipe_tx6_data_o ,\n output wire pipe_tx6_elec_idle_o ,\n output wire [ 1:0] pipe_tx6_powerdown_o , \n \n // Pipe Per-Lane Signals - Lane 7\n output wire [ 1:0] pipe_rx7_char_is_k_o ,\n output wire [15:0] pipe_rx7_data_o ,\n output wire pipe_rx7_valid_o ,\n output wire pipe_rx7_chanisaligned_o ,\n output wire [ 2:0] pipe_rx7_status_o ,\n output wire pipe_rx7_phy_status_o ,\n output wire pipe_rx7_elec_idle_o ,\n input wire pipe_rx7_polarity_i ,\n input wire pipe_tx7_compliance_i ,\n input wire [ 1:0] pipe_tx7_char_is_k_i ,\n input wire [15:0] pipe_tx7_data_i ,\n input wire pipe_tx7_elec_idle_i ,\n input wire [ 1:0] pipe_tx7_powerdown_i , \n\n input wire [ 1:0] pipe_rx7_char_is_k_i ,\n input wire [15:0] pipe_rx7_data_i ,\n input wire pipe_rx7_valid_i ,\n input wire pipe_rx7_chanisaligned_i ,\n input wire [ 2:0] pipe_rx7_status_i ,\n input wire pipe_rx7_phy_status_i ,\n input wire pipe_rx7_elec_idle_i ,\n output wire pipe_rx7_polarity_o ,\n output wire pipe_tx7_compliance_o ,\n output wire [ 1:0] pipe_tx7_char_is_k_o ,\n output wire [15:0] pipe_tx7_data_o ,\n output wire pipe_tx7_elec_idle_o ,\n output wire [ 1:0] pipe_tx7_powerdown_o , \n\n // Non PIPE signals\n input wire [ 5:0] pl_ltssm_state ,\n input wire pipe_clk , \n input wire rst_n \n);\n\n//******************************************************************//\n// Reality check. //\n//******************************************************************//\n\n localparam Tc2o = 1; // clock to out delay model\n\n\n wire [ 1:0] pipe_rx0_char_is_k_q ;\n wire [15:0] pipe_rx0_data_q ;\n wire [ 1:0] pipe_rx1_char_is_k_q ;\n wire [15:0] pipe_rx1_data_q ;\n wire [ 1:0] pipe_rx2_char_is_k_q ;\n wire [15:0] pipe_rx2_data_q ;\n wire [ 1:0] pipe_rx3_char_is_k_q ;\n wire [15:0] pipe_rx3_data_q ;\n wire [ 1:0] pipe_rx4_char_is_k_q ;\n wire [15:0] pipe_rx4_data_q ;\n wire [ 1:0] pipe_rx5_char_is_k_q ;\n wire [15:0] pipe_rx5_data_q ;\n wire [ 1:0] pipe_rx6_char_is_k_q ;\n wire [15:0] pipe_rx6_data_q ;\n wire [ 1:0] pipe_rx7_char_is_k_q ;\n wire [15:0] pipe_rx7_data_q ;\n\n//synthesis translate_off\n// initial begin\n// $display(\"[%t] %m NO_OF_LANES %0d PIPE_PIPELINE_STAGES %0d\", $time, NO_OF_LANES, PIPE_PIPELINE_STAGES);\n// end\n//synthesis translate_on\n \n generate\n\n pcie_pipe_misc_v6 # (\n\n .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)\n\n )\n pipe_misc_i (\n\n .pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i),\n .pipe_tx_reset_i(pipe_tx_reset_i),\n .pipe_tx_rate_i(pipe_tx_rate_i),\n .pipe_tx_deemph_i(pipe_tx_deemph_i),\n .pipe_tx_margin_i(pipe_tx_margin_i),\n .pipe_tx_swing_i(pipe_tx_swing_i),\n \n .pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o),\n .pipe_tx_reset_o(pipe_tx_reset_o),\n .pipe_tx_rate_o(pipe_tx_rate_o),\n .pipe_tx_deemph_o(pipe_tx_deemph_o),\n .pipe_tx_margin_o(pipe_tx_margin_o),\n .pipe_tx_swing_o(pipe_tx_swing_o) ,\n \n .pipe_clk(pipe_clk),\n .rst_n(rst_n)\n );\n\n\n pcie_pipe_lane_v6 # (\n\n .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)\n\n ) \n pipe_lane_0_i (\n\n .pipe_rx_char_is_k_o(pipe_rx0_char_is_k_q),\n .pipe_rx_data_o(pipe_rx0_data_q),\n .pipe_rx_valid_o(pipe_rx0_valid_o),\n .pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o),\n .pipe_rx_status_o(pipe_rx0_status_o),\n .pipe_rx_phy_status_o(pipe_rx0_phy_status_o),\n .pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o),\n .pipe_rx_polarity_i(pipe_rx0_polarity_i),\n .pipe_tx_compliance_i(pipe_tx0_compliance_i),\n .pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i),\n .pipe_tx_data_i(pipe_tx0_data_i),\n .pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i),\n .pipe_tx_powerdown_i(pipe_tx0_powerdown_i),\n \n .pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i),\n .pipe_rx_data_i(pipe_rx0_data_i),\n .pipe_rx_valid_i(pipe_rx0_valid_i),\n .pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i),\n .pipe_rx_status_i(pipe_rx0_status_i),\n .pipe_rx_phy_status_i(pipe_rx0_phy_status_i),\n .pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i),\n .pipe_rx_polarity_o(pipe_rx0_polarity_o),\n .pipe_tx_compliance_o(pipe_tx0_compliance_o),\n .pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o),\n .pipe_tx_data_o(pipe_tx0_data_o),\n .pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o),\n .pipe_tx_powerdown_o(pipe_tx0_powerdown_o),\n \n .pipe_clk(pipe_clk),\n .rst_n(rst_n)\n\n );\n\n if (NO_OF_LANES >= 2) begin\n\n pcie_pipe_lane_v6 # (\n \n .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)\n\n ) \n pipe_lane_1_i (\n\n .pipe_rx_char_is_k_o(pipe_rx1_char_is_k_q),\n .pipe_rx_data_o(pipe_rx1_data_q),\n .pipe_rx_valid_o(pipe_rx1_valid_o),\n .pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o),\n .pipe_rx_status_o(pipe_rx1_status_o),\n .pipe_rx_phy_status_o(pipe_rx1_phy_status_o),\n .pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o),\n .pipe_rx_polarity_i(pipe_rx1_polarity_i),\n .pipe_tx_compliance_i(pipe_tx1_compliance_i),\n .pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i),\n .pipe_tx_data_i(pipe_tx1_data_i),\n .pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i),\n .pipe_tx_powerdown_i(pipe_tx1_powerdown_i),\n \n .pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i),\n .pipe_rx_data_i(pipe_rx1_data_i),\n .pipe_rx_valid_i(pipe_rx1_valid_i),\n .pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i),\n .pipe_rx_status_i(pipe_rx1_status_i),\n .pipe_rx_phy_status_i(pipe_rx1_phy_status_i),\n .pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i),\n .pipe_rx_polarity_o(pipe_rx1_polarity_o),\n .pipe_tx_compliance_o(pipe_tx1_compliance_o),\n .pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o),\n .pipe_tx_data_o(pipe_tx1_data_o),\n .pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o),\n .pipe_tx_powerdown_o(pipe_tx1_powerdown_o),\n \n .pipe_clk(pipe_clk),\n .rst_n(rst_n)\n\n );\n\n end\n else begin\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n assign pipe_rx1_char_is_k_o = 2'b00;\n assign pipe_rx1_data_o = 16'h0000;\n assign pipe_rx1_valid_o = 1'b0;\n assign pipe_rx1_chanisaligned_o = 1'b0;\n assign pipe_rx1_status_o = 3'b000;\n assign pipe_rx1_phy_status_o = 1'b0;\n assign pipe_rx1_elec_idle_o = 1'b1;\n assign pipe_rx1_polarity_o = 1'b0;\n assign pipe_tx1_compliance_o = 1'b0;\n assign pipe_tx1_char_is_k_o = 2'b00;\n assign pipe_tx1_data_o = 16'h0000;\n assign pipe_tx1_elec_idle_o = 1'b1;\n assign pipe_tx1_powerdown_o = 2'b00;\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n end \n\n if (NO_OF_LANES >= 4) begin\n\n pcie_pipe_lane_v6 # (\n \n .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)\n ) \n pipe_lane_2_i (\n\n .pipe_rx_char_is_k_o(pipe_rx2_char_is_k_q),\n .pipe_rx_data_o(pipe_rx2_data_q),\n .pipe_rx_valid_o(pipe_rx2_valid_o),\n .pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o),\n .pipe_rx_status_o(pipe_rx2_status_o),\n .pipe_rx_phy_status_o(pipe_rx2_phy_status_o),\n .pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o),\n .pipe_rx_polarity_i(pipe_rx2_polarity_i),\n .pipe_tx_compliance_i(pipe_tx2_compliance_i),\n .pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i),\n .pipe_tx_data_i(pipe_tx2_data_i),\n .pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i),\n .pipe_tx_powerdown_i(pipe_tx2_powerdown_i),\n \n .pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i),\n .pipe_rx_data_i(pipe_rx2_data_i),\n .pipe_rx_valid_i(pipe_rx2_valid_i),\n .pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i),\n .pipe_rx_status_i(pipe_rx2_status_i),\n .pipe_rx_phy_status_i(pipe_rx2_phy_status_i),\n .pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i),\n .pipe_rx_polarity_o(pipe_rx2_polarity_o),\n .pipe_tx_compliance_o(pipe_tx2_compliance_o),\n .pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o),\n .pipe_tx_data_o(pipe_tx2_data_o),\n .pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o),\n .pipe_tx_powerdown_o(pipe_tx2_powerdown_o),\n \n .pipe_clk(pipe_clk),\n .rst_n(rst_n)\n\n );\n\n pcie_pipe_lane_v6 # (\n \n .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)\n\n ) \n pipe_lane_3_i (\n\n .pipe_rx_char_is_k_o(pipe_rx3_char_is_k_q),\n .pipe_rx_data_o(pipe_rx3_data_q),\n .pipe_rx_valid_o(pipe_rx3_valid_o),\n .pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o),\n .pipe_rx_status_o(pipe_rx3_status_o),\n .pipe_rx_phy_status_o(pipe_rx3_phy_status_o),\n .pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o),\n .pipe_rx_polarity_i(pipe_rx3_polarity_i),\n .pipe_tx_compliance_i(pipe_tx3_compliance_i),\n .pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i),\n .pipe_tx_data_i(pipe_tx3_data_i),\n .pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i),\n .pipe_tx_powerdown_i(pipe_tx3_powerdown_i),\n \n .pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i),\n .pipe_rx_data_i(pipe_rx3_data_i),\n .pipe_rx_valid_i(pipe_rx3_valid_i),\n .pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i),\n .pipe_rx_status_i(pipe_rx3_status_i),\n .pipe_rx_phy_status_i(pipe_rx3_phy_status_i),\n .pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i),\n .pipe_rx_polarity_o(pipe_rx3_polarity_o),\n .pipe_tx_compliance_o(pipe_tx3_compliance_o),\n .pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o),\n .pipe_tx_data_o(pipe_tx3_data_o),\n .pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o),\n .pipe_tx_powerdown_o(pipe_tx3_powerdown_o),\n \n .pipe_clk(pipe_clk),\n .rst_n(rst_n)\n\n );\n\n end\n else begin\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n assign pipe_rx2_char_is_k_o = 2'b00;\n assign pipe_rx2_data_o = 16'h0000;\n assign pipe_rx2_valid_o = 1'b0;\n assign pipe_rx2_chanisaligned_o = 1'b0;\n assign pipe_rx2_status_o = 3'b000;\n assign pipe_rx2_phy_status_o = 1'b0;\n assign pipe_rx2_elec_idle_o = 1'b1;\n assign pipe_rx2_polarity_o = 1'b0;\n assign pipe_tx2_compliance_o = 1'b0;\n assign pipe_tx2_char_is_k_o = 2'b00;\n assign pipe_tx2_data_o = 16'h0000;\n assign pipe_tx2_elec_idle_o = 1'b1;\n assign pipe_tx2_powerdown_o = 2'b00;\n\n assign pipe_rx3_char_is_k_o = 2'b00;\n assign pipe_rx3_data_o = 16'h0000;\n assign pipe_rx3_valid_o = 1'b0;\n assign pipe_rx3_chanisaligned_o = 1'b0;\n assign pipe_rx3_status_o = 3'b000;\n assign pipe_rx3_phy_status_o = 1'b0;\n assign pipe_rx3_elec_idle_o = 1'b1;\n assign pipe_rx3_polarity_o = 1'b0;\n assign pipe_tx3_compliance_o = 1'b0;\n assign pipe_tx3_char_is_k_o = 2'b00;\n assign pipe_tx3_data_o = 16'h0000;\n assign pipe_tx3_elec_idle_o = 1'b1;\n assign pipe_tx3_powerdown_o = 2'b00;\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n end \n\n if (NO_OF_LANES >= 8) begin\n\n pcie_pipe_lane_v6 # (\n \n .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)\n\n ) \n pipe_lane_4_i (\n\n .pipe_rx_char_is_k_o(pipe_rx4_char_is_k_q),\n .pipe_rx_data_o(pipe_rx4_data_q),\n .pipe_rx_valid_o(pipe_rx4_valid_o),\n .pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o),\n .pipe_rx_status_o(pipe_rx4_status_o),\n .pipe_rx_phy_status_o(pipe_rx4_phy_status_o),\n .pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o),\n .pipe_rx_polarity_i(pipe_rx4_polarity_i),\n .pipe_tx_compliance_i(pipe_tx4_compliance_i),\n .pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i),\n .pipe_tx_data_i(pipe_tx4_data_i),\n .pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i),\n .pipe_tx_powerdown_i(pipe_tx4_powerdown_i),\n \n .pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i),\n .pipe_rx_data_i(pipe_rx4_data_i),\n .pipe_rx_valid_i(pipe_rx4_valid_i),\n .pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i),\n .pipe_rx_status_i(pipe_rx4_status_i),\n .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),\n .pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),\n .pipe_rx_polarity_o(pipe_rx4_polarity_o),\n .pipe_tx_compliance_o(pipe_tx4_compliance_o),\n .pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o),\n .pipe_tx_data_o(pipe_tx4_data_o),\n .pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o),\n .pipe_tx_powerdown_o(pipe_tx4_powerdown_o),\n \n .pipe_clk(pipe_clk),\n .rst_n(rst_n)\n\n );\n\n pcie_pipe_lane_v6 # (\n \n .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)\n\n ) \n pipe_lane_5_i (\n\n .pipe_rx_char_is_k_o(pipe_rx5_char_is_k_q),\n .pipe_rx_data_o(pipe_rx5_data_q),\n .pipe_rx_valid_o(pipe_rx5_valid_o),\n .pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o),\n .pipe_rx_status_o(pipe_rx5_status_o),\n .pipe_rx_phy_status_o(pipe_rx5_phy_status_o),\n .pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o),\n .pipe_rx_polarity_i(pipe_rx5_polarity_i),\n .pipe_tx_compliance_i(pipe_tx5_compliance_i),\n .pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i),\n .pipe_tx_data_i(pipe_tx5_data_i),\n .pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i),\n .pipe_tx_powerdown_i(pipe_tx5_powerdown_i),\n \n .pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i),\n .pipe_rx_data_i(pipe_rx5_data_i),\n .pipe_rx_valid_i(pipe_rx5_valid_i),\n .pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i),\n .pipe_rx_status_i(pipe_rx5_status_i),\n .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),\n .pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),\n .pipe_rx_polarity_o(pipe_rx5_polarity_o),\n .pipe_tx_compliance_o(pipe_tx5_compliance_o),\n .pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o),\n .pipe_tx_data_o(pipe_tx5_data_o),\n .pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o),\n .pipe_tx_powerdown_o(pipe_tx5_powerdown_o),\n \n .pipe_clk(pipe_clk),\n .rst_n(rst_n)\n\n );\n\n pcie_pipe_lane_v6 # (\n \n .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)\n\n ) \n pipe_lane_6_i (\n\n .pipe_rx_char_is_k_o(pipe_rx6_char_is_k_q),\n .pipe_rx_data_o(pipe_rx6_data_q),\n .pipe_rx_valid_o(pipe_rx6_valid_o),\n .pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o),\n .pipe_rx_status_o(pipe_rx6_status_o),\n .pipe_rx_phy_status_o(pipe_rx6_phy_status_o),\n .pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o),\n .pipe_rx_polarity_i(pipe_rx6_polarity_i),\n .pipe_tx_compliance_i(pipe_tx6_compliance_i),\n .pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i),\n .pipe_tx_data_i(pipe_tx6_data_i),\n .pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i),\n .pipe_tx_powerdown_i(pipe_tx6_powerdown_i),\n \n .pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i),\n .pipe_rx_data_i(pipe_rx6_data_i),\n .pipe_rx_valid_i(pipe_rx6_valid_i),\n .pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i),\n .pipe_rx_status_i(pipe_rx6_status_i),\n .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),\n .pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i),\n .pipe_rx_polarity_o(pipe_rx6_polarity_o),\n .pipe_tx_compliance_o(pipe_tx6_compliance_o),\n .pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o),\n .pipe_tx_data_o(pipe_tx6_data_o),\n .pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o),\n .pipe_tx_powerdown_o(pipe_tx6_powerdown_o),\n \n .pipe_clk(pipe_clk),\n .rst_n(rst_n)\n\n );\n\n pcie_pipe_lane_v6 # (\n \n .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)\n\n ) \n pipe_lane_7_i (\n\n .pipe_rx_char_is_k_o(pipe_rx7_char_is_k_q),\n .pipe_rx_data_o(pipe_rx7_data_q),\n .pipe_rx_valid_o(pipe_rx7_valid_o),\n .pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o),\n .pipe_rx_status_o(pipe_rx7_status_o),\n .pipe_rx_phy_status_o(pipe_rx7_phy_status_o),\n .pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o),\n .pipe_rx_polarity_i(pipe_rx7_polarity_i),\n .pipe_tx_compliance_i(pipe_tx7_compliance_i),\n .pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i),\n .pipe_tx_data_i(pipe_tx7_data_i),\n .pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i),\n .pipe_tx_powerdown_i(pipe_tx7_powerdown_i),\n \n .pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i),\n .pipe_rx_data_i(pipe_rx7_data_i),\n .pipe_rx_valid_i(pipe_rx7_valid_i),\n .pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i),\n .pipe_rx_status_i(pipe_rx7_status_i),\n .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),\n .pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i),\n .pipe_rx_polarity_o(pipe_rx7_polarity_o),\n .pipe_tx_compliance_o(pipe_tx7_compliance_o),\n .pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o),\n .pipe_tx_data_o(pipe_tx7_data_o),\n .pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o),\n .pipe_tx_powerdown_o(pipe_tx7_powerdown_o),\n \n .pipe_clk(pipe_clk),\n .rst_n(rst_n)\n\n );\n\n end\n else begin\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n assign pipe_rx4_char_is_k_o = 2'b00;\n assign pipe_rx4_data_o = 16'h0000;\n assign pipe_rx4_valid_o = 1'b0;\n assign pipe_rx4_chanisaligned_o = 1'b0;\n assign pipe_rx4_status_o = 3'b000;\n assign pipe_rx4_phy_status_o = 1'b0;\n assign pipe_rx4_elec_idle_o = 1'b1;\n assign pipe_rx4_polarity_o = 1'b0;\n assign pipe_tx4_compliance_o = 1'b0;\n assign pipe_tx4_char_is_k_o = 2'b00;\n assign pipe_tx4_data_o = 16'h0000;\n assign pipe_tx4_elec_idle_o = 1'b1;\n assign pipe_tx4_powerdown_o = 2'b00;\n\n assign pipe_rx5_char_is_k_o = 2'b00;\n assign pipe_rx5_data_o = 16'h0000;\n assign pipe_rx5_valid_o = 1'b0;\n assign pipe_rx5_chanisaligned_o = 1'b0;\n assign pipe_rx5_status_o = 3'b000;\n assign pipe_rx5_phy_status_o = 1'b0;\n assign pipe_rx5_elec_idle_o = 1'b1;\n assign pipe_rx5_polarity_o = 1'b0;\n assign pipe_tx5_compliance_o = 1'b0;\n assign pipe_tx5_char_is_k_o = 2'b00;\n assign pipe_tx5_data_o = 16'h0000;\n assign pipe_tx5_elec_idle_o = 1'b1;\n assign pipe_tx5_powerdown_o = 2'b00;\n\n assign pipe_rx6_char_is_k_o = 2'b00;\n assign pipe_rx6_data_o = 16'h0000;\n assign pipe_rx6_valid_o = 1'b0;\n assign pipe_rx6_chanisaligned_o = 1'b0;\n assign pipe_rx6_status_o = 3'b000;\n assign pipe_rx6_phy_status_o = 1'b0;\n assign pipe_rx6_elec_idle_o = 1'b1;\n assign pipe_rx6_polarity_o = 1'b0;\n assign pipe_tx6_compliance_o = 1'b0;\n assign pipe_tx6_char_is_k_o = 2'b00;\n assign pipe_tx6_data_o = 16'h0000;\n assign pipe_tx6_elec_idle_o = 1'b1;\n assign pipe_tx6_powerdown_o = 2'b00;\n\n assign pipe_rx7_char_is_k_o = 2'b00;\n assign pipe_rx7_data_o = 16'h0000;\n assign pipe_rx7_valid_o = 1'b0;\n assign pipe_rx7_chanisaligned_o = 1'b0;\n assign pipe_rx7_status_o = 3'b000;\n assign pipe_rx7_phy_status_o = 1'b0;\n assign pipe_rx7_elec_idle_o = 1'b1;\n assign pipe_rx7_polarity_o = 1'b0;\n assign pipe_tx7_compliance_o = 1'b0;\n assign pipe_tx7_char_is_k_o = 2'b00;\n assign pipe_tx7_data_o = 16'h0000;\n assign pipe_tx7_elec_idle_o = 1'b1;\n assign pipe_tx7_powerdown_o = 2'b00;\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n end \n\n endgenerate\n\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n\n assign pipe_rx0_char_is_k_o = pipe_rx0_char_is_k_q;\n assign pipe_rx0_data_o = pipe_rx0_data_q;\n assign pipe_rx1_char_is_k_o = pipe_rx1_char_is_k_q;\n assign pipe_rx1_data_o = pipe_rx1_data_q;\n assign pipe_rx2_char_is_k_o = pipe_rx2_char_is_k_q;\n assign pipe_rx2_data_o = pipe_rx2_data_q;\n assign pipe_rx3_char_is_k_o = pipe_rx3_char_is_k_q;\n assign pipe_rx3_data_o = pipe_rx3_data_q;\n assign pipe_rx4_char_is_k_o = pipe_rx4_char_is_k_q;\n assign pipe_rx4_data_o = pipe_rx4_data_q;\n assign pipe_rx5_char_is_k_o = pipe_rx5_char_is_k_q;\n assign pipe_rx5_data_o = pipe_rx5_data_q;\n assign pipe_rx6_char_is_k_o = pipe_rx6_char_is_k_q;\n assign pipe_rx6_data_o = pipe_rx6_data_q;\n assign pipe_rx7_char_is_k_o = pipe_rx7_char_is_k_q;\n assign pipe_rx7_data_o = pipe_rx7_data_q;\n\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/pcie_reset_delay_v6.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : pcie_reset_delay_v6.v\n// Version : 2.4\n//--\n//-- Description: sys_reset_n delay (20ms) for Virtex6 PCIe Block\n//--\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns/1ns\n\nmodule pcie_reset_delay_v6 # (\n\n parameter PL_FAST_TRAIN = \"FALSE\",\n parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz\n parameter TCQ = 1\n\n)\n(\n\n input wire ref_clk,\n input wire sys_reset_n,\n output delayed_sys_reset_n\n \n);\n\n\n localparam TBIT = (PL_FAST_TRAIN == \"FALSE\") ? ((REF_CLK_FREQ == 1) ? 20: (REF_CLK_FREQ == 0) ? 20 : 21) : 2;\n\n reg [7:0] reg_count_7_0;\n reg [7:0] reg_count_15_8;\n reg [7:0] reg_count_23_16;\n wire [23:0] concat_count;\n\n assign concat_count = {reg_count_23_16, reg_count_15_8, reg_count_7_0};\n\n always @(posedge ref_clk or negedge sys_reset_n) begin\n\n if (!sys_reset_n) begin\n\n reg_count_7_0 <= #TCQ 8'h0;\n reg_count_15_8 <= #TCQ 8'h0;\n reg_count_23_16 <= #TCQ 8'h0;\n\n end else begin\n\n if (delayed_sys_reset_n != 1'b1) begin\n\n reg_count_7_0 <= #TCQ reg_count_7_0 + 1'b1;\n reg_count_15_8 <= #TCQ (reg_count_7_0 == 8'hff)? reg_count_15_8 + 1'b1 : reg_count_15_8 ;\n reg_count_23_16 <= #TCQ ((reg_count_15_8 == 8'hff) & (reg_count_7_0 == 8'hff)) ? reg_count_23_16 + 1'b1 : reg_count_23_16;\n\n end \n\n end\n\n end\n\n assign delayed_sys_reset_n = concat_count[TBIT]; \n\nendmodule\n\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/pcie_upconfig_fix_3451_v6.v", "content": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//-----------------------------------------------------------------------------\n// Project : Virtex-6 Integrated Block for PCI Express\n// File : pcie_upconfig_fix_3451_v6.v\n// Version : 2.4\n//--\n//-- Description: Virtex6 Workaround for Root Port Upconfigurability Bug\n//--\n//--\n//--------------------------------------------------------------------------------\n\n`timescale 1ns/1ns\n\nmodule pcie_upconfig_fix_3451_v6 # (\n\n parameter UPSTREAM_FACING = \"TRUE\",\n parameter PL_FAST_TRAIN = \"FALSE\",\n parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08,\n parameter TCQ = 1\n\n)\n(\n\n input pipe_clk,\n input pl_phy_lnkup_n,\n\n input [5:0] pl_ltssm_state,\n input pl_sel_lnk_rate,\n input [1:0] pl_directed_link_change,\n\n input [3:0] cfg_link_status_negotiated_width,\n input [15:0] pipe_rx0_data,\n input [1:0] pipe_rx0_char_isk,\n\n output filter_pipe\n\n);\n\n\n reg reg_filter_pipe;\n reg [15:0] reg_tsx_counter;\n wire [15:0] tsx_counter;\n\n wire [5:0] cap_link_width;\n\n // Corrupting all Tsx on all lanes as soon as we do R.RC->R.RI transition to allow time for\n // the core to see the TS1s on all the lanes being configured at the same time\n // R.RI has a 2ms timeout.Corrupting tsxs for ~1/4 of that time\n // 225 pipe_clk cycles-sim_fast_train\n // 60000 pipe_clk cycles-without sim_fast_train\n // Not taking any action when PLDIRECTEDLINKCHANGE is set\n\n// Detect xx, COM then PAD,xx or COM,PAD then PAD,xx\n// data0 will be the first symbol on lane 0, data1 will be the next symbol.\n// Don't look for PAD on data1 since it's unnecessary.\n// COM=0xbc and PAD=0xf7 (and isk).\n// detect if (data & 0xb4) == 0xb4 and isk, and then\n// if (data & 0x4b) == 0x08 or 0x43. This distinguishes COM and PAD, using\n// no more than a 6-input LUT, so should be \"free\".\n\nreg reg_filter_used, reg_com_then_pad;\nreg reg_data0_b4, reg_data0_08, reg_data0_43;\nreg reg_data1_b4, reg_data1_08, reg_data1_43;\nreg reg_data0_com, reg_data1_com, reg_data1_pad;\n\nwire data0_b4 = pipe_rx0_char_isk[0] &&\n ((pipe_rx0_data[7:0] & 8'hb4) == 8'hb4);\nwire data0_08 = ((pipe_rx0_data[7:0] & 8'h4b) == 8'h08);\nwire data0_43 = ((pipe_rx0_data[7:0] & 8'h4b) == 8'h43);\nwire data1_b4 = pipe_rx0_char_isk[1] &&\n ((pipe_rx0_data[15:8] & 8'hb4) == 8'hb4);\nwire data1_08 = ((pipe_rx0_data[15:8] & 8'h4b) == 8'h08);\nwire data1_43 = ((pipe_rx0_data[15:8] & 8'h4b) == 8'h43);\n\nwire data0_com = reg_data0_b4 && reg_data0_08;\nwire data1_com = reg_data1_b4 && reg_data1_08;\nwire data0_pad = reg_data0_b4 && reg_data0_43;\nwire data1_pad = reg_data1_b4 && reg_data1_43;\n\nwire com_then_pad0 = reg_data0_com && reg_data1_pad && data0_pad;\nwire com_then_pad1 = reg_data1_com && data0_pad && data1_pad;\nwire com_then_pad = (com_then_pad0 || com_then_pad1) && ~reg_filter_used;\nwire filter_used = (pl_ltssm_state == 6'h20) &&\n (reg_filter_pipe || reg_filter_used);\n\n always @(posedge pipe_clk) begin\n\n reg_data0_b4 <= #TCQ data0_b4;\n reg_data0_08 <= #TCQ data0_08;\n reg_data0_43 <= #TCQ data0_43;\n reg_data1_b4 <= #TCQ data1_b4;\n reg_data1_08 <= #TCQ data1_08;\n reg_data1_43 <= #TCQ data1_43;\n reg_data0_com <= #TCQ data0_com;\n reg_data1_com <= #TCQ data1_com;\n reg_data1_pad <= #TCQ data1_pad;\n reg_com_then_pad <= #TCQ (~pl_phy_lnkup_n) ? com_then_pad : 1'b0;\n reg_filter_used <= #TCQ (~pl_phy_lnkup_n) ? filter_used : 1'b0;\n\n end\n\n always @ (posedge pipe_clk) begin\n\n if (pl_phy_lnkup_n) begin\n\n reg_tsx_counter <= #TCQ 16'h0;\n reg_filter_pipe <= #TCQ 1'b0;\n\n end else if ((pl_ltssm_state == 6'h20) &&\n reg_com_then_pad &&\n (cfg_link_status_negotiated_width != cap_link_width) &&\n (pl_directed_link_change[1:0] == 2'b00)) begin\n\n reg_tsx_counter <= #TCQ 16'h0;\n reg_filter_pipe <= #TCQ 1'b1;\n\n end else if (filter_pipe == 1'b1) begin\n\n if (tsx_counter < ((PL_FAST_TRAIN == \"TRUE\") ? 16'd225: pl_sel_lnk_rate ? 16'd800 : 16'd400)) begin\n\n reg_tsx_counter <= #TCQ tsx_counter + 1'b1;\n reg_filter_pipe <= #TCQ 1'b1;\n\n end else begin\n\n reg_tsx_counter <= #TCQ 16'h0;\n reg_filter_pipe <= #TCQ 1'b0;\n\n end\n\n end\n\n end\n\n assign filter_pipe = (UPSTREAM_FACING == \"TRUE\") ? 1'b0 : reg_filter_pipe;\n assign tsx_counter = reg_tsx_counter;\n\n assign cap_link_width = LINK_CAP_MAX_LINK_WIDTH;\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/ram_1clk_1w_1r.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tram_1clk_1w_1r.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tAn inferrable RAM module. Single clock, 1 write port, 1 \n//\t\t\t\t\t\tread port. In Xilinx designs, specify RAM_STYLE=\"BLOCK\" \n//\t\t\t\t\t\tto use BRAM memory or RAM_STYLE=\"DISTRIBUTED\" to use \n//\t\t\t\t\t\tLUT memory.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule ram_1clk_1w_1r (\n\tCLK,\n\tADDRA,\n\tWEA,\n\tDINA,\n\tADDRB,\n\tDOUTB\n);\n\n`include \"common_functions.v\"\n\nparameter C_RAM_WIDTH = 32;\nparameter C_RAM_DEPTH = 1024;\n//Local parameters\nparameter C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);\n\ninput\t\t\t\t\t\t\tCLK;\ninput \t[C_RAM_ADDR_BITS-1:0]\tADDRA;\ninput \t\t\t\t\t\t\tWEA;\ninput \t[C_RAM_ADDR_BITS-1:0]\tADDRB;\ninput \t[C_RAM_WIDTH-1:0]\t\tDINA;\noutput \t[C_RAM_WIDTH-1:0]\t\tDOUTB;\n\nreg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];\nreg [C_RAM_WIDTH-1:0] rDout; \n\nassign DOUTB = rDout;\n\nalways @(posedge CLK) begin\n if (WEA)\n\t rRAM[ADDRA] <= #1 DINA;\n rDout <= #1 rRAM[ADDRB];\nend\n\t\t\t\t\t\t\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/ram_2clk_1w_1r.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tram_2clk_1w_1r.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tAn inferrable RAM module. Dual clocks, 1 write port, 1 \n//\t\t\t\t\t\tread port. In Xilinx designs, specify RAM_STYLE=\"BLOCK\" \n//\t\t\t\t\t\tto use BRAM memory or RAM_STYLE=\"DISTRIBUTED\" to use \n//\t\t\t\t\t\tLUT memory.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule ram_2clk_1w_1r (\n\tCLKA,\n\tADDRA,\n\tWEA,\n\tDINA,\n\tCLKB,\n\tADDRB,\n\tDOUTB\n);\n\n`include \"common_functions.v\"\n\nparameter C_RAM_WIDTH = 32;\nparameter C_RAM_DEPTH = 1024;\n//Local parameters\nparameter C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);\n\ninput\t\t\t\t\t\t\tCLKA;\ninput\t\t\t\t\t\t\tCLKB;\ninput \t\t\t\t\t\t\tWEA;\ninput \t[C_RAM_ADDR_BITS-1:0]\tADDRA;\ninput \t[C_RAM_ADDR_BITS-1:0]\tADDRB;\ninput \t[C_RAM_WIDTH-1:0]\t\tDINA;\noutput \t[C_RAM_WIDTH-1:0]\t\tDOUTB;\n\nreg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];\nreg [C_RAM_WIDTH-1:0] rDout; \n\nassign DOUTB = rDout;\n\nalways @(posedge CLKA) begin\n if (WEA)\n\t rRAM[ADDRA] <= #1 DINA;\nend\n\nalways @(posedge CLKB) begin\n rDout <= #1 rRAM[ADDRB];\nend\n\t\t\t\t\t\t\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/recv_credit_flow_ctrl.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\trecv_credit_flow_ctrl.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\tMonitors the receive completion credits for headers and\n// \t\t\tdata to make sure the rx_port modules don't request too \n//\t\t\tmuch data from the root complex, as this could result in\n//\t\t\tsome data being dropped/lost.\n// Author:\t\tMatt Jacobsen\n// Author:\t\tDustin Richmond\n// History:\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule recv_credit_flow_ctrl\n (\n input \tCLK,\n input \tRST,\n input [2:0] \tCONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n input [11:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data\n input [7:0] \tCONFIG_MAX_CPL_HDR, // Receive credit limit for headers\n input \tCONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 bytes)w\n input \tRX_ENG_RD_DONE, // Read completed\n input \tTX_ENG_RD_REQ_SENT, // Read completion request issued\n output \tRXBUF_SPACE_AVAIL // High if enough read completion credits exist to make a read completion request\n );\n\n reg \t\trCreditAvail=0;\n reg \t\trCplDAvail=0;\n reg \t\trCplHAvail=0;\n reg [12:0] \trMaxRecv=0;\n reg [11:0] \trCplDAmt=0;\n reg [7:0] \trCplHAmt=0;\n reg [11:0] \trCplD=0;\n reg [7:0] \trCplH=0;\n\n assign RXBUF_SPACE_AVAIL = rCreditAvail;\n\n // Determine the completions required for a max read completion request.\n always @(posedge CLK) begin\n rMaxRecv <= #1 (13'd128<>({2'b11, CONFIG_CPL_BOUNDARY_SEL}));\n rCplDAmt <= #1 (rMaxRecv>>4);\n rCplHAvail <= #1 (rCplH <= CONFIG_MAX_CPL_HDR);\n rCplDAvail <= #1 (rCplD <= CONFIG_MAX_CPL_DATA);\n rCreditAvail <= #1 (rCplHAvail & rCplDAvail);\n end\n\n // Count the number of outstanding read completion requests.\n always @ (posedge CLK) begin\n if (RST) begin\n\t rCplH <= #1 0;\n\t rCplD <= #1 0;\n end\n else if (RX_ENG_RD_DONE & TX_ENG_RD_REQ_SENT) begin\n\t rCplH <= #1 rCplH;\n\t rCplD <= #1 rCplD;\n end\n else if (TX_ENG_RD_REQ_SENT) begin\n\t rCplH <= #1 rCplH + rCplHAmt;\n\t rCplD <= #1 rCplD + rCplDAmt;\n end\n else if (RX_ENG_RD_DONE) begin\n\t rCplH <= #1 rCplH - rCplHAmt;\n\t rCplD <= #1 rCplD - rCplDAmt;\n end\n end\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/reorder_queue.v", "content": "`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 19:27:32 06/14/2012 \n// Design Name: \n// Module Name: reorder_queue\n// Project Name: \n// Target Devices: \n// Tool versions: \n// Description:\n// Reorders downstream TLPs to output in increasing tag sequence. Input packets\n// are stored in RAM and then read out when all previous sequence numbers have\n// arrived and been read out. This module also provides the next available tag\n// for the TX engine to use when sending memory request TLPs.\n//\n// Dependencies: \n// reorder_queue_input.v\n// reorder_queue_output.v\n//\n// Revision: \n// Revision 0.01 - File Created\n// Additional Comments: \n//\n//////////////////////////////////////////////////////////////////////////////////\nmodule reorder_queue #(\n\tparameter C_PCI_DATA_WIDTH = 9'd128,\n\tparameter C_NUM_CHNL = 4'd12,\n\tparameter C_MAX_READ_REQ_BYTES = 512,\t\t\t// Max size of read requests (in bytes)\n\tparameter C_TAG_WIDTH = 5, \t\t\t\t\t\t// Number of outstanding requests \n\t// Local parameters\n\tparameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,\n\tparameter C_PCI_DATA_COUNT_WIDTH = clog2(C_PCI_DATA_WORD+1),\n\tparameter C_NUM_TAGS = 2**C_TAG_WIDTH,\n\tparameter C_DW_PER_TAG = C_MAX_READ_REQ_BYTES/4,\n\tparameter C_TAG_DW_COUNT_WIDTH = clog2s(C_DW_PER_TAG+1),\n\tparameter C_DATA_ADDR_STRIDE_WIDTH = clog2s(C_DW_PER_TAG/C_PCI_DATA_WORD), // div by C_PCI_DATA_WORD b/c there are C_PCI_DATA_WORD RAMs\n\tparameter C_DATA_ADDR_WIDTH = C_TAG_WIDTH + C_DATA_ADDR_STRIDE_WIDTH\n)\n(\n\tinput CLK,\t\t\t\t\t\t\t\t\t\t\t\t\t\t// Clock\n\tinput RST,\t\t\t\t\t\t\t\t\t\t\t\t\t\t// Synchronous reset\n\tinput VALID,\t\t\t\t\t\t\t\t\t\t\t\t\t// Valid input packet\n\tinput [C_PCI_DATA_WIDTH-1:0] DATA,\t\t\t\t\t\t\t\t// Input packet payload\n\tinput [C_PCI_DATA_WORD-1:0] DATA_EN,\t\t\t\t\t\t\t// Input packet payload data enable\n\tinput [C_PCI_DATA_COUNT_WIDTH-1:0] DATA_EN_COUNT,\t\t\t\t// Input packet payload data enable count\n\tinput DONE,\t\t\t\t\t\t\t\t\t\t\t\t\t\t// Input packet done\n\tinput ERR,\t\t\t\t\t\t\t\t\t\t\t\t\t\t// Input packet has error\n\tinput [C_TAG_WIDTH-1:0] TAG,\t\t\t\t\t\t\t\t\t// Input packet tag (external tag)\n\n\tinput [5:0] INT_TAG,\t\t\t\t\t\t\t\t\t\t\t// Internal tag to exchange with external\n\tinput INT_TAG_VALID,\t\t\t\t\t\t\t\t\t\t\t// High to signal tag exchange \n\toutput [C_TAG_WIDTH-1:0] EXT_TAG,\t\t\t\t\t\t\t\t// External tag to provide in exchange for internal tag\n\toutput EXT_TAG_VALID,\t\t\t\t\t\t\t\t\t\t\t// High to signal external tag is valid\n\n\toutput [C_PCI_DATA_WIDTH-1:0] ENG_DATA,\t\t\t\t\t\t\t// Engine data \n\toutput [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN,\t// Main data enable\n\toutput [C_NUM_CHNL-1:0] MAIN_DONE,\t\t\t\t\t\t\t\t// Main data complete\n\toutput [C_NUM_CHNL-1:0] MAIN_ERR,\t\t\t\t\t\t\t\t// Main data completed with error\n\toutput [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN,\t// Scatter gather for RX data enable\n\toutput [C_NUM_CHNL-1:0] SG_RX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for RX data complete\n\toutput [C_NUM_CHNL-1:0] SG_RX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for RX data completed with error\n\toutput [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN,\t// Scatter gather for TX data enable\n\toutput [C_NUM_CHNL-1:0] SG_TX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for TX data complete\n\toutput [C_NUM_CHNL-1:0] SG_TX_ERR\t\t\t\t\t\t\t\t// Scatter gather for TX data completed with error\n);\n\n`include \"common_functions.v\"\n\nwire\t[(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0]\twWrDataAddr;\nwire\t[C_PCI_DATA_WIDTH-1:0]\t\t\t\t\t\twWrData;\nwire\t[C_PCI_DATA_WORD-1:0]\t\t\t\t\t\twWrDataEn;\n\nwire\t[C_TAG_WIDTH-1:0] \t\t\t\t\t\t\twWrPktTag;\nwire\t[C_TAG_DW_COUNT_WIDTH-1:0] \t\t\t\t\twWrPktWords;\nwire\t\t\t\t\t\t\t \t\t\t\t\twWrPktWordsLTE1;\nwire\t\t\t\t\t\t\t \t\t\t\t\twWrPktWordsLTE2;\nwire\t\t\t\t\t\t\t \t\t\t\t\twWrPktValid;\nwire\t\t\t\t\t\t\t \t\t\t\t\twWrPktDone;\nwire\t\t\t\t\t\t\t \t\t\t\t\twWrPktErr;\n\nwire\t[C_DATA_ADDR_WIDTH-1:0]\t\t\t\t\t\twRdDataAddr;\nwire\t[C_PCI_DATA_WIDTH-1:0]\t\t\t\t\t\twRdData;\n\nwire\t[C_TAG_WIDTH-1:0] \t\t\t\t\t\t\twRdPktTag;\nwire\t[(1+1+1+1+C_TAG_DW_COUNT_WIDTH)-1:0] \t\twRdPktInfo;\n\nwire\t[5:0]\t\t\t\t\t\t\t\t\t\twRdTagMap;\n\nreg\t\t[C_TAG_WIDTH-1:0]\t\t\t\t\t\t\trPos=0;\nreg\t\t\t\t\t\t\t\t\t\t\t\t\trValid=0;\nwire\t[C_NUM_TAGS-1:0]\t\t\t\t\t\t\twFinish;\nreg\t\t[C_NUM_TAGS-1:0]\t\t\t\t\t\t\trFinished=0;\nreg\t\t[C_NUM_TAGS-1:0]\t\t\t\t\t\t\trUse=0;\nreg\t\t[C_NUM_TAGS-1:0]\t\t\t\t\t\t\trUsing=0;\nwire\t[C_NUM_TAGS-1:0]\t\t\t\t\t\t\twClear;\n\n\nassign EXT_TAG = rPos;\nassign EXT_TAG_VALID = rValid;\n\n\n// Move through tag/slot/bucket space.\nalways @ (posedge CLK) begin\n\tif (RST) begin\n\t\trPos <= #1 0;\n\t\trUse <= #1 0;\n\t\trValid <= #1 0;\n\tend\n\telse begin\n\t\tif (INT_TAG_VALID & EXT_TAG_VALID) begin\n\t\t\trPos <= #1 rPos + 1'd1;\n\t\t\trUse <= #1 1<>rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]);\n\trValidCount <= #1 (RST ? 0 : rValid[0]<>(C_PCI_DATA_WORD-rShift));\n\t// To cover the gap b/t reads and writes to RAM, next cycle we might need \n\t// to use the existing or even the previous rPos values if the tags match.\n\trUseCurrPos <= #1 (rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[3*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[3]);\n\trUsePrevPos <= #1 (rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[4]);\n\tfor (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin\n\t\trPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1 \n\t\t\t(RST ? wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] : rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);\n\tend\n\t// See if we need to reset the positions\n\trPosValid <= #1 (RST ? 1'd0 : rPosRst>>rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]);\n\trValidPos <= #1 (RST ? 0 : rValid[2]<>rShiftDown);\n\trLTE1Pkt <= #1 (rWords[1*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH] <= C_PCI_DATA_WORD);\n\trLTE2Pkt <= #1 (rWords[1*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH] <= (C_PCI_DATA_WORD*2));\n\trFinish <= #1 (rValid[4] & (rDone[4] | rErr[4]))<>(32*rDataIn[29]));\nwire [C_PCI_DATA_WIDTH-1:0] wDataIn64bShftB = (rDataIn>>(32*rNext4DWHeader));\nalways @ (posedge CLK) begin\n\trReqState <= #1 (RST ? `S_RXENG128_REQ_PARSE : _rReqState);\n\trReqWen <= #1 (RST ? 1'd0 : _rReqWen);\n\trTC <= #1 _rTC;\n\trTD <= #1 _rTD;\n\trEP <= #1 _rEP;\n\trAttr <= #1 _rAttr;\n\trReqLen <= #1 _rReqLen;\n\trReqId <= #1 _rReqId;\n\trReqTag <= #1 _rReqTag;\n\trBE <= #1 _rBE;\n\trRNW <= #1 _rRNW;\n\trReqData <= #1 _rReqData;\n\trReqAddr <= #1 _rReqAddr;\n rNQWA <= #1 _rNQWA;\n\trNextTC <= #1 _rNextTC;\n\trNextTD <= #1 _rNextTD;\n\trNextEP <= #1 _rNextEP;\n\trNextAttr <= #1 _rNextAttr;\n\trNextReqLen <= #1 _rNextReqLen;\n\trNextReqId <= #1 _rNextReqId;\n\trNextReqTag <= #1 _rNextReqTag;\n\trNextBE <= #1 _rNextBE;\n\trNextRNW <= #1 _rNextRNW;\n\trNext4DWHeader <= #1 _rNext4DWHeader;\nend\n\nalways @ (*) begin\n\t_rReqState = rReqState;\n\t_rTC = rTC;\n\t_rTD = rTD;\n\t_rEP = rEP;\n\t_rAttr = rAttr;\n\t_rReqLen = rReqLen;\n\t_rReqId = rReqId;\n\t_rReqTag = rReqTag;\n\t_rBE = rBE;\n\t_rRNW = rRNW;\n\t_rReqData = rReqData;\n\t_rReqAddr = rReqAddr;\n\t_rReqWen = rReqWen;\n\t_rNQWA = rNQWA;\t\n\n\t_rNextTC = (rValid ? rDataIn[86:84] : rNextTC);\n\t_rNextTD = (rValid ? rDataIn[79] : rNextTD);\n\t_rNextEP = (rValid ? rDataIn[78] : rNextEP);\n\t_rNextAttr = (rValid ? rDataIn[77:76] : rNextAttr);\n\t_rNextReqLen = (rValid ? rDataIn[73:64] : rNextReqLen);\n\t_rNextReqId = (rValid ? rDataIn[127:112] : rNextReqId);\n\t_rNextReqTag = (rValid ? rDataIn[111:104] : rNextReqTag);\n\t_rNextBE = (rValid ? rDataIn[99:96] : rNextBE);\n\t_rNextRNW = (rValid ? rFmtHi[0] : rNextRNW);\n\t_rNext4DWHeader = (rValid ? rDataIn[93] : rNext4DWHeader);\n\t\n\tcase (rReqState)\n\n\t`S_RXENG128_REQ_PARSE : begin\n _rNQWA = RX_DATA[98] & RX_DATA[29] & wALTERA; // 98 is 3rd address bit, 29 is 4 DW header, \n\t\t_rTC = rDataIn[22:20];\n\t\t_rTD = rDataIn[15];\n\t\t_rEP = rDataIn[14];\n\t\t_rAttr = rDataIn[13:12];\n\t\t_rReqLen = rDataIn[9:0];\n\t\t_rReqId = rDataIn[63:48];\n\t\t_rReqTag = rDataIn[47:40];\n\t\t_rBE = rDataIn[35:32];\t\n\t\t_rRNW = rFmtLo[0];\n\t\t_rReqAddr = wDataIn64bShftA[95:66];\n\t\t_rReqData = rDataIn[127:96];\n // Write the request to the fifo if it's a read (no data) or it's a write with a 3DWH and a non-QWA address (EOF)\n // (rFmtLo checks for SOF)\n _rReqWen = rLenOneLo & ((rFmtLo == 3'd1) || ((rFmtLo == 3'd2) && (rEOF == 1'b1)));\n\t\t// rFmtHi/rFmtLo non-zero if the packet is valid, only one will have a non-zero value\n\t\tcase ({rFmtHi, rFmtLo}) \n\t\t\t{3'd1, 3'd0} :\t_rReqState = (rLenOneHi ? `S_RXENG128_REQ_ASSIGN : `S_RXENG128_REQ_PARSE);\n {3'd0, 3'd2} : _rReqState = (rLenOneLo & ~rEOF) ? `S_RXENG128_REQ_DATA : `S_RXENG128_REQ_PARSE;\n\t\t\t{3'd2, 3'd0} :\t_rReqState = (rLenOneHi ? `S_RXENG128_REQ_ASSIGN : `S_RXENG128_REQ_PARSE);\n\t\t\tdefault :\t_rReqState = `S_RXENG128_REQ_PARSE;\n\t\tendcase\n\n\tend \n\n\t`S_RXENG128_REQ_ASSIGN : begin\n\t\t_rTC = rNextTC;\n\t\t_rTD = rNextTD;\n\t\t_rEP = rNextEP;\n\t\t_rAttr = rNextAttr;\n\t\t_rReqLen = rNextReqLen;\n\t\t_rReqId = rNextReqId;\n\t\t_rReqTag = rNextReqTag;\n\t\t_rBE = rNextBE;\t\n\t\t_rRNW = rNextRNW;\n\t\t_rReqAddr = wDataIn64bShftB[31:2];\n\t\t_rReqData = wDataIn64bShftB[63:32];\n\t\t_rReqWen = rValid;\n\t\tif (rValid) begin\n\t\t\tcase (rFmtHi) \n\t\t\t\t3'd1 :\t_rReqState = (rLenOneHi ? `S_RXENG128_REQ_ASSIGN : `S_RXENG128_REQ_PARSE);\n\t\t\t\t3'd2 :\t_rReqState = (rLenOneHi ? `S_RXENG128_REQ_ASSIGN : `S_RXENG128_REQ_PARSE);\n\t\t\t\tdefault :\t_rReqState = `S_RXENG128_REQ_PARSE;\n\t\t\tendcase\n\t\tend\n\tend\n\n\t`S_RXENG128_REQ_DATA : begin\n _rReqData = rDataIn >> ({5'd0,rNQWA}<<5);\n\t\t_rReqWen = rValid;\n\t\tif (rValid) begin\n\t\t\tcase (rFmtHi) \n\t\t\t\t3'd1 :\t_rReqState = (rLenOneHi ? `S_RXENG128_REQ_ASSIGN : `S_RXENG128_REQ_PARSE);\n\t\t\t\t3'd2 :\t_rReqState = (rLenOneHi ? `S_RXENG128_REQ_ASSIGN : `S_RXENG128_REQ_PARSE);\n\t\t\t\tdefault :\t_rReqState = `S_RXENG128_REQ_PARSE;\n\t\t\tendcase\n\t\tend\n\tend\n\n\tdefault : begin\n\t\t_rReqState = `S_RXENG128_REQ_PARSE;\n\tend\n\n\tendcase\nend\n\n\n// Handle cpls and cplds.\nalways @ (posedge CLK) begin\n\trCplState <= #1 (RST ? `S_RXENG128_CPL_PARSE : _rCplState);\n\trDataEn <= #1 (RST ? 4'd0 : _rDataEn);\n\trDataCount <= #1 (RST ? 3'd0 : _rDataCount);\n\trDone <= #1 (RST ? 1'd0 : _rDone);\n\trErr <= #1 (RST ? 1'd0 : _rErr);\n\trLastCPLD <= #1 _rLastCPLD;\n\trData <= #1 _rData;\n\trNextCplErr <= #1 _rNextCplErr;\n\trNextLastCPLD <= #1 _rNextLastCPLD;\n\trOutValid <= #1 _rOutValid;\n\trShft <= #1 _rShft;\nend\n\nalways @ (*) begin\n\t_rCplState = rCplState;\n\t_rLastCPLD = rLastCPLD;\n\t_rDataEn = rDataEn;\n\t_rDataCount = rDataCount;\n\t_rDone = rDone;\n\t_rErr = rErr;\n\t_rShft = rShft;\n\n\t_rOutValid = rValid;\n\t_rData = (rDataIn>>(32*rCplState)); // See state values\n\t_rNextCplErr = (rValid ? rCplErrHi : rNextCplErr); // Completion status code\n\t_rNextLastCPLD = (rValid ? (rDataIn[107:96] == (rDataIn[73:64]<<2)) : rNextLastCPLD); // byte_count == length ?\n\n\tcase (rCplState)\n\n\t`S_RXENG128_CPL_PARSE : begin\n\t\t_rShft = rDataIn[79:72]; // Tag\n _rDataEn = (rFmtLo[2] & rFmtLo[1] & (~rQWACpl | ~wALTERA)); // 1 if rFmtLo == 6\n\t\t_rDataCount = (rFmtLo[2] & rFmtLo[1] & (~rQWACpl | ~wALTERA)); // 1 if rFmtLo == 6\n\t\t_rErr = (rFmtLo[2] & rCplErrLo); // If rFmtLo == 4 or rFmtLo == 6\n\t\t_rDone = (rFmtLo[2] & (!rFmtLo[1] | rEOF)); // If rFmtLo == 4 or (rFmtLo == 6 && length == 1)\n\t\t// Save for S_RXENG128_CPL_DATA_CONT\n\t\t_rLastCPLD = (rDataIn[43:32] == (rDataIn[9:0]<<2)); // byte_count == length ?\n\t\t// rFmtHi/rFmtLo non-zero if the packet is valid, only one will have a non-zero value\n\t\tcase ({rFmtHi, rFmtLo}) \n\t\t\t{3'd0, 3'd4} :\t_rCplState = `S_RXENG128_CPL_PARSE;\n\t\t\t{3'd4, 3'd0} :\t_rCplState = `S_RXENG128_CPL_NO_DATA;\n\t\t\t{3'd0, 3'd6} :\t_rCplState = (`S_RXENG128_CPL_PARSE & {2{(rEOF | rCplErrLo)}}); // Changes to S_RXENG128_CPL_DATA_CONT\n\t\t\t{3'd6, 3'd0} :\t_rCplState = `S_RXENG128_CPL_DATA;\n\t\t\tdefault :\t_rCplState = `S_RXENG128_CPL_PARSE;\n\t\tendcase\n\tend \n\n\t`S_RXENG128_CPL_NO_DATA : begin\n\t\t_rShft = rDataIn[15:8]; // Tag\n\t\t_rDataEn = 0;\n\t\t_rDataCount = 0;\n\t\t_rErr = rNextCplErr;\n\t\t_rDone = 1;\n\t\tif (rValid) begin\n\t\t\tcase (rFmtHi) \n\t\t\t\t3'd4 :\t_rCplState = `S_RXENG128_CPL_NO_DATA;\n\t\t\t\t3'd6 :\t_rCplState = `S_RXENG128_CPL_DATA;\n\t\t\t\tdefault :\t_rCplState = `S_RXENG128_CPL_PARSE;\n\t\t\tendcase\n\t\tend\n\tend\n\n\t`S_RXENG128_CPL_DATA : begin\n\t\t_rShft = rDataIn[15:8]; // Tag\n\t\t_rDataEn = ({3{!rEOF}} | wEOFPosEn[5:3]);\n\t\t_rDataCount = ({2{!rEOF}} | rEOFPos);\n\t\t_rErr = rNextCplErr;\n\t\t_rDone = (rEOF & rNextLastCPLD);\n\t\t// Save for S_RXENG128_CPL_DATA_CONT\n\t\t_rLastCPLD = rNextLastCPLD;\n\t\tif (rValid) begin\n\t\t\tif (rEOF) begin // Ends in this packet\n\t\t\t\tcase (rFmtHi) \n\t\t\t\t\t3'd4 :\t_rCplState = `S_RXENG128_CPL_NO_DATA;\n\t\t\t\t\t3'd6 :\t_rCplState = `S_RXENG128_CPL_DATA;\n\t\t\t\t\tdefault :\t_rCplState = `S_RXENG128_CPL_PARSE;\n\t\t\t\tendcase\n\t\t\tend\n\t\t\telse if (rNextCplErr) begin // Bad completion code\n\t\t\t\t_rCplState = `S_RXENG128_CPL_PARSE;\n\t\t\tend\n\t\t\telse begin // Continues past this packet, send 1 DW now\n\t\t\t\t_rCplState = `S_RXENG128_CPL_DATA_CONT;\n\t\t\tend\n\t\tend\n\tend\n\n\t`S_RXENG128_CPL_DATA_CONT : begin // Process TLP until end\n\t\t_rDataEn = ({4{!rEOF}} | wEOFCountEn[7:4]);\n\t\t_rDataCount = (rEOFCount | {!rEOF, 2'd0});\n\t\t_rErr = 0;\n\t\t_rDone = (rEOF & rLastCPLD);\n\t\tif (rValid) begin // Process and write until last packet\n\t\t\tif (rEOF) begin\n\t\t\t\tcase (rFmtHi) \n\t\t\t\t\t3'd4 :\t_rCplState = `S_RXENG128_CPL_NO_DATA;\n\t\t\t\t\t3'd6 :\t_rCplState = `S_RXENG128_CPL_DATA;\n\t\t\t\t\tdefault :\t_rCplState = `S_RXENG128_CPL_PARSE;\n\t\t\t\tendcase\n\t\t\tend\n\t\tend\n\tend\n\t\n\tendcase\nend\n\n\n// Output the data and enables\nalways @ (posedge CLK) begin\n\trDataValid <= #1 (RST ? 1'd0 : _rDataValid);\n\trDataOutEn <= #1 _rDataOutEn;\n\trDataOutCount <= #1 _rDataOutCount;\n\trDataDone <= #1 _rDataDone;\n\trDataErr <= #1 _rDataErr;\n\trDataTag <= #1 _rDataTag;\n\trDataOut <= #1 _rDataOut;\nend\n\nalways @ (*) begin\n\t_rDataValid = (rOutValid && ((rDataCount | rDone | rErr) != 3'd0));\n\t_rDataOutEn = rDataEn;\n\t_rDataOutCount = rDataCount;\n\t_rDataDone = (rDone | rErr);\n\t_rDataErr = rErr;\n\t_rDataTag = rShft[C_TAG_WIDTH-1:0];\n\t_rDataOut = rData;\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/rx_engine_32.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\trx_engine_32.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tReceive engine for PCIe using AXI interface from Xilinx \n//\t\t\t\t\t\tPCIe Endpoint core.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: Very good PCIe header reference:\n// http://www.pzk-agro.com/0321156307_ch04lev1sec5.html#ch04lev4sec14\n// Also byte swap each payload word due to Xilinx incorrect mapping, see\n// http://forums.xilinx.com/t5/PCI-Express/PCI-Express-payload-required-to-be-Big-Endian-by-specification/td-p/285551\n//-----------------------------------------------------------------------------\n`define FMT_RXENG32_RD32\t7'b00_00000\n`define FMT_RXENG32_WR32\t7'b10_00000\n`define FMT_RXENG32_RD64\t7'b01_00000\n`define FMT_RXENG32_WR64\t7'b11_00000\n`define FMT_RXENG32_CPL\t\t7'b00_01010\n`define FMT_RXENG32_CPLD\t7'b10_01010\n\n`define S_RXENG32_REQ_PARSE\t\t\t3'd0\n`define S_RXENG32_REQ_UNHANDLED\t\t3'd1\n`define S_RXENG32_REQ_MEM_0\t\t\t3'd2\n`define S_RXENG32_REQ_MEM_1\t\t\t3'd3\n`define S_RXENG32_REQ_MEM_2\t\t\t3'd4\n`define S_RXENG32_REQ_MEM_WR\t\t3'd5\n\n`define S_RXENG32_CPL_PARSE\t\t\t3'd0\n`define S_RXENG32_CPL_WAIT_FOR_END\t3'd1\n`define S_RXENG32_CPL_0\t\t\t\t3'd2\n`define S_RXENG32_CPL_1\t\t\t\t3'd3\n`define S_RXENG32_CPL_DATA\t\t\t3'd4\n\nmodule rx_engine_32 #(\n\tparameter C_PCI_DATA_WIDTH = 9'd32,\n\tparameter C_NUM_CHNL = 4'd12,\n\tparameter C_MAX_READ_REQ_BYTES = 512,\t\t\t// Max size of read requests (in bytes)\n\tparameter C_TAG_WIDTH = 5, \t\t\t\t\t\t// Number of outstanding requests \n\t// Local parameters\n\tparameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,\n\tparameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1)\n)\n(\n\tinput CLK,\n\tinput RST,\n\t// Receive\n\tinput [C_PCI_DATA_WIDTH-1:0] RX_DATA,\n\tinput RX_TLP_END_FLAG,\n\tinput RX_DATA_VALID,\n\toutput RX_DATA_READY,\n\tinput RX_TLP_ERROR_POISON,\n\t// Received read/write memory requests\n\toutput REQ_WR,\t\t\t\t\t\t\t\t\t\t\t\t\t// Memory write request\n\tinput REQ_WR_DONE,\t\t\t\t\t\t\t\t\t\t\t\t// Memory write completed\n\toutput REQ_RD,\t\t\t\t\t\t\t\t\t\t\t\t\t// Memory read request\n\tinput REQ_RD_DONE,\t\t\t\t\t\t\t\t\t\t\t\t// Memory read complete\n\toutput [9:0] REQ_LEN,\t\t\t\t\t\t\t\t\t\t\t// Memory length (1DW)\n\toutput [29:0] REQ_ADDR,\t\t\t\t\t\t\t\t\t\t\t// Memory address (bottom 2 bits are always 00)\n\toutput [31:0] REQ_DATA,\t\t\t\t\t\t\t\t\t\t\t// Memory write data\n\toutput [3:0] REQ_BE,\t\t\t\t\t\t\t\t\t\t\t// Memory byte enables\n\toutput [2:0] REQ_TC,\t\t\t\t\t\t\t\t\t\t\t// Memory traffic class\n\toutput REQ_TD, \t\t\t\t\t\t\t\t// Memory packet digest\n\toutput REQ_EP, \t\t\t\t\t\t\t\t\t\t\t// Memory poisoned packet\n\toutput [1:0] REQ_ATTR,\t\t\t\t\t\t\t\t\t\t\t// Memory packet relaxed ordering, no snoop\n\toutput [15:0] REQ_ID,\t\t\t\t\t\t\t\t\t\t\t// Memory requestor id\n\toutput [7:0] REQ_TAG,\t\t\t\t\t\t\t\t\t\t\t// Memory packet tag\n\t// Tag exchange\n\tinput [5:0] INT_TAG,\t\t\t\t\t\t\t\t\t\t\t// Internal tag to exchange with external\n\tinput INT_TAG_VALID,\t\t\t\t\t\t\t\t\t\t\t// High to signal tag exchange \n\toutput [C_TAG_WIDTH-1:0] EXT_TAG,\t\t\t\t\t\t\t\t// External tag to provide in exchange for internal tag\n\toutput EXT_TAG_VALID,\t\t\t\t\t\t\t\t\t\t\t// High to signal external tag is valid\n\t// Received read completions\n output ENG_RD_COMPLETE, \n\toutput [C_PCI_DATA_WIDTH-1:0] ENG_DATA,\t\t\t\t\t\t\t// Engine data \n\toutput [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN,\t// Main data enable\n\toutput [C_NUM_CHNL-1:0] MAIN_DONE,\t\t\t\t\t\t\t\t// Main data complete\n\toutput [C_NUM_CHNL-1:0] MAIN_ERR,\t\t\t\t\t\t\t\t// Main data completed with error\n\toutput [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN,\t// Scatter gather for RX data enable\n\toutput [C_NUM_CHNL-1:0] SG_RX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for RX data complete\n\toutput [C_NUM_CHNL-1:0] SG_RX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for RX data completed with error\n\toutput [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN,\t// Scatter gather for TX data enable\n\toutput [C_NUM_CHNL-1:0] SG_TX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for TX data complete\n\toutput [C_NUM_CHNL-1:0] SG_TX_ERR\t\t\t\t\t\t\t\t// Scatter gather for TX data completed with error\n);\n\n`include \"common_functions.v\"\n\n\nreg\t\t[2:0]\t\t\t\t\t\trTrigger=0, _rTrigger=0;\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trDataIn=0, _rDataIn=0;\nreg\t\t\t\t\t\t\t\t\trValidIn=0, _rValidIn=0;\nreg\t\t\t\t\t\t\t\t\trLastIn=0, _rLastIn=0;\nreg\t\t\t\t\t\t\t\t\trLenOneIn=0, _rLenOneIn=0;\n\nreg\t\t[2:0]\t\t\t\t\t\trReqState=`S_RXENG32_REQ_PARSE, _rReqState=`S_RXENG32_REQ_PARSE;\nreg\t\t[29:0]\t\t\t\t\t\trReqAddr=0, _rReqAddr=0;\nreg\t\t[31:0]\t\t\t\t\t\trReqData=0, _rReqData=0;\nreg\t\t\t\t\t\t\t\t\trReqWen=0, _rReqWen=0;\nreg\t\t\t\t\t\t\t\t\trRNW=0, _rRNW=0;\nreg\t\t[3:0]\t\t\t\t\t\trBE=0, _rBE=0;\nreg\t\t[2:0]\t\t\t\t\t\trTC=0, _rTC=0;\nreg\t\t\t\t\t\t\t\t\trTD=0, _rTD=0;\nreg\t\t\t\t\t\t\t\t\trEP=0, _rEP=0;\nreg\t\t[1:0]\t\t\t\t\t\trAttr=0, _rAttr=0;\nreg\t\t[9:0]\t\t\t\t\t\trReqLen=0, _rReqLen=0;\nreg\t\t[15:0]\t\t\t\t\t\trReqId=0, _rReqId=0;\nreg\t\t[7:0]\t\t\t\t\t\trReqTag=0, _rReqTag=0;\nreg\t\t\t\t\t\t\t\t\tr3DWHeader=0, _r3DWHeader=0;\n\nreg\t\t[2:0]\t\t\t\t\t\trCplState=`S_RXENG32_CPL_PARSE, _rCplState=`S_RXENG32_CPL_PARSE;\nreg\t\t\t\t\t\t\t\t\trCplErr=0, _rCplErr=0;\nreg\t\t\t\t\t\t\t\t\trLastCPLD=0, _rLastCPLD=0;\n\nreg\t\t[C_PCI_DATA_COUNT_WIDTH-1:0]\trDataOutCount=0, _rDataOutCount=0;\nreg\t\t[C_PCI_DATA_WORD-1:0]\t\trDataOutEn=0, _rDataOutEn=0;\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trDataOut={C_PCI_DATA_WIDTH{1'b0}}, _rDataOut={C_PCI_DATA_WIDTH{1'b0}};\nreg\t\t\t\t\t\t\t\t\trDataDone=0, _rDataDone=0;\nreg\t\t\t\t\t\t\t\t\trDataErr=0, _rDataErr=0;\nreg\t\t\t\t\t\t\t\t\trDataValid=0, _rDataValid=0;\nreg\t\t[7:0]\t\t\t\t\t\trChnlShft=0, _rChnlShft=0;\nreg\t\t[9:0]\t\t\t\t\t\trLen=0, _rLen=0;\nreg\t\t\t\t\t\t\t\t\trWithData=0, _rWithData=0;\n\nwire\t[31:0]\t\t\t\t\t\twReqData = {rReqData[7:0], rReqData[15:8], rReqData[23:16], rReqData[31:24]};\nwire\t[C_PCI_DATA_WIDTH-1:0]\t\twDataOut = {rDataOut[7:0], rDataOut[15:8], rDataOut[23:16], rDataOut[31:24]};\n\n\nassign RX_DATA_READY = 1;\nassign ENG_RD_COMPLETE = rDataDone;\n\n\n// Handle servicing write & read memory requests in a separate state machine.\nrx_engine_req #( \n\t.C_NUM_CHNL(C_NUM_CHNL)\n) rxEngReq (\n\t.CLK(CLK), \n\t.RST(RST), \n\t.REQ_WR(REQ_WR), \n\t.REQ_WR_DONE(REQ_WR_DONE), \n\t.REQ_RD(REQ_RD), \n\t.REQ_RD_DONE(REQ_RD_DONE), \n\t.REQ_LEN(REQ_LEN), \n\t.REQ_ADDR(REQ_ADDR), \n\t.REQ_DATA(REQ_DATA), \n\t.REQ_BE(REQ_BE), \n\t.REQ_TC(REQ_TC), \n\t.REQ_TD(REQ_TD), \n\t.REQ_EP(REQ_EP), \n\t.REQ_ATTR(REQ_ATTR), \n\t.REQ_ID(REQ_ID), \n\t.REQ_TAG(REQ_TAG),\n\t.WEN(rReqWen),\n\t.RNW(rRNW),\n\t.LEN(rReqLen), \n\t.ADDR(rReqAddr), \n\t.DATA(wReqData), \n\t.BE(rBE), \n\t.TC(rTC), \n\t.TD(rTD), \n\t.EP(rEP), \n\t.ATTR(rAttr), \n\t.ID(rReqId), \n\t.TAG(rReqTag)\n);\n\n\n// Handle reordering completion data.\nreorder_queue #( \n\t.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),\n\t.C_NUM_CHNL(C_NUM_CHNL),\n\t.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),\n\t.C_TAG_WIDTH(C_TAG_WIDTH)\n) reorderQueue (\n\t.CLK(CLK), \n\t.RST(RST), \n\t.VALID(rDataValid), \n\t.DATA(wDataOut), \n\t.DATA_EN(rDataOutEn), \n\t.DATA_EN_COUNT(rDataOutCount), \n\t.DONE(rDataDone), \n\t.ERR(rDataErr), \n\t.TAG(rChnlShft[C_TAG_WIDTH-1:0]), \n\t.INT_TAG(INT_TAG), \n\t.INT_TAG_VALID(INT_TAG_VALID), \n\t.EXT_TAG(EXT_TAG), \n\t.EXT_TAG_VALID(EXT_TAG_VALID), \n\t.ENG_DATA(ENG_DATA), \n\t.MAIN_DATA_EN(MAIN_DATA_EN), \n\t.MAIN_DONE(MAIN_DONE),\n\t.MAIN_ERR(MAIN_ERR),\n\t.SG_RX_DATA_EN(SG_RX_DATA_EN),\n\t.SG_RX_DONE(SG_RX_DONE),\n\t.SG_RX_ERR(SG_RX_ERR), \n\t.SG_TX_DATA_EN(SG_TX_DATA_EN), \n\t.SG_TX_DONE(SG_TX_DONE), \n\t.SG_TX_ERR(SG_TX_ERR)\n);\n\n\n// Handle receiving data from PCIe receive channel.\nwire wValid = (RX_DATA_VALID & !RX_TLP_ERROR_POISON);\nalways @ (posedge CLK) begin\n\trTrigger <= #1 (RST ? 3'd0 : _rTrigger);\n\trValidIn <= #1 (RST ? 1'd0 : _rValidIn);\n\trDataIn <= #1 _rDataIn;\n\trLastIn <= #1 _rLastIn;\n\trLenOneIn <= #1 _rLenOneIn;\nend\n\nalways @ (*) begin\n\t_rDataIn = rDataIn;\n\t_rValidIn = rValidIn;\n\t_rLastIn = rLastIn;\n\t_rLenOneIn = rLenOneIn;\n\t_rTrigger = rTrigger;\n\t\n\t// Buffer the incoming data\n\t_rDataIn = RX_DATA;\n\t_rValidIn = (RX_DATA_VALID && !RX_TLP_ERROR_POISON);\n\t_rLastIn = RX_TLP_END_FLAG;\n\t_rLenOneIn = (RX_DATA[9:0] == 10'd1);\n\n\t// Direct the main FSM with what kind of packet this represents\n\tcase (RX_DATA[30:24])\n\t\t`FMT_RXENG32_RD32 :\t_rTrigger = 3'd1 & ({3{wValid}});\n\t\t`FMT_RXENG32_RD64 :\t_rTrigger = 3'd1 & ({3{wValid}});\n\t\t`FMT_RXENG32_WR32 :\t_rTrigger = 3'd2 & ({3{wValid}});\n\t\t`FMT_RXENG32_WR64 :\t_rTrigger = 3'd2 & ({3{wValid}});\n\t\t`FMT_RXENG32_CPL :\t_rTrigger = 3'd3 & ({3{wValid}});\n\t\t`FMT_RXENG32_CPLD :\t_rTrigger = 3'd4 & ({3{wValid}});\n\t\tdefault\t\t\t :\t_rTrigger = 3'd5 & ({3{wValid}});\n\tendcase\nend\n\n\n// Handle receiving memory reads and writes.\nalways @ (posedge CLK) begin\n\trReqState <= #1 (RST ? `S_RXENG32_REQ_PARSE : _rReqState);\n\trReqWen <= #1 (RST ? 1'd0 : _rReqWen);\n\trRNW <= #1 _rRNW;\n\trTC <= #1 _rTC;\n\trTD <= #1 _rTD;\n\trEP <= #1 _rEP;\n\trAttr <= #1 _rAttr;\n\trReqLen <= #1 _rReqLen;\n\trReqId <= #1 _rReqId;\n\trReqTag <= #1 _rReqTag;\n\trBE <= #1 _rBE;\n\tr3DWHeader <= #1 _r3DWHeader;\n\trReqData <= #1 _rReqData;\n\trReqAddr <= #1 _rReqAddr;\nend\n\nalways @ (*) begin\n\t_rReqState = rReqState;\n\t_rTC = rTC;\n\t_rTD = rTD;\n\t_rEP = rEP;\n\t_rAttr = rAttr;\n\t_rReqLen = rReqLen;\n\t_rReqId = rReqId;\n\t_rReqTag = rReqTag;\n\t_rBE = rBE;\n\t_r3DWHeader = r3DWHeader;\n\t_rReqData = rReqData;\n\t_rReqAddr = rReqAddr;\n\t_rReqWen = rReqWen;\n\t_rRNW = rRNW;\n\n\tcase (rReqState)\n\n\t`S_RXENG32_REQ_PARSE : begin // Process DW0, DW1\n\t\t_rTC = rDataIn[22:20];\n\t\t_rTD = rDataIn[15];\n\t\t_rEP = rDataIn[14];\n\t\t_rAttr = rDataIn[13:12];\n\t\t_rReqLen = rDataIn[9:0];\n\t\t_r3DWHeader = !rDataIn[29];\n\t\t_rRNW = (rTrigger == 3'd1);\n\t\t_rReqWen = 0;\n\t\t// Trigger only set if the packet is valid\n\t\tcase (rTrigger) \n\t\t\t3'd0 :\t\t_rReqState = rReqState; \n\t\t\t3'd1 :\t\t_rReqState = (rLenOneIn ? `S_RXENG32_REQ_MEM_0 : `S_RXENG32_REQ_UNHANDLED);\n\t\t\t3'd2 :\t\t_rReqState = (rLenOneIn ? `S_RXENG32_REQ_MEM_0 : `S_RXENG32_REQ_UNHANDLED);\n\t\t\tdefault :\t_rReqState = `S_RXENG32_REQ_UNHANDLED;\n\t\tendcase\n\tend \n\n\t`S_RXENG32_REQ_UNHANDLED : begin\n\t\tif (rValidIn & rLastIn)\n\t\t\t_rReqState = `S_RXENG32_REQ_PARSE;\t\t\n\tend\n\n\t`S_RXENG32_REQ_MEM_0 : begin\n\t\t_rReqId = rDataIn[31:16];\n\t\t_rReqTag = rDataIn[15:8];\n\t\t_rBE = rDataIn[3:0];\t\n\t\tif (rValidIn)\n\t\t\t_rReqState = (rLastIn ? `S_RXENG32_REQ_PARSE : `S_RXENG32_REQ_MEM_1);\n\tend\n\n\t`S_RXENG32_REQ_MEM_1 : begin\n\t\t_rReqAddr = rDataIn[31:2];\n\t\t_rReqWen = (rRNW & r3DWHeader & rValidIn & rLastIn);\n\t\tif (rValidIn) begin\n\t\t\tcase ({rRNW, r3DWHeader, rLastIn})\n\t\t\t3'b000: _rReqState = `S_RXENG32_REQ_MEM_2; // 4DW Write\n\t\t\t3'b010: _rReqState = `S_RXENG32_REQ_MEM_WR; // 3DW Write\n\t\t\t3'b100: _rReqState = `S_RXENG32_REQ_MEM_2; // 4DW Read\n\t\t\t3'b110: _rReqState = `S_RXENG32_REQ_UNHANDLED;\n\t\t\t3'b111: _rReqState = `S_RXENG32_REQ_PARSE; // 3DW Read\n\t\t\tdefault: _rReqState = `S_RXENG32_REQ_PARSE;\n\t\t\tendcase\n\t\tend\n\tend\n\n\t`S_RXENG32_REQ_MEM_2 : begin\n\t\t_rReqAddr = rDataIn[31:2];\n\t\t_rReqWen = (rRNW & rValidIn & rLastIn);\n\t\tif (rValidIn) begin\n\t\t\tcase ({rRNW, rLastIn})\n\t\t\t2'b00: _rReqState = `S_RXENG32_REQ_MEM_WR; // 4DW Write\n\t\t\t2'b01: _rReqState = `S_RXENG32_REQ_PARSE;\n\t\t\t2'b10: _rReqState = `S_RXENG32_REQ_UNHANDLED;\n\t\t\t2'b11: _rReqState = `S_RXENG32_REQ_PARSE; // 4DW Read\n\t\t\tendcase\n\t\tend\n\tend\n\n\t`S_RXENG32_REQ_MEM_WR : begin\n\t\t_rReqData = rDataIn[31:0];\n\t\t_rReqWen = (rValidIn & rLastIn);\n\t\tif (rValidIn)\n\t\t\t_rReqState = (rLastIn ? `S_RXENG32_REQ_PARSE : `S_RXENG32_REQ_UNHANDLED);\n\tend\n\n\tdefault : begin\n\t\t_rReqState = `S_RXENG32_REQ_PARSE;\n\tend\n\n\tendcase\nend\n\n\n// When signaled, start processing the packet, handle cpls and cplds.\nalways @ (posedge CLK) begin\n\trCplState <= #1 (RST ? `S_RXENG32_CPL_PARSE : _rCplState);\n\trDataOutEn <= #1 (RST ? 1'd0 : _rDataOutEn);\n\trDataOutCount <= #1 (RST ? 1'd0 : _rDataOutCount);\n\trDataDone <= #1 (RST ? 1'd0 : _rDataDone);\n\trDataErr <= #1 (RST ? 1'd0 : _rDataErr);\n\trDataValid <= #1 (RST ? 1'd0 : _rDataValid);\n\trCplErr <= #1 _rCplErr;\n\trLastCPLD <= #1 _rLastCPLD;\n\trDataOut <= #1 _rDataOut;\n\trChnlShft <= #1 _rChnlShft;\n\trWithData <= #1 _rWithData;\n\trLen <= #1 _rLen;\nend\n\nalways @ (*) begin\n\t_rCplState = rCplState;\n\t_rCplErr = rCplErr;\n\t_rLastCPLD = rLastCPLD;\n\t_rDataOut = rDataOut;\n\t_rDataOutEn = rDataOutEn;\n\t_rDataOutCount = rDataOutCount;\n\t_rDataDone = rDataDone;\n\t_rDataErr = rDataErr;\n\t_rDataValid = rDataValid;\n\t_rChnlShft = rChnlShft;\n\t_rWithData = rWithData;\n\t_rLen = rLen;\n\tcase (rCplState)\n\n\t`S_RXENG32_CPL_PARSE : begin // Process DW0, DW1\n\t\t_rDataOutEn = 0;\n\t\t_rDataOutCount = 0;\n\t\t_rDataDone = 0;\n\t\t_rDataErr = 0;\n\t\t_rDataValid = 0;\n\t\t_rLen = rDataIn[9:0];\n\t\t_rWithData = (rTrigger == 3'd4);\n\t\t// Trigger only set if the packet is valid\n\t\tcase (rTrigger) \n\t\t\t3'd0 :\t\t_rCplState = rCplState;\n\t\t\t3'd3 :\t\t_rCplState = `S_RXENG32_CPL_0;\n\t\t\t3'd4 :\t\t_rCplState = `S_RXENG32_CPL_0;\n\t\t\tdefault :\t_rCplState = `S_RXENG32_CPL_WAIT_FOR_END;\n\t\tendcase\n\tend \n\n\t`S_RXENG32_CPL_WAIT_FOR_END : begin // Wait until the end of the TLP\n\t\t_rDataOutEn = 0;\n\t\t_rDataOutCount = 0;\n\t\t_rDataDone = 0;\n\t\t_rDataErr = 0;\n\t\t_rDataValid = 0;\n\t\tif (rValidIn & rLastIn)\n\t\t\t_rCplState = `S_RXENG32_CPL_PARSE;\t\t\n\tend\n\n\t`S_RXENG32_CPL_0 : begin\n\t\t_rCplErr = (rDataIn[15:13] != 3'b000); // Completion status code\n\t\t_rLastCPLD = (rDataIn[11:0] == (rLen<<2)); // byte_count == length ?\n\t\tif (rValidIn) begin\n\t\t\t_rCplState = (rLastIn ? `S_RXENG32_CPL_PARSE : `S_RXENG32_CPL_1);\n\t\tend\n\tend\n\t\n\t`S_RXENG32_CPL_1 : begin\n\t\t_rChnlShft = rDataIn[15:8]; // Tag is [15:8]\n\t\t_rDataValid = rValidIn;\n\t\tif (rValidIn) begin\n\t\t\t_rDataErr = rCplErr;\n\t\t\t_rDataDone = (rCplErr | (rLastIn & rLastCPLD));\n\t\t\tif (rLastIn) // Ends in this packet\n\t\t\t\t_rCplState = `S_RXENG32_CPL_PARSE;\n\t\t\telse if (rCplErr | !rWithData) // Bad completion code or just CPL\n\t\t\t\t_rCplState = `S_RXENG32_CPL_WAIT_FOR_END;\n\t\t\telse // Continues past this packet\n\t\t\t\t_rCplState = `S_RXENG32_CPL_DATA;\n\t\tend\n\tend\n\n\t`S_RXENG32_CPL_DATA : begin\n\t\t_rDataValid = rValidIn;\n\t\t_rDataOut = rDataIn;\n\t\tif (rValidIn) begin\n\t\t\t_rDataOutEn = 1;\n\t\t\t_rDataOutCount = 1;\n\t\t\t_rDataDone = (rLastIn & rLastCPLD);\n\t\t\t_rCplState = (rLastIn ? `S_RXENG32_CPL_PARSE : `S_RXENG32_CPL_DATA);\n\t\tend\n\tend\n\n\tdefault : begin\n\t\t_rCplState = `S_RXENG32_CPL_PARSE;\n\tend\n\t\n\tendcase\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/rx_engine_64.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\trx_engine_64.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tReceive engine for PCIe using AXI interface from Xilinx \n//\t\t\t\t\t\tPCIe Endpoint core.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: Very good PCIe header reference:\n// http://www.pzk-agro.com/0321156307_ch04lev1sec5.html#ch04lev4sec14\n// Also byte swap each payload word due to Xilinx incorrect mapping, see\n// http://forums.xilinx.com/t5/PCI-Express/PCI-Express-payload-required-to-be-Big-Endian-by-specification/td-p/285551\n//-----------------------------------------------------------------------------\n`define FMT_RXENG64_RD32\t7'b00_00000\n`define FMT_RXENG64_WR32\t7'b10_00000\n`define FMT_RXENG64_RD64\t7'b01_00000\n`define FMT_RXENG64_WR64\t7'b11_00000\n`define FMT_RXENG64_CPL\t\t7'b00_01010\n`define FMT_RXENG64_CPLD\t7'b10_01010\n\n`define S_RXENG64_REQ_PARSE\t\t\t3'd0\n`define S_RXENG64_REQ_UNHANDLED\t\t3'd1\n`define S_RXENG64_REQ_MEM_RD_0\t\t3'd2\n`define S_RXENG64_REQ_MEM_WR_0\t\t3'd3\n`define S_RXENG64_REQ_MEM_WR_1\t\t3'd4\n\n`define S_RXENG64_CPL_PARSE\t\t\t3'd0\n`define S_RXENG64_CPL_WAIT_FOR_END\t3'd1\n`define S_RXENG64_CPL_NO_DATA\t\t3'd2\n`define S_RXENG64_CPL_DATA\t\t\t3'd3\n`define S_RXENG64_CPL_DATA_CONT\t\t3'd4\n\nmodule rx_engine_64 #(\n\tparameter C_PCI_DATA_WIDTH = 9'd64,\n\tparameter C_NUM_CHNL = 4'd12,\n\tparameter C_MAX_READ_REQ_BYTES = 512,\t\t\t// Max size of read requests (in bytes)\n\tparameter C_TAG_WIDTH = 5, \t\t\t\t\t\t// Number of outstanding requests \n\tparameter C_ALTERA = 1'b1,\t\t\t\t\t\t// 1 if Altera, 0 if Xilinx\n\t// Local parameters\n\tparameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,\n\tparameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1)\n)\n(\n\tinput CLK,\n\tinput RST,\n\t// Receive\n\tinput [C_PCI_DATA_WIDTH-1:0] RX_DATA,\n\tinput [(C_PCI_DATA_WIDTH/8)-1:0] RX_DATA_BYTE_ENABLE,\n\tinput RX_TLP_END_FLAG,\n\tinput RX_DATA_VALID,\n\toutput RX_DATA_READY,\n\tinput RX_TLP_ERROR_POISON,\n\t// Received read/write memory requests\n\toutput REQ_WR,\t\t\t\t\t\t\t\t\t\t\t\t\t// Memory write request\n\tinput REQ_WR_DONE,\t\t\t\t\t\t\t\t\t\t\t\t// Memory write completed\n\toutput REQ_RD,\t\t\t\t\t\t\t\t\t\t\t\t\t// Memory read request\n\tinput REQ_RD_DONE,\t\t\t\t\t\t\t\t\t\t\t\t// Memory read complete\n\toutput [9:0] REQ_LEN,\t\t\t\t\t\t\t\t\t\t\t// Memory length (1DW)\n\toutput [29:0] REQ_ADDR,\t\t\t\t\t\t\t\t\t\t\t// Memory address (bottom 2 bits are always 00)\n\toutput [31:0] REQ_DATA,\t\t\t\t\t\t\t\t\t\t\t// Memory write data\n\toutput [3:0] REQ_BE,\t\t\t\t\t\t\t\t\t\t\t// Memory byte enables\n\toutput [2:0] REQ_TC,\t\t\t\t\t\t\t\t\t\t\t// Memory traffic class\n\toutput REQ_TD, \t\t\t\t\t\t\t\t// Memory packet digest\n\toutput REQ_EP, \t\t\t\t\t\t\t\t\t\t\t// Memory poisoned packet\n\toutput [1:0] REQ_ATTR,\t\t\t\t\t\t\t\t\t\t\t// Memory packet relaxed ordering, no snoop\n\toutput [15:0] REQ_ID,\t\t\t\t\t\t\t\t\t\t\t// Memory requestor id\n\toutput [7:0] REQ_TAG,\t\t\t\t\t\t\t\t\t\t\t// Memory packet tag\n\t// Tag exchange\n\tinput [5:0] INT_TAG,\t\t\t\t\t\t\t\t\t\t\t// Internal tag to exchange with external\n\tinput INT_TAG_VALID,\t\t\t\t\t\t\t\t\t\t\t// High to signal tag exchange \n\toutput [C_TAG_WIDTH-1:0] EXT_TAG,\t\t\t\t\t\t\t\t// External tag to provide in exchange for internal tag\n\toutput EXT_TAG_VALID,\t\t\t\t\t\t\t\t\t\t\t// High to signal external tag is valid\n\t// Received read completions\n output ENG_RD_COMPLETE, \n\toutput [C_PCI_DATA_WIDTH-1:0] ENG_DATA,\t\t\t\t\t\t\t// Engine data \n\toutput [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN,\t// Main data enable\n\toutput [C_NUM_CHNL-1:0] MAIN_DONE,\t\t\t\t\t\t\t\t// Main data complete\n\toutput [C_NUM_CHNL-1:0] MAIN_ERR,\t\t\t\t\t\t\t\t// Main data completed with error\n\toutput [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN,\t// Scatter gather for RX data enable\n\toutput [C_NUM_CHNL-1:0] SG_RX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for RX data complete\n\toutput [C_NUM_CHNL-1:0] SG_RX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for RX data completed with error\n\toutput [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN,\t// Scatter gather for TX data enable\n\toutput [C_NUM_CHNL-1:0] SG_TX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for TX data complete\n\toutput [C_NUM_CHNL-1:0] SG_TX_ERR\t\t\t\t\t\t\t\t// Scatter gather for TX data completed with error\n);\n\n`include \"common_functions.v\"\n\n\nreg\t\t[2:0]\t\t\t\t\t\trTrigger=0, _rTrigger=0;\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trDataIn=0, _rDataIn=0;\nreg\t\t\t\t\t\t\t\t\trValidIn=0, _rValidIn=0;\nreg\t\t\t\t\t\t\t\t\trKeepBothIn=0, _rKeepBothIn=0;\nreg\t\t\t\t\t\t\t\t\trLastIn=0, _rLastIn=0;\nreg\t\t\t\t\t\t\t\t\trLenOneIn=0, _rLenOneIn=0;\n\nreg\t\t[2:0]\t\t\t\t\t\trReqState=`S_RXENG64_REQ_PARSE, _rReqState=`S_RXENG64_REQ_PARSE;\nreg\t\t[29:0]\t\t\t\t\t\trReqAddr=0, _rReqAddr=0;\nreg\t\t[31:0]\t\t\t\t\t\trReqData=0, _rReqData=0;\nreg\t\t\t\t\t\t\t\t\trReqWen=0, _rReqWen=0;\nreg\t\t\t\t\t\t\t\t\trRNW=0, _rRNW=0;\nreg\t\t[3:0]\t\t\t\t\t\trBE=0, _rBE=0;\nreg\t\t[2:0]\t\t\t\t\t\trTC=0, _rTC=0;\nreg\t\t\t\t\t\t\t\t\trTD=0, _rTD=0;\nreg\t\t\t\t\t\t\t\t\trEP=0, _rEP=0;\nreg\t\t[1:0]\t\t\t\t\t\trAttr=0, _rAttr=0;\nreg\t\t[9:0]\t\t\t\t\t\trReqLen=0, _rReqLen=0;\nreg\t\t[15:0]\t\t\t\t\t\trReqId=0, _rReqId=0;\nreg\t\t[7:0]\t\t\t\t\t\trReqTag=0, _rReqTag=0;\nreg\t\t\t\t\t\t\t\t\tr3DWHeader=0, _r3DWHeader=0;\n\nreg\t\t[2:0]\t\t\t\t\t\trCplState=`S_RXENG64_CPL_PARSE, _rCplState=`S_RXENG64_CPL_PARSE;\nreg\t\t\t\t\t\t\t\t\trCplErr=0, _rCplErr=0;\nreg\t\t\t\t\t\t\t\t\trLastCPLD=0, _rLastCPLD=0;\n\nreg\t\t[C_PCI_DATA_COUNT_WIDTH-1:0]rDataOutCount=0, _rDataOutCount=0;\nreg\t\t[C_PCI_DATA_WORD-1:0]\t\trDataOutEn=0, _rDataOutEn=0;\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trDataOut={C_PCI_DATA_WIDTH{1'b0}}, _rDataOut={C_PCI_DATA_WIDTH{1'b0}};\nreg\t\t\t\t\t\t\t\t\trDataDone=0, _rDataDone=0;\nreg\t\t\t\t\t\t\t\t\trDataErr=0, _rDataErr=0;\nreg\t\t\t\t\t\t\t\t\trDataValid=0, _rDataValid=0;\nreg\t\t[7:0]\t\t\t\t\t\trChnlShft=0, _rChnlShft=0;\n\nreg rQWACpl,_rQWACpl;\nreg rQWAReq,_rQWAReq;\n\nwire wALTERA = C_ALTERA;\n\nwire [31:0] wReqData;\nwire [C_PCI_DATA_WIDTH-1:0] wDataOut;\n\nassign wReqData = wALTERA? rReqData :{rReqData[7:0], rReqData[15:8], rReqData[23:16], rReqData[31:24]};\nassign wDataOut = wALTERA? rDataOut :{rDataOut[39:32], rDataOut[47:40], rDataOut[55:48], rDataOut[63:56],\n\t\t\t\t\t\t\t\t\trDataOut[07:00], rDataOut[15:08], rDataOut[23:16], rDataOut[31:24]};\nassign RX_DATA_READY = 1;\nassign ENG_RD_COMPLETE = rDataDone;\n\n// Handle servicing write & read memory requests in a separate state machine.\nrx_engine_req #( \n\t.C_NUM_CHNL(C_NUM_CHNL)\n) rxEngReq (\n\t.CLK(CLK), \n\t.RST(RST), \n\t.REQ_WR(REQ_WR), \n\t.REQ_WR_DONE(REQ_WR_DONE), \n\t.REQ_RD(REQ_RD), \n\t.REQ_RD_DONE(REQ_RD_DONE), \n\t.REQ_LEN(REQ_LEN), \n\t.REQ_ADDR(REQ_ADDR), \n\t.REQ_DATA(REQ_DATA), \n\t.REQ_BE(REQ_BE), \n\t.REQ_TC(REQ_TC), \n\t.REQ_TD(REQ_TD), \n\t.REQ_EP(REQ_EP), \n\t.REQ_ATTR(REQ_ATTR), \n\t.REQ_ID(REQ_ID), \n\t.REQ_TAG(REQ_TAG),\n\t.WEN(rReqWen),\n\t.RNW(rRNW),\n\t.LEN(rReqLen), \n\t.ADDR(rReqAddr), \n\t.DATA(wReqData), \n\t.BE(rBE), \n\t.TC(rTC), \n\t.TD(rTD), \n\t.EP(rEP), \n\t.ATTR(rAttr), \n\t.ID(rReqId), \n\t.TAG(rReqTag)\n);\n\n\n// Handle reordering completion data.\nreorder_queue #( \n\t.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),\n\t.C_NUM_CHNL(C_NUM_CHNL),\n\t.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),\n\t.C_TAG_WIDTH(C_TAG_WIDTH)\n) reorderQueue (\n\t.CLK(CLK), \n\t.RST(RST), \n\t.VALID(rDataValid), \n\t.DATA(wDataOut), \n\t.DATA_EN(rDataOutEn), \n\t.DATA_EN_COUNT(rDataOutCount), \n\t.DONE(rDataDone), \n\t.ERR(rDataErr), \n\t.TAG(rChnlShft[C_TAG_WIDTH-1:0]), \n\t.INT_TAG(INT_TAG), \n\t.INT_TAG_VALID(INT_TAG_VALID), \n\t.EXT_TAG(EXT_TAG), \n\t.EXT_TAG_VALID(EXT_TAG_VALID), \n\t.ENG_DATA(ENG_DATA), \n\t.MAIN_DATA_EN(MAIN_DATA_EN), \n\t.MAIN_DONE(MAIN_DONE),\n\t.MAIN_ERR(MAIN_ERR),\n\t.SG_RX_DATA_EN(SG_RX_DATA_EN),\n\t.SG_RX_DONE(SG_RX_DONE),\n\t.SG_RX_ERR(SG_RX_ERR), \n\t.SG_TX_DATA_EN(SG_TX_DATA_EN), \n\t.SG_TX_DONE(SG_TX_DONE), \n\t.SG_TX_ERR(SG_TX_ERR)\n);\n\n\n// Handle receiving data from PCIe receive channel.\nwire wValid = (RX_DATA_VALID & !RX_TLP_ERROR_POISON);\nalways @ (posedge CLK) begin\n\trTrigger <= #1 (RST ? 3'd0 : _rTrigger);\n\trValidIn <= #1 (RST ? 1'd0 : _rValidIn);\n\trDataIn <= #1 _rDataIn;\n\trKeepBothIn <= #1 _rKeepBothIn;\n\trLastIn <= #1 _rLastIn;\n\trLenOneIn <= #1 _rLenOneIn;\n rQWACpl <= #1 _rQWACpl;\nend\n\nalways @ (*) begin\n\t_rDataIn = rDataIn;\n\t_rValidIn = rValidIn;\n\t_rKeepBothIn = rKeepBothIn;\n\t_rLastIn = rLastIn;\n\t_rLenOneIn = rLenOneIn;\n\t_rTrigger = rTrigger;\n _rQWACpl = rQWACpl;\n\n\t// Buffer the incoming data\n\t_rDataIn = RX_DATA;\n\t_rValidIn = (RX_DATA_VALID && !RX_TLP_ERROR_POISON);\n\t_rKeepBothIn = (RX_DATA_BYTE_ENABLE == 8'hFF);\n\t_rLastIn = RX_TLP_END_FLAG;\n\t_rLenOneIn = (RX_DATA[9:0] == 10'd1);\n _rQWACpl = ~RX_DATA[2];\n\n\t// Direct the main FSM with what kind of packet this represents\n\tcase (RX_DATA[30:24])\n\t\t`FMT_RXENG64_RD32 :\t_rTrigger = 3'd1 & ({3{wValid}});\n\t\t`FMT_RXENG64_RD64 :\t_rTrigger = 3'd1 & ({3{wValid}});\n\t\t`FMT_RXENG64_WR32 :\t_rTrigger = 3'd2 & ({3{wValid}});\n\t\t`FMT_RXENG64_WR64 :\t_rTrigger = 3'd2 & ({3{wValid}});\n\t\t`FMT_RXENG64_CPL :\t_rTrigger = 3'd3 & ({3{wValid}});\n\t\t`FMT_RXENG64_CPLD :\t_rTrigger = 3'd4 & ({3{wValid}});\n\t\tdefault\t\t\t :\t_rTrigger = 3'd5 & ({3{wValid}});\n\tendcase\nend\n\n\n// Handle receiving memory reads and writes.\nalways @ (posedge CLK) begin\n\trReqState <= #1 (RST ? `S_RXENG64_REQ_PARSE : _rReqState);\n\trReqWen <= #1 (RST ? 1'd0 : _rReqWen);\n\trRNW <= #1 _rRNW;\n\trTC <= #1 _rTC;\n\trTD <= #1 _rTD;\n\trEP <= #1 _rEP;\n\trAttr <= #1 _rAttr;\n\trReqLen <= #1 _rReqLen;\n\trReqId <= #1 _rReqId;\n\trReqTag <= #1 _rReqTag;\n\trBE <= #1 _rBE;\n\tr3DWHeader <= #1 _r3DWHeader;\n\trReqData <= #1 _rReqData;\n\trReqAddr <= #1 _rReqAddr;\n\trQWAReq <= #1 _rQWAReq;\nend\n\nalways @ (*) begin\n\t_rReqState = rReqState;\n\t_rTC = rTC;\n\t_rTD = rTD;\n\t_rEP = rEP;\n\t_rAttr = rAttr;\n\t_rReqLen = rReqLen;\n\t_rReqId = rReqId;\n\t_rReqTag = rReqTag;\n\t_rBE = rBE;\n\t_r3DWHeader = r3DWHeader;\n\t_rReqData = rReqData;\n\t_rReqAddr = rReqAddr;\n\t_rReqWen = rReqWen;\n\t_rRNW = rRNW;\n _rQWAReq = rQWAReq;\n\n\tcase (rReqState)\n\n\t`S_RXENG64_REQ_PARSE : begin // Process DW0, DW1\n\t\t_rTC = rDataIn[22:20];\n\t\t_rTD = rDataIn[15];\n\t\t_rEP = rDataIn[14];\n\t\t_rAttr = rDataIn[13:12];\n\t\t_rReqLen = rDataIn[9:0];\n\t\t_rReqId = rDataIn[63:48];\n\t\t_rReqTag = rDataIn[47:40];\n\t\t_rBE = rDataIn[35:32];\t\n\t\t_r3DWHeader = !rDataIn[29];\n\t\t_rReqWen = 0;\n\t\t// Trigger only set if the packet is valid\n\t\tcase (rTrigger) \n\t\t\t3'd0 :\t\t_rReqState = rReqState; \n\t\t\t3'd1 :\t\t_rReqState = (rLenOneIn ? `S_RXENG64_REQ_MEM_RD_0 : `S_RXENG64_REQ_UNHANDLED);\n\t\t\t3'd2 :\t\t_rReqState = (rLenOneIn ? `S_RXENG64_REQ_MEM_WR_0 : `S_RXENG64_REQ_UNHANDLED);\n\t\t\tdefault :\t_rReqState = `S_RXENG64_REQ_UNHANDLED;\n\t\tendcase\n\tend \n\n\t`S_RXENG64_REQ_UNHANDLED : begin\n\t\tif (rValidIn & rLastIn)\n\t\t\t_rReqState = `S_RXENG64_REQ_PARSE;\t\t\n\tend\n\n\t`S_RXENG64_REQ_MEM_RD_0 : begin\n\t\t_rReqAddr = (r3DWHeader ? rDataIn[31:2] : rDataIn[63:34]);\n\t\t_rRNW = 1;\n\t\t_rReqWen = (rValidIn & rLastIn);\n\t\tif (rValidIn)\n\t\t\t_rReqState = (rLastIn ? `S_RXENG64_REQ_PARSE : `S_RXENG64_REQ_UNHANDLED);\n\tend\n\n\t`S_RXENG64_REQ_MEM_WR_0 : begin\n\t\t_rReqData = rDataIn[63:32];\n\t\t_rReqAddr = (r3DWHeader ? rDataIn[31:2] : rDataIn[63:34]);\n _rQWAReq = (~rDataIn[2] & r3DWHeader) | (~r3DWHeader & ~rDataIn[34]);\n\t\t_rRNW = 0;\n\t\t_rReqWen = (rValidIn & rLastIn);\n\t\tif (rValidIn) begin\n\t\t\t_rReqState = (rLastIn ? `S_RXENG64_REQ_PARSE : `S_RXENG64_REQ_MEM_WR_1);\n\t\tend\n\tend\n\n\t`S_RXENG64_REQ_MEM_WR_1 : begin\n\t\t_rReqData = rDataIn >> ({5'd0,~(rQWAReq | (~wALTERA))} << 5);\n\t\t_rReqWen = (rValidIn & rLastIn);\n\t\tif (rValidIn)\n\t\t\t_rReqState = (rLastIn ? `S_RXENG64_REQ_PARSE : `S_RXENG64_REQ_UNHANDLED);\n\tend\n\n\tdefault : begin\n\t\t_rReqState = `S_RXENG64_REQ_PARSE;\n\tend\n\n\tendcase\nend\n\n\n// When signaled, start processing the packet, handle cpls and cplds.\nalways @ (posedge CLK) begin\n\trCplState <= #1 (RST ? `S_RXENG64_CPL_PARSE : _rCplState);\n\trDataOutEn <= #1 (RST ? 2'd0 : _rDataOutEn);\n\trDataOutCount <= #1 (RST ? 2'd0 : _rDataOutCount);\n\trDataDone <= #1 (RST ? 1'd0 : _rDataDone);\n\trDataErr <= #1 (RST ? 1'd0 : _rDataErr);\n\trDataValid <= #1 (RST ? 1'd0 : _rDataValid);\n\trCplErr <= #1 _rCplErr;\n\trLastCPLD <= #1 _rLastCPLD;\n\trDataOut <= #1 _rDataOut;\n\trChnlShft <= #1 _rChnlShft;\nend\n\nalways @ (*) begin\n\t_rCplState = rCplState;\n\t_rCplErr = rCplErr;\n\t_rLastCPLD = rLastCPLD;\n\t_rDataOut = rDataOut;\n\t_rDataOutEn = rDataOutEn;\n\t_rDataOutCount = rDataOutCount;\n\t_rDataDone = rDataDone;\n\t_rDataErr = rDataErr;\n\t_rDataValid = rDataValid;\n\t_rChnlShft = rChnlShft;\n\tcase (rCplState)\n\n\t`S_RXENG64_CPL_PARSE : begin // Process DW0, DW1\n\t\t_rDataOutEn = 0;\n\t\t_rDataOutCount = 0;\n\t\t_rDataDone = 0;\n\t\t_rDataErr = 0;\n\t\t_rDataValid = 0;\n\t\t_rCplErr = (rDataIn[47:45] != 3'b000); // Completion status code\n\t\t_rLastCPLD = (rDataIn[43:32] == (rDataIn[9:0]<<2)); // byte_count == length ?\n\t\t// Trigger only set if the packet is valid\n\t\tcase (rTrigger) \n\t\t\t3'd0 :\t\t_rCplState = rCplState;\n\t\t\t3'd3 :\t\t_rCplState = `S_RXENG64_CPL_NO_DATA;\n\t\t\t3'd4 :\t\t_rCplState = `S_RXENG64_CPL_DATA;\n\t\t\tdefault :\t_rCplState = `S_RXENG64_CPL_WAIT_FOR_END;\n\t\tendcase\n\tend \n\n\t`S_RXENG64_CPL_WAIT_FOR_END : begin // Wait until the end of the TLP\n\t\t_rDataOutEn = 0;\n\t\t_rDataOutCount = 0;\n\t\t_rDataDone = 0;\n\t\t_rDataErr = 0;\n\t\t_rDataValid = 0;\n\t\tif (rValidIn & rLastIn)\n\t\t\t_rCplState = `S_RXENG64_CPL_PARSE;\t\t\n\tend\n\n\t`S_RXENG64_CPL_NO_DATA : begin // Process DW2\n\t\t_rChnlShft = rDataIn[15:8]; // Tag is [15:8]\n\t\t_rDataValid = rValidIn;\n\t\tif (rValidIn) begin\n\t\t\t_rDataOutEn = 0;\n\t\t\t_rDataOutCount = 0;\n\t\t\t_rDataErr = rCplErr;\n\t\t\t_rDataDone = 1;\n\t\t\t_rCplState = (rLastIn ? `S_RXENG64_CPL_PARSE : `S_RXENG64_CPL_WAIT_FOR_END);\n\t\tend\n\tend\n\n\t`S_RXENG64_CPL_DATA : begin // Process DW2, DW3\n\t\t_rChnlShft = rDataIn[15:8]; // Tag is [15:8]\n\t\t_rDataValid = rValidIn;\n\t\t_rDataOut = (rDataIn>>32);\n\t\tif (rValidIn) begin\n\t\t\t_rDataOutEn = rKeepBothIn & (~rQWACpl | ~wALTERA);\n\t\t\t_rDataOutCount = rKeepBothIn & (~rQWACpl | ~wALTERA);\n\t\t\t_rDataDone = (rCplErr | (rLastIn & rLastCPLD));\n\t\t\t_rDataErr = rCplErr;\n\t\t\tif (rLastIn) // Ends in this packet\n\t\t\t\t_rCplState = `S_RXENG64_CPL_PARSE;\n\t\t\telse if (rCplErr) // Bad completion code\n\t\t\t\t_rCplState = `S_RXENG64_CPL_WAIT_FOR_END;\n\t\t\telse // Continues past this packet, send 1 DW now\n\t\t\t\t_rCplState = `S_RXENG64_CPL_DATA_CONT;\n\t\tend\n\tend\n\n\t`S_RXENG64_CPL_DATA_CONT : begin // Process packet until end\n\t\t_rDataValid = rValidIn;\n\t\t_rDataOut = rDataIn;\n\t\tif (rValidIn) begin // Process and write until last packet\n\t\t\t_rDataOutEn = {(!rLastIn | rKeepBothIn), 1'b1};\n\t\t\t_rDataOutCount = (2'd1<<(!rLastIn | rKeepBothIn));\n\t\t\t_rDataDone = (rLastIn & rLastCPLD);\n\t\t\t_rDataErr = 0;\n\t\t\t_rCplState = (rLastIn ? `S_RXENG64_CPL_PARSE : `S_RXENG64_CPL_DATA_CONT);\n\t\tend\n\tend\n\n\tendcase\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/rx_engine_req.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\trx_engine_req.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tHandles write and read memory requests for the rx_engine\n// by queuing them up and processing in a separate state machine. This allows\n// the rx_engine to process incoming TLPs at line rate. \n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments:\n//-----------------------------------------------------------------------------\n`define S_RXENGREQ_IDLE\t\t2'd0\n`define S_RXENGREQ_PAUSE\t2'd1\n`define S_RXENGREQ_ASSIGN\t2'd2\n`define S_RXENGREQ_WAIT\t\t2'd3\n\nmodule rx_engine_req #(\n\tparameter C_NUM_CHNL = 4'd12,\n\t// Local parameters\n\tparameter C_FIFO_DEPTH = 6*C_NUM_CHNL,\n\tparameter C_WR_DATA_WIDTH = 30+32, // 62\n\tparameter C_RD_DATA_WIDTH = 30+10+4+3+1+1+2+16+8, // 75\n\tparameter C_FIFO_WIDTH = (C_WR_DATA_WIDTH > C_RD_DATA_WIDTH ? C_WR_DATA_WIDTH : C_RD_DATA_WIDTH) + 1\n)\n(\n\tinput CLK,\n\tinput RST,\n\n\t// Received read/write memory requests\n\toutput REQ_WR,\t\t\t\t// Memory write request\n\tinput REQ_WR_DONE,\t\t\t// Memory write completed\n\toutput REQ_RD,\t\t\t\t// Memory read request\n\tinput REQ_RD_DONE,\t\t\t// Memory read complete\n\toutput [9:0] REQ_LEN,\t\t// Memory length (1DW)\n\toutput [29:0] REQ_ADDR,\t\t// Memory address (bottom 2 bits are always 00)\n\toutput [31:0] REQ_DATA,\t\t// Memory write data\n\toutput [3:0] REQ_BE,\t\t// Memory byte enables\n\toutput [2:0] REQ_TC,\t\t// Memory traffic class\n\toutput REQ_TD,\t\t\t\t// Memory packet digest\n\toutput REQ_EP, \t\t// Memory poisoned packet\n\toutput [1:0] REQ_ATTR,\t\t// Memory packet relaxed ordering, no snoop\n\toutput [15:0] REQ_ID,\t\t// Memory requestor id\n\toutput [7:0] REQ_TAG,\t\t// Memory packet tag\n\n\t// Memory requests \n\tinput WEN,\t\t\t\t\t// Memory request write enable\n\tinput RNW,\t\t\t\t\t// Memory read (not write) request\n\tinput [9:0] LEN,\t\t\t// Memory length (1DW)\n\tinput [29:0] ADDR,\t\t\t// Memory address (bottom 2 bits are always 00)\n\tinput [31:0] DATA,\t\t\t// Memory write data\n\tinput [3:0] BE,\t\t\t\t// Memory byte enables\n\tinput [2:0] TC,\t\t\t\t// Memory traffic class\n\tinput TD,\t\t\t\t\t// Memory packet digest\n\tinput EP, \t\t\t\t// Memory poisoned packet\n\tinput [1:0] ATTR,\t\t\t// Memory packet relaxed ordering, no snoop\n\tinput [15:0] ID,\t\t\t// Memory requestor id\n\tinput [7:0] TAG\t\t\t\t// Memory packet tag\n\n);\n\n`include \"common_functions.v\"\n\nreg\t\t[1:0]\t\t\t\t\t\trState=`S_RXENGREQ_IDLE, _rState=`S_RXENGREQ_IDLE;\nreg\t\t\t\t\t\t\t\t\trRd=0, _rRd=0;\nreg\t\t\t\t\t\t\t\t\trWr=0, _rWr=0;\nreg\t\t\t\t\t\t\t\t\trRen=0, _rRen=0;\nreg\t\t[29:0]\t\t\t\t\t\trAddr=0, _rAddr=0;\nreg\t\t[31:0]\t\t\t\t\t\trData=0, _rData=0;\nreg\t\t[2:0]\t\t\t\t\t\trTC=0, _rTC=0;\nreg\t\t\t\t\t\t\t\t\trTD=0, _rTD=0;\nreg\t\t\t\t\t\t\t\t\trEP=0, _rEP=0;\nreg\t\t[1:0]\t\t\t\t\t\trAttr=0, _rAttr=0;\nreg\t\t[9:0]\t\t\t\t\t\trLen=0, _rLen=0;\nreg\t\t[15:0]\t\t\t\t\t\trId=0, _rId=0;\nreg\t\t[7:0]\t\t\t\t\t\trTag=0, _rTag=0;\nreg\t\t[3:0]\t\t\t\t\t\trBE=0, _rBE=0;\nwire\t\t\t\t\t\t\t\twFifoEmpty;\nwire\t[C_FIFO_WIDTH-1:0]\t\t\twDataOut;\nwire\t[C_FIFO_WIDTH-1:0]\t\t\twDataIn = ({LEN, BE, TC, TD, EP, ATTR, ID, TAG, ADDR, RNW, DATA, RNW})>>(33*RNW);\n\n\nassign REQ_RD = rRd;\nassign REQ_WR = rWr;\nassign REQ_ADDR = rAddr;\nassign REQ_DATA = rData;\nassign REQ_BE = rBE;\nassign REQ_TC = rTC;\nassign REQ_TD = rTD;\nassign REQ_EP = rEP;\nassign REQ_ATTR = rAttr;\nassign REQ_LEN = rLen;\nassign REQ_ID = rId;\nassign REQ_TAG = rTag;\n\n\n// FIFO for storing data for read/write requests.\n(* RAM_STYLE=\"DISTRIBUTED\" *)\nsync_fifo #(.C_WIDTH(C_FIFO_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (\n\t.RST(RST),\n\t.CLK(CLK),\n\t.WR_EN(WEN),\n\t.WR_DATA(wDataIn),\n\t.FULL(),\n\t.COUNT(),\n\t.RD_EN(rRen),\n\t.RD_DATA(wDataOut),\n\t.EMPTY(wFifoEmpty)\n);\n\n\n// Process writes and reads when the FIFOs are not empty. This will always \n// process writes over reads.\nalways @ (posedge CLK) begin\n\trState <= #1 (RST ? `S_RXENGREQ_IDLE : _rState);\n\trRd <= #1 (RST ? 1'd0 : _rRd);\n\trWr <= #1 (RST ? 1'd0 : _rWr);\n\trRen <= #1 (RST ? 1'd0 : _rRen);\n\trAddr <= #1 _rAddr;\n\trData <= #1 _rData;\n\trLen <= #1 _rLen;\n\trBE <= #1 _rBE;\n\trTC <= #1 _rTC;\n\trTD <= #1 _rTD;\n\trEP <= #1 _rEP;\n\trAttr <= #1 _rAttr;\n\trId <= #1 _rId;\n\trTag <= #1 _rTag;\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\t_rRd = rRd;\n\t_rWr = rWr;\n\t_rRen = rRen;\n\t_rAddr = rAddr;\n\t_rData = rData;\n\t_rLen = rLen;\n\t_rBE = rBE;\n\t_rTC = rTC;\n\t_rTD = rTD;\n\t_rEP = rEP;\n\t_rAttr = rAttr;\n\t_rId = rId;\n\t_rTag = rTag;\n\t\n\tcase (rState)\n\t\n\t`S_RXENGREQ_IDLE: begin\n\t\tif (!wFifoEmpty) begin\n\t\t\t_rRen = 1;\n\t\t\t_rState = `S_RXENGREQ_PAUSE;\n\t\tend\n\tend\n\n\t`S_RXENGREQ_PAUSE: begin\n\t\t_rRen = 0;\n\t\t_rState = `S_RXENGREQ_ASSIGN;\n\tend\n\n\t`S_RXENGREQ_ASSIGN: begin\n\t\t_rWr = !wDataOut[0]; // !RNW\n\t\t_rRd = wDataOut[0]; // RNW\n\t\tif (wDataOut[0]) begin\n\t\t\t{_rLen, _rBE, _rTC, _rTD, _rEP, _rAttr, _rId, _rTag, _rAddr} = wDataOut[C_FIFO_WIDTH-1:1];\n\t\tend\n\t\telse begin\n\t\t\t_rAddr = wDataOut[63:34];\n\t\t\t_rData = wDataOut[32:1];\n\t\tend\t\t\n\t\t_rState = `S_RXENGREQ_WAIT;\n\tend\n\n\t`S_RXENGREQ_WAIT: begin\n\t\tif (rWr & REQ_WR_DONE) begin\n\t\t\t_rWr = 0;\n\t\t\t_rState = `S_RXENGREQ_IDLE;\n\t\tend\n\t\telse if (rRd & REQ_RD_DONE) begin\n\t\t\t_rRd = 0;\n\t\t\t_rState = `S_RXENGREQ_IDLE;\n\t\tend\n\tend\n\t\n\tendcase\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/rx_port_128.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\trx_port_128.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tReceives data from the rx_engine and buffers the output \n//\t\t\t\t\t\tfor the RIFFA channel.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule rx_port_128 #(\n\tparameter C_DATA_WIDTH = 9'd128,\n\tparameter C_MAIN_FIFO_DEPTH = 1024,\n\tparameter C_SG_FIFO_DEPTH = 512,\n\tparameter C_MAX_READ_REQ = 2,\t\t\t\t\t// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t// Local parameters\n\tparameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),\n\tparameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),\n\tparameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [2:0] CONFIG_MAX_READ_REQUEST_SIZE,\t\t\t\t// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\n\toutput SG_RX_BUF_RECVD,\t\t\t\t\t\t\t// Scatter gather RX buffer completely read (ready for next if applicable)\n\tinput [31:0] SG_RX_BUF_DATA,\t\t\t\t\t// Scatter gather RX buffer data\n\tinput SG_RX_BUF_LEN_VALID,\t\t\t\t\t\t// Scatter gather RX buffer length valid\n\tinput SG_RX_BUF_ADDR_HI_VALID,\t\t\t\t\t// Scatter gather RX buffer high address valid\n\tinput SG_RX_BUF_ADDR_LO_VALID,\t\t\t\t\t// Scatter gather RX buffer low address valid\n\n\toutput SG_TX_BUF_RECVD,\t\t\t\t\t\t\t// Scatter gather TX buffer completely read (ready for next if applicable)\n\tinput [31:0] SG_TX_BUF_DATA,\t\t\t\t\t// Scatter gather TX buffer data\n\tinput SG_TX_BUF_LEN_VALID,\t\t\t\t\t\t// Scatter gather TX buffer length valid\n\tinput SG_TX_BUF_ADDR_HI_VALID,\t\t\t\t\t// Scatter gather TX buffer high address valid\n\tinput SG_TX_BUF_ADDR_LO_VALID,\t\t\t\t\t// Scatter gather TX buffer low address valid\n\n\toutput [C_DATA_WIDTH-1:0] SG_DATA,\t\t\t\t// Scatter gather TX buffer data\n\toutput SG_DATA_EMPTY,\t\t\t\t\t\t\t// Scatter gather TX buffer data empty\n\tinput SG_DATA_REN,\t\t\t\t\t\t\t\t// Scatter gather TX buffer data read enable\n\tinput SG_RST,\t\t\t\t\t\t\t\t\t// Scatter gather TX buffer data reset\n\toutput SG_ERR,\t\t\t\t\t\t\t\t\t// Scatter gather TX encountered an error\n\t\n\tinput [31:0] TXN_DATA,\t\t\t\t\t\t\t// Read transaction data\n\tinput TXN_LEN_VALID,\t\t\t\t\t\t\t// Read transaction length valid\n\tinput TXN_OFF_LAST_VALID,\t\t\t\t\t\t// Read transaction offset/last valid\n\toutput [31:0] TXN_DONE_LEN,\t\t\t\t\t\t// Read transaction actual transfer length\n\toutput TXN_DONE,\t\t\t\t\t\t\t\t// Read transaction done\n\tinput TXN_DONE_ACK,\t\t\t\t\t\t\t\t// Read transaction actual transfer length read\n\n\toutput RX_REQ,\t\t\t\t\t\t\t\t\t// Read request\n\tinput RX_REQ_ACK,\t\t\t\t\t\t\t\t// Read request accepted\n\toutput [1:0] RX_REQ_TAG,\t\t\t\t\t\t// Read request data tag \n\toutput [63:0] RX_REQ_ADDR,\t\t\t\t\t\t// Read request address\n\toutput [9:0] RX_REQ_LEN,\t\t\t\t\t\t// Read request length\n\n\tinput [C_DATA_WIDTH-1:0] MAIN_DATA,\t\t\t\t// Main incoming data \n\tinput [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,\t\t// Main incoming data enable\n\tinput MAIN_DONE,\t\t\t\t\t\t\t\t// Main incoming data complete\n\tinput MAIN_ERR,\t\t\t\t\t\t\t\t\t// Main incoming data completed with error\n\tinput [C_DATA_WIDTH-1:0] SG_RX_DATA,\t\t\t// Scatter gather for RX incoming data \n\tinput [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,\t// Scatter gather for RX incoming data enable\n\tinput SG_RX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for RX incoming data complete\n\tinput SG_RX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for RX incoming data completed with error\n\tinput [C_DATA_WIDTH-1:0] SG_TX_DATA,\t\t\t// Scatter gather for TX incoming data \n\tinput [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,\t// Scatter gather for TX incoming data enable\n\tinput SG_TX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for TX incoming data complete\n\tinput SG_TX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for TX incoming data completed with error\n\n\tinput CHNL_CLK,\t\t\t\t\t\t\t\t\t// Channel read clock\n\toutput CHNL_RX,\t\t\t\t\t\t\t\t\t// Channel read receive signal\n\tinput CHNL_RX_ACK,\t\t\t\t\t\t\t\t// Channle read received signal\n\toutput CHNL_RX_LAST,\t\t\t\t\t\t\t// Channel last read\n\toutput [31:0] CHNL_RX_LEN,\t\t\t\t\t\t// Channel read length\n\toutput [30:0] CHNL_RX_OFF,\t\t\t\t\t\t// Channel read offset\n\toutput [C_DATA_WIDTH-1:0] CHNL_RX_DATA,\t\t\t// Channel read data\n\toutput CHNL_RX_DATA_VALID,\t\t\t\t\t\t// Channel read data valid\n\tinput CHNL_RX_DATA_REN\t\t\t\t\t\t\t// Channel read data has been recieved\n);\n\n`include \"common_functions.v\"\n\n\nassign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);\n\n\nwire\t[C_DATA_WIDTH-1:0]\t\t\twPackedMainData;\nwire\t\t\t\t\t\t\t\twPackedMainWen;\nwire\t\t\t\t\t\t\t\twPackedMainDone;\nwire\t\t\t\t\t\t\t\twPackedMainErr;\nwire\t\t\t\t\t\t\t\twMainFlush;\nwire\t\t\t\t\t\t\t\twMainFlushed;\n\nwire\t[C_DATA_WIDTH-1:0]\t\t\twPackedSgRxData;\nwire\t\t\t\t\t\t\t\twPackedSgRxWen;\nwire\t\t\t\t\t\t\t\twPackedSgRxDone;\nwire\t\t\t\t\t\t\t\twPackedSgRxErr;\nwire\t\t\t\t\t\t\t\twSgRxFlush;\nwire\t\t\t\t\t\t\t\twSgRxFlushed;\n\nwire\t[C_DATA_WIDTH-1:0]\t\t\twPackedSgTxData;\nwire\t\t\t\t\t\t\t\twPackedSgTxWen;\nwire\t\t\t\t\t\t\t\twPackedSgTxDone;\nwire\t\t\t\t\t\t\t\twPackedSgTxErr;\nwire\t\t\t\t\t\t\t\twSgTxFlush;\nwire\t\t\t\t\t\t\t\twSgTxFlushed;\n\nwire\t\t\t\t\t\t\t\twMainDataRen;\nwire\t\t\t\t\t\t\t\twMainDataEmpty;\nwire\t[C_DATA_WIDTH-1:0]\t\t\twMainData;\n\nwire\t\t\t\t\t\t\t\twSgRxRst;\nwire\t\t\t\t\t\t\t\twSgRxDataRen;\nwire\t\t\t\t\t\t\t\twSgRxDataEmpty;\nwire\t[C_DATA_WIDTH-1:0]\t\t\twSgRxData;\nwire\t[C_SG_FIFO_DEPTH_WIDTH-1:0]\twSgRxFifoCount;\n\nwire\t\t\t\t\t\t\t\twSgTxRst;\nwire\t[C_SG_FIFO_DEPTH_WIDTH-1:0]\twSgTxFifoCount;\n\nwire\t\t\t\t\t\t\t\twSgRxReq;\nwire\t[63:0]\t\t\t\t\t\twSgRxReqAddr;\nwire\t[9:0]\t\t\t\t\t\twSgRxReqLen;\n\nwire\t\t\t\t\t\t\t\twSgTxReq;\nwire\t[63:0]\t\t\t\t\t\twSgTxReqAddr;\nwire\t[9:0]\t\t\t\t\t\twSgTxReqLen;\n\nwire\t\t\t\t\t\t\t\twSgRxReqProc;\nwire\t\t\t\t\t\t\t\twSgTxReqProc;\nwire\t\t\t\t\t\t\t\twMainReqProc;\nwire\t\t\t\t\t\t\t\twReqAck;\n\nwire\t\t\t\t\t\t\t\twSgElemRdy;\nwire\t\t\t\t\t\t\t\twSgElemRen;\nwire\t[63:0]\t\t\t\t\t\twSgElemAddr;\nwire\t[31:0]\t\t\t\t\t\twSgElemLen;\n\nwire\t\t\t\t\t\t\t\twSgRst;\nwire\t\t\t\t\t\t\t\twMainReq;\nwire\t[63:0]\t\t\t\t\t\twMainReqAddr;\nwire\t[9:0]\t\t\t\t\t\twMainReqLen;\nwire\t\t\t\t\t\t\t\twTxnErr;\nwire\t\t\t\t\t\t\t\twChnlRx;\nwire\t\t\t\t\t\t\t\twChnlRxRecvd;\nwire\t\t\t\t\t\t\t\twChnlRxAckRecvd;\nwire\t\t\t\t\t\t\t\twChnlRxLast;\nwire\t[31:0]\t\t\t\t\t\twChnlRxLen;\nwire\t[30:0]\t\t\t\t\t\twChnlRxOff;\nwire\t[31:0]\t\t\t\t\t\twChnlRxConsumed;\n\nreg\t\t[4:0]\t\t\t\t\t\trWideRst=0;\nreg\t\t\t\t\t\t\t\t\trRst=0;\n\n\n// Generate a wide reset from the input reset.\nalways @ (posedge CLK) begin\n\trRst <= #1 rWideRst[4]; \n\tif (RST) \n\t\trWideRst <= #1 5'b11111;\n\telse \n\t\trWideRst <= (rWideRst<<1);\nend\n\n\n// Pack received data tightly into our FIFOs \nfifo_packer_128 mainFifoPacker (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.DATA_IN(MAIN_DATA),\n\t.DATA_IN_EN(MAIN_DATA_EN),\n\t.DATA_IN_DONE(MAIN_DONE),\n\t.DATA_IN_ERR(MAIN_ERR),\n\t.DATA_IN_FLUSH(wMainFlush),\n\t.PACKED_DATA(wPackedMainData),\n\t.PACKED_WEN(wPackedMainWen),\n\t.PACKED_DATA_DONE(wPackedMainDone),\n\t.PACKED_DATA_ERR(wPackedMainErr),\n\t.PACKED_DATA_FLUSHED(wMainFlushed)\n);\n\nfifo_packer_128 sgRxFifoPacker (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.DATA_IN(SG_RX_DATA),\n\t.DATA_IN_EN(SG_RX_DATA_EN),\n\t.DATA_IN_DONE(SG_RX_DONE),\n\t.DATA_IN_ERR(SG_RX_ERR),\n\t.DATA_IN_FLUSH(wSgRxFlush),\n\t.PACKED_DATA(wPackedSgRxData),\n\t.PACKED_WEN(wPackedSgRxWen),\n\t.PACKED_DATA_DONE(wPackedSgRxDone),\n\t.PACKED_DATA_ERR(wPackedSgRxErr),\n\t.PACKED_DATA_FLUSHED(wSgRxFlushed)\n);\n\nfifo_packer_128 sgTxFifoPacker (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.DATA_IN(SG_TX_DATA),\n\t.DATA_IN_EN(SG_TX_DATA_EN),\n\t.DATA_IN_DONE(SG_TX_DONE),\n\t.DATA_IN_ERR(SG_TX_ERR),\n\t.DATA_IN_FLUSH(wSgTxFlush),\n\t.PACKED_DATA(wPackedSgTxData),\n\t.PACKED_WEN(wPackedSgTxWen),\n\t.PACKED_DATA_DONE(wPackedSgTxDone),\n\t.PACKED_DATA_ERR(wPackedSgTxErr),\n\t.PACKED_DATA_FLUSHED(wSgTxFlushed)\n);\n\n\n// FIFOs for storing received data for the channel.\n(* RAM_STYLE=\"BLOCK\" *)\nasync_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (\n\t.WR_CLK(CLK),\n\t.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),\n\t.WR_EN(wPackedMainWen),\n\t.WR_DATA(wPackedMainData),\n\t.WR_FULL(),\n\t.RD_CLK(CHNL_CLK),\n\t.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),\n\t.RD_EN(wMainDataRen),\n\t.RD_DATA(wMainData),\n\t.RD_EMPTY(wMainDataEmpty)\n);\n\n(* RAM_STYLE=\"BLOCK\" *)\nsync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (\n\t.RST(rRst | wSgRxRst),\n\t.CLK(CLK),\n\t.WR_EN(wPackedSgRxWen),\n\t.WR_DATA(wPackedSgRxData),\n\t.FULL(),\n\t.RD_EN(wSgRxDataRen),\n\t.RD_DATA(wSgRxData),\n\t.EMPTY(wSgRxDataEmpty),\n\t.COUNT(wSgRxFifoCount)\n);\n\n(* RAM_STYLE=\"BLOCK\" *)\nsync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (\n\t.RST(rRst | wSgTxRst),\n\t.CLK(CLK),\n\t.WR_EN(wPackedSgTxWen),\n\t.WR_DATA(wPackedSgTxData),\n\t.FULL(),\n\t.RD_EN(SG_DATA_REN),\n\t.RD_DATA(SG_DATA),\n\t.EMPTY(SG_DATA_EMPTY),\n\t.COUNT(wSgTxFifoCount)\n);\n\n\n// Manage requesting and acknowledging scatter gather data. Note that\n// these modules will share the main requestor's RX channel. They will\n// take priority over the main logic's use of the RX channel.\nsg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),\n\t.USER_RST(wSgRst),\n\t.BUF_RECVD(SG_RX_BUF_RECVD),\n\t.BUF_DATA(SG_RX_BUF_DATA),\n\t.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),\n\t.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),\n\t.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),\n\t.FIFO_COUNT(wSgRxFifoCount),\n\t.FIFO_FLUSH(wSgRxFlush),\n\t.FIFO_FLUSHED(wSgRxFlushed),\n\t.FIFO_RST(wSgRxRst),\n\t.RX_REQ(wSgRxReq),\n\t.RX_ADDR(wSgRxReqAddr),\n\t.RX_LEN(wSgRxReqLen),\n\t.RX_REQ_ACK(wReqAck & wSgRxReqProc),\n\t.RX_DONE(wPackedSgRxDone)\n);\n\nsg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),\n\t.USER_RST(SG_RST),\n\t.BUF_RECVD(SG_TX_BUF_RECVD),\n\t.BUF_DATA(SG_TX_BUF_DATA),\n\t.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),\n\t.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),\n\t.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),\n\t.FIFO_COUNT(wSgTxFifoCount),\n\t.FIFO_FLUSH(wSgTxFlush),\n\t.FIFO_FLUSHED(wSgTxFlushed),\n\t.FIFO_RST(wSgTxRst),\n\t.RX_REQ(wSgTxReq),\n\t.RX_ADDR(wSgTxReqAddr),\n\t.RX_LEN(wSgTxReqLen),\n\t.RX_REQ_ACK(wReqAck & wSgTxReqProc),\n\t.RX_DONE(wPackedSgTxDone)\n);\n\n\n// A read requester for the channel and scatter gather requesters.\nrx_port_requester_mux requesterMux (\n\t.RST(rRst), \n\t.CLK(CLK), \n\t.SG_RX_REQ(wSgRxReq), \n\t.SG_RX_LEN(wSgRxReqLen), \n\t.SG_RX_ADDR(wSgRxReqAddr), \n\t.SG_RX_REQ_PROC(wSgRxReqProc),\n\t.SG_TX_REQ(wSgTxReq), \n\t.SG_TX_LEN(wSgTxReqLen), \n\t.SG_TX_ADDR(wSgTxReqAddr), \n\t.SG_TX_REQ_PROC(wSgTxReqProc),\n\t.MAIN_REQ(wMainReq), \n\t.MAIN_LEN(wMainReqLen), \n\t.MAIN_ADDR(wMainReqAddr), \n\t.MAIN_REQ_PROC(wMainReqProc),\n\t.RX_REQ(RX_REQ),\n\t.RX_REQ_ACK(RX_REQ_ACK),\n\t.RX_REQ_TAG(RX_REQ_TAG),\n\t.RX_REQ_ADDR(RX_REQ_ADDR),\n\t.RX_REQ_LEN(RX_REQ_LEN),\n\t.REQ_ACK(wReqAck)\n);\n\n\n// Read the scatter gather buffer address and length, continuously so that\n// we have it ready whenever the next buffer is needed.\nsg_list_reader_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (\n\t.CLK(CLK),\n\t.RST(rRst | wSgRst),\n\t.BUF_DATA(wSgRxData),\n\t.BUF_DATA_EMPTY(wSgRxDataEmpty),\n\t.BUF_DATA_REN(wSgRxDataRen),\n\t.VALID(wSgElemRdy),\n\t.EMPTY(),\n\t.REN(wSgElemRen),\n\t.ADDR(wSgElemAddr),\n\t.LEN(wSgElemLen)\n);\n\n\n// Main port reader logic\nrx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (\n\t.CLK(CLK), \n\t.RST(rRst), \n\t.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),\n\t.TXN_DATA(TXN_DATA), \n\t.TXN_LEN_VALID(TXN_LEN_VALID), \n\t.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID), \n\t.TXN_DONE_LEN(TXN_DONE_LEN),\n\t.TXN_DONE(TXN_DONE),\n\t.TXN_ERR(wTxnErr),\n\t.TXN_DONE_ACK(TXN_DONE_ACK),\n\t.TXN_DATA_FLUSH(wMainFlush),\n\t.TXN_DATA_FLUSHED(wMainFlushed),\n\t.RX_REQ(wMainReq),\n\t.RX_ADDR(wMainReqAddr),\n\t.RX_LEN(wMainReqLen),\n\t.RX_REQ_ACK(wReqAck & wMainReqProc),\n\t.RX_DATA_EN(MAIN_DATA_EN), \n\t.RX_DONE(wPackedMainDone),\n\t.RX_ERR(wPackedMainErr),\n\t.SG_DONE(wPackedSgRxDone), \n\t.SG_ERR(wPackedSgRxErr), \n\t.SG_ELEM_ADDR(wSgElemAddr), \n\t.SG_ELEM_LEN(wSgElemLen),\n\t.SG_ELEM_RDY(wSgElemRdy),\n\t.SG_ELEM_REN(wSgElemRen),\n\t.SG_RST(wSgRst),\n\t.CHNL_RX(wChnlRx), \n\t.CHNL_RX_LEN(wChnlRxLen), \n\t.CHNL_RX_LAST(wChnlRxLast),\n\t.CHNL_RX_OFF(wChnlRxOff), \n\t.CHNL_RX_RECVD(wChnlRxRecvd), \n\t.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd), \n\t.CHNL_RX_CONSUMED(wChnlRxConsumed)\n);\n\n\n// Manage the CHNL_RX* signals in the CHNL_CLK domain.\nrx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (\n\t.RST(rRst), \n\t.CLK(CLK), \n\t.RX(wChnlRx), \n\t.RX_RECVD(wChnlRxRecvd), \n\t.RX_ACK_RECVD(wChnlRxAckRecvd), \n\t.RX_LAST(wChnlRxLast), \n\t.RX_LEN(wChnlRxLen), \n\t.RX_OFF(wChnlRxOff), \n\t.RX_CONSUMED(wChnlRxConsumed), \n\t.RD_DATA(wMainData), \n\t.RD_EMPTY(wMainDataEmpty), \n\t.RD_EN(wMainDataRen), \n\t.CHNL_CLK(CHNL_CLK), \n\t.CHNL_RX(CHNL_RX), \n\t.CHNL_RX_ACK(CHNL_RX_ACK), \n\t.CHNL_RX_LAST(CHNL_RX_LAST), \n\t.CHNL_RX_LEN(CHNL_RX_LEN), \n\t.CHNL_RX_OFF(CHNL_RX_OFF), \n\t.CHNL_RX_DATA(CHNL_RX_DATA), \n\t.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), \n\t.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)\n);\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/rx_port_32.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\trx_port_32.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tReceives data from the rx_engine and buffers the output \n//\t\t\t\t\t\tfor the RIFFA channel.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule rx_port_32 #(\n\tparameter C_DATA_WIDTH = 9'd32,\n\tparameter C_MAIN_FIFO_DEPTH = 1024,\n\tparameter C_SG_FIFO_DEPTH = 512,\n\tparameter C_MAX_READ_REQ = 2,\t\t\t\t\t// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t// Local parameters\n\tparameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),\n\tparameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),\n\tparameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [2:0] CONFIG_MAX_READ_REQUEST_SIZE,\t\t\t\t// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\n\toutput SG_RX_BUF_RECVD,\t\t\t\t\t\t\t// Scatter gather RX buffer completely read (ready for next if applicable)\n\tinput [31:0] SG_RX_BUF_DATA,\t\t\t\t\t// Scatter gather RX buffer data\n\tinput SG_RX_BUF_LEN_VALID,\t\t\t\t\t\t// Scatter gather RX buffer length valid\n\tinput SG_RX_BUF_ADDR_HI_VALID,\t\t\t\t\t// Scatter gather RX buffer high address valid\n\tinput SG_RX_BUF_ADDR_LO_VALID,\t\t\t\t\t// Scatter gather RX buffer low address valid\n\n\toutput SG_TX_BUF_RECVD,\t\t\t\t\t\t\t// Scatter gather TX buffer completely read (ready for next if applicable)\n\tinput [31:0] SG_TX_BUF_DATA,\t\t\t\t\t// Scatter gather TX buffer data\n\tinput SG_TX_BUF_LEN_VALID,\t\t\t\t\t\t// Scatter gather TX buffer length valid\n\tinput SG_TX_BUF_ADDR_HI_VALID,\t\t\t\t\t// Scatter gather TX buffer high address valid\n\tinput SG_TX_BUF_ADDR_LO_VALID,\t\t\t\t\t// Scatter gather TX buffer low address valid\n\n\toutput [C_DATA_WIDTH-1:0] SG_DATA,\t\t\t\t// Scatter gather TX buffer data\n\toutput SG_DATA_EMPTY,\t\t\t\t\t\t\t// Scatter gather TX buffer data empty\n\tinput SG_DATA_REN,\t\t\t\t\t\t\t\t// Scatter gather TX buffer data read enable\n\tinput SG_RST,\t\t\t\t\t\t\t\t\t// Scatter gather TX buffer data reset\n\toutput SG_ERR,\t\t\t\t\t\t\t\t\t// Scatter gather TX encountered an error\n\t\n\tinput [31:0] TXN_DATA,\t\t\t\t\t\t\t// Read transaction data\n\tinput TXN_LEN_VALID,\t\t\t\t\t\t\t// Read transaction length valid\n\tinput TXN_OFF_LAST_VALID,\t\t\t\t\t\t// Read transaction offset/last valid\n\toutput [31:0] TXN_DONE_LEN,\t\t\t\t\t\t// Read transaction actual transfer length\n\toutput TXN_DONE,\t\t\t\t\t\t\t\t// Read transaction done\n\tinput TXN_DONE_ACK,\t\t\t\t\t\t\t\t// Read transaction actual transfer length read\n\n\toutput RX_REQ,\t\t\t\t\t\t\t\t\t// Read request\n\tinput RX_REQ_ACK,\t\t\t\t\t\t\t\t// Read request accepted\n\toutput [1:0] RX_REQ_TAG,\t\t\t\t\t\t// Read request data tag \n\toutput [63:0] RX_REQ_ADDR,\t\t\t\t\t\t// Read request address\n\toutput [9:0] RX_REQ_LEN,\t\t\t\t\t\t// Read request length\n\n\tinput [C_DATA_WIDTH-1:0] MAIN_DATA,\t\t\t\t// Main incoming data \n\tinput [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,\t\t// Main incoming data enable\n\tinput MAIN_DONE,\t\t\t\t\t\t\t\t// Main incoming data complete\n\tinput MAIN_ERR,\t\t\t\t\t\t\t\t\t// Main incoming data completed with error\n\tinput [C_DATA_WIDTH-1:0] SG_RX_DATA,\t\t\t// Scatter gather for RX incoming data \n\tinput [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,\t// Scatter gather for RX incoming data enable\n\tinput SG_RX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for RX incoming data complete\n\tinput SG_RX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for RX incoming data completed with error\n\tinput [C_DATA_WIDTH-1:0] SG_TX_DATA,\t\t\t// Scatter gather for TX incoming data \n\tinput [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,\t// Scatter gather for TX incoming data enable\n\tinput SG_TX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for TX incoming data complete\n\tinput SG_TX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for TX incoming data completed with error\n\n\tinput CHNL_CLK,\t\t\t\t\t\t\t\t\t// Channel read clock\n\toutput CHNL_RX,\t\t\t\t\t\t\t\t\t// Channel read receive signal\n\tinput CHNL_RX_ACK,\t\t\t\t\t\t\t\t// Channle read received signal\n\toutput CHNL_RX_LAST,\t\t\t\t\t\t\t// Channel last read\n\toutput [31:0] CHNL_RX_LEN,\t\t\t\t\t\t// Channel read length\n\toutput [30:0] CHNL_RX_OFF,\t\t\t\t\t\t// Channel read offset\n\toutput [C_DATA_WIDTH-1:0] CHNL_RX_DATA,\t\t\t// Channel read data\n\toutput CHNL_RX_DATA_VALID,\t\t\t\t\t\t// Channel read data valid\n\tinput CHNL_RX_DATA_REN\t\t\t\t\t\t\t// Channel read data has been recieved\n);\n\n`include \"common_functions.v\"\n\n\nassign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);\n\n\nwire\t[C_DATA_WIDTH-1:0]\t\t\twPackedMainData;\nwire\t\t\t\t\t\t\t\twPackedMainWen;\nwire\t\t\t\t\t\t\t\twPackedMainDone;\nwire\t\t\t\t\t\t\t\twPackedMainErr;\nwire\t\t\t\t\t\t\t\twMainFlush;\nwire\t\t\t\t\t\t\t\twMainFlushed;\n\nwire\t[C_DATA_WIDTH-1:0]\t\t\twPackedSgRxData;\nwire\t\t\t\t\t\t\t\twPackedSgRxWen;\nwire\t\t\t\t\t\t\t\twPackedSgRxDone;\nwire\t\t\t\t\t\t\t\twPackedSgRxErr;\nwire\t\t\t\t\t\t\t\twSgRxFlush;\nwire\t\t\t\t\t\t\t\twSgRxFlushed;\n\nwire\t[C_DATA_WIDTH-1:0]\t\t\twPackedSgTxData;\nwire\t\t\t\t\t\t\t\twPackedSgTxWen;\nwire\t\t\t\t\t\t\t\twPackedSgTxDone;\nwire\t\t\t\t\t\t\t\twPackedSgTxErr;\nwire\t\t\t\t\t\t\t\twSgTxFlush;\nwire\t\t\t\t\t\t\t\twSgTxFlushed;\n\nwire\t\t\t\t\t\t\t\twMainDataRen;\nwire\t\t\t\t\t\t\t\twMainDataEmpty;\nwire\t[C_DATA_WIDTH-1:0]\t\t\twMainData;\n\nwire\t\t\t\t\t\t\t\twSgRxRst;\nwire\t\t\t\t\t\t\t\twSgRxDataRen;\nwire\t\t\t\t\t\t\t\twSgRxDataEmpty;\nwire\t[C_DATA_WIDTH-1:0]\t\t\twSgRxData;\nwire\t[C_SG_FIFO_DEPTH_WIDTH-1:0]\twSgRxFifoCount;\n\nwire\t\t\t\t\t\t\t\twSgTxRst;\nwire\t[C_SG_FIFO_DEPTH_WIDTH-1:0]\twSgTxFifoCount;\n\nwire\t\t\t\t\t\t\t\twSgRxReq;\nwire\t[63:0]\t\t\t\t\t\twSgRxReqAddr;\nwire\t[9:0]\t\t\t\t\t\twSgRxReqLen;\n\nwire\t\t\t\t\t\t\t\twSgTxReq;\nwire\t[63:0]\t\t\t\t\t\twSgTxReqAddr;\nwire\t[9:0]\t\t\t\t\t\twSgTxReqLen;\n\nwire\t\t\t\t\t\t\t\twSgRxReqProc;\nwire\t\t\t\t\t\t\t\twSgTxReqProc;\nwire\t\t\t\t\t\t\t\twMainReqProc;\nwire\t\t\t\t\t\t\t\twReqAck;\n\nwire\t\t\t\t\t\t\t\twSgElemRdy;\nwire\t\t\t\t\t\t\t\twSgElemRen;\nwire\t[63:0]\t\t\t\t\t\twSgElemAddr;\nwire\t[31:0]\t\t\t\t\t\twSgElemLen;\n\nwire\t\t\t\t\t\t\t\twSgRst;\nwire\t\t\t\t\t\t\t\twMainReq;\nwire\t[63:0]\t\t\t\t\t\twMainReqAddr;\nwire\t[9:0]\t\t\t\t\t\twMainReqLen;\nwire\t\t\t\t\t\t\t\twTxnErr;\nwire\t\t\t\t\t\t\t\twChnlRx;\nwire\t\t\t\t\t\t\t\twChnlRxRecvd;\nwire\t\t\t\t\t\t\t\twChnlRxAckRecvd;\nwire\t\t\t\t\t\t\t\twChnlRxLast;\nwire\t[31:0]\t\t\t\t\t\twChnlRxLen;\nwire\t[30:0]\t\t\t\t\t\twChnlRxOff;\nwire\t[31:0]\t\t\t\t\t\twChnlRxConsumed;\n\nreg\t\t[4:0]\t\t\t\t\t\trWideRst=0;\nreg\t\t\t\t\t\t\t\t\trRst=0;\n\n\n// Generate a wide reset from the input reset.\nalways @ (posedge CLK) begin\n\trRst <= #1 rWideRst[4]; \n\tif (RST) \n\t\trWideRst <= #1 5'b11111;\n\telse \n\t\trWideRst <= (rWideRst<<1);\nend\n\n\n// Pack received data tightly into our FIFOs \nfifo_packer_32 mainFifoPacker (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.DATA_IN(MAIN_DATA),\n\t.DATA_IN_EN(MAIN_DATA_EN),\n\t.DATA_IN_DONE(MAIN_DONE),\n\t.DATA_IN_ERR(MAIN_ERR),\n\t.DATA_IN_FLUSH(wMainFlush),\n\t.PACKED_DATA(wPackedMainData),\n\t.PACKED_WEN(wPackedMainWen),\n\t.PACKED_DATA_DONE(wPackedMainDone),\n\t.PACKED_DATA_ERR(wPackedMainErr),\n\t.PACKED_DATA_FLUSHED(wMainFlushed)\n);\n\nfifo_packer_32 sgRxFifoPacker (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.DATA_IN(SG_RX_DATA),\n\t.DATA_IN_EN(SG_RX_DATA_EN),\n\t.DATA_IN_DONE(SG_RX_DONE),\n\t.DATA_IN_ERR(SG_RX_ERR),\n\t.DATA_IN_FLUSH(wSgRxFlush),\n\t.PACKED_DATA(wPackedSgRxData),\n\t.PACKED_WEN(wPackedSgRxWen),\n\t.PACKED_DATA_DONE(wPackedSgRxDone),\n\t.PACKED_DATA_ERR(wPackedSgRxErr),\n\t.PACKED_DATA_FLUSHED(wSgRxFlushed)\n);\n\nfifo_packer_32 sgTxFifoPacker (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.DATA_IN(SG_TX_DATA),\n\t.DATA_IN_EN(SG_TX_DATA_EN),\n\t.DATA_IN_DONE(SG_TX_DONE),\n\t.DATA_IN_ERR(SG_TX_ERR),\n\t.DATA_IN_FLUSH(wSgTxFlush),\n\t.PACKED_DATA(wPackedSgTxData),\n\t.PACKED_WEN(wPackedSgTxWen),\n\t.PACKED_DATA_DONE(wPackedSgTxDone),\n\t.PACKED_DATA_ERR(wPackedSgTxErr),\n\t.PACKED_DATA_FLUSHED(wSgTxFlushed)\n);\n\n\n// FIFOs for storing received data for the channel.\n(* RAM_STYLE=\"BLOCK\" *)\nasync_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (\n\t.WR_CLK(CLK),\n\t.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),\n\t.WR_EN(wPackedMainWen),\n\t.WR_DATA(wPackedMainData),\n\t.WR_FULL(),\n\t.RD_CLK(CHNL_CLK),\n\t.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),\n\t.RD_EN(wMainDataRen),\n\t.RD_DATA(wMainData),\n\t.RD_EMPTY(wMainDataEmpty)\n);\n\n(* RAM_STYLE=\"BLOCK\" *)\nsync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (\n\t.RST(rRst | wSgRxRst),\n\t.CLK(CLK),\n\t.WR_EN(wPackedSgRxWen),\n\t.WR_DATA(wPackedSgRxData),\n\t.FULL(),\n\t.RD_EN(wSgRxDataRen),\n\t.RD_DATA(wSgRxData),\n\t.EMPTY(wSgRxDataEmpty),\n\t.COUNT(wSgRxFifoCount)\n);\n\n(* RAM_STYLE=\"BLOCK\" *)\nsync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (\n\t.RST(rRst | wSgTxRst),\n\t.CLK(CLK),\n\t.WR_EN(wPackedSgTxWen),\n\t.WR_DATA(wPackedSgTxData),\n\t.FULL(),\n\t.RD_EN(SG_DATA_REN),\n\t.RD_DATA(SG_DATA),\n\t.EMPTY(SG_DATA_EMPTY),\n\t.COUNT(wSgTxFifoCount)\n);\n\n\n// Manage requesting and acknowledging scatter gather data. Note that\n// these modules will share the main requestor's RX channel. They will\n// take priority over the main logic's use of the RX channel.\nsg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),\n\t.USER_RST(wSgRst),\n\t.BUF_RECVD(SG_RX_BUF_RECVD),\n\t.BUF_DATA(SG_RX_BUF_DATA),\n\t.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),\n\t.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),\n\t.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),\n\t.FIFO_COUNT(wSgRxFifoCount),\n\t.FIFO_FLUSH(wSgRxFlush),\n\t.FIFO_FLUSHED(wSgRxFlushed),\n\t.FIFO_RST(wSgRxRst),\n\t.RX_REQ(wSgRxReq),\n\t.RX_ADDR(wSgRxReqAddr),\n\t.RX_LEN(wSgRxReqLen),\n\t.RX_REQ_ACK(wReqAck & wSgRxReqProc),\n\t.RX_DONE(wPackedSgRxDone)\n);\n\nsg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),\n\t.USER_RST(SG_RST),\n\t.BUF_RECVD(SG_TX_BUF_RECVD),\n\t.BUF_DATA(SG_TX_BUF_DATA),\n\t.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),\n\t.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),\n\t.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),\n\t.FIFO_COUNT(wSgTxFifoCount),\n\t.FIFO_FLUSH(wSgTxFlush),\n\t.FIFO_FLUSHED(wSgTxFlushed),\n\t.FIFO_RST(wSgTxRst),\n\t.RX_REQ(wSgTxReq),\n\t.RX_ADDR(wSgTxReqAddr),\n\t.RX_LEN(wSgTxReqLen),\n\t.RX_REQ_ACK(wReqAck & wSgTxReqProc),\n\t.RX_DONE(wPackedSgTxDone)\n);\n\n\n// A read requester for the channel and scatter gather requesters.\nrx_port_requester_mux requesterMux (\n\t.RST(rRst), \n\t.CLK(CLK), \n\t.SG_RX_REQ(wSgRxReq), \n\t.SG_RX_LEN(wSgRxReqLen), \n\t.SG_RX_ADDR(wSgRxReqAddr), \n\t.SG_RX_REQ_PROC(wSgRxReqProc),\n\t.SG_TX_REQ(wSgTxReq), \n\t.SG_TX_LEN(wSgTxReqLen), \n\t.SG_TX_ADDR(wSgTxReqAddr), \n\t.SG_TX_REQ_PROC(wSgTxReqProc),\n\t.MAIN_REQ(wMainReq), \n\t.MAIN_LEN(wMainReqLen), \n\t.MAIN_ADDR(wMainReqAddr), \n\t.MAIN_REQ_PROC(wMainReqProc),\n\t.RX_REQ(RX_REQ),\n\t.RX_REQ_ACK(RX_REQ_ACK),\n\t.RX_REQ_TAG(RX_REQ_TAG),\n\t.RX_REQ_ADDR(RX_REQ_ADDR),\n\t.RX_REQ_LEN(RX_REQ_LEN),\n\t.REQ_ACK(wReqAck)\n);\n\n\n// Read the scatter gather buffer address and length, continuously so that\n// we have it ready whenever the next buffer is needed.\nsg_list_reader_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (\n\t.CLK(CLK),\n\t.RST(rRst | wSgRst),\n\t.BUF_DATA(wSgRxData),\n\t.BUF_DATA_EMPTY(wSgRxDataEmpty),\n\t.BUF_DATA_REN(wSgRxDataRen),\n\t.VALID(wSgElemRdy),\n\t.EMPTY(),\n\t.REN(wSgElemRen),\n\t.ADDR(wSgElemAddr),\n\t.LEN(wSgElemLen)\n);\n\n\n// Main port reader logic\nrx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (\n\t.CLK(CLK), \n\t.RST(rRst), \n\t.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),\n\t.TXN_DATA(TXN_DATA), \n\t.TXN_LEN_VALID(TXN_LEN_VALID), \n\t.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID), \n\t.TXN_DONE_LEN(TXN_DONE_LEN),\n\t.TXN_DONE(TXN_DONE),\n\t.TXN_ERR(wTxnErr),\n\t.TXN_DONE_ACK(TXN_DONE_ACK),\n\t.TXN_DATA_FLUSH(wMainFlush),\n\t.TXN_DATA_FLUSHED(wMainFlushed),\n\t.RX_REQ(wMainReq),\n\t.RX_ADDR(wMainReqAddr),\n\t.RX_LEN(wMainReqLen),\n\t.RX_REQ_ACK(wReqAck & wMainReqProc),\n\t.RX_DATA_EN(MAIN_DATA_EN), \n\t.RX_DONE(wPackedMainDone),\n\t.RX_ERR(wPackedMainErr),\n\t.SG_DONE(wPackedSgRxDone), \n\t.SG_ERR(wPackedSgRxErr), \n\t.SG_ELEM_ADDR(wSgElemAddr), \n\t.SG_ELEM_LEN(wSgElemLen),\n\t.SG_ELEM_RDY(wSgElemRdy),\n\t.SG_ELEM_REN(wSgElemRen),\n\t.SG_RST(wSgRst),\n\t.CHNL_RX(wChnlRx), \n\t.CHNL_RX_LEN(wChnlRxLen), \n\t.CHNL_RX_LAST(wChnlRxLast),\n\t.CHNL_RX_OFF(wChnlRxOff), \n\t.CHNL_RX_RECVD(wChnlRxRecvd), \n\t.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd), \n\t.CHNL_RX_CONSUMED(wChnlRxConsumed)\n);\n\n\n// Manage the CHNL_RX* signals in the CHNL_CLK domain.\nrx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (\n\t.RST(rRst), \n\t.CLK(CLK), \n\t.RX(wChnlRx), \n\t.RX_RECVD(wChnlRxRecvd), \n\t.RX_ACK_RECVD(wChnlRxAckRecvd), \n\t.RX_LAST(wChnlRxLast), \n\t.RX_LEN(wChnlRxLen), \n\t.RX_OFF(wChnlRxOff), \n\t.RX_CONSUMED(wChnlRxConsumed), \n\t.RD_DATA(wMainData), \n\t.RD_EMPTY(wMainDataEmpty), \n\t.RD_EN(wMainDataRen), \n\t.CHNL_CLK(CHNL_CLK), \n\t.CHNL_RX(CHNL_RX), \n\t.CHNL_RX_ACK(CHNL_RX_ACK), \n\t.CHNL_RX_LAST(CHNL_RX_LAST), \n\t.CHNL_RX_LEN(CHNL_RX_LEN), \n\t.CHNL_RX_OFF(CHNL_RX_OFF), \n\t.CHNL_RX_DATA(CHNL_RX_DATA), \n\t.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), \n\t.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)\n);\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/rx_port_64.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\trx_port_64.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tReceives data from the rx_engine and buffers the output \n//\t\t\t\t\t\tfor the RIFFA channel.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule rx_port_64 #(\n\tparameter C_DATA_WIDTH = 9'd64,\n\tparameter C_MAIN_FIFO_DEPTH = 1024,\n\tparameter C_SG_FIFO_DEPTH = 512,\n\tparameter C_MAX_READ_REQ = 2,\t\t\t\t\t// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t// Local parameters\n\tparameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),\n\tparameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),\n\tparameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [2:0] CONFIG_MAX_READ_REQUEST_SIZE,\t\t\t\t// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\n\toutput SG_RX_BUF_RECVD,\t\t\t\t\t\t\t// Scatter gather RX buffer completely read (ready for next if applicable)\n\tinput [31:0] SG_RX_BUF_DATA,\t\t\t\t\t// Scatter gather RX buffer data\n\tinput SG_RX_BUF_LEN_VALID,\t\t\t\t\t\t// Scatter gather RX buffer length valid\n\tinput SG_RX_BUF_ADDR_HI_VALID,\t\t\t\t\t// Scatter gather RX buffer high address valid\n\tinput SG_RX_BUF_ADDR_LO_VALID,\t\t\t\t\t// Scatter gather RX buffer low address valid\n\n\toutput SG_TX_BUF_RECVD,\t\t\t\t\t\t\t// Scatter gather TX buffer completely read (ready for next if applicable)\n\tinput [31:0] SG_TX_BUF_DATA,\t\t\t\t\t// Scatter gather TX buffer data\n\tinput SG_TX_BUF_LEN_VALID,\t\t\t\t\t\t// Scatter gather TX buffer length valid\n\tinput SG_TX_BUF_ADDR_HI_VALID,\t\t\t\t\t// Scatter gather TX buffer high address valid\n\tinput SG_TX_BUF_ADDR_LO_VALID,\t\t\t\t\t// Scatter gather TX buffer low address valid\n\n\toutput [C_DATA_WIDTH-1:0] SG_DATA,\t\t\t\t// Scatter gather TX buffer data\n\toutput SG_DATA_EMPTY,\t\t\t\t\t\t\t// Scatter gather TX buffer data empty\n\tinput SG_DATA_REN,\t\t\t\t\t\t\t\t// Scatter gather TX buffer data read enable\n\tinput SG_RST,\t\t\t\t\t\t\t\t\t// Scatter gather TX buffer data reset\n\toutput SG_ERR,\t\t\t\t\t\t\t\t\t// Scatter gather TX encountered an error\n\t\n\tinput [31:0] TXN_DATA,\t\t\t\t\t\t\t// Read transaction data\n\tinput TXN_LEN_VALID,\t\t\t\t\t\t\t// Read transaction length valid\n\tinput TXN_OFF_LAST_VALID,\t\t\t\t\t\t// Read transaction offset/last valid\n\toutput [31:0] TXN_DONE_LEN,\t\t\t\t\t\t// Read transaction actual transfer length\n\toutput TXN_DONE,\t\t\t\t\t\t\t\t// Read transaction done\n\tinput TXN_DONE_ACK,\t\t\t\t\t\t\t\t// Read transaction actual transfer length read\n\n\toutput RX_REQ,\t\t\t\t\t\t\t\t\t// Read request\n\tinput RX_REQ_ACK,\t\t\t\t\t\t\t\t// Read request accepted\n\toutput [1:0] RX_REQ_TAG,\t\t\t\t\t\t// Read request data tag \n\toutput [63:0] RX_REQ_ADDR,\t\t\t\t\t\t// Read request address\n\toutput [9:0] RX_REQ_LEN,\t\t\t\t\t\t// Read request length\n\n\tinput [C_DATA_WIDTH-1:0] MAIN_DATA,\t\t\t\t// Main incoming data \n\tinput [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,\t\t// Main incoming data enable\n\tinput MAIN_DONE,\t\t\t\t\t\t\t\t// Main incoming data complete\n\tinput MAIN_ERR,\t\t\t\t\t\t\t\t\t// Main incoming data completed with error\n\tinput [C_DATA_WIDTH-1:0] SG_RX_DATA,\t\t\t// Scatter gather for RX incoming data \n\tinput [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,\t// Scatter gather for RX incoming data enable\n\tinput SG_RX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for RX incoming data complete\n\tinput SG_RX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for RX incoming data completed with error\n\tinput [C_DATA_WIDTH-1:0] SG_TX_DATA,\t\t\t// Scatter gather for TX incoming data \n\tinput [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,\t// Scatter gather for TX incoming data enable\n\tinput SG_TX_DONE,\t\t\t\t\t\t\t\t// Scatter gather for TX incoming data complete\n\tinput SG_TX_ERR,\t\t\t\t\t\t\t\t// Scatter gather for TX incoming data completed with error\n\n\tinput CHNL_CLK,\t\t\t\t\t\t\t\t\t// Channel read clock\n\toutput CHNL_RX,\t\t\t\t\t\t\t\t\t// Channel read receive signal\n\tinput CHNL_RX_ACK,\t\t\t\t\t\t\t\t// Channle read received signal\n\toutput CHNL_RX_LAST,\t\t\t\t\t\t\t// Channel last read\n\toutput [31:0] CHNL_RX_LEN,\t\t\t\t\t\t// Channel read length\n\toutput [30:0] CHNL_RX_OFF,\t\t\t\t\t\t// Channel read offset\n\toutput [C_DATA_WIDTH-1:0] CHNL_RX_DATA,\t\t\t// Channel read data\n\toutput CHNL_RX_DATA_VALID,\t\t\t\t\t\t// Channel read data valid\n\tinput CHNL_RX_DATA_REN\t\t\t\t\t\t\t// Channel read data has been recieved\n);\n\n`include \"common_functions.v\"\n\n\nassign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);\n\n\nwire\t[C_DATA_WIDTH-1:0]\t\t\twPackedMainData;\nwire\t\t\t\t\t\t\t\twPackedMainWen;\nwire\t\t\t\t\t\t\t\twPackedMainDone;\nwire\t\t\t\t\t\t\t\twPackedMainErr;\nwire\t\t\t\t\t\t\t\twMainFlush;\nwire\t\t\t\t\t\t\t\twMainFlushed;\n\nwire\t[C_DATA_WIDTH-1:0]\t\t\twPackedSgRxData;\nwire\t\t\t\t\t\t\t\twPackedSgRxWen;\nwire\t\t\t\t\t\t\t\twPackedSgRxDone;\nwire\t\t\t\t\t\t\t\twPackedSgRxErr;\nwire\t\t\t\t\t\t\t\twSgRxFlush;\nwire\t\t\t\t\t\t\t\twSgRxFlushed;\n\nwire\t[C_DATA_WIDTH-1:0]\t\t\twPackedSgTxData;\nwire\t\t\t\t\t\t\t\twPackedSgTxWen;\nwire\t\t\t\t\t\t\t\twPackedSgTxDone;\nwire\t\t\t\t\t\t\t\twPackedSgTxErr;\nwire\t\t\t\t\t\t\t\twSgTxFlush;\nwire\t\t\t\t\t\t\t\twSgTxFlushed;\n\nwire\t\t\t\t\t\t\t\twMainDataRen;\nwire\t\t\t\t\t\t\t\twMainDataEmpty;\nwire\t[C_DATA_WIDTH-1:0]\t\t\twMainData;\n\nwire\t\t\t\t\t\t\t\twSgRxRst;\nwire\t\t\t\t\t\t\t\twSgRxDataRen;\nwire\t\t\t\t\t\t\t\twSgRxDataEmpty;\nwire\t[C_DATA_WIDTH-1:0]\t\t\twSgRxData;\nwire\t[C_SG_FIFO_DEPTH_WIDTH-1:0]\twSgRxFifoCount;\n\nwire\t\t\t\t\t\t\t\twSgTxRst;\nwire\t[C_SG_FIFO_DEPTH_WIDTH-1:0]\twSgTxFifoCount;\n\nwire\t\t\t\t\t\t\t\twSgRxReq;\nwire\t[63:0]\t\t\t\t\t\twSgRxReqAddr;\nwire\t[9:0]\t\t\t\t\t\twSgRxReqLen;\n\nwire\t\t\t\t\t\t\t\twSgTxReq;\nwire\t[63:0]\t\t\t\t\t\twSgTxReqAddr;\nwire\t[9:0]\t\t\t\t\t\twSgTxReqLen;\n\nwire\t\t\t\t\t\t\t\twSgRxReqProc;\nwire\t\t\t\t\t\t\t\twSgTxReqProc;\nwire\t\t\t\t\t\t\t\twMainReqProc;\nwire\t\t\t\t\t\t\t\twReqAck;\n\nwire\t\t\t\t\t\t\t\twSgElemRdy;\nwire\t\t\t\t\t\t\t\twSgElemRen;\nwire\t[63:0]\t\t\t\t\t\twSgElemAddr;\nwire\t[31:0]\t\t\t\t\t\twSgElemLen;\n\nwire\t\t\t\t\t\t\t\twSgRst;\nwire\t\t\t\t\t\t\t\twMainReq;\nwire\t[63:0]\t\t\t\t\t\twMainReqAddr;\nwire\t[9:0]\t\t\t\t\t\twMainReqLen;\nwire\t\t\t\t\t\t\t\twTxnErr;\nwire\t\t\t\t\t\t\t\twChnlRx;\nwire\t\t\t\t\t\t\t\twChnlRxRecvd;\nwire\t\t\t\t\t\t\t\twChnlRxAckRecvd;\nwire\t\t\t\t\t\t\t\twChnlRxLast;\nwire\t[31:0]\t\t\t\t\t\twChnlRxLen;\nwire\t[30:0]\t\t\t\t\t\twChnlRxOff;\nwire\t[31:0]\t\t\t\t\t\twChnlRxConsumed;\n\nreg\t\t[4:0]\t\t\t\t\t\trWideRst=0;\nreg\t\t\t\t\t\t\t\t\trRst=0;\n\n\n// Generate a wide reset from the input reset.\nalways @ (posedge CLK) begin\n\trRst <= #1 rWideRst[4]; \n\tif (RST) \n\t\trWideRst <= #1 5'b11111;\n\telse \n\t\trWideRst <= (rWideRst<<1);\nend\n\n\n// Pack received data tightly into our FIFOs \nfifo_packer_64 mainFifoPacker (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.DATA_IN(MAIN_DATA),\n\t.DATA_IN_EN(MAIN_DATA_EN),\n\t.DATA_IN_DONE(MAIN_DONE),\n\t.DATA_IN_ERR(MAIN_ERR),\n\t.DATA_IN_FLUSH(wMainFlush),\n\t.PACKED_DATA(wPackedMainData),\n\t.PACKED_WEN(wPackedMainWen),\n\t.PACKED_DATA_DONE(wPackedMainDone),\n\t.PACKED_DATA_ERR(wPackedMainErr),\n\t.PACKED_DATA_FLUSHED(wMainFlushed)\n);\n\nfifo_packer_64 sgRxFifoPacker (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.DATA_IN(SG_RX_DATA),\n\t.DATA_IN_EN(SG_RX_DATA_EN),\n\t.DATA_IN_DONE(SG_RX_DONE),\n\t.DATA_IN_ERR(SG_RX_ERR),\n\t.DATA_IN_FLUSH(wSgRxFlush),\n\t.PACKED_DATA(wPackedSgRxData),\n\t.PACKED_WEN(wPackedSgRxWen),\n\t.PACKED_DATA_DONE(wPackedSgRxDone),\n\t.PACKED_DATA_ERR(wPackedSgRxErr),\n\t.PACKED_DATA_FLUSHED(wSgRxFlushed)\n);\n\nfifo_packer_64 sgTxFifoPacker (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.DATA_IN(SG_TX_DATA),\n\t.DATA_IN_EN(SG_TX_DATA_EN),\n\t.DATA_IN_DONE(SG_TX_DONE),\n\t.DATA_IN_ERR(SG_TX_ERR),\n\t.DATA_IN_FLUSH(wSgTxFlush),\n\t.PACKED_DATA(wPackedSgTxData),\n\t.PACKED_WEN(wPackedSgTxWen),\n\t.PACKED_DATA_DONE(wPackedSgTxDone),\n\t.PACKED_DATA_ERR(wPackedSgTxErr),\n\t.PACKED_DATA_FLUSHED(wSgTxFlushed)\n);\n\n\n// FIFOs for storing received data for the channel.\n(* RAM_STYLE=\"BLOCK\" *)\nasync_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (\n\t.WR_CLK(CLK),\n\t.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),\n\t.WR_EN(wPackedMainWen),\n\t.WR_DATA(wPackedMainData),\n\t.WR_FULL(),\n\t.RD_CLK(CHNL_CLK),\n\t.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),\n\t.RD_EN(wMainDataRen),\n\t.RD_DATA(wMainData),\n\t.RD_EMPTY(wMainDataEmpty)\n);\n\n(* RAM_STYLE=\"BLOCK\" *)\nsync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (\n\t.RST(rRst | wSgRxRst),\n\t.CLK(CLK),\n\t.WR_EN(wPackedSgRxWen),\n\t.WR_DATA(wPackedSgRxData),\n\t.FULL(),\n\t.RD_EN(wSgRxDataRen),\n\t.RD_DATA(wSgRxData),\n\t.EMPTY(wSgRxDataEmpty),\n\t.COUNT(wSgRxFifoCount)\n);\n\n(* RAM_STYLE=\"BLOCK\" *)\nsync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (\n\t.RST(rRst | wSgTxRst),\n\t.CLK(CLK),\n\t.WR_EN(wPackedSgTxWen),\n\t.WR_DATA(wPackedSgTxData),\n\t.FULL(),\n\t.RD_EN(SG_DATA_REN),\n\t.RD_DATA(SG_DATA),\n\t.EMPTY(SG_DATA_EMPTY),\n\t.COUNT(wSgTxFifoCount)\n);\n\n\n// Manage requesting and acknowledging scatter gather data. Note that\n// these modules will share the main requestor's RX channel. They will\n// take priority over the main logic's use of the RX channel.\nsg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),\n\t.USER_RST(wSgRst),\n\t.BUF_RECVD(SG_RX_BUF_RECVD),\n\t.BUF_DATA(SG_RX_BUF_DATA),\n\t.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),\n\t.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),\n\t.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),\n\t.FIFO_COUNT(wSgRxFifoCount),\n\t.FIFO_FLUSH(wSgRxFlush),\n\t.FIFO_FLUSHED(wSgRxFlushed),\n\t.FIFO_RST(wSgRxRst),\n\t.RX_REQ(wSgRxReq),\n\t.RX_ADDR(wSgRxReqAddr),\n\t.RX_LEN(wSgRxReqLen),\n\t.RX_REQ_ACK(wReqAck & wSgRxReqProc),\n\t.RX_DONE(wPackedSgRxDone)\n);\n\nsg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (\n\t.CLK(CLK),\n\t.RST(rRst),\n\t.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),\n\t.USER_RST(SG_RST),\n\t.BUF_RECVD(SG_TX_BUF_RECVD),\n\t.BUF_DATA(SG_TX_BUF_DATA),\n\t.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),\n\t.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),\n\t.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),\n\t.FIFO_COUNT(wSgTxFifoCount),\n\t.FIFO_FLUSH(wSgTxFlush),\n\t.FIFO_FLUSHED(wSgTxFlushed),\n\t.FIFO_RST(wSgTxRst),\n\t.RX_REQ(wSgTxReq),\n\t.RX_ADDR(wSgTxReqAddr),\n\t.RX_LEN(wSgTxReqLen),\n\t.RX_REQ_ACK(wReqAck & wSgTxReqProc),\n\t.RX_DONE(wPackedSgTxDone)\n);\n\n\n// A read requester for the channel and scatter gather requesters.\nrx_port_requester_mux requesterMux (\n\t.RST(rRst), \n\t.CLK(CLK), \n\t.SG_RX_REQ(wSgRxReq), \n\t.SG_RX_LEN(wSgRxReqLen), \n\t.SG_RX_ADDR(wSgRxReqAddr), \n\t.SG_RX_REQ_PROC(wSgRxReqProc),\n\t.SG_TX_REQ(wSgTxReq), \n\t.SG_TX_LEN(wSgTxReqLen), \n\t.SG_TX_ADDR(wSgTxReqAddr), \n\t.SG_TX_REQ_PROC(wSgTxReqProc),\n\t.MAIN_REQ(wMainReq), \n\t.MAIN_LEN(wMainReqLen), \n\t.MAIN_ADDR(wMainReqAddr), \n\t.MAIN_REQ_PROC(wMainReqProc),\n\t.RX_REQ(RX_REQ),\n\t.RX_REQ_ACK(RX_REQ_ACK),\n\t.RX_REQ_TAG(RX_REQ_TAG),\n\t.RX_REQ_ADDR(RX_REQ_ADDR),\n\t.RX_REQ_LEN(RX_REQ_LEN),\n\t.REQ_ACK(wReqAck)\n);\n\n\n// Read the scatter gather buffer address and length, continuously so that\n// we have it ready whenever the next buffer is needed.\nsg_list_reader_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (\n\t.CLK(CLK),\n\t.RST(rRst | wSgRst),\n\t.BUF_DATA(wSgRxData),\n\t.BUF_DATA_EMPTY(wSgRxDataEmpty),\n\t.BUF_DATA_REN(wSgRxDataRen),\n\t.VALID(wSgElemRdy),\n\t.EMPTY(),\n\t.REN(wSgElemRen),\n\t.ADDR(wSgElemAddr),\n\t.LEN(wSgElemLen)\n);\n\n\n// Main port reader logic\nrx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (\n\t.CLK(CLK), \n\t.RST(rRst), \n\t.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),\n\t.TXN_DATA(TXN_DATA), \n\t.TXN_LEN_VALID(TXN_LEN_VALID), \n\t.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID), \n\t.TXN_DONE_LEN(TXN_DONE_LEN),\n\t.TXN_DONE(TXN_DONE),\n\t.TXN_ERR(wTxnErr),\n\t.TXN_DONE_ACK(TXN_DONE_ACK),\n\t.TXN_DATA_FLUSH(wMainFlush),\n\t.TXN_DATA_FLUSHED(wMainFlushed),\n\t.RX_REQ(wMainReq),\n\t.RX_ADDR(wMainReqAddr),\n\t.RX_LEN(wMainReqLen),\n\t.RX_REQ_ACK(wReqAck & wMainReqProc),\n\t.RX_DATA_EN(MAIN_DATA_EN), \n\t.RX_DONE(wPackedMainDone),\n\t.RX_ERR(wPackedMainErr),\n\t.SG_DONE(wPackedSgRxDone), \n\t.SG_ERR(wPackedSgRxErr), \n\t.SG_ELEM_ADDR(wSgElemAddr), \n\t.SG_ELEM_LEN(wSgElemLen),\n\t.SG_ELEM_RDY(wSgElemRdy),\n\t.SG_ELEM_REN(wSgElemRen),\n\t.SG_RST(wSgRst),\n\t.CHNL_RX(wChnlRx), \n\t.CHNL_RX_LEN(wChnlRxLen), \n\t.CHNL_RX_LAST(wChnlRxLast),\n\t.CHNL_RX_OFF(wChnlRxOff), \n\t.CHNL_RX_RECVD(wChnlRxRecvd), \n\t.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd), \n\t.CHNL_RX_CONSUMED(wChnlRxConsumed)\n);\n\n\n// Manage the CHNL_RX* signals in the CHNL_CLK domain.\nrx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (\n\t.RST(rRst), \n\t.CLK(CLK), \n\t.RX(wChnlRx), \n\t.RX_RECVD(wChnlRxRecvd), \n\t.RX_ACK_RECVD(wChnlRxAckRecvd), \n\t.RX_LAST(wChnlRxLast), \n\t.RX_LEN(wChnlRxLen), \n\t.RX_OFF(wChnlRxOff), \n\t.RX_CONSUMED(wChnlRxConsumed), \n\t.RD_DATA(wMainData), \n\t.RD_EMPTY(wMainDataEmpty), \n\t.RD_EN(wMainDataRen), \n\t.CHNL_CLK(CHNL_CLK), \n\t.CHNL_RX(CHNL_RX), \n\t.CHNL_RX_ACK(CHNL_RX_ACK), \n\t.CHNL_RX_LAST(CHNL_RX_LAST), \n\t.CHNL_RX_LEN(CHNL_RX_LEN), \n\t.CHNL_RX_OFF(CHNL_RX_OFF), \n\t.CHNL_RX_DATA(CHNL_RX_DATA), \n\t.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), \n\t.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)\n);\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/rx_port_channel_gate.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\trx_port_channel_gate.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tProvides cross domain synchronization for the CHNL_RX* \n// signals between the CHNL_CLK and CLK domains. \n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n\nmodule rx_port_channel_gate #(\n\tparameter C_DATA_WIDTH = 9'd64\n)\n(\n\tinput RST,\n\tinput CLK,\n\n\tinput RX,\t\t\t\t\t\t\t\t// Channel read signal (CLK)\n\toutput RX_RECVD,\t\t\t\t\t\t// Channel read received signal (CLK)\n\toutput RX_ACK_RECVD,\t\t\t\t\t// Channel read acknowledgment received signal (CLK)\n\tinput RX_LAST,\t\t\t\t\t\t\t// Channel last read (CLK)\n\tinput [31:0] RX_LEN,\t\t\t\t\t// Channel read length (CLK)\n\tinput [30:0] RX_OFF,\t\t\t\t\t// Channel read offset (CLK)\n\toutput [31:0] RX_CONSUMED,\t\t\t\t// Channel words consumed (CLK)\n\t\n\tinput [C_DATA_WIDTH-1:0] RD_DATA,\t\t// FIFO read data (CHNL_CLK)\n\tinput RD_EMPTY,\t\t\t\t\t\t\t// FIFO is empty (CHNL_CLK)\n\toutput RD_EN,\t\t\t\t\t\t\t// FIFO read enable (CHNL_CLK)\n\n\tinput CHNL_CLK,\t\t\t\t\t\t\t// Channel read clock\n\toutput CHNL_RX,\t\t\t\t\t\t\t// Channel read receive signal (CHNL_CLK)\n\tinput CHNL_RX_ACK,\t\t\t\t\t\t// Channle read received signal (CHNL_CLK)\n\toutput CHNL_RX_LAST,\t\t\t\t\t// Channel last read (CHNL_CLK)\n\toutput [31:0] CHNL_RX_LEN,\t\t\t\t// Channel read length (CHNL_CLK)\n\toutput [30:0] CHNL_RX_OFF,\t\t\t\t// Channel read offset (CHNL_CLK)\n\toutput [C_DATA_WIDTH-1:0] CHNL_RX_DATA,\t// Channel read data (CHNL_CLK)\n\toutput CHNL_RX_DATA_VALID,\t\t\t\t// Channel read data valid (CHNL_CLK)\n\tinput CHNL_RX_DATA_REN\t\t\t\t\t// Channel read data has been recieved (CHNL_CLK)\n);\n\nreg\t\t\t\t\t\t\t\trAckd=0, _rAckd=0;\nreg\t\t\t\t\t\t\t\trChnlRxAck=0, _rChnlRxAck=0;\n\nreg\t\t[31:0]\t\t\t\t\trConsumed=0, _rConsumed=0;\nreg\t\t[31:0]\t\t\t\t\trConsumedStable=0, _rConsumedStable=0;\nreg\t\t[31:0]\t\t\t\t\trConsumedSample=0, _rConsumedSample=0;\nreg\t\t\t\t\t\t\t\trCountRead=0, _rCountRead=0;\nwire\t\t\t\t\t\t\twCountRead;\nwire\t\t\t\t\t\t\twCountStable;\nwire\t\t\t\t\t\t\twDataRead = (CHNL_RX_DATA_REN & CHNL_RX_DATA_VALID);\n\n\nassign RX_CONSUMED = rConsumedSample;\n\nassign RD_EN = CHNL_RX_DATA_REN;\n\nassign CHNL_RX_LAST = RX_LAST;\nassign CHNL_RX_LEN = RX_LEN;\nassign CHNL_RX_OFF = RX_OFF;\nassign CHNL_RX_DATA = RD_DATA;\nassign CHNL_RX_DATA_VALID = !RD_EMPTY;\n\n\n// Buffer the input signals that come from outside the rx_port.\nalways @ (posedge CHNL_CLK) begin\n\trChnlRxAck <= #1 (RST ? 1'd0 : _rChnlRxAck);\nend\n\nalways @ (*) begin\n\t_rChnlRxAck = CHNL_RX_ACK;\nend\n\n\n// Signal receive into the channel domain.\ncross_domain_signal rxSig (\n\t.CLK_A(CLK), \n\t.CLK_A_SEND(RX), \n\t.CLK_A_RECV(RX_RECVD), \n\t.CLK_B(CHNL_CLK), \n\t.CLK_B_RECV(CHNL_RX), \n\t.CLK_B_SEND(CHNL_RX)\n);\n\n// Signal acknowledgment of receive into the CLK domain.\nsyncff rxAckSig (.CLK(CLK), .IN_ASYNC(rAckd), .OUT_SYNC(RX_ACK_RECVD));\n\n\n// Capture CHNL_RX_ACK and reset only after the CHNL_RX drops.\nalways @ (posedge CHNL_CLK) begin\n\trAckd <= #1 (RST ? 1'd0 : _rAckd);\nend\n\nalways @ (*) begin\n\t_rAckd = (CHNL_RX & (rAckd | rChnlRxAck));\nend\n\n\n// Count the words consumed by the channel and pass it into the CLK domain.\nalways @ (posedge CHNL_CLK) begin\n\trConsumed <= #1 _rConsumed;\n\trConsumedStable <= #1 _rConsumedStable;\n\trCountRead <= #1 (RST ? 1'd0 : _rCountRead);\nend\n\nalways @ (*) begin\n\t_rConsumed = (!CHNL_RX ? 0 : rConsumed + (wDataRead*(C_DATA_WIDTH/32)));\n\t_rConsumedStable = (wCountRead | rCountRead ? rConsumedStable : rConsumed);\n\t_rCountRead = !wCountRead;\nend\n\nalways @ (posedge CLK) begin\n\trConsumedSample <= #1 _rConsumedSample;\nend\n\nalways @ (*) begin\n\t_rConsumedSample = (wCountStable ? rConsumedStable : rConsumedSample);\nend\n\n// Determine when it's safe to update the count in the CLK domain.\ncross_domain_signal countSync (\n\t.CLK_A(CHNL_CLK), \n\t.CLK_A_SEND(rCountRead), \n\t.CLK_A_RECV(wCountRead), \n\t.CLK_B(CLK), \n\t.CLK_B_RECV(wCountStable), \n\t.CLK_B_SEND(wCountStable)\n);\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/rx_port_reader.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\trx_port_reader.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tHandles the RX lifecycle and issuing requests for receiving\n// data input. \n//\t\t\t\t\t\tfor the RIFFA channel.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_RXPORTRD_MAIN_IDLE\t\t6'b00_0001\n`define S_RXPORTRD_MAIN_CHECK\t\t6'b00_0010\n`define S_RXPORTRD_MAIN_READ\t\t6'b00_0100\n`define S_RXPORTRD_MAIN_FLUSH\t\t6'b00_1000\n`define S_RXPORTRD_MAIN_DONE\t\t6'b01_0000\n`define S_RXPORTRD_MAIN_RESET\t\t6'b10_0000\n\n`define S_RXPORTRD_RX_IDLE\t\t8'b0000_0001\n`define S_RXPORTRD_RX_BUF\t\t8'b0000_0010\n`define S_RXPORTRD_RX_ADJ_0\t\t8'b0000_0100\n`define S_RXPORTRD_RX_ADJ_1\t\t8'b0000_1000\n`define S_RXPORTRD_RX_ISSUE\t\t8'b0001_0000\n`define S_RXPORTRD_RX_WAIT_0\t8'b0010_0000\n`define S_RXPORTRD_RX_WAIT_1\t8'b0100_0000\n`define S_RXPORTRD_RX_DONE\t\t8'b1000_0000\n\nmodule rx_port_reader #(\n\tparameter C_DATA_WIDTH = 9'd64,\n\tparameter C_FIFO_DEPTH = 1024,\n\tparameter C_MAX_READ_REQ = 2,\t\t\t\t// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t// Local parameters\n\tparameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),\n\tparameter C_FIFO_WORDS = (C_DATA_WIDTH/32)*C_FIFO_DEPTH\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [2:0] CONFIG_MAX_READ_REQUEST_SIZE,\t\t\t// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t\n\tinput [31:0] TXN_DATA,\t\t\t\t\t\t// Read transaction data\n\tinput TXN_LEN_VALID,\t\t\t\t\t\t// Read transaction length valid\n\tinput TXN_OFF_LAST_VALID,\t\t\t\t\t// Read transaction offset/last valid\n\toutput [31:0] TXN_DONE_LEN,\t\t\t\t\t// Read transaction actual transfer length\n\toutput TXN_DONE,\t\t\t\t\t\t\t// Read transaction done\n\toutput TXN_ERR,\t\t\t\t\t\t\t\t// Read transaction completed with error\n\tinput TXN_DONE_ACK,\t\t\t\t\t\t\t// Read transaction actual transfer length read\n\n\toutput TXN_DATA_FLUSH,\t\t\t\t\t\t// Request that all data in the packer be flushed\n\tinput TXN_DATA_FLUSHED,\t\t\t\t\t\t// All data in the packer has been flushed\n\n\toutput RX_REQ,\t\t\t\t\t\t\t\t// Issue a read request\n\toutput [63:0] RX_ADDR,\t\t\t\t\t\t// Request address\n\toutput [9:0] RX_LEN,\t\t\t\t\t\t// Request length\n\tinput RX_REQ_ACK,\t\t\t\t\t\t\t// Request has been accepted\n\n\tinput [C_DATA_WORD_WIDTH-1:0] RX_DATA_EN,\t// Incoming read data enable\n\tinput RX_DONE,\t\t\t\t\t\t\t\t// Incoming read completed\n\tinput RX_ERR,\t\t\t\t\t\t\t\t// Incoming read completed with error\n\tinput SG_DONE,\t\t\t\t\t\t\t\t// Incoming scatter gather read completed\n\tinput SG_ERR,\t\t\t\t\t\t\t\t// Incoming scatter gather read completed with error\n\n\tinput [63:0] SG_ELEM_ADDR,\t\t\t\t\t// Scatter gather element address\n\tinput [31:0] SG_ELEM_LEN,\t\t\t\t\t// Scatter gather element length (in words)\n\tinput SG_ELEM_RDY,\t\t\t\t\t\t\t// Scatter gather element ready\n\toutput SG_ELEM_REN,\t\t\t\t\t\t\t// Scatter gather element read enable\n\toutput SG_RST,\t\t\t\t\t\t\t\t// Scatter gather reset\n\n\toutput CHNL_RX,\t\t\t\t\t\t\t\t// Signal channel RX\n\toutput [31:0] CHNL_RX_LEN,\t\t\t\t\t// Channel RX length\n\toutput CHNL_RX_LAST,\t\t\t\t\t\t// Channel RX last\n\toutput [30:0] CHNL_RX_OFF,\t\t\t\t\t// Channel RX offset\n\tinput CHNL_RX_RECVD,\t\t\t\t\t\t// Channel RX received\n\tinput CHNL_RX_ACK_RECVD,\t\t\t\t\t// Channel RX acknowledgment received\n\tinput [31:0] CHNL_RX_CONSUMED\t\t\t\t// Channel words consumed in current RX\n);\n\n`include \"common_functions.v\"\n\n\nreg\t\t[31:0]\t\t\t\t\t\trTxnData=0, _rTxnData=0;\nreg\t\t\t\t\t\t\t\t\trTxnOffLastValid=0, _rTxnOffLastValid=0;\nreg\t\t\t\t\t\t\t\t\trTxnLenValid=0, _rTxnLenValid=0;\nreg\t\t[C_DATA_WORD_WIDTH-1:0]\t\trRxDataEn=0, _rRxDataEn=0;\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[5:0]\t\t\t\t\t\trMainState=`S_RXPORTRD_MAIN_IDLE, _rMainState=`S_RXPORTRD_MAIN_IDLE;\nreg\t\t[31:0]\t\t\t\t\t\trOffLast=0, _rOffLast=0;\nreg\t\t[31:0]\t\t\t\t\t\trReadWords=0, _rReadWords=0;\nreg\t\t\t\t\t\t\t\t\trReadWordsZero=0, _rReadWordsZero=0;\nreg\t\t[0:0]\t\t\t\t\t\trStart=0, _rStart=0;\nreg\t\t[3:0]\t\t\t\t\t\trFlushed=0, _rFlushed=0;\nreg\t\t[31:0]\t\t\t\t\t\trDoneLen=0, _rDoneLen=0;\nreg\t\t\t\t\t\t\t\t\trTxnDone=0, _rTxnDone=0;\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[7:0]\t\t\t\t\t\trRxState=`S_RXPORTRD_RX_IDLE, _rRxState=`S_RXPORTRD_RX_IDLE;\nreg\t\t\t\t\t\t\t\t\trSgRen=0, _rSgRen=0;\nreg\t\t[31:0]\t\t\t\t\t\trWords=0, _rWords=0;\nreg\t\t[31:0]\t\t\t\t\t\trBufWords=0, _rBufWords=0;\nreg\t\t[31:0]\t\t\t\t\t\trBufWordsInit=0, _rBufWordsInit=0;\nreg\t\t\t\t\t\t\t\t\trLargeBuf=0, _rLargeBuf=0;\nreg\t\t[63:0]\t\t\t\t\t\trAddr=64'd0, _rAddr=64'd0;\nreg\t\t[3:0]\t\t\t\t\t\trValsProp=0, _rValsProp=0;\nreg\t\t[2:0]\t\t\t\t\t\trCarry=0, _rCarry=0;\nreg\t\t\t\t\t\t\t\t\trCopyBufWords=0, _rCopyBufWords=0;\nreg\t\t\t\t\t\t\t\t\trUseInit=0, _rUseInit=0;\nreg\t\t[10:0]\t\t\t\t\t\trPageRem=0, _rPageRem=0;\nreg\t\t\t\t\t\t\t\t\trPageSpill=0, _rPageSpill=0;\nreg\t\t\t\t\t\t\t\t\trPageSpillInit=0, _rPageSpillInit=0;\nreg\t\t[10:0]\t\t\t\t\t\trPreLen=0, _rPreLen=0;\nreg\t\t[2:0]\t\t\t\t\t\trMaxPayloadTrain=0, _rMaxPayloadTrain=0;\nreg\t\t[2:0]\t\t\t\t\t\trMaxPayloadShift=0, _rMaxPayloadShift=0;\nreg\t\t[9:0]\t\t\t\t\t\trMaxPayload=0, _rMaxPayload=0;\nreg\t\t\t\t\t\t\t\t\trPayloadSpill=0, _rPayloadSpill=0;\nreg\t\t\t\t\t\t\t\t\trMaxLen=0, _rMaxLen=0;\nreg\t\t[9:0]\t\t\t\t\t\trLen=0, _rLen=0;\nreg\t\t\t\t\t\t\t\t\trLenEQWordsHi=0, _rLenEQWordsHi=0;\nreg\t\t\t\t\t\t\t\t\trLenEQWordsLo=0, _rLenEQWordsLo=0;\nreg\t\t\t\t\t\t\t\t\trLenEQBufWordsHi=0, _rLenEQBufWordsHi=0;\nreg\t\t\t\t\t\t\t\t\trLenEQBufWordsLo=0, _rLenEQBufWordsLo=0;\n\nreg\t\t[31:0]\t\t\t\t\t\trRecvdWords=0, _rRecvdWords=0;\nreg\t\t[31:0]\t\t\t\t\t\trReqdWords=0, _rReqdWords=0;\nreg\t\t[31:0]\t\t\t\t\t\trRequestingWords=0, _rRequestingWords=0;\nreg\t\t[31:0]\t\t\t\t\t\trAvailWords=0, _rAvailWords=0;\nreg\t\t[31:0]\t\t\t\t\t\trPartWords=0, _rPartWords=0;\nreg\t\t[10:0]\t\t\t\t\t\trAckCount=0, _rAckCount=0;\nreg\t\t\t\t\t\t\t\t\trAckCountEQ0=0, _rAckCountEQ0=0;\nreg\t\t\t\t\t\t\t\t\trLastDoneRead=1, _rLastDoneRead=1;\nreg\t\t\t\t\t\t\t\t\trTxnDoneAck=0, _rTxnDoneAck=0;\nreg\t\t\t\t\t\t\t\t\trPartWordsRecvd=0, _rPartWordsRecvd=0;\nreg\t\t\t\t\t\t\t\t\trCarryInv=0, _rCarryInv=0;\nreg\t\t\t\t\t\t\t\t\trSpaceAvail=0, _rSpaceAvail=0;\n\nreg\t\t\t\t\t\t\t\t\trPartialDone=0, _rPartialDone=0;\nreg\t\t\t\t\t\t\t\t\trReqPartialDone=0, _rReqPartialDone=0;\n\nreg\t\t\t\t\t\t\t\t\trErr=0, _rErr=0;\n\n\nassign TXN_DONE_LEN = rDoneLen;\nassign TXN_DONE = (rTxnDone | rPartialDone);\nassign TXN_ERR = rErr;\n\nassign TXN_DATA_FLUSH = rMainState[3]; // S_RXPORTRD_MAIN_FLUSH\n\nassign RX_REQ = (rRxState[4] & rSpaceAvail); // S_RXPORTRD_RX_ISSUE\nassign RX_ADDR = rAddr;\nassign RX_LEN = rLen;\n\nassign SG_ELEM_REN = rSgRen;\nassign SG_RST = rMainState[1]; // S_RXPORTRD_MAIN_CHECK\n\nassign CHNL_RX = (rMainState[2] | rMainState[3] | rMainState[4]); // S_RXPORTRD_MAIN_READ | S_RXPORTRD_MAIN_FLUSH | S_RXPORTRD_MAIN_DONE\nassign CHNL_RX_LEN = rReadWords;\nassign CHNL_RX_LAST = rOffLast[0];\nassign CHNL_RX_OFF = rOffLast[31:1];\n\n\n// Buffer signals that come from outside the rx_port.\nalways @ (posedge CLK) begin\n\trTxnData <= #1 _rTxnData;\n\trTxnOffLastValid <= #1 _rTxnOffLastValid;\n\trTxnLenValid <= #1 _rTxnLenValid;\n\trTxnDoneAck <= #1 (RST ? 1'd0 : _rTxnDoneAck);\t\n\trRxDataEn <= #1 _rRxDataEn;\nend\n\nalways @ (*) begin\n\t_rTxnData = TXN_DATA;\n\t_rTxnOffLastValid = TXN_OFF_LAST_VALID;\n\t_rTxnLenValid = TXN_LEN_VALID;\n\t_rTxnDoneAck = TXN_DONE_ACK;\t\n\t_rRxDataEn = RX_DATA_EN;\nend\n\n\n// Handle RX lifecycle.\nalways @ (posedge CLK) begin\n\trMainState <= #1 (RST ? `S_RXPORTRD_MAIN_IDLE : _rMainState);\n\trOffLast <= #1 _rOffLast;\n\trReadWords <= #1 _rReadWords;\n\trReadWordsZero <= #1 _rReadWordsZero;\n\trStart <= #1 _rStart;\n\trFlushed <= #1 _rFlushed;\n\trDoneLen <= #1 (RST ? 0 : _rDoneLen);\n\trTxnDone <= #1 _rTxnDone;\nend\n\nalways @ (*) begin\n\t_rMainState = rMainState;\n\t_rDoneLen = rDoneLen;\n\t_rTxnDone = rTxnDone;\n\t\n\t_rOffLast = (rTxnOffLastValid ? rTxnData : rOffLast);\n\t_rReadWords = (rMainState[0] & rTxnLenValid ? rTxnData : rReadWords);\n\t_rReadWordsZero = (rReadWords == 0);\n\t_rStart = ((rStart<<1) | rTxnLenValid);\n\t_rFlushed = ((rFlushed<<1) | TXN_DATA_FLUSHED);\n\n\tcase (rMainState)\n\n\t`S_RXPORTRD_MAIN_IDLE: begin // Wait for new read transaction offset/last & length\n\t\t_rTxnDone = 0;\n\t\tif (rStart[0])\n\t\t\t_rMainState = `S_RXPORTRD_MAIN_CHECK;\n\tend\n\n\t`S_RXPORTRD_MAIN_CHECK: begin // See if we should start a transaction\n\t\tif (!rReadWordsZero)\n\t\t\t_rMainState = `S_RXPORTRD_MAIN_READ;\n\t\telse if (rOffLast[0])\n\t\t\t_rMainState = `S_RXPORTRD_MAIN_FLUSH;\n\t\telse\n\t\t\t_rMainState = `S_RXPORTRD_MAIN_IDLE;\n\tend\n\t\n\t`S_RXPORTRD_MAIN_READ: begin // Issue read transfers, wait for data to arrive\n\t\tif (rRxState[7] & rLastDoneRead) begin // S_RXPORTRD_RX_DONE\n\t\t\t_rDoneLen = rRecvdWords;\n\t\t\t_rMainState = `S_RXPORTRD_MAIN_FLUSH;\n\t\tend\n\tend\n\n\t`S_RXPORTRD_MAIN_FLUSH: begin // Wait for data to be flushed\n\t\tif (rFlushed[3])\n\t\t\t_rMainState = `S_RXPORTRD_MAIN_DONE;\n\tend\n\n\t`S_RXPORTRD_MAIN_DONE: begin // Wait for RX to be received and ackd in the channel\n\t\tif (CHNL_RX_RECVD & CHNL_RX_ACK_RECVD)\n\t\t\t_rMainState = `S_RXPORTRD_MAIN_RESET;\n\tend\n\n\t`S_RXPORTRD_MAIN_RESET: begin // Wait until RX has dropped in the channel\n\t\tif (!CHNL_RX_RECVD) begin\n\t\t\t_rTxnDone = 1;\n\t\t\t_rMainState = `S_RXPORTRD_MAIN_IDLE;\n\t\tend\n\tend\n\n\tdefault: begin\n\t\t_rMainState = `S_RXPORTRD_MAIN_IDLE;\n\tend\n\n\tendcase\nend\n\n\n// Issue the read requests at the buffer level. Decrement the amount requested\n// after every request. Continue until all words have been requested.\nwire [9:0] wAddrLoInv = ~rAddr[11:2];\nalways @ (posedge CLK) begin\n\trRxState <= #1 (RST ? `S_RXPORTRD_RX_IDLE : _rRxState);\n\trSgRen <= #1 (RST ? 1'd0: _rSgRen);\n\trWords <= #1 _rWords;\n\trBufWords <= #1 _rBufWords;\n\trBufWordsInit <= #1 _rBufWordsInit;\n\trLargeBuf <= #1 _rLargeBuf;\n\trAddr <= #1 _rAddr;\n\trCarry <= #1 _rCarry;\n\trValsProp <= #1 _rValsProp;\n\trPageRem <= #1 _rPageRem;\n\trPageSpill <= #1 _rPageSpill;\n\trPageSpillInit <= #1 _rPageSpillInit;\n\trCopyBufWords <= #1 _rCopyBufWords;\n\trUseInit <= #1 _rUseInit;\n\trPreLen <= #1 _rPreLen;\n\trMaxPayloadTrain <= #1 _rMaxPayloadTrain;\n\trMaxPayloadShift <= #1 _rMaxPayloadShift;\n\trMaxPayload <= #1 _rMaxPayload;\n\trPayloadSpill <= #1 _rPayloadSpill;\n\trMaxLen <= #1 _rMaxLen;\n\trLen <= #1 _rLen;\n\trLenEQWordsHi <= #1 _rLenEQWordsHi;\n\trLenEQWordsLo <= #1 _rLenEQWordsLo;\n\trLenEQBufWordsHi <= #1 _rLenEQBufWordsHi;\n\trLenEQBufWordsLo <= #1 _rLenEQBufWordsLo;\nend\n\nalways @ (*) begin\n\t_rRxState = rRxState;\n\t_rCopyBufWords = rCopyBufWords;\n\t_rUseInit = rUseInit;\n\t_rSgRen = rSgRen;\n\n\t_rValsProp = ((rValsProp<<1) | rRxState[2]); // S_RXPORTRD_RX_ADJ_0\n\t_rLargeBuf = (SG_ELEM_LEN > rWords);\n \t{_rCarry[0], _rAddr[15:0]} = (rRxState[1] ? SG_ELEM_ADDR[15:0] : (rAddr[15:0] + ({12{RX_REQ_ACK}} & {rLen,2'd0}))); \n\t{_rCarry[1], _rAddr[31:16]} = (rRxState[1] ? SG_ELEM_ADDR[31:16] : (rAddr[31:16] + rCarry[0]));\n\t{_rCarry[2], _rAddr[47:32]} = (rRxState[1] ? SG_ELEM_ADDR[47:32] : (rAddr[47:32] + rCarry[1]));\n\t\t\t\t _rAddr[63:48] = (rRxState[1] ? SG_ELEM_ADDR[63:48] : (rAddr[63:48] + rCarry[2]));\n\t_rWords = (rRxState[0] ? rReadWords : (rWords - ({10{RX_REQ_ACK}} & rLen)));\n\t_rBufWordsInit = (rLargeBuf ? rWords : SG_ELEM_LEN);\n _rBufWords = (rCopyBufWords ? rBufWordsInit : rBufWords) - ({10{RX_REQ_ACK}} & rLen);\n\t_rPageRem = (wAddrLoInv + 1'd1);\t\n\t_rPageSpillInit = (rBufWordsInit > rPageRem);\t\n\t_rPageSpill = (rBufWords > rPageRem);\t\n\t_rPreLen = ((rPageSpillInit & rUseInit) | (rPageSpill & !rUseInit) ? rPageRem : rBufWords[10:0]);\n\t_rMaxPayloadTrain = (CONFIG_MAX_READ_REQUEST_SIZE > 3'd4 ? 3'd4 : CONFIG_MAX_READ_REQUEST_SIZE);\n\t_rMaxPayloadShift = (C_MAX_READ_REQ[2:0] < rMaxPayloadTrain ? C_MAX_READ_REQ[2:0] : rMaxPayloadTrain);\n\t_rMaxPayload = (6'd32< rMaxPayload);\n\t_rMaxLen = ((rMaxLen & !rValsProp[2]) | RX_REQ_ACK);\n\t_rLen = (rPayloadSpill | rMaxLen ? rMaxPayload : rPreLen[9:0]);\n\t_rLenEQWordsHi = (16'd0 == rWords[31:16]);\n\t_rLenEQWordsLo = ({6'd0, rLen} == rWords[15:0]);\n\t_rLenEQBufWordsHi = (16'd0 == rBufWords[31:16]);\n\t_rLenEQBufWordsLo = ({6'd0, rLen} == rBufWords[15:0]);\n\n\tcase (rRxState)\n\n\t`S_RXPORTRD_RX_IDLE: begin // Wait for a new read transaction\n\t\tif (rMainState[2]) // S_RXPORTRD_MAIN_READ\n\t\t\t_rRxState = `S_RXPORTRD_RX_BUF;\n\tend\n\n\t`S_RXPORTRD_RX_BUF: begin // Wait for buffer length and address\n\t\tif (SG_ELEM_RDY) begin\n\t\t\t_rSgRen = 1;\n\t\t\t_rRxState = `S_RXPORTRD_RX_ADJ_0;\n\t\tend\n\t\telse if (rErr) begin\n\t\t\t_rRxState = `S_RXPORTRD_RX_WAIT_0;\n\t\tend\n\tend\n\n\t`S_RXPORTRD_RX_ADJ_0: begin // Fix for large buffer\n\t\t_rSgRen = 0;\n\t\t_rCopyBufWords = rSgRen;\n\t\t_rRxState = `S_RXPORTRD_RX_ADJ_1;\n\tend\n\n\t// (bufwords and pagerem valid here) \n\t`S_RXPORTRD_RX_ADJ_1: begin // Wait for the value to propagate \n\t\t// Check for page boundary crossing\n\t\t// Fix for page boundary crossing\n\t\t// Check for max read payload\n\t\t// Fix for max read payload\n\t\t_rCopyBufWords = 0;\n\t\t_rUseInit = rCopyBufWords;\n\t\tif (rValsProp[3])\n\t\t\t_rRxState = `S_RXPORTRD_RX_ISSUE;\n\tend\n\n\t`S_RXPORTRD_RX_ISSUE: begin // Wait for the request to be accepted\n\t\tif (RX_REQ_ACK) begin\n\t\t\tif (rErr | (rLenEQWordsHi & rLenEQWordsLo))\n\t\t\t\t_rRxState = `S_RXPORTRD_RX_WAIT_0;\n\t\t\telse if (rLenEQBufWordsHi & rLenEQBufWordsLo)\n\t\t\t\t_rRxState = `S_RXPORTRD_RX_BUF;\n\t\t\telse\n\t\t\t\t_rRxState = `S_RXPORTRD_RX_ADJ_0;\n\t\tend\n\tend\n\n\t`S_RXPORTRD_RX_WAIT_0: begin // Wait for rAckCount to update\n\t\t_rRxState = `S_RXPORTRD_RX_WAIT_1;\n\tend\n\n\t`S_RXPORTRD_RX_WAIT_1: begin // Wait for requested data to arrive\n\t\tif (rAckCountEQ0)\n\t\t\t_rRxState = `S_RXPORTRD_RX_DONE;\n\tend\n\n\t`S_RXPORTRD_RX_DONE: begin // Signal done\n\t\tif (rMainState[3]) // S_RXPORTRD_MAIN_FLUSH\n\t\t\t_rRxState = `S_RXPORTRD_RX_IDLE;\n\tend\n\t\n\tdefault: begin\n\t\t_rRxState = `S_RXPORTRD_RX_IDLE;\n\tend\n\t\n\tendcase\nend\n\n\n// Count the data.\nalways @ (posedge CLK) begin\n\trRecvdWords <= #1 _rRecvdWords;\n\trReqdWords <= #1 _rReqdWords;\n\trPartWords <= #1 _rPartWords;\n\trAckCount <= #1 _rAckCount;\n\trAckCountEQ0 <= #1 _rAckCountEQ0;\n\trPartWordsRecvd <= #1 _rPartWordsRecvd;\n\trRequestingWords <= #1 _rRequestingWords;\n\trAvailWords <= #1 _rAvailWords;\n\trCarryInv <= #1 _rCarryInv;\n\trSpaceAvail <= #1 _rSpaceAvail;\n\trLastDoneRead <= #1 (RST ? 1'd1 : _rLastDoneRead);\t\nend\n\nalways @ (*) begin\n\t// Count words as they arrive (words from the rx_engine directly).\n\tif (rMainState[0]) // S_RXPORTRD_MAIN_IDLE\n\t\t_rRecvdWords = #1 0;\n\telse\n\t\t_rRecvdWords = #1 rRecvdWords + rRxDataEn;\n\n\t// Count words as they are requested.\n\tif (rMainState[0]) // S_RXPORTRD_MAIN_IDLE\n\t\t_rReqdWords = #1 0;\n\telse\n _rReqdWords = #1 rReqdWords + ({10{RX_REQ_ACK}} & rLen);\n\n\t// Track outstanding requests\n\tif (rMainState[0]) // S_RXPORTRD_MAIN_IDLE\n\t\t_rAckCount = 0;\n\telse\n\t\t_rAckCount = rAckCount + RX_REQ_ACK - RX_DONE;\n\t_rAckCountEQ0 = (rAckCount == 11'd0);\n\n\t// Track when the user reads the actual transfer amount.\n\t_rLastDoneRead = (rTxnDone ? 1'd0 : (rLastDoneRead | rTxnDoneAck));\n\n\t// Track the amount of words that are expected to arrive.\n\t_rPartWords = #1 (rTxnLenValid ? rTxnData : rPartWords);\n\n\t// Compare counts.\n\t_rPartWordsRecvd = (rRecvdWords >= rPartWords);\n\t_rRequestingWords = rReqdWords + rLen;\n\t{_rCarryInv, _rAvailWords[15:0]} = {1'd1, rRequestingWords[15:0]} - CHNL_RX_CONSUMED[15:0];\n\t_rAvailWords[31:16] = rRequestingWords[31:16] - CHNL_RX_CONSUMED[31:16] - !rCarryInv;\n\t_rSpaceAvail = (rAvailWords <= C_FIFO_WORDS);\nend\n\n\n// Facilitate sending a TXN_DONE when we receive a TXN_ACK after the transaction\n// has begun sending. This will happen when the workstation detects that it has \n// sent/used all its currently mapped scatter gather elements, but it's not enough \n// to complete the transaction. The TXN_DONE will let the workstation know it can\n// release the current scatter gather mappings and allocate new ones.\nalways @ (posedge CLK) begin\n\trPartialDone <= #1 _rPartialDone;\n\trReqPartialDone <= #1 (RST ? 1'd0 : _rReqPartialDone);\nend\n\nalways @ (*) begin\n\t// Signal TXN_DONE after we've recieved the (seemingly superfluous) TXN_ACK \n\t// and received the corresponding amount of words.\n\t_rPartialDone = (rReqPartialDone & rPartWordsRecvd);\n\t\n\t// Keep track of (seemingly superfluous) TXN_ACK requests.\n\tif ((rReqPartialDone & rPartWordsRecvd) | rMainState[0]) // S_RXPORTRD_MAIN_IDLE\n\t\t_rReqPartialDone = 0;\n\telse\n\t\t_rReqPartialDone = (rReqPartialDone | rTxnLenValid);\nend\n\n\n// Handle errors in the main data or scatter gather data.\nalways @ (posedge CLK) begin\n\trErr <= #1 (RST ? 1'd0 : _rErr);\nend\n\nalways @ (*) begin\n\t// Keep track of errors if we encounter them.\n\tif (rMainState[0]) // S_RXPORTRD_MAIN_IDLE\n\t\t_rErr = 0;\n\telse\n\t\t_rErr = (rErr | (RX_DONE & RX_ERR) | (SG_DONE & SG_ERR));\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/rx_port_requester_mux.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\trx_port_requester.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tIssues read requests to the tx_engine for the rx_port\n// and sg_list_requester modules in the rx_port. Expects those modules to update\n// their address and length values after every request issued. Also expects them\n// to update their space available values within 6 cycles of a change to the\n// RX_LEN.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_RXPORTREQ_RX_TX\t\t2'b00\n`define S_RXPORTREQ_TX_RX\t\t2'b01\n`define S_RXPORTREQ_ISSUE\t\t2'b10\n\nmodule rx_port_requester_mux (\n\tinput RST,\n\tinput CLK,\n\t\n\tinput SG_RX_REQ,\t\t\t\t// Scatter gather RX read request\n\tinput [9:0] SG_RX_LEN,\t\t\t// Scatter gather RX read request length\n\tinput [63:0] SG_RX_ADDR,\t\t// Scatter gather RX read request address\n\toutput SG_RX_REQ_PROC,\t\t\t// Scatter gather RX read request processing\n\n\tinput SG_TX_REQ,\t\t\t\t// Scatter gather TX read request\n\tinput [9:0] SG_TX_LEN,\t\t\t// Scatter gather TX read request length\n\tinput [63:0] SG_TX_ADDR,\t\t// Scatter gather TX read request address\n\toutput SG_TX_REQ_PROC,\t\t\t// Scatter gather TX read request processing\n\t\n\tinput MAIN_REQ,\t\t\t\t\t// Main read request\n\tinput [9:0] MAIN_LEN,\t\t\t// Main read request length\n\tinput [63:0] MAIN_ADDR,\t\t\t// Main read request address\n\toutput MAIN_REQ_PROC,\t\t\t// Main read request processing\n\n\toutput RX_REQ,\t\t\t\t\t// Read request\n\tinput RX_REQ_ACK,\t\t\t\t// Read request accepted\n\toutput [1:0] RX_REQ_TAG,\t\t// Read request data tag \n\toutput [63:0] RX_REQ_ADDR,\t\t// Read request address\n\toutput [9:0] RX_REQ_LEN,\t\t// Read request length\n\n\toutput REQ_ACK\t\t\t\t\t// Request accepted\n);\n\nreg\t\t\t\t\t\t\t\t\trRxReqAck=0, _rRxReqAck=0;\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[1:0]\t\t\t\t\t\trState=`S_RXPORTREQ_RX_TX, _rState=`S_RXPORTREQ_RX_TX;\nreg\t\t[9:0]\t\t\t\t\t\trLen=0, _rLen=0;\nreg\t\t[63:0]\t\t\t\t\t\trAddr=64'd0, _rAddr=64'd0;\nreg\t\t\t\t\t\t\t\t\trSgRxAck=0, _rSgRxAck=0;\nreg\t\t\t\t\t\t\t\t\trSgTxAck=0, _rSgTxAck=0;\nreg\t\t\t\t\t\t\t\t\trMainAck=0, _rMainAck=0;\nreg\t\t\t\t\t\t\t\t\trAck=0, _rAck=0;\n\n\nassign SG_RX_REQ_PROC = rSgRxAck;\nassign SG_TX_REQ_PROC = rSgTxAck;\nassign MAIN_REQ_PROC = rMainAck;\n\nassign RX_REQ = rState[1]; // S_RXPORTREQ_ISSUE\nassign RX_REQ_TAG = {rSgTxAck, rSgRxAck};\nassign RX_REQ_ADDR = rAddr;\nassign RX_REQ_LEN = rLen;\n\nassign REQ_ACK = rAck;\n\n\n// Buffer signals that come from outside the rx_port.\nalways @ (posedge CLK) begin\n\trRxReqAck <= #1 (RST ? 1'd0 : _rRxReqAck);\nend\n\nalways @ (*) begin\n\t_rRxReqAck = RX_REQ_ACK;\nend\n\n\n// Handle issuing read requests. Scatter gather requests are processed\n// with higher priority than the main channel.\nalways @ (posedge CLK) begin\n\trState <= #1 (RST ? `S_RXPORTREQ_RX_TX : _rState);\n\trLen <= #1 _rLen;\n\trAddr <= #1 _rAddr;\n\trSgRxAck <= #1 _rSgRxAck;\n\trSgTxAck <= #1 _rSgTxAck;\n\trMainAck <= #1 _rMainAck;\n\trAck <= #1 _rAck;\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\t_rLen = rLen;\n\t_rAddr = rAddr;\n\t_rSgRxAck = rSgRxAck;\n\t_rSgTxAck = rSgTxAck;\n\t_rMainAck = rMainAck;\n\t_rAck = rAck;\n\tcase (rState)\n\n\t`S_RXPORTREQ_RX_TX: begin // Wait for a new read request\n\t\tif (SG_RX_REQ) begin\n\t\t\t_rLen = SG_RX_LEN;\n\t\t\t_rAddr = SG_RX_ADDR;\n\t\t\t_rSgRxAck = 1;\n\t\t\t_rAck = 1;\n\t\t\t_rState = `S_RXPORTREQ_ISSUE;\n\t\tend\n\t\telse if (SG_TX_REQ) begin\n\t\t\t_rLen = SG_TX_LEN;\n\t\t\t_rAddr = SG_TX_ADDR;\n\t\t\t_rSgTxAck = 1;\n\t\t\t_rAck = 1;\n\t\t\t_rState = `S_RXPORTREQ_ISSUE;\n\t\tend\n\t\telse if (MAIN_REQ) begin\n\t\t\t_rLen = MAIN_LEN;\n\t\t\t_rAddr = MAIN_ADDR;\n\t\t\t_rMainAck = 1;\n\t\t\t_rAck = 1;\n\t\t\t_rState = `S_RXPORTREQ_ISSUE;\n\t\tend\n\t\telse begin\n\t\t\t_rState = `S_RXPORTREQ_TX_RX;\n\t\tend\n\tend\n\n\t`S_RXPORTREQ_TX_RX: begin // Wait for a new read request\n\t\tif (SG_TX_REQ) begin\n\t\t\t_rLen = SG_TX_LEN;\n\t\t\t_rAddr = SG_TX_ADDR;\n\t\t\t_rSgTxAck = 1;\n\t\t\t_rAck = 1;\n\t\t\t_rState = `S_RXPORTREQ_ISSUE;\n\t\tend\n\t\telse if (SG_RX_REQ) begin\n\t\t\t_rLen = SG_RX_LEN;\n\t\t\t_rAddr = SG_RX_ADDR;\n\t\t\t_rSgRxAck = 1;\n\t\t\t_rAck = 1;\n\t\t\t_rState = `S_RXPORTREQ_ISSUE;\n\t\tend\n\t\telse if (MAIN_REQ) begin\n\t\t\t_rLen = MAIN_LEN;\n\t\t\t_rAddr = MAIN_ADDR;\n\t\t\t_rMainAck = 1;\n\t\t\t_rAck = 1;\n\t\t\t_rState = `S_RXPORTREQ_ISSUE;\n\t\tend\n\t\telse begin\n\t\t\t_rState = `S_RXPORTREQ_RX_TX;\n\t\tend\n\tend\n\n\t`S_RXPORTREQ_ISSUE: begin // Issue the request\n\t\t_rAck = 0;\n\t\tif (rRxReqAck) begin\n\t\t\t_rSgRxAck = 0;\n\t\t\t_rSgTxAck = 0;\n\t\t\t_rMainAck = 0;\n\t\t\tif (rSgRxAck)\n\t\t\t\t_rState = `S_RXPORTREQ_TX_RX;\n\t\t\telse\n\t\t\t\t_rState = `S_RXPORTREQ_RX_TX;\n\t\tend\n\tend\n\n\tdefault: begin\n\t\t_rState = `S_RXPORTREQ_RX_TX;\n\tend\n\n\tendcase\nend\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/sg_list_reader_128.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tsg_list_reader_128.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tReads data from the scatter gather list buffer.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_SGR128_RD_0\t\t1'b1\n`define S_SGR128_RD_WAIT\t1'b0\n\n`define S_SGR128_CAP_0\t\t1'b0\n`define S_SGR128_CAP_RDY\t1'b1\n\nmodule sg_list_reader_128 #(\n\tparameter C_DATA_WIDTH = 9'd128\n)\n(\n\tinput CLK,\n\tinput RST,\n\n\tinput [C_DATA_WIDTH-1:0] BUF_DATA,\t// Scatter gather buffer data \n\tinput BUF_DATA_EMPTY,\t\t\t\t// Scatter gather buffer data empty\n\toutput BUF_DATA_REN,\t\t\t\t// Scatter gather buffer data read enable\n\n\toutput VALID,\t\t\t\t\t\t// Scatter gather element data is valid\n\toutput EMPTY,\t\t\t\t\t\t// Scatter gather elements empty\n\tinput REN,\t\t\t\t\t\t\t// Scatter gather element data read enable\n\toutput [63:0] ADDR,\t\t\t\t\t// Scatter gather element address\n\toutput [31:0] LEN\t\t\t\t\t// Scatter gather element length (in words)\n);\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t\t\t\t\t\trRdState=`S_SGR128_RD_0, _rRdState=`S_SGR128_RD_0;\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t\t\t\t\t\trCapState=`S_SGR128_CAP_0, _rCapState=`S_SGR128_CAP_0;\nreg\t\t[C_DATA_WIDTH-1:0]\trData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};\nreg\t\t[63:0]\t\t\t\trAddr=64'd0, _rAddr=64'd0;\nreg\t\t[31:0]\t\t\t\trLen=0, _rLen=0;\nreg\t\t\t\t\t\t\trFifoValid=0, _rFifoValid=0;\nreg\t\t\t\t\t\t\trDataValid=0, _rDataValid=0;\n\n\nassign BUF_DATA_REN = rRdState; // Not S_SGR128_RD_WAIT\nassign VALID = rCapState; // S_SGR128_CAP_RDY\nassign EMPTY = (BUF_DATA_EMPTY & rRdState); // Not S_SGR128_RD_WAIT\nassign ADDR = rAddr;\nassign LEN = rLen;\n\n\n// Capture address and length as it comes out of the FIFO\nalways @ (posedge CLK) begin\n\trRdState <= #1 (RST ? `S_SGR128_RD_0 : _rRdState);\n\trCapState <= #1 (RST ? `S_SGR128_CAP_0 : _rCapState);\n\trData <= #1 _rData;\n\trFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);\n\trDataValid <= #1 (RST ? 1'd0 : _rDataValid);\n\trAddr <= #1 _rAddr;\n\trLen <= #1 _rLen;\nend\n\nalways @ (*) begin\n\t_rRdState = rRdState;\n\t_rCapState = rCapState;\n\t_rAddr = rAddr;\n\t_rLen = rLen;\n\t_rData = BUF_DATA;\n\t_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);\n\t_rDataValid = rFifoValid;\n\n\tcase (rCapState)\n\t\n\t`S_SGR128_CAP_0: begin\n\t\tif (rDataValid) begin\n\t\t\t_rAddr = rData[63:0];\n\t\t\t_rLen = rData[95:64];\n\t\t\t_rCapState = `S_SGR128_CAP_RDY;\n\t\tend\n\tend\n\n\t`S_SGR128_CAP_RDY: begin\n\t\tif (REN)\n\t\t\t_rCapState = `S_SGR128_CAP_0;\n\tend\n\t\n\tendcase\n\n\tcase (rRdState)\n\n\t`S_SGR128_RD_0: begin // Read from the sg data FIFO\n\t\tif (!BUF_DATA_EMPTY)\n\t\t\t_rRdState = `S_SGR128_RD_WAIT;\n\tend\n\n\t`S_SGR128_RD_WAIT: begin // Wait for the data to be consumed\n\t\tif (REN)\n\t\t\t_rRdState = `S_SGR128_RD_0;\n\tend\n\t\n\tendcase\nend\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/sg_list_reader_32.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tsg_list_reader_32.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tReads data from the scatter gather list buffer.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_SGR32_RD_0\t\t3'b000\n`define S_SGR32_RD_1\t\t3'b001\n`define S_SGR32_RD_2\t\t3'b010\n`define S_SGR32_RD_3\t\t3'b011\n`define S_SGR32_RD_WAIT\t\t3'b100\n\n`define S_SGR32_CAP_0\t\t3'b000\n`define S_SGR32_CAP_1\t\t3'b001\n`define S_SGR32_CAP_2\t\t3'b010\n`define S_SGR32_CAP_3\t\t3'b011\n`define S_SGR32_CAP_RDY\t\t3'b100\n\nmodule sg_list_reader_32 #(\n\tparameter C_DATA_WIDTH = 9'd32\n)\n(\n\tinput CLK,\n\tinput RST,\n\n\tinput [C_DATA_WIDTH-1:0] BUF_DATA,\t// Scatter gather buffer data \n\tinput BUF_DATA_EMPTY,\t\t\t\t// Scatter gather buffer data empty\n\toutput BUF_DATA_REN,\t\t\t\t// Scatter gather buffer data read enable\n\n\toutput VALID,\t\t\t\t\t\t// Scatter gather element data is valid\n\toutput EMPTY,\t\t\t\t\t\t// Scatter gather elements empty\n\tinput REN,\t\t\t\t\t\t\t// Scatter gather element data read enable\n\toutput [63:0] ADDR,\t\t\t\t\t// Scatter gather element address\n\toutput [31:0] LEN\t\t\t\t\t// Scatter gather element length (in words)\n);\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[2:0]\t\t\t\trRdState=`S_SGR32_RD_0, _rRdState=`S_SGR32_RD_0;\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[2:0]\t\t\t\trCapState=`S_SGR32_CAP_0, _rCapState=`S_SGR32_CAP_0;\nreg\t\t[C_DATA_WIDTH-1:0]\trData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};\nreg\t\t[63:0]\t\t\t\trAddr=64'd0, _rAddr=64'd0;\nreg\t\t[31:0]\t\t\t\trLen=0, _rLen=0;\nreg\t\t\t\t\t\t\trFifoValid=0, _rFifoValid=0;\nreg\t\t\t\t\t\t\trDataValid=0, _rDataValid=0;\n\n\nassign BUF_DATA_REN = !rRdState[2]; // Not S_SGR32_RD_0\nassign VALID = rCapState[2]; // S_SGR32_CAP_RDY\nassign EMPTY = (BUF_DATA_EMPTY & !rRdState[2]); // Not S_SGR32_RD_0\nassign ADDR = rAddr;\nassign LEN = rLen;\n\n\n// Capture address and length as it comes out of the FIFO\nalways @ (posedge CLK) begin\n\trRdState <= #1 (RST ? `S_SGR32_RD_0 : _rRdState);\n\trCapState <= #1 (RST ? `S_SGR32_CAP_0 : _rCapState);\n\trData <= #1 _rData;\n\trFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);\n\trDataValid <= #1 (RST ? 1'd0 : _rDataValid);\n\trAddr <= #1 _rAddr;\n\trLen <= #1 _rLen;\nend\n\nalways @ (*) begin\n\t_rRdState = rRdState;\n\t_rCapState = rCapState;\n\t_rAddr = rAddr;\n\t_rLen = rLen;\n\t_rData = BUF_DATA;\n\t_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);\n\t_rDataValid = rFifoValid;\n\n\tcase (rCapState)\n\t\n\t`S_SGR32_CAP_0: begin\n\t\tif (rDataValid) begin\n\t\t\t_rAddr[31:0] = rData;\n\t\t\t_rCapState = `S_SGR32_CAP_1;\n\t\tend\n\tend\n\n\t`S_SGR32_CAP_1: begin\n\t\tif (rDataValid) begin\n\t\t\t_rAddr[63:32] = rData;\n\t\t\t_rCapState = `S_SGR32_CAP_2;\n\t\tend\n\tend\n\t\n\t`S_SGR32_CAP_2: begin\n\t\tif (rDataValid) begin\n\t\t\t_rLen = rData;\n\t\t\t_rCapState = `S_SGR32_CAP_3;\n\t\tend\n\tend\n\n\t`S_SGR32_CAP_3: begin\n\t\tif (rDataValid)\n\t\t\t_rCapState = `S_SGR32_CAP_RDY;\n\tend\n\n\t`S_SGR32_CAP_RDY: begin\n\t\tif (REN)\n\t\t\t_rCapState = `S_SGR32_CAP_0;\n\tend\n\n\tdefault: begin\n\t\t_rCapState = `S_SGR32_CAP_0;\n\tend\n\t\n\tendcase\n\n\tcase (rRdState)\n\n\t`S_SGR32_RD_0: begin // Read from the sg data FIFO\n\t\tif (!BUF_DATA_EMPTY)\n\t\t\t_rRdState = `S_SGR32_RD_1;\n\tend\n\n\t`S_SGR32_RD_1: begin // Read from the sg data FIFO\n\t\tif (!BUF_DATA_EMPTY)\n\t\t\t_rRdState = `S_SGR32_RD_2;\n\tend\n\n\t`S_SGR32_RD_2: begin // Read from the sg data FIFO\n\t\tif (!BUF_DATA_EMPTY)\n\t\t\t_rRdState = `S_SGR32_RD_3;\n\tend\n\n\t`S_SGR32_RD_3: begin // Read from the sg data FIFO\n\t\tif (!BUF_DATA_EMPTY)\n\t\t\t_rRdState = `S_SGR32_RD_WAIT;\n\tend\n\n\t`S_SGR32_RD_WAIT: begin // Wait for the data to be consumed\n\t\tif (REN)\n\t\t\t_rRdState = `S_SGR32_RD_0;\n\tend\n\n\tdefault: begin\n\t\t_rRdState = `S_SGR32_RD_0;\n\tend\n\t\n\tendcase\nend\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/sg_list_reader_64.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tsg_list_reader_64.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tReads data from the scatter gather list buffer.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_SGR64_RD_0\t\t2'b01\n`define S_SGR64_RD_1\t\t2'b11\n`define S_SGR64_RD_WAIT\t\t2'b10\n\n`define S_SGR64_CAP_0\t\t2'b00\n`define S_SGR64_CAP_1\t\t2'b01\n`define S_SGR64_CAP_RDY\t\t2'b10\n\nmodule sg_list_reader_64 #(\n\tparameter C_DATA_WIDTH = 9'd64\n)\n(\n\tinput CLK,\n\tinput RST,\n\n\tinput [C_DATA_WIDTH-1:0] BUF_DATA,\t// Scatter gather buffer data \n\tinput BUF_DATA_EMPTY,\t\t\t\t// Scatter gather buffer data empty\n\toutput BUF_DATA_REN,\t\t\t\t// Scatter gather buffer data read enable\n\n\toutput VALID,\t\t\t\t\t\t// Scatter gather element data is valid\n\toutput EMPTY,\t\t\t\t\t\t// Scatter gather elements empty\n\tinput REN,\t\t\t\t\t\t\t// Scatter gather element data read enable\n\toutput [63:0] ADDR,\t\t\t\t\t// Scatter gather element address\n\toutput [31:0] LEN\t\t\t\t\t// Scatter gather element length (in words)\n);\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[1:0]\t\t\t\trRdState=`S_SGR64_RD_0, _rRdState=`S_SGR64_RD_0;\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[1:0]\t\t\t\trCapState=`S_SGR64_CAP_0, _rCapState=`S_SGR64_CAP_0;\nreg\t\t[C_DATA_WIDTH-1:0]\trData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};\nreg\t\t[63:0]\t\t\t\trAddr=64'd0, _rAddr=64'd0;\nreg\t\t[31:0]\t\t\t\trLen=0, _rLen=0;\nreg\t\t\t\t\t\t\trFifoValid=0, _rFifoValid=0;\nreg\t\t\t\t\t\t\trDataValid=0, _rDataValid=0;\n\n\nassign BUF_DATA_REN = rRdState[0]; // Not S_SGR64_RD_WAIT\nassign VALID = rCapState[1]; // S_SGR64_CAP_RDY\nassign EMPTY = (BUF_DATA_EMPTY & rRdState[0]); // Not S_SGR64_RD_WAIT\nassign ADDR = rAddr;\nassign LEN = rLen;\n\n\n// Capture address and length as it comes out of the FIFO\nalways @ (posedge CLK) begin\n\trRdState <= #1 (RST ? `S_SGR64_RD_0 : _rRdState);\n\trCapState <= #1 (RST ? `S_SGR64_CAP_0 : _rCapState);\n\trData <= #1 _rData;\n\trFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);\n\trDataValid <= #1 (RST ? 1'd0 : _rDataValid);\n\trAddr <= #1 _rAddr;\n\trLen <= #1 _rLen;\nend\n\nalways @ (*) begin\n\t_rRdState = rRdState;\n\t_rCapState = rCapState;\n\t_rAddr = rAddr;\n\t_rLen = rLen;\n\t_rData = BUF_DATA;\n\t_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);\n\t_rDataValid = rFifoValid;\n\n\tcase (rCapState)\n\t\n\t`S_SGR64_CAP_0: begin\n\t\tif (rDataValid) begin\n\t\t\t_rAddr = rData;\n\t\t\t_rCapState = `S_SGR64_CAP_1;\n\t\tend\n\tend\n\t\n\t`S_SGR64_CAP_1: begin\n\t\tif (rDataValid) begin\n\t\t\t_rLen = rData[31:0];\n\t\t\t_rCapState = `S_SGR64_CAP_RDY;\n\t\tend\n\tend\n\n\t`S_SGR64_CAP_RDY: begin\n\t\tif (REN)\n\t\t\t_rCapState = `S_SGR64_CAP_0;\n\tend\n\n\tdefault: begin\n\t\t_rCapState = `S_SGR64_CAP_0;\n\tend\n\t\n\tendcase\n\n\tcase (rRdState)\n\n\t`S_SGR64_RD_0: begin // Read from the sg data FIFO\n\t\tif (!BUF_DATA_EMPTY)\n\t\t\t_rRdState = `S_SGR64_RD_1;\n\tend\n\n\t`S_SGR64_RD_1: begin // Read from the sg data FIFO\n\t\tif (!BUF_DATA_EMPTY)\n\t\t\t_rRdState = `S_SGR64_RD_WAIT;\n\tend\n\n\t`S_SGR64_RD_WAIT: begin // Wait for the data to be consumed\n\t\tif (REN)\n\t\t\t_rRdState = `S_SGR64_RD_0;\n\tend\n\n\tdefault: begin\n\t\t_rRdState = `S_SGR64_RD_0;\n\tend\n\t\n\tendcase\nend\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/sg_list_requester.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tsg_list_requester.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tReceives scatter gather address/length info and requests\n// the scatter gather data from the RX engine. Monitors the state of the scatter\n// gather FIFO to make sure it can accommodate the requested data. Also signals\n// when the entire scatter gather data has been received so the buffer can be\n// overwritten with new data.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_SGREQ_IDLE\t8'b0000_0001\n`define S_SGREQ_WAIT_0\t8'b0000_0010\n`define S_SGREQ_WAIT_1\t8'b0000_0100\n`define S_SGREQ_CHECK\t8'b0000_1000\n`define S_SGREQ_ISSUE\t8'b0001_0000\n`define S_SGREQ_UPDATE\t8'b0010_0000\n`define S_SGREQ_COUNT\t8'b0100_0000\n`define S_SGREQ_FLUSH\t8'b1000_0000\n\nmodule sg_list_requester #(\n\tparameter C_FIFO_DATA_WIDTH = 9'd64,\n\tparameter C_FIFO_DEPTH = 1024,\n\tparameter C_MAX_READ_REQ = 2,\t\t\t\t// Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t// Local parameters\n\tparameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),\n\tparameter C_WORDS_PER_ELEM = 4,\n\tparameter C_MAX_ELEMS = 200,\n\tparameter C_MAX_ENTRIES = (C_MAX_ELEMS*C_WORDS_PER_ELEM),\n\tparameter C_FIFO_COUNT_THRESH = C_FIFO_DEPTH - C_MAX_ENTRIES\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [2:0] CONFIG_MAX_READ_REQUEST_SIZE,\t\t\t// Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\n\tinput USER_RST,\t\t\t\t\t\t\t\t// User reset, should clear FIFO data too\n\t\n\toutput BUF_RECVD,\t\t\t\t\t\t\t// Signals when scatter gather buffer received\n\tinput [31:0] BUF_DATA,\t\t\t\t\t\t// Buffer data\n\tinput BUF_LEN_VALID,\t\t\t\t\t\t// Buffer length valid\n\tinput BUF_ADDR_HI_VALID,\t\t\t\t\t// Buffer high address valid\n\tinput BUF_ADDR_LO_VALID,\t\t\t\t\t// Buffer low address valid\n\n\tinput [C_FIFO_DEPTH_WIDTH-1:0] FIFO_COUNT,\t// Scatter gather FIFO count\n\toutput FIFO_FLUSH,\t\t\t\t\t\t\t// Scatter gather FIFO flush request\n\tinput FIFO_FLUSHED,\t\t\t\t\t\t\t// Scatter gather FIFO flushed\n\toutput FIFO_RST,\t\t\t\t\t\t\t// Scatter gather FIFO data reset request\n\n\toutput RX_REQ,\t\t\t\t\t\t\t\t// Issue a read request\n\toutput [63:0] RX_ADDR,\t\t\t\t\t\t// Request address\n\toutput [9:0] RX_LEN,\t\t\t\t\t\t// Request length\n\tinput RX_REQ_ACK,\t\t\t\t\t\t\t// Request has been issued\n\tinput RX_DONE\t\t\t\t\t\t\t\t// Request has completed (data received)\n);\n\n`include \"common_functions.v\"\n\nreg\t\t[31:0]\t\t\trData=0, _rData=0;\nreg\t\t\t\t\t\trAddrHiValid=0, _rAddrHiValid=0;\nreg\t\t\t\t\t\trAddrLoValid=0, _rAddrLoValid=0;\nreg\t\t\t\t\t\trLenValid=0, _rLenValid=0;\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[7:0]\t\t\trState=`S_SGREQ_IDLE, _rState=`S_SGREQ_IDLE;\nreg\t\t\t\t\t\trDone=0, _rDone=0;\nreg\t\t\t\t\t\trDelay=0, _rDelay=0;\nreg\t\t[2:0]\t\t\trCarry=0, _rCarry=0;\nreg\t\t[3:0]\t\t\trValsProp=0, _rValsProp=0;\nreg\t\t[63:0]\t\t\trAddr=64'd0, _rAddr=64'd0;\nreg\t\t[31:0]\t\t\trBufWords=0, _rBufWords=0;\nreg\t\t[10:0]\t\t\trPageRem=0, _rPageRem=0;\nreg\t\t\t\t\t\trPageSpill=0, _rPageSpill=0;\nreg\t\t[10:0]\t\t\trPreLen=0, _rPreLen=0;\nreg\t\t[2:0]\t\t\trMaxPayloadTrain=0, _rMaxPayloadTrain=0;\nreg\t\t[2:0]\t\t\trMaxPayloadShift=0, _rMaxPayloadShift=0;\nreg\t\t[9:0]\t\t\trMaxPayload=0, _rMaxPayload=0;\nreg\t\t\t\t\t\trPayloadSpill=0, _rPayloadSpill=0;\nreg\t\t[9:0]\t\t\trLen=0, _rLen=0;\nreg\t\t\t\t\t\trBufWordsEQ0Hi=0, _rBufWordsEQ0Hi=0;\nreg\t\t\t\t\t\trBufWordsEQ0Lo=0, _rBufWordsEQ0Lo=0;\nreg\t\t\t\t\t\trUserRst=0, _rUserRst=0;\n\nreg\t\t\t\t\t\trRecvdAll=0, _rRecvdAll=0;\nreg\t\t[10:0]\t\t\trAckCount=0, _rAckCount=0;\n\n\nassign BUF_RECVD = rDone;\n\nassign FIFO_FLUSH = rState[7]; // S_SGREQ_FLUSH\nassign FIFO_RST = (rUserRst & rState[0]); // S_SGREQ_IDLE\n\nassign RX_ADDR = rAddr;\nassign RX_LEN = rLen;\nassign RX_REQ = rState[4]; // S_SGREQ_ISSUE\n\n\n// Buffer signals coming from outside the rx_port.\nalways @ (posedge CLK) begin\n\trData <= #1 _rData;\n\trAddrHiValid <= #1 _rAddrHiValid;\n\trAddrLoValid <= #1 _rAddrLoValid;\n\trLenValid <= #1 _rLenValid;\nend\n\nalways @ (*) begin\n\t_rData = BUF_DATA;\n\t_rAddrHiValid = BUF_ADDR_HI_VALID;\n\t_rAddrLoValid = BUF_ADDR_LO_VALID;\n\t_rLenValid = BUF_LEN_VALID;\nend\n\n\n// Handle requesting the next scatter gather buffer data.\nwire [9:0] wAddrLoInv = ~rAddr[11:2];\nalways @ (posedge CLK) begin\n\trState <= #1 (RST ? `S_SGREQ_IDLE : _rState);\n\trDone <= #1 (RST ? 1'd0 : _rDone);\n\trDelay <= #1 _rDelay;\n\trAddr <= #1 _rAddr;\n\trCarry <= #1 _rCarry;\n\trBufWords <= #1 _rBufWords;\n\trValsProp <= #1 _rValsProp;\n\trPageRem <= #1 _rPageRem;\n\trPageSpill <= #1 _rPageSpill;\n\trPreLen <= #1 _rPreLen;\n\trMaxPayloadTrain <= #1 _rMaxPayloadTrain;\n\trMaxPayloadShift <= #1 _rMaxPayloadShift;\n\trMaxPayload <= #1 _rMaxPayload;\n\trPayloadSpill <= #1 _rPayloadSpill;\n\trLen <= #1 _rLen;\n\trBufWordsEQ0Hi <= #1 _rBufWordsEQ0Hi;\n\trBufWordsEQ0Lo <= #1 _rBufWordsEQ0Lo;\n\trUserRst <= #1 (RST ? 1'd0 : _rUserRst);\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\t_rDone = rDone;\n\t_rDelay = rDelay;\n\n\t_rUserRst = ((rUserRst & !rState[0]) | USER_RST);\n\t_rValsProp = ((rValsProp<<1) | RX_REQ_ACK);\n\t{_rCarry[0], _rAddr[15:0]} = (rAddrLoValid ? rData[15:0] : (rAddr[15:0] + ({12{RX_REQ_ACK}} & {2'b0,rLen}<<2)));\n\t{_rCarry[1], _rAddr[31:16]} = (rAddrLoValid ? rData[31:16] : (rAddr[31:16] + rCarry[0]));\n\t{_rCarry[2], _rAddr[47:32]} = (rAddrHiValid ? rData[15:0] : (rAddr[47:32] + rCarry[1]));\n\t\t\t\t _rAddr[63:48] = (rAddrHiValid ? rData[31:16] : (rAddr[63:48] + rCarry[2]));\n\t_rBufWords = (rLenValid ? rData : rBufWords) - ({10{RX_REQ_ACK}} & rLen);\n\t_rPageRem = (wAddrLoInv + 1'd1);\t\n\t_rPageSpill = (rBufWords > rPageRem);\t\n\t_rPreLen = (rPageSpill ? rPageRem : rBufWords[10:0]);\t\t\t\n\t_rMaxPayloadTrain = (CONFIG_MAX_READ_REQUEST_SIZE > 3'd4 ? 3'd4 : CONFIG_MAX_READ_REQUEST_SIZE);\n\t_rMaxPayloadShift = (C_MAX_READ_REQ[2:0] < rMaxPayloadTrain ? C_MAX_READ_REQ[2:0] : rMaxPayloadTrain);\n\t_rMaxPayload = (6'd32< rMaxPayload);\n\t_rLen = (rPayloadSpill ? rMaxPayload : rPreLen[9:0]);\n\t_rBufWordsEQ0Hi = (16'd0 == rBufWords[31:16]);\n\t_rBufWordsEQ0Lo = (16'd0 == rBufWords[15:0]);\n\n\tcase (rState)\n\n\t`S_SGREQ_IDLE: begin // Wait for addr & length\n\t\t_rDone = 0;\n\t\tif (rLenValid)\n\t\t\t_rState = `S_SGREQ_WAIT_0;\n\tend\n\n\t`S_SGREQ_WAIT_0: begin // Wait 1 cycle for values to propagate\n\t\t_rDelay = 0;\n\t\t_rState = `S_SGREQ_WAIT_1;\n\tend\n\n\t`S_SGREQ_WAIT_1: begin // Wait 2 cycles for values to propagate\n\t\t_rDelay = 1;\n\t\tif (rDelay)\n\t\t\t_rState = `S_SGREQ_CHECK;\n\tend\n\n\t`S_SGREQ_CHECK: begin // Wait for space to be made available\n\t\tif (FIFO_COUNT < C_FIFO_COUNT_THRESH)\n\t\t\t_rState = `S_SGREQ_ISSUE;\n\t\telse if (rUserRst)\n\t\t\t_rState = `S_SGREQ_COUNT;\n\tend\n\t\n\t`S_SGREQ_ISSUE: begin // Wait for read request to be serviced\n\t\tif (RX_REQ_ACK)\n\t\t\t_rState = `S_SGREQ_UPDATE;\n\tend\n\n\t`S_SGREQ_UPDATE: begin // Update the address and length\n\t\tif (rUserRst | (rBufWordsEQ0Hi & rBufWordsEQ0Lo))\n\t\t\t_rState = `S_SGREQ_COUNT;\n\t\telse if (rValsProp[3])\n\t\t\t_rState = `S_SGREQ_ISSUE;\n\tend\n\n\t`S_SGREQ_COUNT: begin // Wait for read data to arrive\n\t\tif (rRecvdAll)\n\t\t\t_rState = `S_SGREQ_FLUSH;\n\tend\n\n\t`S_SGREQ_FLUSH: begin // Wait for read data to arrive\n\t\tif (FIFO_FLUSHED) begin\n\t\t\t_rDone = !rUserRst;\n\t\t\t_rState = `S_SGREQ_IDLE;\n\t\tend\n\tend\n\n\tdefault: begin\n\t\t_rState = `S_SGREQ_IDLE;\n\tend\n\n\tendcase\nend\n\n\n// Keep track of requests made and requests completed so we know when all\n// the outstanding data has been received.\nalways @ (posedge CLK) begin\n\trAckCount <= #1 (RST ? 10'd0 : _rAckCount);\n\trRecvdAll <= #1 _rRecvdAll;\nend\n\nalways @ (*) begin\n\t// Track REQ_DONE and SG_DONE to maintain an outstanding request count.\n\t_rRecvdAll = (rAckCount == 10'd0);\n\tif (rState[0]) // S_SGREQ_IDLE\n\t\t_rAckCount = 0;\n\telse\n\t\t_rAckCount = rAckCount + RX_REQ_ACK - RX_DONE; \nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/sync_fifo.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tsync_fifo.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tA synchronous capable parameterized FIFO. As with all\n// traditional FIFOs, the RD_DATA will be valid one cycle following a RD_EN \n// assertion. EMPTY will remain low until the cycle following the last RD_EN \n// assertion. Note, that EMPTY may actually be high on the same cycle that \n// RD_DATA contains valid data.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n\nmodule sync_fifo #(\n\tparameter C_WIDTH = 32,\t// Data bus width\n\tparameter C_DEPTH = 1024,\t// Depth of the FIFO\n\tparameter C_PROVIDE_COUNT = 0, // Include code for counts\n\t// Local parameters\n\tparameter C_REAL_DEPTH = 2**clog2(C_DEPTH),\n\tparameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),\n\tparameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1)\n)\n(\n\tinput CLK,\t\t\t\t\t\t\t\t// Clock\n\tinput RST, \t\t\t\t\t\t\t\t// Sync reset, active high\n\tinput [C_WIDTH-1:0] WR_DATA, \t\t\t// Write data input\n\tinput WR_EN, \t\t\t\t\t\t\t// Write enable, high active\n\toutput [C_WIDTH-1:0] RD_DATA, \t\t\t// Read data output\n\tinput RD_EN,\t\t\t\t\t\t\t// Read enable, high active\n\toutput FULL, \t\t\t\t\t\t\t// Full condition\n\toutput EMPTY, \t\t\t\t\t\t\t// Empty condition\n\toutput [C_DEPTH_P1_BITS-1:0] COUNT\t\t// Data count\n);\n\n`include \"common_functions.v\"\n\nreg\t\t[C_DEPTH_BITS:0]\trWrPtr=0, _rWrPtr=0;\nreg\t\t[C_DEPTH_BITS:0]\trWrPtrPlus1=1, _rWrPtrPlus1=1;\nreg\t\t[C_DEPTH_BITS:0]\trRdPtr=0, _rRdPtr=0;\nreg\t\t[C_DEPTH_BITS:0]\trRdPtrPlus1=1, _rRdPtrPlus1=1;\nreg\t\t\t\t\t\t\trFull=0, _rFull=0;\nreg\t\t\t\t\t\t\trEmpty=1, _rEmpty=1;\n\n// Memory block (synthesis attributes applied to this module will\n// determine the memory option).\nram_1clk_1w_1r #(.C_RAM_WIDTH(C_WIDTH), .C_RAM_DEPTH(C_REAL_DEPTH)) mem (\n\t.CLK(CLK),\n\t.ADDRA(rWrPtr[C_DEPTH_BITS-1:0]),\n\t.WEA(WR_EN & !rFull),\n\t.DINA(WR_DATA),\n\t.ADDRB(rRdPtr[C_DEPTH_BITS-1:0]),\n\t.DOUTB(RD_DATA)\n);\n\n\n// Write pointer logic.\nalways @ (posedge CLK) begin\n\tif (RST) begin\n\t\trWrPtr <= #1 0;\n\t\trWrPtrPlus1 <= #1 1;\n\tend\n\telse begin\n\t\trWrPtr <= #1 _rWrPtr;\n\t\trWrPtrPlus1 <= #1 _rWrPtrPlus1;\n\tend\nend\n\nalways @ (*) begin\n\tif (WR_EN & !rFull) begin\n\t\t_rWrPtr = rWrPtrPlus1;\n\t\t_rWrPtrPlus1 = rWrPtrPlus1 + 1'd1;\n\tend\n\telse begin\n\t\t_rWrPtr = rWrPtr;\n\t\t_rWrPtrPlus1 = rWrPtrPlus1;\n\tend\nend\n\n\n// Read pointer logic.\nalways @ (posedge CLK) begin\n\tif (RST) begin\n\t\trRdPtr <= #1 0;\n\t\trRdPtrPlus1 <= #1 1;\n\tend\n\telse begin\n\t\trRdPtr <= #1 _rRdPtr;\n\t\trRdPtrPlus1 <= #1 _rRdPtrPlus1;\n\tend\nend\n\nalways @ (*) begin\n\tif (RD_EN & !rEmpty) begin\n\t\t_rRdPtr = rRdPtrPlus1;\n\t\t_rRdPtrPlus1 = rRdPtrPlus1 + 1'd1;\n\tend\n\telse begin\n\t\t_rRdPtr = rRdPtr;\n\t\t_rRdPtrPlus1 = rRdPtrPlus1;\n\tend\nend\n\n\n// Calculate empty\nassign EMPTY = rEmpty;\n\nalways @ (posedge CLK) begin\n\trEmpty <= #1 (RST ? 1'd1 : _rEmpty);\nend\n\nalways @ (*) begin\n\t_rEmpty = (rWrPtr == rRdPtr) || (RD_EN && !rEmpty && (rWrPtr == rRdPtrPlus1));\nend\n\n\n// Calculate full\nassign FULL = rFull;\n\nalways @ (posedge CLK) begin\n\trFull <= #1 (RST ? 1'd0 : _rFull);\nend\n\nalways @ (*) begin\n\t_rFull = ((rWrPtr[C_DEPTH_BITS-1:0] == rRdPtr[C_DEPTH_BITS-1:0]) && (rWrPtr[C_DEPTH_BITS] != rRdPtr[C_DEPTH_BITS])) ||\n\t(WR_EN && (rWrPtrPlus1[C_DEPTH_BITS-1:0] == rRdPtr[C_DEPTH_BITS-1:0]) && (rWrPtrPlus1[C_DEPTH_BITS] != rRdPtr[C_DEPTH_BITS]));\nend\n\ngenerate\nif (C_PROVIDE_COUNT) begin: provide_count\n\treg [C_DEPTH_BITS:0] rCount=0, _rCount=0;\n\n\tassign COUNT = (rFull ? C_REAL_DEPTH[C_DEPTH_P1_BITS-1:0] : rCount);\n\n\t// Calculate read count\n\talways @ (posedge CLK) begin\n\t\tif (RST)\n\t\t\trCount <= #1 0;\n\t\telse\n\t\t\trCount <= #1 _rCount;\n\tend\n\n\talways @ (*) begin\n\t\t_rCount = (rWrPtr - rRdPtr);\n\tend\nend\nelse begin: provide_no_count\n\tassign COUNT = 0;\nend \nendgenerate\n \nendmodule\n " }, { "path": "hw/boards/ML605/ipcore_dir/riffa/syncff.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\tsyncff.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tA back to back FF design to mitigate metastable issues \n// \t\t\t\t\t\twhen crossing clock domains.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\nmodule syncff(\n\tCLK,\n\tIN_ASYNC,\n\tOUT_SYNC\n);\n\ninput \t\t\t\t\tCLK;\ninput \t\t\t\t\tIN_ASYNC;\noutput \t\t\t\tOUT_SYNC;\n\nwire\t\t\t\t\twSyncFFQ;\n\nff syncFF (\n\t.CLK(CLK),\n\t.D(IN_ASYNC),\n\t.Q(wSyncFFQ)\n);\n\nff metaFF (\n\t.CLK(CLK),\n\t.D(wSyncFFQ),\n\t.Q(OUT_SYNC)\n);\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/translation_layer.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date:\t 19:27:32 05/15/2014 \n// Design Name: \n// Module Name:\t translation_layer\n// Project Name: \n// Target Devices: \n// Tool versions: \n// Description:\n// Translates AXI (Xilinx) or Avalon (Altera) signals into Unified (architecture\n// independent) streaming signals for riffa. The altera RX interface has a 1 cycle\n// latency because it needs to produce several metadata signals that are not \n// provided by the altera PCIe Core.\n//\n// Dependencies: None\n//\n// Revision: \n// Revision 0.01 - File Created\n// Additional Comments: \n//\n//////////////////////////////////////////////////////////////////////////////////\nmodule translation_layer\n\t#(parameter C_ALTERA = 1'b1,\n\t parameter C_PCI_DATA_WIDTH = 9'd128,\n\t parameter C_TX_READY_LATENCY = 3'd1)\n\t(\n\t input \t\t\t\t\t\t\t CLK,\n\t input \t\t\t\t\t\t\t RST_IN,\n\n\t // Xilinx Signals\n\t input [C_PCI_DATA_WIDTH-1:0] \t M_AXIS_RX_TDATA,\n\t input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,\n\t input \t\t\t\t\t\t\t M_AXIS_RX_TLAST, // Not used in the 128 bit interface\n\t input \t\t\t\t\t\t\t M_AXIS_RX_TVALID,\n\t output \t\t\t\t\t\t M_AXIS_RX_TREADY,\n\t input [4:0] \t\t\t\t\t IS_SOF,\n\t input [4:0] \t\t\t\t\t IS_EOF,\n\t input \t\t\t\t\t\t\t RERR_FWD,\n\t\n\t output [C_PCI_DATA_WIDTH-1:0] \t S_AXIS_TX_TDATA,\n\t output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,\n\t output \t\t\t\t\t\t S_AXIS_TX_TLAST,\n\t output \t\t\t\t\t\t S_AXIS_TX_TVALID,\n\t output \t\t\t\t\t\t S_AXIS_SRC_DSC,\n\t input \t\t\t\t\t\t\t S_AXIS_TX_TREADY,\n\t\n\t input [15:0] \t\t\t\t\t COMPLETER_ID,\n\t input \t\t\t\t\t\t\t CFG_BUS_MSTR_ENABLE, \n\t input [5:0] \t\t\t\t\t CFG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=? \n\t input [1:0] \t\t\t\t\t CFG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?\n\t input [2:0] \t\t\t\t\t CFG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t input [2:0] \t\t\t\t\t CFG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B\n\n\t input \t\t\t\t\t\t\t CFG_INTERRUPT_MSIEN, // 1 if MSI interrupts are enable, 0 if only legacy are supported\n\t input \t\t\t\t\t\t\t CFG_INTERRUPT_RDY, // High when interrupt is able to be sent\n\t output \t\t\t\t\t\t CFG_INTERRUPT, // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high, interrupt is sent);\n\t input \t\t\t\t\t\t\t RCB,\n\t input [11:0] \t\t\t\t\t MAX_RC_CPLD, // Receive credit limit for data (be sure fc_sel == 001)\n\t input [7:0] \t\t\t\t\t MAX_RC_CPLH, // Receive credit limit for headers (be sure fc_sel == 001)\n\t\n\t // Altera Signals\n\t input [C_PCI_DATA_WIDTH-1:0] \t RX_ST_DATA,\n\t input [0:0] \t\t\t\t\t RX_ST_EOP,\n\t input [0:0] \t\t\t\t\t RX_ST_SOP, \n\t input [0:0] \t\t\t\t\t RX_ST_VALID,\n\t output \t\t\t\t\t\t RX_ST_READY,\n\t input [0:0] \t\t\t\t\t RX_ST_EMPTY,\n\n\t output [C_PCI_DATA_WIDTH-1:0] \t TX_ST_DATA,\n\t output [0:0] \t\t\t\t\t TX_ST_VALID,\n\t input \t\t\t\t\t\t\t TX_ST_READY,\n\t output [0:0] \t\t\t\t\t TX_ST_EOP,\n\t output [0:0] \t\t\t\t\t TX_ST_SOP,\n\t output [0:0] \t\t\t\t\t TX_ST_EMPTY,\n\t input [31:0] \t\t\t\t\t TL_CFG_CTL,\n\t input [3:0] \t\t\t\t\t TL_CFG_ADD,\n\t input [52:0] \t\t\t\t\t TL_CFG_STS,\n\n\t input [7:0] \t\t\t\t\t KO_CPL_SPC_HEADER,\n\t input [11:0] \t\t\t\t\t KO_CPL_SPC_DATA,\n\t\n\t input \t\t\t\t\t\t\t APP_MSI_ACK,\n\t output \t\t\t\t\t\t APP_MSI_REQ,\n\n\t // Unified Signals\n\t output [C_PCI_DATA_WIDTH-1:0] \t RX_DATA,\n\t output \t\t\t\t\t\t RX_DATA_VALID,\n\t input \t\t\t\t\t\t\t RX_DATA_READY,\n\t output [(C_PCI_DATA_WIDTH/8)-1:0] RX_DATA_BYTE_ENABLE,\n\n\t output \t\t\t\t\t\t RX_TLP_END_FLAG,\n\t output [3:0] \t\t\t\t\t RX_TLP_END_OFFSET,\n\t output \t\t\t\t\t\t RX_TLP_START_FLAG,\n\t output [3:0] \t\t\t\t\t RX_TLP_START_OFFSET,\n\t output \t\t\t\t\t\t RX_TLP_ERROR_POISON,\n\t\n\t input [C_PCI_DATA_WIDTH-1:0] \t TX_DATA,\n\t input [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,\n\t input \t\t\t\t\t\t\t TX_TLP_END_FLAG,\n\t input \t\t\t\t\t\t\t TX_TLP_START_FLAG,\n\t input \t\t\t\t\t\t\t TX_DATA_VALID,\n\t input \t\t\t\t\t\t\t TX_TLP_ERROR_POISON, \n\t output \t\t\t\t\t\t TX_DATA_READY,\n\n\t output [15:0] \t\t\t\t\t CONFIG_COMPLETER_ID,\n\t output \t\t\t\t\t\t CONFIG_BUS_MASTER_ENABLE, \n\t output [5:0] \t\t\t\t\t CONFIG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=? \n\t output [1:0] \t\t\t\t\t CONFIG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?\n\t output [2:0] \t\t\t\t\t CONFIG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t output [2:0] \t\t\t\t\t CONFIG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B\n\t output \t\t\t\t\t\t CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported\n\n\t output [11:0] \t\t\t\t\t CONFIG_MAX_CPL_DATA, // Receive credit limit for data\n\t output [7:0] \t\t\t\t\t CONFIG_MAX_CPL_HDR, // Receive credit limit for headers\n\t output \t\t\t\t\t\t CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 bytes)w\n\t output \t\t\t\t\t\t INTR_MSI_RDY, // High when interrupt is able to be sent\n\t input \t\t\t\t\t\t\t INTR_MSI_REQUEST // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are hi\n\n\t );\n\t\n\tgenerate\n\t\tif (C_PCI_DATA_WIDTH == 9'd32) begin : endpoint32\n\t\t\ttranslation_layer_32\n\t\t\t\t#(.C_ALTERA(1'b0),\n\t\t\t\t .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))\n\t\t\ttl32_inst\n\t\t\t\t(/*AUTOINST*/\n\t\t\t\t // Outputs\n\t\t\t\t .M_AXIS_RX_TREADY\t\t(M_AXIS_RX_TREADY),\n\t\t\t\t .S_AXIS_TX_TDATA\t\t(S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .S_AXIS_TX_TKEEP\t\t(S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),\n\t\t\t\t .S_AXIS_TX_TLAST\t\t(S_AXIS_TX_TLAST),\n\t\t\t\t .S_AXIS_TX_TVALID\t\t(S_AXIS_TX_TVALID),\n\t\t\t\t .S_AXIS_SRC_DSC\t\t(S_AXIS_SRC_DSC),\n\t\t\t\t .CFG_INTERRUPT\t\t\t(CFG_INTERRUPT),\n\t\t\t\t .RX_ST_READY\t\t\t(RX_ST_READY),\n\t\t\t\t .TX_ST_DATA\t\t\t(TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .TX_ST_VALID\t\t\t(TX_ST_VALID[0:0]),\n\t\t\t\t .TX_ST_EOP\t\t\t\t(TX_ST_EOP[0:0]),\n\t\t\t\t .TX_ST_SOP\t\t\t\t(TX_ST_SOP[0:0]),\n\t\t\t\t .TX_ST_EMPTY\t\t\t(TX_ST_EMPTY[0:0]),\n\t\t\t\t .APP_MSI_REQ\t\t\t(APP_MSI_REQ),\n\t\t\t\t .RX_DATA\t\t\t\t(RX_DATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .RX_DATA_VALID\t\t\t(RX_DATA_VALID),\n\t\t\t\t .RX_DATA_BYTE_ENABLE\t(RX_DATA_BYTE_ENABLE[(C_PCI_DATA_WIDTH/8)-1:0]),\n\t\t\t\t .RX_TLP_END_FLAG\t\t(RX_TLP_END_FLAG),\n\t\t\t\t .RX_TLP_END_OFFSET\t\t(RX_TLP_END_OFFSET[3:0]),\n\t\t\t\t .RX_TLP_START_FLAG\t\t(RX_TLP_START_FLAG),\n\t\t\t\t .RX_TLP_START_OFFSET\t(RX_TLP_START_OFFSET[3:0]),\n\t\t\t\t .RX_TLP_ERROR_POISON\t(RX_TLP_ERROR_POISON),\n\t\t\t\t .TX_DATA_READY\t\t\t(TX_DATA_READY),\n\t\t\t\t .CONFIG_COMPLETER_ID\t(CONFIG_COMPLETER_ID[15:0]),\n\t\t\t\t .CONFIG_BUS_MASTER_ENABLE(CONFIG_BUS_MASTER_ENABLE),\n\t\t\t\t .CONFIG_LINK_WIDTH\t\t(CONFIG_LINK_WIDTH[5:0]),\n\t\t\t\t .CONFIG_LINK_RATE\t\t(CONFIG_LINK_RATE[1:0]),\n\t\t\t\t .CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),\n\t\t\t\t .CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE[2:0]),\n\t\t\t\t .CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),\n\t\t\t\t .CONFIG_MAX_CPL_DATA\t(CONFIG_MAX_CPL_DATA[11:0]),\n\t\t\t\t .CONFIG_MAX_CPL_HDR\t(CONFIG_MAX_CPL_HDR[7:0]),\n\t\t\t\t .CONFIG_CPL_BOUNDARY_SEL(CONFIG_CPL_BOUNDARY_SEL),\n\t\t\t\t .INTR_MSI_RDY\t\t\t(INTR_MSI_RDY),\n\t\t\t\t // Inputs\n\t\t\t\t .CLK\t\t\t\t\t(CLK),\n\t\t\t\t .RST_IN\t\t\t\t(RST_IN),\n\t\t\t\t .M_AXIS_RX_TDATA\t\t(M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .M_AXIS_RX_TKEEP\t\t(M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),\n\t\t\t\t .M_AXIS_RX_TLAST\t\t(M_AXIS_RX_TLAST),\n\t\t\t\t .M_AXIS_RX_TVALID\t\t(M_AXIS_RX_TVALID),\n\t\t\t\t .IS_SOF\t\t\t\t(IS_SOF[(C_PCI_DATA_WIDTH/32):0]),\n\t\t\t\t .IS_EOF\t\t\t\t(IS_EOF[(C_PCI_DATA_WIDTH/32):0]),\n\t\t\t\t .RERR_FWD\t\t\t\t(RERR_FWD),\n\t\t\t\t .S_AXIS_TX_TREADY\t\t(S_AXIS_TX_TREADY),\n\t\t\t\t .COMPLETER_ID\t\t\t(COMPLETER_ID[15:0]),\n\t\t\t\t .CFG_BUS_MSTR_ENABLE\t(CFG_BUS_MSTR_ENABLE),\n\t\t\t\t .CFG_LINK_WIDTH\t\t(CFG_LINK_WIDTH[5:0]),\n\t\t\t\t .CFG_LINK_RATE\t\t\t(CFG_LINK_RATE[1:0]),\n\t\t\t\t .CFG_MAX_READ_REQUEST_SIZE(CFG_MAX_READ_REQUEST_SIZE[2:0]),\n\t\t\t\t .CFG_MAX_PAYLOAD_SIZE\t(CFG_MAX_PAYLOAD_SIZE[2:0]),\n\t\t\t\t .CFG_INTERRUPT_MSIEN\t(CFG_INTERRUPT_MSIEN),\n\t\t\t\t .CFG_INTERRUPT_RDY\t\t(CFG_INTERRUPT_RDY),\n\t\t\t\t .RCB\t\t\t\t\t(RCB),\n\t\t\t\t .MAX_RC_CPLD\t\t\t(MAX_RC_CPLD[11:0]),\n\t\t\t\t .MAX_RC_CPLH\t\t\t(MAX_RC_CPLH[7:0]),\n\t\t\t\t .RX_ST_DATA\t\t\t(RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .RX_ST_EOP\t\t\t\t(RX_ST_EOP[0:0]),\n\t\t\t\t .RX_ST_VALID\t\t\t(RX_ST_VALID[0:0]),\n\t\t\t\t .RX_ST_SOP\t\t\t\t(RX_ST_SOP[0:0]),\n\t\t\t\t .RX_ST_EMPTY\t\t\t(RX_ST_EMPTY[0:0]),\n\t\t\t\t .TX_ST_READY\t\t\t(TX_ST_READY),\n\t\t\t\t .TL_CFG_CTL\t\t\t(TL_CFG_CTL[31:0]),\n\t\t\t\t .TL_CFG_ADD\t\t\t(TL_CFG_ADD[3:0]),\n\t\t\t\t .TL_CFG_STS\t\t\t(TL_CFG_STS[52:0]),\n\t\t\t\t .KO_CPL_SPC_HEADER\t\t(KO_CPL_SPC_HEADER[7:0]),\n\t\t\t\t .KO_CPL_SPC_DATA\t\t(KO_CPL_SPC_DATA[11:0]),\n\t\t\t\t .APP_MSI_ACK\t\t\t(APP_MSI_ACK),\n\t\t\t\t .RX_DATA_READY\t\t\t(RX_DATA_READY),\n\t\t\t\t .TX_DATA\t\t\t\t(TX_DATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .TX_DATA_BYTE_ENABLE\t(TX_DATA_BYTE_ENABLE[(C_PCI_DATA_WIDTH/8)-1:0]),\n\t\t\t\t .TX_TLP_END_FLAG\t\t(TX_TLP_END_FLAG),\n\t\t\t\t .TX_DATA_VALID\t\t\t(TX_DATA_VALID),\n\t\t\t\t .TX_TLP_ERROR_POISON\t(TX_TLP_ERROR_POISON),\n\t\t\t\t .INTR_MSI_REQUEST\t\t(INTR_MSI_REQUEST));\n\t\tend\n\t\telse if (C_PCI_DATA_WIDTH == 9'd64) begin : endpoint64\n\t\t\ttranslation_layer_64\n\t\t\t\t#(.C_ALTERA(C_ALTERA),\n\t\t\t\t .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),\n\t\t\t\t .C_TX_READY_LATENCY(C_TX_READY_LATENCY))\n\t\t\ttl64_inst\n\t\t\t\t(/*AUTOINST*/\n\t\t\t\t // Outputs\n\t\t\t\t .M_AXIS_RX_TREADY\t\t(M_AXIS_RX_TREADY),\n\t\t\t\t .S_AXIS_TX_TDATA\t\t(S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .S_AXIS_TX_TKEEP\t\t(S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),\n\t\t\t\t .S_AXIS_TX_TLAST\t\t(S_AXIS_TX_TLAST),\n\t\t\t\t .S_AXIS_TX_TVALID\t\t(S_AXIS_TX_TVALID),\n\t\t\t\t .S_AXIS_SRC_DSC\t\t(S_AXIS_SRC_DSC),\n\t\t\t\t .CFG_INTERRUPT\t\t\t(CFG_INTERRUPT),\n\t\t\t\t .RX_ST_READY\t\t\t(RX_ST_READY),\n\t\t\t\t .TX_ST_DATA\t\t\t(TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .TX_ST_VALID\t\t\t(TX_ST_VALID[0:0]),\n\t\t\t\t .TX_ST_EOP\t\t\t\t(TX_ST_EOP[0:0]),\n\t\t\t\t .TX_ST_SOP\t\t\t\t(TX_ST_SOP[0:0]),\n\t\t\t\t .TX_ST_EMPTY\t\t\t(TX_ST_EMPTY[0:0]),\n\t\t\t\t .APP_MSI_REQ\t\t\t(APP_MSI_REQ),\n\t\t\t\t .RX_DATA\t\t\t\t(RX_DATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .RX_DATA_VALID\t\t\t(RX_DATA_VALID),\n\t\t\t\t .RX_DATA_BYTE_ENABLE\t(RX_DATA_BYTE_ENABLE[(C_PCI_DATA_WIDTH/8)-1:0]),\n\t\t\t\t .RX_TLP_END_FLAG\t\t(RX_TLP_END_FLAG),\n\t\t\t\t .RX_TLP_END_OFFSET\t\t(RX_TLP_END_OFFSET[3:0]),\n\t\t\t\t .RX_TLP_START_FLAG\t\t(RX_TLP_START_FLAG),\n\t\t\t\t .RX_TLP_START_OFFSET\t(RX_TLP_START_OFFSET[3:0]),\n\t\t\t\t .RX_TLP_ERROR_POISON\t(RX_TLP_ERROR_POISON),\n\t\t\t\t .TX_DATA_READY\t\t\t(TX_DATA_READY),\n\t\t\t\t .CONFIG_COMPLETER_ID\t(CONFIG_COMPLETER_ID[15:0]),\n\t\t\t\t .CONFIG_BUS_MASTER_ENABLE(CONFIG_BUS_MASTER_ENABLE),\n\t\t\t\t .CONFIG_LINK_WIDTH\t\t(CONFIG_LINK_WIDTH[5:0]),\n\t\t\t\t .CONFIG_LINK_RATE\t\t(CONFIG_LINK_RATE[1:0]),\n\t\t\t\t .CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),\n\t\t\t\t .CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE[2:0]),\n\t\t\t\t .CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),\n\t\t\t\t .CONFIG_MAX_CPL_DATA\t(CONFIG_MAX_CPL_DATA[11:0]),\n\t\t\t\t .CONFIG_MAX_CPL_HDR\t(CONFIG_MAX_CPL_HDR[7:0]),\n\t\t\t\t .CONFIG_CPL_BOUNDARY_SEL(CONFIG_CPL_BOUNDARY_SEL),\n\t\t\t\t .INTR_MSI_RDY\t\t\t(INTR_MSI_RDY),\n\t\t\t\t // Inputs\n\t\t\t\t .CLK\t\t\t\t\t(CLK),\n\t\t\t\t .RST_IN\t\t\t\t(RST_IN),\n\t\t\t\t .M_AXIS_RX_TDATA\t\t(M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .M_AXIS_RX_TKEEP\t\t(M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),\n\t\t\t\t .M_AXIS_RX_TLAST\t\t(M_AXIS_RX_TLAST),\n\t\t\t\t .M_AXIS_RX_TVALID\t\t(M_AXIS_RX_TVALID),\n\t\t\t\t .IS_SOF\t\t\t\t(IS_SOF[(C_PCI_DATA_WIDTH/32):0]),\n\t\t\t\t .IS_EOF\t\t\t\t(IS_EOF[(C_PCI_DATA_WIDTH/32):0]),\n\t\t\t\t .RERR_FWD\t\t\t\t(RERR_FWD),\n\t\t\t\t .S_AXIS_TX_TREADY\t\t(S_AXIS_TX_TREADY),\n\t\t\t\t .COMPLETER_ID\t\t\t(COMPLETER_ID[15:0]),\n\t\t\t\t .CFG_BUS_MSTR_ENABLE\t(CFG_BUS_MSTR_ENABLE),\n\t\t\t\t .CFG_LINK_WIDTH\t\t(CFG_LINK_WIDTH[5:0]),\n\t\t\t\t .CFG_LINK_RATE\t\t\t(CFG_LINK_RATE[1:0]),\n\t\t\t\t .CFG_MAX_READ_REQUEST_SIZE(CFG_MAX_READ_REQUEST_SIZE[2:0]),\n\t\t\t\t .CFG_MAX_PAYLOAD_SIZE\t(CFG_MAX_PAYLOAD_SIZE[2:0]),\n\t\t\t\t .CFG_INTERRUPT_MSIEN\t(CFG_INTERRUPT_MSIEN),\n\t\t\t\t .CFG_INTERRUPT_RDY\t\t(CFG_INTERRUPT_RDY),\n\t\t\t\t .RCB\t\t\t\t\t(RCB),\n\t\t\t\t .MAX_RC_CPLD\t\t\t(MAX_RC_CPLD[11:0]),\n\t\t\t\t .MAX_RC_CPLH\t\t\t(MAX_RC_CPLH[7:0]),\n\t\t\t\t .RX_ST_DATA\t\t\t(RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .RX_ST_EOP\t\t\t\t(RX_ST_EOP[0:0]),\n\t\t\t\t .RX_ST_VALID\t\t\t(RX_ST_VALID[0:0]),\n\t\t\t\t .RX_ST_SOP\t\t\t\t(RX_ST_SOP[0:0]),\n\t\t\t\t .RX_ST_EMPTY\t\t\t(RX_ST_EMPTY[0:0]),\n\t\t\t\t .TX_ST_READY\t\t\t(TX_ST_READY),\n\t\t\t\t .TL_CFG_CTL\t\t\t(TL_CFG_CTL[31:0]),\n\t\t\t\t .TL_CFG_ADD\t\t\t(TL_CFG_ADD[3:0]),\n\t\t\t\t .TL_CFG_STS\t\t\t(TL_CFG_STS[52:0]),\n\t\t\t\t .KO_CPL_SPC_HEADER\t\t(KO_CPL_SPC_HEADER[7:0]),\n\t\t\t\t .KO_CPL_SPC_DATA\t\t(KO_CPL_SPC_DATA[11:0]),\n\t\t\t\t .APP_MSI_ACK\t\t\t(APP_MSI_ACK),\n\t\t\t\t .RX_DATA_READY\t\t\t(RX_DATA_READY),\n\t\t\t\t .TX_DATA\t\t\t\t(TX_DATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .TX_DATA_BYTE_ENABLE\t(TX_DATA_BYTE_ENABLE[(C_PCI_DATA_WIDTH/8)-1:0]),\n\t\t\t\t .TX_TLP_END_FLAG\t\t(TX_TLP_END_FLAG),\n\t\t\t\t .TX_TLP_START_FLAG\t\t(TX_TLP_START_FLAG),\n\t\t\t\t .TX_DATA_VALID\t\t\t(TX_DATA_VALID),\n\t\t\t\t .TX_TLP_ERROR_POISON\t(TX_TLP_ERROR_POISON),\n\t\t\t\t .INTR_MSI_REQUEST\t\t(INTR_MSI_REQUEST));\n\t\tend\n\t\telse if (C_PCI_DATA_WIDTH == 9'd128) begin : endpoint128\n\t\t\ttranslation_layer_128\n\t\t\t\t#(.C_ALTERA(C_ALTERA),\n\t\t\t\t .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),\n\t\t\t\t .C_TX_READY_LATENCY(C_TX_READY_LATENCY))\n\t\t\ttl128_inst\n\t\t\t\t(/*AUTOINST*/\n\t\t\t\t // Outputs\n\t\t\t\t .M_AXIS_RX_TREADY\t\t(M_AXIS_RX_TREADY),\n\t\t\t\t .S_AXIS_TX_TDATA\t\t(S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .S_AXIS_TX_TKEEP\t\t(S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),\n\t\t\t\t .S_AXIS_TX_TLAST\t\t(S_AXIS_TX_TLAST),\n\t\t\t\t .S_AXIS_TX_TVALID\t\t(S_AXIS_TX_TVALID),\n\t\t\t\t .S_AXIS_SRC_DSC\t\t(S_AXIS_SRC_DSC),\n\t\t\t\t .CFG_INTERRUPT\t\t\t(CFG_INTERRUPT),\n\t\t\t\t .RX_ST_READY\t\t\t(RX_ST_READY),\n\t\t\t\t .TX_ST_DATA\t\t\t(TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .TX_ST_VALID\t\t\t(TX_ST_VALID[0:0]),\n\t\t\t\t .TX_ST_EOP\t\t\t\t(TX_ST_EOP[0:0]),\n\t\t\t\t .TX_ST_SOP\t\t\t\t(TX_ST_SOP[0:0]),\n\t\t\t\t .TX_ST_EMPTY\t\t\t(TX_ST_EMPTY[0:0]),\n\t\t\t\t .APP_MSI_REQ\t\t\t(APP_MSI_REQ),\n\t\t\t\t .RX_DATA\t\t\t\t(RX_DATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .RX_DATA_VALID\t\t\t(RX_DATA_VALID),\n\t\t\t\t .RX_TLP_END_FLAG\t\t(RX_TLP_END_FLAG),\n\t\t\t\t .RX_TLP_END_OFFSET\t\t(RX_TLP_END_OFFSET[3:0]),\n\t\t\t\t .RX_TLP_START_FLAG\t\t(RX_TLP_START_FLAG),\n\t\t\t\t .RX_TLP_START_OFFSET\t(RX_TLP_START_OFFSET[3:0]),\n\t\t\t\t .RX_TLP_ERROR_POISON\t(RX_TLP_ERROR_POISON),\n\t\t\t\t .TX_DATA_READY\t\t\t(TX_DATA_READY),\n\t\t\t\t .CONFIG_COMPLETER_ID\t(CONFIG_COMPLETER_ID[15:0]),\n\t\t\t\t .CONFIG_BUS_MASTER_ENABLE(CONFIG_BUS_MASTER_ENABLE),\n\t\t\t\t .CONFIG_LINK_WIDTH\t\t(CONFIG_LINK_WIDTH[5:0]),\n\t\t\t\t .CONFIG_LINK_RATE\t\t(CONFIG_LINK_RATE[1:0]),\n\t\t\t\t .CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),\n\t\t\t\t .CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE[2:0]),\n\t\t\t\t .CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),\n\t\t\t\t .CONFIG_MAX_CPL_DATA\t(CONFIG_MAX_CPL_DATA[11:0]),\n\t\t\t\t .CONFIG_MAX_CPL_HDR\t(CONFIG_MAX_CPL_HDR[7:0]),\n\t\t\t\t .CONFIG_CPL_BOUNDARY_SEL(CONFIG_CPL_BOUNDARY_SEL),\n\t\t\t\t .INTR_MSI_RDY\t\t\t(INTR_MSI_RDY),\n\t\t\t\t // Inputs\n\t\t\t\t .CLK\t\t\t\t\t(CLK),\n\t\t\t\t .RST_IN\t\t\t\t(RST_IN),\n\t\t\t\t .M_AXIS_RX_TDATA\t\t(M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .M_AXIS_RX_TKEEP\t\t(M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),\n\t\t\t\t .M_AXIS_RX_TLAST\t\t(M_AXIS_RX_TLAST),\n\t\t\t\t .M_AXIS_RX_TVALID\t\t(M_AXIS_RX_TVALID),\n\t\t\t\t .IS_SOF\t\t\t\t(IS_SOF[(C_PCI_DATA_WIDTH/32):0]),\n\t\t\t\t .IS_EOF\t\t\t\t(IS_EOF[(C_PCI_DATA_WIDTH/32):0]),\n\t\t\t\t .RERR_FWD\t\t\t\t(RERR_FWD),\n\t\t\t\t .S_AXIS_TX_TREADY\t\t(S_AXIS_TX_TREADY),\n\t\t\t\t .COMPLETER_ID\t\t\t(COMPLETER_ID[15:0]),\n\t\t\t\t .CFG_BUS_MSTR_ENABLE\t(CFG_BUS_MSTR_ENABLE),\n\t\t\t\t .CFG_LINK_WIDTH\t\t(CFG_LINK_WIDTH[5:0]),\n\t\t\t\t .CFG_LINK_RATE\t\t\t(CFG_LINK_RATE[1:0]),\n\t\t\t\t .CFG_MAX_READ_REQUEST_SIZE(CFG_MAX_READ_REQUEST_SIZE[2:0]),\n\t\t\t\t .CFG_MAX_PAYLOAD_SIZE\t(CFG_MAX_PAYLOAD_SIZE[2:0]),\n\t\t\t\t .CFG_INTERRUPT_MSIEN\t(CFG_INTERRUPT_MSIEN),\n\t\t\t\t .CFG_INTERRUPT_RDY\t\t(CFG_INTERRUPT_RDY),\n\t\t\t\t .RCB\t\t\t\t\t(RCB),\n\t\t\t\t .MAX_RC_CPLD\t\t\t(MAX_RC_CPLD[11:0]),\n\t\t\t\t .MAX_RC_CPLH\t\t\t(MAX_RC_CPLH[7:0]),\n\t\t\t\t .RX_ST_DATA\t\t\t(RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .RX_ST_EOP\t\t\t\t(RX_ST_EOP[0:0]),\n\t\t\t\t .RX_ST_VALID\t\t\t(RX_ST_VALID[0:0]),\n\t\t\t\t .RX_ST_SOP\t\t\t\t(RX_ST_SOP[0:0]),\n\t\t\t\t .RX_ST_EMPTY\t\t\t(RX_ST_EMPTY[0:0]),\n\t\t\t\t .TX_ST_READY\t\t\t(TX_ST_READY),\n\t\t\t\t .TL_CFG_CTL\t\t\t(TL_CFG_CTL[31:0]),\n\t\t\t\t .TL_CFG_ADD\t\t\t(TL_CFG_ADD[3:0]),\n\t\t\t\t .TL_CFG_STS\t\t\t(TL_CFG_STS[52:0]),\n\t\t\t\t .KO_CPL_SPC_HEADER\t\t(KO_CPL_SPC_HEADER[7:0]),\n\t\t\t\t .KO_CPL_SPC_DATA\t\t(KO_CPL_SPC_DATA[11:0]),\n\t\t\t\t .APP_MSI_ACK\t\t\t(APP_MSI_ACK),\n\t\t\t\t .RX_DATA_READY\t\t\t(RX_DATA_READY),\n\t\t\t\t .TX_DATA\t\t\t\t(TX_DATA[C_PCI_DATA_WIDTH-1:0]),\n\t\t\t\t .TX_DATA_BYTE_ENABLE\t(TX_DATA_BYTE_ENABLE[(C_PCI_DATA_WIDTH/8)-1:0]),\n\t\t\t\t .TX_TLP_END_FLAG\t\t(TX_TLP_END_FLAG),\n\t\t\t\t .TX_TLP_START_FLAG\t\t(TX_TLP_START_FLAG),\n\t\t\t\t .TX_DATA_VALID\t\t\t(TX_DATA_VALID),\n\t\t\t\t .TX_TLP_ERROR_POISON\t(TX_TLP_ERROR_POISON),\n\t\t\t\t .INTR_MSI_REQUEST\t\t(INTR_MSI_REQUEST));\n\t\tend\n\tendgenerate\nendmodule // translation_layer\n\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/translation_layer_128.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n// //////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 19:27:32 05/15/2014 \n// Design Name: \n// Module Name: translation_layer_128\n// Project Name: \n// Target Devices: \n// Tool versions: \n// Description:\n// Translates AXI (Xilinx) or Avalon (Altera) signals into Unified (architecture\n// independent) streaming signals for riffa. The altera RX interface has a 1 cycle\n// latency because it needs to produce several metadata signals that are not \n// provided by the altera PCIe Core.\n//\n// Dependencies: None\n//\n// Revision: \n// Revision 0.01 - File Created\n// Additional Comments: \n//\n//////////////////////////////////////////////////////////////////////////////////\nmodule translation_layer_128\n #(\n parameter C_ALTERA = 1'b1,\n parameter C_PCI_DATA_WIDTH = 10'd128,\n parameter C_RX_READY_LATENCY = 3'd2,\n parameter C_TX_READY_LATENCY = 3'd2\n )\n (\t\n input CLK,\n\t input RST_IN,\n\n // Xilinx Signals\n\t input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,\n\t input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,\n\t input M_AXIS_RX_TLAST, // Not used in the 128 bit interface\n\t input M_AXIS_RX_TVALID,\n\t output M_AXIS_RX_TREADY,\n\t input [(C_PCI_DATA_WIDTH/32):0] IS_SOF,\n\t input [(C_PCI_DATA_WIDTH/32):0] IS_EOF,\n\t input RERR_FWD,\n \n\t output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,\n\t output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,\n\t output S_AXIS_TX_TLAST,\n\t output S_AXIS_TX_TVALID,\n\t output S_AXIS_SRC_DSC,\n\t input S_AXIS_TX_TREADY,\n \n\t input [15:0] COMPLETER_ID,\n\t input CFG_BUS_MSTR_ENABLE, \n\t input [5:0] CFG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=? \n\t input [1:0] CFG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?\n\t input [2:0] CFG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t input [2:0] CFG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B\n\n\t input CFG_INTERRUPT_MSIEN, // 1 if MSI interrupts are enable, 0 if only legacy are supported\n\t input CFG_INTERRUPT_RDY, // High when interrupt is able to be sent\n\t output CFG_INTERRUPT, // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high, interrupt is sent)\n\t\tinput \t\t\t\t RCB,\n\t\tinput [11:0] \t\t\t MAX_RC_CPLD, // Receive credit limit for data (be sure fc_sel == 001)\n\t\tinput [7:0] \t\t\t MAX_RC_CPLH, // Receive credit limit for headers (be sure fc_sel == 001)\n\n // Altera Signals\n input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,\n input [0:0] RX_ST_EOP,\n input [0:0] RX_ST_VALID,\n output RX_ST_READY,\n input [0:0] RX_ST_SOP,\n input [0:0] RX_ST_EMPTY,\n\n output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,\n output [0:0] TX_ST_VALID,\n input TX_ST_READY,\n output [0:0] TX_ST_EOP,\n output [0:0] TX_ST_SOP,\n\t\toutput [0:0] TX_ST_EMPTY,\n\n input [31:0] TL_CFG_CTL,\n input [3:0] TL_CFG_ADD,\n input [52:0] TL_CFG_STS,\n\n\t\tinput [7:0] \t\t\t KO_CPL_SPC_HEADER,\n\t\tinput [11:0] \t\t\t KO_CPL_SPC_DATA,\n input APP_MSI_ACK,\n output APP_MSI_REQ,\n\n // Unified Signals\n\t output [C_PCI_DATA_WIDTH-1:0] RX_DATA,\n\t output RX_DATA_VALID,\n input RX_DATA_READY,\n\n\t output RX_TLP_END_FLAG,\n\t output [3:0] RX_TLP_END_OFFSET,\n output RX_TLP_START_FLAG,\n\t output [3:0] RX_TLP_START_OFFSET,\n\t output RX_TLP_ERROR_POISON,\n \n\t input [C_PCI_DATA_WIDTH-1:0] TX_DATA,\n\t input [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,\n\t input TX_TLP_END_FLAG,\n input TX_TLP_START_FLAG,\n\t input TX_DATA_VALID,\n\t input TX_TLP_ERROR_POISON, \n\t output TX_DATA_READY,\n\n\t output [15:0] CONFIG_COMPLETER_ID,\n\t output CONFIG_BUS_MASTER_ENABLE, \n\t output [5:0] CONFIG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=? \n\t output [1:0] CONFIG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?\n\t output [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t output [2:0] CONFIG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B\n output CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported\n\t\toutput [11:0] \t\t\t CONFIG_MAX_CPL_DATA, // Receive credit limit for data\n\t\toutput [7:0] \t\t\t CONFIG_MAX_CPL_HDR, // Receive credit limit for headers\n\t\toutput \t\t\t\t CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 byt\n \n\t output INTR_MSI_RDY,\n\t input INTR_MSI_REQUEST\n );\n generate\n if(C_ALTERA == 1'b1) begin : altera_translator_128\n wire [2:0] wFMT; // Format field of the TLP Header\n wire [4:0] wType; // Type field of the TLP header \n wire [9:0] wLength; // Length field of the TLP Header\n wire wLenEven; // 1 if even number of TLP data words, else 0\n wire wQWA4DWH, wQWA3DWH;\n wire wMsgType;\n wire wEP;\n wire w3DWH;\n wire w4DWH;\n \n reg _r1CyTLP,r1CyTLP;\n reg _rEven4DWH, rEven4DWH;\n reg _rEven3DWH, rEven3DWH;\n reg _rEvenMsg, rEvenMsg;\n reg _rEP, rEP;\n reg _rMSG, rMSG/* synthesis noprune */;\n\n reg [3:0] rTlCfgAdd,_rTlCfgAdd;\n reg [31:0] rTlCfgCtl,_rTlCfgCtl;\n reg [52:0] rTlCfgSts,_rTlCfgSts;\n\n reg [15:0] rCfgCompleterId;\n reg rCfgBusMstrEnable;\n reg [2:0] rCfgMaxReadRequestSize;\n reg [2:0] rCfgMaxPayloadSize;\n reg rCfgInterruptMsienable;\n\t \t reg \t rReadCompletionBoundarySel;\n\n reg [1:0] _rTlpEndOffset_I, rTlpEndOffset_I;\n reg [1:0] _rTlpEndOffset_D, rTlpEndOffset_D;\n\n reg [127:0] rRxStData;\n reg rRxStValid;\n reg rRxStEop;\n reg rRxStSop;\n\n assign wEP = RX_ST_DATA[14];\n assign wLength = RX_ST_DATA[9:0];\n assign wType = RX_ST_DATA[28:24];\n assign wFMT = RX_ST_DATA[31:29];\n assign wQWA3DWH = ~RX_ST_DATA[66];\n assign wQWA4DWH = ~RX_ST_DATA[98];\n\n assign w4DWH = wFMT[0];\n assign w3DWH = ~wFMT[0];\n assign wLenEven = ~wLength[0];\n assign wMsgType = wType[4];\n\n // Pre-calculating TLP End offset\n always @(*) begin\n // We expect to recieve three different types of packets\n // 3 DWH Packets, 4 DWH Packets, and Messages (No address)\n _rEven4DWH = w4DWH & ((wQWA4DWH & wLenEven) | (~wQWA4DWH & ~wLenEven));\n _rEven3DWH = w3DWH & ((wQWA3DWH & wLenEven) | (~wQWA3DWH & ~wLenEven));\n _rEvenMsg = wMsgType & wLenEven;\n _rMSG = (RX_ST_SOP & RX_ST_DATA[28]) | (rMSG & ~RX_ST_EOP);\n _rEP = (wEP & RX_ST_SOP) | (rEP & ~RX_TLP_END_FLAG); \n _rTlpEndOffset_I = {1'b1, ((~wLenEven & w3DWH)| w4DWH)};\n _rTlpEndOffset_D = {~RX_ST_EMPTY,rEven4DWH|rEven3DWH|rEvenMsg};\n _r1CyTLP = RX_ST_SOP & RX_ST_EOP;\n\n _rTlCfgCtl = TL_CFG_CTL;\n _rTlCfgAdd = TL_CFG_ADD;\n _rTlCfgSts = TL_CFG_STS;\n end\n\n always @(posedge CLK) begin // Should be the same clock as pld_clk\n rTlCfgAdd <= _rTlCfgAdd;\n rTlCfgCtl <= _rTlCfgCtl;\n rTlCfgSts <= _rTlCfgSts;\n\n rEP <= _rEP;\n rTlpEndOffset_I <= _rTlpEndOffset_I;\n rTlpEndOffset_D <= _rTlpEndOffset_D;\n r1CyTLP <= _r1CyTLP;\n \n rRxStData <= RX_ST_DATA;\n rRxStValid <= RX_ST_VALID;\n rRxStEop <= RX_ST_EOP;\n rRxStSop <= RX_ST_SOP;\n \n\n rMSG <= _rMSG;\n \n if(RX_ST_SOP) begin\n rEven4DWH <= _rEven4DWH;\n rEven3DWH <= _rEven3DWH;\n rEvenMsg <= _rEvenMsg;\n end\n if(rTlCfgAdd == 4'h0) begin\n rCfgMaxReadRequestSize <= rTlCfgCtl[30:28];\n rCfgMaxPayloadSize <= rTlCfgCtl[23:21];\n end\n\t \n\t \tif(rTlCfgAdd == 4'h2) begin\n\t\t\t\trReadCompletionBoundarySel <= rTlCfgCtl[19];\n end\n if(rTlCfgAdd == 4'h3) begin\n rCfgBusMstrEnable <= rTlCfgCtl[10];\n end\n if(rTlCfgAdd == 4'hD) begin\n rCfgInterruptMsienable <= rTlCfgCtl[0];\n end\n if(rTlCfgAdd == 4'hF) begin\n rCfgCompleterId <= {rTlCfgCtl[12:0],3'b0};\n end\n end // always @ (posedge CLK)\n \n // Rx Interface (To PCIe Core)\n assign RX_ST_READY = RX_DATA_READY;\n\n // Rx Interface (From PCIe Core)\n assign RX_DATA = rRxStData;\n assign RX_DATA_VALID = rRxStValid;\n\n assign RX_TLP_END_FLAG = rRxStEop;\n assign RX_TLP_END_OFFSET = {r1CyTLP?rTlpEndOffset_I:rTlpEndOffset_D,2'b11};\n assign RX_TLP_START_FLAG = rRxStSop;\n assign RX_TLP_START_OFFSET = 4'h0000; \n assign RX_TLP_ERROR_POISON = rEP; \n\n // Configuration Interface\n assign CONFIG_COMPLETER_ID = rCfgCompleterId; \n assign CONFIG_BUS_MASTER_ENABLE = rCfgBusMstrEnable;\n assign CONFIG_LINK_WIDTH = rTlCfgSts[40:35]; \n assign CONFIG_LINK_RATE = rTlCfgSts[32:31];\n assign CONFIG_MAX_READ_REQUEST_SIZE = rCfgMaxReadRequestSize;\n assign CONFIG_MAX_PAYLOAD_SIZE = rCfgMaxPayloadSize;\n assign CONFIG_INTERRUPT_MSIENABLE = rCfgInterruptMsienable;\n\t assign CONFIG_CPL_BOUNDARY_SEL = rReadCompletionBoundarySel;\n\t assign CONFIG_MAX_CPL_HDR = KO_CPL_SPC_HEADER;\n\t assign CONFIG_MAX_CPL_DATA = KO_CPL_SPC_DATA;\n\n // Interrupt interface \n assign APP_MSI_REQ = INTR_MSI_REQUEST;\n assign INTR_MSI_RDY = APP_MSI_ACK; \n\n tx_qword_aligner_128\n #(\n .C_ALTERA(C_ALTERA),\n .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),\n .C_TX_READY_LATENCY(C_TX_READY_LATENCY)\n )\n aligner_inst\n (\n // Outputs\n .TX_DATA_READY (TX_DATA_READY),\n .TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),\n .TX_ST_VALID (TX_ST_VALID[0:0]),\n .TX_ST_EOP (TX_ST_EOP[0:0]),\n .TX_ST_SOP (TX_ST_SOP[0:0]),\n .TX_ST_EMPTY (TX_ST_EMPTY),\n // Inputs\n .CLK (CLK),\n .RST_IN (RST_IN),\n .TX_DATA (TX_DATA[C_PCI_DATA_WIDTH-1:0]),\n .TX_DATA_VALID (TX_DATA_VALID),\n .TX_TLP_END_FLAG (TX_TLP_END_FLAG),\n .TX_TLP_START_FLAG (TX_TLP_START_FLAG),\n .TX_ST_READY (TX_ST_READY)); \n\n\n end else begin : xilinx_translator_128\n // Rx Interface (From PCIe Core)\n assign RX_DATA = M_AXIS_RX_TDATA;\n assign RX_DATA_VALID = M_AXIS_RX_TVALID;\n\n assign RX_TLP_END_FLAG = IS_EOF[4]; // Also, M_AXIS_RX_TLAST\n assign RX_TLP_END_OFFSET = IS_EOF[3:0]; \n assign RX_TLP_START_FLAG = IS_SOF[4]; // Also, posedge M_AXIS_RX_TVALID or negedge M_AXIS_RX_TLAST and M_AXIS_RX_TVALID = 1\n assign RX_TLP_START_OFFSET = IS_SOF[3:0];\n assign RX_TLP_ERROR_POISON = RERR_FWD;\n // Rx Interface (To PCIe Core)\n assign M_AXIS_RX_TREADY = RX_DATA_READY;\n\n // TX Interface (From PCIe Core)\n assign TX_DATA_READY = S_AXIS_TX_TREADY;\n\n // TX Interface (TO PCIe Core)\n assign S_AXIS_TX_TDATA = TX_DATA;\n assign S_AXIS_TX_TVALID = TX_DATA_VALID;\n assign S_AXIS_TX_TKEEP = TX_DATA_BYTE_ENABLE;\n assign S_AXIS_TX_TLAST = TX_TLP_END_FLAG;\n assign S_AXIS_SRC_DSC = TX_TLP_ERROR_POISON;\n\n // Configuration Interface\n assign CONFIG_COMPLETER_ID = COMPLETER_ID;\n assign CONFIG_BUS_MASTER_ENABLE = CFG_BUS_MSTR_ENABLE;\n assign CONFIG_LINK_WIDTH = CFG_LINK_WIDTH;\n assign CONFIG_LINK_RATE = CFG_LINK_RATE;\n assign CONFIG_MAX_READ_REQUEST_SIZE = CFG_MAX_READ_REQUEST_SIZE;\n assign CONFIG_MAX_PAYLOAD_SIZE = CFG_MAX_PAYLOAD_SIZE;\n assign CONFIG_INTERRUPT_MSIENABLE = CFG_INTERRUPT_MSIEN;\n assign CONFIG_CPL_BOUNDARY_SEL = RCB;\n assign CONFIG_MAX_CPL_DATA = MAX_RC_CPLD;\n assign CONFIG_MAX_CPL_HDR = MAX_RC_CPLH;\n\n // Interrupt interface\n assign CFG_INTERRUPT = INTR_MSI_REQUEST;\n assign INTR_MSI_RDY = CFG_INTERRUPT_RDY;\n end\n endgenerate\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/translation_layer_32.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 19:27:32 05/15/2014 \n// Design Name: \n// Module Name: translation_layer_32\n// Project Name: \n// Target Devices: \n// Tool versions: \n// Description:\n// Translates AXI (Xilinx) signals into Unified (architecture\n// independent) streaming signals for riffa. \n//\n// Dependencies: None\n//\n// Revision: \n// Revision 0.01 - File Created\n// Additional Comments: \n//\n//////////////////////////////////////////////////////////////////////////////////\nmodule translation_layer_32\n #(parameter C_ALTERA = 1'b1,\n parameter C_PCI_DATA_WIDTH = 10'd32)\n (\t\n input CLK,\n\t input RST_IN,\n\n // Xilinx Signals\n\t input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,\n\t input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,\n\t input M_AXIS_RX_TLAST, // Not used in the 128 bit interface\n\t input M_AXIS_RX_TVALID,\n\t output M_AXIS_RX_TREADY,\n\t input [(C_PCI_DATA_WIDTH/32):0] IS_SOF,\n\t input [(C_PCI_DATA_WIDTH/32):0] IS_EOF,\n\t input RERR_FWD,\n \n\t output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,\n\t output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,\n\t output S_AXIS_TX_TLAST,\n\t output S_AXIS_TX_TVALID,\n\t output S_AXIS_SRC_DSC,\n\t input S_AXIS_TX_TREADY,\n \n\t input [15:0] COMPLETER_ID,\n\t input CFG_BUS_MSTR_ENABLE, \n\t input [5:0] CFG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=? \n\t input [1:0] CFG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?\n\t input [2:0] CFG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t input [2:0] CFG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B\n\n\t input CFG_INTERRUPT_MSIEN, // 1 if MSI interrupts are enable, 0 if only legacy are supported\n\t input CFG_INTERRUPT_RDY, // High when interrupt is able to be sent\n\t output CFG_INTERRUPT, // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high, interrupt is sent)\n\t\tinput \t\t\t\t RCB,\n\t\tinput [11:0] \t\t\t MAX_RC_CPLD, // Receive credit limit for data (be sure fc_sel == 001)\n\t\tinput [7:0] \t\t\t MAX_RC_CPLH, // Receive credit limit for headers (be sure fc_sel == 001)\n\n // Altera Signals\n input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,\n input [0:0] RX_ST_EOP,\n input [0:0] RX_ST_VALID,\n output RX_ST_READY,\n input [0:0] RX_ST_SOP,\n input [0:0] RX_ST_EMPTY,\n\n output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,\n output [0:0] TX_ST_VALID,\n input TX_ST_READY,\n output [0:0] TX_ST_EOP,\n output [0:0] TX_ST_SOP,\n\t\toutput [0:0] TX_ST_EMPTY,\n\n input [31:0] TL_CFG_CTL,\n input [3:0] TL_CFG_ADD,\n input [52:0] TL_CFG_STS,\n\n\t\tinput [7:0] \t\t\t KO_CPL_SPC_HEADER,\n\t\tinput [11:0] \t\t\t KO_CPL_SPC_DATA,\n input APP_MSI_ACK,\n output APP_MSI_REQ,\n\n // Unified Signals\n\t output [C_PCI_DATA_WIDTH-1:0] RX_DATA,\n\t output RX_DATA_VALID,\n input RX_DATA_READY,\n\t output [(C_PCI_DATA_WIDTH/8)-1:0] RX_DATA_BYTE_ENABLE,\n\n\t output RX_TLP_END_FLAG,\n\t output [3:0] RX_TLP_END_OFFSET,\n output RX_TLP_START_FLAG,\n\t output [3:0] RX_TLP_START_OFFSET,\n\t output RX_TLP_ERROR_POISON,\n \n\t input [C_PCI_DATA_WIDTH-1:0] TX_DATA,\n\t input [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,\n\t input TX_TLP_END_FLAG,\n\t input TX_DATA_VALID,\n\t input TX_TLP_ERROR_POISON, \n\t output TX_DATA_READY,\n\n\t output [15:0] CONFIG_COMPLETER_ID,\n\t output CONFIG_BUS_MASTER_ENABLE, \n\t output [5:0] CONFIG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=? \n\t output [1:0] CONFIG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?\n\t output [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t output [2:0] CONFIG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B\n output CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported\n\n\t\toutput [11:0] \t\t\t CONFIG_MAX_CPL_DATA, // Receive credit limit for data\n\t\toutput [7:0] \t\t\t CONFIG_MAX_CPL_HDR, // Receive credit limit for headers\n\t\toutput \t\t\t\t CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 byte\n\n\t output INTR_MSI_RDY, // High when interrupt is able to be sent\n\t input INTR_MSI_REQUEST // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high\n );\n generate\n if(C_ALTERA == 1'b1) begin : altera_translator_32\n // If you have reached here, something has gone\n // horrendously wrong. Altera does not have a 32-bit PCIE\n // interface. Please adapt your application and try again.\n\n end else begin : xilinx_translator_32\n // Rx Interface (From PCIe Core)\n assign RX_DATA = M_AXIS_RX_TDATA;\n assign RX_DATA_VALID = M_AXIS_RX_TVALID;\n assign RX_DATA_BYTE_ENABLE = M_AXIS_RX_TKEEP;\n assign RX_TLP_END_FLAG = M_AXIS_RX_TLAST;\n assign RX_TLP_END_OFFSET = M_AXIS_RX_TKEEP[3];\n assign RX_TLP_START_FLAG = 1'd0;\n assign RX_TLP_START_OFFSET = 4'h0;\n assign RX_TLP_ERROR_POISON = RERR_FWD;\n\n // Rx Interface (To PCIe Core)\n assign M_AXIS_RX_TREADY = RX_DATA_READY;\n\n // TX Interface (From PCIe Core)\n assign TX_DATA_READY = S_AXIS_TX_TREADY;\n\n // TX Interface (TO PCIe Core)\n assign S_AXIS_TX_TDATA = TX_DATA;\n assign S_AXIS_TX_TVALID = TX_DATA_VALID;\n assign S_AXIS_TX_TKEEP = TX_DATA_BYTE_ENABLE;\n assign S_AXIS_TX_TLAST = TX_TLP_END_FLAG;\n assign S_AXIS_SRC_DSC = TX_TLP_ERROR_POISON;\n\n // Configuration Interface\n assign CONFIG_COMPLETER_ID = COMPLETER_ID;\n assign CONFIG_BUS_MASTER_ENABLE = CFG_BUS_MSTR_ENABLE;\n assign CONFIG_LINK_WIDTH = CFG_LINK_WIDTH;\n assign CONFIG_LINK_RATE = CFG_LINK_RATE;\n assign CONFIG_MAX_READ_REQUEST_SIZE = CFG_MAX_READ_REQUEST_SIZE;\n assign CONFIG_MAX_PAYLOAD_SIZE = CFG_MAX_PAYLOAD_SIZE;\n assign CONFIG_INTERRUPT_MSIENABLE = CFG_INTERRUPT_MSIEN;\n\t \t assign CONFIG_CPL_BOUNDARY_SEL = RCB;\n\t \t assign CONFIG_MAX_CPL_DATA = MAX_RC_CPLD;\n\t \t assign CONFIG_MAX_CPL_HDR = MAX_RC_CPLH;\n\n // Interrupt interface\n assign CFG_INTERRUPT = INTR_MSI_REQUEST;\n assign INTR_MSI_RDY = CFG_INTERRUPT_RDY;\n end\n endgenerate\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/translation_layer_64.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 19:27:32 05/15/2014 \n// Design Name: \n// Module Name: translation_layer_64\n// Project Name: \n// Target Devices: \n// Tool versions: \n// Description:\n// Translates AXI (Xilinx) or Avalon (Altera) signals into Unified (architecture\n// independent) streaming signals for riffa. The altera RX interface has a 1 cycle\n// latency because it needs to produce several metadata signals that are not \n// provided by the altera PCIe Core.\n//\n// Dependencies: None\n//\n// Revision: \n// Revision 0.01 - File Created\n// Additional Comments: \n//\n//////////////////////////////////////////////////////////////////////////////////\nmodule translation_layer_64\n #(parameter C_ALTERA = 1'b1,\n parameter C_PCI_DATA_WIDTH = 10'd64,\n parameter C_RX_READY_LATENCY = 3'd2,\n parameter C_TX_READY_LATENCY = 3'd2)\n (\t\n input CLK,\n\t input RST_IN,\n\n // Xilinx Signals\n\t input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,\n\t input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,\n\t input M_AXIS_RX_TLAST, // Not used in the 128 bit interface\n\t input M_AXIS_RX_TVALID,\n\t output M_AXIS_RX_TREADY,\n\t input [(C_PCI_DATA_WIDTH/32):0] IS_SOF,\n\t input [(C_PCI_DATA_WIDTH/32):0] IS_EOF,\n\t input RERR_FWD,\n \n\t output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,\n\t output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,\n\t output S_AXIS_TX_TLAST,\n\t output S_AXIS_TX_TVALID,\n\t output S_AXIS_SRC_DSC,\n\t input S_AXIS_TX_TREADY,\n \n\t input [15:0] COMPLETER_ID,\n\t input CFG_BUS_MSTR_ENABLE, \n\t input [5:0] CFG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=? \n\t input [1:0] CFG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?\n\t input [2:0] CFG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t input [2:0] CFG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B\n\n\t input CFG_INTERRUPT_MSIEN, // 1 if MSI interrupts are enable, 0 if only legacy are supported\n\t input CFG_INTERRUPT_RDY, // High when interrupt is able to be sent\n\t output CFG_INTERRUPT, // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high, interrupt is sent)\n\t\tinput \t\t\t\t RCB,\n\t\tinput [11:0] \t\t\t MAX_RC_CPLD, // Receive credit limit for data (be sure fc_sel == 001)\n\t\tinput [7:0] \t\t\t MAX_RC_CPLH, // Receive credit limit for headers (be sure fc_sel == 001)\n\n // Altera Signals\n input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,\n input [0:0] RX_ST_EOP,\n input [0:0] RX_ST_VALID,\n output RX_ST_READY,\n input [0:0] RX_ST_SOP,\n input [0:0] RX_ST_EMPTY,\n\n output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,\n output [0:0] TX_ST_VALID,\n input TX_ST_READY,\n output [0:0] TX_ST_EOP,\n output [0:0] TX_ST_SOP,\n\t\toutput [0:0] TX_ST_EMPTY, // NC\n \n input [31:0] TL_CFG_CTL,\n input [3:0] TL_CFG_ADD,\n input [52:0] TL_CFG_STS,\n\n\t\tinput [7:0] \t\t\t KO_CPL_SPC_HEADER,\n\t\tinput [11:0] \t\t\t KO_CPL_SPC_DATA,\n input APP_MSI_ACK,\n output APP_MSI_REQ,\n\n // Unified Signals\n\t output [C_PCI_DATA_WIDTH-1:0] RX_DATA,\n\t output RX_DATA_VALID,\n input RX_DATA_READY,\n\t output [(C_PCI_DATA_WIDTH/8)-1:0] RX_DATA_BYTE_ENABLE,\n\n\t output RX_TLP_END_FLAG,\n\t output [3:0] RX_TLP_END_OFFSET,\n output RX_TLP_START_FLAG,\n\t output [3:0] RX_TLP_START_OFFSET,\n\t output RX_TLP_ERROR_POISON,\n \n\t input [C_PCI_DATA_WIDTH-1:0] TX_DATA,\n\t input [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,\n\t input TX_TLP_END_FLAG,\n input TX_TLP_START_FLAG,\n\t input TX_DATA_VALID,\n\t input TX_TLP_ERROR_POISON, \n\t output TX_DATA_READY,\n\n\t output [15:0] CONFIG_COMPLETER_ID,\n\t output CONFIG_BUS_MASTER_ENABLE, \n\t output [5:0] CONFIG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=? \n\t output [1:0] CONFIG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?\n\t output [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B\n\t output [2:0] CONFIG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B\n output CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported\n\t\toutput [11:0] \t\t\t CONFIG_MAX_CPL_DATA, // Receive credit limit for data\n\t\toutput [7:0] \t\t\t CONFIG_MAX_CPL_HDR, // Receive credit limit for headers\n\t\toutput \t\t\t\t CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 byt\n\t\n\t output INTR_MSI_RDY, // High when interrupt is able to be sent\n\t input INTR_MSI_REQUEST // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high\n );\n generate\n if(C_ALTERA == 1'b1) begin : altera_translator_64\n wire wEP;\n wire [9:0] wLength; // Length field of the TLP Header\n wire [4:0] wType; // Type field of the TLP header \n wire [3:0] wFMT; // Format field of the TLP Header\n wire w4DWH;\n wire w3DWH;\n\n wire wLenEven; // 1 if even number of TLP data words, else 0\n wire wMsg;\n\n wire [64:0] wAddr3DWH;\n wire [64:0] wAddr4DWH;\n wire wQWA4DWH;\n wire wQWA3DWH;\n\n\n /// Configuration signals\n reg [15:0] rCfgCompleterId;\n reg rCfgBusMstrEnable;\n reg [2:0] rCfgMaxReadRequestSize;\n reg [2:0] rCfgMaxPayloadSize;\n reg rCfgInterruptMsienable;\n\t \t reg \t rReadCompletionBoundarySel;\n\n reg [3:0] rTlCfgAdd,_rTlCfgAdd;\n reg [31:0] rTlCfgCtl,_rTlCfgCtl;\n reg [52:0] rTlCfgSts,_rTlCfgSts;\n \n reg [63:0] rRxStData;\n reg rRxStValid;\n reg rRxStEop;\n reg rRxStSop;\n\n reg rEP, _rEP;\n reg rLenEven,_rLenEven;\n reg rMsg,_rMsg;\n reg r3DWH,_r3DWH;\n reg r4DWH,_r4DWH;\n\n reg rTlpEndOffset, _rTlpEndOffset;\n \n // Valid when RX_ST_SOP & RX_ST_VALID\n assign wEP = RX_ST_DATA[14];\n assign wLength = RX_ST_DATA[9:0];\n assign wType = RX_ST_DATA[28:24];\n assign wFMT = RX_ST_DATA[31:29];\n assign w4DWH = wFMT[0];\n assign w3DWH = ~wFMT[0];\n \n assign wLenEven = ~wLength[0];\n assign wMsg = wType[4];\n\n // Valid when rRxStSop & RX_ST_VALID\n assign wAddr3DWH = {32'd0,RX_ST_DATA[31:0]};\n assign wAddr4DWH = {RX_ST_DATA[31:0],RX_ST_DATA[63:32]};\n\n assign wQWA3DWH = ~wAddr3DWH[2];\n assign wQWA4DWH = ~wAddr4DWH[2];\n \n always @(*) begin\n // We expect to recieve three different types of packets\n // 3 DWH Packets, 4 DWH Packets, and Messages (No address)\n _rEP = wEP;\n _rLenEven = wLenEven;\n _rMsg = wMsg;\n _r3DWH = w3DWH;\n _r4DWH = w4DWH;\n \n // If the whole TLP is of even length, then the end will be at\n // offset byte 7, otherwise the end will be at byte offset 3\n _rTlpEndOffset = ( rMsg & rLenEven) | \n (~rMsg & (( rLenEven & r3DWH & wQWA3DWH)|\n (~rLenEven & r3DWH & ~wQWA3DWH)|\n ( rLenEven & r4DWH & wQWA4DWH)| \n (~rLenEven & r4DWH & ~wQWA4DWH)));\n\n _rTlCfgCtl = TL_CFG_CTL;\n _rTlCfgAdd = TL_CFG_ADD;\n _rTlCfgSts = TL_CFG_STS;\n end\n\n always @(posedge CLK) begin // Should be the same clock as pld_clk\n rTlCfgAdd <= _rTlCfgAdd;\n rTlCfgCtl <= _rTlCfgCtl;\n rTlCfgSts <= _rTlCfgSts;\n \n rRxStData <= RX_ST_DATA;\n rRxStValid <= RX_ST_VALID;\n\n if(RX_ST_VALID) begin\n rRxStEop <= RX_ST_EOP;\n rRxStSop <= RX_ST_SOP;\n end\n\n if(rRxStSop) begin\n rTlpEndOffset <= _rTlpEndOffset;\n end\n\n if(RX_ST_SOP & RX_ST_VALID) begin\n rEP <= _rEP;\n rLenEven <= _rLenEven;\n rMsg <= _rMsg;\n r3DWH <= _r3DWH;\n r4DWH <= _r4DWH;\n end\n \n if(rTlCfgAdd == 4'h0) begin\n rCfgMaxReadRequestSize <= rTlCfgCtl[30:28];\n rCfgMaxPayloadSize <= rTlCfgCtl[23:21];\n end\n\n\t \tif(rTlCfgAdd == 4'h2) begin\n\t\t\t\trReadCompletionBoundarySel <= rTlCfgCtl[19];\n end\n\n if(rTlCfgAdd == 4'h3) begin\n rCfgBusMstrEnable <= rTlCfgCtl[10];\n end\n if(rTlCfgAdd == 4'hD) begin\n rCfgInterruptMsienable <= rTlCfgCtl[0];\n end\n if(rTlCfgAdd == 4'hF) begin\n rCfgCompleterId <= {rTlCfgCtl[12:0],3'b0};\n end\n end // always @ (posedge CLK)\n \n // Rx Interface (To PCIe Core)\n assign RX_ST_READY = RX_DATA_READY;\n\n // Rx Interface (From PCIe Core)\n assign RX_DATA = rRxStData;\n assign RX_DATA_VALID = rRxStValid;\n\n assign RX_DATA_BYTE_ENABLE = {{4{rTlpEndOffset}},4'hF};\n assign RX_TLP_END_FLAG = rRxStEop;\n assign RX_TLP_END_OFFSET = {rTlpEndOffset,2'b11};\n assign RX_TLP_START_FLAG = rRxStSop;\n assign RX_TLP_START_OFFSET = 4'h0;\n assign RX_TLP_ERROR_POISON = rEP;\n\n // Configuration Interface\n assign CONFIG_COMPLETER_ID = rCfgCompleterId; \n assign CONFIG_BUS_MASTER_ENABLE = rCfgBusMstrEnable;\n assign CONFIG_LINK_WIDTH = rTlCfgSts[40:35]; \n assign CONFIG_LINK_RATE = rTlCfgSts[32:31];\n assign CONFIG_MAX_READ_REQUEST_SIZE = rCfgMaxReadRequestSize;\n assign CONFIG_MAX_PAYLOAD_SIZE = rCfgMaxPayloadSize;\n assign CONFIG_INTERRUPT_MSIENABLE = rCfgInterruptMsienable;\n\t \t assign CONFIG_CPL_BOUNDARY_SEL = rReadCompletionBoundarySel;\n\t \t assign CONFIG_MAX_CPL_HDR = KO_CPL_SPC_HEADER;\n\t \t assign CONFIG_MAX_CPL_DATA = KO_CPL_SPC_DATA;\n\n // Interrupt interface \n assign APP_MSI_REQ = INTR_MSI_REQUEST;\n assign INTR_MSI_RDY = APP_MSI_ACK; \n\n tx_qword_aligner_64\n #(\n .C_ALTERA(C_ALTERA),\n .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),\n .C_TX_READY_LATENCY(C_TX_READY_LATENCY)\n )\n aligner_inst\n (\n // Outputs\n .TX_DATA_READY (TX_DATA_READY),\n .TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),\n .TX_ST_VALID (TX_ST_VALID[0:0]),\n .TX_ST_EOP (TX_ST_EOP[0:0]),\n .TX_ST_SOP (TX_ST_SOP[0:0]),\n .TX_ST_EMPTY (TX_ST_EMPTY), \n // Inputs\n .CLK (CLK),\n .RST_IN (RST_IN),\n .TX_DATA (TX_DATA[C_PCI_DATA_WIDTH-1:0]),\n .TX_DATA_VALID (TX_DATA_VALID),\n .TX_TLP_END_FLAG (TX_TLP_END_FLAG),\n .TX_TLP_START_FLAG (TX_TLP_START_FLAG),\n .TX_ST_READY (TX_ST_READY));\n\n end else begin : xilinx_translator_64\n // Rx Interface (From PCIe Core)\n assign RX_DATA = M_AXIS_RX_TDATA;\n assign RX_DATA_VALID = M_AXIS_RX_TVALID;\n assign RX_DATA_BYTE_ENABLE = M_AXIS_RX_TKEEP;\n assign RX_TLP_END_FLAG = M_AXIS_RX_TLAST;\n assign RX_TLP_END_OFFSET = {3'b000,M_AXIS_RX_TKEEP[4]};\n assign RX_TLP_START_FLAG = 1'd0;\n assign RX_TLP_START_OFFSET = 4'h0;\n assign RX_TLP_ERROR_POISON = RERR_FWD;\n \n // Rx Interface (To PCIe Core)\n assign M_AXIS_RX_TREADY = RX_DATA_READY;\n\n // TX Interface (From PCIe Core)\n assign TX_DATA_READY = S_AXIS_TX_TREADY;\n\n // TX Interface (TO PCIe Core)\n assign S_AXIS_TX_TDATA = TX_DATA;\n assign S_AXIS_TX_TVALID = TX_DATA_VALID;\n assign S_AXIS_TX_TKEEP = TX_DATA_BYTE_ENABLE;\n assign S_AXIS_TX_TLAST = TX_TLP_END_FLAG;\n assign S_AXIS_SRC_DSC = TX_TLP_ERROR_POISON;\n\n // Configuration Interface\n assign CONFIG_COMPLETER_ID = COMPLETER_ID;\n assign CONFIG_BUS_MASTER_ENABLE = CFG_BUS_MSTR_ENABLE;\n assign CONFIG_LINK_WIDTH = CFG_LINK_WIDTH;\n assign CONFIG_LINK_RATE = CFG_LINK_RATE;\n assign CONFIG_MAX_READ_REQUEST_SIZE = CFG_MAX_READ_REQUEST_SIZE;\n assign CONFIG_MAX_PAYLOAD_SIZE = CFG_MAX_PAYLOAD_SIZE;\n assign CONFIG_INTERRUPT_MSIENABLE = CFG_INTERRUPT_MSIEN;\n\t \t assign CONFIG_CPL_BOUNDARY_SEL = RCB;\n\t \t assign CONFIG_MAX_CPL_DATA = MAX_RC_CPLD;\n\t \t assign CONFIG_MAX_CPL_HDR = MAX_RC_CPLH;\n\n // Interrupt interface\n assign CFG_INTERRUPT = INTR_MSI_REQUEST;\n assign INTR_MSI_RDY = CFG_INTERRUPT_RDY;\n end\n endgenerate\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_128.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_engine_128.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tTransmit engine for PCIe using AXI interface from Xilinx \n// PCIe Endpoint core.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: Very good PCIe header reference:\n// http://www.pzk-agro.com/0321156307_ch04lev1sec5.html#ch04lev4sec14\n//-----------------------------------------------------------------------------\n\nmodule tx_engine_128 #(\n\tparameter C_PCI_DATA_WIDTH = 9'd128,\n\tparameter C_NUM_CHNL = 4'd12,\n\tparameter C_TAG_WIDTH = 5, \t\t\t\t\t\t\t// Number of outstanding requests \n\tparameter C_ALTERA = 1'b1,\t\t\t\t\t\t\t// 1 if Altera, 0 if Xilinx\n\t// Local parameters\n\tparameter C_FIFO_DEPTH = 512,\n\tparameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [15:0] CONFIG_COMPLETER_ID,\n\tinput [2:0] CONFIG_MAX_PAYLOAD_SIZE,\t\t\t\t// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B\n\n\toutput [C_PCI_DATA_WIDTH-1:0] TX_DATA,\t\t\t\t// AXI data output \n\toutput [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,\t// AXI data keep\n\toutput TX_TLP_END_FLAG,\t\t\t\t\t\t\t\t// AXI data last\n output TX_TLP_START_FLAG, // AXI data start\n\toutput TX_DATA_VALID,\t\t\t\t\t\t\t\t// AXI data valid\n\toutput S_AXIS_SRC_DSC,\t\t\t\t\t\t\t\t// AXI data discontinue\n\tinput TX_DATA_READY,\t\t\t\t\t\t\t\t// AXI ready for data\n\n\tinput [C_NUM_CHNL-1:0] WR_REQ,\t\t\t\t\t\t// Write request\n\tinput [(C_NUM_CHNL*64)-1:0] WR_ADDR,\t\t\t\t// Write address\n\tinput [(C_NUM_CHNL*10)-1:0] WR_LEN,\t\t\t\t\t// Write data length\n\tinput [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA,\t// Write data\n\toutput [C_NUM_CHNL-1:0] WR_DATA_REN,\t\t\t\t// Write data read enable\n\toutput [C_NUM_CHNL-1:0] WR_ACK,\t\t\t\t\t\t// Write request has been accepted\n\toutput [C_NUM_CHNL-1:0] WR_SENT, \t\t\t\t\t// Pulsed at channel pos when write request sent\n\n\tinput [C_NUM_CHNL-1:0] RD_REQ,\t\t\t\t\t\t// Read request\n\tinput [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL,\t\t\t\t// Read request channel for scatter gather lists\n\tinput [(C_NUM_CHNL*64)-1:0] RD_ADDR,\t\t\t\t// Read request address\n\tinput [(C_NUM_CHNL*10)-1:0] RD_LEN,\t\t\t\t\t// Read request length\n\toutput [C_NUM_CHNL-1:0] RD_ACK,\t\t\t\t\t\t// Read request has been accepted\n\t\n\toutput [5:0] INT_TAG,\t\t\t\t\t\t\t\t// Internal tag to exchange with external\n\toutput INT_TAG_VALID,\t\t\t\t\t\t\t\t// High to signal tag exchange \n\tinput [C_TAG_WIDTH-1:0] EXT_TAG,\t\t\t\t\t// External tag to provide in exchange for internal tag\n\tinput EXT_TAG_VALID,\t\t\t\t\t\t\t\t// High to signal external tag is valid\n\n output \t\t\t\t TX_ENG_RD_REQ_SENT, // Read completion request issued\n input \t\t\t\t RXBUF_SPACE_AVAIL,\n\t\n\tinput COMPL_REQ,\t\t\t\t\t\t\t\t\t// RX Engine request for completion\n\toutput COMPL_DONE,\t\t\t\t\t\t\t\t\t// Completion done\n\tinput [2:0] REQ_TC,\n\tinput REQ_TD,\n\tinput REQ_EP,\n\tinput [1:0] REQ_ATTR,\n\tinput [9:0] REQ_LEN,\n\tinput [15:0] REQ_ID,\n\tinput [7:0] REQ_TAG,\n\tinput [3:0] REQ_BE,\n\tinput [29:0] REQ_ADDR,\n\tinput [31:0] REQ_DATA,\n\toutput [31:0] REQ_DATA_SENT\t\t\t\t\t\t\t// Actual completion data sent\n);\n\n`include \"common_functions.v\"\n\nwire \t[C_PCI_DATA_WIDTH-1:0]\t\twFifoWrData;\nwire \t[C_PCI_DATA_WIDTH-1:0]\t\twFifoRdData;\nwire\t[C_FIFO_DEPTH_WIDTH-1:0]\twFifoCount;\nwire\t\t\t\t\t\t\t\twFifoEmpty;\nwire\t\t\t\t\t\t\t\twFifoRen;\nwire\t\t\t\t\t\t\t\twFifoWen;\nwire\t\t\t\t\t\t\t\twAltera = C_ALTERA;\n\n// Convert the read and write requests into PCI packet format and mux\n// them together into a FIFO.\ntx_engine_upper_128 #(\n .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), \n .C_NUM_CHNL(C_NUM_CHNL), \n .C_FIFO_DEPTH(C_FIFO_DEPTH), \n .C_TAG_WIDTH(C_TAG_WIDTH),\n .C_ALTERA(C_ALTERA)\n) upper (\n\t.RST(RST),\n\t.CLK(CLK),\n\t.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),\n\t.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),\n\t.WR_REQ(WR_REQ),\n\t.WR_ADDR(WR_ADDR),\n\t.WR_LEN(WR_LEN),\n\t.WR_DATA(WR_DATA),\n\t.WR_DATA_REN(WR_DATA_REN),\n\t.WR_ACK(WR_ACK),\n\t.RD_REQ(RD_REQ),\n\t.RD_SG_CHNL(RD_SG_CHNL),\n\t.RD_ADDR(RD_ADDR),\n\t.RD_LEN(RD_LEN),\n\t.RD_ACK(RD_ACK),\n .TX_ENG_RD_REQ_SENT(TX_ENG_RD_REQ_SENT),\n .RXBUF_SPACE_AVAIL(RXBUF_SPACE_AVAIL | !wAltera),\n\t.INT_TAG(INT_TAG),\n\t.INT_TAG_VALID(INT_TAG_VALID),\n\t.EXT_TAG(EXT_TAG),\n\t.EXT_TAG_VALID(EXT_TAG_VALID),\n\t.FIFO_DATA(wFifoWrData),\n\t.FIFO_COUNT(wFifoCount),\n\t.FIFO_WEN(wFifoWen)\n);\n\n\n// FIFO for storing outbound read/write requests.\n(* RAM_STYLE=\"BLOCK\" *)\nsync_fifo #(.C_WIDTH(C_PCI_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (\n\t.RST(RST),\n\t.CLK(CLK),\n\t.WR_EN(wFifoWen),\n\t.WR_DATA(wFifoWrData),\n\t.FULL(),\n\t.COUNT(wFifoCount),\n\t.RD_EN(wFifoRen),\n\t.RD_DATA(wFifoRdData),\n\t.EMPTY(wFifoEmpty)\n);\n\n\n// Process the formatted PCI packets in the FIFO and completions.\n// Completions take top priority. Mux the data into the AXI interface\n// for the PCIe Endpoint.\ntx_engine_lower_128 #(\n .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), \n .C_NUM_CHNL(C_NUM_CHNL),\n .C_ALTERA(C_ALTERA)\n) lower (\n\t.RST(RST),\n\t.CLK(CLK),\n\t.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),\n\t.TX_DATA(TX_DATA),\n\t.TX_DATA_BYTE_ENABLE(TX_DATA_BYTE_ENABLE),\n\t.TX_TLP_END_FLAG(TX_TLP_END_FLAG),\n .TX_TLP_START_FLAG(TX_TLP_START_FLAG),\n\t.TX_DATA_VALID(TX_DATA_VALID),\n\t.S_AXIS_SRC_DSC(S_AXIS_SRC_DSC),\n\t.TX_DATA_READY(TX_DATA_READY),\n\t.COMPL_REQ(COMPL_REQ),\n\t.COMPL_DONE(COMPL_DONE),\n\t.REQ_TC(REQ_TC),\n\t.REQ_TD(REQ_TD),\n\t.REQ_EP(REQ_EP),\n\t.REQ_ATTR(REQ_ATTR),\n\t.REQ_LEN(REQ_LEN),\n\t.REQ_ID(REQ_ID),\n\t.REQ_TAG(REQ_TAG),\n\t.REQ_BE(REQ_BE),\n\t.REQ_ADDR(REQ_ADDR),\n\t.REQ_DATA(REQ_DATA),\n\t.REQ_DATA_SENT(REQ_DATA_SENT),\n\t.FIFO_DATA(wFifoRdData),\n\t.FIFO_EMPTY(wFifoEmpty),\n\t.FIFO_REN(wFifoRen),\n\t.WR_SENT(WR_SENT)\n);\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_32.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_engine_32.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tTransmit engine for PCIe using AXI interface from Xilinx \n// PCIe Endpoint core.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: Very good PCIe header reference:\n// http://www.pzk-agro.com/0321156307_ch04lev1sec5.html#ch04lev4sec14\n//-----------------------------------------------------------------------------\n\nmodule tx_engine_32 #(\n\tparameter C_PCI_DATA_WIDTH = 9'd32,\n\tparameter C_NUM_CHNL = 4'd12,\n\tparameter C_TAG_WIDTH = 5, \t\t\t\t\t\t\t// Number of outstanding requests \n parameter C_ALTERA = 1'b1,\t\t\t\t// 1 if Altera, 0 if Xilinx\n\t// Local parameters\n\tparameter C_FIFO_DEPTH = 512,\n\tparameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [15:0] CONFIG_COMPLETER_ID,\n\tinput [2:0] CONFIG_MAX_PAYLOAD_SIZE,\t\t\t\t// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B\n\n\toutput [C_PCI_DATA_WIDTH-1:0] TX_DATA,\t\t\t\t// AXI data output \n\toutput [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,\t// AXI data keep\n\toutput TX_TLP_END_FLAG,\t\t\t\t\t\t\t\t// AXI data last\n output TX_TLP_START_FLAG, // AXI data first\n\toutput TX_DATA_VALID,\t\t\t\t\t\t\t\t// AXI data valid\n\toutput S_AXIS_SRC_DSC,\t\t\t\t\t\t\t\t// AXI data discontinue\n\tinput TX_DATA_READY,\t\t\t\t\t\t\t\t// AXI ready for data\n\n\tinput [C_NUM_CHNL-1:0] WR_REQ,\t\t\t\t\t\t// Write request\n\tinput [(C_NUM_CHNL*64)-1:0] WR_ADDR,\t\t\t\t// Write address\n\tinput [(C_NUM_CHNL*10)-1:0] WR_LEN,\t\t\t\t\t// Write data length\n\tinput [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA,\t// Write data\n\toutput [C_NUM_CHNL-1:0] WR_DATA_REN,\t\t\t\t// Write data read enable\n\toutput [C_NUM_CHNL-1:0] WR_ACK,\t\t\t\t\t\t// Write request has been accepted\n\toutput [C_NUM_CHNL-1:0] WR_SENT, \t\t\t\t\t// Pulsed at channel pos when write request sent\n\n\tinput [C_NUM_CHNL-1:0] RD_REQ,\t\t\t\t\t\t// Read request\n\tinput [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL,\t\t\t\t// Read request channel for scatter gather lists\n\tinput [(C_NUM_CHNL*64)-1:0] RD_ADDR,\t\t\t\t// Read request address\n\tinput [(C_NUM_CHNL*10)-1:0] RD_LEN,\t\t\t\t\t// Read request length\n\toutput [C_NUM_CHNL-1:0] RD_ACK,\t\t\t\t\t\t// Read request has been accepted\n\t\n\toutput [5:0] INT_TAG,\t\t\t\t\t\t\t\t// Internal tag to exchange with external\n\toutput INT_TAG_VALID,\t\t\t\t\t\t\t\t// High to signal tag exchange \n\tinput [C_TAG_WIDTH-1:0] EXT_TAG,\t\t\t\t\t// External tag to provide in exchange for internal tag\n\tinput EXT_TAG_VALID,\t\t\t\t\t\t\t\t// High to signal external tag is valid\n\n output \t\t\t\t TX_ENG_RD_REQ_SENT, // Read completion request issued\n input \t\t\t\t RXBUF_SPACE_AVAIL,\n\t\n\tinput COMPL_REQ,\t\t\t\t\t\t\t\t\t// RX Engine request for completion\n\toutput COMPL_DONE,\t\t\t\t\t\t\t\t\t// Completion done\n\tinput [2:0] REQ_TC,\n\tinput REQ_TD,\n\tinput REQ_EP,\n\tinput [1:0] REQ_ATTR,\n\tinput [9:0] REQ_LEN,\n\tinput [15:0] REQ_ID,\n\tinput [7:0] REQ_TAG,\n\tinput [3:0] REQ_BE,\n\tinput [29:0] REQ_ADDR,\n\tinput [31:0] REQ_DATA,\n\toutput [31:0] REQ_DATA_SENT\t\t\t\t\t\t\t// Actual completion data sent\n);\n\n`include \"common_functions.v\"\n\nwire \t[C_PCI_DATA_WIDTH-1:0]\t\twFifoWrData;\nwire \t[C_PCI_DATA_WIDTH-1:0]\t\twFifoRdData;\nwire\t[C_FIFO_DEPTH_WIDTH-1:0]\twFifoCount;\nwire\t\t\t\t\t\t\t\twFifoEmpty;\nwire\t\t\t\t\t\t\t\twFifoRen;\nwire\t\t\t\t\t\t\t\twFifoWen;\nwire\t\t\t\t\t\t\t\twAltera = C_ALTERA;\n\n// Convert the read and write requests into PCI packet format and mux\n// them together into a FIFO.\ntx_engine_upper_32 #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), .C_NUM_CHNL(C_NUM_CHNL), .C_FIFO_DEPTH(C_FIFO_DEPTH), .C_TAG_WIDTH(C_TAG_WIDTH)) upper (\n\t.RST(RST),\n\t.CLK(CLK),\n\t.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),\n\t.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),\n\t.WR_REQ(WR_REQ),\n\t.WR_ADDR(WR_ADDR),\n\t.WR_LEN(WR_LEN),\n\t.WR_DATA(WR_DATA),\n\t.WR_DATA_REN(WR_DATA_REN),\n\t.WR_ACK(WR_ACK),\n\t.RD_REQ(RD_REQ),\n\t.RD_SG_CHNL(RD_SG_CHNL),\n\t.RD_ADDR(RD_ADDR),\n\t.RD_LEN(RD_LEN),\n\t.RD_ACK(RD_ACK),\n .TX_ENG_RD_REQ_SENT(TX_ENG_RD_REQ_SENT),\n .RXBUF_SPACE_AVAIL(RXBUF_SPACE_AVAIL | !wAltera),\n\t.INT_TAG(INT_TAG),\n\t.INT_TAG_VALID(INT_TAG_VALID),\n\t.EXT_TAG(EXT_TAG),\n\t.EXT_TAG_VALID(EXT_TAG_VALID),\n\t.FIFO_DATA(wFifoWrData),\n\t.FIFO_COUNT(wFifoCount),\n\t.FIFO_WEN(wFifoWen)\n);\n\n\n// FIFO for storing outbound read/write requests.\n(* RAM_STYLE=\"BLOCK\" *)\nsync_fifo #(.C_WIDTH(C_PCI_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (\n\t.RST(RST),\n\t.CLK(CLK),\n\t.WR_EN(wFifoWen),\n\t.WR_DATA(wFifoWrData),\n\t.FULL(),\n\t.COUNT(wFifoCount),\n\t.RD_EN(wFifoRen),\n\t.RD_DATA(wFifoRdData),\n\t.EMPTY(wFifoEmpty)\n);\n\n\n// Process the formatted PCI packets in the FIFO and completions.\n// Completions take top priority. Mux the data into the AXI interface\n// for the PCIe Endpoint.\ntx_engine_lower_32 #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), .C_NUM_CHNL(C_NUM_CHNL)) lower (\n\t.RST(RST),\n\t.CLK(CLK),\n\t.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),\n\t.TX_DATA(TX_DATA),\n\t.TX_DATA_BYTE_ENABLE(TX_DATA_BYTE_ENABLE),\n\t.TX_TLP_END_FLAG(TX_TLP_END_FLAG),\n\t.TX_TLP_START_FLAG(TX_TLP_START_FLAG),\n\t.TX_DATA_VALID(TX_DATA_VALID),\n\t.S_AXIS_SRC_DSC(S_AXIS_SRC_DSC),\n\t.TX_DATA_READY(TX_DATA_READY),\n\t.COMPL_REQ(COMPL_REQ),\n\t.COMPL_DONE(COMPL_DONE),\n\t.REQ_TC(REQ_TC),\n\t.REQ_TD(REQ_TD),\n\t.REQ_EP(REQ_EP),\n\t.REQ_ATTR(REQ_ATTR),\n\t.REQ_LEN(REQ_LEN),\n\t.REQ_ID(REQ_ID),\n\t.REQ_TAG(REQ_TAG),\n\t.REQ_BE(REQ_BE),\n\t.REQ_ADDR(REQ_ADDR),\n\t.REQ_DATA(REQ_DATA),\n\t.REQ_DATA_SENT(REQ_DATA_SENT),\n\t.FIFO_DATA(wFifoRdData),\n\t.FIFO_EMPTY(wFifoEmpty),\n\t.FIFO_REN(wFifoRen),\n\t.WR_SENT(WR_SENT)\n);\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_64.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_engine_64.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tTransmit engine for PCIe using AXI interface from Xilinx \n// PCIe Endpoint core.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: Very good PCIe header reference:\n// http://www.pzk-agro.com/0321156307_ch04lev1sec5.html#ch04lev4sec14\n//-----------------------------------------------------------------------------\n\nmodule tx_engine_64 #(\n\tparameter C_PCI_DATA_WIDTH = 9'd64,\n\tparameter C_NUM_CHNL = 4'd12,\n\tparameter C_TAG_WIDTH = 5, \t\t\t\t\t\t\t// Number of outstanding requests \n\tparameter C_ALTERA = 1'b1,\t\t\t\t\t\t\t// 1 if Altera, 0 if Xilinx\n\t// Local parameters\n\tparameter C_FIFO_DEPTH = 512,\n\tparameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [15:0] CONFIG_COMPLETER_ID,\n\tinput [2:0] CONFIG_MAX_PAYLOAD_SIZE,\t\t\t\t// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B\n\n\toutput [C_PCI_DATA_WIDTH-1:0] TX_DATA,\t\t\t\t// AXI data output \n\toutput [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,\t// AXI data keep\n\toutput TX_TLP_END_FLAG,\t\t\t\t\t\t\t\t// AXI data last\n output TX_TLP_START_FLAG, // AXI data first\n\toutput TX_DATA_VALID,\t\t\t\t\t\t\t\t// AXI data valid\n\toutput S_AXIS_SRC_DSC,\t\t\t\t\t\t\t\t// AXI data discontinue\n\tinput TX_DATA_READY,\t\t\t\t\t\t\t\t// AXI ready for data\n\n\tinput [C_NUM_CHNL-1:0] WR_REQ,\t\t\t\t\t\t// Write request\n\tinput [(C_NUM_CHNL*64)-1:0] WR_ADDR,\t\t\t\t// Write address\n\tinput [(C_NUM_CHNL*10)-1:0] WR_LEN,\t\t\t\t\t// Write data length\n\tinput [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA,\t// Write data\n\toutput [C_NUM_CHNL-1:0] WR_DATA_REN,\t\t\t\t// Write data read enable\n\toutput [C_NUM_CHNL-1:0] WR_ACK,\t\t\t\t\t\t// Write request has been accepted\n\toutput [C_NUM_CHNL-1:0] WR_SENT, \t\t\t\t\t// Pulsed at channel pos when write request sent\n\n\tinput [C_NUM_CHNL-1:0] RD_REQ,\t\t\t\t\t\t// Read request\n\tinput [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL,\t\t\t\t// Read request channel for scatter gather lists\n\tinput [(C_NUM_CHNL*64)-1:0] RD_ADDR,\t\t\t\t// Read request address\n\tinput [(C_NUM_CHNL*10)-1:0] RD_LEN,\t\t\t\t\t// Read request length\n\toutput [C_NUM_CHNL-1:0] RD_ACK,\t\t\t\t\t\t// Read request has been accepted\n\t\n\toutput [5:0] INT_TAG,\t\t\t\t\t\t\t\t// Internal tag to exchange with external\n\toutput INT_TAG_VALID,\t\t\t\t\t\t\t\t// High to signal tag exchange \n\tinput [C_TAG_WIDTH-1:0] EXT_TAG,\t\t\t\t\t// External tag to provide in exchange for internal tag\n\tinput EXT_TAG_VALID,\t\t\t\t\t\t\t\t// High to signal external tag is valid\n\n output \t\t\t\t TX_ENG_RD_REQ_SENT, // Read completion request issued\n input \t\t\t\t RXBUF_SPACE_AVAIL,\n\t\n\tinput COMPL_REQ,\t\t\t\t\t\t\t\t\t// RX Engine request for completion\n\toutput COMPL_DONE,\t\t\t\t\t\t\t\t\t// Completion done\n\tinput [2:0] REQ_TC,\n\tinput REQ_TD,\n\tinput REQ_EP,\n\tinput [1:0] REQ_ATTR,\n\tinput [9:0] REQ_LEN,\n\tinput [15:0] REQ_ID,\n\tinput [7:0] REQ_TAG,\n\tinput [3:0] REQ_BE,\n\tinput [29:0] REQ_ADDR,\n\tinput [31:0] REQ_DATA,\n\toutput [31:0] REQ_DATA_SENT\t\t\t\t\t\t\t// Actual completion data sent\n);\n\n`include \"common_functions.v\"\n\nwire \t[C_PCI_DATA_WIDTH-1:0]\t\twFifoWrData;\nwire \t[C_PCI_DATA_WIDTH-1:0]\t\twFifoRdData;\nwire\t[C_FIFO_DEPTH_WIDTH-1:0]\twFifoCount;\nwire\t\t\t\t\t\t\t\twFifoEmpty;\nwire\t\t\t\t\t\t\t\twFifoRen;\nwire\t\t\t\t\t\t\t\twFifoWen;\nwire\t\t\t\t\t\t\t\twAltera = C_ALTERA;\n\n// Convert the read and write requests into PCI packet format and mux\n// them together into a FIFO.\ntx_engine_upper_64 #(\n .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), \n .C_NUM_CHNL(C_NUM_CHNL), \n\t.C_FIFO_DEPTH(C_FIFO_DEPTH), \n .C_TAG_WIDTH(C_TAG_WIDTH),\n\t.C_ALTERA(C_ALTERA)\n) upper (\n\t.RST(RST),\n\t.CLK(CLK),\n\t.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),\n\t.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),\n\t.WR_REQ(WR_REQ),\n\t.WR_ADDR(WR_ADDR),\n\t.WR_LEN(WR_LEN),\n\t.WR_DATA(WR_DATA),\n\t.WR_DATA_REN(WR_DATA_REN),\n\t.WR_ACK(WR_ACK),\n\t.RD_REQ(RD_REQ),\n\t.RD_SG_CHNL(RD_SG_CHNL),\n\t.RD_ADDR(RD_ADDR),\n\t.RD_LEN(RD_LEN),\n\t.RD_ACK(RD_ACK),\n .TX_ENG_RD_REQ_SENT(TX_ENG_RD_REQ_SENT),\n .RXBUF_SPACE_AVAIL(RXBUF_SPACE_AVAIL | !wAltera),\n\t.INT_TAG(INT_TAG),\n\t.INT_TAG_VALID(INT_TAG_VALID),\n\t.EXT_TAG(EXT_TAG),\n\t.EXT_TAG_VALID(EXT_TAG_VALID),\n\t.FIFO_DATA(wFifoWrData),\n\t.FIFO_COUNT(wFifoCount),\n\t.FIFO_WEN(wFifoWen)\n);\n\n\n// FIFO for storing outbound read/write requests.\n(* RAM_STYLE=\"BLOCK\" *)\nsync_fifo #(.C_WIDTH(C_PCI_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (\n\t.RST(RST),\n\t.CLK(CLK),\n\t.WR_EN(wFifoWen),\n\t.WR_DATA(wFifoWrData),\n\t.FULL(),\n\t.COUNT(wFifoCount),\n\t.RD_EN(wFifoRen),\n\t.RD_DATA(wFifoRdData),\n\t.EMPTY(wFifoEmpty)\n);\n\n\n// Process the formatted PCI packets in the FIFO and completions.\n// Completions take top priority. Mux the data into the AXI interface\n// for the PCIe Endpoint.\ntx_engine_lower_64 #(\n\t.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), \n\t.C_NUM_CHNL(C_NUM_CHNL),\n\t.C_ALTERA(C_ALTERA)\n) lower (\n\t.RST(RST),\n\t.CLK(CLK),\n\t.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),\n\t.TX_DATA(TX_DATA),\n\t.TX_DATA_BYTE_ENABLE(TX_DATA_BYTE_ENABLE),\n\t.TX_TLP_END_FLAG(TX_TLP_END_FLAG),\n .TX_TLP_START_FLAG(TX_TLP_START_FLAG),\n\t.TX_DATA_VALID(TX_DATA_VALID),\n\t.S_AXIS_SRC_DSC(S_AXIS_SRC_DSC),\n\t.TX_DATA_READY(TX_DATA_READY),\n\t.COMPL_REQ(COMPL_REQ),\n\t.COMPL_DONE(COMPL_DONE),\n\t.REQ_TC(REQ_TC),\n\t.REQ_TD(REQ_TD),\n\t.REQ_EP(REQ_EP),\n\t.REQ_ATTR(REQ_ATTR),\n\t.REQ_LEN(REQ_LEN),\n\t.REQ_ID(REQ_ID),\n\t.REQ_TAG(REQ_TAG),\n\t.REQ_BE(REQ_BE),\n\t.REQ_ADDR(REQ_ADDR),\n\t.REQ_DATA(REQ_DATA),\n\t.REQ_DATA_SENT(REQ_DATA_SENT),\n\t.FIFO_DATA(wFifoRdData),\n\t.FIFO_EMPTY(wFifoEmpty),\n\t.FIFO_REN(wFifoRen),\n\t.WR_SENT(WR_SENT)\n);\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_formatter_128.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_engine_formatter_128.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tFormats read and write request data into PCI packets.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: Very good PCIe header reference:\n// http://www.pzk-agro.com/0321156307_ch04lev1sec5.html#ch04lev4sec14\n//-----------------------------------------------------------------------------\n`define FMT_TXENGFMTR128_WR32\t7'b10_00000\n`define FMT_TXENGFMTR128_RD32\t7'b00_00000\n`define FMT_TXENGFMTR128_WR64\t7'b11_00000\n`define FMT_TXENGFMTR128_RD64\t7'b01_00000\n\n`define S_TXENGFMTR128_IDLE\t\t1'b0\n`define S_TXENGFMTR128_WR\t\t1'b1\n\nmodule tx_engine_formatter_128 #(\n\tparameter C_PCI_DATA_WIDTH = 9'd128,\n\t// Local parameters\n\tparameter C_TRAFFIC_CLASS = 3'b0,\n\tparameter C_RELAXED_ORDER = 1'b0,\n\tparameter C_NO_SNOOP = 1'b0\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [15:0] CONFIG_COMPLETER_ID,\n\n\tinput VALID,\t\t \t\t\t\t\t// Are input parameters valid?\n\tinput WNR,\t\t \t\t\t\t\t\t// Is a write request, not a read?\n\tinput [7:0] TAG,\t\t \t\t\t\t// External tag\n\tinput [3:0] CHNL,\t\t \t\t\t\t// Internal tag (just channel portion)\n\tinput [61:0] ADDR,\t\t \t\t\t\t// Request address\n\tinput ADDR_64,\t\t \t\t\t\t\t// Request address is 64 bit\n\tinput [9:0] LEN,\t\t \t\t\t\t// Request length\n\tinput LEN_ONE,\t\t \t\t\t\t\t// Request length equals 1\n\tinput [C_PCI_DATA_WIDTH-1:0] WR_DATA,\t// Request data, timed to arrive accordingly\n\n\toutput [C_PCI_DATA_WIDTH-1:0] OUT_DATA,\t// Formatted PCI packet data\n\toutput OUT_DATA_WEN \t\t\t\t\t// Write enable for formatted packet data\n);\n\nreg\t\t\t\t\t\t\t\t\trState=`S_TXENGFMTR128_IDLE, _rState=`S_TXENGFMTR128_IDLE;\nreg\t\t\t\t\t\t\t\t\trAddr64=0, _rAddr64=0;\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trData={C_PCI_DATA_WIDTH{1'd0}}, _rData={C_PCI_DATA_WIDTH{1'd0}};\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trPrevData={C_PCI_DATA_WIDTH{1'd0}}, _rPrevData={C_PCI_DATA_WIDTH{1'd0}};\nreg\t\t\t\t\t\t\t\t\trDataWen=0, _rDataWen=0;\nreg\t\t[9:0]\t\t\t\t\t\trLen=0, _rLen=0;\nreg\t\t\t\t\t\t\t\t\trDone=0, _rDone=0;\n\n\nassign OUT_DATA = rData;\nassign OUT_DATA_WEN = rDataWen;\n\n\n// Format read and write requests into PCIe packets.\nwire [63:0] wHdrData = ({WR_DATA[31:0], ADDR[29:0], 2'b00, ADDR[61:30]})>>(32*(!ADDR_64));\nwire [C_PCI_DATA_WIDTH-1:0] wWrData = ({WR_DATA[31:0], rPrevData})>>(32*(!rAddr64));\n\nalways @ (posedge CLK) begin\n\trState <= #1 (RST ? `S_TXENGFMTR128_IDLE : _rState);\n\trDataWen <= #1 (RST ? 1'd0 : _rDataWen);\n\trData <= #1 _rData;\n\trLen <= #1 _rLen;\n\trAddr64 <= #1 _rAddr64;\n\trPrevData <= #1 _rPrevData;\n\trDone <= #1 _rDone;\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\t_rLen = rLen;\n\t_rData = rData;\n\t_rDataWen = rDataWen;\n\t_rPrevData = WR_DATA;\n\t_rAddr64 = rAddr64;\n\tcase (rState) \n\n\t`S_TXENGFMTR128_IDLE : begin // FIFO data should be available now (if it's a write)\n\t\t_rLen = LEN - !ADDR_64; // Subtract 1 for 32 bit (HDR has one)\n\t\t_rAddr64 = ADDR_64;\n\t\t_rData = {wHdrData,\t\t\t\t\t\t\t\t\t\t\t\t\t\t// DW3, DW2\n\t\t\t\t\tCONFIG_COMPLETER_ID[15:3], 3'b0, TAG,\n\t\t\t\t\t(LEN_ONE ? 4'b0 : 4'b1111), 4'b1111,\t\t\t\t\t\t// DW1\n\t\t\t\t\t1'b0, {WNR, ADDR_64, 5'd0}, 1'b0, C_TRAFFIC_CLASS, CHNL, 1'b0, 1'b0, // Use the reserved 4 bits before traffic class to hide the internal tag \n\t\t\t\t\tC_RELAXED_ORDER, C_NO_SNOOP, 2'b0, LEN};\t\t\t\t\t// DW0\n\t\t_rDataWen = VALID;\n\t\t_rDone = (LEN <= {1'b1, 1'b0, !ADDR_64});\n\t\t_rState = (VALID & WNR & (ADDR_64 | !LEN_ONE) ? `S_TXENGFMTR128_WR : `S_TXENGFMTR128_IDLE);\n\tend\n\n\t`S_TXENGFMTR128_WR : begin\n\t\t_rLen = rLen - 3'd4;\n\t\t_rDone = (rLen <= 4'd8);\n\t\t_rData = wWrData;\n\t\t_rState = (rDone ? `S_TXENGFMTR128_IDLE : `S_TXENGFMTR128_WR);\n\tend\n\n\tendcase\nend\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_formatter_32.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_engine_formatter_32.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tFormats read and write request data into PCI packets.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: Very good PCIe header reference:\n// http://www.pzk-agro.com/0321156307_ch04lev1sec5.html#ch04lev4sec14\n//-----------------------------------------------------------------------------\n`define FMT_TXENGFMTR32_WR32\t7'b10_00000\n`define FMT_TXENGFMTR32_RD32\t7'b00_00000\n`define FMT_TXENGFMTR32_WR64\t7'b11_00000\n`define FMT_TXENGFMTR32_RD64\t7'b01_00000\n\n`define S_TXENGFMTR32_IDLE\t\t3'd0\n`define S_TXENGFMTR32_HDR_0\t\t3'd1\n`define S_TXENGFMTR32_HDR_1\t\t3'd2\n`define S_TXENGFMTR32_HDR_2\t\t3'd3\n`define S_TXENGFMTR32_WR\t\t3'd4\n\nmodule tx_engine_formatter_32 #(\n\tparameter C_PCI_DATA_WIDTH = 9'd32,\n\t// Local parameters\n\tparameter C_TRAFFIC_CLASS = 3'b0,\n\tparameter C_RELAXED_ORDER = 1'b0,\n\tparameter C_NO_SNOOP = 1'b0\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [15:0] CONFIG_COMPLETER_ID,\n\n\tinput VALID,\t\t \t\t\t\t\t// Are input parameters valid?\n\tinput WNR,\t\t \t\t\t\t\t\t// Is a write request, not a read?\n\tinput [7:0] TAG,\t\t \t\t\t\t// External tag\n\tinput [3:0] CHNL,\t\t \t\t\t\t// Internal tag (just channel portion)\n\tinput [61:0] ADDR,\t\t \t\t\t\t// Request address\n\tinput ADDR_64,\t\t \t\t\t\t\t// Request address is 64 bit\n\tinput [9:0] LEN,\t\t \t\t\t\t// Request length\n\tinput LEN_ONE,\t\t \t\t\t\t\t// Request length equals 1\n\tinput [C_PCI_DATA_WIDTH-1:0] WR_DATA,\t// Request data, timed to arrive accordingly\n\n\toutput [C_PCI_DATA_WIDTH-1:0] OUT_DATA,\t// Formatted PCI packet data\n\toutput OUT_DATA_WEN \t\t\t\t\t// Write enable for formatted packet data\n);\n\nreg\t\t[2:0]\t\t\t\t\t\trState=`S_TXENGFMTR32_IDLE, _rState=`S_TXENGFMTR32_IDLE;\nreg\t\t[61:0]\t\t\t\t\t\trAddr=62'd0, _rAddr=62'd0;\nreg\t\t\t\t\t\t\t\t\trAddr64=0, _rAddr64=0;\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trData={C_PCI_DATA_WIDTH{1'd0}}, _rData={C_PCI_DATA_WIDTH{1'd0}};\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trPrevData={C_PCI_DATA_WIDTH{1'd0}}, _rPrevData={C_PCI_DATA_WIDTH{1'd0}};\nreg\t\t\t\t\t\t\t\t\trDataWen=0, _rDataWen=0;\nreg\t\t[9:0]\t\t\t\t\t\trLen=0, _rLen=0;\nreg\t\t\t\t\t\t\t\t\trLenEQ1=0, _rLenEQ1=0;\nreg\t\t\t\t\t\t\t\t\trWNR=0, _rWNR=0;\nreg\t\t[7:0]\t\t\t\t\t\trTag=0, _rTag=0;\nreg\t\t\t\t\t\t\t\t\trInitDone=0, _rInitDone=0;\nreg\t\t\t\t\t\t\t\t\trDone=0, _rDone=0;\n\n\nassign OUT_DATA = rData;\nassign OUT_DATA_WEN = rDataWen;\n\n\n// Format read and write requests into PCIe packets.\nwire [31:0] wData = ({rPrevData, WR_DATA}>>(32*rAddr64));\nalways @ (posedge CLK) begin\n\trState <= #1 (RST ? `S_TXENGFMTR32_IDLE : _rState);\n\trDataWen <= #1 (RST ? 1'd0 : _rDataWen);\n\trData <= #1 _rData;\n\trLen <= #1 _rLen;\n\trAddr <= #1 _rAddr;\n\trAddr64 <= #1 _rAddr64;\n\trWNR <= #1 _rWNR;\n\trTag <= #1 _rTag;\n\trLenEQ1 <= #1 _rLenEQ1;\n\trInitDone <= #1 _rInitDone;\n\trDone <= #1 _rDone;\n\trPrevData <= #1 _rPrevData;\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\t_rLen = rLen;\n\t_rData = rData;\n\t_rDataWen = rDataWen;\n\t_rAddr64 = rAddr64;\n\t_rAddr = rAddr;\n\t_rWNR = rWNR;\n\t_rTag = rTag;\n\t_rLenEQ1 = rLenEQ1;\n\t_rInitDone = rInitDone;\n\t_rDone = rDone;\n\t\n\t_rPrevData = WR_DATA;\n\t\n\tcase (rState) \n\n\t`S_TXENGFMTR32_IDLE : begin\n\t\t_rLen = LEN;\n\t\t_rAddr64 = ADDR_64;\n\t\t_rAddr = ADDR;\n\t\t_rWNR = WNR;\n\t\t_rTag = TAG;\n\t\t_rLenEQ1 = LEN_ONE;\n\t\t_rData = {1'b0, {WNR, ADDR_64, 5'd0}, 1'b0, C_TRAFFIC_CLASS, CHNL, 1'b0, 1'b0, // Use the reserved 4 bits before traffic class to hide the internal tag \n\t\t\t\t\tC_RELAXED_ORDER, C_NO_SNOOP, 2'b0, LEN};\n\t\t_rDataWen = VALID;\n\t\t_rState = (VALID ? `S_TXENGFMTR32_HDR_0 : `S_TXENGFMTR32_IDLE);\n\tend\n\n\t`S_TXENGFMTR32_HDR_0 : begin\n\t\t_rData = {CONFIG_COMPLETER_ID[15:3], 3'b0, rTag,\n\t\t\t\t\t(rLenEQ1 ? 4'b0 : 4'b1111), 4'b1111};\n\t\t_rInitDone = (!rAddr64 & !rWNR);\n\t\t_rState = (rAddr64 ? `S_TXENGFMTR32_HDR_1 : `S_TXENGFMTR32_HDR_2);\n\tend\n\n\t`S_TXENGFMTR32_HDR_1 : begin\n\t\t_rData = rAddr[61:30];\n\t\t_rInitDone = !rWNR;\n\t\t_rState = `S_TXENGFMTR32_HDR_2;\n\tend\n\n\t`S_TXENGFMTR32_HDR_2 : begin // FIFO data should be available now (if it's a write)\n\t\t_rData = {rAddr[29:0], 2'b00};\n\t\t_rDone = rLenEQ1;\n\t\t_rState = (rInitDone ? `S_TXENGFMTR32_IDLE : `S_TXENGFMTR32_WR);\n\tend\n\n\t`S_TXENGFMTR32_WR : begin \n\t\t_rLen = rLen - 1'd1;\n\t\t_rData = wData;\n\t\t_rDone = (rLen == 2'd2);\n\t\t_rState = (rDone ? `S_TXENGFMTR32_IDLE : `S_TXENGFMTR32_WR);\n\tend\n\n\tdefault : begin\n\t\t_rState = `S_TXENGFMTR32_IDLE;\n\tend\n\n\tendcase\nend\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_formatter_64.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_engine_formatter_64.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tFormats read and write request data into PCI packets.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: Very good PCIe header reference:\n// http://www.pzk-agro.com/0321156307_ch04lev1sec5.html#ch04lev4sec14\n//-----------------------------------------------------------------------------\n`define FMT_TXENGFMTR64_WR32\t7'b10_00000\n`define FMT_TXENGFMTR64_RD32\t7'b00_00000\n`define FMT_TXENGFMTR64_WR64\t7'b11_00000\n`define FMT_TXENGFMTR64_RD64\t7'b01_00000\n\n`define S_TXENGFMTR64_IDLE\t\t2'b10\n`define S_TXENGFMTR64_HDR\t\t2'b01\n`define S_TXENGFMTR64_WR\t\t2'b00\n\nmodule tx_engine_formatter_64 #(\n\tparameter C_PCI_DATA_WIDTH = 9'd64,\n\t// Local parameters\n\tparameter C_TRAFFIC_CLASS = 3'b0,\n\tparameter C_RELAXED_ORDER = 1'b0,\n\tparameter C_NO_SNOOP = 1'b0\n)\n(\n\tinput CLK,\n\tinput RST,\n\tinput [15:0] CONFIG_COMPLETER_ID,\n\n\tinput VALID,\t\t \t\t\t\t\t// Are input parameters valid?\n\tinput WNR,\t\t \t\t\t\t\t\t// Is a write request, not a read?\n\tinput [7:0] TAG,\t\t \t\t\t\t// External tag\n\tinput [3:0] CHNL,\t\t \t\t\t\t// Internal tag (just channel portion)\n\tinput [61:0] ADDR,\t\t \t\t\t\t// Request address\n\tinput ADDR_64,\t\t \t\t\t\t\t// Request address is 64 bit\n\tinput [9:0] LEN,\t\t \t\t\t\t// Request length\n\tinput LEN_ONE,\t\t \t\t\t\t\t// Request length equals 1\n\tinput [C_PCI_DATA_WIDTH-1:0] WR_DATA,\t// Request data, timed to arrive accordingly\n\n\toutput [C_PCI_DATA_WIDTH-1:0] OUT_DATA,\t// Formatted PCI packet data\n\toutput OUT_DATA_WEN \t\t\t\t\t// Write enable for formatted packet data\n);\n\n(* fsm_encoding = \"user\" *)\nreg\t\t[1:0]\t\t\t\t\t\trState=`S_TXENGFMTR64_IDLE, _rState=`S_TXENGFMTR64_IDLE;\nreg\t\t[61:0]\t\t\t\t\t\trAddr=62'd0, _rAddr=62'd0;\nreg\t\t\t\t\t\t\t\t\trAddr64=0, _rAddr64=0;\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trData={C_PCI_DATA_WIDTH{1'd0}}, _rData={C_PCI_DATA_WIDTH{1'd0}};\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trPrevData={C_PCI_DATA_WIDTH{1'd0}}, _rPrevData={C_PCI_DATA_WIDTH{1'd0}};\nreg\t\t\t\t\t\t\t\t\trDataWen=0, _rDataWen=0;\nreg\t\t[9:0]\t\t\t\t\t\trLen=0, _rLen=0;\nreg\t\t\t\t\t\t\t\t\trInitDone=0, _rInitDone=0;\nreg\t\t\t\t\t\t\t\t\trDone=0, _rDone=0;\n\n\nassign OUT_DATA = rData;\nassign OUT_DATA_WEN = rDataWen;\n\n\n// Format read and write requests into PCIe packets.\nwire [C_PCI_DATA_WIDTH-1:0] wHdrData = ({WR_DATA[31:0], rAddr[29:0], 2'b00, rAddr[61:30]})>>(32*(!rAddr64));\nwire [C_PCI_DATA_WIDTH-1:0] wWrData = ({WR_DATA[31:0], rPrevData})>>(32*(!rAddr64));\n\nalways @ (posedge CLK) begin\n\trState <= #1 (RST ? `S_TXENGFMTR64_IDLE : _rState);\n\trDataWen <= #1 (RST ? 1'd0 : _rDataWen);\n\trData <= #1 _rData;\n\trLen <= #1 _rLen;\n\trAddr <= #1 _rAddr;\n\trAddr64 <= #1 _rAddr64;\n\trPrevData <= #1 _rPrevData;\n\trInitDone <= #1 _rInitDone;\n\trDone <= #1 _rDone;\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\t_rLen = rLen;\n\t_rData = rData;\n\t_rDataWen = rDataWen;\n\t_rPrevData = WR_DATA;\n\t_rAddr64 = rAddr64;\n\t_rAddr = rAddr;\n\t_rInitDone = rInitDone;\n\t_rDone = (rLen <= 3'd4);\n\tcase (rState) \n\n\t`S_TXENGFMTR64_IDLE : begin\n\t\t_rLen = LEN - !ADDR_64 + 2'd2; // Subtract 1 for 32 bit (HDR has one), add 2 so we can always decrement by 2\n\t\t_rAddr64 = ADDR_64;\n\t\t_rAddr = ADDR;\n\t\t_rData = {CONFIG_COMPLETER_ID[15:3], 3'b0, TAG,\n\t\t\t\t\t(LEN_ONE ? 4'b0 : 4'b1111), 4'b1111,\t\t\t\t\t\t\t// DW1\n\t\t\t\t\t1'b0, {WNR, ADDR_64, 5'd0}, 1'b0, C_TRAFFIC_CLASS, CHNL, 1'b0, 1'b0, // Use the reserved 4 bits before traffic class to hide the internal tag \n\t\t\t\t\tC_RELAXED_ORDER, C_NO_SNOOP, 2'b0, LEN};\t\t\t\t\t// DW0\n\t\t_rDataWen = VALID;\n\t\t_rInitDone = ((!ADDR_64 & LEN_ONE) | !WNR);\n\t\t_rState = (VALID ? `S_TXENGFMTR64_HDR : `S_TXENGFMTR64_IDLE);\n\tend\n\n\t`S_TXENGFMTR64_HDR : begin // FIFO data should be available now (if it's a write)\n\t\t_rLen = rLen - 2'd2;\n\t\t_rData = wHdrData;\n\t\t_rState = (rInitDone ? `S_TXENGFMTR64_IDLE : `S_TXENGFMTR64_WR);\n\tend\n\n\t`S_TXENGFMTR64_WR : begin\n\t\t_rLen = rLen - 2'd2;\n\t\t_rData = wWrData;\n\t\t_rState = (rDone ? `S_TXENGFMTR64_IDLE : `S_TXENGFMTR64_WR);\n\tend\n\n\tdefault : begin\n\t\t_rState = `S_TXENGFMTR64_IDLE;\n\tend\n\n\tendcase\nend\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_lower_128.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_engine_lower_128.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tTransmit engine for completion requests and pre-formatted\n// PCIe read/write data. Muxes traffic for the AXI interface on the Xilinx PCIe \n// Endpoint core.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: Very good PCIe header reference:\n// http://www.pzk-agro.com/0321156307_ch04lev1sec5.html#ch04lev4sec14\n// Also byte swap each payload word due to Xilinx incorrect mapping, see\n// http://forums.xilinx.com/t5/PCI-Express/PCI-Express-payload-required-to-be-Big-Endian-by-specification/td-p/285551\n//-----------------------------------------------------------------------------\n`define FMT_TXENGLWR128_CPLD\t7'b10_01010\n\n`define S_TXENGLWR128_IDLE\t\t2'd0\n`define S_TXENGLWR128_CPLD_0\t2'd1\n`define S_TXENGLWR128_CPLD_1\t2'd2\n`define S_TXENGLWR128_WR\t\t2'd3\n\nmodule tx_engine_lower_128 #(\n\tparameter C_PCI_DATA_WIDTH = 9'd128,\n\tparameter C_NUM_CHNL = 4'd12,\n\tparameter C_ALTERA = 1'b1\n)\n(\n\tinput CLK,\n\tinput RST,\n\n\tinput [15:0] CONFIG_COMPLETER_ID,\n\n\toutput [C_PCI_DATA_WIDTH-1:0] TX_DATA,\t\t\t\t\t// AXI data output \n\toutput [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,\t// AXI data keep\n\toutput TX_TLP_END_FLAG,\t\t\t\t\t\t\t\t\t// AXI data last\n\toutput TX_DATA_VALID,\t\t\t\t\t\t\t\t\t// AXI data valid\n\toutput S_AXIS_SRC_DSC,\t\t\t\t\t\t\t\t\t// AXI data discontinue\n output TX_TLP_START_FLAG,\t\t\t\t\t\t\t\t// AXI data start\n\tinput TX_DATA_READY,\t\t\t\t\t\t\t\t\t// AXI ready for data\n\n\tinput COMPL_REQ,\t\t\t\t\t\t\t\t\t\t// RX Engine request for completion\n\toutput COMPL_DONE,\t\t\t\t\t\t\t\t\t\t// Completion done\n\tinput [2:0] REQ_TC,\n\tinput REQ_TD,\n\tinput REQ_EP,\n\tinput [1:0] REQ_ATTR,\n\tinput [9:0] REQ_LEN,\n\tinput [15:0] REQ_ID,\n\tinput [7:0] REQ_TAG,\n\tinput [3:0] REQ_BE,\n\tinput [29:0] REQ_ADDR,\n\tinput [31:0] REQ_DATA,\n\toutput [31:0] REQ_DATA_SENT,\t\t\t\t\t\t\t// Actual completion data sent\n\n\tinput [C_PCI_DATA_WIDTH-1:0] FIFO_DATA,\t\t\t\t\t// Read/Write FIFO requests + data\n\tinput FIFO_EMPTY,\t\t\t\t\t\t\t\t\t\t// Read/Write FIFO is empty\n\toutput FIFO_REN,\t\t\t\t\t\t\t\t\t\t// Read/Write FIFO read enable\n\toutput [C_NUM_CHNL-1:0] WR_SENT \t\t\t\t\t\t// Pulsed at channel pos when write request sent\n );\n\n\nreg [11:0] rByteCount=0;\nreg [6:0] rLowerAddr=0;\n\nreg rFifoRen=0, _rFifoRen=0;\nreg rFifoRenIssued=0, _rFifoRenIssued=0;\nreg rFifoDataEmpty=1, _rFifoDataEmpty=1;\nreg [2:0] rFifoDataValid=0, _rFifoDataValid=0;\nreg [(3*C_PCI_DATA_WIDTH)-1:0] rFifoData={3*C_PCI_DATA_WIDTH{1'd0}}, _rFifoData={3*C_PCI_DATA_WIDTH{1'd0}};\nwire [(3*C_PCI_DATA_WIDTH)-1:0] wFifoData = (rFifoData>>(C_PCI_DATA_WIDTH*(!rFifoRen)))>>(C_PCI_DATA_WIDTH*(!rFifoRenIssued));\nwire [2:0] wFifoDataValid = (rFifoDataValid>>(!rFifoRen))>>(!rFifoRenIssued);\n\nreg [1:0] rState=`S_TXENGLWR128_IDLE, _rState=`S_TXENGLWR128_IDLE;\nreg rComplDone=0, _rComplDone=0;\nreg rValid=0, _rValid=0;\nreg [C_PCI_DATA_WIDTH-1:0] rData={C_PCI_DATA_WIDTH{1'd0}}, _rData={C_PCI_DATA_WIDTH{1'd0}};\nreg rLast=0, _rLast=0;\nreg rFirst=0, _rFirst=0;\nreg [3:0] rKeep=0, _rKeep=0;\nreg [C_NUM_CHNL-1:0] rDone=0, _rDone=0;\nreg [9:0] rLen=0, _rLen=0;\nreg rIsLast=0, _rIsLast=0;\nwire [31:0] wReqDataSwap;\nwire [7:0] wKeep = (8'b00001111<<(rLen[2:0])) | {8{!rIsLast}};\t\t\t\n\n\nassign TX_DATA = rData;\nassign TX_DATA_BYTE_ENABLE = {{4{rKeep[3]}}, {4{rKeep[2]}}, {4{rKeep[1]}}, {4{rKeep[0]}}};\nassign TX_TLP_END_FLAG = rLast;\nassign TX_TLP_START_FLAG = rFirst;\nassign TX_DATA_VALID = rValid;\nassign S_AXIS_SRC_DSC = 0;\n\nassign COMPL_DONE = rComplDone;\n\ngenerate\nif(C_ALTERA == 1'b1) begin : altera_data\n\tassign REQ_DATA_SENT = rData[127:96];\n\tassign wReqDataSwap = REQ_DATA[31:0];\nend \nelse begin : xilinx_data\n\tassign REQ_DATA_SENT = {rData[103:96], rData[111:104], rData[119:112], rData[127:120]};\n\tassign wReqDataSwap = {REQ_DATA[7:0], REQ_DATA[15:8], REQ_DATA[23:16], REQ_DATA[31:24]};\nend\nendgenerate\n \n\nassign FIFO_REN = rFifoRen;\nassign WR_SENT = rDone;\n\n\n// Calculate byte count based on byte enable\nalways @ (REQ_BE) begin\n\tcasex (REQ_BE)\n\t4'b1xx1 : rByteCount = 12'h004;\n\t4'b01x1 : rByteCount = 12'h003;\n\t4'b1x10 : rByteCount = 12'h003;\n\t4'b0011 : rByteCount = 12'h002;\n\t4'b0110 : rByteCount = 12'h002;\n\t4'b1100 : rByteCount = 12'h002;\n\t4'b0001 : rByteCount = 12'h001;\n\t4'b0010 : rByteCount = 12'h001;\n\t4'b0100 : rByteCount = 12'h001;\n\t4'b1000 : rByteCount = 12'h001;\n\t4'b0000 : rByteCount = 12'h001;\n\tendcase\nend\n\n\n// Calculate lower address based on byte enable\nalways @ (REQ_BE or REQ_ADDR) begin\n\tcasex (REQ_BE)\n\t4'b0000 : rLowerAddr = {REQ_ADDR[4:0], 2'b00};\n\t4'bxxx1 : rLowerAddr = {REQ_ADDR[4:0], 2'b00};\n\t4'bxx10 : rLowerAddr = {REQ_ADDR[4:0], 2'b01};\n\t4'bx100 : rLowerAddr = {REQ_ADDR[4:0], 2'b10};\n\t4'b1000 : rLowerAddr = {REQ_ADDR[4:0], 2'b11};\n\tendcase\nend\n\n\n// Read in the pre-formatted PCIe data.\nalways @ (posedge CLK) begin\n\trFifoRenIssued <= #1 (RST ? 1'd0 : _rFifoRenIssued);\n\trFifoDataValid <= #1 (RST ? 1'd0 : _rFifoDataValid);\n\trFifoDataEmpty <= #1 (RST ? 1'd1 : _rFifoDataEmpty);\n\trFifoData <= #1 _rFifoData;\nend\n\nalways @ (*) begin\n\t_rFifoRenIssued = rFifoRen;\n\t_rFifoDataEmpty = (rFifoRen ? FIFO_EMPTY : rFifoDataEmpty);\n\n\tif (rFifoRenIssued) begin\n\t\t_rFifoData = ((rFifoData<<(C_PCI_DATA_WIDTH)) | FIFO_DATA);\n\t\t_rFifoDataValid = ((rFifoDataValid<<1) | (!rFifoDataEmpty));\n\tend\n\telse begin\n\t\t_rFifoData = rFifoData;\n\t\t_rFifoDataValid = rFifoDataValid;\n\tend\nend\n\n\n// Multiplex completion requests and read/write pre-formatted PCIe data onto\n// the AXI PCIe Endpoint interface. Remember that TX_DATA_READY may drop at\n// *any* time during transmission. So be sure to buffer enough data to \n// accommodate starts and stops.\nalways @ (posedge CLK) begin\n\trState <= #1 (RST ? `S_TXENGLWR128_IDLE : _rState);\n\trComplDone <= #1 (RST ? 1'd0 : _rComplDone);\n\trValid <= #1 (RST ? 1'd0 : _rValid);\n\trFifoRen <= #1 (RST ? 1'd0 : _rFifoRen);\n\trDone <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rDone);\n\trData <= #1 _rData;\n\trLast <= #1 _rLast;\n\trKeep <= #1 _rKeep;\n\trLen <= #1 _rLen;\n\trIsLast <= #1 _rIsLast;\n\trFirst <= #1 _rFirst;\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\t_rComplDone = rComplDone;\n\t_rValid = rValid;\n\t_rFifoRen = rFifoRen;\n\t_rData = rData;\n\t_rLast = rLast;\n\t_rKeep = rKeep;\n\t_rDone = rDone;\n\t_rLen = rLen;\n\t_rIsLast = rIsLast;\n\t_rFirst = rFirst;\n \n\tcase (rState) \n\n\t`S_TXENGLWR128_IDLE : begin\n\t\t_rFifoRen = (TX_DATA_READY & !COMPL_REQ);\n\t\t_rDone = ((TX_DATA_READY & !COMPL_REQ & wFifoDataValid[0] & wFifoData[30])<>(!wFifoData[30] & !wFifoData[29])); // Not WRITE TLP && !64 bit \n\t\t\t_rLen = wFifoData[9:0] - !wFifoData[29]; // LEN - !64 bit\n\t\t\t_rIsLast = (wFifoData[9:0] <= {1'b1, 1'b0, !wFifoData[29]}); // LEN <= 4 + !64 bit\n\t\t\tif (COMPL_REQ) // PIO read completions\n\t\t\t\t_rState = `S_TXENGLWR128_CPLD_0;\n\t\t\telse if (wFifoDataValid[0]) // Read FIFO data if it's ready\n\t\t\t\t_rState = (wFifoData[30] & (wFifoData[29] | wFifoData[36]) ? `S_TXENGLWR128_WR : `S_TXENGLWR128_IDLE); // WRITE TLP & (64 bit | LEN != 1)?\n\t\tend\n\tend\n\n\t`S_TXENGLWR128_CPLD_0 : begin\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rComplDone = 1;\n\t\t\t_rValid = 1;\n\t\t\t_rLast = 1;\n\t\t\t_rFirst = 1;\n\t\t\t_rKeep = 4'b1111;\n\t\t\t_rData = {wReqDataSwap,\t\t\t\t\t\t\t\t\t\t\t\t\t\t// DW3\n\t\t\t\t\t\tREQ_ID, REQ_TAG, 1'b0, rLowerAddr,\t\t\t\t\t\t\t\t// DW2\n\t\t\t\t\t\tCONFIG_COMPLETER_ID[15:3], 3'b0, 3'b0, 1'b0, rByteCount,\t\t// DW1\n\t\t\t\t\t\t1'b0, `FMT_TXENGLWR128_CPLD, 1'b0, REQ_TC, 4'b0, REQ_TD,\n\t\t\t\t\t\tREQ_EP, REQ_ATTR, 2'b0, REQ_LEN};\t\t\t\t\t\t\t\t// DW0\n\t\t\t_rState = `S_TXENGLWR128_CPLD_1;\n\t\tend\n\tend\n\n\t`S_TXENGLWR128_CPLD_1 : begin\n\t\t// Just wait a cycle for the COMP_REQ to drop.\n\t\t_rComplDone = 0;\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rFirst = 0;\n\t\t\t_rValid = 0;\n\t\t\t_rState = `S_TXENGLWR128_IDLE;\n\t\tend\n\tend\n\n\t`S_TXENGLWR128_WR : begin\n\t\t_rFifoRen = TX_DATA_READY;\n\t\t_rDone = 0;\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rFirst = 0;\n\t\t\t_rData = wFifoData[127:0];\n\t\t\t_rValid = 1;\n\t\t\t_rLast = rIsLast;\n\t\t\t_rKeep = wKeep[7:4];\t\t\t\n\t\t\t_rLen = rLen - 3'd4;\n\t\t\t_rIsLast = (rLen <= 4'd8);\n\t\t\t_rState = (rIsLast ? `S_TXENGLWR128_IDLE : `S_TXENGLWR128_WR);\n\t\tend\n\tend\n\n\tendcase\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_lower_32.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_engine_lower_32.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tTransmit engine for completion requests and pre-formatted\n// PCIe read/write data. Muxes traffic for the AXI interface on the Xilinx PCIe \n// Endpoint core.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: Very good PCIe header reference:\n// http://www.pzk-agro.com/0321156307_ch04lev1sec5.html#ch04lev4sec14\n// Also byte swap each payload word due to Xilinx incorrect mapping, see\n// http://forums.xilinx.com/t5/PCI-Express/PCI-Express-payload-required-to-be-Big-Endian-by-specification/td-p/285551\n//-----------------------------------------------------------------------------\n`define FMT_TXENGLWR32_CPLD\t\t7'b10_01010\n\n`define S_TXENGLWR32_IDLE\t\t4'd0\n`define S_TXENGLWR32_CPLD_0\t\t4'd1\n`define S_TXENGLWR32_CPLD_1\t\t4'd2\n`define S_TXENGLWR32_CPLD_2\t\t4'd3\n`define S_TXENGLWR32_CPLD_3\t\t4'd4\n`define S_TXENGLWR32_CPLD_4\t\t4'd5\n`define S_TXENGLWR32_MEM_0\t\t4'd6\n`define S_TXENGLWR32_RD_0\t\t4'd7\n`define S_TXENGLWR32_RD_1\t\t4'd8\n`define S_TXENGLWR32_WR_0\t\t4'd9\n`define S_TXENGLWR32_WR_1\t\t4'd10\n`define S_TXENGLWR32_WR_2\t\t4'd11\n\nmodule tx_engine_lower_32 #(\n\tparameter C_PCI_DATA_WIDTH = 9'd32,\n\tparameter C_NUM_CHNL = 4'd12\n)\n(\n\tinput CLK,\n\tinput RST,\n\n\tinput [15:0] CONFIG_COMPLETER_ID,\n\n\toutput [C_PCI_DATA_WIDTH-1:0] TX_DATA,\t\t\t\t// AXI data output \n\toutput [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,\t// AXI data keep\n\toutput TX_TLP_END_FLAG,\t\t\t\t\t\t\t\t// AXI data last\n output TX_TLP_START_FLAG, // AXI data start\n\toutput TX_DATA_VALID,\t\t\t\t\t\t\t\t// AXI data valid\n\toutput S_AXIS_SRC_DSC,\t\t\t\t\t\t\t\t// AXI data discontinue\n\tinput TX_DATA_READY,\t\t\t\t\t\t\t\t// AXI ready for data\n\n\tinput COMPL_REQ,\t\t\t\t\t\t\t\t\t// RX Engine request for completion\n\toutput COMPL_DONE,\t\t\t\t\t\t\t\t\t// Completion done\n\tinput [2:0] REQ_TC,\n\tinput REQ_TD,\n\tinput REQ_EP,\n\tinput [1:0] REQ_ATTR,\n\tinput [9:0] REQ_LEN,\n\tinput [15:0] REQ_ID,\n\tinput [7:0] REQ_TAG,\n\tinput [3:0] REQ_BE,\n\tinput [29:0] REQ_ADDR,\n\tinput [31:0] REQ_DATA,\n\toutput [31:0] REQ_DATA_SENT,\t\t\t\t\t\t// Actual completion data sent\n\n\tinput [C_PCI_DATA_WIDTH-1:0] FIFO_DATA,\t\t \t\t// Read/Write FIFO requests + data\n\tinput FIFO_EMPTY, \t\t\t\t\t\t\t\t\t// Read/Write FIFO is empty\n\toutput FIFO_REN, \t\t\t\t\t\t\t\t\t// Read/Write FIFO read enable\n\toutput [C_NUM_CHNL-1:0] WR_SENT \t\t\t\t\t// Pulsed at channel pos when write request sent\n);\n\n\nreg\t\t[11:0]\t\t\t\t\t\trByteCount=0;\nreg\t\t[6:0]\t\t\t\t\t\trLowerAddr=0;\n\nreg\t\t\t\t\t\t\t\t\trFifoRen=0, _rFifoRen=0;\nreg\t\t\t\t\t\t\t\t\trFifoRenIssued=0, _rFifoRenIssued=0;\nreg\t\t\t\t\t\t\t\t\trFifoDataEmpty=1, _rFifoDataEmpty=1;\nreg\t\t[2:0]\t\t\t\t\t\trFifoDataValid=0, _rFifoDataValid=0;\nreg\t\t[(3*C_PCI_DATA_WIDTH)-1:0]\trFifoData={3*C_PCI_DATA_WIDTH{1'd0}}, _rFifoData={3*C_PCI_DATA_WIDTH{1'd0}};\nwire\t[C_PCI_DATA_WIDTH-1:0]\t\twFifoData = (rFifoData>>(C_PCI_DATA_WIDTH*(!rFifoRen)))>>(C_PCI_DATA_WIDTH*(!rFifoRenIssued));\nwire\t\t\t\t\t\t\t\twFifoDataValid = (rFifoDataValid>>(!rFifoRen))>>(!rFifoRenIssued);\n\n\nreg\t\t[3:0]\t\t\t\t\t\trState=`S_TXENGLWR32_IDLE, _rState=`S_TXENGLWR32_IDLE;\nreg\t\t\t\t\t\t\t\t\trComplDone=0, _rComplDone=0;\nreg\t\t\t\t\t\t\t\t\trValid=0, _rValid=0;\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trData={C_PCI_DATA_WIDTH{1'd0}}, _rData={C_PCI_DATA_WIDTH{1'd0}};\nreg\t\t\t\t\t\t\t\t\trLast=0, _rLast=0;\nreg\t\t[C_NUM_CHNL-1:0]\t\t\trDone=0, _rDone=0;\nreg\t\t[9:0]\t\t\t\t\t\trLen=0, _rLen=0;\nreg\t\t[3:0]\t\t\t\t\t\trChnl=0, _rChnl=0;\nreg\t\t\t\t\t\t\t\t\tr3DW=0, _r3DW=0;\nreg\t\t\t\t\t\t\t\t\trRNW=0, _rRNW=0;\nreg\t\t\t\t\t\t\t\t\trIsLast=0, _rIsLast=0;\n\n\nassign TX_DATA = rData;\nassign TX_DATA_BYTE_ENABLE = {4'hF};\nassign TX_TLP_END_FLAG = rLast;\nassign TX_TLP_START_FLAG = 1'b0;\nassign TX_DATA_VALID = rValid;\nassign S_AXIS_SRC_DSC = 1'b0;\n\nassign COMPL_DONE = rComplDone;\nassign REQ_DATA_SENT = {rData[7:0], rData[15:8], rData[23:16], rData[31:24]};\n\nassign FIFO_REN = rFifoRen;\nassign WR_SENT = rDone;\n\n\n// Calculate byte count based on byte enable\nalways @ (REQ_BE) begin\n\tcasex (REQ_BE)\n\t4'b1xx1 : rByteCount = 12'h004;\n\t4'b01x1 : rByteCount = 12'h003;\n\t4'b1x10 : rByteCount = 12'h003;\n\t4'b0011 : rByteCount = 12'h002;\n\t4'b0110 : rByteCount = 12'h002;\n\t4'b1100 : rByteCount = 12'h002;\n\t4'b0001 : rByteCount = 12'h001;\n\t4'b0010 : rByteCount = 12'h001;\n\t4'b0100 : rByteCount = 12'h001;\n\t4'b1000 : rByteCount = 12'h001;\n\t4'b0000 : rByteCount = 12'h001;\n\tendcase\nend\n\n\n// Calculate lower address based on byte enable\nalways @ (REQ_BE or REQ_ADDR) begin\n\tcasex (REQ_BE)\n\t4'b0000 : rLowerAddr = {REQ_ADDR[4:0], 2'b00};\n\t4'bxxx1 : rLowerAddr = {REQ_ADDR[4:0], 2'b00};\n\t4'bxx10 : rLowerAddr = {REQ_ADDR[4:0], 2'b01};\n\t4'bx100 : rLowerAddr = {REQ_ADDR[4:0], 2'b10};\n\t4'b1000 : rLowerAddr = {REQ_ADDR[4:0], 2'b11};\n\tendcase\nend\n\n\n// Read in the pre-formatted PCIe data.\nalways @ (posedge CLK) begin\n\trFifoRenIssued <= #1 (RST ? 1'd0 : _rFifoRenIssued);\n\trFifoDataValid <= #1 (RST ? 1'd0 : _rFifoDataValid);\n\trFifoDataEmpty <= #1 (RST ? 1'd1 : _rFifoDataEmpty);\n\trFifoData <= #1 _rFifoData;\nend\n\nalways @ (*) begin\n\t_rFifoRenIssued = rFifoRen;\n\t_rFifoDataEmpty = (rFifoRen ? FIFO_EMPTY : rFifoDataEmpty);\n\n\tif (rFifoRenIssued) begin\n\t\t_rFifoData = ((rFifoData<<(C_PCI_DATA_WIDTH)) | FIFO_DATA);\n\t\t_rFifoDataValid = ((rFifoDataValid<<1) | (!rFifoDataEmpty));\n\tend\n\telse begin\n\t\t_rFifoData = rFifoData;\n\t\t_rFifoDataValid = rFifoDataValid;\n\tend\nend\n\n\n// Multiplex completion requests and read/write pre-formatted PCIe data onto\n// the AXI PCIe Endpoint interface. Remember that TX_DATA_READY may drop at\n// *any* time during transmission. So be sure to buffer enough data to \n// accommodate starts and stops.\nalways @ (posedge CLK) begin\n\trState <= #1 (RST ? `S_TXENGLWR32_IDLE : _rState);\n\trComplDone <= #1 (RST ? 1'd0 : _rComplDone);\n\trValid <= #1 (RST ? 1'd0 : _rValid);\n\trFifoRen <= #1 (RST ? 1'd0 : _rFifoRen);\n\trDone <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rDone);\n\trData <= #1 _rData;\n\trLast <= #1 _rLast;\n\trChnl <= #1 _rChnl;\n\tr3DW <= #1 _r3DW;\n\trRNW <= #1 _rRNW;\n\trLen <= #1 _rLen;\n\trIsLast <= #1 _rIsLast;\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\t_rComplDone = rComplDone;\n\t_rValid = rValid;\n\t_rFifoRen = rFifoRen;\n\t_rData = rData;\n\t_rLast = rLast;\n\t_rChnl = rChnl;\n\t_rDone = rDone;\n\t_r3DW = r3DW;\n\t_rRNW = rRNW;\n\t_rLen = rLen;\n\t_rIsLast = rIsLast;\n\t\n\tcase (rState) \n\n\t`S_TXENGLWR32_IDLE : begin\n\t\t_rFifoRen = (TX_DATA_READY & !COMPL_REQ);\n\t\t_rDone = 0;\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rData = {wFifoData[31:20], 4'd0, wFifoData[15:0]}; // Revert the reserved 4 bits back to 0.\n\t\t\t_rValid = (!COMPL_REQ & wFifoDataValid);\n\t\t\t_rLast = 0;\n\t\t\t_rChnl = wFifoData[19:16]; // CHNL buried in header\n\t\t\t_r3DW = !wFifoData[29]; // !64 bit\n\t\t\t_rRNW = !wFifoData[30]; // !Write TLP\n\t\t\t_rLen = wFifoData[9:0]; // LEN\n\t\t\tif (COMPL_REQ) // PIO read completions\n\t\t\t\t_rState = `S_TXENGLWR32_CPLD_0;\n\t\t\telse if (wFifoDataValid) // Read FIFO data if it's ready\n\t\t\t\t_rState = `S_TXENGLWR32_MEM_0;\n\t\tend\n\tend\n\n\t`S_TXENGLWR32_CPLD_0 : begin\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rValid = 1;\n\t\t\t_rLast = 0;\n\t\t\t_rData = {1'b0, `FMT_TXENGLWR32_CPLD, 1'b0, REQ_TC, 4'b0, REQ_TD,\n\t\t\t\t\t\tREQ_EP, REQ_ATTR, 2'b0, REQ_LEN};\n\t\t\t_rState = `S_TXENGLWR32_CPLD_1;\n\t\tend\n\tend\n\n\t`S_TXENGLWR32_CPLD_1 : begin\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rValid = 1;\n\t\t\t_rLast = 0;\n\t\t\t_rData = {CONFIG_COMPLETER_ID[15:3], 3'b0, 3'b0, 1'b0, rByteCount};\n\t\t\t_rState = `S_TXENGLWR32_CPLD_2;\n\t\tend\n\tend\n\n\t`S_TXENGLWR32_CPLD_2 : begin\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rValid = 1;\n\t\t\t_rLast = 0;\n\t\t\t_rData = {REQ_ID, REQ_TAG, 1'b0, rLowerAddr};\n\t\t\t_rState = `S_TXENGLWR32_CPLD_3;\n\t\tend\n\tend\n\n\t`S_TXENGLWR32_CPLD_3 : begin\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rComplDone = 1;\n\t\t\t_rValid = 1;\n\t\t\t_rLast = 1;\n\t\t\t_rData = {REQ_DATA[7:0], REQ_DATA[15:8], REQ_DATA[23:16], REQ_DATA[31:24]};\n\t\t\t_rState = `S_TXENGLWR32_CPLD_4;\n\t\tend\n\tend\n\n\t`S_TXENGLWR32_CPLD_4 : begin\n\t\t// Just wait a cycle for the COMP_REQ to drop.\n\t\t_rComplDone = 0;\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rValid = 0;\n\t\t\t_rState = `S_TXENGLWR32_IDLE;\n\t\tend\n\tend\n\n\t`S_TXENGLWR32_MEM_0 : begin\n\t\t_rFifoRen = TX_DATA_READY;\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rData = wFifoData;\n\t\t\t_rValid = 1;\n\t\t\t_rLast = 0;\n\t\t\t_rState = (rRNW ? `S_TXENGLWR32_RD_0 : `S_TXENGLWR32_WR_0);\n\t\tend\n\tend\n\n\t`S_TXENGLWR32_RD_0 : begin\n\t\t_rFifoRen = TX_DATA_READY;\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rData = wFifoData;\n\t\t\t_rValid = 1;\n\t\t\t_rLast = r3DW;\n\t\t\t_rState = (r3DW ? `S_TXENGLWR32_IDLE : `S_TXENGLWR32_RD_1);\n\t\tend\n\tend\n\n\t`S_TXENGLWR32_RD_1 : begin\n\t\t_rFifoRen = TX_DATA_READY;\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rData = wFifoData;\n\t\t\t_rValid = 1;\n\t\t\t_rLast = 1;\n\t\t\t_rState = `S_TXENGLWR32_IDLE;\n\t\tend\n\tend\n\t\n\t`S_TXENGLWR32_WR_0 : begin\n\t\t_rFifoRen = TX_DATA_READY;\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rDone = (1'd1<>(C_PCI_DATA_WIDTH*(!rFifoRen)))>>(C_PCI_DATA_WIDTH*(!rFifoRenIssued));\nwire\t\t\t\t\t\t\t\twFifoDataValid = (rFifoDataValid>>(!rFifoRen))>>(!rFifoRenIssued);\n\n\nreg\t\t[2:0]\t\t\t\t\t\trState=`S_TXENGLWR64_IDLE, _rState=`S_TXENGLWR64_IDLE;\nreg\t\t\t\t\t\t\t\t\trComplDone=0, _rComplDone=0;\nreg\t\t\t\t\t\t\t\t\trValid=0, _rValid=0;\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trData={C_PCI_DATA_WIDTH{1'd0}}, _rData={C_PCI_DATA_WIDTH{1'd0}};\nreg\t\t\t\t\t\t\t\t\trLast=0, _rLast=0;\nreg rFirst=0, _rFirst=0;\nreg\t\t\t\t\t\t\t\t\trKeep=0, _rKeep=0;\nreg\t\t[C_NUM_CHNL-1:0]\t\t\trDone=0, _rDone=0;\nreg\t\t[9:0]\t\t\t\t\t\trInitLen=0, _rInitLen=0;\nreg\t\t[9:0]\t\t\t\t\t\trLen=0, _rLen=0;\nreg\t\t[3:0]\t\t\t\t\t\trChnl=0, _rChnl=0;\nreg\t\t\t\t\t\t\t\t\tr3DW=0, _r3DW=0;\nreg\t\t\t\t\t\t\t\t\trIsLast=0, _rIsLast=0;\nreg \t\t\t\t\t\t\t\trInitIsLast=0, _rInitIsLast=0;\nwire [31:0] wReqDataSwap;\n\nassign TX_DATA = rData;\nassign TX_DATA_BYTE_ENABLE = {{4{rKeep}}, 4'hF};\nassign TX_TLP_END_FLAG = rLast;\nassign TX_TLP_START_FLAG = rFirst;\nassign TX_DATA_VALID = rValid;\nassign S_AXIS_SRC_DSC = 0;\n\nassign COMPL_DONE = rComplDone;\n\ngenerate\nif(C_ALTERA == 1'b1) begin : altera_data\n\tassign REQ_DATA_SENT = rData[63:32];\n\tassign wReqDataSwap = REQ_DATA[31:0];\nend\nelse begin : xilinx_data\n\tassign REQ_DATA_SENT = {rData[39:32], rData[47:40], rData[55:48], rData[63:56]};\n\tassign wReqDataSwap = {REQ_DATA[7:0], REQ_DATA[15:8], REQ_DATA[23:16], REQ_DATA[31:24]};\nend\nendgenerate\n\nassign FIFO_REN = rFifoRen;\nassign WR_SENT = rDone;\n\n\n// Calculate byte count based on byte enable\nalways @ (REQ_BE) begin\n\tcasex (REQ_BE)\n\t4'b1xx1 : rByteCount = 12'h004;\n\t4'b01x1 : rByteCount = 12'h003;\n\t4'b1x10 : rByteCount = 12'h003;\n\t4'b0011 : rByteCount = 12'h002;\n\t4'b0110 : rByteCount = 12'h002;\n\t4'b1100 : rByteCount = 12'h002;\n\t4'b0001 : rByteCount = 12'h001;\n\t4'b0010 : rByteCount = 12'h001;\n\t4'b0100 : rByteCount = 12'h001;\n\t4'b1000 : rByteCount = 12'h001;\n\t4'b0000 : rByteCount = 12'h001;\n\tendcase\nend\n\n\n// Calculate lower address based on byte enable\nalways @ (REQ_BE or REQ_ADDR) begin\n\tcasex (REQ_BE)\n\t4'b0000 : rLowerAddr = {REQ_ADDR[4:0], 2'b00};\n\t4'bxxx1 : rLowerAddr = {REQ_ADDR[4:0], 2'b00};\n\t4'bxx10 : rLowerAddr = {REQ_ADDR[4:0], 2'b01};\n\t4'bx100 : rLowerAddr = {REQ_ADDR[4:0], 2'b10};\n\t4'b1000 : rLowerAddr = {REQ_ADDR[4:0], 2'b11};\n\tendcase\nend\n\n\n// Read in the pre-formatted PCIe data.\nalways @ (posedge CLK) begin\n\trFifoRenIssued <= #1 (RST ? 1'd0 : _rFifoRenIssued);\n\trFifoDataValid <= #1 (RST ? 1'd0 : _rFifoDataValid);\n\trFifoDataEmpty <= #1 (RST ? 1'd1 : _rFifoDataEmpty);\n\trFifoData <= #1 _rFifoData;\nend\n\nalways @ (*) begin\n\t_rFifoRenIssued = rFifoRen;\n\t_rFifoDataEmpty = (rFifoRen ? FIFO_EMPTY : rFifoDataEmpty);\n\n\tif (rFifoRenIssued) begin\n\t\t_rFifoData = ((rFifoData<<(C_PCI_DATA_WIDTH)) | FIFO_DATA);\n\t\t_rFifoDataValid = ((rFifoDataValid<<1) | (!rFifoDataEmpty));\n\tend\n\telse begin\n\t\t_rFifoData = rFifoData;\n\t\t_rFifoDataValid = rFifoDataValid;\n\tend\nend\n\n\n// Multiplex completion requests and read/write pre-formatted PCIe data onto\n// the AXI PCIe Endpoint interface. Remember that TX_DATA_READY may drop at\n// *any* time during transmission. So be sure to buffer enough data to \n// accommodate starts and stops.\nalways @ (posedge CLK) begin\n\trState <= #1 (RST ? `S_TXENGLWR64_IDLE : _rState);\n\trComplDone <= #1 (RST ? 1'd0 : _rComplDone);\n\trValid <= #1 (RST ? 1'd0 : _rValid);\n\trFifoRen <= #1 (RST ? 1'd0 : _rFifoRen);\n\trDone <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rDone);\n\trData <= #1 _rData;\n\trLast <= #1 _rLast;\n\trKeep <= #1 _rKeep;\n\trChnl <= #1 _rChnl;\n\tr3DW <= #1 _r3DW;\n\trLen <= #1 _rLen;\n\trInitLen <= #1 _rInitLen;\n\trIsLast <= #1 _rIsLast;\n\trInitIsLast <= #1 _rInitIsLast;\n rFirst <= #1 _rFirst;\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\t_rComplDone = rComplDone;\n\t_rValid = rValid;\n\t_rFifoRen = rFifoRen;\n\t_rData = rData;\n\t_rLast = rLast;\n\t_rKeep = rKeep;\n\t_rChnl = rChnl;\n\t_rDone = rDone;\n\t_r3DW = r3DW;\n\t_rLen = rLen;\n\t_rInitLen = rInitLen;\n\t_rIsLast = rIsLast;\n\t_rInitIsLast = rInitIsLast;\n\t_rFirst = rFirst;\n\tcase (rState) \n\n\t`S_TXENGLWR64_IDLE : begin\n\t\t_rFifoRen = (TX_DATA_READY & !COMPL_REQ);\n\t\t_rDone = 0;\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rData = {wFifoData[63:20], 4'd0, wFifoData[15:0]}; // Revert the reserved 4 bits back to 0.\n\t\t\t_rValid = (!COMPL_REQ & wFifoDataValid);\n _rFirst = 1;\n\t\t\t_rLast = 0;\n\t\t\t_rKeep = 1;\n\t\t\t_rChnl = wFifoData[19:16]; // CHNL buried in header\n\t\t\t_r3DW = !wFifoData[29]; // !64 bit\n\t\t\t_rInitLen = wFifoData[9:0]; // LEN\n\t\t\t_rInitIsLast = (!wFifoData[29] & !wFifoData[36]); // !64 bit && !(LEN != 1)\n\t\t\tif (COMPL_REQ) // PIO read completions\n\t\t\t\t_rState = `S_TXENGLWR64_CPLD_0;\n\t\t\telse if (wFifoDataValid) // Read FIFO data if it's ready\n\t\t\t\t_rState = (wFifoData[30] ? `S_TXENGLWR64_WR_0 : `S_TXENGLWR64_RD_0); // WRITE TLP?\n\t\tend\n\tend\n\n\t`S_TXENGLWR64_CPLD_0 : begin\n\t\tif (TX_DATA_READY) begin // Check for throttling\n _rFirst = 1;\n\t\t\t_rValid = 1;\n\t\t\t_rLast = 0;\n\t\t\t_rKeep = 1;\n\t\t\t_rData = {CONFIG_COMPLETER_ID[15:3], 3'b0, 3'b0, 1'b0, rByteCount,\t\t\t// DW1\n\t\t\t\t\t\t1'b0, `FMT_TXENGLWR64_CPLD, 1'b0, REQ_TC, 4'b0, REQ_TD,\n\t\t\t\t\t\tREQ_EP, REQ_ATTR, 2'b0, REQ_LEN};\t\t\t\t\t\t\t\t// DW0\n\t\t\t_rState = `S_TXENGLWR64_CPLD_1;\n\t\tend\n\tend\n\n\t`S_TXENGLWR64_CPLD_1 : begin\n\t\t// Send rest of header and requested data\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rComplDone = 1;\n\t\t\t_rValid = 1;\n _rFirst = 0;\n\t\t\t_rLast = 1;\n\t\t\t_rKeep = 1;\n\t\t\t_rData = {wReqDataSwap,\t\t\t\t\t\t\t\t\t\t\t\t\t\t// DW3\n\t\t\t\t\t REQ_ID, REQ_TAG, 1'b0, rLowerAddr};\t\t\t\t\t\t\t\t// DW2\n\t\t\t_rState = `S_TXENGLWR64_CPLD_2;\n\t\tend\n\tend\n\n\t`S_TXENGLWR64_CPLD_2 : begin\n\t\t// Just wait a cycle for the COMP_REQ to drop.\n\t\t_rComplDone = 0;\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rValid = 0;\n _rFirst = 0;\n\t\t\t_rState = `S_TXENGLWR64_IDLE;\n\t\tend\n\tend\n\n\t`S_TXENGLWR64_RD_0 : begin\n\t\t_rFifoRen = TX_DATA_READY;\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rData = wFifoData;\n\t\t\t_rValid = 1;\n _rFirst = 0;\n\t\t\t_rLast = 1;\n\t\t\t_rKeep = !r3DW;\n\t\t\t_rState = `S_TXENGLWR64_IDLE;\n\t\tend\n\tend\n\t\n\t`S_TXENGLWR64_WR_0 : begin\n\t\t_rFifoRen = TX_DATA_READY;\n\t\tif (TX_DATA_READY) begin // Check for throttling\n\t\t\t_rDone = (1'd1<>(rChnlNextNext));\nreg\t\t\t\t\t\t\t\t\trReq=0, _rReq=0;\nwire\t\t\t\t\t\t\t\twReq = (REQ_ALL>>(rReqChnl));\nreg\t\t\t\t\t\t\t\t\trReqChnlNextUpdated=0, _rReqChnlNextUpdated=0;\n\n\nassign REQ = rReq;\nassign CHNL = rReqChnl;\n\n\n// Search for the next request so that we can move onto it immediately after\n// the current channel has released its request.\nalways @ (posedge CLK) begin\n\trReq <= #1 (RST ? 1'd0 : _rReq);\n\trReqChnl <= #1 (RST ? 4'd0 : _rReqChnl);\n\trReqChnlNext <= #1 (RST ? 4'd0 : _rReqChnlNext);\n\trChnlNext <= #1 (RST ? 4'd0 : _rChnlNext);\n\trChnlNextNext <= #1 (RST ? 4'd0 : _rChnlNextNext);\n\trChnlNextDfrnt <= #1 (RST ? 1'd0 : _rChnlNextDfrnt);\n\trChnlNextNextOn <= #1 (RST ? 1'd0 : _rChnlNextNextOn);\n\trReqChnlsSame <= #1 (RST ? 1'd0 : _rReqChnlsSame);\n\trReqChnlNextUpdated <= #1 (RST ? 1'd1 : _rReqChnlNextUpdated);\nend\n\nalways @ (*) begin\n\t// Go through each channel (RR), looking for requests\n\t_rChnlNextNextOn = wChnlNextNextOn;\n\t_rChnlNext = rChnlNextNext;\n\t_rChnlNextNext = (rChnlNextNext == C_NUM_CHNL - 1 ? 4'd0 : rChnlNextNext + 1'd1);\n\t_rChnlNextDfrnt = (rChnlNextNext != rReqChnl);\n\t_rReqChnlsSame = (rReqChnlNext == rReqChnl);\n\n\t// Save ready channel if it is not the same channel we're currently on\n\tif (rChnlNextNextOn & rChnlNextDfrnt & rReqChnlsSame & !rReqChnlNextUpdated) begin\n\t\t_rReqChnlNextUpdated = 1;\n\t\t_rReqChnlNext = rChnlNext;\n\tend\n\telse begin\n\t\t_rReqChnlNextUpdated = 0;\n\t\t_rReqChnlNext = rReqChnlNext;\n\tend\n\t\n\t// Assign the new channel\n\t_rReq = wReq;\n\t_rReqChnl = (!rReq ? rReqChnlNext : rReqChnl);\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_upper_128.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_engine_upper_128.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tFormats read/write requests into PCI packets and adds \n// them to a FIFO. The FIFO will be read by the tx_engine_lower core and transmitted\n// to the attached PCIe Endpoint.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n// Additional Comments: Very good PCIe header reference:\n// http://www.pzk-agro.com/0321156307_ch04lev1sec5.html#ch04lev4sec14\n// Also byte swap each payload word due to Xilinx incorrect mapping, see\n// http://forums.xilinx.com/t5/PCI-Express/PCI-Express-payload-required-to-be-Big-Endian-by-specification/td-p/285551\n//-----------------------------------------------------------------------------\n`define FMT_TXENGUPR128_WR32\t7'b10_00000\n`define FMT_TXENGUPR128_RD32\t7'b00_00000\n`define FMT_TXENGUPR128_WR64\t7'b11_00000\n`define FMT_TXENGUPR128_RD64\t7'b01_00000\n\n`define S_TXENGUPR128_MAIN_IDLE\t\t1'b0\n`define S_TXENGUPR128_MAIN_WR\t\t1'b1\n\n`define S_TXENGUPR128_CAP_RD_WR\t\t4'b0001\n`define S_TXENGUPR128_CAP_WR_RD\t\t4'b0010\n`define S_TXENGUPR128_CAP_CAP\t\t4'b0100\n`define S_TXENGUPR128_CAP_REL\t\t4'b1000\n\nmodule tx_engine_upper_128 #(\n\tparameter C_PCI_DATA_WIDTH = 9'd128,\n\tparameter C_NUM_CHNL = 4'd12,\n\tparameter C_FIFO_DEPTH = 512,\n\tparameter C_TAG_WIDTH = 5, \t\t\t\t\t\t\t// Number of outstanding requests \n parameter C_ALTERA = 1'b1,\n\t// Local parameters\n\tparameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),\t\n\tparameter C_MAX_ENTRIES = (11'd128*11'd8/C_PCI_DATA_WIDTH),\n\tparameter C_DATA_DELAY = 3'd6 // Delays read/write params to accommodate tx_port_buffer delay and tx_engine_formatter delay.\n)\n(\n\tinput CLK,\n\tinput RST,\n\n\tinput [15:0] CONFIG_COMPLETER_ID,\n\tinput [2:0] CONFIG_MAX_PAYLOAD_SIZE,\t\t\t\t\t\t// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B\n\n\tinput [C_NUM_CHNL-1:0] WR_REQ,\t\t\t\t\t\t// Write request\n\tinput [(C_NUM_CHNL*64)-1:0] WR_ADDR,\t\t\t\t// Write address\n\tinput [(C_NUM_CHNL*10)-1:0] WR_LEN,\t\t\t\t\t// Write data length\n\tinput [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA,\t// Write data\n\toutput [C_NUM_CHNL-1:0] WR_DATA_REN,\t\t\t\t// Write data read enable\n\toutput [C_NUM_CHNL-1:0] WR_ACK,\t\t\t\t\t\t// Write request has been accepted\n\n\tinput [C_NUM_CHNL-1:0] RD_REQ,\t\t\t\t\t\t// Read request\n\tinput [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL,\t\t\t\t// Read request channel for scatter gather lists\n\tinput [(C_NUM_CHNL*64)-1:0] RD_ADDR,\t\t\t\t// Read request address\n\tinput [(C_NUM_CHNL*10)-1:0] RD_LEN,\t\t\t\t\t// Read request length\n\toutput [C_NUM_CHNL-1:0] RD_ACK,\t\t\t\t\t\t// Read request has been accepted\n\n\toutput [5:0] INT_TAG,\t\t\t\t\t\t\t\t// Internal tag to exchange with external\n\toutput INT_TAG_VALID,\t\t\t\t\t\t\t\t// High to signal tag exchange \n\tinput [C_TAG_WIDTH-1:0] EXT_TAG,\t\t\t\t\t// External tag to provide in exchange for internal tag\n\tinput EXT_TAG_VALID,\t\t\t\t\t\t\t\t// High to signal external tag is valid\n\n output \t\t\t\t TX_ENG_RD_REQ_SENT, // Read completion request issued\n input \t\t\t\t RXBUF_SPACE_AVAIL,\n\n\toutput [C_PCI_DATA_WIDTH-1:0] FIFO_DATA,\t\t \t// Formatted read/write request data\n\tinput [C_FIFO_DEPTH_WIDTH-1:0] FIFO_COUNT, \t\t\t// Formatted read/write FIFO count\n\toutput FIFO_WEN \t\t\t\t\t\t\t\t\t// Formatted read/write FIFO read enable\t\n);\n\n`include \"common_functions.v\"\n\nreg\t\t\t\t\t\t\t\t\trMainState=`S_TXENGUPR128_MAIN_IDLE, _rMainState=`S_TXENGUPR128_MAIN_IDLE;\nreg\t\t\t\t\t\t\t\t\trCountIsWr=0, _rCountIsWr=0;\nreg\t\t[9:0]\t\t\t\t\t\trCountLen=0, _rCountLen=0;\nreg\t\t[3:0]\t\t\t\t\t\trCountChnl=0, _rCountChnl=0;\nreg\t\t[C_TAG_WIDTH-1:0]\t\t\trCountTag=0, _rCountTag=0;\nreg\t\t[61:0]\t\t\t\t\t\trCountAddr=62'd0, _rCountAddr=62'd0;\nreg\t\t\t\t\t\t\t\t\trCountAddr64=0, _rCountAddr64=0;\nreg\t\t[9:0]\t\t\t\t\t\trCount=0, _rCount=0;\nreg\t\t\t\t\t\t\t\t\trCountDone=0, _rCountDone=0;\nreg\t\t\t\t\t\t\t\t\trCountValid=0, _rCountValid=0;\nreg\t\t[C_NUM_CHNL-1:0]\t\t\trWrDataRen=0, _rWrDataRen=0;\n\nreg \t\t\t\t\t\t\t\trTxEngRdReqAck, _rTxEngRdReqAck;\n \nwire\t\t\t\t\t\t\t\twRdReq;\nwire\t[3:0]\t\t\t\t\t\twRdReqChnl;\nwire\t\t\t\t\t\t\t\twWrReq;\nwire\t[3:0]\t\t\t\t\t\twWrReqChnl;\nwire \t\t\t\t\t\t\t\twRdAck;\n\nwire\t[3:0]\t\t\t\t\t\twCountChnl;\nwire \t[11:0] \t\t\t\t\t\twCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire\nwire\t[63:0]\t\t\t\t\t\twRdAddr = (RD_ADDR>>(wRdReqChnl*64));\nwire\t[9:0]\t\t\t\t\t\twRdLen = (RD_LEN>>(wRdReqChnl*10));\nwire\t[1:0]\t\t\t\t\t\twRdSgChnl = (RD_SG_CHNL>>(wRdReqChnl*2));\nwire\t[63:0]\t\t\t\t\t\twWrAddr = (WR_ADDR>>(wWrReqChnl*64));\nwire\t[9:0]\t\t\t\t\t\twWrLen = (WR_LEN>>(wWrReqChnl*10));\nwire\t[C_PCI_DATA_WIDTH-1:0]\t\twWrData = (WR_DATA>>wCountChnlShiftDW);\nwire\t[C_PCI_DATA_WIDTH-1:0]\t\twWrDataSwap;\n\nreg\t\t[3:0]\t\t\t\t\t\trRdChnl=0, _rRdChnl=0;\nreg\t\t[61:0]\t\t\t\t\t\trRdAddr=62'd0, _rRdAddr=62'd0;\nreg\t\t[9:0]\t\t\t\t\t\trRdLen=0, _rRdLen=0;\nreg\t\t[1:0]\t\t\t\t\t\trRdSgChnl=0, _rRdSgChnl=0;\nreg\t\t[3:0]\t\t\t\t\t\trWrChnl=0, _rWrChnl=0;\nreg\t\t[61:0]\t\t\t\t\t\trWrAddr=62'd0, _rWrAddr=62'd0;\nreg\t\t[9:0]\t\t\t\t\t\trWrLen=0, _rWrLen=0;\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};\n\ngenerate\nif(C_ALTERA == 1'b1) begin : altera_data\n\tassign wWrDataSwap = rWrData;\nend\nelse begin : xilinx_data\n\tassign wWrDataSwap = {rWrData[103:96], rWrData[111:104], rWrData[119:112], rWrData[127:120],\n\t\t\t\t\t\t\trWrData[71:64], rWrData[79:72], rWrData[87:80], rWrData[95:88],\n\t\t\t\t\t\t\trWrData[39:32], rWrData[47:40], rWrData[55:48], rWrData[63:56],\n\t\t\t\t\t\t\trWrData[07:00], rWrData[15:08], rWrData[23:16], rWrData[31:24]};\nend\nendgenerate\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[3:0]\t\t\t\t\t\trCapState=`S_TXENGUPR128_CAP_RD_WR, _rCapState=`S_TXENGUPR128_CAP_RD_WR;\nreg\t\t[C_NUM_CHNL-1:0]\t\t\trRdAck=0, _rRdAck=0;\nreg\t\t[C_NUM_CHNL-1:0]\t\t\trWrAck=0, _rWrAck=0;\nreg\t\t\t\t\t\t\t\t\trIsWr=0, _rIsWr=0;\nreg\t\t[5:0]\t\t\t\t\t\trCapChnl=0, _rCapChnl=0;\nreg\t\t[61:0]\t\t\t\t\t\trCapAddr=62'd0, _rCapAddr=62'd0;\nreg\t\t\t\t\t\t\t\t\trCapAddr64=0, _rCapAddr64=0;\nreg\t\t[9:0]\t\t\t\t\t\trCapLen=0, _rCapLen=0;\nreg\t\t\t\t\t\t\t\t\trCapIsWr=0, _rCapIsWr=0;\nreg\t\t\t\t\t\t\t\t\trExtTagReq=0, _rExtTagReq=0;\nreg\t\t[C_TAG_WIDTH-1:0]\t\t\trExtTag=0, _rExtTag=0;\n\nreg\t\t[C_FIFO_DEPTH_WIDTH-1:0]\trFifoCount=0, _rFifoCount=0;\nreg\t\t[9:0]\t\t\t\t\t\trMaxEntries=0, _rMaxEntries=0;\nreg\t\t\t\t\t\t\t\t\trSpaceAvail=0, _rSpaceAvail=0;\n\nreg\t\t[C_DATA_DELAY-1:0]\t\t\trWnR=0, _rWnR=0;\nreg\t\t[(C_DATA_DELAY*4)-1:0]\t\trChnl=0, _rChnl=0;\nreg\t\t[(C_DATA_DELAY*8)-1:0]\t\trTag=0, _rTag=0;\nreg\t\t[(C_DATA_DELAY*62)-1:0]\t\trAddr=0, _rAddr=0;\nreg\t\t[C_DATA_DELAY-1:0]\t\t\trAddr64=0, _rAddr64=0;\nreg\t\t[(C_DATA_DELAY*10)-1:0]\t\trLen=0, _rLen=0;\nreg\t\t[C_DATA_DELAY-1:0]\t\t\trLenEQ1=0, _rLenEQ1=0;\nreg\t\t[C_DATA_DELAY-1:0]\t\t\trValid=0, _rValid=0;\n\n\nassign WR_DATA_REN = rWrDataRen;\nassign WR_ACK = rWrAck;\nassign RD_ACK = rRdAck;\n\nassign INT_TAG = {rRdSgChnl, rRdChnl};\nassign INT_TAG_VALID = rExtTagReq;\n\nassign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;\nassign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);\n\n// Search for the next request so that we can move onto it immediately after\n// the current channel has released its request.\ntx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));\ntx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));\n\n\n// Buffer shift-selected channel request signals and FIFO data.\nalways @ (posedge CLK) begin\n\trRdChnl <= #1 _rRdChnl;\n\trRdAddr <= #1 _rRdAddr;\n\trRdLen <= #1 _rRdLen;\n\trRdSgChnl <= #1 _rRdSgChnl;\n\trWrChnl <= #1 _rWrChnl;\n\trWrAddr <= #1 _rWrAddr;\n\trWrLen <= #1 _rWrLen;\n\trWrData <= #1 _rWrData;\nend\n\nalways @ (*) begin\n\t_rRdChnl = wRdReqChnl;\n\t_rRdAddr = wRdAddr[63:2];\n\t_rRdLen = wRdLen;\n\t_rRdSgChnl = wRdSgChnl;\n\t_rWrChnl = wWrReqChnl;\n\t_rWrAddr = wWrAddr[63:2];\n\t_rWrLen = wWrLen;\n\t_rWrData = wWrData;\nend\n\n// Accept requests when the selector indicates. Capture the buffered \n// request parameters for hand-off to the formatting pipeline. Then\n// acknowledge the receipt to the channel so it can deassert the \n// request, and let the selector choose another channel.\nalways @ (posedge CLK) begin\n\trCapState <= #1 (RST ? `S_TXENGUPR128_CAP_RD_WR : _rCapState);\n\trRdAck <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rRdAck);\n\trWrAck <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rWrAck);\n\trIsWr <= #1 _rIsWr;\n\trCapChnl <= #1 _rCapChnl;\n\trCapAddr <= #1 _rCapAddr;\n\trCapAddr64 <= #1 _rCapAddr64;\n\trCapLen <= #1 _rCapLen;\n\trCapIsWr <= #1 _rCapIsWr;\n\trExtTagReq <= #1 _rExtTagReq;\n\trExtTag <= #1 _rExtTag;\n rTxEngRdReqAck <= #1 _rTxEngRdReqAck;\nend\n\nalways @ (*) begin\n\t_rCapState = rCapState;\n\t_rRdAck = rRdAck;\n\t_rWrAck = rWrAck;\n\t_rIsWr = rIsWr;\n\t_rCapChnl = rCapChnl;\n\t_rCapAddr = rCapAddr;\n\t_rCapAddr64 = rCapAddr64;\n\t_rCapLen = rCapLen;\n\t_rCapIsWr = rCapIsWr;\n\t_rExtTagReq = rExtTagReq;\n\t_rExtTag = rExtTag;\n _rTxEngRdReqAck = rTxEngRdReqAck;\n\n\tcase (rCapState) \n\n\t`S_TXENGUPR128_CAP_RD_WR : begin\n\t\t_rIsWr = !wRdReq;\n\t _rRdAck = ((wRdAck)<>(rCapIsWr)); // Changes to S_TXENGUPR128_CAP_RD_WR\n\tend\n\t\n\tdefault : begin\n\t\t_rCapState = `S_TXENGUPR128_CAP_RD_WR;\n\tend\n\t\n\tendcase\nend\n\n\n// Calculate the available space in the FIFO, accounting for the \n// formatting pipeline depth. This will be conservative.\nwire [9:0] wMaxEntries = (C_MAX_ENTRIES<>(wRdReqChnl*64));\nwire\t[9:0]\t\t\t\t\t\twRdLen = (RD_LEN>>(wRdReqChnl*10));\nwire\t[1:0]\t\t\t\t\t\twRdSgChnl = (RD_SG_CHNL>>(wRdReqChnl*2));\nwire\t[63:0]\t\t\t\t\t\twWrAddr = (WR_ADDR>>(wWrReqChnl*64));\nwire\t[9:0]\t\t\t\t\t\twWrLen = (WR_LEN>>(wWrReqChnl*10));\nwire\t[C_PCI_DATA_WIDTH-1:0]\t\twWrData = (WR_DATA>>wCountChnlShiftDW);\n\nreg\t\t[3:0]\t\t\t\t\t\trRdChnl=0, _rRdChnl=0;\nreg\t\t[61:0]\t\t\t\t\t\trRdAddr=62'd0, _rRdAddr=62'd0;\nreg\t\t[9:0]\t\t\t\t\t\trRdLen=0, _rRdLen=0;\nreg\t\t[1:0]\t\t\t\t\t\trRdSgChnl=0, _rRdSgChnl=0;\nreg\t\t[3:0]\t\t\t\t\t\trWrChnl=0, _rWrChnl=0;\nreg\t\t[61:0]\t\t\t\t\t\trWrAddr=62'd0, _rWrAddr=62'd0;\nreg\t\t[9:0]\t\t\t\t\t\trWrLen=0, _rWrLen=0;\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};\nwire\t[C_PCI_DATA_WIDTH-1:0]\t\twWrDataSwap = {rWrData[7:0], rWrData[15:8], rWrData[23:16], rWrData[31:24]};\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[3:0]\t\t\t\t\t\trCapState=`S_TXENGUPR32_CAP_RD_WR, _rCapState=`S_TXENGUPR32_CAP_RD_WR;\nreg\t\t[C_NUM_CHNL-1:0]\t\t\trRdAck=0, _rRdAck=0;\nreg\t\t[C_NUM_CHNL-1:0]\t\t\trWrAck=0, _rWrAck=0;\nreg\t\t\t\t\t\t\t\t\trIsWr=0, _rIsWr=0;\nreg\t\t[5:0]\t\t\t\t\t\trCapChnl=0, _rCapChnl=0;\nreg\t\t[61:0]\t\t\t\t\t\trCapAddr=62'd0, _rCapAddr=62'd0;\nreg\t\t\t\t\t\t\t\t\trCapAddr64=0, _rCapAddr64=0;\nreg\t\t[9:0]\t\t\t\t\t\trCapLen=0, _rCapLen=0;\nreg\t\t\t\t\t\t\t\t\trCapIsWr=0, _rCapIsWr=0;\nreg\t\t\t\t\t\t\t\t\trExtTagReq=0, _rExtTagReq=0;\nreg\t\t[C_TAG_WIDTH-1:0]\t\t\trExtTag=0, _rExtTag=0;\n\nreg\t\t[C_FIFO_DEPTH_WIDTH-1:0]\trFifoCount=0, _rFifoCount=0;\nreg\t\t[9:0]\t\t\t\t\t\trMaxEntries=0, _rMaxEntries=0;\nreg\t\t\t\t\t\t\t\t\trSpaceAvail=0, _rSpaceAvail=0;\n\nreg\t\t[C_DATA_DELAY-1:0]\t\t\trWnR=0, _rWnR=0;\nreg\t\t[(C_DATA_DELAY*4)-1:0]\t\trChnl=0, _rChnl=0;\nreg\t\t[(C_DATA_DELAY*8)-1:0]\t\trTag=0, _rTag=0;\nreg\t\t[(C_DATA_DELAY*62)-1:0]\t\trAddr=0, _rAddr=0;\nreg\t\t[C_DATA_DELAY-1:0]\t\t\trAddr64=0, _rAddr64=0;\nreg\t\t[(C_DATA_DELAY*10)-1:0]\t\trLen=0, _rLen=0;\nreg\t\t[C_DATA_DELAY-1:0]\t\t\trLenEQ1=0, _rLenEQ1=0;\nreg\t\t[C_DATA_DELAY-1:0]\t\t\trValid=0, _rValid=0;\n\n\nassign WR_DATA_REN = rWrDataRen;\nassign WR_ACK = rWrAck;\nassign RD_ACK = rRdAck;\n\nassign INT_TAG = {rRdSgChnl, rRdChnl};\nassign INT_TAG_VALID = rExtTagReq;\n\nassign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;\nassign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);\n\n// Search for the next request so that we can move onto it immediately after\n// the current channel has released its request.\ntx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));\ntx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));\n\n\n// Buffer shift-selected channel request signals and FIFO data.\nalways @ (posedge CLK) begin\n\trRdChnl <= #1 _rRdChnl;\n\trRdAddr <= #1 _rRdAddr;\n\trRdLen <= #1 _rRdLen;\n\trRdSgChnl <= #1 _rRdSgChnl;\n\trWrChnl <= #1 _rWrChnl;\n\trWrAddr <= #1 _rWrAddr;\n\trWrLen <= #1 _rWrLen;\n\trWrData <= #1 _rWrData;\nend\n\nalways @ (*) begin\n\t_rRdChnl = wRdReqChnl;\n\t_rRdAddr = wRdAddr[63:2];\n\t_rRdLen = wRdLen;\n\t_rRdSgChnl = wRdSgChnl;\n\t_rWrChnl = wWrReqChnl;\n\t_rWrAddr = wWrAddr[63:2];\n\t_rWrLen = wWrLen;\n\t_rWrData = wWrData;\nend\n\n\n// Accept requests when the selector indicates. Capture the buffered \n// request parameters for hand-off to the formatting pipeline. Then\n// acknowledge the receipt to the channel so it can deassert the \n// request, and let the selector choose another channel.\nalways @ (posedge CLK) begin\n\trCapState <= #1 (RST ? `S_TXENGUPR32_CAP_RD_WR : _rCapState);\n\trRdAck <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rRdAck);\n\trWrAck <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rWrAck);\n\trIsWr <= #1 _rIsWr;\n\trCapChnl <= #1 _rCapChnl;\n\trCapAddr <= #1 _rCapAddr;\n\trCapAddr64 <= #1 _rCapAddr64;\n\trCapLen <= #1 _rCapLen;\n\trCapIsWr <= #1 _rCapIsWr;\n\trExtTagReq <= #1 _rExtTagReq;\n\trExtTag <= #1 _rExtTag;\n rTxEngRdReqAck <= #1 _rTxEngRdReqAck;\nend\n\nalways @ (*) begin\n\t_rCapState = rCapState;\n\t_rRdAck = rRdAck;\n\t_rWrAck = rWrAck;\n\t_rIsWr = rIsWr;\n\t_rCapChnl = rCapChnl;\n\t_rCapAddr = rCapAddr;\n\t_rCapAddr64 = (rCapAddr[61:30] != 0);\n\t_rCapLen = rCapLen;\n\t_rCapIsWr = rCapIsWr;\n\t_rExtTagReq = rExtTagReq;\n\t_rExtTag = rExtTag;\n _rTxEngRdReqAck = rTxEngRdReqAck;\n \n\tcase (rCapState) \n\n\t`S_TXENGUPR32_CAP_RD_WR : begin\n\t\t_rIsWr = !wRdReq;\n\t _rRdAck = ((wRdAck)<>(rCapIsWr)); // Changes to S_TXENGUPR32_CAP_RD_WR\n\tend\n\t\n\tdefault : begin\n\t\t_rCapState = `S_TXENGUPR32_CAP_RD_WR;\n\tend\n\t\n\tendcase\nend\n\n\n// Calculate the available space in the FIFO, accounting for the \n// formatting pipeline depth. This will be conservative.\nwire [9:0] wMaxEntries = (C_MAX_ENTRIES<>(wRdReqChnl*64));\nwire\t[9:0]\t\t\t\t\t\twRdLen = (RD_LEN>>(wRdReqChnl*10));\nwire\t[1:0]\t\t\t\t\t\twRdSgChnl = (RD_SG_CHNL>>(wRdReqChnl*2));\nwire\t[63:0]\t\t\t\t\t\twWrAddr = (WR_ADDR>>(wWrReqChnl*64));\nwire\t[9:0]\t\t\t\t\t\twWrLen = (WR_LEN>>(wWrReqChnl*10));\nwire\t[C_PCI_DATA_WIDTH-1:0]\t\twWrData = (WR_DATA>>wCountChnlShiftDW);\n\nreg\t\t[3:0]\t\t\t\t\t\trRdChnl=0, _rRdChnl=0;\nreg\t\t[61:0]\t\t\t\t\t\trRdAddr=62'd0, _rRdAddr=62'd0;\nreg\t\t[9:0]\t\t\t\t\t\trRdLen=0, _rRdLen=0;\nreg\t\t[1:0]\t\t\t\t\t\trRdSgChnl=0, _rRdSgChnl=0;\nreg\t\t[3:0]\t\t\t\t\t\trWrChnl=0, _rWrChnl=0;\nreg\t\t[61:0]\t\t\t\t\t\trWrAddr=62'd0, _rWrAddr=62'd0;\nreg\t\t[9:0]\t\t\t\t\t\trWrLen=0, _rWrLen=0;\nreg\t\t[C_PCI_DATA_WIDTH-1:0]\t\trWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};\n\ngenerate\nif(C_ALTERA == 1'b1) begin : altera_data\n\tassign wWrDataSwap = rWrData;\nend\nelse begin : xilinx_data\n\tassign wWrDataSwap = {rWrData[39:32], rWrData[47:40], rWrData[55:48], rWrData[63:56],\n\t\t\t\t\t\t\trWrData[07:00], rWrData[15:08], rWrData[23:16], rWrData[31:24]};\nend\nendgenerate\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[3:0]\t\t\t\t\t\trCapState=`S_TXENGUPR64_CAP_RD_WR, _rCapState=`S_TXENGUPR64_CAP_RD_WR;\nreg\t\t[C_NUM_CHNL-1:0]\t\t\trRdAck=0, _rRdAck=0;\nreg\t\t[C_NUM_CHNL-1:0]\t\t\trWrAck=0, _rWrAck=0;\nreg\t\t\t\t\t\t\t\t\trIsWr=0, _rIsWr=0;\nreg\t\t[5:0]\t\t\t\t\t\trCapChnl=0, _rCapChnl=0;\nreg\t\t[61:0]\t\t\t\t\t\trCapAddr=62'd0, _rCapAddr=62'd0;\nreg\t\t\t\t\t\t\t\t\trCapAddr64=0, _rCapAddr64=0;\nreg\t\t[9:0]\t\t\t\t\t\trCapLen=0, _rCapLen=0;\nreg\t\t\t\t\t\t\t\t\trCapIsWr=0, _rCapIsWr=0;\nreg\t\t\t\t\t\t\t\t\trExtTagReq=0, _rExtTagReq=0;\nreg\t\t[C_TAG_WIDTH-1:0]\t\t\trExtTag=0, _rExtTag=0;\n\nreg\t\t[C_FIFO_DEPTH_WIDTH-1:0]\trFifoCount=0, _rFifoCount=0;\nreg\t\t[9:0]\t\t\t\t\t\trMaxEntries=0, _rMaxEntries=0;\nreg\t\t\t\t\t\t\t\t\trSpaceAvail=0, _rSpaceAvail=0;\n\nreg\t\t[C_DATA_DELAY-1:0]\t\t\trWnR=0, _rWnR=0;\nreg\t\t[(C_DATA_DELAY*4)-1:0]\t\trChnl=0, _rChnl=0;\nreg\t\t[(C_DATA_DELAY*8)-1:0]\t\trTag=0, _rTag=0;\nreg\t\t[(C_DATA_DELAY*62)-1:0]\t\trAddr=0, _rAddr=0;\nreg\t\t[C_DATA_DELAY-1:0]\t\t\trAddr64=0, _rAddr64=0;\nreg\t\t[(C_DATA_DELAY*10)-1:0]\t\trLen=0, _rLen=0;\nreg\t\t[C_DATA_DELAY-1:0]\t\t\trLenEQ1=0, _rLenEQ1=0;\nreg\t\t[C_DATA_DELAY-1:0]\t\t\trValid=0, _rValid=0;\n\n\nassign WR_DATA_REN = rWrDataRen;\nassign WR_ACK = rWrAck;\nassign RD_ACK = rRdAck;\n\nassign INT_TAG = {rRdSgChnl, rRdChnl};\nassign INT_TAG_VALID = rExtTagReq;\n\n assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;\n assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);\n\n// Search for the next request so that we can move onto it immediately after\n// the current channel has released its request.\ntx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));\ntx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));\n\n\n// Buffer shift-selected channel request signals and FIFO data.\nalways @ (posedge CLK) begin\n\trRdChnl <= #1 _rRdChnl;\n\trRdAddr <= #1 _rRdAddr;\n\trRdLen <= #1 _rRdLen;\n\trRdSgChnl <= #1 _rRdSgChnl;\n\trWrChnl <= #1 _rWrChnl;\n\trWrAddr <= #1 _rWrAddr;\n\trWrLen <= #1 _rWrLen;\n\trWrData <= #1 _rWrData;\nend\n\nalways @ (*) begin\n\t_rRdChnl = wRdReqChnl;\n\t_rRdAddr = wRdAddr[63:2];\n\t_rRdLen = wRdLen;\n\t_rRdSgChnl = wRdSgChnl;\n\t_rWrChnl = wWrReqChnl;\n\t_rWrAddr = wWrAddr[63:2];\n\t_rWrLen = wWrLen;\n\t_rWrData = wWrData;\nend\n\n\n// Accept requests when the selector indicates. Capture the buffered \n// request parameters for hand-off to the formatting pipeline. Then\n// acknowledge the receipt to the channel so it can deassert the \n// request, and let the selector choose another channel.\nalways @ (posedge CLK) begin\n\trCapState <= #1 (RST ? `S_TXENGUPR64_CAP_RD_WR : _rCapState);\n\trRdAck <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rRdAck);\n\trWrAck <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rWrAck);\n\trIsWr <= #1 _rIsWr;\n\trCapChnl <= #1 _rCapChnl;\n\trCapAddr <= #1 _rCapAddr;\n\trCapAddr64 <= #1 _rCapAddr64;\n\trCapLen <= #1 _rCapLen;\n\trCapIsWr <= #1 _rCapIsWr;\n\trExtTagReq <= #1 _rExtTagReq;\n\trExtTag <= #1 _rExtTag;\n rTxEngRdReqAck <= #1 _rTxEngRdReqAck;\nend\n\nalways @ (*) begin\n\t_rCapState = rCapState;\n\t_rRdAck = rRdAck;\n\t_rWrAck = rWrAck;\n\t_rIsWr = rIsWr;\n\t_rCapChnl = rCapChnl;\n\t_rCapAddr = rCapAddr;\n\t_rCapAddr64 = (rCapAddr[61:30] != 0);\n\t_rCapLen = rCapLen;\n\t_rCapIsWr = rCapIsWr;\n\t_rExtTagReq = rExtTagReq;\n\t_rExtTag = rExtTag;\n _rTxEngRdReqAck = rTxEngRdReqAck;\n\n\tcase (rCapState) \n\n\t`S_TXENGUPR64_CAP_RD_WR : begin\n\t\t_rIsWr = !wRdReq;\n\t _rRdAck = (wRdAck<>(rCapIsWr)); // Changes to S_TXENGUPR64_CAP_RD_WR\n\tend\n\t\n\tdefault : begin\n\t\t_rCapState = `S_TXENGUPR64_CAP_RD_WR;\n\tend\n\t\n\tendcase\nend\n\n\n// Calculate the available space in the FIFO, accounting for the \n// formatting pipeline depth. This will be conservative.\nwire [9:0] wMaxEntries = (C_MAX_ENTRIES<>({rConsumedHist[8:6], 5'd0})) | (rFifoData<<({rCountHist[7:6], 5'd0})));\n\telse\n\t\t_rData = (rData>>({rConsumedHist[8:6], 5'd0}));\nend\n\n\n// Buffer up to 4 length LSB values for use to detect unread data that was\n// part of a consumed packet. Should only need 2. This is basically a FIFO.\nalways @ (posedge CLK) begin\n\trRdPtr <= #1 (RST ? 2'd0 : _rRdPtr);\n\trWrPtr <= #1 (RST ? 2'd0 : _rWrPtr);\n\trLenLSB0 <= #1 _rLenLSB0;\n\trLenLSB1 <= #1 _rLenLSB1;\n\trLenLast <= #1 _rLenLast;\nend\n\nalways @ (*) begin\n\t_rRdPtr = (wAfterEnd ? rRdPtr + 1'd1 : rRdPtr);\n\t_rWrPtr = (rLenValid ? rWrPtr + 1'd1 : rWrPtr);\n\t_rLenLSB0 = rLenLSB0;\n\t_rLenLSB1 = rLenLSB1;\n\t{_rLenLSB1[rWrPtr], _rLenLSB0[rWrPtr]} = (rLenValid ? (~LEN_LSB + 1'd1) : {rLenLSB1[rWrPtr], rLenLSB0[rWrPtr]});\n\t_rLenLast = rLenLast;\n\t_rLenLast[rWrPtr] = (rLenValid ? LEN_LAST : rLenLast[rWrPtr]);\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_buffer_32.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_port_buffer_32.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tWraps a FIFO for saving channel data and provides a \n// registered read output. Data is available 3 cycles after RD_EN is asserted \n// (not 1, like a traditional FIFO).\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n\nmodule tx_port_buffer_32 #(\n\tparameter C_FIFO_DATA_WIDTH = 9'd32,\n\tparameter C_FIFO_DEPTH = 512,\n\t// Local parameters\n\tparameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)\n)\n(\n\tinput RST,\n\tinput CLK,\n\n\tinput [C_FIFO_DATA_WIDTH-1:0] WR_DATA,\t\t// Input data\n\tinput WR_EN,\t\t\t\t\t\t\t\t// Input data write enable\n\toutput [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,\t// Input data FIFO is full\n\n\toutput [C_FIFO_DATA_WIDTH-1:0] RD_DATA,\t\t// Output data\n\tinput RD_EN\t\t\t\t\t\t\t\t\t// Output data read enable\n);\n\n`include \"common_functions.v\"\n\nreg \t\t\t\t\t\t\t\trFifoRdEn=0, _rFifoRdEn=0;\nreg\t\t[C_FIFO_DATA_WIDTH-1:0]\t\trFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};\nwire\t[C_FIFO_DATA_WIDTH-1:0]\t\twFifoData;\n\nassign RD_DATA = rFifoData;\n\n\n// Buffer the input signals that come from outside the tx_port.\nalways @ (posedge CLK) begin\n\trFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);\nend\n\nalways @ (*) begin\n\t_rFifoRdEn = RD_EN;\nend\n\n\n// FIFO for storing data from the channel.\n(* RAM_STYLE=\"BLOCK\" *)\nsync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (\n\t.CLK(CLK),\n\t.RST(RST),\n\t.WR_EN(WR_EN),\n\t.WR_DATA(WR_DATA),\n\t.FULL(),\n\t.COUNT(WR_COUNT),\n\t.RD_EN(rFifoRdEn),\n\t.RD_DATA(wFifoData),\n\t.EMPTY()\n);\n\n\n// Buffer data from the FIFO.\nalways @ (posedge CLK) begin\n\trFifoData <= #1 _rFifoData;\nend\n\nalways @ (*) begin\n\t_rFifoData = wFifoData;\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_buffer_64.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_port_buffer_64.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tWraps a FIFO for saving channel data and provides a \n// registered read output. Retains unread words from reads that are a length \n// which is not a multiple of the data bus width (C_FIFO_DATA_WIDTH). Data is\n// available 5 cycles after RD_EN is asserted (not 1, like a traditional FIFO).\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n\nmodule tx_port_buffer_64 #(\n\tparameter C_FIFO_DATA_WIDTH = 9'd64,\n\tparameter C_FIFO_DEPTH = 512,\n\t// Local parameters\n\tparameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),\n\tparameter C_RD_EN_HIST = 2,\n\tparameter C_FIFO_RD_EN_HIST = 2,\n\tparameter C_CONSUME_HIST = 3,\n\tparameter C_COUNT_HIST = 3,\n\tparameter C_LEN_LAST_HIST = 1\n)\n(\n\tinput RST,\n\tinput CLK,\n\n\tinput LEN_VALID,\t\t\t\t\t\t\t// Transfer length is valid\n\tinput [0:0] LEN_LSB,\t\t\t\t\t\t// LSBs of transfer length\n\tinput LEN_LAST,\t\t\t\t\t\t\t\t// Last transfer in transaction\n\n\tinput [C_FIFO_DATA_WIDTH-1:0] WR_DATA,\t\t// Input data\n\tinput WR_EN,\t\t\t\t\t\t\t\t// Input data write enable\n\toutput [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,\t// Input data FIFO is full\n\n\toutput [C_FIFO_DATA_WIDTH-1:0] RD_DATA,\t\t// Output data\n\tinput RD_EN\t\t\t\t\t\t\t\t\t// Output data read enable\n);\n\n`include \"common_functions.v\"\n\nreg \t[1:0]\t\t\t\t\t\trRdPtr=0, _rRdPtr=0;\nreg \t[1:0]\t\t\t\t\t\trWrPtr=0, _rWrPtr=0;\nreg \t[3:0]\t\t\t\t\t\trLenLSB=0, _rLenLSB=0;\nreg \t[3:0]\t\t\t\t\t\trLenLast=0, _rLenLast=0;\nreg\t\t\t\t\t\t\t\t\trLenValid=0, _rLenValid=0;\n\nreg\t\t\t\t\t\t\t\t\trRen=0, _rRen=0;\t\nreg \t[1:0]\t\t\t\t\t\trCount=0, _rCount=0;\nreg \t[(C_COUNT_HIST*2)-1:0]\t\trCountHist={C_COUNT_HIST{2'd0}}, _rCountHist={C_COUNT_HIST{2'd0}};\nreg \t[C_LEN_LAST_HIST-1:0]\t\trLenLastHist={C_LEN_LAST_HIST{1'd0}}, _rLenLastHist={C_LEN_LAST_HIST{1'd0}};\nreg \t[C_RD_EN_HIST-1:0]\t\t\trRdEnHist={C_RD_EN_HIST{1'd0}}, _rRdEnHist={C_RD_EN_HIST{1'd0}};\nreg \t\t\t\t\t\t\t\trFifoRdEn=0, _rFifoRdEn=0;\nreg \t[C_FIFO_RD_EN_HIST-1:0]\t\trFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}}, _rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}};\nreg \t[(C_CONSUME_HIST*2)-1:0]\trConsumedHist={C_CONSUME_HIST{2'd0}}, _rConsumedHist={C_CONSUME_HIST{2'd0}};\nreg\t\t[C_FIFO_DATA_WIDTH-1:0]\t\trFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};\nreg\t\t[95:0]\t\t\t\t\t\trData=96'd0, _rData=96'd0;\n\nwire\t[C_FIFO_DATA_WIDTH-1:0]\t\twFifoData;\n\nassign RD_DATA = rData[0 +:C_FIFO_DATA_WIDTH];\n\n\n// Buffer the input signals that come from outside the tx_port.\nalways @ (posedge CLK) begin\n\trLenValid <= #1 (RST ? 1'd0 : _rLenValid);\n\trRen <= #1 (RST ? 1'd0 : _rRen);\nend\n\nalways @ (*) begin\n\t_rLenValid = LEN_VALID;\n\t_rRen = RD_EN;\nend\n\n\n// FIFO for storing data from the channel.\n(* RAM_STYLE=\"BLOCK\" *)\nsync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (\n\t.CLK(CLK),\n\t.RST(RST),\n\t.WR_EN(WR_EN),\n\t.WR_DATA(WR_DATA),\n\t.FULL(),\n\t.COUNT(WR_COUNT),\n\t.RD_EN(rFifoRdEn),\n\t.RD_DATA(wFifoData),\n\t.EMPTY()\n);\n\n\n// Manage shifting of data in from the FIFO and shifting of data out once\n// it is consumed. We'll keep 3 words of output registers to hold an input\n// packet with up to 1 extra word of unread data.\nwire wLenOdd = rLenLSB[rRdPtr];\nwire wLenLast = rLenLast[rRdPtr];\nwire wAfterEnd = (!rRen & rRdEnHist[0]);\nwire [1:0] wConsumed = ({(rRdEnHist[0] | (!rRdEnHist[0] & rRdEnHist[1] & rLenLastHist[0])), 1'd0}) - (wAfterEnd & wLenOdd);\n \nalways @ (posedge CLK) begin\n\trCount <= #1 (RST ? 2'd0 : _rCount);\n\trCountHist <= #1 _rCountHist;\n\trRdEnHist <= #1 (RST ? {C_RD_EN_HIST{1'd0}} : _rRdEnHist);\n\trFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);\n\trFifoRdEnHist <= #1 (RST ? {C_FIFO_RD_EN_HIST{1'd0}} : _rFifoRdEnHist);\n\trConsumedHist <= #1 _rConsumedHist;\n\trLenLastHist <= #1 (RST ? {C_LEN_LAST_HIST{1'd0}} : _rLenLastHist);\n\trFifoData <= #1 _rFifoData;\n\trData <= #1 _rData;\nend\n\nalways @ (*) begin\n\t// Keep track of words in our buffer. Subtract 2 when we reach 2 on RD_EN.\n\t// Add 1 when we finish a sequence of RD_EN that read an odd number of words.\n\t_rCount = rCount + (wAfterEnd & wLenOdd & !wLenLast) - ({rRen & rCount[1], 1'd0}) - ({(wAfterEnd & wLenLast)&rCount[1], (wAfterEnd & wLenLast)&rCount[0]});\n\t_rCountHist = ((rCountHist<<2) | rCount);\n\n\t// Track read enables in the pipeline.\n\t_rRdEnHist = ((rRdEnHist<<1) | rRen);\n\t_rFifoRdEnHist = ((rFifoRdEnHist<<1) | rFifoRdEn);\n\t\n\t// Track delayed length last value\n\t_rLenLastHist = ((rLenLastHist<<1) | wLenLast);\n\n\t// Calculate the amount to shift out each RD_EN. This is always 2 unless\n\t// it's the last RD_EN in the sequence and the read words length is odd.\n\t_rConsumedHist = ((rConsumedHist<<2) | wConsumed);\n\n\t// Read from the FIFO unless we have 2 words cached.\n\t_rFifoRdEn = (!rCount[1] & rRen);\n\n\t// Buffer the FIFO data.\n\t_rFifoData = wFifoData;\n\n\t// Shift the buffered FIFO data into and the consumed data out of the output register.\n\tif (rFifoRdEnHist[1])\n\t\t_rData = ((rData>>({rConsumedHist[5:4], 5'd0})) | (rFifoData<<({rCountHist[4], 5'd0})));\n\telse\n\t\t_rData = (rData>>({rConsumedHist[5:4], 5'd0}));\nend\n\n\n// Buffer up to 4 length LSB values for use to detect unread data that was\n// part of a consumed packet. Should only need 2. This is basically a FIFO.\nalways @ (posedge CLK) begin\n\trRdPtr <= #1 (RST ? 2'd0 : _rRdPtr);\n\trWrPtr <= #1 (RST ? 2'd0 : _rWrPtr);\n\trLenLSB <= #1 _rLenLSB;\n\trLenLast <= #1 _rLenLast;\nend\n\nalways @ (*) begin\n\t_rRdPtr = (wAfterEnd ? rRdPtr + 1'd1 : rRdPtr);\n\t_rWrPtr = (rLenValid ? rWrPtr + 1'd1 : rWrPtr);\n\t_rLenLSB = rLenLSB;\n\t_rLenLSB[rWrPtr] = (rLenValid ? (~LEN_LSB + 1'd1) : rLenLSB[rWrPtr]);\n\t_rLenLast = rLenLast;\n\t_rLenLast[rWrPtr] = (rLenValid ? LEN_LAST : rLenLast[rWrPtr]);\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_channel_gate_128.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_port_channel_gate_128.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tCaptures transaction open/close events as well as data\n// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can\n// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When\n// CHNL_TX drops, the channel closes (until the next transaction -- signaled by\n// CHNL_TX going up again).\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_TXPORTGATE128_IDLE\t\t2'b00\n`define S_TXPORTGATE128_OPENING\t\t2'b01\n`define S_TXPORTGATE128_OPEN\t\t2'b10\n`define S_TXPORTGATE128_CLOSED\t\t2'b11\n\nmodule tx_port_channel_gate_128 #(\n\tparameter C_DATA_WIDTH = 9'd128,\n\t// Local parameters\n\tparameter C_FIFO_DEPTH = 8,\n\tparameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1\n)\n(\n\tinput RST,\n\n\tinput RD_CLK,\t\t\t\t\t\t\t// FIFO read clock\n\toutput [C_FIFO_DATA_WIDTH-1:0] RD_DATA,\t// FIFO read data\n\toutput RD_EMPTY,\t\t\t\t\t\t// FIFO is empty\n\tinput RD_EN,\t\t\t\t\t\t\t// FIFO read enable\n\n\tinput CHNL_CLK,\t\t\t\t\t\t\t// Channel write clock\n\tinput CHNL_TX,\t\t\t\t\t\t\t// Channel write receive signal\n\toutput CHNL_TX_ACK,\t\t\t\t\t\t// Channel write acknowledgement signal\n\tinput CHNL_TX_LAST,\t\t\t\t\t\t// Channel last write\n\tinput [31:0] CHNL_TX_LEN,\t\t\t\t// Channel write length (in 32 bit words)\n\tinput [30:0] CHNL_TX_OFF,\t\t\t\t// Channel write offset\n\tinput [C_DATA_WIDTH-1:0] CHNL_TX_DATA,\t// Channel write data\n\tinput CHNL_TX_DATA_VALID,\t\t\t\t// Channel write data valid\n\toutput CHNL_TX_DATA_REN\t\t\t\t\t// Channel write data has been recieved\n);\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[1:0]\t\t\t\t\trState=`S_TXPORTGATE128_IDLE, _rState=`S_TXPORTGATE128_IDLE;\nreg\t\t\t\t\t\t\t\trFifoWen=0, _rFifoWen=0;\nreg\t\t[C_FIFO_DATA_WIDTH-1:0]\trFifoData=0, _rFifoData=0;\nwire\t\t\t\t\t\t wFifoFull;\n\nreg\t\t\t\t\t\t\t\trChnlTx=0, _rChnlTx=0;\nreg\t\t\t\t\t\t\t\trChnlLast=0, _rChnlLast=0;\nreg\t\t[31:0]\t\t\t\t\trChnlLen=0, _rChnlLen=0;\nreg\t\t[30:0]\t\t\t\t\trChnlOff=0, _rChnlOff=0;\nreg\t\t\t\t\t\t\t\trAck=0, _rAck=0;\nreg\t\t\t\t\t\t\t\trPause=0, _rPause=0;\nreg\t\t\t\t\t\t\t\trClosed=0, _rClosed=0;\n\n\nassign CHNL_TX_ACK = rAck;\nassign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE128_OPEN\n\n\n// Buffer the input signals that come from outside the tx_port.\nalways @ (posedge CHNL_CLK) begin\n\trChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);\n\trChnlLast <= #1 _rChnlLast;\n\trChnlLen <= #1 _rChnlLen;\n\trChnlOff <= #1 _rChnlOff;\nend\n\nalways @ (*) begin\n\t_rChnlTx = CHNL_TX;\n\t_rChnlLast = CHNL_TX_LAST;\n\t_rChnlLen = CHNL_TX_LEN;\n\t_rChnlOff = CHNL_TX_OFF;\nend\n\n\n// FIFO for temporarily storing data from the channel.\n(* RAM_STYLE=\"DISTRIBUTED\" *)\nasync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (\n\t.WR_CLK(CHNL_CLK),\n\t.WR_RST(RST),\n\t.WR_EN(rFifoWen),\n\t.WR_DATA(rFifoData),\n\t.WR_FULL(wFifoFull),\n\t.RD_CLK(RD_CLK),\n\t.RD_RST(RST),\n\t.RD_EN(RD_EN),\n\t.RD_DATA(RD_DATA),\n\t.RD_EMPTY(RD_EMPTY)\n);\n\n\n// Pass the transaction open event, transaction data, and the transaction\n// close event through to the RD_CLK domain via the async_fifo.\nalways @ (posedge CHNL_CLK) begin\n\trState <= #1 (RST ? `S_TXPORTGATE128_IDLE : _rState);\n\trFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);\n\trFifoData <= #1 _rFifoData;\n\trAck <= #1 (RST ? 1'd0 : _rAck);\n\trPause <= #1 (RST ? 1'd0 : _rPause);\n\trClosed <= #1 (RST ? 1'd0 : _rClosed);\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\t_rFifoWen = rFifoWen;\n\t_rFifoData = rFifoData;\n\t_rPause = rPause;\n\t_rAck = rAck;\n\t_rClosed = rClosed;\n\tcase (rState)\n\n\t`S_TXPORTGATE128_IDLE: begin // Write the len, off, last\n\t\t_rPause = 0;\n\t\t_rClosed = 0;\n\t\tif (!wFifoFull) begin\n\t\t\t_rAck = rChnlTx;\n\t\t\t_rFifoWen = rChnlTx;\n\t\t\t_rFifoData = {1'd1, 64'd0, rChnlLen, rChnlOff, rChnlLast};\n\t\t\tif (rChnlTx)\n\t\t\t\t_rState = `S_TXPORTGATE128_OPENING;\n\t\tend\n\tend\n\n\t`S_TXPORTGATE128_OPENING: begin // Write the len, off, last (again)\n\t\t_rAck = 0;\n\t\t_rClosed = (rClosed | !rChnlTx);\n\t\tif (!wFifoFull) begin\n\t\t\tif (rClosed | !rChnlTx)\n\t\t\t\t_rState = `S_TXPORTGATE128_CLOSED;\n\t\t\telse\n\t\t\t\t_rState = `S_TXPORTGATE128_OPEN;\n\t\tend\n\tend\n\n\t`S_TXPORTGATE128_OPEN: begin // Copy channel data into the FIFO\n\t\tif (!wFifoFull) begin\n\t\t\t_rFifoWen = CHNL_TX_DATA_VALID; \t// CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered\n\t\t\t_rFifoData = {1'd0, CHNL_TX_DATA};\t// but the VALID+REN model seem to make this difficult.\n\t\tend\n\t\tif (!rChnlTx)\n\t\t\t_rState = `S_TXPORTGATE128_CLOSED;\n\tend\n\t\n\t`S_TXPORTGATE128_CLOSED: begin // Write the end marker (twice)\n\t\tif (!wFifoFull) begin\n\t\t\t_rPause = 1;\n\t\t\t_rFifoWen = 1;\n\t\t\t_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};\n\t\t\tif (rPause)\n\t\t\t_rState = `S_TXPORTGATE128_IDLE;\n\t\tend\n\tend\n\t\n\tendcase\t\nend\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_channel_gate_32.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_port_channel_gate_32.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tCaptures transaction open/close events as well as data\n// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can\n// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When\n// CHNL_TX drops, the channel closes (until the next transaction -- signaled by\n// CHNL_TX going up again).\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_TXPORTGATE32_IDLE\t\t2'b00\n`define S_TXPORTGATE32_OPENING\t2'b01\n`define S_TXPORTGATE32_OPEN\t\t2'b10\n`define S_TXPORTGATE32_CLOSED\t2'b11\n\nmodule tx_port_channel_gate_32 #(\n\tparameter C_DATA_WIDTH = 9'd32,\n\t// Local parameters\n\tparameter C_FIFO_DEPTH = 8,\n\tparameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1\n)\n(\n\tinput RST,\n\n\tinput RD_CLK,\t\t\t\t\t\t\t// FIFO read clock\n\toutput [C_FIFO_DATA_WIDTH-1:0] RD_DATA,\t// FIFO read data\n\toutput RD_EMPTY,\t\t\t\t\t\t// FIFO is empty\n\tinput RD_EN,\t\t\t\t\t\t\t// FIFO read enable\n\n\tinput CHNL_CLK,\t\t\t\t\t\t\t// Channel write clock\n\tinput CHNL_TX,\t\t\t\t\t\t\t// Channel write receive signal\n\toutput CHNL_TX_ACK,\t\t\t\t\t\t// Channel write acknowledgement signal\n\tinput CHNL_TX_LAST,\t\t\t\t\t\t// Channel last write\n\tinput [31:0] CHNL_TX_LEN,\t\t\t\t// Channel write length (in 32 bit words)\n\tinput [30:0] CHNL_TX_OFF,\t\t\t\t// Channel write offset\n\tinput [C_DATA_WIDTH-1:0] CHNL_TX_DATA,\t// Channel write data\n\tinput CHNL_TX_DATA_VALID,\t\t\t\t// Channel write data valid\n\toutput CHNL_TX_DATA_REN\t\t\t\t\t// Channel write data has been recieved\n);\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[1:0]\t\t\t\t\trState=`S_TXPORTGATE32_IDLE, _rState=`S_TXPORTGATE32_IDLE;\nreg\t\t\t\t\t\t\t\trFifoWen=0, _rFifoWen=0;\nreg\t\t[C_FIFO_DATA_WIDTH-1:0]\trFifoData=0, _rFifoData=0;\nwire\t\t\t\t\t\t\twFifoFull;\n\nreg\t\t\t\t\t\t\t\trChnlTx=0, _rChnlTx=0;\nreg\t\t\t\t\t\t\t\trChnlLast=0, _rChnlLast=0;\nreg\t\t[31:0]\t\t\t\t\trChnlLen=0, _rChnlLen=0;\nreg\t\t[30:0]\t\t\t\t\trChnlOff=0, _rChnlOff=0;\nreg\t\t\t\t\t\t\t\trAck=0, _rAck=0;\nreg\t\t\t\t\t\t\t\trPause=0, _rPause=0;\nreg\t\t\t\t\t\t\t\trClosed=0, _rClosed=0;\n\n\nassign CHNL_TX_ACK = rAck;\nassign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE32_OPEN\n\n\n// Buffer the input signals that come from outside the tx_port.\nalways @ (posedge CHNL_CLK) begin\n\trChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);\n\trChnlLast <= #1 _rChnlLast;\n\trChnlLen <= #1 _rChnlLen;\n\trChnlOff <= #1 _rChnlOff;\nend\n\nalways @ (*) begin\n\t_rChnlTx = CHNL_TX;\n\t_rChnlLast = CHNL_TX_LAST;\n\t_rChnlLen = CHNL_TX_LEN;\n\t_rChnlOff = CHNL_TX_OFF;\nend\n\n\n// FIFO for temporarily storing data from the channel.\n(* RAM_STYLE=\"DISTRIBUTED\" *)\nasync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (\n\t.WR_CLK(CHNL_CLK),\n\t.WR_RST(RST),\n\t.WR_EN(rFifoWen),\n\t.WR_DATA(rFifoData),\n\t.WR_FULL(wFifoFull),\n\t.RD_CLK(RD_CLK),\n\t.RD_RST(RST),\n\t.RD_EN(RD_EN),\n\t.RD_DATA(RD_DATA),\n\t.RD_EMPTY(RD_EMPTY)\n);\n\n\n// Pass the transaction open event, transaction data, and the transaction\n// close event through to the RD_CLK domain via the async_fifo.\nalways @ (posedge CHNL_CLK) begin\n\trState <= #1 (RST ? `S_TXPORTGATE32_IDLE : _rState);\n\trFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);\n\trFifoData <= #1 _rFifoData;\n\trAck <= #1 (RST ? 1'd0 : _rAck);\n\trPause <= #1 (RST ? 1'd0 : _rPause);\n\trClosed <= #1 (RST ? 1'd0 : _rClosed);\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\t_rFifoWen = rFifoWen;\n\t_rFifoData = rFifoData;\n\t_rPause = rPause;\n\t_rAck = rAck;\n\t_rClosed = rClosed;\n\tcase (rState)\n\n\t`S_TXPORTGATE32_IDLE: begin // Write the len\n\t\t_rPause = 0;\n\t\t_rClosed = 0;\n\t\tif (!wFifoFull) begin\n\t\t\t_rFifoWen = rChnlTx;\n\t\t\t_rFifoData = {1'd1, rChnlLen};\n\t\t\tif (rChnlTx)\n\t\t\t\t_rState = `S_TXPORTGATE32_OPENING;\n\t\tend\n\tend\n\n\t`S_TXPORTGATE32_OPENING: begin // Write the off, last\n\t\t_rClosed = (rClosed | !rChnlTx);\n\t\tif (!wFifoFull) begin\n\t\t\t_rAck = rChnlTx;\n\t\t\t_rFifoData = {1'd1, rChnlOff, rChnlLast};\n\t\t\tif (rClosed | !rChnlTx)\n\t\t\t\t_rState = `S_TXPORTGATE32_CLOSED;\n\t\t\telse\n\t\t\t\t_rState = `S_TXPORTGATE32_OPEN;\n\t\tend\n\tend\n\n\t`S_TXPORTGATE32_OPEN: begin // Copy channel data into the FIFO\n\t\t_rAck = 0;\n\t\tif (!wFifoFull) begin\n\t\t\t_rFifoWen = CHNL_TX_DATA_VALID; \t// CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered\n\t\t\t_rFifoData = {1'd0, CHNL_TX_DATA};\t// but the VALID+REN model seem to make this difficult.\n\t\tend\n\t\tif (!rChnlTx)\n\t\t\t_rState = `S_TXPORTGATE32_CLOSED;\n\tend\n\t\n\t`S_TXPORTGATE32_CLOSED: begin // Write the end marker (twice)\n\t\t_rAck = 0;\n\t\tif (!wFifoFull) begin\n\t\t\t_rPause = 1;\n\t\t\t_rFifoWen = 1;\n\t\t\t_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};\n\t\t\tif (rPause)\n\t\t\t_rState = `S_TXPORTGATE32_IDLE;\n\t\tend\n\tend\n\t\n\tendcase\t\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_channel_gate_64.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_port_channel_gate_64.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tCaptures transaction open/close events as well as data\n// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can\n// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When\n// CHNL_TX drops, the channel closes (until the next transaction -- signaled by\n// CHNL_TX going up again).\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_TXPORTGATE64_IDLE\t\t2'b00\n`define S_TXPORTGATE64_OPENING\t2'b01\n`define S_TXPORTGATE64_OPEN\t\t2'b10\n`define S_TXPORTGATE64_CLOSED\t2'b11\n\nmodule tx_port_channel_gate_64 #(\n\tparameter C_DATA_WIDTH = 9'd64,\n\t// Local parameters\n\tparameter C_FIFO_DEPTH = 8,\n\tparameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1\n)\n(\n\tinput RST,\n\n\tinput RD_CLK,\t\t\t\t\t\t\t// FIFO read clock\n\toutput [C_FIFO_DATA_WIDTH-1:0] RD_DATA,\t// FIFO read data\n\toutput RD_EMPTY,\t\t\t\t\t\t// FIFO is empty\n\tinput RD_EN,\t\t\t\t\t\t\t// FIFO read enable\n\n\tinput CHNL_CLK,\t\t\t\t\t\t\t// Channel write clock\n\tinput CHNL_TX,\t\t\t\t\t\t\t// Channel write receive signal\n\toutput CHNL_TX_ACK,\t\t\t\t\t\t// Channel write acknowledgement signal\n\tinput CHNL_TX_LAST,\t\t\t\t\t\t// Channel last write\n\tinput [31:0] CHNL_TX_LEN,\t\t\t\t// Channel write length (in 32 bit words)\n\tinput [30:0] CHNL_TX_OFF,\t\t\t\t// Channel write offset\n\tinput [C_DATA_WIDTH-1:0] CHNL_TX_DATA,\t// Channel write data\n\tinput CHNL_TX_DATA_VALID,\t\t\t\t// Channel write data valid\n\toutput CHNL_TX_DATA_REN\t\t\t\t\t// Channel write data has been recieved\n);\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[1:0]\t\t\t\t\trState=`S_TXPORTGATE64_IDLE, _rState=`S_TXPORTGATE64_IDLE;\nreg\t\t\t\t\t\t\t\trFifoWen=0, _rFifoWen=0;\nreg\t\t[C_FIFO_DATA_WIDTH-1:0]\trFifoData=0, _rFifoData=0;\nwire\t\t\t\t\t\t\twFifoFull;\n\nreg\t\t\t\t\t\t\t\trChnlTx=0, _rChnlTx=0;\nreg\t\t\t\t\t\t\t\trChnlLast=0, _rChnlLast=0;\nreg\t\t[31:0]\t\t\t\t\trChnlLen=0, _rChnlLen=0;\nreg\t\t[30:0]\t\t\t\t\trChnlOff=0, _rChnlOff=0;\nreg\t\t\t\t\t\t\t\trAck=0, _rAck=0;\nreg\t\t\t\t\t\t\t\trPause=0, _rPause=0;\nreg\t\t\t\t\t\t\t\trClosed=0, _rClosed=0;\n\n\nassign CHNL_TX_ACK = rAck;\nassign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE64_OPEN\n\n\n// Buffer the input signals that come from outside the tx_port.\nalways @ (posedge CHNL_CLK) begin\n\trChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);\n\trChnlLast <= #1 _rChnlLast;\n\trChnlLen <= #1 _rChnlLen;\n\trChnlOff <= #1 _rChnlOff;\nend\n\nalways @ (*) begin\n\t_rChnlTx = CHNL_TX;\n\t_rChnlLast = CHNL_TX_LAST;\n\t_rChnlLen = CHNL_TX_LEN;\n\t_rChnlOff = CHNL_TX_OFF;\nend\n\n\n// FIFO for temporarily storing data from the channel.\n(* RAM_STYLE=\"DISTRIBUTED\" *)\nasync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (\n\t.WR_CLK(CHNL_CLK),\n\t.WR_RST(RST),\n\t.WR_EN(rFifoWen),\n\t.WR_DATA(rFifoData),\n\t.WR_FULL(wFifoFull),\n\t.RD_CLK(RD_CLK),\n\t.RD_RST(RST),\n\t.RD_EN(RD_EN),\n\t.RD_DATA(RD_DATA),\n\t.RD_EMPTY(RD_EMPTY)\n);\n\n\n// Pass the transaction open event, transaction data, and the transaction\n// close event through to the RD_CLK domain via the async_fifo.\nalways @ (posedge CHNL_CLK) begin\n\trState <= #1 (RST ? `S_TXPORTGATE64_IDLE : _rState);\n\trFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);\n\trFifoData <= #1 _rFifoData;\n\trAck <= #1 (RST ? 1'd0 : _rAck);\n\trPause <= #1 (RST ? 1'd0 : _rPause);\n\trClosed <= #1 (RST ? 1'd0 : _rClosed);\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\t_rFifoWen = rFifoWen;\n\t_rFifoData = rFifoData;\n\t_rPause = rPause;\n\t_rAck = rAck;\n\t_rClosed = rClosed;\n\tcase (rState)\n\n\t`S_TXPORTGATE64_IDLE: begin // Write the len, off, last\n\t\t_rPause = 0;\n\t\t_rClosed = 0;\n\t\tif (!wFifoFull) begin\n\t\t\t_rAck = rChnlTx;\n\t\t\t_rFifoWen = rChnlTx;\n\t\t\t_rFifoData = {1'd1, rChnlLen, rChnlOff, rChnlLast};\n\t\t\tif (rChnlTx)\n\t\t\t\t_rState = `S_TXPORTGATE64_OPENING;\n\t\tend\n\tend\n\n\t`S_TXPORTGATE64_OPENING: begin // Write the len, off, last (again)\n\t\t_rAck = 0;\n\t\t_rClosed = (rClosed | !rChnlTx);\n\t\tif (!wFifoFull) begin\n\t\t\tif (rClosed | !rChnlTx)\n\t\t\t\t_rState = `S_TXPORTGATE64_CLOSED;\n\t\t\telse\n\t\t\t\t_rState = `S_TXPORTGATE64_OPEN;\n\t\tend\n\tend\n\n\t`S_TXPORTGATE64_OPEN: begin // Copy channel data into the FIFO\n\t\tif (!wFifoFull) begin\n\t\t\t_rFifoWen = CHNL_TX_DATA_VALID; \t// CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered\n\t\t\t_rFifoData = {1'd0, CHNL_TX_DATA};\t// but the VALID+REN model seem to make this difficult.\n\t\tend\n\t\tif (!rChnlTx)\n\t\t\t_rState = `S_TXPORTGATE64_CLOSED;\n\tend\n\t\n\t`S_TXPORTGATE64_CLOSED: begin // Write the end marker (twice)\n\t\tif (!wFifoFull) begin\n\t\t\t_rPause = 1;\n\t\t\t_rFifoWen = 1;\n\t\t\t_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};\n\t\t\tif (rPause)\n\t\t\t_rState = `S_TXPORTGATE64_IDLE;\n\t\tend\n\tend\n\t\n\tendcase\t\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_monitor_128.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_port_monitor_128.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tDetects transaction open/close events from the stream\n// of data from the tx_port_channel_gate. Filters out events and passes data\n// onto the tx_port_buffer. \n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_TXPORTMON128_NEXT\t\t5'b0_0001\n`define S_TXPORTMON128_TXN\t\t5'b0_0010\n`define S_TXPORTMON128_READ\t\t5'b0_0100\n`define S_TXPORTMON128_END_0\t5'b0_1000\n`define S_TXPORTMON128_END_1\t5'b1_0000\n\nmodule tx_port_monitor_128 #(\n\tparameter C_DATA_WIDTH = 9'd128,\n\tparameter C_FIFO_DEPTH = 512,\n\t// Local parameters\n\tparameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),\n\tparameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),\n\tparameter C_VALID_HIST = 1\n)\n(\n\tinput RST,\n\tinput CLK,\n\n\tinput [C_DATA_WIDTH:0] EVT_DATA,\t\t\t// Event data from tx_port_channel_gate\n\tinput EVT_DATA_EMPTY,\t\t\t\t\t\t// Event data FIFO is empty\n\toutput EVT_DATA_RD_EN,\t\t\t\t\t\t// Event data FIFO read enable\n\n\toutput [C_DATA_WIDTH-1:0] WR_DATA,\t\t\t// Output data\n\toutput WR_EN,\t\t\t\t\t\t\t\t// Write enable for output data\n\tinput [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,\t// Output FIFO count\n\n\toutput TXN,\t\t\t\t\t\t\t\t\t// Transaction parameters are valid\n\tinput ACK,\t\t\t\t\t\t\t\t\t// Transaction parameter read, continue\n\toutput LAST,\t\t\t\t\t\t\t\t// Channel last write\n\toutput [31:0] LEN,\t\t\t\t\t\t\t// Channel write length (in 32 bit words)\n\toutput [30:0] OFF,\t\t\t\t\t\t\t// Channel write offset\n\toutput [31:0] WORDS_RECVD,\t\t\t\t\t// Count of data words received in transaction\n\toutput DONE,\t\t\t\t\t\t\t\t// Transaction is closed\n\n\tinput TX_ERR\t\t\t\t\t\t\t\t// Transaction encountered an error\n);\n\n`include \"common_functions.v\"\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg \t[4:0]\t\t\t\trState=`S_TXPORTMON128_NEXT, _rState=`S_TXPORTMON128_NEXT;\nreg \t\t\t\t\t\trRead=0, _rRead=0;\nreg \t[C_VALID_HIST-1:0]\trDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};\nreg \t\t\t\t\t\trEvent=0, _rEvent=0;\nreg \t[63:0]\t\t\t\trReadData=64'd0, _rReadData=64'd0;\nreg \t[31:0]\t\t\t\trWordsRecvd=0, _rWordsRecvd=0;\nreg \t[31:0]\t\t\t\trWordsRecvdAdv=0, _rWordsRecvdAdv=0;\nreg \t\t\t\t\t\trAlmostAllRecvd=0, _rAlmostAllRecvd=0;\nreg \t\t\t\t\t\trAlmostFull=0, _rAlmostFull=0;\nreg \t\t\t\t\t\trLenEQ0Hi=0, _rLenEQ0Hi=0;\nreg \t\t\t\t\t\trLenEQ0Lo=0, _rLenEQ0Lo=0;\nreg \t\t\t\t\t\trLenLE4Lo=0, _rLenLE4Lo=0;\nreg\t\t\t\t\t\t\trTxErr=0, _rTxErr=0;\n\n\nassign EVT_DATA_RD_EN = rRead;\n\nassign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];\nassign WR_EN = wPayloadData; // S_TXPORTMON128_READ\n\nassign TXN = rState[1]; // S_TXPORTMON128_TXN\nassign LAST = rReadData[0];\nassign OFF = rReadData[31:1];\nassign LEN = rReadData[63:32];\nassign WORDS_RECVD = rWordsRecvd;\nassign DONE = !rState[2]; // !S_TXPORTMON128_READ\n\n\nwire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);\nwire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON128_READ\nwire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE4Lo)) & wPayloadData);\n\n\n// Buffer the input signals that come from outside the tx_port.\nalways @ (posedge CLK) begin\n\trTxErr <= #1 (RST ? 1'd0 : _rTxErr);\nend\n\nalways @ (*) begin\n\t_rTxErr = TX_ERR;\nend\n\n\n// Transaction monitoring FSM.\nalways @ (posedge CLK) begin\n\trState <= #1 (RST ? `S_TXPORTMON128_NEXT : _rState);\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\tcase (rState)\n\n\t`S_TXPORTMON128_NEXT: begin // Read, wait for start of transaction event\n\t\tif (rEvent)\n\t\t\t_rState = `S_TXPORTMON128_TXN;\n\tend\n\n\t`S_TXPORTMON128_TXN: begin // Don't read, wait until transaction has been acknowledged\n\t\tif (ACK)\n\t\t\t_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON128_END_0 : `S_TXPORTMON128_READ);\n\tend\n\n\t`S_TXPORTMON128_READ: begin // Continue reading, wait for end of transaction event or all expected data\n\t\tif (rEvent)\n\t\t\t_rState = `S_TXPORTMON128_END_1;\n\t\telse if (wAllWordsRecvd | rTxErr)\n\t\t\t_rState = `S_TXPORTMON128_END_0;\n\tend\n\t\n\t`S_TXPORTMON128_END_0: begin // Continue reading, wait for first end of transaction event\n\t\tif (rEvent)\n\t\t\t_rState = `S_TXPORTMON128_END_1;\n\tend\n\n\t`S_TXPORTMON128_END_1: begin // Continue reading, wait for second end of transaction event\n\t\tif (rEvent)\n\t\t\t_rState = `S_TXPORTMON128_NEXT;\n\tend\n\n\tdefault: begin\n\t\t_rState = `S_TXPORTMON128_NEXT;\n\tend\n\n\tendcase\t\nend\n\n\n// Manage reading from the FIFO and tracking amounts read.\nalways @ (posedge CLK) begin\n\trRead <= #1 (RST ? 1'd0 : _rRead);\n\trDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);\n\trEvent <= #1 (RST ? 1'd0 : _rEvent);\n\trReadData <= #1 _rReadData;\n\trWordsRecvd <= #1 _rWordsRecvd;\n\trWordsRecvdAdv <= #1 _rWordsRecvdAdv;\n\trAlmostAllRecvd <= #1 _rAlmostAllRecvd;\n\trAlmostFull <= #1 _rAlmostFull;\n\trLenEQ0Hi <= #1 _rLenEQ0Hi;\n\trLenEQ0Lo <= #1 _rLenEQ0Lo;\n\trLenLE4Lo <= #1 _rLenLE4Lo;\nend\n\nalways @ (*) begin\n\t// Don't get to the full point in the output FIFO\n\t_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);\n\n\t// Track read history so we know when data is valid\n\t_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));\n\n\t// Read until we get a (valid) event\n\t_rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON128_TXN\n\n\t// Track detected events\n\t_rEvent = wEventData;\n\n\t// Save event data when valid\n\tif (wEventData)\n\t\t_rReadData = EVT_DATA[63:0];\n\telse\n\t\t_rReadData = rReadData;\n\t\n\t// If LEN == 0, we don't want to send any data to the output\n\t_rLenEQ0Hi = (LEN[31:16] == 16'd0);\n\t_rLenEQ0Lo = (LEN[15:0] == 16'd0);\n\n\t// If LEN <= 4, we want to trigger the almost all received flag\n\t_rLenLE4Lo = (LEN[15:0] <= 16'd4);\n\t\n\t// Count received non-event data\n\t_rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<2));\n\t_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<2));\n\t_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_monitor_32.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_port_monitor_32.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tDetects transaction open/close events from the stream\n// of data from the tx_port_channel_gate. Filters out events and passes data\n// onto the tx_port_buffer. \n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_TXPORTMON32_NEXT\t5'b0_0001\n`define S_TXPORTMON32_TXN\t5'b0_0010\n`define S_TXPORTMON32_READ\t5'b0_0100\n`define S_TXPORTMON32_END_0\t5'b0_1000\n`define S_TXPORTMON32_END_1\t5'b1_0000\n\nmodule tx_port_monitor_32 #(\n\tparameter C_DATA_WIDTH = 9'd32,\n\tparameter C_FIFO_DEPTH = 512,\n\t// Local parameters\n\tparameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),\n\tparameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),\n\tparameter C_VALID_HIST = 1\n)\n(\n\tinput RST,\n\tinput CLK,\n\n\tinput [C_DATA_WIDTH:0] EVT_DATA,\t\t\t// Event data from tx_port_channel_gate\n\tinput EVT_DATA_EMPTY,\t\t\t\t\t\t// Event data FIFO is empty\n\toutput EVT_DATA_RD_EN,\t\t\t\t\t\t// Event data FIFO read enable\n\n\toutput [C_DATA_WIDTH-1:0] WR_DATA,\t\t\t// Output data\n\toutput WR_EN,\t\t\t\t\t\t\t\t// Write enable for output data\n\tinput [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,\t// Output FIFO count\n\n\toutput TXN,\t\t\t\t\t\t\t\t\t// Transaction parameters are valid\n\tinput ACK,\t\t\t\t\t\t\t\t\t// Transaction parameter read, continue\n\toutput LAST,\t\t\t\t\t\t\t\t// Channel last write\n\toutput [31:0] LEN,\t\t\t\t\t\t\t// Channel write length (in 32 bit words)\n\toutput [30:0] OFF,\t\t\t\t\t\t\t// Channel write offset\n\toutput [31:0] WORDS_RECVD,\t\t\t\t\t// Count of data words received in transaction\n\toutput DONE,\t\t\t\t\t\t\t\t// Transaction is closed\n\n\tinput TX_ERR\t\t\t\t\t\t\t\t// Transaction encountered an error\n);\n\n`include \"common_functions.v\"\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg \t[4:0]\t\t\t\trState=`S_TXPORTMON32_NEXT, _rState=`S_TXPORTMON32_NEXT;\nreg \t\t\t\t\t\trRead=0, _rRead=0;\nreg \t[C_VALID_HIST-1:0]\trDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};\nreg \t\t\t\t\t\trEvent=0, _rEvent=0;\nreg \t[31:0]\t\t\t\trReadOffLast=0, _rReadOffLast=0;\nreg \t[31:0]\t\t\t\trReadLen=0, _rReadLen=0;\nreg \t\t\t\t\t\trReadCount=0, _rReadCount=0;\nreg \t[31:0]\t\t\t\trWordsRecvd=0, _rWordsRecvd=0;\nreg \t[31:0]\t\t\t\trWordsRecvdAdv=0, _rWordsRecvdAdv=0;\nreg \t\t\t\t\t\trAlmostAllRecvd=0, _rAlmostAllRecvd=0;\nreg \t\t\t\t\t\trAlmostFull=0, _rAlmostFull=0;\nreg \t\t\t\t\t\trLenEQ0Hi=0, _rLenEQ0Hi=0;\nreg \t\t\t\t\t\trLenEQ0Lo=0, _rLenEQ0Lo=0;\nreg \t\t\t\t\t\trLenLE1Lo=0, _rLenLE1Lo=0;\nreg\t\t\t\t\t\t\trTxErr=0, _rTxErr=0;\n\n\nassign EVT_DATA_RD_EN = rRead;\n\nassign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];\nassign WR_EN = wPayloadData;\n\nassign TXN = rState[1]; // S_TXPORTMON32_TXN\nassign LAST = rReadOffLast[0];\nassign OFF = rReadOffLast[31:1];\nassign LEN = rReadLen;\nassign WORDS_RECVD = rWordsRecvd;\nassign DONE = !rState[2]; // !S_TXPORTMON32_READ\n\n\nwire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);\nwire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON32_READ\nwire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE1Lo)) & wPayloadData);\n\n\n// Buffer the input signals that come from outside the tx_port.\nalways @ (posedge CLK) begin\n\trTxErr <= #1 (RST ? 1'd0 : _rTxErr);\nend\n\nalways @ (*) begin\n\t_rTxErr = TX_ERR;\nend\n\n\n// Transaction monitoring FSM.\nalways @ (posedge CLK) begin\n\trState <= #1 (RST ? `S_TXPORTMON32_NEXT : _rState);\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\tcase (rState)\n\n\t`S_TXPORTMON32_NEXT: begin // Read, wait for start of transaction event\n\t\tif (rEvent)\n\t\t\t_rState = `S_TXPORTMON32_TXN;\n\tend\n\n\t`S_TXPORTMON32_TXN: begin // Don't read, wait until transaction has been acknowledged\n\t\tif (ACK)\n\t\t\t_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON32_END_0 : `S_TXPORTMON32_READ);\n\tend\n\n\t`S_TXPORTMON32_READ: begin // Continue reading, wait for end of transaction event or all expected data\n\t\tif (rEvent)\n\t\t\t_rState = `S_TXPORTMON32_END_1;\n\t\telse if (wAllWordsRecvd | rTxErr)\n\t\t\t_rState = `S_TXPORTMON32_END_0;\n\tend\n\t\n\t`S_TXPORTMON32_END_0: begin // Continue reading, wait for first end of transaction event\n\t\tif (rEvent)\n\t\t\t_rState = `S_TXPORTMON32_END_1;\n\tend\n\n\t`S_TXPORTMON32_END_1: begin // Continue reading, wait for second end of transaction event\n\t\tif (rEvent)\n\t\t\t_rState = `S_TXPORTMON32_NEXT;\n\tend\n\n\tdefault: begin\n\t\t_rState = `S_TXPORTMON32_NEXT;\n\tend\n\n\tendcase\t\nend\n\n\n// Manage reading from the FIFO and tracking amounts read.\nalways @ (posedge CLK) begin\n\trRead <= #1 (RST ? 1'd0 : _rRead);\n\trDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);\n\trEvent <= #1 (RST ? 1'd0 : _rEvent);\n\trReadOffLast <= #1 _rReadOffLast;\n\trReadLen <= #1 _rReadLen;\n\trReadCount <= #1 (RST ? 1'd0 : _rReadCount);\n\trWordsRecvd <= #1 _rWordsRecvd;\n\trWordsRecvdAdv <= #1 _rWordsRecvdAdv;\n\trAlmostAllRecvd <= #1 _rAlmostAllRecvd;\n\trAlmostFull <= #1 _rAlmostFull;\n\trLenEQ0Hi <= #1 _rLenEQ0Hi;\n\trLenEQ0Lo <= #1 _rLenEQ0Lo;\n\trLenLE1Lo <= #1 _rLenLE1Lo;\nend\n\nalways @ (*) begin\n\t// Don't get to the full point in the output FIFO\n\t_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);\n\n\t// Track read history so we know when data is valid\n\t_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));\n\n\t// Read until we get a (valid) event\n\t_rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON32_TXN\n\n\t// Track detected events\n\t_rEvent = wEventData;\n\n\t// Save event data when valid\n\tif (wEventData) begin\n\t\t_rReadOffLast = (rReadCount ? EVT_DATA[C_DATA_WIDTH-1:0] : rReadOffLast);\n\t\t_rReadLen = (!rReadCount ? EVT_DATA[C_DATA_WIDTH-1:0] : rReadLen);\n\t\t_rReadCount = rReadCount + 1'd1;\n\tend\n\telse begin\n\t\t_rReadOffLast = rReadOffLast;\n\t\t_rReadLen = rReadLen;\n\t\t_rReadCount = rReadCount;\n\tend\n\t\n\t// If LEN == 0, we don't want to send any data to the output\n\t_rLenEQ0Hi = (LEN[31:16] == 16'd0);\n\t_rLenEQ0Lo = (LEN[15:0] == 16'd0);\n\n\t// If LEN <= 1, we want to trigger the almost all received flag\n\t_rLenLE1Lo = (LEN[15:0] <= 16'd1);\n\t\n\t// Count received non-event data\n\t_rWordsRecvd = (ACK ? 0 : rWordsRecvd + wPayloadData);\n\t_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + wPayloadData);\n\t_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_monitor_64.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_port_monitor_64.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tDetects transaction open/close events from the stream\n// of data from the tx_port_channel_gate. Filters out events and passes data\n// onto the tx_port_buffer. \n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_TXPORTMON64_NEXT\t5'b0_0001\n`define S_TXPORTMON64_TXN\t5'b0_0010\n`define S_TXPORTMON64_READ\t5'b0_0100\n`define S_TXPORTMON64_END_0\t5'b0_1000\n`define S_TXPORTMON64_END_1\t5'b1_0000\n\nmodule tx_port_monitor_64 #(\n\tparameter C_DATA_WIDTH = 9'd64,\n\tparameter C_FIFO_DEPTH = 512,\n\t// Local parameters\n\tparameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),\n\tparameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),\n\tparameter C_VALID_HIST = 1\n)\n(\n\tinput RST,\n\tinput CLK,\n\n\tinput [C_DATA_WIDTH:0] EVT_DATA,\t\t\t// Event data from tx_port_channel_gate\n\tinput EVT_DATA_EMPTY,\t\t\t\t\t\t// Event data FIFO is empty\n\toutput EVT_DATA_RD_EN,\t\t\t\t\t\t// Event data FIFO read enable\n\n\toutput [C_DATA_WIDTH-1:0] WR_DATA,\t\t\t// Output data\n\toutput WR_EN,\t\t\t\t\t\t\t\t// Write enable for output data\n\tinput [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,\t// Output FIFO count\n\n\toutput TXN,\t\t\t\t\t\t\t\t\t// Transaction parameters are valid\n\tinput ACK,\t\t\t\t\t\t\t\t\t// Transaction parameter read, continue\n\toutput LAST,\t\t\t\t\t\t\t\t// Channel last write\n\toutput [31:0] LEN,\t\t\t\t\t\t\t// Channel write length (in 32 bit words)\n\toutput [30:0] OFF,\t\t\t\t\t\t\t// Channel write offset\n\toutput [31:0] WORDS_RECVD,\t\t\t\t\t// Count of data words received in transaction\n\toutput DONE,\t\t\t\t\t\t\t\t// Transaction is closed\n\n\tinput TX_ERR\t\t\t\t\t\t\t\t// Transaction encountered an error\n);\n\n`include \"common_functions.v\"\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg \t[4:0]\t\t\t\trState=`S_TXPORTMON64_NEXT, _rState=`S_TXPORTMON64_NEXT;\nreg \t\t\t\t\t\trRead=0, _rRead=0;\nreg \t[C_VALID_HIST-1:0]\trDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};\nreg \t\t\t\t\t\trEvent=0, _rEvent=0;\nreg \t[63:0]\t\t\t\trReadData=64'd0, _rReadData=64'd0;\nreg \t[31:0]\t\t\t\trWordsRecvd=0, _rWordsRecvd=0;\nreg \t[31:0]\t\t\t\trWordsRecvdAdv=0, _rWordsRecvdAdv=0;\nreg \t\t\t\t\t\trAlmostAllRecvd=0, _rAlmostAllRecvd=0;\nreg \t\t\t\t\t\trAlmostFull=0, _rAlmostFull=0;\nreg \t\t\t\t\t\trLenEQ0Hi=0, _rLenEQ0Hi=0;\nreg \t\t\t\t\t\trLenEQ0Lo=0, _rLenEQ0Lo=0;\nreg \t\t\t\t\t\trLenLE2Lo=0, _rLenLE2Lo=0;\nreg\t\t\t\t\t\t\trTxErr=0, _rTxErr=0;\n\n\nassign EVT_DATA_RD_EN = rRead;\n\nassign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];\nassign WR_EN = wPayloadData; // S_TXPORTMON64_READ\n\nassign TXN = rState[1]; // S_TXPORTMON64_TXN\nassign LAST = rReadData[0];\nassign OFF = rReadData[31:1];\nassign LEN = rReadData[63:32];\nassign WORDS_RECVD = rWordsRecvd;\nassign DONE = !rState[2]; // !S_TXPORTMON64_READ\n\n\nwire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);\nwire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON64_READ\nwire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE2Lo)) & wPayloadData);\n\n\n// Buffer the input signals that come from outside the tx_port.\nalways @ (posedge CLK) begin\n\trTxErr <= #1 (RST ? 1'd0 : _rTxErr);\nend\n\nalways @ (*) begin\n\t_rTxErr = TX_ERR;\nend\n\n\n// Transaction monitoring FSM.\nalways @ (posedge CLK) begin\n\trState <= #1 (RST ? `S_TXPORTMON64_NEXT : _rState);\nend\n\nalways @ (*) begin\n\t_rState = rState;\n\tcase (rState)\n\n\t`S_TXPORTMON64_NEXT: begin // Read, wait for start of transaction event\n\t\tif (rEvent)\n\t\t\t_rState = `S_TXPORTMON64_TXN;\n\tend\n\n\t`S_TXPORTMON64_TXN: begin // Don't read, wait until transaction has been acknowledged\n\t\tif (ACK)\n\t\t\t_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON64_END_0 : `S_TXPORTMON64_READ);\n\tend\n\n\t`S_TXPORTMON64_READ: begin // Continue reading, wait for end of transaction event or all expected data\n\t\tif (rEvent)\n\t\t\t_rState = `S_TXPORTMON64_END_1;\n\t\telse if (wAllWordsRecvd | rTxErr)\n\t\t\t_rState = `S_TXPORTMON64_END_0;\n\tend\n\t\n\t`S_TXPORTMON64_END_0: begin // Continue reading, wait for first end of transaction event\n\t\tif (rEvent)\n\t\t\t_rState = `S_TXPORTMON64_END_1;\n\tend\n\n\t`S_TXPORTMON64_END_1: begin // Continue reading, wait for second end of transaction event\n\t\tif (rEvent)\n\t\t\t_rState = `S_TXPORTMON64_NEXT;\n\tend\n\n\tdefault: begin\n\t\t_rState = `S_TXPORTMON64_NEXT;\n\tend\n\n\tendcase\t\nend\n\n\n// Manage reading from the FIFO and tracking amounts read.\nalways @ (posedge CLK) begin\n\trRead <= #1 (RST ? 1'd0 : _rRead);\n\trDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);\n\trEvent <= #1 (RST ? 1'd0 : _rEvent);\n\trReadData <= #1 _rReadData;\n\trWordsRecvd <= #1 _rWordsRecvd;\n\trWordsRecvdAdv <= #1 _rWordsRecvdAdv;\n\trAlmostAllRecvd <= #1 _rAlmostAllRecvd;\n\trAlmostFull <= #1 _rAlmostFull;\n\trLenEQ0Hi <= #1 _rLenEQ0Hi;\n\trLenEQ0Lo <= #1 _rLenEQ0Lo;\n\trLenLE2Lo <= #1 _rLenLE2Lo;\nend\n\nalways @ (*) begin\n\t// Don't get to the full point in the output FIFO\n\t_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);\n\n\t// Track read history so we know when data is valid\n\t_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));\n\n\t// Read until we get a (valid) event\n\t_rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON64_TXN\n\n\t// Track detected events\n\t_rEvent = wEventData;\n\n\t// Save event data when valid\n\tif (wEventData)\n\t\t_rReadData = EVT_DATA[C_DATA_WIDTH-1:0];\n\telse\n\t\t_rReadData = rReadData;\n\t\n\t// If LEN == 0, we don't want to send any data to the output\n\t_rLenEQ0Hi = (LEN[31:16] == 16'd0);\n\t_rLenEQ0Lo = (LEN[15:0] == 16'd0);\n\n\t// If LEN <= 2, we want to trigger the almost all received flag\n\t_rLenLE2Lo = (LEN[15:0] <= 16'd2);\n\t\n\t// Count received non-event data\n\t_rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<1));\n\t_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<1));\n\t_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);\nend\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_writer.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n// Filename:\t\t\ttx_port_writer.v\n// Version:\t\t\t\t1.00.a\n// Verilog Standard:\tVerilog-2001\n// Description:\t\t\tHandles receiving new transaction events and data, and\n// making requests to tx engine. \n//\t\t\t\t\t\tfor the RIFFA channel.\n// Author:\t\t\t\tMatt Jacobsen\n// History:\t\t\t\t@mattj: Version 2.0\n//-----------------------------------------------------------------------------\n`define S_TXPORTWR_MAIN_IDLE\t\t8'b0000_0001\n`define S_TXPORTWR_MAIN_CHECK\t\t8'b0000_0010\n`define S_TXPORTWR_MAIN_SIG_NEW\t\t8'b0000_0100\n`define S_TXPORTWR_MAIN_NEW_ACK\t\t8'b0000_1000\n`define S_TXPORTWR_MAIN_WRITE\t\t8'b0001_0000\n`define S_TXPORTWR_MAIN_DONE\t\t8'b0010_0000\n`define S_TXPORTWR_MAIN_SIG_DONE\t8'b0100_0000\n`define S_TXPORTWR_MAIN_RESET\t\t8'b1000_0000\n\n`define S_TXPORTWR_TX_IDLE\t\t\t8'b0000_0001\n`define S_TXPORTWR_TX_BUF\t\t\t8'b0000_0010\n`define S_TXPORTWR_TX_ADJ_0\t\t\t8'b0000_0100\n`define S_TXPORTWR_TX_ADJ_1\t\t\t8'b0000_1000\n`define S_TXPORTWR_TX_ADJ_2\t\t\t8'b0001_0000\n`define S_TXPORTWR_TX_CHECK_DATA\t8'b0010_0000\n`define S_TXPORTWR_TX_WRITE\t\t\t8'b0100_0000\n`define S_TXPORTWR_TX_WRITE_REM\t\t8'b1000_0000\n\nmodule tx_port_writer (\n\tinput CLK,\n\tinput RST,\n\tinput [2:0] CONFIG_MAX_PAYLOAD_SIZE,\t// Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B\n\n\toutput TXN,\t\t\t\t\t\t\t// Write transaction notification\n\tinput TXN_ACK,\t\t\t\t\t\t// Write transaction acknowledged\n\toutput [31:0] TXN_LEN,\t\t\t\t// Write transaction length\n\toutput [31:0] TXN_OFF_LAST,\t\t\t// Write transaction offset/last\n\toutput [31:0] TXN_DONE_LEN,\t\t\t// Write transaction actual transfer length\n\toutput TXN_DONE,\t\t\t\t\t// Write transaction done\n\toutput TXN_ERR,\t\t\t\t\t\t// Write transaction encountered an error\n\tinput TXN_DONE_ACK,\t\t\t\t\t// Write transaction actual transfer length read\n\n\tinput NEW_TXN,\t\t\t\t\t\t// Transaction parameters are valid\n\toutput NEW_TXN_ACK,\t\t\t\t\t// Transaction parameter read, continue\n\tinput NEW_TXN_LAST,\t\t\t\t\t// Channel last write\n\tinput [31:0] NEW_TXN_LEN,\t\t\t// Channel write length (in 32 bit words)\n\tinput [30:0] NEW_TXN_OFF,\t\t\t// Channel write offset\n\tinput [31:0] NEW_TXN_WORDS_RECVD,\t// Count of data words received in transaction\n\tinput NEW_TXN_DONE,\t\t\t\t\t// Transaction is closed\n\n\tinput [63:0] SG_ELEM_ADDR,\t\t\t// Scatter gather element address\n\tinput [31:0] SG_ELEM_LEN,\t\t\t// Scatter gather element length (in words)\n\tinput SG_ELEM_RDY,\t\t\t\t\t// Scatter gather element ready\n\tinput SG_ELEM_EMPTY,\t\t\t\t// Scatter gather elements empty\n\toutput SG_ELEM_REN,\t\t\t\t\t// Scatter gather element read enable\n\toutput SG_RST,\t\t\t\t\t\t// Scatter gather data reset\n\tinput SG_ERR,\t\t\t\t\t\t// Scatter gather read encountered an error\n\t\n\toutput TX_REQ,\t\t\t\t\t\t// Outgoing write request\n\tinput TX_REQ_ACK,\t\t\t\t\t// Outgoing write request acknowledged\n\toutput [63:0] TX_ADDR,\t\t\t\t// Outgoing write high address\n\toutput [9:0] TX_LEN,\t\t\t\t// Outgoing write length (in 32 bit words)\n\toutput TX_LAST,\t\t\t\t\t\t// Outgoing write is last request for transaction\n\tinput TX_SENT\t\t\t\t\t\t// Outgoing write complete\n);\n\n`include \"common_functions.v\"\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[7:0]\t\t\t\t\t\trMainState=`S_TXPORTWR_MAIN_IDLE, _rMainState=`S_TXPORTWR_MAIN_IDLE;\nreg\t\t[31:0]\t\t\t\t\t\trOffLast=0, _rOffLast=0;\nreg\t\t\t\t\t\t\t\t\trWordsEQ0=0, _rWordsEQ0=0;\nreg\t\t\t\t\t\t\t\t\trStarted=0, _rStarted=0;\nreg\t\t[31:0]\t\t\t\t\t\trDoneLen=0, _rDoneLen=0;\nreg\t\t\t\t\t\t\t\t\trSgErr=0, _rSgErr=0;\nreg\t\t\t\t\t\t\t\t\trTxErrd=0, _rTxErrd=0;\nreg\t\t\t\t\t\t\t\t\trTxnAck=0, _rTxnAck=0;\n\n(* syn_encoding = \"user\" *)\n(* fsm_encoding = \"user\" *)\nreg\t\t[7:0]\t\t\t\t\t\trTxState=`S_TXPORTWR_TX_IDLE, _rTxState=`S_TXPORTWR_TX_IDLE;\nreg\t\t[31:0]\t\t\t\t\t\trSentWords=0, _rSentWords=0;\nreg\t\t[31:0]\t\t\t\t\t\trWords=0, _rWords=0;\nreg\t\t[31:0]\t\t\t\t\t\trBufWords=0, _rBufWords=0;\nreg\t\t[31:0]\t\t\t\t\t\trBufWordsInit=0, _rBufWordsInit=0;\nreg\t\t\t\t\t\t\t\t\trLargeBuf=0, _rLargeBuf=0;\nreg\t\t[63:0]\t\t\t\t\t\trAddr=64'd0, _rAddr=64'd0;\nreg\t\t[2:0]\t\t\t\t\t\trCarry=0, _rCarry=0;\nreg\t\t\t\t\t\t\t\t\trValsPropagated=0, _rValsPropagated=0;\nreg\t\t[5:0]\t\t\t\t\t\trValsProp=0, _rValsProp=0;\nreg\t\t\t\t\t\t\t\t\trCopyBufWords=0, _rCopyBufWords=0;\nreg\t\t\t\t\t\t\t\t\trUseInit=0, _rUseInit=0;\nreg\t\t[10:0]\t\t\t\t\t\trPageRem=0, _rPageRem=0;\nreg\t\t\t\t\t\t\t\t\trPageSpill=0, _rPageSpill=0;\nreg\t\t\t\t\t\t\t\t\trPageSpillInit=0, _rPageSpillInit=0;\nreg\t\t[10:0]\t\t\t\t\t\trPreLen=0, _rPreLen=0;\nreg\t\t[2:0]\t\t\t\t\t\trMaxPayloadSize=0, _rMaxPayloadSize=0;\nreg\t\t[2:0]\t\t\t\t\t\trMaxPayloadShift=0, _rMaxPayloadShift=0;\nreg\t\t[9:0]\t\t\t\t\t\trMaxPayload=0, _rMaxPayload=0;\nreg\t\t\t\t\t\t\t\t\trPayloadSpill=0, _rPayloadSpill=0;\nreg\t\t\t\t\t\t\t\t\trMaxLen=1, _rMaxLen=1;\nreg\t\t[9:0]\t\t\t\t\t\trLen=0, _rLen=0;\nreg\t\t[31:0]\t\t\t\t\t\trSendingWords=0, _rSendingWords=0;\nreg\t\t\t\t\t\t\t\t\trAvail=0, _rAvail=0;\nreg\t\t[1:0]\t\t\t\t\t\trTxnDone=0, _rTxnDone=0;\nreg\t\t[9:0]\t\t\t\t\t\trLastLen=0, _rLastLen=0;\nreg\t\t\t\t\t\t\t\t\trLastLenEQ0=0, _rLastLenEQ0=0;\nreg\t\t\t\t\t\t\t\t\trLenEQWords=0, _rLenEQWords=0;\nreg\t\t\t\t\t\t\t\t\trLenEQBufWords=0, _rLenEQBufWords=0;\n\nreg\t\t\t\t\t\t\t\t\trNotRequesting=1, _rNotRequesting=1;\nreg\t\t[63:0]\t\t\t\t\t\trReqAddr=64'd0, _rReqAddr=64'd0;\nreg\t\t[9:0]\t\t\t\t\t\trReqLen=0, _rReqLen=0;\nreg\t\t\t\t\t\t\t\t\trReqLast=0, _rReqLast=0;\nreg\t\t\t\t\t\t\t\t\trTxReqAck=0, _rTxReqAck=0;\n\nreg\t\t\t\t\t\t\t\t\trDone=0, _rDone=0;\nreg\t\t[9:0]\t\t\t\t\t\trAckCount=0, _rAckCount=0;\nreg\t\t\t\t\t\t\t\t\trTxSent=0, _rTxSent=0;\nreg\t\t\t\t\t\t\t\t\trLastDoneRead=1, _rLastDoneRead=1;\nreg\t\t\t\t\t\t\t\t\trTxnDoneAck=0, _rTxnDoneAck=0;\n\nreg\t\t\t\t\t\t\t\t\trReqPartialDone=0, _rReqPartialDone=0;\nreg\t\t\t\t\t\t\t\t\trPartialDone=0, _rPartialDone=0;\n\n\nassign NEW_TXN_ACK = rMainState[1]; // S_TXPORTWR_MAIN_CHECK\n\nassign TXN = rMainState[2]; // S_TXPORTWR_MAIN_SIG_NEW\nassign TXN_DONE = (rMainState[6] | rPartialDone); // S_TXPORTWR_MAIN_SIG_DONE\nassign TXN_LEN = rWords;\nassign TXN_OFF_LAST = rOffLast;\nassign TXN_DONE_LEN = rDoneLen;\nassign TXN_ERR = rTxErrd;\n\nassign SG_ELEM_REN = rTxState[2]; // S_TXPORTWR_TX_ADJ_0\nassign SG_RST = rMainState[3]; // S_TXPORTWR_MAIN_NEW_ACK\n\nassign TX_REQ = !rNotRequesting;\nassign TX_ADDR = rReqAddr; \nassign TX_LEN = rReqLen;\nassign TX_LAST = rReqLast;\n\n\n// Buffer the input signals that come from outside the tx_port.\nalways @ (posedge CLK) begin\n\trTxnAck <= #1 (RST ? 1'd0 : _rTxnAck);\n\trTxnDoneAck <= #1 (RST ? 1'd0 : _rTxnDoneAck);\n\trSgErr <= #1 (RST ? 1'd0 : _rSgErr);\n\trTxReqAck <= #1 (RST ? 1'd0 : _rTxReqAck);\n\trTxSent <= #1 (RST ? 1'd0 : _rTxSent);\nend\n\nalways @ (*) begin\n\t_rTxnAck = TXN_ACK;\n\t_rTxnDoneAck = TXN_DONE_ACK;\n\t_rSgErr = SG_ERR;\n\t_rTxReqAck = TX_REQ_ACK;\n\t_rTxSent = TX_SENT;\nend\n\t\n\n// Wait for a NEW_TXN request. Then request transfers until all the data is sent\n// or until the specified length is reached. Then signal TXN_DONE.\nalways @ (posedge CLK) begin\n\trMainState <= #1 (RST ? `S_TXPORTWR_MAIN_IDLE : _rMainState);\n\trOffLast <= #1 _rOffLast;\n\trWordsEQ0 <= #1 _rWordsEQ0;\n\trStarted <= #1 _rStarted;\n\trDoneLen <= #1 (RST ? 0 : _rDoneLen);\n\trTxErrd <= #1 (RST ? 1'd0 : _rTxErrd);\nend\n\nalways @ (*) begin\n\t_rMainState = rMainState;\n\t_rOffLast = rOffLast;\n\t_rWordsEQ0 = rWordsEQ0;\n\t_rStarted = rStarted;\n\t_rDoneLen = rDoneLen;\n\t_rTxErrd = rTxErrd;\n\tcase (rMainState)\n\n\t`S_TXPORTWR_MAIN_IDLE: begin // Wait for channel write request\n\t\t_rStarted = 0;\n\t\t_rWordsEQ0 = (NEW_TXN_LEN == 0);\n\t\t_rOffLast = {NEW_TXN_OFF, NEW_TXN_LAST};\n\t\tif (NEW_TXN)\n\t\t\t_rMainState = `S_TXPORTWR_MAIN_CHECK;\n\tend\n\n\t`S_TXPORTWR_MAIN_CHECK: begin // Continue with transaction?\n\t\tif (rOffLast[0] | !rWordsEQ0)\n\t\t\t_rMainState = `S_TXPORTWR_MAIN_SIG_NEW;\n\t\telse\n\t\t\t_rMainState = `S_TXPORTWR_MAIN_RESET;\n\tend\n\n\t`S_TXPORTWR_MAIN_SIG_NEW: begin // Signal new write\n\t\t_rMainState = `S_TXPORTWR_MAIN_NEW_ACK;\n\tend\n\n\t`S_TXPORTWR_MAIN_NEW_ACK: begin // Wait for acknowledgement\n\t\tif (rTxnAck) // ACK'd on PC read of TXN length\n\t\t\t_rMainState = (rWordsEQ0 ? `S_TXPORTWR_MAIN_SIG_DONE : `S_TXPORTWR_MAIN_WRITE);\n\tend\n\n\t`S_TXPORTWR_MAIN_WRITE: begin // Start writing and wait for all writes to complete\n\t\t_rStarted = (rStarted | rTxState[1]); // S_TXPORTWR_TX_BUF\n\t\t_rTxErrd = (rTxErrd | rSgErr);\n\t\tif (rTxState[0] & rStarted) // S_TXPORTWR_TX_IDLE\n\t\t\t_rMainState = `S_TXPORTWR_MAIN_DONE;\n\tend\n\n\t`S_TXPORTWR_MAIN_DONE: begin // Wait for the last transaction to complete\n\t\tif (rDone & rLastDoneRead) begin\n\t\t\t_rDoneLen = rSentWords;\n\t\t\t_rMainState = `S_TXPORTWR_MAIN_SIG_DONE;\n\t\tend\n\tend\n\n\t`S_TXPORTWR_MAIN_SIG_DONE: begin // Signal the done port\n\t\t_rTxErrd = 0;\n\t\t_rMainState = `S_TXPORTWR_MAIN_RESET;\n\tend\n\n\t`S_TXPORTWR_MAIN_RESET: begin // Wait for the channel tx to drop\n\t\tif (NEW_TXN_DONE)\n\t\t\t_rMainState = `S_TXPORTWR_MAIN_IDLE;\n\tend\n\t\n\tdefault: begin\n\t\t_rMainState = `S_TXPORTWR_MAIN_IDLE;\n\tend\n\t\n\tendcase\nend\n\n\n// Manage sending TX requests to the TX engine. Transfers will be limited\n// by each scatter gather buffer's size, max payload size, and must not\n// cross a (4KB) page boundary. The request is only made if there is sufficient\n// data already written to the buffer.\nwire [9:0] wLastLen = (NEW_TXN_WORDS_RECVD - rSentWords);\nwire [9:0] wAddrLoInv = ~rAddr[11:2];\nwire [10:0] wPageRem = (wAddrLoInv + 1'd1);\t\nalways @ (posedge CLK) begin\n\trTxState <= #1 (RST | rSgErr ? `S_TXPORTWR_TX_IDLE : _rTxState);\n\trSentWords <= #1 (rMainState[0] ? 0 : _rSentWords);\n\trWords <= #1 _rWords;\n\trBufWords <= #1 _rBufWords;\n\trBufWordsInit <= #1 _rBufWordsInit;\n\trAddr <= #1 _rAddr;\n\trCarry <= #1 _rCarry;\n\trValsPropagated <= #1 _rValsPropagated;\n\trValsProp <= #1 _rValsProp;\n\trLargeBuf <= #1 _rLargeBuf;\n\trPageRem <= #1 _rPageRem;\n\trPageSpill <= #1 _rPageSpill;\n\trPageSpillInit <= #1 _rPageSpillInit;\n\trCopyBufWords <= #1 _rCopyBufWords;\n\trUseInit <= #1 _rUseInit;\n\trPreLen <= #1 _rPreLen;\n\trMaxPayloadSize <= #1 _rMaxPayloadSize;\n\trMaxPayloadShift <= #1 _rMaxPayloadShift;\n\trMaxPayload <= #1 _rMaxPayload;\n\trPayloadSpill <= #1 _rPayloadSpill;\n\trMaxLen <= #1 (RST ? 1'd1 : _rMaxLen);\n\trLen <= #1 _rLen;\n\trSendingWords <= #1 _rSendingWords;\n\trAvail <= #1 _rAvail;\n\trTxnDone <= #1 _rTxnDone;\n\trLastLen <= #1 _rLastLen;\n\trLastLenEQ0 <= #1 _rLastLenEQ0;\n\trLenEQWords <= #1 _rLenEQWords;\n\trLenEQBufWords <= #1 _rLenEQBufWords;\nend\n\nalways @ (*) begin\n\t_rTxState = rTxState;\n\t_rCopyBufWords = rCopyBufWords;\n\t_rUseInit = rUseInit;\n\t\n\t_rValsProp = ((rValsProp<<1) | rTxState[3]); // S_TXPORTWR_TX_ADJ_1\n\t_rValsPropagated = (rValsProp == 6'd0);\n\t_rLargeBuf = (SG_ELEM_LEN > rWords);\n\t{_rCarry[0], _rAddr[15:0]} = (rTxState[1] ? SG_ELEM_ADDR[15:0] : (rAddr[15:0] + ({12{rTxState[6]}} & {rLen, 2'd0}))); // S_TXPORTWR_TX_WRITE\n\t{_rCarry[1], _rAddr[31:16]} = (rTxState[1] ? SG_ELEM_ADDR[31:16] : (rAddr[31:16] + rCarry[0]));\n\t{_rCarry[2], _rAddr[47:32]} = (rTxState[1] ? SG_ELEM_ADDR[47:32] : (rAddr[47:32] + rCarry[1]));\n\t\t\t\t _rAddr[63:48] = (rTxState[1] ? SG_ELEM_ADDR[63:48] : (rAddr[63:48] + rCarry[2]));\n\t_rSentWords = (rTxState[7] ? NEW_TXN_WORDS_RECVD : rSentWords) + ({10{rTxState[6]}} & rLen); // S_TXPORTWR_TX_WRITE\n\t_rWords = (NEW_TXN_ACK ? NEW_TXN_LEN : (rWords - ({10{rTxState[6]}} & rLen))); // S_TXPORTWR_TX_WRITE\n\t_rBufWordsInit = (rLargeBuf ? rWords : SG_ELEM_LEN); \n\t_rBufWords = (rCopyBufWords ? rBufWordsInit : rBufWords) - ({10{rTxState[6]}} & rLen); // S_TXPORTWR_TX_WRITE\n\t_rPageRem = wPageRem;\t\n\t_rPageSpillInit = (rBufWordsInit > wPageRem);\t\n\t_rPageSpill = (rBufWords > wPageRem);\t\n\t_rPreLen = ((rPageSpillInit & rUseInit) | (rPageSpill & !rUseInit) ? rPageRem : rBufWords[10:0]);\n\t_rMaxPayloadSize = CONFIG_MAX_PAYLOAD_SIZE;\n\t_rMaxPayloadShift = (rMaxPayloadSize > 3'd4 ? 3'd4 : rMaxPayloadSize);\n\t_rMaxPayload = (6'd32< rMaxPayload);\n\t_rMaxLen = ((rMaxLen & !rValsProp[1]) | rTxState[6]); // S_TXPORTWR_TX_WRITE\n\t_rLen = (rPayloadSpill | rMaxLen ? rMaxPayload : rPreLen[9:0]);\n\t_rSendingWords = rSentWords + rLen;\n\t_rAvail = (NEW_TXN_WORDS_RECVD >= rSendingWords);\n\t_rTxnDone = ((rTxnDone<<1) | NEW_TXN_DONE);\n\t_rLastLen = wLastLen;\n\t_rLastLenEQ0 = (rLastLen == 10'd0);\n\t_rLenEQWords = (rLen == rWords);\n\t_rLenEQBufWords = (rLen == rBufWords);\n\t\n\tcase (rTxState)\n\n\t`S_TXPORTWR_TX_IDLE: begin // Wait for channel write request\n\t\tif (rMainState[4] & !rStarted) // S_TXPORTWR_MAIN_WRITE\n\t\t\t_rTxState = `S_TXPORTWR_TX_BUF;\n\tend\n\n\t`S_TXPORTWR_TX_BUF: begin // Wait for buffer length and address\n\t\tif (SG_ELEM_RDY)\n\t\t\t_rTxState = `S_TXPORTWR_TX_ADJ_0;\n\tend\n\n\t`S_TXPORTWR_TX_ADJ_0: begin // Fix for large buffer\n\t\t_rCopyBufWords = 1;\n\t\t_rTxState = `S_TXPORTWR_TX_ADJ_1;\n\tend\n\n\t`S_TXPORTWR_TX_ADJ_1: begin // Check for page boundary crossing\n\t\t_rCopyBufWords = 0;\n\t\t_rUseInit = rCopyBufWords;\n\t\t_rTxState = `S_TXPORTWR_TX_ADJ_2;\n\tend\n\n\t`S_TXPORTWR_TX_ADJ_2: begin // Wait for values to propagate\n\t\t// Fix for page boundary crossing\n\t\t// Check for max payload\n\t\t// Fix for max payload\n\t\t_rUseInit = 0;\n\t\tif (rValsProp[2])\n\t\t\t_rTxState = `S_TXPORTWR_TX_CHECK_DATA;\n\tend\n\n\t`S_TXPORTWR_TX_CHECK_DATA: begin // Wait for available data\n\t\tif (rNotRequesting) begin\n\t\t\tif (rAvail)\n\t\t\t\t_rTxState = `S_TXPORTWR_TX_WRITE;\n\t\t\telse if (rValsPropagated & rTxnDone[1])\n\t\t\t\t_rTxState = (rLastLenEQ0 ? `S_TXPORTWR_TX_IDLE : `S_TXPORTWR_TX_WRITE_REM);\n\t\tend\n\tend\n\n\t`S_TXPORTWR_TX_WRITE: begin // Send len and repeat or finish?\n\t\tif (rLenEQWords)\n\t\t\t_rTxState = `S_TXPORTWR_TX_IDLE;\n\t\telse if (rLenEQBufWords)\n\t\t\t_rTxState = `S_TXPORTWR_TX_BUF;\n\t\telse\n\t\t\t_rTxState = `S_TXPORTWR_TX_ADJ_1;\n\tend\n\n\t`S_TXPORTWR_TX_WRITE_REM: begin // Send remaining data and finish\n\t\t_rTxState = `S_TXPORTWR_TX_IDLE;\n\tend\n\t\n\tdefault: begin\n\t\t_rTxState = `S_TXPORTWR_TX_IDLE;\n\tend\n\t\n\tendcase\nend\n\n// Request TX transfers separately so that the TX FSM can continue calculating\n// the next set of request parameters without having to wait for the TX_REQ_ACK.\nalways @ (posedge CLK) begin\n\trAckCount <= #1 (RST ? 10'd0 : _rAckCount);\n\trNotRequesting <= #1 (RST ? 1'd1 : _rNotRequesting);\n\trReqAddr <= #1 _rReqAddr;\n\trReqLen <= #1 _rReqLen;\n\trReqLast <= #1 _rReqLast;\n\trDone <= #1 _rDone;\n\trLastDoneRead <= #1 (RST ? 1'd1 : _rLastDoneRead);\nend\n\nalways @ (*) begin\n\t// Start signaling when the TX FSM is ready.\n\tif (rTxState[6] | rTxState[7]) // S_TXPORTWR_TX_WRITE\n\t\t_rNotRequesting = 0;\n\telse\n\t\t_rNotRequesting = (rNotRequesting | rTxReqAck);\n\n\t// Pass off the rAddr & rLen when ready and wait for TX_REQ_ACK.\n\tif (rTxState[6]) begin // S_TXPORTWR_TX_WRITE\n\t\t_rReqAddr = rAddr;\n\t\t_rReqLen = rLen;\n\t\t_rReqLast = rLenEQWords;\n\tend\n\telse if (rTxState[7]) begin // S_TXPORTWR_TX_WRITE_REM\n\t\t_rReqAddr = rAddr;\n\t\t_rReqLen = rLastLen;\n\t\t_rReqLast = 1;\n\tend\n\telse begin\n\t\t_rReqAddr = rReqAddr;\n\t\t_rReqLen = rReqLen;\n\t\t_rReqLast = rReqLast;\n\tend\n\n\t// Track TX_REQ_ACK and TX_SENT to determine when the transaction is over.\n\t_rDone = (rAckCount == 10'd0);\n\tif (rMainState[0]) // S_TXPORTWR_MAIN_IDLE\n\t\t_rAckCount = 0;\n\telse\n\t\t_rAckCount = rAckCount + rTxState[6] + rTxState[7] - rTxSent; // S_TXPORTWR_TX_WRITE, S_TXPORTWR_TX_WRITE_REM\n\t\t\n\t// Track when the user reads the actual transfer amount.\n\t_rLastDoneRead = (rMainState[6] ? 1'd0 : (rLastDoneRead | rTxnDoneAck)); // S_TXPORTWR_MAIN_SIG_DONE\nend\n\n\n// Facilitate sending a TXN_DONE when we receive a TXN_ACK after the transaction\n// has begun sending. This will happen when the workstation detects that it has \n// sent/used all its currently mapped scatter gather elements, but it's not enough \n// to complete the transaction. The TXN_DONE will let the workstation know it can\n// release the current scatter gather mappings and allocate new ones.\nalways @ (posedge CLK) begin\n\trPartialDone <= #1 _rPartialDone;\n\trReqPartialDone <= #1 (RST ? 1'd0 : _rReqPartialDone);\nend\n\nalways @ (*) begin\n\t// Signal TXN_DONE after we've recieved the (seemingly superfluous) TXN_ACK, \n\t// we have no outstanding transfer requests, we're not currently requesting a\n\t// transfer, and there are no more scatter gather elements.\n\t_rPartialDone = (rReqPartialDone & rDone & rNotRequesting & SG_ELEM_EMPTY & rTxState[1]); // S_TXPORTWR_TX_BUF\n\t\n\t// Keep track of (seemingly superfluous) TXN_ACK requests.\n\tif ((rReqPartialDone & rDone & rNotRequesting & SG_ELEM_EMPTY & rTxState[1]) | rMainState[0]) // S_TXPORTWR_MAIN_IDLE\n\t\t_rReqPartialDone = 0;\n\telse\n\t\t_rReqPartialDone = (rReqPartialDone | (rTxnAck & !rMainState[3])); // !S_TXPORTWR_MAIN_NEW_ACK\nend\n\n\n\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_qword_aligner_128.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 19:27:32 05/15/2014 \n// Design Name: \n// Module Name: tx_qword_aligner_128\n// Project Name: \n// Target Devices: \n// Tool versions: \n// Description:\n// Shifts the data payload of outgoing TLP's to conform to Altera's Quad-word\n// alignment requirement. This module has a 2 cycle latency. It also handles the\n// 2 cycle Transmit ready latency from the specification.\n//\n// Dependencies: None\n//\n// Revision: \n// Revision 0.01 - File Created\n// Additional Comments: \n//\n//////////////////////////////////////////////////////////////////////////////////\n`define S_TXALIGNER128UP_IDLE 2'b00\n`define S_TXALIGNER128UP_HDR0 2'b01\n`define S_TXALIGNER128UP_PAY 2'b10\n\n`define S_TXALIGNER128LOW_IDLE 2'b00\n`define S_TXALIGNER128LOW_PROC 2'b01\n`define S_TXALIGNER128LOW_PREOVFL 2'b10\n`define S_TXALIGNER128LOW_OVFL 2'b11\n\nmodule tx_qword_aligner_128\n #(\n parameter C_ALTERA = 1'b1,\n parameter C_PCI_DATA_WIDTH = 9'd128,\n parameter C_TX_READY_LATENCY = 3'd2\n )\n (\n input CLK,\n input RST_IN,\n\n input [C_PCI_DATA_WIDTH-1:0] TX_DATA,\n input TX_DATA_VALID,\n output TX_DATA_READY,\n input TX_TLP_END_FLAG,\n input TX_TLP_START_FLAG,\n\n output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA, \n output [0:0] TX_ST_VALID,\n input TX_ST_READY,\n output [0:0] TX_ST_EOP,\n output [0:0] TX_ST_SOP,\n output TX_ST_EMPTY\n );\n\n reg [C_TX_READY_LATENCY-1:0] rTxStReady=0, _rTxStReady=0;\n\n // Registers for first cycle of pipeline (upper)\n // Capture\n reg [C_PCI_DATA_WIDTH-1:0] rTxData=0,_rTxData=0;\n reg rTxDataValid=0, _rTxDataValid=0;\n reg rTxTlpEndFlag=0, _rTxTlpEndFlag=0;\n reg rTxTlpStartFlag=0, _rTxTlpStartFlag=0;\n // Computed\n reg [1:0] rOverflow=0, _rOverflow=0;\n reg [9:0] rRealLength=0, _rRealLength=0;\n reg [9:0] rAdjLength=0, _rAdjLength=0;\n reg rInsBlank=0,_rInsBlank=0; \n\n // State (controls pipeline)\n reg [1:0] rUpState=0, _rUpState=0;\n\n // Second cycle of pipeline (lower)\n reg [C_PCI_DATA_WIDTH+32-1:0] rAlignBuffer=0, _rAlignBuffer=0;\n reg [1:0] rLowState=0, _rLowState=0;\n reg rSel=0, _rSel=0;\n reg rTrigger=0,_rTrigger=0;\n\n // Registered outputs\n reg rTxStValid=0,_rTxStValid=0;\n reg rTxStEop=0,_rTxStEop=0;\n reg rTxStSop=0,_rTxStSop=0;\n reg rTxStEmpty=0,_rTxStEmpty=0;\n\n wire [1:0] wRegEn; \n\n // Wires (unregistered) from input\n wire [2:0] wFMT;\n wire [63:0] w4DWHAddr;\n wire [31:0] w3DWHAddr;\n wire w3DWH;\n wire w4DWH;\n wire wInsBlank;\n wire w4DWHQWA;\n wire w3DWHQWA;\n wire [9:0] wLength;\n wire wDataTLP;\n wire w3DWHInsBlank;\n wire w4DWHInsBlank;\n // Overflow indicating wire to the second stage of the pipeline\n wire wOverflow;\n\n wire wSMLowEnable;\n wire wSMUpEnable; \n wire wTxStEopCondition;\n\n wire [255:0] wAlignBufMux; \n\n // Wires from the unregistered TLP Header\n assign wFMT = TX_DATA[31:29];\n assign w4DWHAddr = {TX_DATA[95:64],TX_DATA[127:96]};\n assign w3DWHAddr = TX_DATA[95:64];\n assign wLength = TX_DATA[9:0];\n assign w4DWH = wFMT[0];\n assign w3DWH = ~wFMT[0];\n assign wDataTLP = wFMT[1];\n assign w4DWHQWA = ~w4DWHAddr[2];\n assign w3DWHQWA = ~w3DWHAddr[2];\n assign w3DWHInsBlank = w3DWHQWA & w3DWH & wDataTLP;\n assign w4DWHInsBlank = ~w4DWHQWA & w4DWH & wDataTLP;\n assign wInsBlank = w3DWHInsBlank | w4DWHInsBlank; // Insert a blank DW after the header\n\n assign wRegEn[0] = (~rTxDataValid | wRegEn[1]);\n assign wSMUpEnable = wRegEn[0];\n assign TX_DATA_READY = wRegEn[0];\n\n // Unconditional input capture\n always @(*) begin \n _rTxStReady = (rTxStReady << 1) | TX_ST_READY;\n end\n\n always @(posedge CLK) begin\n rTxStReady <= _rTxStReady;\n end\n\n // All of these signals are \"valid\" when rTxTlpStartFlag and rTxDataValid is high\n always @(*) begin \n _rInsBlank = wInsBlank & TX_TLP_START_FLAG & TX_DATA_VALID;\n _rRealLength = wLength + {7'd0,{w4DWH,~w4DWH,~w4DWH}};\n _rAdjLength = wLength + {9'd0,wInsBlank} + {7'd0,{w4DWH,~w4DWH,~w4DWH}};\n\n _rTxData = TX_DATA;\n _rTxTlpEndFlag = TX_TLP_END_FLAG & TX_DATA_VALID;\n _rTxTlpStartFlag = TX_TLP_START_FLAG & TX_DATA_VALID;\n end // always @ begin\n\n always @(posedge CLK) begin\n rInsBlank <= _rInsBlank;\n rRealLength <= _rRealLength;\n rAdjLength <= _rAdjLength;\n \n if(wRegEn[0]) begin\n rTxData <= _rTxData;\n rTxTlpEndFlag <= _rTxTlpEndFlag;\n rTxTlpStartFlag <= _rTxTlpStartFlag;\n end\n end\n \n always @(*) begin\n _rOverflow[0] = TX_TLP_START_FLAG & TX_TLP_END_FLAG & w3DWHInsBlank;\n _rOverflow[1] = rTxTlpStartFlag & (rRealLength[9:2] < rAdjLength[9:2]); \n end // always @ begin\n\n always @(posedge CLK) begin\n if(wSMUpEnable) begin\n\t rOverflow[0] <= _rOverflow[0];\n\t rOverflow[1] <= _rOverflow[1];\n end\n end\n\n // State machine for the upper pipeline\n // Valid never goes down inside of a TLP.\n always @(*) begin\n _rTxDataValid = rTxDataValid;\n\n if(wSMUpEnable & TX_DATA_VALID) begin\n _rTxDataValid = 1'b1;\n end else if ( wSMUpEnable & rTxTlpEndFlag)begin\n _rTxDataValid = 1'b0;\n end\n\n _rUpState = rUpState;\n case (rUpState)\n `S_TXALIGNER128UP_IDLE: begin\n if (TX_DATA_VALID & wRegEn[0]) begin\n _rUpState = `S_TXALIGNER128UP_HDR0;\n end\n end\n `S_TXALIGNER128UP_HDR0: begin\n if(wSMUpEnable) begin\n casex ({rTxTlpEndFlag,TX_DATA_VALID})\n 2'b0x: _rUpState = `S_TXALIGNER128UP_PAY;\n 2'b10: _rUpState = `S_TXALIGNER128UP_IDLE;\n 2'b11: _rUpState = `S_TXALIGNER128UP_HDR0;\n endcase // case (rTxTlpEndFlag)\n end\n end\n `S_TXALIGNER128UP_PAY : begin\n if(wSMUpEnable) begin\n casex ({rTxTlpEndFlag,TX_DATA_VALID})\n 2'b0x: _rUpState = `S_TXALIGNER128UP_PAY;\n 2'b10: _rUpState = `S_TXALIGNER128UP_IDLE;\n 2'b11: _rUpState = `S_TXALIGNER128UP_HDR0;\n endcase // case (rTxTlpEndFlag)\n end\n end\n default: _rUpState = `S_TXALIGNER128UP_IDLE;\n endcase // case (rUpState)\n end // always @ begin\n\n always @(posedge CLK) begin\n if(RST_IN) begin\n rTxDataValid <= 0;\n rUpState <= `S_TXALIGNER128UP_IDLE;\n end else begin\n rTxDataValid <= _rTxDataValid;\n rUpState <= _rUpState;\n end\n end // always @ (posedge CLK)\n\n // These signals comprise the lower aligner\n assign wSMLowEnable = rTxStReady[C_TX_READY_LATENCY-1] | ~rTxStValid;\n assign wRegEn[1] = ~(rLowState == `S_TXALIGNER128LOW_PREOVFL & rTrigger) & (wSMLowEnable); \n\n assign wOverflow = (rOverflow[0] | rOverflow[1]);\n assign wAlignBufMux = ({{rTxData[95:0],rAlignBuffer[159:128]},rTxData}) >> ({rSel,7'd0});\n\n always @(*) begin\n _rAlignBuffer = {rTxData[127:96], wAlignBufMux[127:0]};\n end // always @ begin\n\n always @(posedge CLK) begin\n if(wSMLowEnable) begin\n rAlignBuffer <= _rAlignBuffer; \n end\n end\n\n assign wTxStEopCondition = (rLowState == `S_TXALIGNER128LOW_PREOVFL & rTrigger) | \n (rLowState != `S_TXALIGNER128LOW_PREOVFL & {rTxTlpEndFlag,wOverflow,rTxDataValid} == 3'b101);\n\n // Valid never goes down inside of a TLP.\n always @(*) begin\n _rLowState = rLowState;\n _rTrigger = rTrigger;\n _rTxStValid = rTxStValid;\n _rTxStEop = rTxStEop;\n _rTxStSop = rTxStSop;\n _rSel = rSel;\n\n _rTxStEop = wTxStEopCondition;\n _rTrigger = rTxTlpEndFlag & rTxDataValid;\n _rTxStEmpty = (rAdjLength[1:0] == 2'b01) | (rAdjLength[1:0] == 2'b10);\n\n // Take the next txDataValid if we are taking data\n // and it's a start flag and the data is valid\n if ( wRegEn[1] & rTxTlpStartFlag & rTxDataValid ) begin\n _rTxStValid = 1;\n end else if ( wSMLowEnable & rTxStEop ) begin\n _rTxStValid = 0;\n end\n\n if ( wRegEn[1] & rTxDataValid ) begin // DOUBLE CHECK\n _rTxStSop = rTxTlpStartFlag;\n end else if ( wSMLowEnable ) begin\n _rTxStSop = 0;\n end\n\n // rSel should be set on wInsBlank kept high until the end of the packet\n // Note: rSel is only applicable in multi-cycle packets\n if (wSMLowEnable & rInsBlank) begin\n _rSel = 1'b1;\n end else if (wSMLowEnable & wTxStEopCondition) begin\n _rSel = 1'b0;\n end\n \n case (rLowState)\n `S_TXALIGNER128LOW_IDLE : begin\n if(wSMLowEnable) begin\n casex({rTxTlpEndFlag,wOverflow,rTxDataValid}) // Set the state for the next cycle\n 3'bxx0: _rLowState = `S_TXALIGNER128LOW_IDLE; // Stay here\n 3'b001: _rLowState = `S_TXALIGNER128LOW_PROC; // Process\n 3'b011: _rLowState = `S_TXALIGNER128LOW_PREOVFL; // Don't set rTxStEop (set trigger)\n 3'b101: _rLowState = `S_TXALIGNER128LOW_PROC; // Set rTxStEop\n 3'b111: _rLowState = `S_TXALIGNER128LOW_PREOVFL; // Don't set rTxStEop (set trigger)\n endcase\n end\n end\n `S_TXALIGNER128LOW_PROC : begin\n if(wSMLowEnable) begin\n casex({rTxTlpEndFlag,wOverflow,rTxDataValid}) // Set the state for the next cycle\n 3'bxx0: _rLowState = `S_TXALIGNER128LOW_IDLE; // If the next cycle is not valid Eop must have been set this cycle and we should go to idle\n 3'b001: _rLowState = `S_TXALIGNER128LOW_PROC; // Continue processing\n 3'b011: _rLowState = `S_TXALIGNER128LOW_PREOVFL; // Don't set rTxStEop (set trigger)\n 3'b101: _rLowState = `S_TXALIGNER128LOW_PROC; // set rTxStEop \n 3'b111: _rLowState = `S_TXALIGNER128LOW_PREOVFL; // Don't set rTxStEop (set trigger)\n endcase\n end\n end\n `S_TXALIGNER128LOW_PREOVFL : begin\n if(wSMLowEnable) begin\n if(rTrigger) begin\n _rLowState = `S_TXALIGNER128LOW_OVFL;\n end\n end\n end\n `S_TXALIGNER128LOW_OVFL : begin\n if(wSMLowEnable) begin\n casex({rTxTlpEndFlag,wOverflow,rTxDataValid}) // Set the state for the next cycle\n 3'bxx0: _rLowState = `S_TXALIGNER128LOW_IDLE; // If the next cycle is not valid Eop must have been set this cycle and we should go to idle\n 3'b001: _rLowState = `S_TXALIGNER128LOW_PROC; // Continue processing\n 3'b011: _rLowState = `S_TXALIGNER128LOW_PREOVFL; // Don't set rTxStEop (Don't set trigger)\n 3'b101: _rLowState = `S_TXALIGNER128LOW_PROC; // set rTxStEop\n 3'b111: _rLowState = `S_TXALIGNER128LOW_PREOVFL; // Don't set rTxStEop (set trigger)\n endcase\n end\n end\n endcase\n end // always @ begin\n \n always @(posedge CLK) begin\n if(RST_IN) begin\n rLowState <= `S_TXALIGNER128LOW_IDLE;\n rTxStValid <= 0;\n rTxStSop <= 0;\n rSel <= 0;\n end else begin\n rTxStValid <= _rTxStValid;\n rTxStSop <= _rTxStSop;\n rSel <= _rSel;\n rLowState <= _rLowState;\n end // else: !if(RST_IN)\n if (RST_IN) begin\n rTxStEop <= 1'b0;\n end else if (wSMLowEnable) begin\n rTxStEop <= _rTxStEop;\n end\n if (RST_IN) begin\n rTrigger <= 1'b0;\n end else if (wRegEn[1]) begin\n rTrigger <= _rTrigger;\n end\n if (RST_IN) begin\n rTxStEmpty <= 1'b0;\n end else if(wRegEn[1] & rTxTlpStartFlag) begin\n rTxStEmpty <= _rTxStEmpty;\n end\n end // always @ (posedge CLK)\n\n // Outputs from the aligner to the PCIe Core\n assign TX_ST_VALID = (rTxStValid & rTxStReady[C_TX_READY_LATENCY-1]);\n assign TX_ST_EOP = rTxStEop;\n assign TX_ST_SOP = rTxStSop;\n assign TX_ST_EMPTY = rTxStEmpty;\n assign TX_ST_DATA = rAlignBuffer[127:0];\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/riffa/tx_qword_aligner_64.v", "content": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Copyright © 2012 The Regents of the University of \n// California. All Rights Reserved.\n//\n// Permission to copy, modify, and distribute this software and its \n// documentation for educational, research and non-profit purposes, without \n// fee, and without a written agreement is hereby granted, provided that the \n// above copyright notice, this paragraph and the following three paragraphs \n// appear in all copies.\n//\n// Permission to make commercial use of this software may be obtained by \n// contacting:\n// Technology Transfer Office\n// 9500 Gilman Drive, Mail Code 0910\n// University of California\n// La Jolla, CA 92093-0910\n// (858) 534-5815\n// invent@ucsd.edu\n// \n// This software program and documentation are copyrighted by The Regents of \n// the University of California. The software program and documentation are \n// supplied \"as is\", without any accompanying services from The Regents. The \n// Regents does not warrant that the operation of the program will be \n// uninterrupted or error-free. The end-user understands that the program was \n// developed for research purposes and is advised not to rely exclusively on \n// the program for any reason.\n// \n// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n// THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n// MODIFICATIONS.\n//----------------------------------------------------------------------------\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 19:27:32 06/14/2012 \n// Design Name: \n// Module Name: tx_qword_aligner_64 \n// Project Name: \n// Target Devices: \n// Tool versions: \n// Description:\n// Shifts the data payload of outgoing TLP's to conform to Altera's Quad-word\n// alignment requirement. This module has a 2 cycle latency. It also handles the\n// 2 cycle Transmit ready latency from the specification.\n//\n// Dependencies: None\n//\n// Revision: \n// Revision 0.01 - File Created\n// Additional Comments: \n//\n//////////////////////////////////////////////////////////////////////////////////\n`define S_TXALIGNER64UP_IDLE 2'b00\n`define S_TXALIGNER64UP_HDR0 2'b01\n`define S_TXALIGNER64UP_HDR1 2'b10\n`define S_TXALIGNER64UP_PAY 2'b11\n\n`define S_TXALIGNER64LOW_IDLE 2'b00\n`define S_TXALIGNER64LOW_PROC 2'b01\n`define S_TXALIGNER64LOW_PREOVFL 2'b10\n`define S_TXALIGNER64LOW_OVFL 2'b11\n\nmodule tx_qword_aligner_64\n #(\n parameter C_ALTERA = 1'b1,\n parameter C_PCI_DATA_WIDTH = 9'd64,\n parameter C_TX_READY_LATENCY = 3'd1\n )\n (\n input CLK,\n input RST_IN,\n\n input [C_PCI_DATA_WIDTH-1:0] TX_DATA,\n input TX_DATA_VALID,\n output TX_DATA_READY,\n input TX_TLP_END_FLAG,\n input TX_TLP_START_FLAG,\n\n output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA, \n output [0:0] TX_ST_VALID,\n input TX_ST_READY,\n output [0:0] TX_ST_EOP,\n output [0:0] TX_ST_SOP,\n output TX_ST_EMPTY\n );\n\n reg [C_TX_READY_LATENCY-1:0] rTxStReady, _rTxStReady;\n\n // Registers for first cycle of pipeline (upper)\n // Capture\n reg [C_PCI_DATA_WIDTH-1:0] rTxData,_rTxData;\n reg rTxDataValid, _rTxDataValid;\n reg rTxTlpEndFlag, _rTxTlpEndFlag;\n reg rTxTlpStartFlag, _rTxTlpStartFlag;\n\n // Registers for the second cycle of the state machine\n reg r3DWHInsBlank,_r3DWHInsBlank;\n reg [C_PCI_DATA_WIDTH+32-1:0] rAlignBuffer, _rAlignBuffer;\n\n // Registers for the third cycle of the state machine\n reg r4DWHInsBlank,_r4DWHInsBlank;\n\n // State (controls upper pipeline)\n reg [1:0] rUpState, _rUpState;\n reg rSel, _rSel;\n reg rTrigger,_rTrigger;\n \n // Second stage of pipeline (lower)\n reg [1:0] rLowState, _rLowState;\n\n // Registered Outputs\n reg rTxStValid,_rTxStValid;\n reg rTxStEop,_rTxStEop;\n reg rTxStSop,_rTxStSop;\n \n // Wires\n wire [1:0] wRegEn;\n\n reg r4DWH, _r4DWH;\n reg r3DWH, _r3DWH;\n reg rDataTLP, _rDataTLP;\n reg rLenEven,_rLenEven;\n reg rLenOdd,_rLenOdd;\n reg r4DWHQWA, _r4DWHQWA;\n reg r3DWHQWA, _r3DWHQWA;\n\n wire [127:0] wAlignBufMux;\n \n wire w3DWHInsBlank;\n wire w4DWHInsBlank;\n wire wOverflow;\n wire wSMLowEnable;\n wire wSMUpEnable;\n wire wTxStEopCondition;\n \n // Unconditional input capture\n always @(*) begin \n _rTxStReady = (rTxStReady << 1) | TX_ST_READY;\n end\n\n always @(posedge CLK) begin\n rTxStReady <= _rTxStReady;\n end\n\n // Take data when: \n assign wRegEn[0] = (~rTxDataValid | wRegEn[1]);\n assign wSMUpEnable = wRegEn[0];\n assign TX_DATA_READY = wRegEn[0];\n\n always @(*) begin \n _rTxData = TX_DATA;\n _rTxTlpEndFlag = TX_TLP_END_FLAG & TX_DATA_VALID;\n _rTxTlpStartFlag = TX_TLP_START_FLAG & TX_DATA_VALID;\n end // always @ begin\n\n always @(posedge CLK) begin\n if(wRegEn[0]) begin\n rTxData <= _rTxData;\n rTxTlpEndFlag <= _rTxTlpEndFlag;\n rTxTlpStartFlag <= _rTxTlpStartFlag;\n end\n end\n \n always @(*) begin\n _r4DWH = rTxData[29] & rTxTlpStartFlag;\n _r3DWH = ~rTxData[29] & rTxTlpStartFlag;\n _rDataTLP = rTxData[30] & rTxTlpStartFlag;\n _rLenEven = ~rTxData[0] & rTxTlpStartFlag;\n _rLenOdd = rTxData[0] & rTxTlpStartFlag;\n\n _r4DWHQWA = ~TX_DATA[34] & rTxTlpStartFlag;\n _r3DWHQWA = ~TX_DATA[2] & rTxTlpStartFlag;\n end // always @ begin\n\n always @(posedge CLK) begin\n if(wRegEn[0]) begin\n r4DWH <= _r4DWH;\n r3DWH <= _r3DWH;\n rDataTLP <= _rDataTLP;\n rLenEven <= _rLenEven;\n rLenOdd <= _rLenOdd;\n r4DWHQWA <= _r4DWHQWA;\n r3DWHQWA <= _r3DWHQWA;\n end\n end\n \n // State machine for the upper pipeline\n // Valid never goes down inside of a TLP.\n always @(*) begin\n _rTxDataValid = rTxDataValid;\n\n if(wSMUpEnable & TX_DATA_VALID) begin // & TX_TLP_START_FLAG\n _rTxDataValid = 1'b1;\n end else if ( wSMUpEnable & rTxTlpEndFlag)begin\n _rTxDataValid = 1'b0;\n end\n _rUpState = rUpState;\n case (rUpState)\n `S_TXALIGNER64UP_IDLE: begin\n if (TX_DATA_VALID & wSMUpEnable) begin\n _rUpState = `S_TXALIGNER64UP_HDR0;\n end\n end\n `S_TXALIGNER64UP_HDR0: begin\n if(wSMUpEnable) begin\n _rUpState = `S_TXALIGNER64UP_HDR1;\n end\n end\n `S_TXALIGNER64UP_HDR1: begin\n if(wSMUpEnable) begin\n casex ({rTxTlpEndFlag,TX_DATA_VALID})\n 2'b0x: _rUpState = `S_TXALIGNER64UP_PAY;\n 2'b10: _rUpState = `S_TXALIGNER64UP_IDLE; // No new TLP\n 2'b11: _rUpState = `S_TXALIGNER64UP_HDR0;\n endcase // case (rTxTlpEndFlag)\n end\n end\n `S_TXALIGNER64UP_PAY : begin\n if(wSMUpEnable) begin\n casex ({rTxTlpEndFlag,TX_DATA_VALID})\n 2'b0x: _rUpState = `S_TXALIGNER64UP_PAY;\n 2'b10: _rUpState = `S_TXALIGNER64UP_IDLE; // No new TLP\n 2'b11: _rUpState = `S_TXALIGNER64UP_HDR0;\n endcase // case (rTxTlpEndFlag)\n end\n end\n endcase // case (rUpState)\n end // always @ begin\n\n always @(posedge CLK) begin\n rTxDataValid <= _rTxDataValid;\n if(RST_IN) begin\n rUpState <= `S_TXALIGNER64UP_IDLE;\n end else begin\n rUpState <= _rUpState;\n end\n end // always @ (posedge CLK)\n\n assign wSMLowEnable = rTxStReady[C_TX_READY_LATENCY-1] | ~rTxStValid;\n assign wRegEn[1] = ~(rLowState == `S_TXALIGNER64LOW_PREOVFL & rTrigger) & (wSMLowEnable); \n\n assign w3DWHInsBlank = rDataTLP & r3DWH & r3DWHQWA;\n assign w4DWHInsBlank = rDataTLP & r4DWH & ~r4DWHQWA;\n assign wOverflow = (w4DWHInsBlank & rLenEven) | (w3DWHInsBlank & rLenOdd);\n assign wAlignBufMux = ({{rTxData[31:0],rAlignBuffer[95:64]},rTxData[63:0]}) >> ({rSel,6'd0});\n\n always @(*) begin\n _rAlignBuffer = {rTxData[63:32], wAlignBufMux[63:0]};\n end // always @ begin\n\n always @(posedge CLK) begin\n if(wSMLowEnable) begin\n rAlignBuffer <= _rAlignBuffer; \n end\n end\n\n assign wTxStEopCondition = (rLowState == `S_TXALIGNER64LOW_PREOVFL & rTrigger) | \n (rLowState != `S_TXALIGNER64LOW_PREOVFL & {rTxTlpEndFlag,wOverflow,rTxDataValid} == 3'b101);\n\n // Valid never goes down inside of a TLP.\n always @(*) begin\n _rLowState = rLowState;\n _rTrigger = rTrigger;\n _rTxStValid = rTxStValid;\n _rTxStEop = rTxStEop;\n _rTxStSop = rTxStSop;\n _rSel = rSel;\n\n _rTxStEop = wTxStEopCondition;\n _rTrigger = rTxDataValid & rTxTlpEndFlag;\n\n // Take the next txDataValid if we are taking data (wRegEn[1])\n // and it's a start flag and the data is valid\n if ( wRegEn[1] & rTxTlpStartFlag & rTxDataValid ) begin\n _rTxStValid = 1;\n end else if ( wSMLowEnable & rTxStEop | RST_IN ) begin\n _rTxStValid = 0;\n end\n\n if ( wRegEn[1] & rTxDataValid ) begin\n _rTxStSop = rTxTlpStartFlag;\n end else if ( wSMLowEnable | RST_IN) begin\n _rTxStSop = 0;\n end\n\n // rSel should be set on wInsBlank kept high until the end of the packet\n // Note: rSel is only applicable in multi-cycle packets\n if (wSMLowEnable & (w3DWHInsBlank | w4DWHInsBlank)) begin\n _rSel = 1'b1;\n end else if (wSMLowEnable & wTxStEopCondition | RST_IN) begin\n _rSel = 1'b0;\n end\n\n case (rLowState)\n `S_TXALIGNER64LOW_IDLE : begin\n if(wSMLowEnable) begin\n casex({rTxTlpEndFlag,wOverflow,rTxDataValid}) // Set the state for the next cycle\n 3'bxx0: _rLowState = `S_TXALIGNER64LOW_IDLE; // Stay here\n 3'b001: _rLowState = `S_TXALIGNER64LOW_PROC; // Process\n 3'b011: _rLowState = `S_TXALIGNER64LOW_PREOVFL; // Don't set rTxStEop (set trigger)\n 3'b101: _rLowState = `S_TXALIGNER64LOW_PROC; // Set rTxStEop\n 3'b111: _rLowState = `S_TXALIGNER64LOW_PREOVFL; // Don't set rTxStEop (set trigger)\n endcase\n end\n end\n `S_TXALIGNER64LOW_PROC : begin\n if(wSMLowEnable) begin\n casex({rTxTlpEndFlag,wOverflow,rTxDataValid}) // Set the state for the next cycle\n 3'bxx0: _rLowState = `S_TXALIGNER64LOW_IDLE; // If the next cycle is not valid Eop must have been set this cycle and we should go to idle\n 3'b001: _rLowState = `S_TXALIGNER64LOW_PROC; // Continue processing\n 3'b011: _rLowState = `S_TXALIGNER64LOW_PREOVFL; // Don't set rTxStEop (set trigger)\n 3'b101: _rLowState = `S_TXALIGNER64LOW_PROC; // set rTxStEop \n 3'b111: _rLowState = `S_TXALIGNER64LOW_PREOVFL; // Don't set rTxStEop (set trigger)\n endcase\n end\n end\n `S_TXALIGNER64LOW_PREOVFL : begin\n if(wSMLowEnable) begin\n if(rTrigger) begin\n _rLowState = `S_TXALIGNER64LOW_OVFL;\n end\n end\n end\n `S_TXALIGNER64LOW_OVFL : begin\n if(wSMLowEnable) begin\n casex({rTxTlpEndFlag,wOverflow,rTxDataValid}) // Set the state for the next cycle\n 3'bxx0: _rLowState = `S_TXALIGNER64LOW_IDLE; // If the next cycle is not valid Eop must have been set this cycle and we should go to idle\n 3'b001: _rLowState = `S_TXALIGNER64LOW_PROC; // Continue processing\n 3'b011: _rLowState = `S_TXALIGNER64LOW_PREOVFL; // Don't set rTxStEop (Don't set trigger)\n 3'b101: _rLowState = `S_TXALIGNER64LOW_PROC; // set rTxStEop\n 3'b111: _rLowState = `S_TXALIGNER64LOW_PREOVFL; // Don't set rTxStEop (set trigger)\n endcase\n end\n end\n endcase\n end // always @ begin\n \n always @(posedge CLK) begin\n if(RST_IN) begin\n rLowState <= `S_TXALIGNER64LOW_IDLE;\n rTxStValid <= 0;\n rTxStSop <= 0;\n rSel <= 0;\n end else begin\n rTxStValid <= _rTxStValid;\n rTxStSop <= _rTxStSop;\n rSel <= _rSel;\n rLowState <= _rLowState;\n end\n if (RST_IN) begin\n rTxStEop <= 1'b0;\n end else if (wSMLowEnable) begin\n rTxStEop <= _rTxStEop;\n end\n if (RST_IN) begin\n rTrigger <= 1'b0;\n end else if (wRegEn[1]) begin\n rTrigger <= _rTrigger;\n end\n end // always @ (posedge CLK)\n\n // Outputs from the aligner to the PCIe Core\n assign TX_ST_VALID = (rTxStValid & rTxStReady[C_TX_READY_LATENCY-1]);\n assign TX_ST_EOP = rTxStEop;\n assign TX_ST_SOP = rTxStSop;\n assign TX_ST_EMPTY = 1'b0;\n assign TX_ST_DATA = rAlignBuffer[63:0];\nendmodule\n" }, { "path": "hw/boards/ML605/ipcore_dir/xilinx_mig/example_design/mig.prj", "content": "\n\n xilinx_mig\n 1\n 0\n OFF\n xc6vlx240t-ff1156/-1\n 3.92\n Differential\n FALSE\n HIGH\n 0\n \n DDR3_SDRAM/SODIMMs/MT4JSF6464HY-1G1\n 2500\n 64\n 1\n 1\n FALSE\n \n 13\n 10\n 3\n \n \n \n Disabled\n 1\n 25\n ROW_BANK_COLUMN\n Normal\n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 6\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n RZQ/4\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 5\n Enabled\n Normal\n Dynamic ODT off\n NATIVE\n \n\n" }, { "path": "hw/boards/ML605/ipcore_dir/xilinx_mig/user_design/mig.prj", "content": "\n\n xilinx_mig\n 1\n 0\n OFF\n xc6vlx240t-ff1156/-1\n 3.92\n Differential\n FALSE\n HIGH\n 0\n \n DDR3_SDRAM/SODIMMs/MT4JSF6464HY-1G1\n 2500\n 64\n 1\n 1\n FALSE\n \n 13\n 10\n 3\n \n \n \n Disabled\n 1\n 25\n ROW_BANK_COLUMN\n Normal\n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 6\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n RZQ/4\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 5\n Enabled\n Normal\n Dynamic ODT off\n NATIVE\n \n\n" }, { "path": "hw/boards/ML605/ipcore_dir/xilinx_mig.xco", "content": "##############################################################\n#\n# Xilinx Core Generator version 14.6\n# Date: Fri Feb 3 17:08:27 2017\n#\n##############################################################\n#\n# This file contains the customisation parameters for a\n# Xilinx CORE Generator IP GUI. It is strongly recommended\n# that you do not manually alter this file as it may cause\n# unexpected and unsupported behavior.\n#\n##############################################################\n#\n# Generated from component: xilinx.com:ip:mig:3.92\n#\n##############################################################\n#\n# BEGIN Project Options\nSET addpads = false\nSET asysymbol = true\nSET busformat = BusFormatAngleBracketNotRipped\nSET createndf = false\nSET designentry = Verilog\nSET device = xc6vlx240t\nSET devicefamily = virtex6\nSET flowvendor = Other\nSET formalverification = false\nSET foundationsym = false\nSET implementationfiletype = Ngc\nSET package = ff1156\nSET removerpms = false\nSET simulationfiles = Behavioral\nSET speedgrade = -1\nSET verilogsim = true\nSET vhdlsim = false\n# END Project Options\n# BEGIN Select\nSELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.92\n# END Select\n# BEGIN Parameters\nCSET component_name=xilinx_mig\nCSET xml_input_file=./xilinx_mig/user_design/mig.prj\n# END Parameters\n# BEGIN Extra information\nMISC pkg_timestamp=2013-06-08T23:00:50Z\n# END Extra information\nGENERATE\n# CRC: 5879c58d\n" }, { "path": "hw/boards/ML605/ipcore_dir/xilinx_mig.xise", "content": "\n\n\n
\n \n \n \n \n \n \n \n \n
\n\n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n \n \n \n\n \n\n \n \n \n \n \n \n \n \n\n\n" }, { "path": "hw/boards/ML605/iseq_dispatcher.v", "content": "`timescale 1ns / 1ps\n\nmodule iseq_dispatcher #(parameter ROW_WIDTH = 15, BANK_WIDTH = 3, CKE_WIDTH = 1, \r\n\t\t\t\t\t\t\t\t\t\tCS_WIDTH = 1, nCS_PER_RANK = 1, DQ_WIDTH = 64) (\r\n\tinput clk,\r\n\tinput rst,\r\n\t\n\tinput periodic_read_lock,\n\t\r\n\tinput process_iseq,\r\n\t\r\n\toutput dispatcher_busy,\r\n\t\r\n\toutput instr0_fifo_rd,\r\n\tinput instr0_fifo_empty,\r\n\tinput[31:0] instr0_fifo_data,\n\t\r\n\toutput instr1_fifo_rd,\r\n\tinput instr1_fifo_empty,\r\n\tinput[31:0] instr1_fifo_data,\r\n\t\r\n\t//DFI Interface\r\n\t// DFI Control/Address\n\tinput \t\t\t\t\t\t\t\t\t\tdfi_ready,\r\n\tinput \t\t\t\t\t\t\t\t\t\tdfi_init_complete,\n\toutput [ROW_WIDTH-1:0] dfi_address0,\n\toutput [ROW_WIDTH-1:0] dfi_address1,\n\toutput [BANK_WIDTH-1:0] dfi_bank0,\n\toutput [BANK_WIDTH-1:0] dfi_bank1,\n\toutput\t\t\t\t\t\t\t\t\t\tdfi_cke0,\n\toutput\t\t\t\t\t\t\t\t\t\tdfi_cke1,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_cas_n0,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_cas_n1,\n\toutput [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n0,\n\toutput [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n1,\r\n\toutput [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt0,\n\toutput [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt1,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_ras_n0,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_ras_n1,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_we_n0,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_we_n1,\n\t// DFI Write\n\toutput dfi_wrdata_en,\n\toutput [4*DQ_WIDTH-1:0] dfi_wrdata,\n\toutput [4*(DQ_WIDTH/8)-1:0] dfi_wrdata_mask,\n\t// DFI Read\n\toutput dfi_rddata_en,\n\toutput\t\t\t\t\t\t\t\t\t\tdfi_rddata_en_even,\n\toutput\t\t\t\t\t\t\t\t\t\tdfi_rddata_en_odd,\r\n\t\r\n\t//Bus Command\r\n\toutput io_config_strobe,\r\n\toutput[1:0] io_config,\n\t\n\t//Misc.\n\toutput pr_rd_ack,\n\t\n\t//auto-refresh\n output aref_set_interval,\n output[27:0] aref_interval, \n output aref_set_trfc,\n output[27:0] aref_trfc\r\n);\r\n\r\n\treg dispatcher_busy_r = 1'b0, dispatcher_busy_ns;\r\n\t\r\n\t//check conditions and start transaction\r\n\talways@*\r\n\t\tdispatcher_busy_ns = ~rst & process_iseq | (dispatcher_busy_r & (~(instr0_fifo_empty & instr1_fifo_empty) \n\t\t\t\t\t\t\t\t\t| instr0_disp_en | instr1_disp_en));\r\n\talways@(posedge clk)\r\n\t\t\tdispatcher_busy_r <= dispatcher_busy_ns;\n\t\r\n\twire instr0_disp_en, instr1_disp_en;\r\n\twire instr0_disp_ack, instr1_disp_ack;\n\twire[31:0] instr0, instr1;\n\t\n\twire instr0_ready, instr1_ready;\n\t\n\tassign instr0_fifo_rd = instr0_ready & dispatcher_busy_r;\n\tassign instr1_fifo_rd = instr1_ready & dispatcher_busy_r;\n\t\n\tpipe_reg #(.WIDTH(32)) i_instr0_reg(\n .clk(clk),\n .rst(rst),\n \n .ready_in(instr0_disp_ack),\n .valid_in(dispatcher_busy_r & !instr0_fifo_empty),\n .data_in(instr0_fifo_data),\n .valid_out(instr0_disp_en),\n .data_out(instr0),\n .ready_out(instr0_ready)\n );\n\t \n\t pipe_reg #(.WIDTH(32)) i_instr1_reg(\n .clk(clk),\n .rst(rst),\n \n .ready_in(instr1_disp_ack),\n .valid_in(dispatcher_busy_r & !instr1_fifo_empty),\n .data_in(instr1_fifo_data),\n .valid_out(instr1_disp_en),\n .data_out(instr1),\n .ready_out(instr1_ready)\n );\r\n\t\r\n\t\r\n\t//Command Dispatcher Instantiation\r\n\tinstr_dispatcher #(.ROW_WIDTH(ROW_WIDTH), .BANK_WIDTH(BANK_WIDTH), .CKE_WIDTH(CKE_WIDTH), \r\n\t\t\t\t\t\t\t\t\t\t.CS_WIDTH(CS_WIDTH), .nCS_PER_RANK(nCS_PER_RANK), .DQ_WIDTH(DQ_WIDTH)) i_instr_dispatcher(\r\n\t.clk(clk),\r\n\t.rst(rst),\r\n\t\n\t.periodic_read_lock(periodic_read_lock),\n\t\r\n\t.en_in0(instr0_disp_en),\r\n\t.en_ack0(instr0_disp_ack),\r\n\t.instr_in0(instr0),\n\t\n\t.en_in1(instr1_disp_en), \r\n\t.en_ack1(instr1_disp_ack),\r\n\t.instr_in1(instr1),\r\n\t\r\n\t//DFI Interface\r\n\t\r\n\t// DFI Control/Address\n\t.dfi_ready(dfi_ready),\n\t.dfi_address0(dfi_address0),\n\t.dfi_address1(dfi_address1),\n\t.dfi_bank0(dfi_bank0),\n\t.dfi_bank1(dfi_bank1),\n\t.dfi_cke0(dfi_cke0),\n\t.dfi_cke1(dfi_cke1),\n\t.dfi_cas_n0(dfi_cas_n0),\n\t.dfi_cas_n1(dfi_cas_n1),\n\t.dfi_cs_n0(dfi_cs_n0),\n\t.dfi_cs_n1(dfi_cs_n1),\r\n\t.dfi_odt0(dfi_odt0),\n\t.dfi_odt1(dfi_odt1),\n\t.dfi_ras_n0(dfi_ras_n0),\n\t.dfi_ras_n1(dfi_ras_n1),\n\t.dfi_we_n0(dfi_we_n0),\n\t.dfi_we_n1(dfi_we_n1),\n\t// DFI Write\n\t.dfi_wrdata_en(dfi_wrdata_en),\n\t.dfi_wrdata(dfi_wrdata),\n\t.dfi_wrdata_mask(dfi_wrdata_mask),\n\t// DFI Read\n\t.dfi_rddata_en(dfi_rddata_en),\n\t.dfi_rddata_en_even(dfi_rddata_en_even),\n\t.dfi_rddata_en_odd(dfi_rddata_en_odd),\r\n\t\r\n\t//Bus Command\r\n\t.io_config_strobe(io_config_strobe),\r\n\t.io_config(io_config),\n\t\n\t//Misc.\n\t.pr_rd_ack(pr_rd_ack),\n\t\n\t//auto-refresh\n\t.aref_set_interval(aref_set_interval),\n\t.aref_interval(aref_interval),\n\t.aref_set_trfc(aref_set_trfc),\n\t.aref_trfc(aref_trfc)\r\n);\r\n\t\r\n\tassign dispatcher_busy = dispatcher_busy_r;\n\t\r\nendmodule" }, { "path": "hw/boards/ML605/maint_ctrl.v", "content": "`timescale 1ps / 1ps\r\n//Hasan\r\n\r\nmodule maint_ctrl_top #(parameter RANK_WIDTH = 1, TCQ = 100, tCK = 2500, nCK_PER_CLK = 2, MAINT_PRESCALER_PERIOD = 200000) (\r\n input clk,\r\n\t input rst,\r\n\t \r\n\t input dfi_init_complete,\r\n\t \r\n\t input periodic_rd_ack,\r\n\t output periodic_rd_req,\r\n\t input zq_ack,\r\n\t output zq_req,\n\t \n\t //Auto-refresh\n\t input autoref_en,\n\t input[27:0] autoref_interval,\n\t input autoref_ack,\n\t output autoref_req\r\n );\r\n\t \r\n\t /*** MAINTENANCE CONTROLLER ***/\r\n\t wire maint_prescaler_tick;\r\n\t maint_ctrl #(.TCQ(TCQ), .tCK(tCK), .nCK_PER_CLK(nCK_PER_CLK), .MAINT_PRESCALER_PERIOD(MAINT_PRESCALER_PERIOD)) i_maint_ctrl(\r\n\t\t.clk(clk),\r\n\t\t.rst(rst),\r\n\t\r\n\t\t.dfi_init_complete(dfi_init_complete),\r\n\t\r\n\t\t.maint_prescaler_tick(maint_prescaler_tick)\r\n\t);\r\n\t \r\n\t \r\n\t /*** PERIODIC READ CONTROLLER ***/\r\n\t periodic_rd_ctrl #(.tCK(tCK), .nCK_PER_CLK(nCK_PER_CLK), .TCQ(TCQ), .MAINT_PRESCALER_PERIOD(MAINT_PRESCALER_PERIOD)) i_prrd_ctrl(\r\n\t\t.clk(clk),\r\n\t\t.rst(rst),\r\n\t\t\r\n\t\t.maint_prescaler_tick(maint_prescaler_tick),\r\n\t\t.dfi_init_complete(dfi_init_complete),\r\n\t\t\r\n\t\t.periodic_rd_ack(periodic_rd_ack),\r\n\t\t.periodic_rd_req(periodic_rd_req)\r\n\t);\r\n\t \r\n\t /*** ZQ CALIBRATION CONTROLLER ***/\r\n\t zq_calib_ctrl #(.TCQ(TCQ), .MAINT_PRESCALER_PERIOD(MAINT_PRESCALER_PERIOD)) i_zq_calib_ctrl(\r\n\t\t.clk(clk),\r\n\t\t.rst(rst),\r\n\t\t\r\n\t\t.maint_prescaler_tick(maint_prescaler_tick),\r\n\t\t.dfi_init_complete(dfi_init_complete),\r\n\t\t\r\n\t\t.zq_ack(zq_ack),\r\n\t\t.zq_request(zq_req)\r\n\t);\n\t\n\tautoref_ctrl #(.TCQ(TCQ)) i_autoref_ctrl (\n\t\t.clk(clk),\n\t\t.rst(rst),\n\t\t\n\t\t.autoref_en(autoref_en),\n\t\t.autoref_interval(autoref_interval),\n\t\t.maint_prescaler_tick(maint_prescaler_tick),\n\t\t.dfi_init_complete(dfi_init_complete),\n\t\t\n\t\t.autoref_ack(autoref_ack),\n\t\t.autoref_req(autoref_req)\n\t);\r\n\r\nendmodule\r\n\r\nmodule maint_ctrl #(parameter TCQ = 100, tCK = 2500, nCK_PER_CLK = 2, MAINT_PRESCALER_PERIOD = 200000) (\r\n\tinput clk,\r\n\tinput rst,\r\n\t\r\n\tinput dfi_init_complete,\r\n\t\r\n\toutput maint_prescaler_tick\r\n);\r\n\r\n\tfunction integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n\tendfunction // clogb2\r\n\t\n localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD/(tCK * nCK_PER_CLK); // Round down.\r\n\tlocalparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1);\r\n\tlocalparam ONE = 1;\r\n\t\r\n\t// Maintenance and periodic read prescaler. Nominally 200 nS.\n\treg maint_prescaler_tick_r_lcl;\n\treg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r;\n\treg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns;\r\n\t\n\twire maint_prescaler_tick_ns = (maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]);\n\talways @(/*AS*/dfi_init_complete or maint_prescaler_r\n\t\t\t\tor maint_prescaler_tick_ns) begin\n\t\tmaint_prescaler_ns = maint_prescaler_r;\n\t\tif (~dfi_init_complete || maint_prescaler_tick_ns)\n\t\t\tmaint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0];\n\t\telse if (|maint_prescaler_r)\n\t\t\tmaint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0];\n\tend\r\n\t\n\talways @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns;\n\n\talways @(posedge clk) maint_prescaler_tick_r_lcl <= #TCQ maint_prescaler_tick_ns;\r\n\t\t\t\t\t\t\t\t \n\tassign maint_prescaler_tick = maint_prescaler_tick_r_lcl;\r\n\r\nendmodule\r\n\r\n//NOTE: this module is designed for 1 rank systems\r\n\r\nmodule periodic_rd_ctrl #(parameter tCK = 2500, nCK_PER_CLK = 2, TCQ = 100, MAINT_PRESCALER_PERIOD = 200000) (\r\n\t\tinput clk,\r\n\t\tinput rst,\r\n\t\t\r\n\t\tinput dfi_init_complete,\r\n\t\tinput maint_prescaler_tick,\r\n\t\t\r\n\t\tinput periodic_rd_ack, //NOTE: this also should be asserted for regular reads\r\n\t\toutput periodic_rd_req\r\n\t);\r\n\t\r\n\tfunction integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n\tendfunction // clogb2\r\n\t\r\n\tlocalparam tPRDI = 1_000_000;\r\n\tlocalparam PERIODIC_RD_TIMER_DIV = tPRDI/MAINT_PRESCALER_PERIOD;\r\n\tlocalparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1);\r\n\tlocalparam ONE = 1;\r\n\t \r\n\treg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r, periodic_rd_timer;\r\n\treg periodic_rd_request_r;\r\n\t \r\n\talways @* begin\r\n\t\tperiodic_rd_timer = periodic_rd_timer_r;\r\n\t\t\r\n\t\tif(~dfi_init_complete) begin\r\n\t\t\tperiodic_rd_timer = {PERIODIC_RD_TIMER_WIDTH{1'b0}};\r\n\t\tend\r\n\t\telse if (periodic_rd_ack) begin\r\n\t\t\tperiodic_rd_timer = PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];\r\n\t\tend\r\n\t\telse if (|periodic_rd_timer_r && maint_prescaler_tick) begin\n\t\t\tperiodic_rd_timer = periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH];\r\n\t\tend\r\n\tend //always\r\n\t \r\n\twire periodic_rd_timer_one = maint_prescaler_tick && (periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]);\r\n\t \r\n\twire periodic_rd_request = ~rst && (/*((PERIODIC_RD_TIMER_DIV != 0) && ~dfi_init_complete) ||*/\n (~periodic_rd_ack && (periodic_rd_request_r || periodic_rd_timer_one)));\r\n\t \r\n\talways @(posedge clk) begin\r\n\t\tperiodic_rd_timer_r <= #TCQ periodic_rd_timer;\r\n\t\tperiodic_rd_request_r <= #TCQ periodic_rd_request;\r\n\tend //always\r\n\t\r\n\tassign periodic_rd_req = periodic_rd_request_r;\r\n\t\r\nendmodule\r\n\r\n\r\nmodule zq_calib_ctrl #(parameter TCQ = 100, MAINT_PRESCALER_PERIOD = 200000) (\r\n\tinput clk,\r\n\tinput rst,\r\n\t\r\n\tinput zq_ack,\r\n\toutput reg zq_request,\r\n\t\r\n\tinput dfi_init_complete,\r\n\tinput maint_prescaler_tick\r\n);\r\n\r\n\tfunction integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n\tendfunction // clogb2\r\n\r\n\t// ZQ timebase. Nominally 128 mS\r\n\tlocalparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000;\n\tlocalparam tZQI = 128_000_000;\r\n\tlocalparam ZQ_TIMER_DIV = tZQI/MAINT_PRESCALER_PERIOD_NS;\n\tlocalparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1);\r\n\tlocalparam ONE = 1;\r\n\t\n\tgenerate\n\t\tbegin : zq_cntrl\n\t\t\treg zq_tick = 1'b0;\r\n\t\t\t\n\t\t\tif (ZQ_TIMER_DIV !=0) begin : zq_timer\n\t\t\t\treg [ZQ_TIMER_WIDTH-1:0] zq_timer_r;\n\t\t\t\treg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns;\r\n\t\t\t\t\n\t\t\t\talways @(/*AS*/dfi_init_complete or maint_prescaler_tick\n\t\t\t\tor zq_tick or zq_timer_r) begin\n\t\t\t\t\tzq_timer_ns = zq_timer_r;\n\t\t\t\t\tif (~dfi_init_complete || zq_tick)\n\t\t\t\t\t\tzq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0];\n\t\t\t\t\telse if (|zq_timer_r && maint_prescaler_tick)\n\t\t\t\t\t\tzq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0];\n\t\t\t\tend\r\n\t\t\t\t\n\t\t\t\talways @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns;\r\n\t\t\t\t\n\t\t\t\talways @(/*AS*/maint_prescaler_tick or zq_timer_r)\n\t\t\t\t\tzq_tick = (zq_timer_r == ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick);\n\t\t\tend // zq_timer\n\n\t\t\t// ZQ request. Set request with timer tick, and when exiting PHY init. Never\n\t\t\t// request if ZQ_TIMER_DIV == 0.\n\t\t\tbegin : zq_request_logic\n\t\t\t\twire zq_clears_zq_request = zq_ack;\n\t\t\t\treg zq_request_r;\n\t\t\t\twire zq_request_ns = ~rst && ((~dfi_init_complete && (ZQ_TIMER_DIV != 0)) || \r\n\t\t\t\t\t(zq_request_r && ~zq_clears_zq_request) || zq_tick);\r\n\t\t\t\t\n\t\t\t\talways @(posedge clk) zq_request_r <= #TCQ zq_request_ns;\r\n\t\t\t\t\n\t\t\t\talways @(/*AS*/dfi_init_complete or zq_request_r)\n\t\t\t\t\tzq_request = dfi_init_complete && zq_request_r;\n\t\t\tend // zq_request_logic\n\t\tend\n\tendgenerate\r\n\r\nendmodule\n\nmodule autoref_ctrl #(parameter TCQ = 100) (\r\n\tinput clk,\r\n\tinput rst,\r\n\t\n\tinput autoref_en,\n\tinput[27:0] autoref_interval,\r\n\tinput autoref_ack,\r\n\toutput autoref_req,\r\n\t\r\n\tinput dfi_init_complete,\r\n\tinput maint_prescaler_tick\r\n);\n\r\n\tlocalparam ONE = 1;\r\n\t \r\n\treg [27:0] autoref_timer_r, autoref_timer;\r\n\treg autoref_request_r;\n\treg ref_en_r;\r\n\t \r\n\talways @* begin\r\n\t\tautoref_timer = autoref_timer_r;\r\n\t\t\r\n\t\tif(~dfi_init_complete || autoref_ack || (~ref_en_r && autoref_en)) begin\r\n\t\t\tautoref_timer = autoref_interval;\r\n\t\tend\r\n\t\telse if (|autoref_timer_r && maint_prescaler_tick) begin\n\t\t\tautoref_timer = autoref_timer_r - ONE[0+:28];\r\n\t\tend\r\n\tend //always\r\n\t \r\n\twire autoref_timer_one = maint_prescaler_tick && (autoref_timer_r == ONE[0+:28]);\r\n\t \r\n\twire autoref_request = ~rst && dfi_init_complete && autoref_en && (\n\t\t\t\t\t\t\t\t(~autoref_ack && (autoref_request_r || autoref_timer_one)));\r\n\t \r\n\talways @(posedge clk) begin\r\n\t\tautoref_timer_r <= #TCQ autoref_timer;\r\n\t\tautoref_request_r <= #TCQ autoref_request;\n\t\tref_en_r <= #TCQ autoref_en;\r\n\tend //always\r\n\t\r\n\tassign autoref_req = autoref_request_r;\n\nendmodule\r\n" }, { "path": "hw/boards/ML605/maint_handler.v", "content": "`timescale 1ps / 1ps\r\n\r\n`include \"softMC.inc\"\r\n\r\nmodule maint_handler #(parameter CS_WIDTH = 1)(\r\n\t\t\tinput clk,\r\n\t\t\tinput rst,\r\n\t\t\t\r\n\t\t\tinput pr_rd_req,\r\n\t\t\tinput zq_req,\r\n\t\t\tinput autoref_req,\r\n\t\t\tinput[1:0] cur_bus_dir,\r\n\t\t\t\r\n\t\t\toutput maint_instr_en,\r\n\t\t\tinput maint_ack,\r\n\t\t\toutput reg[31:0] maint_instr,\r\n\t\t\t\r\n\t\t\tinput pr_rd_ack, //comes from the instruction sequence (iseq) dispatcher\r\n\t\t\toutput reg zq_ack,\r\n\t\t\toutput reg autoref_ack,\r\n\t\t\t\r\n\t\t\toutput periodic_read_lock,\r\n\t\t\t\r\n\t\t\tinput[27:0] trfc\r\n );\r\n\t \r\n\t localparam HIGH = 1'b1;\r\n\t localparam LOW = 1'b0;\r\n\t \r\n\t //maintenance logic\r\n\t reg pr_rd_process_ns, pr_rd_process_r = 1'b0;\r\n reg zq_process_ns, zq_process_r = 1'b0;\r\n\t reg autoref_process_ns, autoref_process_r = 1'b0;\r\n\t wire maint_process;\r\n\t \r\n\t localparam PR_RD_IO = 4'b0000;\r\n\t localparam PR_RD_PRE = 4'b0001;\r\n\t localparam PR_RD_WAIT_PRE = 4'b0010;\r\n\t localparam PR_RD_ACT = 4'b0011;\r\n\t localparam PR_RD_WAIT_ACT = 4'b0100;\r\n\t localparam PR_RD_READ = 4'b0101;\r\n\t localparam PR_RD_WAIT_READ = 4'b0110;\r\n\t localparam PR_RD_PRE2 = 4'b0111;\r\n\t localparam PR_RD_WAIT_PRE2 = 4'b1000;\r\n\t localparam PR_RD_WR_IO = 4'b1001;\r\n\t localparam MAINT_FIN = 4'b1010;\r\n\t \r\n\t localparam ZQ_PRE = 4'b0000;\r\n\t localparam ZQ_WAIT_PRE = 4'b0001;\r\n\t localparam ZQ_ZQ = 4'b0010;\r\n\t localparam ZQ_WAIT_ZQ = 4'b0011;\r\n\t \r\n\t localparam AREF_PRE = 4'b0000;\r\n\t localparam AREF_WAIT_PRE = 4'b0001;\r\n\t localparam AREF_REF = 4'b0010;\r\n\t localparam AREF_WAIT_REF = 4'b0011;\r\n\t \r\n\t reg[3:0] maint_state, maint_state_ns;\r\n\t \r\n\t reg lock_pr_rd_r, lock_pr_rd_ns;\r\n\t reg[1:0] cur_bus_dir_r, cur_bus_dir_ns;\r\n\t \r\n\t always@* begin\r\n\t\tpr_rd_process_ns = pr_rd_process_r;\r\n\t\tzq_process_ns = zq_process_r;\r\n\t\tautoref_process_ns = autoref_process_r;\r\n\t\t\r\n\t\tlock_pr_rd_ns = lock_pr_rd_r;\r\n\t\t\r\n\t\tzq_ack = 1'b0;\r\n\t\tautoref_ack = 1'b0;\r\n\t\t\r\n\t\tmaint_state_ns = maint_state;\r\n\t\tmaint_instr = {`END_ISEQ, 28'd0};\r\n\t\t\r\n\t\tcur_bus_dir_ns = cur_bus_dir_r;\r\n\t\t\t\r\n\t\t//enter maintenance\r\n\t\tif(~maint_process) begin\r\n\t\t\tif(pr_rd_req & ~lock_pr_rd_r) begin\r\n\t\t\t\tpr_rd_process_ns = 1'b1;\r\n\t\t\t\tmaint_state_ns = PR_RD_IO;\r\n\t\t\tend //pr_rd_req\r\n\t\t\telse if(zq_req) begin\r\n\t\t\t\tzq_process_ns = 1'b1;\r\n\t\t\t\tmaint_state_ns = ZQ_PRE;\r\n\t\t\tend //zq_req\r\n\t\t\telse if(autoref_req) begin\r\n\t\t\t\tautoref_process_ns = 1'b1;\r\n\t\t\t\tmaint_state_ns = AREF_PRE;\r\n\t\t\tend\r\n\t\tend //~dispatcher_busy_r\r\n\t\t\r\n\t\t//process maintenance\r\n\t\tif(maint_process) begin\r\n\t\t\tif(pr_rd_process_r) begin //TODO: optimize to reduce periodic dummy read latency when open bank is available\r\n\t\t\t\tcase(maint_state)\r\n\t\t\t\t\tPR_RD_IO: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `SET_BUSDIR;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tcur_bus_dir_ns = cur_bus_dir;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = PR_RD_PRE;\r\n\t\t\t\t\tend //PR_RD_IO\r\n\t\t\t\t\t\r\n\t\t\t\t\tPR_RD_PRE: begin\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t//Precharge banks 0\r\n\t\t\t\t\t\tmaint_instr[31:28] = `DDR_INSTR;\r\n\t\t\t\t\t\tmaint_instr[`CKE_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\r\n\t\t\t\t\t\tmaint_instr[`RAS_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[`CAS_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`WE_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[10] = LOW; //10th bit of the address field, A[10]\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = PR_RD_WAIT_PRE;\r\n\t\t\t\t\tend\r\n\t\t\t\t\t\r\n\t\t\t\t\tPR_RD_WAIT_PRE: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `WAIT;\r\n\t\t\t\t\t\tmaint_instr[27:0] = `DEF_TRP;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = PR_RD_ACT;\r\n\t\t\t\t\tend //PR_RD_WAIT_PRE\r\n\t\t\t\t\t\r\n\t\t\t\t\tPR_RD_ACT: begin\r\n\t\t\t\t\t\t//activate bank 0, row 0\r\n\t\t\t\t\t\tmaint_instr[31:28] = `DDR_INSTR;\r\n\t\t\t\t\t\tmaint_instr[`CKE_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\r\n\t\t\t\t\t\tmaint_instr[`RAS_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[`CAS_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`WE_OFFSET] = HIGH;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = PR_RD_WAIT_ACT;\r\n\t\t\t\t\tend //PR_RD_ACT\r\n\t\t\t\t\t\r\n\t\t\t\t\tPR_RD_WAIT_ACT: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `WAIT;\r\n\t\t\t\t\t\tmaint_instr[27:0] = `DEF_TRCD;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = PR_RD_READ;\r\n\t\t\t\t\tend //PR_RD_WAIT_ACT\r\n\t\t\t\t\t\r\n\t\t\t\t\tPR_RD_READ: begin\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t//Read instruction\r\n\t\t\t\t\t\tmaint_instr[31:28] = `DDR_INSTR;\r\n\t\t\t\t\t\tmaint_instr[`CKE_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\r\n\t\t\t\t\t\tmaint_instr[`RAS_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`CAS_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[`WE_OFFSET] = HIGH;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = PR_RD_WAIT_READ;\r\n\t\t\t\t\tend //PR_RD_READ\r\n\t\t\t\t\t\r\n\t\t\t\t\tPR_RD_WAIT_READ: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `WAIT;\r\n\t\t\t\t\t\tmaint_instr[27:0] = `DEF_TRAS - `DEF_TRCD;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = PR_RD_PRE2;\r\n\t\t\t\t\tend //PR_RD_WAIT_READ\r\n\t\t\t\t\t\r\n\t\t\t\t\tPR_RD_PRE2: begin\r\n\t\t\t\t\t\t//Precharge banks 0\r\n\t\t\t\t\t\tmaint_instr[31:28] = `DDR_INSTR;\r\n\t\t\t\t\t\tmaint_instr[`CKE_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\r\n\t\t\t\t\t\tmaint_instr[`RAS_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[`CAS_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`WE_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[10] = LOW; //10th bit of the address field, A[10]\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = PR_RD_WAIT_PRE2;\r\n\t\t\t\t\tend //PR_RD_PRE2\r\n\t\t\t\t\t\r\n\t\t\t\t\tPR_RD_WAIT_PRE2: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `WAIT;\r\n\t\t\t\t\t\tmaint_instr[27:0] = `DEF_TRP;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = (cur_bus_dir_r == `BUS_DIR_READ) ? MAINT_FIN : PR_RD_WR_IO;\r\n\t\t\t\t\tend //PR_RD_WAIT_PRE2\r\n\t\t\t\t\t\r\n\t\t\t\t\tPR_RD_WR_IO: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `SET_BUSDIR;\r\n\t\t\t\t\t\tmaint_instr[1:0] = `BUS_DIR_WRITE;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = MAINT_FIN;\r\n\t\t\t\t\tend\r\n\t\t\t\t\t\r\n\t\t\t\t\tMAINT_FIN: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `END_ISEQ;\r\n\t\t\t\t\t\tpr_rd_process_ns = 1'b0;\r\n\t\t\t\t\t\tlock_pr_rd_ns = 1'b1;\r\n\t\t\t\t\tend //MAINT_FIN\r\n\t\t\t\t\t\r\n\t\t\t\tendcase //pr_rd_state\r\n\t\t\tend //pr_rd_process_r\r\n\t\t\telse if(zq_process_r) begin\r\n\t\t\t\tcase(maint_state)\r\n\t\t\t\t\tZQ_PRE: begin\r\n\t\t\t\t\t\t//Precharge all banks\r\n\t\t\t\t\t\tmaint_instr[31:28] = `DDR_INSTR;\r\n\t\t\t\t\t\tmaint_instr[`CKE_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\r\n\t\t\t\t\t\tmaint_instr[`RAS_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[`CAS_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`WE_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[10] = HIGH; //10th bit of the address field, A[10]\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = ZQ_WAIT_PRE;\r\n\t\t\t\t\tend //ZQ_INIT\t\r\n\t\t\t\t\t\r\n\t\t\t\t\tZQ_WAIT_PRE: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `WAIT;\r\n\t\t\t\t\t\tmaint_instr[27:0] = `DEF_TRP;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = ZQ_ZQ;\r\n\t\t\t\t\tend //ZQ_WAIT_PRE\r\n\t\t\t\t\t\r\n\t\t\t\t\tZQ_ZQ: begin\r\n\t\t\t\t\t\t//ZQ-Short Instruction\r\n\t\t\t\t\t\tmaint_instr[31:28] = `DDR_INSTR;\r\n\t\t\t\t\t\tmaint_instr[`CKE_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\r\n\t\t\t\t\t\tmaint_instr[`RAS_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`CAS_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`WE_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[10] = LOW; //10th bit of the address field, A[10]\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = ZQ_WAIT_ZQ;\r\n\t\t\t\t\tend //ZQ_ZQ\r\n\t\t\t\t\t\r\n\t\t\t\t\tZQ_WAIT_ZQ: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `WAIT;\r\n\t\t\t\t\t\tmaint_instr[27:0] = `DEF_TZQCS;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = MAINT_FIN;\r\n\t\t\t\t\tend //ZQ_WAIT_ZQ\r\n\t\t\t\t\t\r\n\t\t\t\t\tMAINT_FIN: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `END_ISEQ;\r\n\t\t\t\t\t\tzq_process_ns = 1'b0;\r\n\t\t\t\t\t\tzq_ack = 1'b1;\r\n\t\t\t\t\tend //MAINT_FIN\r\n\t\t\t\t\r\n\t\t\t\tendcase //maint_state\r\n\t\t\tend //zq_process_r\r\n\t\t\t\r\n\t\t\telse if(autoref_process_r) begin\r\n\t\t\t\tcase(maint_state)\r\n\t\t\t\t\tAREF_PRE: begin\r\n\t\t\t\t\t\t//Precharge all banks\r\n\t\t\t\t\t\tmaint_instr[31:28] = `DDR_INSTR;\r\n\t\t\t\t\t\tmaint_instr[`CKE_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\r\n\t\t\t\t\t\tmaint_instr[`RAS_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[`CAS_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`WE_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[10] = HIGH; //10th bit of the address field, A[10]\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = AREF_WAIT_PRE;\r\n\t\t\t\t\tend //AREF_PRE\r\n\t\t\t\t\t\r\n\t\t\t\t\tAREF_WAIT_PRE: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `WAIT;\r\n\t\t\t\t\t\tmaint_instr[27:0] = `DEF_TRP;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = AREF_REF;\r\n\t\t\t\t\tend //AREF_WAIT_PRE\r\n\t\t\t\t\t\r\n\t\t\t\t\tAREF_REF: begin\r\n\t\t\t\t\t\t//Refresh Instruction //TODO: assign CS appropriately when implementing multi-rank support\r\n\t\t\t\t\t\tmaint_instr[31:28] = `DDR_INSTR;\r\n\t\t\t\t\t\tmaint_instr[`CKE_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};\r\n\t\t\t\t\t\tmaint_instr[`RAS_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[`CAS_OFFSET] = LOW;\r\n\t\t\t\t\t\tmaint_instr[`WE_OFFSET] = HIGH;\r\n\t\t\t\t\t\tmaint_instr[10] = HIGH; //10th bit of the address field, A[10]\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = AREF_WAIT_REF;\r\n\t\t\t\t\tend //AREF_REF\r\n\t\t\t\t\t\r\n\t\t\t\t\tAREF_WAIT_REF: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `WAIT;\r\n\t\t\t\t\t\tmaint_instr[27:0] = trfc;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tif(maint_ack)\r\n\t\t\t\t\t\t\tmaint_state_ns = MAINT_FIN;\r\n\t\t\t\t\tend //AREF_WAIT_REF\r\n\t\t\t\t\t\r\n\t\t\t\t\tMAINT_FIN: begin\r\n\t\t\t\t\t\tmaint_instr[31:28] = `END_ISEQ;\r\n\t\t\t\t\t\tautoref_process_ns = 1'b0;\r\n\t\t\t\t\t\tautoref_ack = 1'b1;\r\n\t\t\t\t\tend //MAINT_FIN\r\n\t\t\t\t\t\r\n\t\t\t\tendcase //maint_state\r\n\t\t\tend //autoref_process_r\r\n\t\t\t\r\n\t\tend //maint_process\r\n\t\t\r\n\t\tif(pr_rd_ack) begin\r\n\t\t\tlock_pr_rd_ns = 1'b0;\r\n\t\t\tpr_rd_process_ns = 1'b0;\r\n\t\tend\r\n\t\t\t\r\n end //always maintenance\r\n\t \r\n\t assign periodic_read_lock = lock_pr_rd_r;\r\n\t \r\n\t always@(posedge clk) begin\r\n\t\tif(rst) begin\r\n\t\t\tlock_pr_rd_r <= 1'b0;\r\n\t\t\tmaint_state <= 4'd0;\r\n\t\t\tcur_bus_dir_r <= `BUS_DIR_READ;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tlock_pr_rd_r <= lock_pr_rd_ns;\r\n\t\t\tmaint_state <= maint_state_ns;\r\n\t\t\tcur_bus_dir_r <= cur_bus_dir_ns;\r\n\t\tend\r\n\t end\r\n\t \r\n\t assign maint_process = pr_rd_process_r | zq_process_r | autoref_process_r;\r\n\t \r\n\t assign maint_instr_en = maint_process;\r\n\t\t\r\n\t always@(posedge clk) begin\r\n\t\tpr_rd_process_r <= pr_rd_process_ns;\r\n\t\tzq_process_r <= zq_process_ns;\r\n\t\tautoref_process_r <= autoref_process_ns;\r\n\t end\r\n\r\n\r\nendmodule\r\n" }, { "path": "hw/boards/ML605/patches/iodelay_ctrl.patch", "content": "--- ipcore_dir/xilinx_mig/user_design/rtl/ip_top/iodelay_ctrl.v\n@@ -94,1 +94,2 @@\n input sys_rst,\n+ output clk_200, // single 200MHz clock for ML605\n@@ -161,1 +162,2 @@\n );\n+ assign clk_200 = clk_ref_bufg; // ML605 single 200MHz clock source\n" }, { "path": "hw/boards/ML605/patches/phy_rdctrl_sync.patch", "content": "--- ipcore_dir/xilinx_mig/user_design/rtl/phy/phy_rdctrl_sync.v\t2017-02-03 15:11:19.000000000 +0100\n@@ -91,4 +91,8 @@\n input dfi_rddata_en,\n+ input dfi_rddata_en_even,\n+ input dfi_rddata_en_odd,\n input phy_rddata_en,\n // Control for read logic, initialization logic\n output reg dfi_rddata_valid,\n+ output reg dfi_rddata_valid_even,\n+ output reg dfi_rddata_valid_odd,\n@@ -113,3 +117,7 @@\n wire rddata_en;\n+ wire rddata_en_even;\n+ wire rddata_en_odd;\n wire rddata_en_rsync;\n wire rddata_en_srl_out;\n+ wire rddata_en_srl_out_even;\n+ wire rddata_en_srl_out_odd;\n@@ -124,1 +132,3 @@\n assign rddata_en = (mc_data_sel) ? dfi_rddata_en : phy_rddata_en;\n+ assign rddata_en_even = (mc_data_sel) ? dfi_rddata_en_even : phy_rddata_en;\n+ assign rddata_en_odd = (mc_data_sel) ? dfi_rddata_en_odd : phy_rddata_en;\n@@ -136,1 +146,21 @@\n \n+ SRLC32E u_rddata_en_srl_even\n+ (\n+ .Q (rddata_en_srl_out_even),\n+ .Q31 (),\n+ .A (rd_active_dly),\n+ .CE (1'b1),\n+ .CLK (clk),\n+ .D (rddata_en_even)\n+ );\n+\n+ SRLC32E u_rddata_en_srl_odd\n+ (\n+ .Q (rddata_en_srl_out_odd),\n+ .Q31 (),\n+ .A (rd_active_dly),\n+ .CE (1'b1),\n+ .CLK (clk),\n+ .D (rddata_en_odd)\n+ );\n+\n@@ -140,1 +170,3 @@\n dfi_rddata_valid <= #TCQ rddata_en_srl_out & mc_data_sel;\n+ dfi_rddata_valid_even <= #TCQ rddata_en_srl_out_even & mc_data_sel;\n+ dfi_rddata_valid_odd <= #TCQ rddata_en_srl_out_odd & mc_data_sel;\n" }, { "path": "hw/boards/ML605/patches/phy_read.patch", "content": "--- ipcore_dir/xilinx_mig/user_design/rtl/phy/phy_read.v\t2017-02-03 15:11:19.000000000 +0100\n@@ -129,4 +129,8 @@\n input dfi_rddata_en,\n+ input dfi_rddata_en_even,\n+ input dfi_rddata_en_odd,\n input phy_rddata_en,\n // Synchronized data/valid back to MC/PHY rdlvl logic\n output dfi_rddata_valid,\n+ output dfi_rddata_valid_even,\n+ output dfi_rddata_valid_odd,\n@@ -199,3 +203,7 @@\n .dfi_rddata_en (dfi_rddata_en),\n+ .dfi_rddata_en_even (dfi_rddata_en_even),\n+ .dfi_rddata_en_odd (dfi_rddata_en_odd),\n .phy_rddata_en (phy_rddata_en),\n .dfi_rddata_valid (dfi_rddata_valid),\n+ .dfi_rddata_valid_even(dfi_rddata_valid_even),\n+ .dfi_rddata_valid_odd (dfi_rddata_valid_odd),\n" }, { "path": "hw/boards/ML605/patches/phy_top.patch", "content": "--- ipcore_dir/xilinx_mig/user_design/rtl/phy/phy_top.v\t2017-02-03 15:11:19.000000000 +0100\n@@ -93,1 +93,1 @@\n- parameter BANK_WIDTH = 2, // # of bank bits\n+ parameter BANK_WIDTH = 3, // # of bank bits\n@@ -103,1 +103,1 @@\n- parameter ROW_WIDTH = 14, // DRAM address bus width\n+ parameter ROW_WIDTH = 16, // DRAM address bus width\n@@ -124,1 +124,1 @@\n- parameter REG_CTRL = \"ON\", // \"ON\" for registered DIMM\n+ parameter REG_CTRL = \"OFF\", // \"ON\" for registered DIMM\n@@ -194,3 +194,7 @@\n input dfi_rddata_en,\n+ input dfi_rddata_en_even,\n+ input dfi_rddata_en_odd,\n output [4*DQ_WIDTH-1:0] dfi_rddata,\n output dfi_rddata_valid,\n+ output dfi_rddata_valid_even,\n+ output dfi_rddata_valid_odd,\n@@ -1100,3 +1104,7 @@\n .dfi_rddata_en (dfi_rddata_en),\n+ .dfi_rddata_en_even (dfi_rddata_en_even),\n+ .dfi_rddata_en_odd (dfi_rddata_en_odd),\n .phy_rddata_en (phy_rddata_en),\n .dfi_rddata_valid (dfi_rddata_valid),\n+ .dfi_rddata_valid_even(dfi_rddata_valid_even),\n+ .dfi_rddata_valid_odd (dfi_rddata_valid_odd),\n" }, { "path": "hw/boards/ML605/pipe_reg.v", "content": "`timescale 1ps / 1ps\n\nmodule pipe_reg #(parameter WIDTH = 8) (\n input clk,\n input rst,\n \n input ready_in,\n input valid_in,\n input[WIDTH - 1:0] data_in,\n output valid_out,\n output[WIDTH - 1:0] data_out,\n output ready_out\n );\n \n (* keep = \"true\" *) reg r_ready, r_valid1, r_valid2;\n (* keep = \"true\" *) reg[WIDTH - 1:0] r_data1, r_data2;\n \n wire first_buf_ready = ready_in | ~r_valid1;\n \n assign data_out = r_data1;\n assign valid_out = r_valid1;\n assign ready_out = r_ready;\n \n always@(posedge clk)\n begin\n if(rst) begin\n r_data1 <= 0;\n r_data2 <= 0;\n r_ready <= 0;\n r_valid1 <= 0;\n r_valid2 <= 0;\n end\n else begin\n //data acquisition\n if(r_ready) begin\n if(first_buf_ready) begin\n r_data1 <= data_in;\n r_valid1 <= valid_in;\n end\n else begin\n r_data2 <= data_in;\n r_valid2 <= valid_in;\n end\n end //r_ready\n \n //data shift\n if(~r_ready & ready_in) begin\n r_data1 <= r_data2;\n r_valid1 <= r_valid2;\n end\n end\n \n //control\n r_ready <= first_buf_ready;\n end\nendmodule\n" }, { "path": "hw/boards/ML605/read_capturer.v", "content": "`timescale 1ns / 1ps\n\nmodule read_capturer #(parameter DQ_WIDTH = 64) (\r\n\tinput clk,\r\n\tinput rst,\n\t\n\t//DFI Interface\r\n\tinput [4*DQ_WIDTH-1:0] dfi_rddata,\n\tinput dfi_rddata_valid,\n\tinput\t\t\t\t\t\t\tdfi_rddata_valid_even,\n\tinput\t\t\t\t\t\t\tdfi_rddata_valid_odd,\n\toutput\t\t\t\t\t\tdfi_clk_disable,\n\t\n\t//FIFO interface\n\tinput rdback_fifo_almost_full,\n\tinput rdback_fifo_full,\n\toutput rdback_fifo_wren,\n\toutput[4*DQ_WIDTH-1:0] rdback_fifo_wrdata\r\n);\n\n\treg[4*DQ_WIDTH-1:0] rd_data_r, rd_data_r2;\n\treg rd_data_en_r, rd_data_en_even_r, rd_data_en_odd_r;\n\treg rdback_fifo_full_r;\n\t\n\talways@(posedge clk) begin\n\t\tif(rst) begin\n\t\t\trd_data_r <= 0;\n\t\t\trd_data_r2 <= 0;\n\t\t\trd_data_en_r <= 0;\n\t\t\trd_data_en_even_r <= 0;\n\t\t\trd_data_en_odd_r <= 0;\n\t\t\trdback_fifo_full_r <= 0;\n\t\tend\n\t\telse begin\n\t\t\trd_data_r <= dfi_rddata;\n\t\t\trd_data_r2 <= rd_data_r;\n\t\t\trd_data_en_r <= dfi_rddata_valid;\n\t\t\trd_data_en_even_r <= dfi_rddata_valid_even;\n\t\t\trd_data_en_odd_r <= dfi_rddata_valid_odd;\n\t\t\t\n\t\t\trdback_fifo_full_r <= rdback_fifo_almost_full | rdback_fifo_full;\n\t\tend\n\tend\n\t\n\tassign rdback_fifo_wren = ~rd_data_en_odd_r & rd_data_en_r;\n\tassign rdback_fifo_wrdata = rd_data_en_even_r ? {rd_data_r[DQ_WIDTH*2 - 1:0], rd_data_r2[DQ_WIDTH*2 +: DQ_WIDTH*2]} : rd_data_r;\n\t\n\tassign dfi_clk_disable = rdback_fifo_full_r;\r\n\r\nendmodule\n" }, { "path": "hw/boards/ML605/softMC.inc", "content": "//uncomment the line below to run a simulation using \"tb_softMC_top\"\n//`define SIM\n\n`define tCK 2500\n\n// instruction opcodes\n`define DDR_INSTR 4'b1xxx\n`define END_ISEQ 4'b0000\n`define SET_BUSDIR 4'b0001\n`define SET_TREFI 4'b0010\n`define SET_TRFC 4'b0011\n`define WAIT 4'b0100\n\n\n\n`define ROW_OFFSET 16\n`define WE_OFFSET 19\n`define CAS_OFFSET 20\n`define RAS_OFFSET 21\n`define CS_OFFSET 22\n`define CKE_OFFSET 24\n\n\n\n`define BUS_DIR_READ 2'b00\n`define BUS_DIR_WRITE 2'b10\n\n//Set accordingly to tCK, (6, 6, 14 if tCK = 2500ps)\n`define DEF_TRP 15000/`tCK\n`define DEF_TRCD 15000/`tCK\n`define DEF_TRAS 35000/`tCK\n`define DEF_TZQCS 64 //mem_clk cycles\n" }, { "path": "hw/boards/ML605/softMC.v", "content": "`timescale 1ps / 1ps\r\n\n`include \"softMC.inc\"\n\n//NOTE: currently accepts only one instruction sequence, need to process it first to receive another\r\nmodule softMC #(parameter TCQ = 100, tCK = 2500, nCK_PER_CLK = 2, RANK_WIDTH = 1, ROW_WIDTH = 15, BANK_WIDTH = 3, \r\n\t\t\t\t\t\t\t\tCKE_WIDTH = 1, CS_WIDTH = 1, nCS_PER_RANK = 1, DQ_WIDTH = 64) (\r\n\tinput clk,\r\n\tinput rst,\r\n\t\r\n\t//App Command Interface\r\n\tinput app_en,\n\toutput app_ack,\r\n\tinput[31:0] app_instr, \r\n\toutput iq_full,\n\toutput processing_iseq,\r\n\t\r\n\t// DFI Control/Address\n\toutput [ROW_WIDTH-1:0] dfi_address0,\n\toutput [ROW_WIDTH-1:0] dfi_address1,\n\toutput [BANK_WIDTH-1:0] dfi_bank0,\n\toutput [BANK_WIDTH-1:0] dfi_bank1,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_cas_n0,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_cas_n1,\n\toutput [CKE_WIDTH-1:0] dfi_cke0,\n\toutput [CKE_WIDTH-1:0] dfi_cke1,\n\toutput [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n0,\n\toutput [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n1,\n\toutput [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt0,\n\toutput [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt1,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_ras_n0,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_ras_n1,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_reset_n,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_we_n0,\n\toutput \t\t\t\t\t\t\t\t\t\tdfi_we_n1,\n\t// DFI Write\n\toutput dfi_wrdata_en,\n\toutput [4*DQ_WIDTH-1:0] dfi_wrdata,\n\toutput [4*(DQ_WIDTH/8)-1:0] dfi_wrdata_mask,\n\t// DFI Read\n\toutput dfi_rddata_en,\n\toutput\t\t\t\t\t\t\t\t\t\tdfi_rddata_en_even,\n\toutput\t\t\t\t\t\t\t\t\t\tdfi_rddata_en_odd,\n\tinput [4*DQ_WIDTH-1:0] dfi_rddata,\n\tinput dfi_rddata_valid,\n\tinput\t\t\t\t\t\t\t\t\t\t\tdfi_rddata_valid_even,\n\tinput\t\t\t\t\t\t\t\t\t\t\tdfi_rddata_valid_odd,\n\t// DFI Initialization Status / CLK Disable\n\toutput dfi_dram_clk_disable,\n\tinput dfi_init_complete,\n\t// sideband signals\n\toutput io_config_strobe,\n\toutput [RANK_WIDTH:0] io_config,\n\t\n\t//Data read back Interface\n\toutput rdback_fifo_empty,\n\tinput rdback_fifo_rden,\n\toutput[DQ_WIDTH*4 - 1:0] rdback_data\r\n);\r\n\t \r\n\t //DFI constants\n\t assign dfi_reset_n = 1;\r\n\t \r\n\t wire instr0_fifo_en, instr0_fifo_full, instr0_fifo_empty;\r\n\t wire[31:0] instr0_fifo_data, instr0_fifo_out;\r\n\t wire instr0_fifo_rd_en;\n\t \n\t wire instr1_fifo_en, instr1_fifo_full, instr1_fifo_empty;\r\n\t wire[31:0] instr1_fifo_data, instr1_fifo_out;\r\n\t wire instr1_fifo_rd_en;\r\n\t \r\n\t wire process_iseq;\n\t \r\n\t //MAINTENANCE module\r\n\t localparam MAINT_PRESCALER_PERIOD = 200000;\r\n\t wire pr_rd_req, zq_req, autoref_req;\r\n\t wire pr_rd_ack, zq_ack, autoref_ack;\n\t \n\t //Auto-refresh signals\n\t wire aref_en;\n\t wire[27:0] aref_interval;\n\t wire[27:0] aref_trfc;\n\t wire aref_set_interval, aref_set_trfc;\n\t wire[27:0] aref_interval_in;\n\t wire[27:0] aref_trfc_in;\n\t\r\n\t maint_ctrl_top #(.RANK_WIDTH(RANK_WIDTH), .TCQ (TCQ), .tCK(tCK), \n\t\t\t\t\t\t\t.nCK_PER_CLK(nCK_PER_CLK), .MAINT_PRESCALER_PERIOD(MAINT_PRESCALER_PERIOD)) \n\t i_maint_ctrl(\r\n\t .clk(clk),\r\n\t .rst(rst),\r\n\t\r\n\t .dfi_init_complete(dfi_init_complete),\r\n \t\r\n \t .periodic_rd_ack(pr_rd_ack),\r\n\t .periodic_rd_req(pr_rd_req),\r\n\t .zq_ack(zq_ack),\r\n\t .zq_req(zq_req),\n\t \n\t //Auto-refresh\n\t .autoref_en(aref_en),\n\t .autoref_interval(aref_interval),\n\t .autoref_ack(autoref_ack),\n\t .autoref_req(autoref_req)\r\n );\n\t \n\t wire periodic_read_lock;\n\t wire maint_en;\n\t wire maint_ack;\n\t wire[31:0] maint_instr;\n\t \n\t maint_handler #(.CS_WIDTH(CS_WIDTH)) i_maint_handler(\n\t\t\t.clk(clk),\n\t\t\t.rst(rst),\n\t\t\t\n\t\t\t.pr_rd_req(pr_rd_req),\n\t\t\t.zq_req(zq_req),\n\t\t\t.autoref_req(autoref_req),\n\t\t\t.cur_bus_dir(dfi_odt0 ? `BUS_DIR_WRITE : `BUS_DIR_READ),\n\t\t\t\n\t\t\t.maint_instr_en(maint_en),\n\t\t\t.maint_ack(maint_ack),\n\t\t\t.maint_instr(maint_instr),\n\t\t\t\n\t\t\t.pr_rd_ack(pr_rd_ack), //comes from the transaction dispatcher\n\t\t\t.zq_ack(zq_ack),\n\t\t\t.autoref_ack(autoref_ack),\n\t\t\t.periodic_read_lock(periodic_read_lock),\n\t\t\t\n\t\t\t.trfc(aref_trfc)\n );\n\t \n\t autoref_config i_aref_config(\n\t\t.clk(clk),\n\t\t.rst(rst),\n\t\t\n\t\t.set_interval(aref_set_interval),\n\t\t.interval_in(aref_interval_in),\n\t\t.set_trfc(aref_set_trfc),\n\t\t.trfc_in(aref_trfc_in),\n\t\t\n\t\t\n\t\t.aref_en(aref_en),\n\t\t.aref_interval(aref_interval),\n\t\t.trfc(aref_trfc)\n\t );\r\n\t \r\n\t instr_receiver i_instr_recv(\r\n\t\t.clk(clk),\r\n\t\t.rst(rst),\n\t\t\n\t\t.dispatcher_ready(~dispatcher_busy),\r\n\t\t\r\n\t\t.app_en(app_en),\n\t\t.app_ack(app_ack),\r\n\t\t.app_instr(app_instr), \n\t\t\n\t\t.maint_en(maint_en),\n\t\t.maint_ack(maint_ack),\n\t\t.maint_instr(maint_instr),\r\n\t\t\r\n\t\t.instr0_fifo_en(instr0_fifo_en),\r\n\t\t.instr0_fifo_data(instr0_fifo_data),\n\t\t\n\t\t.instr1_fifo_en(instr1_fifo_en),\r\n\t\t.instr1_fifo_data(instr1_fifo_data),\r\n\t\t\r\n\t\t.process_iseq(process_iseq)\r\n\t);\r\n\t\r\n\tinstr_fifo i_instr0_fifo (\r\n\t .srst(rst), // input rst\r\n\t .clk(clk), // input clk\r\n\t .din(instr0_fifo_data), // input [31 : 0] din\r\n\t .wr_en(instr0_fifo_en), // input wr_en\r\n\t .rd_en(instr0_fifo_rd_en), // input rd_en\r\n\t .dout(instr0_fifo_out), // output [31 : 0] dout\r\n\t .full(instr0_fifo_full), // output full\r\n\t .empty(instr0_fifo_empty) // output empty\r\n\t);\n\t\n\tinstr_fifo i_instr1_fifo (\r\n\t .srst(rst), // input rst\r\n\t .clk(clk), // input clk\r\n\t .din(instr1_fifo_data), // input [31 : 0] din\r\n\t .wr_en(instr1_fifo_en), // input wr_en\r\n\t .rd_en(instr1_fifo_rd_en), // input rd_en\r\n\t .dout(instr1_fifo_out), // output [31 : 0] dout\r\n\t .full(instr1_fifo_full), // output full\r\n\t .empty(instr1_fifo_empty) // output empty\r\n\t);\r\n\t\r\n\t\r\n\twire dfi_ready;\r\n\tiseq_dispatcher #(.ROW_WIDTH(ROW_WIDTH), .BANK_WIDTH(BANK_WIDTH), .CKE_WIDTH(CKE_WIDTH), \r\n\t\t\t\t\t\t\t\t\t\t.CS_WIDTH(CS_WIDTH), .nCS_PER_RANK(nCS_PER_RANK), .DQ_WIDTH(DQ_WIDTH)) i_iseq_disp (\r\n .clk(clk), \r\n .rst(rst), \n\t \n\t .periodic_read_lock(periodic_read_lock),\r\n\t \r\n .process_iseq(process_iseq), \r\n .dispatcher_busy(dispatcher_busy), \n\t \r\n .instr0_fifo_rd(instr0_fifo_rd_en), \r\n .instr0_fifo_empty(instr0_fifo_empty), \r\n .instr0_fifo_data(instr0_fifo_out), \n\n\t .instr1_fifo_rd(instr1_fifo_rd_en), \r\n .instr1_fifo_empty(instr1_fifo_empty), \r\n .instr1_fifo_data(instr1_fifo_out), \r\n\t \r\n\t //DFI Interface\n\t .dfi_ready(dfi_ready),\n\t .dfi_init_complete(dfi_init_complete),\r\n .dfi_address0(dfi_address0), \r\n .dfi_address1(dfi_address1), \r\n .dfi_bank0(dfi_bank0), \r\n .dfi_bank1(dfi_bank1), \n\t .dfi_cke0(dfi_cke0),\n\t .dfi_cke1(dfi_cke1),\r\n .dfi_cas_n0(dfi_cas_n0), \r\n .dfi_cas_n1(dfi_cas_n1), \r\n .dfi_cs_n0(dfi_cs_n0), \r\n .dfi_cs_n1(dfi_cs_n1),\r\n\t .dfi_odt0(dfi_odt0),\n\t .dfi_odt1(dfi_odt1),\r\n .dfi_ras_n0(dfi_ras_n0), \r\n .dfi_ras_n1(dfi_ras_n1), \r\n .dfi_we_n0(dfi_we_n0), \r\n .dfi_we_n1(dfi_we_n1), \r\n .dfi_wrdata_en(dfi_wrdata_en), \r\n .dfi_wrdata(dfi_wrdata), \r\n .dfi_wrdata_mask(dfi_wrdata_mask), \r\n .dfi_rddata_en(dfi_rddata_en), \n\t .dfi_rddata_en_even(dfi_rddata_en_even),\n\t .dfi_rddata_en_odd(dfi_rddata_en_odd),\r\n .io_config_strobe(io_config_strobe), \r\n .io_config(io_config),\n\t \n\t .pr_rd_ack(pr_rd_ack),\n\t \n\t //auto-refresh\n\t .aref_set_interval(aref_set_interval),\n\t .aref_interval(aref_interval_in),\n\t .aref_set_trfc(aref_set_trfc),\n\t .aref_trfc(aref_trfc_in)\r\n );\r\n\t\r\n\t\r\n\tassign iq_full = instr0_fifo_full | instr1_fifo_full;\n\tassign processing_iseq = dispatcher_busy;\n\t\n\twire[DQ_WIDTH*4 - 1: 0] rdback_fifo_wrdata, rdback_fifo_out;\n\twire rdback_fifo_full, rdback_fifo_almost_full;\n\twire rdback_fifo_wren;\n\t\n\trdback_fifo i_rdback_fifo (\n\t .clk(clk), // input clk\n\t .srst(rst), // input srst\n\t .din(rdback_fifo_wrdata), // input [255 : 0] din\n\t .wr_en(rdback_fifo_wren), // input wr_en\n\t .rd_en(rdback_fifo_rden), // input rd_en\n\t .dout(rdback_fifo_out), // output [255 : 0] dout\n\t .full(rdback_fifo_full), // output full\n\t .almost_full(rdback_fifo_almost_full),\n\t .empty(rdback_fifo_empty) // output empty\n\t);\n\tassign rdback_data = rdback_fifo_out;\n\n\twire read_capturer_dfi_clk_disable;\n\tread_capturer #(.DQ_WIDTH(DQ_WIDTH)) i_rd_capturer (\r\n\t.clk(clk),\r\n\t.rst(rst),\n\t\n\t//DFI Interface\r\n\t.dfi_rddata(dfi_rddata),\n\t.dfi_rddata_valid(dfi_rddata_valid),\n\t.dfi_rddata_valid_even(dfi_rddata_valid_even),\n\t.dfi_rddata_valid_odd(dfi_rddata_valid_odd),\n\t.dfi_clk_disable(read_capturer_dfi_clk_disable),\n\t\n\t//FIFO interface\n\t.rdback_fifo_full(rdback_fifo_full),\n\t.rdback_fifo_almost_full(rdback_fifo_almost_full),\n\t.rdback_fifo_wren(rdback_fifo_wren),\n\t.rdback_fifo_wrdata(rdback_fifo_wrdata)\r\n);\n\n\tassign dfi_dram_clk_disable = read_capturer_dfi_clk_disable;\n\tassign dfi_ready = ~dfi_dram_clk_disable;\r\n\r\nendmodule" }, { "path": "hw/boards/ML605/softMC_constraints.ucf", "content": "############################################################################\n# Timing constraints #\n# Most of these were inherited from the constraint file which is generated #\n# after configuring Xilinx MIG IPCore\t\t\t\t\t\t\t\t\t\t\t\t\t#\n############################################################################\n\n#NET \"sys_clk_p\" TNM_NET = TNM_sys_clk;\n#TIMESPEC \"TS_sys_clk\" = PERIOD \"TNM_sys_clk\" 2.5 ns;\n\nNET \"clk_ref_p\" TNM_NET = \"TNM_clk_ref\";\nTIMESPEC TS_clk_ref = PERIOD \"TNM_clk_ref\" 5 ns;\n\n# Constrain BUFR clocks used to synchronize data from IOB to fabric logic\n# Note that ISE cannot infer this from other PERIOD constraints because\n# of the use of OSERDES blocks in the BUFR clock generation path\nNET \"xil_phy/clk_rsync[?]\" TNM_NET = \"TNM_clk_rsync\";\nTIMESPEC TS_clk_rsync = PERIOD \"TNM_clk_rsync\" 5 ns;\n\n# Paths between DQ/DQS ISERDES.Q outputs and CLB flops clocked by falling\n# edge of BUFR will by design only be used if DYNCLKDIVSEL is asserted for\n# that particular flop. Mark this path as being a full-cycle, rather than\n# a half cycle path for timing purposes. NOTE: This constraint forces full-\n# cycle timing to be applied globally for all rising->falling edge paths\n# in all resynchronizaton clock domains. If the user had modified the logic\n# in the resync clock domain such that other rising->falling edge paths\n# exist, then constraint below should be modified to utilize pattern\n# matching to specific affect only the DQ/DQS ISERDES.Q outputs\nTIMEGRP TG_clk_rsync_rise = RISING \"TNM_clk_rsync\";\nTIMEGRP TG_clk_rsync_fall = FALLING \"TNM_clk_rsync\";\nTIMESPEC TS_clk_rsync_rise_to_fall = FROM \"TG_clk_rsync_rise\" TO \"TG_clk_rsync_fall\" 5 ns;\n\n# Signal to select between controller and physical layer signals. Four divided by two clock\n# cycles (4 memory clock cycles) are provided by design for the signal to settle down.\n# Used only by the phy modules.\nINST \"xil_phy/u_phy_init/u_ff_phy_init_data_sel\" TNM = \"TNM_PHY_INIT_SEL\";\nTIMESPEC TS_MC_PHY_INIT_SEL = FROM \"TNM_PHY_INIT_SEL\" TO FFS 10 ns;\n############################################################################\n########################################################################\n# Controller 0\n# Memory Device: DDR3_SDRAM->SODIMMs->MT8JSF25664HZ-1G4\n# Data Width: 64\n# Frequency: 400\n# Time Period: 2500\n# Data Mask: 0\n########################################################################\n\n\n################################################################################\n# I/O STANDARDS\n################################################################################\n\nNET \"ddr_dq[0]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[10]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[11]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[12]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[13]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[14]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[15]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[16]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[17]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[18]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[19]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[1]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[20]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[21]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[22]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[23]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[24]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[25]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[26]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[27]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[28]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[29]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[2]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[30]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[31]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[32]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[33]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[34]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[35]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[36]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[37]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[38]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[39]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[3]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[40]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[41]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[42]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[43]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[44]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[45]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[46]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[47]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[48]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[49]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[4]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[50]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[51]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[52]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[53]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[54]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[55]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[56]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[57]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[58]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[59]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[5]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[60]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[61]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[62]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[63]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[6]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[7]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[8]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_dq[9]\" IOSTANDARD = SSTL15_T_DCI;\nNET \"ddr_addr[0]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[10]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[11]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[12]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[13]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[14]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[15]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[1]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[2]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[3]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[4]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[5]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[6]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[7]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[8]\" IOSTANDARD = SSTL15;\nNET \"ddr_addr[9]\" IOSTANDARD = SSTL15;\nNET \"ddr_ba[0]\" IOSTANDARD = SSTL15;\nNET \"ddr_ba[1]\" IOSTANDARD = SSTL15;\nNET \"ddr_ba[2]\" IOSTANDARD = SSTL15;\nNET \"ddr_ras_n\" IOSTANDARD = SSTL15;\nNET \"ddr_cas_n\" IOSTANDARD = SSTL15;\nNET \"ddr_we_n\" IOSTANDARD = SSTL15;\nNET \"ddr_reset_n\" IOSTANDARD = SSTL15;\nNET \"ddr_cke[0]\" IOSTANDARD = SSTL15;\nNET \"ddr_odt[0]\" IOSTANDARD = SSTL15;\nNET \"ddr_cs_n[0]\" IOSTANDARD = SSTL15;\n#NET \"sys_clk_p\" IOSTANDARD = LVDS_25;\n#NET \"sys_clk_n\" IOSTANDARD = LVDS_25;\nNET \"clk_ref_p\" IOSTANDARD = LVDS_25;\nNET \"clk_ref_n\" IOSTANDARD = LVDS_25;\n#NET \"sda\" IOSTANDARD = LVCMOS25;\n#NET \"scl\" IOSTANDARD = LVCMOS25;\nNET \"sys_rst\" IOSTANDARD = SSTL15;\n#NET \"dfi_init_complete\" IOSTANDARD = LVCMOS25;\nNET \"ddr_dqs_p[0]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_p[1]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_p[2]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_p[3]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_p[4]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_p[5]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_p[6]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_p[7]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_n[0]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_n[1]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_n[2]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_n[3]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_n[4]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_n[5]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_n[6]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_dqs_n[7]\" IOSTANDARD = DIFF_SSTL15_T_DCI;\nNET \"ddr_ck_p[0]\" IOSTANDARD = DIFF_SSTL15;\nNET \"ddr_ck_p[1]\" IOSTANDARD = DIFF_SSTL15;\nNET \"ddr_ck_n[0]\" IOSTANDARD = DIFF_SSTL15;\nNET \"ddr_ck_n[1]\" IOSTANDARD = DIFF_SSTL15;\nNET \"ddr_dm[0]\" IOSTANDARD = SSTL15;\nNET \"ddr_dm[1]\" IOSTANDARD = SSTL15;\nNET \"ddr_dm[2]\" IOSTANDARD = SSTL15;\nNET \"ddr_dm[3]\" IOSTANDARD = SSTL15;\nNET \"ddr_dm[4]\" IOSTANDARD = SSTL15;\nNET \"ddr_dm[5]\" IOSTANDARD = SSTL15;\nNET \"ddr_dm[6]\" IOSTANDARD = SSTL15;\nNET \"ddr_dm[7]\" IOSTANDARD = SSTL15;\n\n################################################################################\n##SAVE attributes to reserve the pins\n################################################################################\n#NET \"sda\" S;\n#NET \"scl\" S;\nCONFIG DCI_CASCADE = \"26 25\";\nCONFIG DCI_CASCADE = \"36 35\";\n##################################################################################\n# Location Constraints\n##################################################################################\n#Bank 26\nNET \"ddr_dq[0]\" LOC = J11;\n#Bank 26\nNET \"ddr_dq[1]\" LOC = E13;\n#Bank 26\nNET \"ddr_dq[2]\" LOC = F13;\n#Bank 26\nNET \"ddr_dq[3]\" LOC = K11;\n#Bank 26\nNET \"ddr_dq[4]\" LOC = L11;\n#Bank 26\nNET \"ddr_dq[5]\" LOC = K13;\n#Bank 26\nNET \"ddr_dq[6]\" LOC = K12;\n#Bank 26\nNET \"ddr_dq[7]\" LOC = D11;\n#Bank 26\nNET \"ddr_dq[8]\" LOC = M13;\n#Bank 26\nNET \"ddr_dq[9]\" LOC = J14;\n#Bank 26\nNET \"ddr_dq[10]\" LOC = B13;\n#Bank 26\nNET \"ddr_dq[11]\" LOC = B12;\n#Bank 26\nNET \"ddr_dq[12]\" LOC = G10;\n#Bank 26\nNET \"ddr_dq[13]\" LOC = M11;\n#Bank 26\nNET \"ddr_dq[14]\" LOC = C12;\n#Bank 26\nNET \"ddr_dq[15]\" LOC = A11;\n#Bank 26\nNET \"ddr_dq[16]\" LOC = G11;\n#Bank 26\nNET \"ddr_dq[17]\" LOC = F11;\n#Bank 26\nNET \"ddr_dq[18]\" LOC = D14;\n#Bank 26\nNET \"ddr_dq[19]\" LOC = C14;\n#Bank 26\nNET \"ddr_dq[20]\" LOC = G12;\n#Bank 26\nNET \"ddr_dq[21]\" LOC = G13;\n#Bank 26\nNET \"ddr_dq[22]\" LOC = F14;\n#Bank 26\nNET \"ddr_dq[23]\" LOC = H14;\n#Bank 36\nNET \"ddr_dq[24]\" LOC = C19;\n#Bank 36\nNET \"ddr_dq[25]\" LOC = G20;\n#Bank 36\nNET \"ddr_dq[26]\" LOC = E19;\n#Bank 36\nNET \"ddr_dq[27]\" LOC = F20;\n#Bank 36\nNET \"ddr_dq[28]\" LOC = A20;\n#Bank 36\nNET \"ddr_dq[29]\" LOC = A21;\n#Bank 36\nNET \"ddr_dq[30]\" LOC = E22;\n#Bank 36\nNET \"ddr_dq[31]\" LOC = E23;\n#Bank 36\nNET \"ddr_dq[32]\" LOC = G21;\n#Bank 36\nNET \"ddr_dq[33]\" LOC = B21;\n#Bank 36\nNET \"ddr_dq[34]\" LOC = A23;\n#Bank 36\nNET \"ddr_dq[35]\" LOC = A24;\n#Bank 36\nNET \"ddr_dq[36]\" LOC = C20;\n#Bank 36\nNET \"ddr_dq[37]\" LOC = D20;\n#Bank 36\nNET \"ddr_dq[38]\" LOC = J20;\n#Bank 36\nNET \"ddr_dq[39]\" LOC = G22;\n#Bank 36\nNET \"ddr_dq[40]\" LOC = D26;\n#Bank 36\nNET \"ddr_dq[41]\" LOC = F26;\n#Bank 36\nNET \"ddr_dq[42]\" LOC = B26;\n#Bank 36\nNET \"ddr_dq[43]\" LOC = E26;\n#Bank 36\nNET \"ddr_dq[44]\" LOC = C24;\n#Bank 36\nNET \"ddr_dq[45]\" LOC = D25;\n#Bank 36\nNET \"ddr_dq[46]\" LOC = D27;\n#Bank 36\nNET \"ddr_dq[47]\" LOC = C25;\n#Bank 35\nNET \"ddr_dq[48]\" LOC = C27;\n#Bank 35\nNET \"ddr_dq[49]\" LOC = B28;\n#Bank 35\nNET \"ddr_dq[50]\" LOC = D29;\n#Bank 35\nNET \"ddr_dq[51]\" LOC = B27;\n#Bank 35\nNET \"ddr_dq[52]\" LOC = G27;\n#Bank 35\nNET \"ddr_dq[53]\" LOC = A28;\n#Bank 35\nNET \"ddr_dq[54]\" LOC = E24;\n#Bank 35\nNET \"ddr_dq[55]\" LOC = G25;\n#Bank 35\nNET \"ddr_dq[56]\" LOC = F28;\n#Bank 35\nNET \"ddr_dq[57]\" LOC = B31;\n#Bank 35\nNET \"ddr_dq[58]\" LOC = H29;\n#Bank 35\nNET \"ddr_dq[59]\" LOC = H28;\n#Bank 35\nNET \"ddr_dq[60]\" LOC = B30;\n#Bank 35\nNET \"ddr_dq[61]\" LOC = A30;\n#Bank 35\nNET \"ddr_dq[62]\" LOC = E29;\n#Bank 35\nNET \"ddr_dq[63]\" LOC = F29;\n#Bank 25\nNET \"ddr_addr[15]\" LOC = C15;\nNET \"ddr_addr[14]\" LOC = D15;\n#Bank 25\nNET \"ddr_addr[13]\" LOC = J15;\n#Bank 25\nNET \"ddr_addr[12]\" LOC = H15;\n#Bank 25\nNET \"ddr_addr[11]\" LOC = M15;\n#Bank 25\nNET \"ddr_addr[10]\" LOC = M16;\n#Bank 25\nNET \"ddr_addr[9]\" LOC = F15;\n#Bank 25\nNET \"ddr_addr[8]\" LOC = G15;\n#Bank 25\nNET \"ddr_addr[7]\" LOC = B15;\n#Bank 25\nNET \"ddr_addr[6]\" LOC = A15;\n#Bank 25\nNET \"ddr_addr[5]\" LOC = J17;\n#Bank 25\nNET \"ddr_addr[4]\" LOC = D16;\n#Bank 25\nNET \"ddr_addr[3]\" LOC = E16;\n#Bank 25\nNET \"ddr_addr[2]\" LOC = B16;\n#Bank 25\nNET \"ddr_addr[1]\" LOC = A16;\n#Bank 25\nNET \"ddr_addr[0]\" LOC = L14;\n#Bank 25\nNET \"ddr_ba[2]\" LOC = L15;\n#Bank 25\nNET \"ddr_ba[1]\" LOC = J19;\n#Bank 25\nNET \"ddr_ba[0]\" LOC = K19;\n#Bank 25\nNET \"ddr_ras_n\" LOC = L19;\n#Bank 25\nNET \"ddr_cas_n\" LOC = C17;\n#Bank 25\nNET \"ddr_we_n\" LOC = B17;\n#Bank 25\nNET \"ddr_reset_n\" LOC = E18;\n#Bank 25\nNET \"ddr_cke[0]\" LOC = M18;\n#Bank 25\nNET \"ddr_odt[0]\" LOC = F18;\n#Bank 25\nNET \"ddr_cs_n[0]\" LOC = K18;\n#NET \"sys_clk_p\" LOC = \"J9\" ; #Bank 34\n#NET \"sys_clk_n\" LOC = \"H9\" ; #Bank 34\n#Bank 34\nNET \"clk_ref_p\" LOC = J9;\n#Bank 34\nNET \"clk_ref_n\" LOC = H9;\n#NET \"sda\" LOC = \"F9\" ; #Bank 34\n#NET \"scl\" LOC = \"F10\" ; #Bank 34\n#Bank 34\nNET \"sys_rst\" LOC = H10;\n#Bank 34\nNET \"dfi_init_complete\" LOC = AC22;\nNET \"dfi_init_complete\" IOSTANDARD = LVCMOS25;\nNET \"processing_iseq\" LOC = AC24;\nNET \"processing_iseq\" IOSTANDARD = LVCMOS25;\nNET \"iq_full\" LOC = AE22;\nNET \"iq_full\" IOSTANDARD = LVCMOS25;\nNET \"rdback_fifo_empty\" LOC = AE23;\nNET \"rdback_fifo_empty\" IOSTANDARD = LVCMOS25;\n#Bank 26\nNET \"ddr_dqs_p[0]\" LOC = D12;\n#Bank 26\nNET \"ddr_dqs_n[0]\" LOC = E12;\n#Bank 26\nNET \"ddr_dqs_p[1]\" LOC = H12;\n#Bank 26\nNET \"ddr_dqs_n[1]\" LOC = J12;\n#Bank 26\nNET \"ddr_dqs_p[2]\" LOC = A13;\n#Bank 26\nNET \"ddr_dqs_n[2]\" LOC = A14;\n#Bank 36\nNET \"ddr_dqs_p[3]\" LOC = H19;\n#Bank 36\nNET \"ddr_dqs_n[3]\" LOC = H20;\n#Bank 36\nNET \"ddr_dqs_p[4]\" LOC = B23;\n#Bank 36\nNET \"ddr_dqs_n[4]\" LOC = C23;\n#Bank 36\nNET \"ddr_dqs_p[5]\" LOC = B25;\n#Bank 36\nNET \"ddr_dqs_n[5]\" LOC = A25;\n#Bank 35\nNET \"ddr_dqs_p[6]\" LOC = H27;\n#Bank 35\nNET \"ddr_dqs_n[6]\" LOC = G28;\n#Bank 35\nNET \"ddr_dqs_p[7]\" LOC = C30;\n#Bank 35\nNET \"ddr_dqs_n[7]\" LOC = D30;\n#Bank 25\nNET \"ddr_ck_p[0]\" LOC = G18;\n#Bank 25\nNET \"ddr_ck_n[0]\" LOC = H18;\n#Bank 25\nNET \"ddr_ck_p[1]\" LOC = K16;\n#Bank 25\nNET \"ddr_ck_n[1]\" LOC = L16;\n\nNET \"ddr_dm[0]\" LOC = E11;\n#Bank 35\nNET \"ddr_dm[1]\" LOC = B11;\n#Bank 35\nNET \"ddr_dm[2]\" LOC = E14;\n#Bank 26\nNET \"ddr_dm[3]\" LOC = D19;\n#Bank 26\nNET \"ddr_dm[4]\" LOC = B22;\n#Bank 25\nNET \"ddr_dm[5]\" LOC = A26;\n#Bank 25\nNET \"ddr_dm[6]\" LOC = A29;\n#Bank 25\nNET \"ddr_dm[7]\" LOC = A31;\n\n\n#CONFIG INTERNAL_VREF_BANK26=0.75;\n#CONFIG INTERNAL_VREF_BANK35=0.75;\n#CONFIG INTERNAL_VREF_BANK36=0.75;\n\n##################################################################################################\n##The following locations must be reserved and cannot be used for external I/O because ##\n##the I/O elements associated with these sites (IODELAY, OSERDES, and associated routing) ##\n##are used to generate and route the clocks necessary for read data capture and synchronization ##\n##to the core clock domain. These pins should not be routed out on the user's PCB ##\n##################################################################################################\n\n##################################################################################################\n##The logic of this pin is used internally to drive a BUFR in the column. This chosen pin must ##\n##be a clock pin capable of spanning to all of the banks containing data bytes in the particular##\n##column. That is, all byte groups must be within +/- 1 bank of this pin. This pin cannot be ##\n##used for other functions and should not be connected externally. If a different pin is chosen,##\n##he corresponding LOC constraint must also be changed. ##\n##################################################################################################\n\nCONFIG PROHIBIT = H22;\nCONFIG PROHIBIT = F21;\nCONFIG PROHIBIT = B20;\nCONFIG PROHIBIT = F19;\nCONFIG PROHIBIT = C13;\nCONFIG PROHIBIT = M12;\nCONFIG PROHIBIT = L13;\nCONFIG PROHIBIT = K14;\nCONFIG PROHIBIT = F25;\nCONFIG PROHIBIT = C29;\nCONFIG PROHIBIT = C28;\nCONFIG PROHIBIT = D24;\n\n######################################################################################\n##Place RSYNC OSERDES and IODELAY: ##\n######################################################################################\n\n##Site: D24 -- Bank 25\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync\" LOC = OLOGIC_X2Y139;\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync\" LOC = IODELAY_X2Y139;\n\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync\" LOC = BUFR_X2Y6;\n\n##Site: M12 -- Bank 35\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync\" LOC = OLOGIC_X1Y139;\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync\" LOC = IODELAY_X1Y139;\n\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync\" LOC = BUFR_X1Y6;\n\n##################################################################################################\n##The logic of this pin is used internally to drive a BUFIO for the byte group. Any clock ##\n##capable pin in the same bank as the data byte group (DQS, DQ, DM if used) can be used for ##\n##this pin. This pin cannot be used for other functions and should not be connected externally. ##\n##If a different pin is chosen, the corresponding LOC constraint must also be changed. ##\n##################################################################################################\n\nCONFIG PROHIBIT = B20,C13,C28,D24,F21,F25,K14,L13;\n\n######################################################################################\n##Place CPT OSERDES and IODELAY: ##\n######################################################################################\n\n##Site: B20 -- Bank 26\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt\" LOC = OLOGIC_X2Y137;\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt\" LOC = IODELAY_X2Y137;\n\n##Site: F21 -- Bank 26\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt\" LOC = OLOGIC_X2Y141;\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt\" LOC = IODELAY_X2Y141;\n\n##Site: H19 -- Bank 26\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt\" LOC = OLOGIC_X2Y143;\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt\" LOC = IODELAY_X2Y143;\n\n##Site: K16 -- Bank 36\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt\" LOC = OLOGIC_X1Y179;\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt\" LOC = IODELAY_X1Y179;\n\n##Site: L15 -- Bank 36\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt\" LOC = OLOGIC_X1Y181;\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_odelay_cpt\" LOC = IODELAY_X1Y181;\n\n##Site: A16 -- Bank 36\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt\" LOC = OLOGIC_X1Y137;\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_odelay_cpt\" LOC = IODELAY_X1Y137;\n\n##Site: K14 -- Bank 35\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt\" LOC = OLOGIC_X1Y141;\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_odelay_cpt\" LOC = IODELAY_X1Y141;\n\n##Site: L13 -- Bank 35\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt\" LOC = OLOGIC_X1Y143;\nINST \"xil_phy/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_odelay_cpt\" LOC = IODELAY_X1Y143;\n\n\n######################################################################################\n## MMCM_ADV CONSTRAINTS ##\n######################################################################################\n\n#Banks 15, 25, 35\nINST \"u_infrastructure/u_mmcm_adv\" LOC = MMCM_ADV_X0Y8;\n\n##########################################\n## PCIE Constraints\n##########################################\n###############################################################################\n# Define Device, Package And Speed Grade\n###############################################################################\n\nCONFIG PART = xc6vlx240t-ff1156-1;\n\n###############################################################################\n# User Time Names / User Time Groups / Time Specs\n###############################################################################\n\n###############################################################################\n# User Physical Constraints\n###############################################################################\n\n\n###############################################################################\n# Pinout and Related I/O Constraints\n###############################################################################\n\n#\n# SYS reset (input) signal. The sys_reset_n signal should be\n# obtained from the PCI Express interface if possible. For\n# slot based form factors, a system reset signal is usually\n# present on the connector. For cable based form factors, a\n# system reset signal may not be available. In this case, the\n# system reset signal must be generated locally by some form of\n# supervisory circuit. You may change the IOSTANDARD and LOC\n# to suit your requirements and VCCO voltage banking rules.\n#\n\nNET \"sys_reset_n\" TIG;\nNET \"sys_reset_n\" NODELAY = \"TRUE\";\nNET \"sys_reset_n\" LOC = AE13;\nNET \"sys_reset_n\" IOSTANDARD = LVCMOS25;\nNET \"sys_reset_n\" PULLUP;\n\n#\n#\n# SYS clock 250 MHz (input) signal. The sys_clk_p and sys_clk_n\n# signals are the PCI Express reference clock. Virtex-6 GT\n# Transceiver architecture requires the use of a dedicated clock\n# resources (FPGA input pins) associated with each GT Transceiver.\n# To use these pins an IBUFDS primitive (refclk_ibuf) is\n# instantiated in user's design.\n# Please refer to the Virtex-6 GT Transceiver User Guide\n# (UG) for guidelines regarding clock resource selection.\n#\n\n#NET \"sys_clk_p\" LOC = V6;\n#NET \"sys_clk_n\" LOC = V5;\nINST \"i_pcie_top/refclk_ibuf\" LOC = IBUFDS_GTXE1_X0Y6;\n\n#\n# Transceiver instance placement. This constraint selects the\n# transceivers to be used, which also dictates the pinout for the\n# transmit and receive differential pairs. Please refer to the\n# Virtex-6 GT Transceiver User Guide (UG) for more information.\n#\n\n# PCIe Lane 0\nINST \"i_pcie_top/core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[0].GTX\" LOC = GTXE1_X0Y15;\n\n# PCIe Lane 1\nINST \"i_pcie_top/core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[1].GTX\" LOC = GTXE1_X0Y14;\n\n# PCIe Lane 2\nINST \"i_pcie_top/core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[2].GTX\" LOC = GTXE1_X0Y13;\n\n# PCIe Lane 3\nINST \"i_pcie_top/core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[3].GTX\" LOC = GTXE1_X0Y12;\n\n# PCIe Lane 4\nINST \"i_pcie_top/core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[4].GTX\" LOC = GTXE1_X0Y11;\n\n# PCIe Lane 5\nINST \"i_pcie_top/core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[5].GTX\" LOC = GTXE1_X0Y10;\n\n# PCIe Lane 6\nINST \"i_pcie_top/core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[6].GTX\" LOC = GTXE1_X0Y9;\n\n# PCIe Lane 7\nINST \"i_pcie_top/core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[7].GTX\" LOC = GTXE1_X0Y8;\n\n\n\n\n#\n# PCI Express Block placement. This constraint selects the PCI Express\n# Block to be used.\n#\n\nINST \"i_pcie_top/core/pcie_2_0_i/pcie_block_i\" LOC = PCIE_X0Y1;\n\n#NET \"led_0\" LOC = \"AC22\" ;\n#NET \"led_1\" LOC = \"AC24\" ;\n#NET \"led_2\" LOC = \"AE22\" ;\n\n#\n# MMCM Placment. This constraint selects the MMCM Placement\n#\nINST \"i_pcie_top/core/pcie_clocking_i/mmcm_adv_i\" LOC = MMCM_ADV_X0Y7;\n\n\n###############################################################################\n# Timing Constraints\n###############################################################################\n\n#\n# Timing requirements and related constraints.\n#\n\nNET \"i_pcie_top/sys_clk_c\" TNM_NET = \"SYSCLK\";\nNET \"i_pcie_top/core*/pcie_clocking_i/clk_125\" TNM_NET = \"CLK_125\";\nNET \"i_pcie_top/core*/TxOutClk_bufg\" TNM_NET = \"TXOUTCLKBUFG\";\nNET \"i_pcie_top/core*/pcie_clocking_i/clk_250\" TNM_NET = \"CLK_250\";\n\nTIMESPEC TS_SYSCLK = PERIOD \"SYSCLK\" 250 MHz HIGH 50 %;\nTIMESPEC TS_CLK_125 = PERIOD \"CLK_125\" TS_SYSCLK / 2 HIGH 50 % PRIORITY 100;\nTIMESPEC TS_TXOUTCLKBUFG = PERIOD \"TXOUTCLKBUFG\" 250 MHz HIGH 50 % PRIORITY 100;\nTIMESPEC TS_CLK_250 = PERIOD \"CLK_250\" TS_SYSCLK * 1 HIGH 50 % PRIORITY 1;\n\n\nPIN \"i_pcie_top/core*/trn_reset_n_int_i.CLR\" TIG;\nPIN \"i_pcie_top/core*/trn_reset_n_i.CLR\" TIG;\nPIN \"i_pcie_top/core*/pcie_clocking_i/mmcm_adv_i.RST\" TIG;\n\nTIMESPEC TS_RESETN = FROM FFS TO FFS(\"i_pcie_top/user_reset_n_i\") 8 ns;\n\n\n###############################################################################\n# Physical Constraints\n###############################################################################\n\n###############################################################################\n# End\n###############################################################################\n" }, { "path": "hw/boards/ML605/softMC_pcie_app.v", "content": "`timescale 1ns / 1ps\n\nmodule softMC_pcie_app #(\n\tparameter C_PCI_DATA_WIDTH = 9'd32, DQ_WIDTH = 64\n)(\n\tinput clk,\n\tinput rst,\n\toutput CHNL_RX_CLK, \n\tinput CHNL_RX, \n\toutput reg CHNL_RX_ACK, \n\tinput CHNL_RX_LAST, \n\tinput [31:0] CHNL_RX_LEN, \n\tinput [30:0] CHNL_RX_OFF, \n\tinput [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA, \n\tinput CHNL_RX_DATA_VALID, \n\toutput CHNL_RX_DATA_REN,\n\t\n\toutput CHNL_TX_CLK, \n\toutput reg CHNL_TX, \n\tinput CHNL_TX_ACK, \n\toutput CHNL_TX_LAST, \n\toutput reg [31:0] CHNL_TX_LEN, \n\toutput [30:0] CHNL_TX_OFF, \n\toutput [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA, \n\toutput reg CHNL_TX_DATA_VALID, \n\tinput CHNL_TX_DATA_REN,\n\t\n\toutput app_en,\n\tinput app_ack,\n\toutput[31:0] app_instr,\n\t\n\t//Data read back Interface\n\tinput rdback_fifo_empty,\n\toutput rdback_fifo_rden,\n\tinput[DQ_WIDTH*4 - 1:0] rdback_data\n );\n \n assign CHNL_RX_CLK = clk;\n assign CHNL_TX_CLK = clk;\n assign CHNL_TX_OFF = 0;\n assign CHNL_TX_LAST = 1'd1;\n \n reg app_en_r;\n reg[C_PCI_DATA_WIDTH-1:0] rx_data_r;\n \n reg old_chnl_rx;\n reg pending_ack = 0;\n \n //always acknowledge transaction\n always@(posedge clk) begin\n\t\told_chnl_rx <= CHNL_RX;\n\t\t\n\t\tif(~old_chnl_rx & CHNL_RX)\n\t\t\tpending_ack <= 1'b1;\n\t\t\n\t\tif(CHNL_RX_ACK)\n\t\t\tCHNL_RX_ACK <= 1'b0;\n\t\telse begin\n\t\t\tif(pending_ack /*& app_ack*/) begin\n\t\t\t\tCHNL_RX_ACK <= 1'b1;\n\t\t\t\tpending_ack <= 1'b0;\n\t\t\tend\n\t\tend\n end\n \n //register incoming data\n assign CHNL_RX_DATA_REN = ~app_en_r | app_ack;\n always@(posedge clk) begin\n\tif(~app_en_r | app_ack) begin\n\t\tapp_en_r <= CHNL_RX_DATA_VALID;\n\t\trx_data_r <= CHNL_RX_DATA;\n\tend\n end\n \n//send to the MC\nassign app_en = app_en_r;\nassign app_instr = rx_data_r;\n\n//SEND DATA TO HOST\nlocalparam RECV_IDLE = 1'b0;\nlocalparam RECV_BUSY = 1'b1;\n\nreg sender_ack;\nreg[DQ_WIDTH*4 - 1:0] send_data_r;\n\nreg recv_state = RECV_IDLE;\nassign rdback_fifo_rden = (recv_state == RECV_IDLE);\nalways@(posedge clk) begin\n\tif(rst) begin\n\t\trecv_state <= RECV_IDLE;\n\tend\n\telse begin\n\t\tcase(recv_state)\n\t\t\tRECV_IDLE: begin\n\t\t\t\tif(~rdback_fifo_empty) begin\n\t\t\t\t\tsend_data_r <= rdback_data;\n\t\t\t\t\trecv_state <= RECV_BUSY;\n\t\t\t\tend\n\t\t\tend //RECV_IDLE\n\t\t\t\n\t\t\tRECV_BUSY: begin\n\t\t\t\tif(sender_ack)\n\t\t\t\t\trecv_state <= RECV_IDLE;\n\t\t\tend //RECV_BUSY\n\t\tendcase\n\tend\nend\n\nreg[2:0] sender_state = 0; //edit this if DQ_WIDTH or C_PCI_DATA_WIDTH changes\nreg[2:0] sender_state_ns;\n\nalways@* begin\n\tsender_ack = 1'b0;\n\tsender_state_ns = sender_state;\n\tCHNL_TX = sender_state[2];\n\t\n\tCHNL_TX_LEN = 16;\n\t\n\tif(recv_state == RECV_BUSY) begin\n\t\tCHNL_TX = 1'b1;\n\t\tCHNL_TX_DATA_VALID = 1'b1;\n\t\t\n\t\tif(CHNL_TX_DATA_REN) begin\n\t\t\tsender_state_ns = sender_state + 3'd1;\n\t\t\t\n\t\t\tif(sender_state[1:0] == 2'b11)\n\t\t\t\tsender_ack = 1'b1;\n\t\tend\n\tend\nend\n\nalways@(posedge clk) begin\n\tif(rst) begin\n\t\tsender_state <= 0;\n\tend\n\telse begin\n\t\tsender_state <= sender_state_ns;\n\tend\nend\n\nwire[7:0] offset = {6'd0, sender_state[1:0]} << 6;\nassign CHNL_TX_DATA = send_data_r[offset +: 64];\n\nendmodule\n" }, { "path": "hw/boards/ML605/softMC_top.v", "content": "`timescale 1ps / 1ps\n\n`include \"softMC.inc\"\n\nmodule softMC_top #\n (\n\tparameter TCQ = 100,\n\tparameter tCK = 2500, //ps, TODO: let memory clok be 400 Mhz for now\n\tparameter nCK_PER_CLK = 2, // # of memory clocks per CLK\n\tparameter REFCLK_FREQ = 200.0, // IODELAY Reference Clock freq (MHz)\n\tparameter DRAM_TYPE = \"DDR3\", // Memory I/F type: \"DDR3\", \"DDR2\"\n\tparameter RST_ACT_LOW = 0,\n\tparameter INPUT_CLK_TYPE = \"DIFFERENTIAL\",\n\n\tparameter CLKFBOUT_MULT_F =6,\n\tparameter DIVCLK_DIVIDE = 1,\n\tparameter CLKOUT_DIVIDE = 3,\n\t \n\t// Slot Conifg parameters\n\tparameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,\n\tparameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,\n // DRAM bus widths\n parameter BANK_WIDTH = 3, // # of bank bits\n parameter CK_WIDTH = 2, // # of CK/CK# outputs to memory\n parameter COL_WIDTH = 10, // column address width\n parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank\n parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))\n parameter DQ_WIDTH = 64, // # of DQ (data)\n parameter DM_WIDTH = 8, // # of DM (data mask)\n parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))\n parameter DQS_WIDTH = 8, // # of DQS (strobe)\n parameter DRAM_WIDTH = 8, // # of DQ per DQS\n parameter ROW_WIDTH = 16, // DRAM address bus width\n parameter RANK_WIDTH = 1, // log2(CS_WIDTH)\n parameter CS_WIDTH = 1, // # of DRAM ranks\n parameter CKE_WIDTH = 1, // # of cke outputs \n parameter CAL_WIDTH = \"HALF\", // # of DRAM ranks to be calibrated\n // CAL_WIDTH = CS_WIDTH when \"FULL\"\n // CAL_WIDTH = CS_WIDTH/2 when \"HALF\" \n // calibration Address. The address given below will be used for calibration\n // read and write operations. \n parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address\n parameter CALIB_COL_ADD = 12'h000, // Calibration column address\n parameter CALIB_BA_ADD = 3'h0, // Calibration bank address \n // DRAM mode settings\n parameter AL = \"0\", // Additive Latency option\n parameter BURST_MODE = \"8\", // Burst length\n parameter BURST_TYPE = \"SEQ\", // Burst type\n parameter nAL = 0, // Additive latency (in clk cyc)\n parameter nCL = 5, // Read CAS latency (in clk cyc)\n parameter nCWL = 5, // Write CAS latency (in clk cyc)\n parameter tRFC = 110000, // Refresh-to-command delay\n parameter OUTPUT_DRV = \"HIGH\", // DRAM reduced output drive option\n parameter REG_CTRL = \"OFF\", // \"ON\" for registered DIMM\n parameter RTT_NOM = \"60\", // ODT Nominal termination value\n parameter RTT_WR = \"OFF\", // ODT Write termination value\n parameter WRLVL = \"ON\", // Enable write leveling\n // Phase Detector/Read Leveling options\n parameter PHASE_DETECT = \"ON\", // Enable read phase detector\n parameter PD_TAP_REQ = 0, // # of IODELAY taps reserved for PD\n parameter PD_MSB_SEL = 8, // # of bits in PD response cntr\n parameter PD_DQS0_ONLY = \"ON\", // Enable use of DQS[0] only for\n // phase detector\n parameter PD_LHC_WIDTH = 16, // sampling averaging cntr widths \n parameter PD_CALIB_MODE = \"PARALLEL\", // parallel/seq PD calibration\n // IODELAY/BUFFER options\n parameter IBUF_LPWR_MODE = \"OFF\", // Input buffer low power mode\n parameter IODELAY_HP_MODE = \"ON\", // IODELAY High Performance Mode\n parameter IODELAY_GRP = \"IODELAY_MIG\", // May be assigned unique name\n // when mult IP cores in design\n // Pin-out related parameters\n parameter nDQS_COL0 = 3, // # DQS groups in I/O column #1\n parameter nDQS_COL1 = 5, // # DQS groups in I/O column #2\n parameter nDQS_COL2 = 0, // # DQS groups in I/O column #3\n parameter nDQS_COL3 = 0, // # DQS groups in I/O column #4\n parameter DQS_LOC_COL0 = 24'h020100,\n // DQS grps in col #1\n parameter DQS_LOC_COL1 = 40'h0706050403, // DQS grps in col #2\n parameter DQS_LOC_COL2 = 0, // DQS grps in col #3\n parameter DQS_LOC_COL3 = 0, // DQS grps in col #4\n parameter USE_DM_PORT = 0, // DM instantation enable\n // Simulation /debug options\n parameter SIM_BYPASS_INIT_CAL = \"NONE\", \n // Parameter used to force skipping\n // or abbreviation of initialization\n // and calibration. Overrides\n // SIM_INIT_OPTION, SIM_CAL_OPTION,\n // and disables various other blocks\n parameter SIM_INIT_OPTION = \"NONE\", // Skip various initialization steps\n parameter SIM_CAL_OPTION = \"NONE\", // Skip various calibration steps\n parameter DEBUG_PORT = \"OFF\", // Enable debug port\n\t\n\tparameter SIMULATION = \"OFF\"\n )(\n\tinput sys_clk_p,\n\tinput sys_clk_n,\n\tinput clk_ref_p,\n\tinput clk_ref_n,\n\tinput sys_rst,\n\tinput sys_reset_n,\n\t// DDRx Output Interface\n\toutput [CK_WIDTH-1:0] ddr_ck_p,\n\toutput [CK_WIDTH-1:0] ddr_ck_n,\n\toutput [ROW_WIDTH-1:0] ddr_addr,\n\toutput [BANK_WIDTH-1:0] ddr_ba,\n\toutput ddr_ras_n,\n\toutput ddr_cas_n,\n\toutput ddr_we_n,\n\toutput [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,\n\toutput [CKE_WIDTH-1:0] ddr_cke,\n\toutput [CS_WIDTH*nCS_PER_RANK-1:0] ddr_odt,\n\toutput ddr_reset_n,\n\t//output ddr_parity,\n\toutput [DM_WIDTH-1:0] ddr_dm,\n\tinout [DQS_WIDTH-1:0] ddr_dqs_p,\n\tinout [DQS_WIDTH-1:0] ddr_dqs_n,\n\tinout [DQ_WIDTH-1:0] ddr_dq,\n\n\toutput dfi_init_complete, //led 0\n\toutput\t\t\t\t\t\t\t\t\t\tprocessing_iseq, //led 1\n\toutput \t\t\t\t\t\t\t\t\t\tiq_full, //led 2\n\toutput \t\t\t\t\t\t\t\t\t\trdback_fifo_empty, //led 3\n\t\n\t//PCIE\n\t\n\t`ifndef SIM //we dont want to simulate PCIe core\n\t\n\toutput [7:0] pci_exp_txp,\n\toutput [7:0] pci_exp_txn,\n\tinput [7:0] pci_exp_rxp,\n\tinput [7:0] pci_exp_rxn\n \n\t`else\n\n\tinput app_en,\n\toutput app_ack,\n\tinput[31:0] app_instr,\n\n\t//Data read back Interface\n\t//output rdback_fifo_empty,\n\tinput rdback_fifo_rden,\n\toutput[DQ_WIDTH*4 - 1:0] rdback_data\n\n\t`endif //SIM\n );\n\t \n\t assign ddr_dm = {DM_WIDTH{1'b0}};\n\t \n\t /*** CLOCK MANAGEMENT ***/\n\t \n\t localparam SYSCLK_PERIOD = tCK * nCK_PER_CLK;\n\t localparam MMCM_ADV_BANDWIDTH = \"OPTIMIZED\";\n\t \n\t wire clk_mem, clk, clk_rd_base;\n\t wire clk_ref = 0;\n\t wire rst;\n\t wire pd_PSDONE, pd_PSEN, pd_PSINCDEC; //phase detector interface\n\t wire iodelay_ctrl_rdy;\n\t wire mmcm_clk;\n\t wire sys_clk = 0;\n\t \n\t //use 200MHZ refrence clock to generate mmcm_clk\n\t iodelay_ctrl #\n (\n .TCQ (TCQ),\n .IODELAY_GRP (IODELAY_GRP),\n .INPUT_CLK_TYPE (INPUT_CLK_TYPE),\n .RST_ACT_LOW (RST_ACT_LOW)\n )\n u_iodelay_ctrl\n (\n .clk_ref_p (clk_ref_p), //input\n .clk_ref_n (clk_ref_n), //input\n .clk_ref (clk_ref), //input\n .sys_rst (sys_rst), //input\n\t\t .clk_200\t\t\t(mmcm_clk),\n .iodelay_ctrl_rdy (iodelay_ctrl_rdy) //output\n );\n\t\t \n\t infrastructure #\n (\n .TCQ (TCQ),\n .CLK_PERIOD (SYSCLK_PERIOD),\n .nCK_PER_CLK (nCK_PER_CLK),\n .MMCM_ADV_BANDWIDTH (MMCM_ADV_BANDWIDTH),\n .CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),\n .DIVCLK_DIVIDE (DIVCLK_DIVIDE),\n .CLKOUT_DIVIDE (CLKOUT_DIVIDE),\n .RST_ACT_LOW (RST_ACT_LOW)\n )\n u_infrastructure\n (\n .clk_mem (clk_mem), //output\n .clk (clk), //output\n .clk_rd_base (clk_rd_base), //output\n .rstdiv0 (rst), //output\n\t\t \n .mmcm_clk (mmcm_clk), //input\n .sys_rst (sys_rst), //input\n .iodelay_ctrl_rdy (iodelay_ctrl_rdy), //input\n .PSDONE (pd_PSDONE), //output\n .PSEN (pd_PSEN), //input\n .PSINCDEC (pd_PSINCDEC) //input\n );\n\t\t \n\t\t \n wire [ROW_WIDTH-1:0] dfi_address0;\n wire [ROW_WIDTH-1:0] dfi_address1;\n wire [BANK_WIDTH-1:0] dfi_bank0;\n wire [BANK_WIDTH-1:0] dfi_bank1;\n wire \t\t\t\t\t\t\t\t\t\t dfi_cas_n0;\n wire \t\t\t\t\t\t\t\t\t\t dfi_cas_n1;\n wire [CKE_WIDTH-1:0] dfi_cke0;\n wire [CKE_WIDTH-1:0] dfi_cke1;\n wire [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n0;\n wire [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n1;\n wire [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt0;\n wire [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt1;\n wire dfi_ras_n0;\n wire dfi_ras_n1;\n wire dfi_reset_n;\n\tassign dfi_reset_n = 1;\n wire dfi_we_n0;\n wire dfi_we_n1;\n // DFI Write\n wire dfi_wrdata_en;\n wire [4*DQ_WIDTH-1:0] dfi_wrdata;\n wire [4*(DQ_WIDTH/8)-1:0] dfi_wrdata_mask;\n // DFI Read\n wire dfi_rddata_en;\n\twire \t\t\t\t\t\t\t\t\t\t dfi_rddata_en_even;\n\twire \t\t\t\t\t\t\t\t\t\t dfi_rddata_en_odd;\n wire [4*DQ_WIDTH-1:0] dfi_rddata;\n wire dfi_rddata_valid;\n wire dfi_rddata_valid_even;\n wire dfi_rddata_valid_odd;\n\n // DFI Initialization Status / CLK Disable\n wire dfi_dram_clk_disable;\n // sideband signals\n wire io_config_strobe;\n wire [RANK_WIDTH:0] io_config;\n\t \n\t localparam CLK_PERIOD = tCK * nCK_PER_CLK;\n\t phy_top #(\n .TCQ (TCQ),\n .REFCLK_FREQ (REFCLK_FREQ),\n .nCS_PER_RANK (nCS_PER_RANK),\n .CAL_WIDTH (CAL_WIDTH),\n .CALIB_ROW_ADD (CALIB_ROW_ADD),\n .CALIB_COL_ADD (CALIB_COL_ADD),\n .CALIB_BA_ADD (CALIB_BA_ADD),\n .CS_WIDTH (CS_WIDTH),\n .nCK_PER_CLK (nCK_PER_CLK),\n .CKE_WIDTH (CKE_WIDTH),\n .DRAM_TYPE (DRAM_TYPE),\n .SLOT_0_CONFIG (SLOT_0_CONFIG),\n .SLOT_1_CONFIG (SLOT_1_CONFIG),\n .CLK_PERIOD (CLK_PERIOD),\n .BANK_WIDTH (BANK_WIDTH),\n .CK_WIDTH (CK_WIDTH),\n .COL_WIDTH (COL_WIDTH),\n .DM_WIDTH (DM_WIDTH),\n .DQ_CNT_WIDTH (DQ_CNT_WIDTH),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_WIDTH (DRAM_WIDTH),\n .ROW_WIDTH (ROW_WIDTH),\n .RANK_WIDTH (RANK_WIDTH),\n .AL (AL),\n .BURST_MODE (BURST_MODE),\n .BURST_TYPE (BURST_TYPE),\n .nAL (nAL),\n .nCL (nCL),\n .nCWL (nCWL),\n .tRFC (tRFC),\n .OUTPUT_DRV (OUTPUT_DRV),\n .REG_CTRL (REG_CTRL),\n .RTT_NOM (RTT_NOM),\n .RTT_WR (RTT_WR),\n .WRLVL (WRLVL),\n .PHASE_DETECT (PHASE_DETECT),\n .IODELAY_HP_MODE (IODELAY_HP_MODE),\n .IODELAY_GRP (IODELAY_GRP),\n // Prevent the following simulation-related parameters from\n // being overridden for synthesis - for synthesis only the\n // default values of these parameters should be used\n // synthesis translate_off\n .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),\n\t .SIM_INIT_OPTION(SIM_INIT_OPTION),\n\t .SIM_CAL_OPTION(SIM_CAL_OPTION),\n\t \n // synthesis translate_on\n .nDQS_COL0 (nDQS_COL0),\n .nDQS_COL1 (nDQS_COL1),\n .nDQS_COL2 (nDQS_COL2),\n .nDQS_COL3 (nDQS_COL3),\n .DQS_LOC_COL0 (DQS_LOC_COL0),\n .DQS_LOC_COL1 (DQS_LOC_COL1),\n .DQS_LOC_COL2 (DQS_LOC_COL2),\n .DQS_LOC_COL3 (DQS_LOC_COL3),\n .USE_DM_PORT (USE_DM_PORT),\n .DEBUG_PORT (DEBUG_PORT)\n ) xil_phy (\n .clk_mem(clk_mem), //input\n .clk(clk), //input\n .clk_rd_base(clk_rd_base), //input\n .rst(rst), //input\n .slot_0_present(SLOT_0_CONFIG), //input\n .slot_1_present(SLOT_1_CONFIG), //input\n\t \n .dfi_address0(dfi_address0), //Note: '0' versions are used for row commands, '1' versions for column commands\n .dfi_address1(dfi_address1), \n .dfi_bank0(dfi_bank0), \n .dfi_bank1(dfi_bank1), \n .dfi_cas_n0(dfi_cas_n0), \n .dfi_cas_n1(dfi_cas_n1), \n .dfi_cke0(dfi_cke0), \n .dfi_cke1(dfi_cke1), \n .dfi_cs_n0(dfi_cs_n0), \n .dfi_cs_n1(dfi_cs_n1), \n .dfi_odt0(dfi_odt0), \n .dfi_odt1(dfi_odt1), \n .dfi_ras_n0(dfi_ras_n0), \n .dfi_ras_n1(dfi_ras_n1), \n .dfi_reset_n(dfi_reset_n), \n .dfi_we_n0(dfi_we_n0), \n .dfi_we_n1(dfi_we_n1), \n .dfi_wrdata_en(dfi_wrdata_en), \n .dfi_wrdata(dfi_wrdata), \n .dfi_wrdata_mask(dfi_wrdata_mask), \n .dfi_rddata_en(dfi_rddata_en), \n\t .dfi_rddata_en_even(dfi_rddata_en_even),\n\t .dfi_rddata_en_odd(dfi_rddata_en_odd),\n .dfi_rddata(dfi_rddata), \n .dfi_rddata_valid(dfi_rddata_valid), \n\t .dfi_rddata_valid_even(dfi_rddata_valid_even),\n .dfi_rddata_valid_odd(dfi_rddata_valid_odd), \n .dfi_dram_clk_disable(dfi_dram_clk_disable), \n .dfi_init_complete(dfi_init_complete), \n\t \n\t //sideband signals\n .io_config_strobe(io_config_strobe), //input\n .io_config(io_config), //input [RANK_WIDTH:0]\n\t \n\t //DRAM signals\n .ddr_ck_p(ddr_ck_p), \n .ddr_ck_n(ddr_ck_n), \n .ddr_addr(ddr_addr), \n .ddr_ba(ddr_ba), \n .ddr_ras_n(ddr_ras_n), \n .ddr_cas_n(ddr_cas_n), \n .ddr_we_n(ddr_we_n), \n .ddr_cs_n(ddr_cs_n), \n .ddr_cke(ddr_cke), \n .ddr_odt(ddr_odt), \n .ddr_reset_n(ddr_reset_n), \n //.ddr_parity(ddr_parity), \n .ddr_dm(ddr_dm), \n .ddr_dqs_p(ddr_dqs_p), \n .ddr_dqs_n(ddr_dqs_n), \n .ddr_dq(ddr_dq), \n\t \n\t //phase detection signals\n .pd_PSDONE(pd_PSDONE), \n .pd_PSEN(pd_PSEN), \n .pd_PSINCDEC(pd_PSINCDEC)\n );\n\t \n\t //App Command Interface\n\t `ifndef SIM\n\twire app_en;\n\twire app_ack;\n\twire[31:0] app_instr;\n\t\n\t\n\t//Data read back Interface\n\twire rdback_fifo_rden;\n\twire[DQ_WIDTH*4 - 1:0] rdback_data;\n\t`endif //SIM\n\t\n\t\n\t softMC #(.TCQ(TCQ), .tCK(tCK), .nCK_PER_CLK(nCK_PER_CLK), .RANK_WIDTH(RANK_WIDTH), .ROW_WIDTH(ROW_WIDTH), .BANK_WIDTH(BANK_WIDTH), \n\t\t\t\t\t\t\t\t.CKE_WIDTH(CKE_WIDTH), .CS_WIDTH(CS_WIDTH), .nCS_PER_RANK(nCS_PER_RANK), .DQ_WIDTH(DQ_WIDTH)) i_softmc(\n\t.clk(clk),\n\t.rst(rst),\n\t\n\t//App Command Interface\n\t.app_en(app_en),\n\t.app_ack(app_ack),\n\t.app_instr(app_instr), \n\t.iq_full(iq_full),\n\t.processing_iseq(processing_iseq),\n\t\n\t// DFI Control/Address\n\t.dfi_address0(dfi_address0),\n\t.dfi_address1(dfi_address1),\n\t.dfi_bank0(dfi_bank0),\n\t.dfi_bank1(dfi_bank1),\n\t.dfi_cas_n0(dfi_cas_n0),\n\t.dfi_cas_n1(dfi_cas_n1),\n\t.dfi_cke0(dfi_cke0),\n\t.dfi_cke1(dfi_cke1),\n\t.dfi_cs_n0(dfi_cs_n0),\n\t.dfi_cs_n1(dfi_cs_n1),\n\t.dfi_odt0(dfi_odt0),\n\t.dfi_odt1(dfi_odt1),\n\t.dfi_ras_n0(dfi_ras_n0),\n\t.dfi_ras_n1(dfi_ras_n1),\n\t.dfi_reset_n(dfi_reset_n),\n\t.dfi_we_n0(dfi_we_n0),\n\t.dfi_we_n1(dfi_we_n1),\n\t// DFI Write\n\t.dfi_wrdata_en(dfi_wrdata_en),\n\t.dfi_wrdata(dfi_wrdata),\n\t.dfi_wrdata_mask(dfi_wrdata_mask),\n\t// DFI Read\n\t.dfi_rddata_en(dfi_rddata_en),\n\t.dfi_rddata_en_even(dfi_rddata_en_even),\n\t.dfi_rddata_en_odd(dfi_rddata_en_odd),\n\t.dfi_rddata(dfi_rddata),\n\t.dfi_rddata_valid(dfi_rddata_valid),\n\t.dfi_rddata_valid_even(dfi_rddata_valid_even),\n\t.dfi_rddata_valid_odd(dfi_rddata_valid_odd),\n\t// DFI Initialization Status / CLK Disable\n\t.dfi_dram_clk_disable(dfi_dram_clk_disable),\n\t.dfi_init_complete(dfi_init_complete),\n\t// sideband signals\n\t.io_config_strobe(io_config_strobe),\n\t.io_config(io_config),\n\t\n\t//Data read back Interface\n\t.rdback_fifo_empty(rdback_fifo_empty),\n\t.rdback_fifo_rden(rdback_fifo_rden),\n\t.rdback_data(rdback_data)\n);\n\n`ifndef SIM\n\nriffa_top_v6_pcie_v2_5 #(\n .C_DATA_WIDTH(64), // RX/TX interface data width\n .DQ_WIDTH(DQ_WIDTH)\n) i_pcie_top\n(\n .pci_exp_txp(pci_exp_txp),\n .pci_exp_txn(pci_exp_txn),\n .pci_exp_rxp(pci_exp_rxp),\n .pci_exp_rxn(pci_exp_rxn),\n\n .sys_clk_p(sys_clk_p),\n .sys_clk_n(sys_clk_n),\n .sys_reset_n(sys_reset_n),\n \n\t.app_clk(clk),\n\t.app_en(app_en),\n\t.app_ack(app_ack),\n\t.app_instr(app_instr),\n\t\n\t//Data read back Interface\n\t.rdback_fifo_empty(rdback_fifo_empty),\n\t.rdback_fifo_rden(rdback_fifo_rden),\n\t.rdback_data(rdback_data)\n);\n\n`endif //SIM\n\nendmodule\n" }, { "path": "hw/boards/ML605/tb_softMC_top.v", "content": "`timescale 1ps / 1ps\n\n`include \"softMC.inc\"\n\nmodule tb_softMC_top;\n\t\n parameter REFCLK_FREQ = 200;\n // # = 200 for all design frequencies of\n // -1 speed grade devices\n // = 200 when design frequency < 480 MHz\n // for -2 and -3 speed grade devices.\n // = 300 when design frequency >= 480 MHz\n // for -2 and -3 speed grade devices.\n parameter SIM_BYPASS_INIT_CAL = \"FAST\";\n // # = \"OFF\" - Complete memory init &\n // calibration sequence\n // # = \"SKIP\" - Skip memory init &\n // calibration sequence\n // # = \"FAST\" - Skip memory init & use\n // abbreviated calib sequence\n parameter RST_ACT_LOW = 0;\n // =1 for active low reset,\n // =0 for active fhigh.\n parameter IODELAY_GRP = \"IODELAY_MIG\";\n //to phy_top\n parameter nCK_PER_CLK = 2;\n // # of memory CKs per fabric clock.\n // # = 2, 1.\n parameter nCS_PER_RANK = 1;\n // # of unique CS outputs per Rank for\n // phy.\n parameter DQS_CNT_WIDTH = 3;\n // # = ceil(log2(DQS_WIDTH)).\n parameter RANK_WIDTH = 1;\n // # = ceil(log2(RANKS)).\n parameter BANK_WIDTH = 3;\n // # of memory Bank Address bits.\n parameter CK_WIDTH = 2;\n // # of CK/CK# outputs to memory.\n parameter CKE_WIDTH = 1;\n // # of CKE outputs to memory.\n parameter COL_WIDTH = 10;\n // # of memory Column Address bits.\n parameter CS_WIDTH = 1;\n // # of unique CS outputs to memory.\n parameter DM_WIDTH = 8;\n // # of Data Mask bits.\n parameter DQ_WIDTH = 64;\n // # of Data (DQ) bits.\n parameter DQS_WIDTH = 8;\n // # of DQS/DQS# bits.\n parameter ROW_WIDTH = 15;\n // # of memory Row Address bits.\n parameter BURST_MODE = \"8\";\n // Burst Length (Mode Register 0).\n // # = \"8\", \"4\", \"OTF\".\n parameter INPUT_CLK_TYPE = \"DIFFERENTIAL\";\n // input clock type DIFFERENTIAL or SINGLE_ENDED\n parameter BM_CNT_WIDTH = 2;\n // # = ceil(log2(nBANK_MACHS)).\n parameter ADDR_CMD_MODE = \"1T\" ;\n // # = \"2T\", \"1T\".\n parameter ORDERING = \"STRICT\";\n // # = \"NORM\", \"STRICT\".\n parameter RTT_NOM = \"60\";\n // RTT_NOM (ODT) (Mode Register 1).\n // # = \"DISABLED\" - RTT_NOM disabled,\n // = \"120\" - RZQ/2,\n // = \"60\" - RZQ/4,\n // = \"40\" - RZQ/6.\n parameter RTT_WR = \"OFF\";\n // RTT_WR (ODT) (Mode Register 2).\n // # = \"OFF\" - Dynamic ODT off,\n // = \"120\" - RZQ/2,\n // = \"60\" - RZQ/4,\n parameter OUTPUT_DRV = \"HIGH\";\n // Output Driver Impedance Control (Mode Register 1).\n // # = \"HIGH\" - RZQ/7,\n // = \"LOW\" - RZQ/6.\n parameter REG_CTRL = \"OFF\";\n // # = \"ON\" - RDIMMs,\n // = \"OFF\" - Components, SODIMMs, UDIMMs.\n parameter CLKFBOUT_MULT_F = 6;\n // write PLL VCO multiplier.\n parameter DIVCLK_DIVIDE = 1;\n // write PLL VCO divisor.\n parameter CLKOUT_DIVIDE = 3;\n // VCO output divisor for fast (memory) clocks.\n parameter tCK = 2500;\n // memory tCK paramter.\n // # = Clock Period.\n parameter DEBUG_PORT = \"OFF\";\n // # = \"ON\" Enable debug signals/controls.\n // = \"OFF\" Disable debug signals/controls.\n parameter tPRDI = 1_000_000;\n // memory tPRDI paramter.\n parameter tREFI = 7800000;\n // memory tREFI paramter.\n parameter tZQI = 128_000_000;\n // memory tZQI paramter.\n parameter ADDR_WIDTH = 29;\n // # = RANK_WIDTH + BANK_WIDTH\n // + ROW_WIDTH + COL_WIDTH;\n parameter STARVE_LIMIT = 2;\n // # = 2,3,4.\n parameter TCQ = 100;\n parameter ECC = \"OFF\";\n parameter ECC_TEST = \"OFF\";\n parameter DATA_WIDTH = 64;\n parameter PAYLOAD_WIDTH = (ECC_TEST == \"OFF\") ? DATA_WIDTH : DQ_WIDTH;\n\n\n //***********************************************************************//\n // Traffic Gen related parameters\n //***********************************************************************//\n parameter EYE_TEST = \"FALSE\";\n // set EYE_TEST = \"TRUE\" to probe memory\n // signals. Traffic Generator will only\n // write to one single location and no\n // read transactions will be generated.\n\n parameter SIMULATION = \"TRUE\";\n // PRBS_DATA_MODE can only be used together with either PRBS_ADDR or SEQUENTIAL_ADDR\n // FIXED_DATA_MODE is designed to work with FIXED_ADDR\n parameter ADDR_MODE = 3;\n //FIXED_ADDR = 2'b01;\n //PRBS_ADDR = 2'b10;\n //SEQUENTIAL_ADDR = 2'b11;\n parameter DATA_MODE = 2; // To change simulation data pattern\n // FIXED_DATA_MODE = 4'b0001;\n // ADDR_DATA_MODE = 4'b0010;\n // HAMMER_DATA_MODE = 4'b0011;\n // NEIGHBOR_DATA_MODE = 4'b0100;\n // WALKING1_DATA_MODE = 4'b0101;\n // WALKING0_DATA_MODE = 4'b0110;\n // PRBS_DATA_MODE = 4'b0111;\n parameter TST_MEM_INSTR_MODE = \"R_W_INSTR_MODE\";\n // available instruction modes:\n //\"FIXED_INSTR_R_MODE\"\n // \"FIXED_INSTR_W_MODE\"\n // \"R_W_INSTR_MODE\"\n parameter DATA_PATTERN = \"DGEN_ALL\";\n // DATA_PATTERN shoule be set to \"DGEN_ALL\"\n // unless it is targeted for S6 small device.\n // \"DGEN_HAMMER\", \"DGEN_WALKING1\",\n // \"DGEN_WALKING0\",\"DGEN_ADDR\",\"\n // \"DGEN_NEIGHBOR\",\"DGEN_PRBS\",\"DGEN_ALL\"\n parameter CMD_PATTERN = \"CGEN_ALL\";\n // CMD_PATTERN shoule be set to \"CGEN_ALL\"\n // unless it is targeted for S6 small device.\n // \"CGEN_RPBS\",\"CGEN_FIXED\",\"CGEN_BRAM\",\n // \"CGEN_SEQUENTIAL\", \"CGEN_ALL\"\n\n parameter BEGIN_ADDRESS = 32'h00000000;\n parameter PRBS_SADDR_MASK_POS = 32'h00000000;\n parameter END_ADDRESS = 32'h000003ff;\n parameter PRBS_EADDR_MASK_POS = 32'hfffffc00;\n parameter SEL_VICTIM_LINE = 11;\n\n //**************************************************************************//\n // Local parameters Declarations\n //**************************************************************************//\n localparam real TPROP_DQS = 0.00; // Delay for DQS signal during Write Operation\n localparam real TPROP_DQS_RD = 0.00; // Delay for DQS signal during Read Operation\n localparam real TPROP_PCB_CTRL = 0.00; // Delay for Address and Ctrl signals\n localparam real TPROP_PCB_DATA = 0.00; // Delay for data signal during Write operation\n localparam real TPROP_PCB_DATA_RD = 0.00; // Delay for data signal during Read operation\n\n localparam MEMORY_WIDTH = 8;\n localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;\n localparam real CLK_PERIOD = tCK;\n localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));\n localparam DRAM_DEVICE = \"SODIMM\";\n // DRAM_TYPE: \"UDIMM\", \"RDIMM\", \"COMPS\"\n\n // VT delay change options/settings\n localparam VT_ENABLE = \"OFF\";\n // Enable VT delay var's\n localparam VT_RATE = CLK_PERIOD/500;\n // Size of each VT step\n localparam VT_UPDATE_INTERVAL = CLK_PERIOD*50;\n // Update interval\n localparam VT_MAX = CLK_PERIOD/40;\n // Maximum VT shift\n\n\n function integer STR_TO_INT;\n input [7:0] in;\n begin\n if(in == \"8\")\n STR_TO_INT = 8;\n else if(in == \"4\")\n STR_TO_INT = 4;\n else\n STR_TO_INT = 0;\n end\n endfunction\n\n localparam APP_DATA_WIDTH = PAYLOAD_WIDTH * 4;\n localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;\n localparam BURST_LENGTH = STR_TO_INT(BURST_MODE);\n //**************************************************************************//\n // Wire Declarations\n //**************************************************************************//\n reg app_en;\n wire app_ack;\n reg[31:0] app_instr; \n wire iq_full;\n wire processing_iseq;\n\t\t\n //Data read back Interface\n wire rdback_fifo_empty;\n reg rdback_fifo_rden;\n wire[255:0] rdback_data;\n \n reg sys_clk;\n reg clk_ref;\n reg sys_rst_n;\n\n wire sys_clk_p;\n wire sys_clk_n;\n wire clk_ref_p;\n wire clk_ref_n;\n\n\n reg [DM_WIDTH-1:0] ddr3_dm_sdram_tmp;\n\n wire sys_rst;\n\n wire error;\n wire phy_init_done;\n wire ddr3_parity;\n wire ddr3_reset_n;\n wire sda;\n wire scl;\n\n wire [DQ_WIDTH-1:0] ddr3_dq_fpga;\n wire [ROW_WIDTH-1:0] ddr3_addr_fpga;\n wire [BANK_WIDTH-1:0] ddr3_ba_fpga;\n wire ddr3_ras_n_fpga;\n wire ddr3_cas_n_fpga;\n wire ddr3_we_n_fpga;\n wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_fpga;\n wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_fpga;\n wire [CKE_WIDTH-1:0] ddr3_cke_fpga;\n wire [DM_WIDTH-1:0] ddr3_dm_fpga;\n wire [DQS_WIDTH-1:0] ddr3_dqs_p_fpga;\n wire [DQS_WIDTH-1:0] ddr3_dqs_n_fpga;\n wire [CK_WIDTH-1:0] ddr3_ck_p_fpga;\n wire [CK_WIDTH-1:0] ddr3_ck_n_fpga;\n\n wire [DQ_WIDTH-1:0] ddr3_dq_sdram;\n reg [ROW_WIDTH-1:0] ddr3_addr_sdram;\n reg [BANK_WIDTH-1:0] ddr3_ba_sdram;\n reg ddr3_ras_n_sdram;\n reg ddr3_cas_n_sdram;\n reg ddr3_we_n_sdram;\n reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_sdram;\n reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_sdram;\n reg [CKE_WIDTH-1:0] ddr3_cke_sdram;\n wire [DM_WIDTH-1:0] ddr3_dm_sdram;\n wire [DQS_WIDTH-1:0] ddr3_dqs_p_sdram;\n wire [DQS_WIDTH-1:0] ddr3_dqs_n_sdram;\n reg [CK_WIDTH-1:0] ddr3_ck_p_sdram;\n reg [CK_WIDTH-1:0] ddr3_ck_n_sdram;\n\n reg [ROW_WIDTH-1:0] ddr3_addr_r;\n reg [BANK_WIDTH-1:0] ddr3_ba_r;\n reg ddr3_ras_n_r;\n reg ddr3_cas_n_r;\n reg ddr3_we_n_r;\n reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_r;\n reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_r;\n reg [CKE_WIDTH-1:0] ddr3_cke_r;\n\n\n wire clk;\n wire rst;\n wire app_sz;\n wire [ADDR_WIDTH-1:0] app_addr;\n wire app_wdf_wren;\n wire [APP_DATA_WIDTH-1:0] app_wdf_data;\n wire [APP_MASK_WIDTH-1:0] app_wdf_mask;\n wire app_wdf_end;\n wire app_rd_data_end;\n wire app_rd_data_valid;\n wire [6:0] tg_wr_fifo_counts;\n wire [6:0] tg_rd_fifo_counts;\n wire tg_rd_en;\n wire [APP_DATA_WIDTH-1:0] app_rd_data;\n wire [31:0] tpt_hdata;\n wire t_gen_run_traffic;\n wire [31:0] t_gen_start_addr;\n wire [31:0] t_gen_end_addr;\n wire [31:0] t_gen_cmd_seed;\n wire [31:0] t_gen_data_seed;\n wire t_gen_load_seed;\n wire [2:0] t_gen_addr_mode;\n wire [3:0] t_gen_instr_mode;\n wire [1:0] t_gen_bl_mode;\n wire [3:0] t_gen_data_mode;\n wire t_gen_mode_load;\n wire [5:0] t_gen_fixed_bl;\n wire [2:0] t_gen_fixed_instr;\n wire [31:0] t_gen_fixed_addr;\n wire manual_clear_error;\n wire modify_enable_sel;\n wire [2:0] vio_data_mode;\n wire [2:0] vio_addr_mode;\n\n //**************************************************************************//\n // Clock generation and reset\n //**************************************************************************//\n\n initial begin\n sys_clk = 1'b0;\n clk_ref = 1'b1;\n sys_rst_n = 1'b0;\n\n #120000\n sys_rst_n = 1'b1;\n end\n\n assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;\n\n // Generate system clock = twice rate of CLK\n always\n sys_clk = #(CLK_PERIOD/2.0) ~sys_clk;\n\n // Generate IDELAYCTRL reference clock (200MHz)\n always\n clk_ref = #REFCLK_PERIOD ~clk_ref;\n\n assign sys_clk_p = sys_clk;\n assign sys_clk_n = ~sys_clk;\n\n assign clk_ref_p = clk_ref;\n assign clk_ref_n = ~clk_ref;\n\n\n //**************************************************************************//\n\n always @( * ) begin\n ddr3_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_p_fpga;\n ddr3_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_n_fpga;\n ddr3_addr_sdram <= #(TPROP_PCB_CTRL) ddr3_addr_fpga;\n ddr3_ba_sdram <= #(TPROP_PCB_CTRL) ddr3_ba_fpga;\n ddr3_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ras_n_fpga;\n ddr3_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cas_n_fpga;\n ddr3_we_n_sdram <= #(TPROP_PCB_CTRL) ddr3_we_n_fpga;\n ddr3_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cs_n_fpga;\n ddr3_cke_sdram <= #(TPROP_PCB_CTRL) ddr3_cke_fpga;\n ddr3_odt_sdram <= #(TPROP_PCB_CTRL) ddr3_odt_fpga;\n ddr3_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr3_dm_fpga;//DM signal generation\n end\n\n assign ddr3_dm_sdram = {DM_WIDTH{1'b0}};\n\n// Controlling the bi-directional BUS\n genvar dqwd;\n generate\n for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay\n WireDelay #\n (\n .Delay_g (TPROP_PCB_DATA),\n .Delay_rd (TPROP_PCB_DATA_RD),\n .ERR_INSERT (\"OFF\")\n )\n u_delay_dq\n (\n .A (ddr3_dq_fpga[dqwd]),\n .B (ddr3_dq_sdram[dqwd]),\n .reset (sys_rst_n),\n .phy_init_done (phy_init_done)\n );\n end\n WireDelay #\n (\n .Delay_g (TPROP_PCB_DATA),\n .Delay_rd (TPROP_PCB_DATA_RD),\n .ERR_INSERT (ECC)\n )\n u_delay_dq_0\n (\n .A (ddr3_dq_fpga[0]),\n .B (ddr3_dq_sdram[0]),\n .reset (sys_rst_n),\n .phy_init_done (phy_init_done)\n );\n\n endgenerate\n\n genvar dqswd;\n generate\n for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay\n WireDelay #\n (\n .Delay_g (TPROP_DQS),\n .Delay_rd (TPROP_DQS_RD),\n .ERR_INSERT (\"OFF\")\n )\n u_delay_dqs_p\n (\n .A (ddr3_dqs_p_fpga[dqswd]),\n .B (ddr3_dqs_p_sdram[dqswd]),\n .reset (sys_rst_n),\n .phy_init_done (phy_init_done)\n );\n\n WireDelay #\n (\n .Delay_g (TPROP_DQS),\n .Delay_rd (TPROP_DQS_RD),\n .ERR_INSERT (\"OFF\")\n )\n u_delay_dqs_n\n (\n .A (ddr3_dqs_n_fpga[dqswd]),\n .B (ddr3_dqs_n_sdram[dqswd]),\n .reset (sys_rst_n),\n .phy_init_done (phy_init_done)\n );\n end\n endgenerate\n assign sda = 1'b1;\n assign scl = 1'b1;\n \n \n // Instantiate the Unit Under Test (UUT)\n\tsoftMC_top #\n (\n .nCK_PER_CLK (nCK_PER_CLK),\n .tCK (tCK),\n .RST_ACT_LOW (RST_ACT_LOW),\n .REFCLK_FREQ (REFCLK_FREQ),\n .IODELAY_GRP (IODELAY_GRP),\n .INPUT_CLK_TYPE (INPUT_CLK_TYPE),\n .BANK_WIDTH (BANK_WIDTH),\n .CK_WIDTH (CK_WIDTH),\n .CKE_WIDTH (CKE_WIDTH),\n .COL_WIDTH (COL_WIDTH),\n .nCS_PER_RANK (nCS_PER_RANK),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .ROW_WIDTH (ROW_WIDTH),\n .RANK_WIDTH (RANK_WIDTH),\n .CS_WIDTH (CS_WIDTH),\n .BURST_MODE (BURST_MODE),\n .BM_CNT_WIDTH (BM_CNT_WIDTH),\n .CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),\n .DIVCLK_DIVIDE (DIVCLK_DIVIDE),\n .CLKOUT_DIVIDE (CLKOUT_DIVIDE),\n .OUTPUT_DRV (OUTPUT_DRV),\n .REG_CTRL (REG_CTRL),\n .RTT_NOM (RTT_NOM),\n .RTT_WR (RTT_WR),\n .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),\n .DEBUG_PORT (DEBUG_PORT),\n .tPRDI (tPRDI),\n .tREFI (tREFI),\n .tZQI (tZQI),\n .ADDR_CMD_MODE (ADDR_CMD_MODE),\n .ORDERING (ORDERING),\n .STARVE_LIMIT (STARVE_LIMIT),\n .ADDR_WIDTH (ADDR_WIDTH),\n .ECC (ECC),\n .ECC_TEST (ECC_TEST),\n .TCQ (TCQ),\n .DATA_WIDTH (DATA_WIDTH),\n .PAYLOAD_WIDTH (PAYLOAD_WIDTH)\n ) uut (\n\t\t.sys_clk_p(sys_clk_p), \n\t\t.sys_clk_n(sys_clk_n), \n\t\t.clk_ref_p(clk_ref_p), \n\t\t.clk_ref_n(clk_ref_n), \n\t\t.sys_rst(sys_rst), \n\t\t.sys_reset_n(1'b1),\n\t\t.ddr_ck_p(ddr3_ck_p_fpga), \n\t\t.ddr_ck_n(ddr3_ck_n_fpga), \n\t\t.ddr_addr(ddr3_addr_fpga), \n\t\t.ddr_ba(ddr3_ba_fpga), \n\t\t.ddr_ras_n(ddr3_ras_n_fpga), \n\t\t.ddr_cas_n(ddr3_cas_n_fpga), \n\t\t.ddr_we_n(ddr3_we_n_fpga), \n\t\t.ddr_cs_n(ddr3_cs_n_fpga), \n\t\t.ddr_cke(ddr3_cke_fpga), \n\t\t.ddr_odt(ddr3_odt_fpga), \n\t\t.ddr_reset_n(ddr3_reset_n), \n\t\t//.ddr_parity(), \n\t\t.ddr_dm(), \n\t\t.ddr_dqs_p(ddr3_dqs_p_fpga), \n\t\t.ddr_dqs_n(ddr3_dqs_n_fpga), \n\t\t.ddr_dq(ddr3_dq_fpga),\n\t\t.dfi_init_complete(phy_init_done),\n\t\t.iq_full(iq_full),\n\t\t.processing_iseq(processing_iseq),\n\t\t\n\t\t.app_en(app_en),\n\t\t.app_ack(app_ack),\n\t\t.app_instr(app_instr),\n\t\t\n\t\t.rdback_fifo_rden(rdback_fifo_rden),\n\t\t.rdback_data(rdback_data),\n\t\t.rdback_fifo_empty(rdback_fifo_empty)\n\t);\n\n\n // Extra one clock pipelining for RDIMM address and\n // control signals is implemented here (Implemented external to memory model)\n always @( posedge ddr3_ck_p_sdram[0] ) begin\n if ( ddr3_reset_n == 1'b0 ) begin\n ddr3_ras_n_r <= 1'b1;\n ddr3_cas_n_r <= 1'b1;\n ddr3_we_n_r <= 1'b1;\n ddr3_cs_n_r <= {(CS_WIDTH*nCS_PER_RANK){1'b1}};\n ddr3_odt_r <= 1'b0;\n end\n else begin\n ddr3_addr_r <= #(CLK_PERIOD/2) ddr3_addr_sdram;\n ddr3_ba_r <= #(CLK_PERIOD/2) ddr3_ba_sdram;\n ddr3_ras_n_r <= #(CLK_PERIOD/2) ddr3_ras_n_sdram;\n ddr3_cas_n_r <= #(CLK_PERIOD/2) ddr3_cas_n_sdram;\n ddr3_we_n_r <= #(CLK_PERIOD/2) ddr3_we_n_sdram;\n if (~(ddr3_cs_n_sdram[0] | ddr3_cs_n_sdram[1]) & ~phy_init_done)\n ddr3_cs_n_r <= #(CLK_PERIOD/2) {(CS_WIDTH*nCS_PER_RANK){1'b1}};\n else\n ddr3_cs_n_r <= #(CLK_PERIOD/2) ddr3_cs_n_sdram;\n ddr3_odt_r <= #(CLK_PERIOD/2) ddr3_odt_sdram;\n end\n end\n\n // to avoid tIS violations on CKE when reset is deasserted\n always @( posedge ddr3_ck_n_sdram[0] )\n if ( ddr3_reset_n == 1'b0 )\n ddr3_cke_r <= 1'b0;\n else\n ddr3_cke_r <= #(CLK_PERIOD) ddr3_cke_sdram;\n\n\n\n //***************************************************************************\n // Instantiate memories\n //***************************************************************************\n\n genvar r,i,dqs_x;\n generate\n if(DRAM_DEVICE == \"COMP\") begin : comp_inst\n for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk\n if(MEMORY_WIDTH == 16) begin: mem_16\n if(DQ_WIDTH/16) begin: gen_mem\n for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem\n ddr3_model u_comp_ddr3\n (\n .rst_n (ddr3_reset_n),\n .ck (ddr3_ck_p_sdram),\n .ck_n (ddr3_ck_n_sdram),\n .cke (ddr3_cke_sdram[r]),\n .cs_n (ddr3_cs_n_sdram[r]),\n .ras_n (ddr3_ras_n_sdram),\n .cas_n (ddr3_cas_n_sdram),\n .we_n (ddr3_we_n_sdram),\n .dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),\n .ba (ddr3_ba_sdram),\n .addr (ddr3_addr_sdram),\n .dq (ddr3_dq_sdram[16*(i+1)-1:16*(i)]),\n .dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),\n .dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),\n .tdqs_n (),\n .odt (ddr3_odt_sdram[r])\n );\n end\n end\n if (DQ_WIDTH%16) begin: gen_mem_extrabits\n ddr3_model u_comp_ddr3\n (\n .rst_n (ddr3_reset_n),\n .ck (ddr3_ck_p_sdram),\n .ck_n (ddr3_ck_n_sdram),\n .cke (ddr3_cke_sdram[r]),\n .cs_n (ddr3_cs_n_sdram[r]),\n .ras_n (ddr3_ras_n_sdram),\n .cas_n (ddr3_cas_n_sdram),\n .we_n (ddr3_we_n_sdram),\n .dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),\n .ba (ddr3_ba_sdram),\n .addr (ddr3_addr_sdram),\n .dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],\n ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),\n .dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],\n ddr3_dqs_p_sdram[DQS_WIDTH-1]}),\n .dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],\n ddr3_dqs_n_sdram[DQS_WIDTH-1]}),\n .tdqs_n (),\n .odt (ddr3_odt_sdram[r])\n );\n end\n end\n else if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4\n for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem\n ddr3_model u_comp_ddr3\n (\n .rst_n (ddr3_reset_n),\n .ck (ddr3_ck_p_sdram),\n .ck_n (ddr3_ck_n_sdram),\n .cke (ddr3_cke_sdram[r]),\n .cs_n (ddr3_cs_n_sdram[r]),\n .ras_n (ddr3_ras_n_sdram),\n .cas_n (ddr3_cas_n_sdram),\n .we_n (ddr3_we_n_sdram),\n .dm_tdqs (ddr3_dm_sdram[i]),\n .ba (ddr3_ba_sdram),\n .addr (ddr3_addr_sdram),\n .dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),\n .dqs (ddr3_dqs_p_sdram[i]),\n .dqs_n (ddr3_dqs_n_sdram[i]),\n .tdqs_n (),\n .odt (ddr3_odt_sdram[r])\n );\n end\n end\n end\n end\n else if(DRAM_DEVICE == \"RDIMM\") begin: rdimm_inst\n for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk\n if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4\n for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem\n ddr3_model u_comp_ddr3\n (\n .rst_n (ddr3_reset_n),\n .ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),\n .ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),\n .cke (ddr3_cke_r[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),\n .cs_n (ddr3_cs_n_r[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),\n .ras_n (ddr3_ras_n_r),\n .cas_n (ddr3_cas_n_r),\n .we_n (ddr3_we_n_r),\n .dm_tdqs (ddr3_dm_sdram[i]),\n .ba (ddr3_ba_r),\n .addr (ddr3_addr_r),\n .dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),\n .dqs (ddr3_dqs_p_sdram[i]),\n .dqs_n (ddr3_dqs_n_sdram[i]),\n .tdqs_n (),\n .odt (ddr3_odt_r[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])\n );\n end\n end\n end\n end\n else if(DRAM_DEVICE == \"UDIMM\") begin: udimm_inst\n for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk\n if(MEMORY_WIDTH == 16) begin: mem_16\n if(DQ_WIDTH/16) begin: gen_mem\n for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem\n ddr3_model u_comp_ddr3\n (\n .rst_n (ddr3_reset_n),\n .ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),\n .ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),\n .cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),\n .cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),\n .ras_n (ddr3_ras_n_sdram),\n .cas_n (ddr3_cas_n_sdram),\n .we_n (ddr3_we_n_sdram),\n .dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),\n .ba (ddr3_ba_sdram),\n .addr (ddr3_addr_sdram),\n .dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),\n .dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),\n .dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),\n .tdqs_n (),\n .odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])\n );\n end\n end\n if (DQ_WIDTH%16) begin: gen_mem_extrabits\n ddr3_model u_comp_ddr3\n (\n .rst_n (ddr3_reset_n),\n .ck (ddr3_ck_p_sdram[(DQ_WIDTH-1)/72]),\n .ck_n (ddr3_ck_n_sdram[(DQ_WIDTH-1)/72]),\n .cke (ddr3_cke_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),\n .cs_n (ddr3_cs_n_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),\n .ras_n (ddr3_ras_n_sdram),\n .cas_n (ddr3_cas_n_sdram),\n .we_n (ddr3_we_n_sdram),\n .dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),\n .ba (ddr3_ba_sdram),\n .addr (ddr3_addr_sdram),\n .dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],\n ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),\n .dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],\n ddr3_dqs_p_sdram[DQS_WIDTH-1]}),\n .dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],\n ddr3_dqs_n_sdram[DQS_WIDTH-1]}),\n .tdqs_n (),\n .odt (ddr3_odt_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)])\n );\n end\n end\n else if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4\n for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem\n ddr3_model u_comp_ddr3\n (\n .rst_n (ddr3_reset_n),\n .ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),\n .ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),\n .cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),\n .cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),\n .ras_n (ddr3_ras_n_sdram),\n .cas_n (ddr3_cas_n_sdram),\n .we_n (ddr3_we_n_sdram),\n .dm_tdqs (ddr3_dm_sdram[i]),\n .ba (ddr3_ba_sdram),\n .addr (ddr3_addr_sdram),\n .dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),\n .dqs (ddr3_dqs_p_sdram[i]),\n .dqs_n (ddr3_dqs_n_sdram[i]),\n .tdqs_n (),\n .odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])\n );\n end\n end\n end\n end\n else if(DRAM_DEVICE == \"SODIMM\") begin: sodimm_inst\n for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk\n if(MEMORY_WIDTH == 16) begin: mem_16\n if(DQ_WIDTH/16) begin: gen_mem\n for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem\n ddr3_model u_comp_ddr3\n (\n .rst_n (ddr3_reset_n),\n .ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),\n .ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),\n .cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),\n .cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),\n .ras_n (ddr3_ras_n_sdram),\n .cas_n (ddr3_cas_n_sdram),\n .we_n (ddr3_we_n_sdram),\n .dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),\n .ba (ddr3_ba_sdram),\n .addr (ddr3_addr_sdram),\n .dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),\n .dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),\n .dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),\n .tdqs_n (),\n .odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])\n );\n end\n end\n if (DQ_WIDTH%16) begin: gen_mem_extrabits\n ddr3_model u_comp_ddr3\n (\n .rst_n (ddr3_reset_n),\n .ck (ddr3_ck_p_sdram[(DQ_WIDTH-1)/72]),\n .ck_n (ddr3_ck_n_sdram[(DQ_WIDTH-1)/72]),\n .cke (ddr3_cke_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),\n .cs_n (ddr3_cs_n_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),\n .ras_n (ddr3_ras_n_sdram),\n .cas_n (ddr3_cas_n_sdram),\n .we_n (ddr3_we_n_sdram),\n .dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),\n .ba (ddr3_ba_sdram),\n .addr (ddr3_addr_sdram),\n .dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],\n ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),\n .dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],\n ddr3_dqs_p_sdram[DQS_WIDTH-1]}),\n .dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],\n ddr3_dqs_n_sdram[DQS_WIDTH-1]}),\n .tdqs_n (),\n .odt (ddr3_odt_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)])\n );\n end\n end\n if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4\n for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem\n ddr3_model u_comp_ddr3\n (\n .rst_n (ddr3_reset_n),\n .ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),\n .ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),\n .cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),\n .cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),\n .ras_n (ddr3_ras_n_sdram),\n .cas_n (ddr3_cas_n_sdram),\n .we_n (ddr3_we_n_sdram),\n .dm_tdqs (ddr3_dm_sdram[i]),\n .ba (ddr3_ba_sdram),\n .addr (ddr3_addr_sdram),\n .dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),\n .dqs (ddr3_dqs_p_sdram[i]),\n .dqs_n (ddr3_dqs_n_sdram[i]),\n .tdqs_n (),\n .odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])\n );\n end\n end\n end\n end\n endgenerate\n\t\n\n\t//***************************************************************************\n // Reporting the test case status\n //***************************************************************************\n localparam APP_CLK_PERIOD = tCK * nCK_PER_CLK;\n initial\n begin : Logging\n\t\tapp_en = 0;\n\t\trdback_fifo_rden = 0;\n begin : calibration_done\n wait (phy_init_done);\n $display(\"Calibration Done\");\n\t\t\t \n #1000000;\n\t\t\t \n\t\t\t \n\t app_en = 0;\n\t #(APP_CLK_PERIOD*1000);\n\t \n\t #APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b00010000000000000000000000000010; //busdir\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b01000000000000000000000000000101; //wait\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b10010001000100110000000000000000; //act\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b01000000000000000000000000000110; //wait\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b10010001000110110000000010110010; //read\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b01000000000000000000000000000101; //wait\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b10101101001000111000000000001110;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b01000000000000000000000000000110;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b11010011001000110100000000001000;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b01000000000000000000000000001010;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b10010001000100110000000000000000;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b01000000000000000000000000000101;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b00010000000000000000000000000000;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b01000000000000000000000000000101;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b10010001000110110000000010110010;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b01000000000000000000000000000101;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b10000001001010110000000000001000;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b01000000000000000000000000001010;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b01000000000000000000000000000011;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b10010001000100110000000000000000;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b01000000000000000000000000000101;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 1;\n\t\tapp_instr = 32'b00000000000000000000000000000000;\n\n\t\t#APP_CLK_PERIOD;\n\t\tapp_en = 0;\n end\n end\n \nendmodule\n\n" }, { "path": "sw/RetentionTest/Makefile", "content": "program_NAME := SoftMC_RetentionTest\nprogram_CXX_SRCS := $(wildcard *.cpp) $(wildcard ../SoftMC_API/*.cpp)\nprogram_CXX_OBJS := ${program_CXX_SRCS:.cpp=.o}\nprogram_OBJS := $(program_CXX_OBJS)\nprogram_INCLUDE_DIRS := ../SoftMC_API\nprogram_LIBRARY_DIRS :=\nprogram_LIBRARIES := riffa\nCPPFLAGS += -g -std=c++11\n\nCPPFLAGS += $(foreach includedir,$(program_INCLUDE_DIRS),-I$(includedir))\nLDFLAGS += $(foreach librarydir,$(program_LIBRARY_DIRS),-L$(librarydir))\nLDFLAGS += $(foreach library,$(program_LIBRARIES),-l$(library))\n\nCC=g++\n\n.PHONY: all clean distclean\n\nall: $(program_NAME)\n\n$(program_NAME): $(program_OBJS)\n\t$(CC) $(CPPFLAGS) $(program_OBJS) -o $(program_NAME) $(LDFLAGS)\n\nclean:\n\t@- $(RM) $(program_NAME)\n\t@- $(RM) $(program_OBJS)\n\ndistclean: clean\n" }, { "path": "sw/RetentionTest/RetentionTest.cpp", "content": "#include \n#include \n#include \n#include \n#include \n#include \n#include \"softmc.h\"\n\nusing namespace std;\n\n//Note that capacity of the instruction buffer is 8192 instructions\nvoid writeRow(fpga_t* fpga, uint row, uint bank, uint8_t pattern, InstructionSequence*& iseq){\n\n\tif(iseq == nullptr)\n\t\tiseq = new InstructionSequence();\n\telse\n\t\tiseq->size = 0;//reuse the provided InstructionSequence to avoid dynamic allocation on each call\n\n\t//Precharge target bank (just in case if its left activated)\n\tiseq->insert(genPRE(bank, PRE_TYPE::SINGLE));\n\n\t//Wait for tRP\n\tiseq->insert(genWAIT(5));//2.5ns have already been passed as we issue in next cycle. So, 5 means 6 cycles latency, 15 ns\n\n\t//Activate target row\n\tiseq->insert(genACT(bank, row));\n\n\t//Wait for tRCD\n\tiseq->insert(genWAIT(5));\n\n\t//Write to the entire row\n\tfor(int i = 0; i < NUM_COLS; i+=8){ //we use 8x burst mode\n\t\tiseq->insert(genWR(bank, i, pattern));\n\n\t\t//We need to wait for tCL and 4 cycles burst (double data-rate)\n\t\tiseq->insert(genWAIT(6 + 4));\n\t}\n\n\t//Wait some more in any case\n\tiseq->insert(genWAIT(3));\n\n\t//Precharge target bank\n\tiseq->insert(genPRE(bank, PRE_TYPE::SINGLE));\n\n\t//Wait for tRP\n\tiseq->insert(genWAIT(5));//we have already 2.5ns passed as we issue in next cycle. So, 5 means 6 cycles latency, 15 ns\n\n\t//START Transaction\n\tiseq->insert(genEND());\n\n\tiseq->execute(fpga);\n}\n\nvoid readAndCompareRow(fpga_t* fpga, const uint row, const uint bank, const uint8_t pattern, InstructionSequence*& iseq){\n\n\tif(iseq == nullptr)\n\t\tiseq = new InstructionSequence();\n\telse\n\t\tiseq->size = 0;//reuse the provided InstructionSequence to avoid dynamic allocation for each call\n\n\t//Precharge target bank (just in case if its left activated)\n\tiseq->insert(genPRE(bank, PRE_TYPE::SINGLE));\n\n\t//Wait for tRP\n\tiseq->insert(genWAIT(5));//2.5ns have already been passed as we issue in next cycle. So, 5 means 6 cycles latency, 15 ns\n\n\t//Activate target row\n\tiseq->insert(genACT(bank, row));\n\n\t//Wait for tRCD\n\tiseq->insert(genWAIT(5));\n\n\t//Read the entire row\n\tfor(int i = 0; i < NUM_COLS; i+=8){ //we use 8x burst mode\n\t\tiseq->insert(genRD(bank, i));\n\n\t\t//We need to wait for tCL and 4 cycles burst (double data-rate)\n\t\tiseq->insert(genWAIT(6 + 4));\n\t}\n\n\t//Wait some more in any case\n\tiseq->insert(genWAIT(3));\n\n\t//Precharge target bank\n\tiseq->insert(genPRE(bank, PRE_TYPE::SINGLE)); //pre 1 -> precharge all, pre 0 precharge bank\n\n\t//Wait for tRP\n\tiseq->insert(genWAIT(5));//we have already 2.5ns passed as we issue in next cycle. So, 5 means 6 cycles latency, 15 ns\n\n\t//START Transaction\n\tiseq->insert(genEND());\n\n\tiseq->execute(fpga);\n\n\t//Receive the data\n\tuint rbuf[16];\n\tfor(int i = 0; i < NUM_COLS; i+=8){ //we receive a single burst at two times (32 bytes each)\n\t\tfpga_recv(fpga, 0, (void*)rbuf, 16, 0);\n\n\t\t//compare with the pattern\n\t\tuint8_t* rbuf8 = (uint8_t *) rbuf;\n\n\t\tfor(int j = 0; j < 64; j++){\n\t\t\tif(rbuf8[j] != pattern)\n\t\t\t\tfprintf(stderr, \"Error at Col: %d, Row: %u, Bank: %u, DATA: %x \\n\", i, row, bank, rbuf8[j]);\n\t\t}\n\t}\n}\n\nvoid turnBus(fpga_t* fpga, BUSDIR b, InstructionSequence* iseq = nullptr){\n\n\tif(iseq == nullptr)\n\t\tiseq = new InstructionSequence();\n\telse\n\t\tiseq->size = 0;//reuse the provided InstructionSequence to avoid dynamic allocation for each call\n\n\tiseq->insert(genBUSDIR(b));\n\n\t//WAIT\n\tiseq->insert(genWAIT(5));\n\n\t//START Transaction\n\tiseq->insert(genEND());\n\n\tiseq->execute(fpga);\t\n}\n\n\n//! Runs a test to check the DRAM cells against the given retention time.\n/*!\n \\param \\e fpga is a pointer to the RIFFA FPGA device.\n \\param \\e retention is the retention time in milliseconds to test.\n*/\nvoid testRetention(fpga_t* fpga, const int retention){\n\n\tuint8_t pattern = 0xff; //the data pattern that we write to the DRAM\n\n\tbool dimm_done = false;\n\n\tInstructionSequence* iseq = nullptr; // we temporarily store (before sending them to the FPGA) the generated instructions here\n\n\tGET_TIME_INIT(2);\n\n\t//writing the entire row takes approximately 5 ms\n\tuint group_size = ceil(retention/5.0f); //number of rows to be written in a single iteration\n\tuint cur_row_write = 0;\n\tuint cur_bank_write = 0;\n\tuint cur_row_read = 0;\n\tuint cur_bank_read = 0;\n\n printf(\"\\n\");\n\n\twhile(!dimm_done){ //continue until we cover the entire DRAM\n\t\t//print the number of the row that we are about to test\n\t\tprintf(\"%c[2K\\r\", 27);\n printf(\"Current Bank: %d, Row: %d\", cur_bank_write, cur_row_write);\n\t\tfflush(stdout);\n \n\t\t// Switch the memory bus to write mode\n\t\tturnBus(fpga, BUSDIR::WRITE, iseq);\n\n\t\tGET_TIME_VAL(0);\n\n\t\t// We write to a chunk of rows (group_size) successively\n\t\tfor(int i = 0; i < group_size; i++){\n\t\t\t// write the data pattern to the entire row\n\t\t\twriteRow(fpga, cur_row_write, cur_bank_write, pattern, iseq);\n\t\t\tcur_row_write++;\n\n\t\t\t// when we complete testing all of the rows in a bank, we move to the next bank\n\t\t\tif(cur_row_write == NUM_ROWS){\n\t\t\t\tcur_row_write = 0;\n\t\t\t\tcur_bank_write++;\n\t\t\t}\n\t\t\n\t\t\t// the entire DIMM is covered when we complete testing all of the bank\n\t\t\tif(cur_bank_write == NUM_BANKS){\n\t\t\t\t// we are done with the entire DIMM\n\t\t\t\tdimm_done = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t// Switch the memory bus to read mode\n\t\tturnBus(fpga, BUSDIR::READ, iseq);\n\n\t\t// wait for the specified retention time (retention)\n\t\tdo{\n\t\t\tGET_TIME_VAL(1);\n\t\t} while((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)) < retention);\n\n\t\t// Read the data back and compare\n\t\tfor(int i = 0; i < group_size; i++){\n\t\t\treadAndCompareRow(fpga, cur_row_read, cur_bank_read, pattern, iseq);\n\n\t\t\tcur_row_read++;\n\n\t\t\tif(cur_row_read == NUM_ROWS){ //NUM_ROWS\n\t\t\t\tcur_row_read = 0;\n\t\t\t\tcur_bank_read++;\n\t\t\t}\n\t\t\n\t\t\tif(cur_bank_read == NUM_BANKS){ //NUM_BANKS\n\t\t\t\t//we are done with the entire DIMM\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tprintf(\"\\n\");\n\n\tdelete iseq;\n}\n\n// provide trefi = 0 to disable auto-refresh\n// auto-refresh is disabled by default (disabled after FPGA boots, disables on pushing reset button)\nvoid setRefreshConfig(fpga_t* fpga, uint trefi, uint trfc){\n\tInstructionSequence* iseq = new InstructionSequence;\n\n\tiseq->insert(genREF_CONFIG(trfc, REGISTER::TRFC));\n\tiseq->insert(genREF_CONFIG(trefi, REGISTER::TREFI));\n\n\t//START Transaction\n\tiseq->insert(genEND());\n\n\tiseq->execute(fpga);\t\n\n\tdelete iseq;\n}\n\n\nvoid printHelp(char* argv[]){\n\tcout << \"A sample application that tests retention time of DRAM cells using SoftMC\" << endl;\n\tcout << \"Usage:\" << argv[0] << \" [REFRESH INTERVAL]\" << endl; \n\tcout << \"The Refresh Interval should be a positive integer, indicating the target retention time in milliseconds.\" << endl;\n}\n\nint main(int argc, char* argv[]){\n\tfpga_t* fpga;\n\tfpga_info_list info;\n\tint fid = 0; //fpga id\n\tint ch = 0; //channel id\n\n\tif(argc != 2 || strcmp(argv[1], \"--help\") == 0){\n\t\tprintHelp(argv);\n\t\treturn -2;\n\t}\n\n string s_ref(argv[1]);\n int refresh_interval = 0;\n\n try{\n refresh_interval = stoi(s_ref); \n }catch(...){\n printHelp(argv);\n return -3;\n }\n\n if(refresh_interval <= 0){\n printHelp(argv);\n return -4;\n }\n\n\t// Get the list of FPGA's attached to the system\n\tif (fpga_list(&info) != 0) {\n\t\tprintf(\"Error populating fpga_info_list\\n\");\n\t\treturn -1;\n\t}\n\tprintf(\"Number of devices: %d\\n\", info.num_fpgas);\n\tfor (int i = 0; i < info.num_fpgas; i++) {\n\t\tprintf(\"%d: id:%d\\n\", i, info.id[i]);\n\t\tprintf(\"%d: num_chnls:%d\\n\", i, info.num_chnls[i]);\n\t\tprintf(\"%d: name:%s\\n\", i, info.name[i]);\n\t\tprintf(\"%d: vendor id:%04X\\n\", i, info.vendor_id[i]);\n\t\tprintf(\"%d: device id:%04X\\n\", i, info.device_id[i]);\n\t}\n\n\t// Open an FPGA device, so we can read/write from/to it\n\tfpga = fpga_open(fid);\n\n\tif(!fpga){\n\t\tprintf(\"Problem on opening the fpga \\n\");\n\t\treturn -1;\n\t}\n\tprintf(\"The FPGA has been opened successfully! \\n\");\n\n\t// send a reset signal to the FPGA\n\tfpga_reset(fpga); //keep this, recovers FPGA from some unwanted state\n\n\t//uint trefi = 7800/200; //7.8us (divide by 200ns as the HW counts with that period)\n\t//uint trfc = 104; //default trfc for 4Gb device\n\t//printf(\"Activating AutoRefresh. tREFI: %d, tRFC: %d \\n\", trefi, trfc);\n\t//setRefreshConfig(fpga, trefi, trfc);\n\n \tprintf(\"Starting Retention Time Test @ %d ms! \\n\", refresh_interval);\n\n\ttestRetention(fpga, refresh_interval);\n\n\tprintf(\"The test has been completed! \\n\");\n\tfpga_close(fpga);\n\n\treturn 0;\n}\n" }, { "path": "sw/SoftMC_API/softmc.cpp", "content": "#include \"softmc.h\"\n#include \n#include \n#include \n\nusing namespace std;\n\nInstructionSequence::InstructionSequence() : InstructionSequence(init_cap){\n}\n\nInstructionSequence::InstructionSequence(const uint capacity){\n\tinstrs = new Instruction[capacity];\n\tsize = 0;\n\tthis->capacity = capacity;\n}\n\nInstructionSequence::~InstructionSequence(){\n\tdelete[] instrs;\n}\n\nvoid InstructionSequence::insert(const Instruction c){\n\tif(size == capacity){\n\t\tInstruction* tmp = new Instruction[capacity*2];\n\t\t\n\t\tfor(int i = 0; i < size; i++)\n\t\t\ttmp[i] = instrs[i];\n\n\t\tdelete[] instrs;\n\t\tcapacity *=2;\n\t\tinstrs = tmp;\n\t}\n\n\tinstrs[size++] = c;\n}\n\nvoid InstructionSequence::execute(fpga_t* fpga){\n\tfpga_send(fpga, 0, (void*)instrs, INSTR_SIZE*size, 0, 1, 0);\n}\n\n//! Generates an instruction to \\b activate the row at the given address.\n/*!\n \\param \\e bank is the bank number.\n \\param \\e row is the row number.\n \\return The generated activate instruction\n*/\nInstruction genACT(uint bank, uint row){\n\tInstruction instr = (uint)INSTR_TYPE::DDR;\n\tinstr <<= 32 - CMD_OFFSET - BANK_OFFSET - ROW_OFFSET;\n\tinstr |= 0x23; //sets CKE(1) CS(0) RAS(0) CAS(1) WE_ACT(1)\n\tinstr <<= BANK_OFFSET;\n\tinstr |= bank;\n\tinstr <<= ROW_OFFSET;\n\tinstr |= row;\n\t\t\n\treturn instr;\n}\n\n//! Generates an instruction to \\b precharge the given bank.\n/*!\n \\param \\e bank is the bank number.\n \\param \\e pc is the precharge type with default value PRE_TYPE.SINGLE.\nCan be \\e PRE_TYPE.SINGLE for a single-bank precharge, or \\e PRE_TYPE.ALL \nfor an all-banks precharge).\n \\return The generated precharge instruction\n*/\nInstruction genPRE(uint bank, PRE_TYPE pc){\n\tInstruction instr = (uint)INSTR_TYPE::DDR;\n\tinstr <<= 32 - CMD_OFFSET - BANK_OFFSET - ROW_OFFSET;\n\tinstr |= 0x22; //to set CKE(1) CS(0) RAS(0) CAS(1) WE_PRE(0)\n\tif(pc == PRE_TYPE::ALL){\n\t\tinstr <<= BANK_OFFSET + ROW_OFFSET - COL_OFFSET;\n\t\tinstr |= 0x1;\n\t\tinstr <<= COL_OFFSET;\n\t}\n\telse{\n\t\tinstr <<= BANK_OFFSET;\n\t\tinstr |= bank;\n\t\tinstr <<= ROW_OFFSET;\n\t}\n\n\treturn instr;\n}\n\n//! Generates an instruction to \\b write a single byte pattern to the given bank/column address.\n/*!\n \\param \\e col is the column number.\n \\param \\e bank is the bank number.\n \\param \\e pattern is the byte that will be written to the entire column.\n \\param \\e ap is the auto-precharge option with default value AUTO_PRECHARGE.NO_AP. \n Can be \\e AUTO_PRECHARGE.AP to perform precharge right after the write,\n or \\e AUTO_PRECHARGE.NO_AP for to disable auto-precharge).\n \\param \\e bl is the burst length with default value BURST_LENGTH.FIXED. \n Can be \\e BURST_LENGTH.FIXED to set burst length to 8, or BURST_LENGTH.CHOP\n to set 4. Do not forget to set MR0 appropriately to enable\n setting the burst length on-the-fly\n \\return The generated write instruction\n*/\nInstruction genWR(uint bank, uint col, uint8_t pattern, AUTO_PRECHARGE ap, BURST_LENGTH bl){\n\tInstruction instr = (uint)INSTR_TYPE::DDR;\n\tinstr <<= 32 - SIGNAL_OFFSET - BANK_OFFSET - ROW_OFFSET - CMD_OFFSET;\n\n\tinstr |= pattern >> 2; //most significant 6 bits of the pattern\n\tinstr <<= SIGNAL_OFFSET;\n\n\tinstr |= 0x24; //to set CKE(1) CS(0)[assumed it should be Low] \n\t \t //RAS(1) CAS(0) WE(0)\n\tinstr <<= BANK_OFFSET;\n\n\tinstr |= bank;\n\tinstr <<= 2;\n\n\tinstr |= pattern & 0x3; //least significant 2 bits of the pattern\n\n\tinstr <<= 2;\n\n\tif(bl == BURST_LENGTH::FIXED)\n\t\tinstr |= 0x1; // to set cmd[12] to 1 (burst length 8)\n\n\tinstr <<= 2;\n\n\tif(ap == AUTO_PRECHARGE::AP)\n\t\tinstr |= 0x1; // to set cmd[10] to 1\n\n\tinstr <<= COL_OFFSET;\n\tinstr |= col;\n\n\treturn instr;\n}\n\n\n//! Generates an instruction to \\b read from the given bank/column address.\n/*!\n \\param \\e col is the column number.\n \\param \\e bank is the bank number.\n \\param \\e ap is the auto-precharge option with default value AUTO_PRECHARGE.NO_AP. \n Can be \\e AUTO_PRECHARGE.AP to perform precharge right after the read,\n or \\e AUTO_PRECHARGE.NO_AP for to disable auto-precharge).\n \\param \\e bl is the burst length with default value BURST_LENGTH.FIXED.\n Can be \\e BURST_LENGTH.FIXED to set burst length to 8, or BURST_LENGTH.CHOP\n to set burst length to 4. Do not forget to set MR0 appropriately to enable\n setting the burst length on-the-fly. \n \\return The generated read instruction\n*/\nInstruction genRD(uint bank, uint col, AUTO_PRECHARGE ap, BURST_LENGTH bl){\n\tInstruction instr = 0x25; //to set CKE(1) CS(0)[assumed it should be Low] RAS(1) CAS(0) WE(1)\n\t\n\tinstr <<= BANK_OFFSET;\n\tinstr |= bank;\n\n\tinstr <<= 4;\n\n\tif(bl == BURST_LENGTH::FIXED)\n\t\tinstr |= 0x1; // to set cmd[12] to 1 (burst length 8)\n\n\tinstr <<= 2;\n\n\tif(ap == AUTO_PRECHARGE::AP)\n\t\tinstr |= 0x1; // to set cmd[10] to 1\n\n\tinstr <<= COL_OFFSET;\n\tinstr |= col;\n\n\tInstruction instr2 = (uint)INSTR_TYPE::DDR;\n\tinstr2 <<= 28;\n\n\tinstr2 |= instr;\n\n\treturn instr2;\n}\n\n//! Generates a \\b wait instruction to pause issuing commands for the given\n//cycle count.\n/*!\n \\param \\e cycles is the column number.\n \\return The generated wait instruction\n*/\nInstruction genWAIT(uint cycles){ //min 1, max 1023\n\tassert(cycles >= 1);\n\tassert(cycles <= 1023 && \"Could not wait for more than 1023 cycles since the current hardware implementation has a 10 bit counter for this purpose.\");\n \t\n\tInstruction instr = (uint)INSTR_TYPE::WAIT;\n\tinstr <<= 28;\n\tinstr |= cycles;\n\n\treturn instr;\n}\n\n//! Generates an instruction to change bus which switches DQ\n//pins between read or write modes.\n/*!\n \\param \\e dir is the new bus mode to be set. Can be BUSDIR.READ to switch to read\nmode, or BUSDIR.WRITE to switch to write mode.\n \\return The generated change bus direction instruction\n*/\nInstruction genBUSDIR(BUSDIR dir){\n\tInstruction instr = (uint)INSTR_TYPE::SET_BUS_DIR;\n\tinstr <<= 28;\n\tinstr |= (uint)dir;\n\n\treturn instr;\n}\n\n//! Generates an instruction to indicate the end of the instruction sequence .\n/*!\n \\return Instruction used to indicate the end of the instruction sequence\n*/\nInstruction genEND(){\n\treturn (Instruction)((uint)INSTR_TYPE::END_OF_INSTRS << 28);\n}\n\n//! Generates an instruction to initiate DDR3 \\b short-ZQ calibration.\n/*!\n \\return The generated short-ZQ instruction\n*/\nInstruction genZQ(){\n\tInstruction instr = (uint)INSTR_TYPE::DDR;\n\tinstr <<= 32 - CMD_OFFSET - BANK_OFFSET - ROW_OFFSET;\n\tinstr |= 0x26; //to set CKE(1) CS(0) RAS(1) CAS(1) WE(0)\n\tinstr <<= BANK_OFFSET + ROW_OFFSET;\n\n\treturn instr;\n}\n\n//! Generates a DDR3 \\b refresh instruction.\n/*!\n \\return The generated refresh instruction\n*/\nInstruction genREF(){\n Instruction instr = (uint)INSTR_TYPE::DDR;\n instr <<= 32 - CMD_OFFSET - BANK_OFFSET - ROW_OFFSET;\n\n instr |= 0x21; //to set CKE(1) CS(0) RAS(0) CAS(0) WE(1)\n\n instr <<= BANK_OFFSET + ROW_OFFSET;\n\n return instr;\n}\n\n//! Generates an instruction for configuring the auto-refresh mechanism.\n/*!\n \\param \\e val is the value to be set.\n \\param \\e r is the parameter to be configured. Can be \\e\nMC_CMD.SET_TREFI or MC_CMD.SET_TRFC. See DDR3 datasheet for the definition\nof tREFI and tRFC. Set tREFI to 0 to disable auto-refresh (disabled\nby default). \n \\return The generated command for auto-refresh configuration\n*/\nInstruction genREF_CONFIG(uint val, REGISTER r){\n assert(val < 0x10000000);\n\n Instruction instr = (uint) r;\n instr <<= 28;\n instr |= val;\n\n return instr;\n}\n" }, { "path": "sw/SoftMC_API/softmc.h", "content": "#ifndef SOFTMC_H\n#define SOFTMC_H\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#define GET_TIME_INIT(num) struct timeval _timers[num]\n\n#define GET_TIME_VAL(num) gettimeofday(&_timers[num], NULL)\n\n#define TIME_VAL_TO_MS(num) (((double)_timers[num].tv_sec*1000.0) + ((double)_timers[num].tv_usec/1000.0))\n\n\n#define BANK_OFFSET 3\n#define ROW_OFFSET 16\n#define CMD_OFFSET 4\n#define COL_OFFSET 10\n#define SIGNAL_OFFSET 6\n\n// The current instruction format is 32 bits wide. But we allocate\n// 64 bits (2 words) for each instruction to keep the hardware simple.\n// Having C_PCI_DATA_WIDTH of 64 performs better than 32 when sending\n// data that we read from the DRAM back to the host machine.\n// TODO: modify the hardware to support 32-bit instructions.\n#define INSTR_SIZE 2 //2 words\n\n#define NUM_ROWS 32768\n#define NUM_COLS 1024\n#define NUM_BANKS 8\n\ntypedef uint64_t Instruction;\ntypedef uint32_t uint;\n\n//DO NOT EDIT (unless you change the verilog code)\nenum class INSTR_TYPE {\n\tEND_OF_INSTRS = 0,\n\tSET_BUS_DIR = 1,\n\tWAIT = 4,\n\tDDR = 8\n};\n//END - DO NOT EDIT\n\nenum class BUSDIR {\n\tREAD = 0,\n\tWRITE = 2\n};\n\nenum class AUTO_PRECHARGE {\n\tNO_AP = 0,\n\tAP = 1\n};\n\nenum class PRE_TYPE {\n\tSINGLE = 0,\n\tALL = 1\n};\n\nenum class BURST_LENGTH {\n\tCHOP = 0,\n\tFIXED = 1\n};\n\nenum class REGISTER {\n\tTREFI = 2,\n\tTRFC = 3\n};\n\n\nclass InstructionSequence{\n\n\tpublic:\n\t\tInstructionSequence();\n\t\tInstructionSequence(const uint capacity);\n\t\tvirtual ~InstructionSequence();\n\n\t\tvoid insert(const Instruction c);\n\t\tvoid execute(fpga_t* fpga);\n\n\t\tuint size;\n\t\tInstruction* instrs;\n\tprivate:\n\t\tuint capacity;\n\t\tconst static uint init_cap = 256;\n};\n\n\nclass DramAddr{\n\n\tpublic:\n\t\tuint row;\n\t\tuint bank;\n\n\t\tDramAddr() : DramAddr(0, 0){}\n\t\tDramAddr(uint row, uint bank){ this->row = row; this->bank = bank;}\n};\n\nInstruction genACT(uint bank, uint row);\nInstruction genPRE(uint bank, PRE_TYPE pt = PRE_TYPE::SINGLE);\nInstruction genWR(uint bank, uint col, uint8_t pattern, AUTO_PRECHARGE ap = AUTO_PRECHARGE::NO_AP, BURST_LENGTH bl = BURST_LENGTH::FIXED);\nInstruction genRD(uint bank, uint col, AUTO_PRECHARGE ap = AUTO_PRECHARGE::NO_AP, BURST_LENGTH bl = BURST_LENGTH::FIXED);\nInstruction genWAIT(uint cycles);\nInstruction genBUSDIR(BUSDIR dir);\nInstruction genEND();\nInstruction genZQ();\nInstruction genREF();\nInstruction genREF_CONFIG(uint val, REGISTER r);\n\n\n#endif //SOFTMC_H\n" }, { "path": "sw/riffa_2.1/LICENSE", "content": "----------------------------------------------------------------------\nCopyright (c) 2016, The Regents of the University of California All\nrights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are\nmet:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n\n * Redistributions in binary form must reproduce the above\n copyright notice, this list of conditions and the following\n disclaimer in the documentation and/or other materials provided\n with the distribution.\n\n * Neither the name of The Regents of the University of California\n nor the names of its contributors may be used to endorse or\n promote products derived from this software without specific\n prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n\"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\nLIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\nA PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE\nUNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\nBUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\nOF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR\nTORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\nUSE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\nDAMAGE.\n----------------------------------------------------------------------\n" }, { "path": "sw/riffa_2.1/README.txt", "content": "To install RIFFA 2.0, find the instructions in the install directory for your\nos. The source directory contains all the source code for the drivers, sample\napplications, etc.\n\nYou can get started with your HDL design using a sample from the FPGA directory.\nIt contains example HDL designs with corresponding example software.\n\nFor further details, see the RIFFA 2.0 website at:\nhttp://cseweb.ucsd.edu/~mdjacobs \n\n\nRelease notes:\n\nVersion 2.0.2\n-------------\n\n- Fixed: Bug in Windows and Linux drivers that could report data sent/received \n before such data was confirmed.\n\n- Fixed: Updated common functions to avoid assigning input values.\n\n- Fixed: FIFO overflow error causing data corruption in tx_engine_upper and\n breaking the Xilinx Endpoint.\n\n- Fixed: Missing default cases in rx_port_reader, sg_list_requester, \n tx_engine_upper, and tx_port_writer.\n\n- Fixed: Bug in tx_engine_lower_128 corrupting s_axis_tx_tkeep, causing Xilinx\n PCIe endpoint core to shut down.\n\n- Fixed: Bug in tx_engine_upper_128 causing incomplete TX data timeouts.\n\n- Changed rx_engine to not block on non-posted TLPs. They're added to a FIFO and\n serviced in order. \n\n- Reset rx_port FIFOs before a receive transaction to avoid data corruption from\n replayed TLPs.\n\nVersion 2.0.1\n-------------\n\n- RIFFA 2.0.1 is a general release. This means we've tested it in a number of\n ways. Please let us know if you encounter a bug. \n\n- Neither the HDL nor the drivers from RIFFA 2.0.1 are backwards compatible with\n the components of any previous release of RIFFA.\n\n- RIFFA 2.0.1 consumes more resources than 2.0 beta. This is because 2.0.1 was\n rewritten to support scatter gather DMA, higher bandwidth, and appreciably \n more signal registering. The additional registering was included to help meet \n timing constraints. \n\n- The Windows driver is supported on Windows 7 32/64. Other Windows versions \n can be supported. The driver simply needs to be built for that target.\n\n- Debugging on Windows is difficult because there exists no system log file.\n Driver log messages are visible only to an attached kernel debugger. So to see\n any messages you'll need the Windows Development Kit debugger (WinDbg) or a \n small utility called DbgView. DbgView is a standalone kernel debug viewer that\n can be downloaded from Microsoft here:\n http://technet.microsoft.com/en-us/sysinternals/bb896647.aspx\n Run DbgView with administrator privileges and be sure to enable the following\n capture options: Capture Kernel, Capture Events, and Capture Verbose Kernel \n Output.\n\n- The Linux driver is supported on kernel version 2.6.27+. \n\n- The Java bindings make use of a native library (in order to connect Java JNI\n to the native library). Libraries for Linux and Windows for both 32/64 bit \n platforms have been compiled and included in the riffa.jar.\n\n- Removed the CHNL_RX_ERR signal from the channel interface. Error handling now\n ends the transaction gracefully. Errors can be easily detected by comparing\n the number of words received to the CHNL_RX_LEN amount. An error will cause\n CHNL_RX will go low prematurely and not provide the advertised amount of data.\n\n- Fixed: Bug in sg_list_requester which could cause an unbounded TLP request.\n\n- Fixed: Bug in tx_port_buffer_128 which could stall the TX transaction.\n\n" }, { "path": "sw/riffa_2.1/driver/linux/Makefile", "content": "# This software is Copyright © 2012 The Regents of the University of \n# California. All Rights Reserved.\n# \n# Permission to copy, modify, and distribute this software and its \n# documentation for educational, research and non-profit purposes, without fee, \n# and without a written agreement is hereby granted, provided that the above \n# copyright notice, this paragraph and the following three paragraphs appear in\n# all copies.\n# \n# Permission to make commercial use of this software may be obtained by \n# contacting:\n# Technology Transfer Office\n# 9500 Gilman Drive, Mail Code 0910\n# University of California\n# La Jolla, CA 92093-0910\n# (858) 534-5815\n# invent@ucsd.edu\n# \n# This software program and documentation are copyrighted by The Regents of the\n# University of California. The software program and documentation are supplied\n# \"as is\", without any accompanying services from The Regents. The Regents does\n# not warrant that the operation of the program will be uninterrupted or error-\n# free. The end-user understands that the program was developed for research \n# purposes and is advised not to rely exclusively on the program for any \n# reason.\n# \n# IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n# ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n# CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n# OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n# EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n# THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n# CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n# THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n# AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n# PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n# MODIFICATIONS.\n\n# Filename: Makefile\n# Version: 2.0\n# Description: Makefile for Linux PCIe device driver for RIFFA.\n# Author: Matthew Jacobsen\n# History: @mattj: Initial release. Version 2.0.\n\n# You must specify the following variables. You can leave the defaults if you\n# like, but make sure they will work in your system.\n# The VENDOR_ID _must_ match what is configured on your FPGA's PCIe endpoint \n# header. Xilinx has a VENDOR_ID = 10EE.\nNAME := riffa\nVENDOR_ID0 := 10EE\nVENDOR_ID1 := 1172\nMAJNUM := 100\n\n# Build variables\nKVER := $(shell uname -r)\nKDIR := /lib/modules/`uname -r`/build\nRHR := /etc/redhat-release\nLIB_SRCS := riffa.c\nLIB_OBJS := $(patsubst %.c,%.o,$(LIB_SRCS))\nLIB_HDR := riffa.h\nLIB_VER_MAJ := 1\nLIB_VER_MIN := 0\nLIB_VER := $(LIB_VER_MAJ).$(LIB_VER_MIN)\nDRVR_HDR := riffa_driver.h\nDBUGVAL := DBUG\n\nobj-m += $(NAME).o\n$(NAME)-y := riffa_driver.o circ_queue.o\n\n# Helper functions\ndefine assert\n $(if $1,,$(error Assertion failed: $2))\nendef\ndefine assert-not-null\n $(call assert,$($1),The variable \"$1\" is null, please specify it.)\nendef\ndefine assert-variables\n\t$(call assert-not-null,NAME)\n\t$(call assert-not-null,MAJNUM)\n\t$(call assert-not-null,VENDOR_ID0)\n\t$(call assert-not-null,VENDOR_ID1)\n\t@printf \"Compiling driver for kernel: %s with the following values\\n\" $(KVER)\n\t@printf \" NAME: '%s'\\n\" $(NAME)\n\t@printf \" MAJNUM: '%s'\\n\" $(MAJNUM)\n\t@printf \"VENDOR_ID0: '%s'\\n\" $(VENDOR_ID0)\n\t@printf \"VENDOR_ID1: '%s'\\n\" $(VENDOR_ID1)\n\t@printf \"\\n\"\nendef\n\nall: builddvr\ndebug: CC += -DDEBUG -g -Wno-error-implicit-function-declaration\ndebug: DBUGVAL = DEBUG\ndebug: builddvr\nbuilddvr: $(NAME).ko $(NAME).so.$(LIB_VER)\n\n$(NAME).ko: *.c *.h\n\t$(call assert-variables)\n\tsed -i 's/#define MAJOR_NUM [^\\n]*/#define MAJOR_NUM $(MAJNUM)/g' $(DRVR_HDR)\n\tsed -i 's/#define DEVICE_NAME [^\\n]*/#define DEVICE_NAME \"$(NAME)\"/g' $(DRVR_HDR)\n\tsed -i 's/#define VENDOR_ID0 [^\\n]*/#define VENDOR_ID0 0x$(VENDOR_ID0)/g' $(DRVR_HDR)\n\tsed -i 's/#define VENDOR_ID1 [^\\n]*/#define VENDOR_ID1 0x$(VENDOR_ID1)/g' $(DRVR_HDR)\n\tsed -i 's/#define DEBUG [^\\n]*/#define DBUG 1/g' $(DRVR_HDR)\n\tsed -i 's/#define DBUG [^\\n]*/#define $(DBUGVAL) 1/g' $(DRVR_HDR)\n\tmake -C $(KDIR) SUBDIRS=`pwd` modules\n\trm -rf $(LIB_OBJS)\n\n$(NAME).so.$(LIB_VER): $(LIB_OBJS)\n\t$(CC) -shared -Wno-error-implicit-function-declaration,-soname,lib$(NAME).so.$(LIB_VER_MAJ) -o lib$@ $^\n\n$(LIB_OBJS): $(LIB_SRCS)\n\t$(CC) -g -Wall -fPIC -c $^\n\nload: $(NAME).ko\n\tinsmod $(NAME).ko\n\t\nunload:\n\trmmod $(NAME)\n\nclean:\n\trm -Rf *.ko *.cmd *.o *.so *.so.* .*.cmd Module.symvers Module.markers modules.order *.mod.c .tmp_versions\n\nsetup:\n\tif [ -f \"$(RHR)\" ]; then yum install kernel-devel-`uname -r`;\\\n\telse apt-get install linux-headers-`uname -r`; fi\n\ninstall: $(NAME).so.$(LIB_VER) $(NAME).ko \n\tmkdir -p /lib/modules/$(KVER)/kernel/drivers/$(NAME)\n\tcp $(NAME).ko /lib/modules/$(KVER)/kernel/drivers/$(NAME)/\n\tif [ -f \"$(RHR)\" ]; then\\\n\t\tprintf \"%b\\n\" \"#!/bin/sh\\nexec /sbin/modprobe $(NAME) >/dev/null 2>&1\" > /etc/sysconfig/modules/$(NAME).modules;\\\n\t\tchmod 755 /etc/sysconfig/modules/$(NAME).modules;\\\n\telse\\\n\t\tif ! grep -Fxq \"$(NAME)\" /etc/modules; then echo \"$(NAME)\" >> /etc/modules; fi;\\\n\tfi\n\tprintf \"%b\\n\" \"KERNEL==\\\"$(NAME)\\\", MODE=\\\"777\\\", GROUP=\\\"root\\\"\" > /etc/udev/rules.d/99-$(NAME).rules\n\tprintf \"/usr/local/lib\\n\" > $(NAME).conf\n\tmv $(NAME).conf /etc/ld.so.conf.d/\n\tcp $(DRVR_HDR) /usr/local/include/\n\tcp $(LIB_HDR) /usr/local/include/\n\tmv lib$(NAME).so.1.0 /usr/local/lib\n\tln -sf /usr/local/lib/lib$(NAME).so.$(LIB_VER) /usr/local/lib/lib$(NAME).so.$(LIB_VER_MAJ)\n\tln -sf /usr/local/lib/lib$(NAME).so.$(LIB_VER) /usr/local/lib/lib$(NAME).so\n\tldconfig\n\tdepmod\n\nuninstall: \n\trm -f /usr/local/lib/lib$(NAME).so*\n\trm -f /usr/local/include/$(LIB_HDR)\n\trm -f /usr/local/include/$(DRVR_HDR)\n\trm -f /etc/ld.so.conf.d/$(NAME).conf\n\trm -rf /lib/modules/$(KVER)/kernel/drivers/$(NAME)\n\trm -f /etc/udev/rules.d/99-$(NAME).rules\n\tif [ -f \"$(RHR)\" ]; then rm -f /etc/sysconfig/modules/$(NAME).modules;\\\n\telse cp /etc/modules ./etc.modules.bak; sed -i '/$(NAME)/d' /etc/modules; fi\n\tldconfig\n\tdepmod\n\n\n" }, { "path": "sw/riffa_2.1/driver/linux/README.txt", "content": "You must build the Linux driver against the version of the Linux kernel you have\ninstalled. This will require the Linux kernel headers. After you've built the\ndriver you can install it in your system so that it loads at boot time. If the\ndriver is installed and there is a RIFFA 2.0.1 capable FPGA installed as well, \nthe driver will detect it. Output in the system log will provide additional \ninformation. This makefile will also build and install the C/C++ native library.\n\nEnsure you have the kernel headers installed:\n\nsudo make setup\n\nThis will attempt to install the kernel headers using your system's package\nmanager. You can skip this step if you've already installed the kernel headers.\n\nCompile the driver and C/C++ library:\n\nmake\n\nor \n\nmake debug\n\nUsing make debug will compile in code to output debug messages to the system log\nat runtime. These messages are useful when developing your design. However they\npollute your system log and incur some overhead. So you may want to install the\nnon-debug version after you've completed development.\n\nInstall the driver and library:\n\nsudo make install\n\nThe system will be configured to load the driver at boot time. The C/C++ library\nwill be installed in the default library path. The header files will be placed\nin the default include path. You will want to reboot after you've installed for\nthe driver to be (re)loaded.\n\nWhen compiling an application you should only need to include the \nheader file and link with -lriffa.\n" }, { "path": "sw/riffa_2.1/driver/linux/circ_queue.c", "content": "/*******************************************************************************\n * This software is Copyright © 2012 The Regents of the University of \n * California. All Rights Reserved.\n * \n * Permission to copy, modify, and distribute this software and its \n * documentation for educational, research and non-profit purposes, without fee, \n * and without a written agreement is hereby granted, provided that the above \n * copyright notice, this paragraph and the following three paragraphs appear in\n * all copies.\n * \n * Permission to make commercial use of this software may be obtained by \n * contacting:\n * Technology Transfer Office\n * 9500 Gilman Drive, Mail Code 0910\n * University of California\n * La Jolla, CA 92093-0910\n * (858) 534-5815\n * invent@ucsd.edu\n * \n * This software program and documentation are copyrighted by The Regents of the\n * University of California. The software program and documentation are supplied\n * \"as is\", without any accompanying services from The Regents. The Regents does\n * not warrant that the operation of the program will be uninterrupted or error-\n * free. The end-user understands that the program was developed for research \n * purposes and is advised not to rely exclusively on the program for any \n * reason.\n * \n * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n * THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n * MODIFICATIONS.\n */\n\n/*\n * Filename: circ_queue.c\n * Version: 1.0\n * Description: A lock-free single-producer circular queue implementation \n * modeled after the more elaborate C++ version from Faustino Frechilla at:\n * http://www.codeproject.com/Articles/153898/Yet-another-implementation-of-a-lock-free-circular\n * Author: Matthew Jacobsen\n * History: @mattj: Initial release. Version 1.0.\n */\n\n#include \n#include \"circ_queue.h\"\n\ncirc_queue * init_circ_queue(int len)\n{\n\tint i;\n\tcirc_queue * q;\n\n\tq = kzalloc(sizeof(circ_queue), GFP_KERNEL);\n\tif (q == NULL) {\n\t\tprintk(KERN_ERR \"Not enough memory to allocate circ_queue\");\n\t\treturn NULL;\n\t}\n\n\tatomic_set(&q->writeIndex, 0);\n\tatomic_set(&q->readIndex, 0);\n\tq->len = len;\n\n\tq->vals = (unsigned int**) kzalloc(len*sizeof(unsigned int*), GFP_KERNEL); \n\tif (q->vals == NULL) {\n\t\tprintk(KERN_ERR \"Not enough memory to allocate circ_queue array\");\n\t\treturn NULL;\n\t}\n\tfor (i = 0; i < len; i++) {\n\t\tq->vals[i] = (unsigned int*) kzalloc(2*sizeof(unsigned int), GFP_KERNEL);\n\t\tif (q->vals[i] == NULL) {\n\t\t\tprintk(KERN_ERR \"Not enough memory to allocate circ_queue array position\");\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\treturn q;\n}\n\n/**\n * Internal function to help count. Returns the queue size normalized position.\n */\nunsigned int queue_count_to_index(unsigned int count, unsigned int len)\n{\n\treturn (count % len);\n}\n\nint push_circ_queue(circ_queue * q, unsigned int val1, unsigned int val2)\n{\n\tunsigned int currReadIndex;\n\tunsigned int currWriteIndex;\n\n\tcurrWriteIndex = atomic_read(&q->writeIndex);\n\tcurrReadIndex = atomic_read(&q->readIndex);\n\tif (queue_count_to_index(currWriteIndex+1, q->len) == queue_count_to_index(currReadIndex, q->len)) {\n\t\t// The queue is full\n\t\treturn 1;\n\t}\n\n\t// Save the data into the queue\n\tq->vals[queue_count_to_index(currWriteIndex, q->len)][0] = val1;\n\tq->vals[queue_count_to_index(currWriteIndex, q->len)][1] = val2;\n\t// Increment atomically write index. Now a consumer thread can read\n\t// the piece of data that was just stored.\n\tatomic_inc(&q->writeIndex);\n\n\treturn 0;\n}\n\nint pop_circ_queue(circ_queue * q, unsigned int * val1, unsigned int * val2)\n{\n\tunsigned int currReadIndex;\n\tunsigned int currMaxReadIndex;\n\n\tdo\n\t{\n\t\tcurrReadIndex = atomic_read(&q->readIndex);\n\t\tcurrMaxReadIndex = atomic_read(&q->writeIndex);\n\t\tif (queue_count_to_index(currReadIndex, q->len) == queue_count_to_index(currMaxReadIndex, q->len)) {\n\t\t\t// The queue is empty or a producer thread has allocate space in the queue\n\t\t\t// but is waiting to commit the data into it\n\t\t\treturn 1;\n\t\t}\n\n\t\t// Retrieve the data from the queue\n\t\t*val1 = q->vals[queue_count_to_index(currReadIndex, q->len)][0];\n\t\t*val2 = q->vals[queue_count_to_index(currReadIndex, q->len)][1];\n\n\t\t// Try to perfrom now the CAS operation on the read index. If we succeed\n\t\t// label & val already contain what q->readIndex pointed to before we \n\t\t// increased it.\n\t\tif (atomic_cmpxchg(&q->readIndex, currReadIndex, currReadIndex+1) == currReadIndex) {\n\t\t\t// The lable & val were retrieved from the queue. Note that the\n\t\t\t// data inside the label or value arrays are not deleted.\n\t\t\treturn 0;\n\t\t}\n\n\t\t// Failed to retrieve the elements off the queue. Someone else must\n\t\t// have read the element stored at countToIndex(currReadIndex)\n\t\t// before we could perform the CAS operation. \n\t} while(1); // keep looping to try again!\n\n\treturn 1;\n}\n\nint circ_queue_empty(circ_queue * q)\n{\n\tunsigned int currReadIndex;\n\tunsigned int currMaxReadIndex;\n\n\tcurrReadIndex = atomic_read(&q->readIndex);\n\tcurrMaxReadIndex = atomic_read(&q->writeIndex);\n\tif (queue_count_to_index(currReadIndex, q->len) == queue_count_to_index(currMaxReadIndex, q->len)) {\n\t\t// The queue is empty or a producer thread has allocate space in the queue\n\t\t// but is waiting to commit the data into it\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\nint circ_queue_full(circ_queue * q)\n{\n\tunsigned int currReadIndex;\n\tunsigned int currWriteIndex;\n\n\tcurrWriteIndex = atomic_read(&q->writeIndex);\n\tcurrReadIndex = atomic_read(&q->readIndex);\n\tif (queue_count_to_index(currWriteIndex+1, q->len) == queue_count_to_index(currReadIndex, q->len)) {\n\t\t// The queue is full\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\nvoid free_circ_queue(circ_queue * q)\n{\n\tint i;\n\n\tif (q == NULL)\n\t\treturn;\n\n\tfor (i = 0; i < q->len; i++) { \n\t\tkfree(q->vals[i]); \n\t}\n\tkfree(q->vals);\n\tkfree(q);\n}\n\n" }, { "path": "sw/riffa_2.1/driver/linux/circ_queue.h", "content": "/*******************************************************************************\n * This software is Copyright © 2012 The Regents of the University of \n * California. All Rights Reserved.\n * \n * Permission to copy, modify, and distribute this software and its \n * documentation for educational, research and non-profit purposes, without fee, \n * and without a written agreement is hereby granted, provided that the above \n * copyright notice, this paragraph and the following three paragraphs appear in\n * all copies.\n * \n * Permission to make commercial use of this software may be obtained by \n * contacting:\n * Technology Transfer Office\n * 9500 Gilman Drive, Mail Code 0910\n * University of California\n * La Jolla, CA 92093-0910\n * (858) 534-5815\n * invent@ucsd.edu\n * \n * This software program and documentation are copyrighted by The Regents of the\n * University of California. The software program and documentation are supplied\n * \"as is\", without any accompanying services from The Regents. The Regents does\n * not warrant that the operation of the program will be uninterrupted or error-\n * free. The end-user understands that the program was developed for research \n * purposes and is advised not to rely exclusively on the program for any \n * reason.\n * \n * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n * THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n * MODIFICATIONS.\n */\n\n/*\n * Filename: circ_queue.h\n * Version: 1.0\n * Description: A lock-free single-producer circular queue implementation \n * modeled after the more elaborate C++ version from Faustino Frechilla at:\n * http://www.codeproject.com/Articles/153898/Yet-another-implementation-of-a-lock-free-circular\n * Author: Matthew Jacobsen\n * History: @mattj: Initial release. Version 1.0.\n */\n#ifndef CIRC_QUEUE_H\n#define CIRC_QUEUE_H\n\n#include \n\n/* Struct for the circular queue. */\nstruct circ_queue {\n\tatomic_t writeIndex;\n\tatomic_t readIndex;\n\tunsigned int ** vals;\n\tunsigned int len;\n};\ntypedef struct circ_queue circ_queue;\n\n/**\n * Initializes a circ_queue with depth/length len. Returns non-NULL on success, \n * NULL if there was a problem creating the queue.\n */\ncirc_queue * init_circ_queue(int len);\n\n/**\n * Pushes a pair of unsigned int values into the specified queue at the head. \n * Returns 0 on success, non-zero if there is no more space in the queue.\n */\nint push_circ_queue(circ_queue * q, unsigned int val1, unsigned int val2);\n\n/**\n * Pops a pair of unsigned int values out of the specified queue from the tail.\n * Returns 0 on success, non-zero if the queue is empty.\n */\nint pop_circ_queue(circ_queue * q, unsigned int * val1, unsigned int * val2);\n\n/**\n * Returns 1 if the circ_queue is empty, 0 otherwise. Note, this is not a \n * synchronized function. If another thread is accessing this circ_queue, the\n * return value may not be valid.\n */\nint circ_queue_empty(circ_queue * q);\n\n/**\n * Returns 1 if the circ_queue is full, 0 otherwise. Note, this is not a \n * synchronized function. If another thread is accessing this circ_queue, the\n * return value may not be valid.\n */\nint circ_queue_full(circ_queue * q);\n\n/**\n * Frees the resources associated with the specified circ_queue.\n */\nvoid free_circ_queue(circ_queue * q);\n\n#endif\n" }, { "path": "sw/riffa_2.1/driver/linux/riffa.c", "content": "/*******************************************************************************\n * This software is Copyright © 2012 The Regents of the University of \n * California. All Rights Reserved.\n * \n * Permission to copy, modify, and distribute this software and its \n * documentation for educational, research and non-profit purposes, without fee, \n * and without a written agreement is hereby granted, provided that the above \n * copyright notice, this paragraph and the following three paragraphs appear in\n * all copies.\n * \n * Permission to make commercial use of this software may be obtained by \n * contacting:\n * Technology Transfer Office\n * 9500 Gilman Drive, Mail Code 0910\n * University of California\n * La Jolla, CA 92093-0910\n * (858) 534-5815\n * invent@ucsd.edu\n * \n * This software program and documentation are copyrighted by The Regents of the\n * University of California. The software program and documentation are supplied\n * \"as is\", without any accompanying services from The Regents. The Regents does\n * not warrant that the operation of the program will be uninterrupted or error-\n * free. The end-user understands that the program was developed for research \n * purposes and is advised not to rely exclusively on the program for any \n * reason.\n * \n * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n * THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n * MODIFICATIONS.\n */\n\n/*\n * Filename: riffa.c\n * Version: 2.0\n * Description: Linux PCIe communications API for RIFFA.\n * Author: Matthew Jacobsen\n * History: @mattj: Initial release. Version 2.0.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \"riffa.h\"\n\nstruct fpga_t\n{\n\tint fd;\n\tint id;\n};\n\nfpga_t * fpga_open(int id) \n{\n\tfpga_t * fpga;\n\n\t// Allocate space for the fpga_dev\n\tfpga = (fpga_t *)malloc(sizeof(fpga_t));\n\tif (fpga == NULL)\n\t\treturn NULL;\n\tfpga->id = id;\t\n\n\t// Open the device file.\n\tfpga->fd = open(\"/dev/\" DEVICE_NAME, O_RDWR | O_SYNC);\n\tif (fpga->fd < 0) {\n\t\tfree(fpga); \n\t\treturn NULL;\n\t}\n\t\n\treturn fpga;\n}\n\nvoid fpga_close(fpga_t * fpga) \n{\n\t// Close the device file.\n\tclose(fpga->fd);\n\tfree(fpga);\n}\n\nint fpga_send(fpga_t * fpga, int chnl, void * data, int len, int destoff, \n\tint last, long long timeout)\n{\n\tfpga_chnl_io io;\n\n\tio.id = fpga->id;\n\tio.chnl = chnl;\n\tio.len = len;\n\tio.offset = destoff;\n\tio.last = last;\n\tio.timeout = timeout;\n\tio.data = (char *)data;\n\n\treturn ioctl(fpga->fd, IOCTL_SEND, &io);\n}\n\nint fpga_recv(fpga_t * fpga, int chnl, void * data, int len, long long timeout)\n{\n\tfpga_chnl_io io;\n\n\tio.id = fpga->id;\n\tio.chnl = chnl;\n\tio.len = len;\n\tio.timeout = timeout;\n\tio.data = (char *)data;\n\n\treturn ioctl(fpga->fd, IOCTL_RECV, &io);\n}\n\nvoid fpga_reset(fpga_t * fpga)\n{\n\tioctl(fpga->fd, IOCTL_RESET, fpga->id);\n}\n\nint fpga_list(fpga_info_list * list) {\n\tint fd;\n\tint rc;\n\n\tfd = open(\"/dev/\" DEVICE_NAME, O_RDWR | O_SYNC);\n\tif (fd < 0)\n\t\treturn fd;\n\trc = ioctl(fd, IOCTL_LIST, list);\n\tclose(fd);\n\treturn rc;\n}\n\n\n\n" }, { "path": "sw/riffa_2.1/driver/linux/riffa.h", "content": "/*******************************************************************************\n * This software is Copyright © 2012 The Regents of the University of \n * California. All Rights Reserved.\n * \n * Permission to copy, modify, and distribute this software and its \n * documentation for educational, research and non-profit purposes, without fee, \n * and without a written agreement is hereby granted, provided that the above \n * copyright notice, this paragraph and the following three paragraphs appear in\n * all copies.\n * \n * Permission to make commercial use of this software may be obtained by \n * contacting:\n * Technology Transfer Office\n * 9500 Gilman Drive, Mail Code 0910\n * University of California\n * La Jolla, CA 92093-0910\n * (858) 534-5815\n * invent@ucsd.edu\n * \n * This software program and documentation are copyrighted by The Regents of the\n * University of California. The software program and documentation are supplied\n * \"as is\", without any accompanying services from The Regents. The Regents does\n * not warrant that the operation of the program will be uninterrupted or error-\n * free. The end-user understands that the program was developed for research \n * purposes and is advised not to rely exclusively on the program for any \n * reason.\n * \n * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n * THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n * MODIFICATIONS.\n */\n\n/*\n * Filename: riffa.h\n * Version: 2.0\n * Description: Linux PCIe communications API for RIFFA.\n * Author: Matthew Jacobsen\n * History: @mattj: Initial release. Version 2.0.\n */\n\n#ifndef RIFFA_H\n#define RIFFA_H\n\n#include \"riffa_driver.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct fpga_t;\ntypedef struct fpga_t fpga_t;\n\n/**\n * Populates the fpga_info_list pointer with all FPGAs registered in the system.\n * Returns 0 on success, a negative value on error.\n */\nint fpga_list(fpga_info_list * list);\n\n/**\n * Initializes the FPGA specified by id. On success, returns a pointer to a \n * fpga_t struct. On error, returns NULL. Each FPGA must be opened before any \n * channels can be accessed. Once opened, any number of threads can use the \n * fpga_t struct.\n */\nfpga_t * fpga_open(int id);\n\n/**\n * Cleans up memory/resources for the FPGA specified by the fd descriptor.\n */\nvoid fpga_close(fpga_t * fpga);\n\n/**\n * Sends len words (4 byte words) from data to FPGA channel chnl using the \n * fpga_t struct. The FPGA channel will be sent len, destoff, and last. If last\n * is 1, the channel should interpret the end of this send as the end of a\n * transaction. If last is 0, the channel should wait for additional sends \n * before the end of the transaction. If timeout is non-zero, this call will \n * send data and wait up to timeout ms for the FPGA to respond (between\n * packets) before timing out. If timeout is zero, this call may block \n * indefinitely. Multiple threads sending on the same channel may result in \n * corrupt data or error. This function is thread safe across channels.\n * On success, returns the number of words sent. On error returns a negative \n * value. \n */\nint fpga_send(fpga_t * fpga, int chnl, void * data, int len, int destoff, \n\tint last, long long timeout);\n\n/**\n * Receives data from the FPGA channel chnl to the data pointer, using the \n * fpga_t struct. The FPGA channel can send any amount of data, so the data \n * array should be large enough to accommodate. The len parameter specifies the\n * actual size of the data buffer in words (4 byte words). The FPGA channel will\n * specify an offset which will determine where in the data array the data will\n * start being written. If the amount of data (plus offset) exceed the size of\n * the data array (len), then that data will be discarded. If timeout is \n * non-zero, this call will wait up to timeout ms for the FPGA to respond \n * (between packets) before timing out. If timeout is zero, this call may block \n * indefinitely. Multiple threads receiving on the same channel may result in \n * corrupt data or error. This function is thread safe across channels.\n * On success, returns the number of words written to the data array. On error \n * returns a negative value. \n */\nint fpga_recv(fpga_t * fpga, int chnl, void * data, int len, long long timeout);\n\n/**\n * Resets the state of the FPGA and all transfers across all channels. This is\n * meant to be used as an alternative to rebooting if an error occurs while \n * sending/receiving. Calling this function while other threads are sending or\n * receiving will result in unexpected behavior.\n */\nvoid fpga_reset(fpga_t * fpga);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "sw/riffa_2.1/driver/linux/riffa_driver.c", "content": "/*******************************************************************************\n * This software is Copyright © 2012 The Regents of the University of \n * California. All Rights Reserved.\n * \n * Permission to copy, modify, and distribute this software and its \n * documentation for educational, research and non-profit purposes, without fee, \n * and without a written agreement is hereby granted, provided that the above \n * copyright notice, this paragraph and the following three paragraphs appear in\n * all copies.\n * \n * Permission to make commercial use of this software may be obtained by \n * contacting:\n * Technology Transfer Office\n * 9500 Gilman Drive, Mail Code 0910\n * University of California\n * La Jolla, CA 92093-0910\n * (858) 534-5815\n * invent@ucsd.edu\n * \n * This software program and documentation are copyrighted by The Regents of the\n * University of California. The software program and documentation are supplied\n * \"as is\", without any accompanying services from The Regents. The Regents does\n * not warrant that the operation of the program will be uninterrupted or error-\n * free. The end-user understands that the program was developed for research \n * purposes and is advised not to rely exclusively on the program for any \n * reason.\n * \n * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n * THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, \n * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n * MODIFICATIONS.\n */\n\n/*\n * Filename: riffa_driver.c\n * Version: 2.0\n * Description: Linux PCIe device driver for RIFFA. Uses Linux kernel APIs in\n * version 2.6.27+ (tested on version 2.6.32 - 3.3.0).\n * Author: Matthew Jacobsen\n * History: @mattj: Initial release. Version 2.0.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \"riffa_driver.h\"\n#include \"circ_queue.h\"\n\nMODULE_LICENSE(\"Dual BSD/GPL\");\nMODULE_DESCRIPTION(\"PCIe driver for RIFFA, Linux (2.6.27+)\");\nMODULE_AUTHOR(\"Matt Jacobsen, Patrick Lai\");\n\n#ifndef __devinit\n#define __devinit\n#define __devexit\n#define __devexit_p\n#endif\n\n#define CHNL_REG(c, o) ((c<<4) + o)\n#if !defined(__LP64__) && !defined(_LP64)\n#define BUILD_32 1\n#endif\n\nstruct sg_mapping {\n\tstruct page ** pages;\n\tstruct scatterlist * sgl;\n\tenum dma_data_direction direction;\n\tint num_sg;\n\tunsigned long num_pages;\n\tunsigned long long length;\n\tunsigned long long overflow;\n};\n\nstruct chnl_dir {\n\twait_queue_head_t waitq;\n\tstruct circ_queue * msgs;\n\tvoid * buf_addr;\n\tdma_addr_t buf_hw_addr;\n\tstruct sg_mapping * sg_map_0;\n\tstruct sg_mapping * sg_map_1;\n};\n\nstruct fpga_state {\n\tstruct pci_dev * dev;\n\tunsigned long long irq;\n\tvoid __iomem *bar0;\n\tunsigned long long bar0_addr;\n\tunsigned long long bar0_len;\n\tunsigned long long bar0_flags; \n\tatomic_t intr_disabled;\n\tvoid * spill_buf_addr;\n\tdma_addr_t spill_buf_hw_addr;\n\tint num_sg;\n\tint sg_buf_size;\n\tint id;\n\tchar name[16];\n\tint vendor_id;\n\tint device_id;\n\tint num_chnls;\n\tstruct chnl_dir ** recv;\n\tstruct chnl_dir ** send;\n};\n\n// Global variables (to this file only)\nstatic struct class * mymodule_class;\nstatic dev_t devt;\nstatic atomic_t used_fpgas[NUM_FPGAS];\nstatic struct fpga_state * fpgas[NUM_FPGAS];\n\n///////////////////////////////////////////////////////\n// MEMORY ALLOCATION & HELPER FUNCTIONS\n///////////////////////////////////////////////////////\n\n/** \n * Returns the value at the specified address.\n */\nstatic inline unsigned int read_reg(struct fpga_state * sc, int offset)\n{\n\treturn readl(sc->bar0 + (offset<<2));\n}\n\n/** \n * Writes the value to the specified address.\n */\nstatic inline void write_reg(struct fpga_state * sc, int offset, unsigned int val)\n{\n\twritel(val, sc->bar0 + (offset<<2));\n}\n\n#ifdef BUILD_32\n/**\n * Needed for 32 bit OS because dma_map_sg macro eventually does some 64 bit\n * division.\n */\nunsigned long long __udivdi3(unsigned long long num, unsigned long long den)\n{\n\tdo_div(num, den);\n\treturn num;\n}\n#endif\n\n///////////////////////////////////////////////////////\n// INTERRUPT HANDLER\n///////////////////////////////////////////////////////\n\n/**\n * Reads the interrupt vector and processes it. If processing VECT0, off will\n * be 0. If processing VECT1, off will be 6.\n */\nstatic inline void process_intr_vector(struct fpga_state * sc, int off, \n\tunsigned int vect)\n{\n\t// VECT_0/VECT_1 are organized from right to left (LSB to MSB) as:\n\t// [ 0] TX_TXN\t\t\tfor channel 0 in VECT_0, channel 6 in VECT_1\n\t// [ 1] TX_SG_BUF_RECVD\tfor channel 0 in VECT_0, channel 6 in VECT_1\n\t// [ 2] TX_TXN_DONE\t\tfor channel 0 in VECT_0, channel 6 in VECT_1\n\t// [ 3] RX_SG_BUF_RECVD\tfor channel 0 in VECT_0, channel 6 in VECT_1\n\t// [ 4] RX_TXN_DONE\t\tfor channel 0 in VECT_0, channel 6 in VECT_1\n\t// ...\n\t// [25] TX_TXN\t\t\tfor channel 5 in VECT_0, channel 11 in VECT_1\n\t// [26] TX_SG_BUF_RECVD\tfor channel 5 in VECT_0, channel 11 in VECT_1\n\t// [27] TX_TXN_DONE\t\tfor channel 5 in VECT_0, channel 11 in VECT_1\n\t// [28] RX_SG_BUF_RECVD\tfor channel 5 in VECT_0, channel 11 in VECT_1\n\t// [29] RX_TXN_DONE\t\tfor channel 5 in VECT_0, channel 11 in VECT_1\n\t// Positions 30 - 31 in both VECT_0 and VECT_1 are zero.\n\n\tunsigned int offlast;\n\tunsigned int len;\n\tint recv;\n\tint send;\n\tint chnl;\n\tint i;\n\n//printk(KERN_INFO \"riffa: intrpt_handler received:%08x\\n\", vect);\n\tif (vect & 0xC0000000) {\n\t\tprintk(KERN_ERR \"riffa: fpga:%d, received bad interrupt vector:%08x\\n\", sc->id, vect);\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < 6 && (i+off) < sc->num_chnls; ++i) {\n\t\tchnl = i + off;\n\t\trecv = 0; \n\t\tsend = 0; \n\n\t\t// TX (PC receive) scatter gather buffer is read.\n\t\tif (vect & (1<<((5*i)+1))) { \n\t\t\trecv = 1; \n\t\t\t// Keep track so the thread can handle this.\n\t\t\tif (push_circ_queue(sc->recv[chnl]->msgs, EVENT_SG_BUF_READ, 0)) {\n\t\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, recv sg buf read msg queue full\\n\", sc->id, chnl);\n\t\t\t}\n\t\t\tDEBUG_MSG(KERN_INFO \"riffa: fpga:%d chnl:%d, recv sg buf read\\n\", sc->id, chnl);\n\t\t}\n\n\t\t// TX (PC receive) transaction done.\n\t\tif (vect & (1<<((5*i)+2))) { \n\t\t\trecv = 1; \n\t\t\t// Read the transferred amount.\n\t\t\tlen = read_reg(sc, CHNL_REG(chnl, TX_TNFR_LEN_REG_OFF));\n\t\t\t// Notify the thread.\n\t\t\tif (push_circ_queue(sc->recv[chnl]->msgs, EVENT_TXN_DONE, len)) {\n\t\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, recv txn done msg queue full\\n\", sc->id, chnl);\n\t\t\t}\n\t\t\tDEBUG_MSG(KERN_INFO \"riffa: fpga:%d chnl:%d, recv txn done\\n\", sc->id, chnl);\n\t\t}\n\n\t\t// New TX (PC receive) transaction.\n\t\tif (vect & (1<<((5*i)+0))) { \n\t\t\trecv = 1; \n\t\t\t// Read the offset/last and length\n\t\t\tofflast = read_reg(sc, CHNL_REG(chnl, TX_OFFLAST_REG_OFF));\n\t\t\tlen = read_reg(sc, CHNL_REG(chnl, TX_LEN_REG_OFF));\n\t\t\t// Keep track of this transaction\n\t\t\tif (push_circ_queue(sc->recv[chnl]->msgs, EVENT_TXN_OFFLAST, offlast)) {\n\t\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, recv txn offlast msg queue full\\n\", sc->id, chnl);\n\t\t\t}\n\t\t\tif (push_circ_queue(sc->recv[chnl]->msgs, EVENT_TXN_LEN, len)) {\n\t\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, recv txn len msg queue full\\n\", sc->id, chnl);\n\t\t\t}\n\t\t\tDEBUG_MSG(KERN_INFO \"riffa: fpga:%d chnl:%d, recv txn (len:%d off:%d last:%d)\\n\", sc->id, chnl, len, (offlast>>1), (offlast & 0x1));\n\t\t}\n\n\t\t// RX (PC send) scatter gather buffer is read.\n\t\tif (vect & (1<<((5*i)+3))) { \n\t\t\tsend = 1; \n\t\t\t// Keep track so the thread can handle this.\n\t\t\tif (push_circ_queue(sc->send[chnl]->msgs, EVENT_SG_BUF_READ, 0)) {\n\t\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, send sg buf read msg queue full\\n\", sc->id, chnl);\n\t\t\t}\n\t\t\tDEBUG_MSG(KERN_INFO \"riffa: fpga:%d chnl:%d, send sg buf read\\n\", sc->id, chnl);\n\t\t}\n\n\t\t// RX (PC send) transaction done.\n\t\tif (vect & (1<<((5*i)+4))) {\n\t\t\tsend = 1; \n\t\t\t// Read the transferred amount.\n\t\t\tlen = read_reg(sc, CHNL_REG(chnl, RX_TNFR_LEN_REG_OFF));\n\t\t\t// Notify the thread.\n\t\t\tif (push_circ_queue(sc->send[chnl]->msgs, EVENT_TXN_DONE, len)) {\n\t\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, send txn done msg queue full\\n\", sc->id, chnl);\n\t\t\t}\n\t\t\tDEBUG_MSG(KERN_INFO \"riffa: fpga:%d chnl:%d, send txn done\\n\", sc->id, chnl);\n\t\t}\n\n\t\t// Wake up the thread?\n\t\tif (recv)\n\t\t\twake_up(&sc->recv[chnl]->waitq);\n\t\tif (send)\n\t\t wake_up(&sc->send[chnl]->waitq);\n\t}\n}\n\n/**\n * Interrupt handler for all interrupts on all files. Reads data/values\n * from FPGA and wakes up waiting threads to process the data. Always returns\n * IRQ_HANDLED.\n */\nstatic irqreturn_t intrpt_handler(int irq, void *dev_id) \n{\n\tunsigned int vect0;\n\tunsigned int vect1;\n\tstruct fpga_state * sc;\n\n\tsc = (struct fpga_state *)dev_id;\n\tvect0 = 0;\n\tvect1 = 0;\n\n\tif (sc == NULL) {\n\t\tprintk(KERN_ERR \"riffa: invalid fpga_state pointer\\n\");\n\t\treturn IRQ_HANDLED;\n\t}\n\n\tif (!atomic_read(&sc->intr_disabled)) {\n\t\t// Read the interrupt vector(s):\n\t\tvect0 = read_reg(sc, IRQ_REG0_OFF);\n\t\tif (sc->num_chnls > 6)\n\t\t\tvect1 = read_reg(sc, IRQ_REG1_OFF);\n\n\t\t// Process the vector(s)\n\t\tprocess_intr_vector(sc, 0, vect0);\n\t\tif (sc->num_chnls > 6)\n\t\t\tprocess_intr_vector(sc, 6, vect1);\n\t}\n\n\treturn IRQ_HANDLED;\n}\n\n\n///////////////////////////////////////////////////////\n// FILE OPERATION HANDLERS\n///////////////////////////////////////////////////////\n\n/**\n * Creates and returns a struct_sg_mapping that holds all the data for the user\n * pages that have been mapped into a scatterlist array. Assumes the user data\n * is 32 bit word aligned. Up to length bytes from the udata pointer will be\n * mapped. After all length bytes are mapped, up to overflow bytes will be\n * mapped using the common spill buffer for the channel. The overflow is used\n * if we run out of space in the supplied udata pointer.\n */\nstatic inline struct sg_mapping * fill_sg_buf(struct fpga_state * sc, int chnl, \n\tvoid * sg_buf, unsigned long udata, unsigned long long length, \n\tunsigned long long overflow, enum dma_data_direction direction) {\n\tconst char * dir = (direction == DMA_TO_DEVICE ? \"send\" : \"recv\");\n\tstruct sg_mapping * sg_map;\n\tstruct page ** pages = NULL;\n\tstruct scatterlist * sgl = NULL;\n\tstruct scatterlist * sg;\n\tunsigned long num_pages_reqd = 0;\n\tlong num_pages = 0;\n\tunsigned int fp_offset;\n\tunsigned int len;\n\tunsigned int hw_len;\n\tdma_addr_t hw_addr;\n\tunsigned long long len_rem = length;\n\tunsigned long long overflow_rem = overflow;\n\tunsigned int * sg_buf_ptr = (unsigned int *)sg_buf;\n\tint num_sg = 0;\n\tint i;\n\n\t// Create the sg_mapping struct.\n\tif ((sg_map = (struct sg_mapping *)kmalloc(sizeof(*sg_map), GFP_KERNEL)) == NULL) {\n\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, %s could not allocate memory for sg_mapping struct\\n\", sc->id, chnl, dir);\n\t\treturn NULL;\n\t}\n\n\tif (length > 0) {\n\t\t// Create the pages array.\n\t\tnum_pages_reqd = ((udata + length - 1)>>PAGE_SHIFT) - (udata>>PAGE_SHIFT) + 1;\n\t\tnum_pages_reqd = (num_pages_reqd > sc->num_sg ? sc->num_sg : num_pages_reqd);\n\t\tif ((pages = kmalloc(num_pages_reqd * sizeof(*pages), GFP_KERNEL)) == NULL) {\n\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, %s could not allocate memory for pages array\\n\", sc->id, chnl, dir);\n\t\t\tkfree(sg_map);\n\t\t\treturn NULL;\n\t\t}\n\n\t\t// Page in the user pages.\n\t\tdown_read(¤t->mm->mmap_sem);\n\t\tnum_pages = get_user_pages(current, current->mm, udata, num_pages_reqd, 1, 0, pages, NULL);\n\t\tup_read(¤t->mm->mmap_sem);\n\t\tif (num_pages <= 0) {\n\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, %s unable to pin any pages in memory\\n\", sc->id, chnl, dir);\n\t\t\tkfree(pages);\n\t\t\tkfree(sg_map);\n\t\t\treturn NULL;\n\t\t}\n\n\t\t// Create the scatterlist array.\n\t\tif ((sgl = kcalloc(num_pages, sizeof(*sgl), GFP_KERNEL)) == NULL) {\n\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, %s could not allocate memory for scatterlist array\\n\", sc->id, chnl, dir);\n\t\t\tfor (i = 0; i < num_pages; ++i)\n\t\t\t\tpage_cache_release(pages[i]);\n\t\t\tkfree(pages);\n\t\t\tkfree(sg_map);\n\t\t\treturn NULL;\n\t\t}\n\n\t\t// Set the scatterlist values\n\t\tfp_offset = (udata & (~PAGE_MASK));\n\t\tsg_init_table(sgl, num_pages);\n\t\tfor (i = 0; i < num_pages; ++i) {\n\t\t\tlen = ((fp_offset + len_rem) > PAGE_SIZE ? (PAGE_SIZE - fp_offset) : len_rem);\n\t\t\tsg_set_page(&sgl[i], pages[i], len, fp_offset);\n\t\t\tlen_rem -= len;\n\t\t\tfp_offset = 0;\n\t\t}\n\n\t\t// Map the scatterlist values and write to the common buffer area\n\t\tnum_sg = dma_map_sg(&sc->dev->dev, sgl, num_pages, direction);\n\t\tfor_each_sg(sgl, sg, num_sg, i) {\n\t\t\thw_addr = sg_dma_address(sg);\n\t\t\thw_len = sg_dma_len(sg);\n\t\t\tsg_buf_ptr[(i*4)+0] = (hw_addr & 0xFFFFFFFF);\n\t\t\tsg_buf_ptr[(i*4)+1] = ((hw_addr>>32) & 0xFFFFFFFF);\n\t\t\tsg_buf_ptr[(i*4)+2] = hw_len>>2; // Words!\n\t\t}\n\t}\n\n\t// Provide scatter gather mappings for overflow data (all in spill common buffer)\n\twhile (len_rem == 0 && overflow_rem > 0 && num_sg < sc->num_sg) {\n\t\tsg_buf_ptr[(num_sg*4)+0] = (sc->spill_buf_hw_addr & 0xFFFFFFFF);\n\t\tsg_buf_ptr[(num_sg*4)+1] = ((sc->spill_buf_hw_addr>>32) & 0xFFFFFFFF);\n\t\tsg_buf_ptr[(num_sg*4)+2] = SPILL_BUF_SIZE>>2; // Words!\n\t\tnum_sg++;\n\t\toverflow_rem -= (SPILL_BUF_SIZE > overflow ? overflow : SPILL_BUF_SIZE);\n\t}\n\n\t// Populate the number of bytes mapped and other sg data\n\tsg_map->direction = direction;\n\tsg_map->num_pages = num_pages;\n\tsg_map->num_sg = num_sg;\n\tsg_map->length = (length - len_rem);\n\tsg_map->overflow = (overflow - overflow_rem);\n\tsg_map->pages = pages;\n\tsg_map->sgl = sgl;\n\n\treturn sg_map;\n}\n\n/**\n * Frees the scatterlist mappings in the struct sg_mapping pointer and frees all\n * corresponding structs.\n */\nstatic inline void free_sg_buf(struct fpga_state * sc, struct sg_mapping * sg_map) {\n\tint i;\n\n\tif (sg_map == NULL)\n\t\treturn;\n\n\t// Unmap the pages.\n\tif (sg_map->sgl != NULL)\n\t\tdma_unmap_sg(&sc->dev->dev, sg_map->sgl, sg_map->num_pages, sg_map->direction);\n\n\t// Free the pages (mark dirty if necessary).\n\tif (sg_map->pages != NULL) {\n\t\tif (sg_map->direction == DMA_FROM_DEVICE) {\n\t\t\tfor (i = 0; i < sg_map->num_pages; ++i) {\n\t\t\t\tif (!PageReserved(sg_map->pages[i]))\n\t\t\t\t\tSetPageDirty(sg_map->pages[i]);\n\t\t\t\tpage_cache_release(sg_map->pages[i]);\n\t\t\t}\n\t\t}\n\t\telse {\n\t\t\tfor (i = 0; i < sg_map->num_pages; ++i) {\n\t\t\t\tpage_cache_release(sg_map->pages[i]);\n\t\t\t}\n\t\t}\n\t}\n\n\t// Free the structures.\n\tif (sg_map->pages != NULL)\n\t\tkfree(sg_map->pages);\n\tif (sg_map->sgl != NULL)\n\t\tkfree(sg_map->sgl);\n\tkfree(sg_map);\n}\n\n/**\n * Reads data from the FPGA. Will block until all the data is received from the\n * FPGA unless timeout is non-zero. If timeout is non-zero, the function will \n * block until all the data is received or until the timeout expires. Received \n * data will be written directly into the user buffer, bufp, by the DMA process\n * (using scatter gather). Up to len words (each word == 32 bits) will be \n * written. On success, the number of words received are returned. On error, \n * returns a negative value. \n */\nstatic inline unsigned int chnl_recv(struct fpga_state * sc, int chnl,\n\tchar __user * bufp, unsigned int len, unsigned long long timeout)\n{\n\tstruct sg_mapping * sg_map;\n\tlong tymeouto;\n\tlong tymeout;\n\tint nomsg;\n\tunsigned int msg_type;\n\tunsigned int msg;\n\tint last = -1;\n\tunsigned long long offset = 0;\n\tunsigned long long length = 0;\n\tunsigned long long overflow = 0;\n\tunsigned long long capacity = (((unsigned long long)len)<<2);\n\tunsigned long long recvd = 0;\n\tunsigned long udata = (unsigned long)bufp;\n\tunsigned long max_ptr;\n\n\tDEFINE_WAIT(wait);\n\n\t// Validate the parameters.\n\tif (chnl >= sc->num_chnls || chnl < 0) {\n\t\tprintk(KERN_INFO \"riffa: fpga:%d chnl:%d, recv channel invalid!\\n\", sc->id, chnl);\n\t\treturn 0;\n\t}\n\tif (udata & 0x3) {\n\t\tprintk(KERN_INFO \"riffa: fpga:%d chnl:%d, recv user buffer must be 32 bit word aligned!\\n\", sc->id, chnl);\n\t\treturn -EINVAL;\n\t}\n\n\t// Convert timeout to jiffies.\n\ttymeout = (timeout == 0 ? MAX_SCHEDULE_TIMEOUT : (timeout * HZ/1000 > LONG_MAX ? LONG_MAX : timeout * HZ/1000));\n\ttymeouto = tymeout;\n\n\t// Initialize the sg_maps\n\tsc->recv[chnl]->sg_map_0 = NULL;\n\tsc->recv[chnl]->sg_map_1 = NULL;\n\n\t// Continue until we get a message or timeout.\n\twhile (1) {\n\t\twhile ((nomsg = pop_circ_queue(sc->recv[chnl]->msgs, &msg_type, &msg))) {\n\t\t\tprepare_to_wait(&sc->recv[chnl]->waitq, &wait, TASK_INTERRUPTIBLE);\n\t\t\t// Another check before we schedule.\n\t\t\tif ((nomsg = pop_circ_queue(sc->recv[chnl]->msgs, &msg_type, &msg)))\n\t\t\t\ttymeout = schedule_timeout(tymeout);\n\t\t\tfinish_wait(&sc->recv[chnl]->waitq, &wait);\n\t\t\tif (signal_pending(current)) {\n\t\t\t\tfree_sg_buf(sc, sc->recv[chnl]->sg_map_0);\n\t\t\t\tfree_sg_buf(sc, sc->recv[chnl]->sg_map_1);\n\t\t\t\treturn -ERESTARTSYS;\n\t\t\t}\n\t\t\tif (!nomsg)\n\t\t\t\tbreak;\n\t\t\tif (tymeout == 0) {\n\t\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, recv timed out\\n\", sc->id, chnl);\n\t\t\t\tfree_sg_buf(sc, sc->recv[chnl]->sg_map_0);\n\t\t\t\tfree_sg_buf(sc, sc->recv[chnl]->sg_map_1);\n\t\t\t\treturn (unsigned int)(recvd>>2);\n\t\t\t}\n\t\t}\n\t\ttymeout = tymeouto;\n\n\t\t// Process the message.\n\t\tswitch (msg_type) {\n\t\tcase EVENT_TXN_OFFLAST:\n\t\t\t// Read the offset and last flags (always before reading length)\n\t\t\toffset = (((unsigned long long)(msg>>1))<<2);\n\t\t\tlast = (msg & 0x1);\n\t\t\tbreak;\n\n\t\tcase EVENT_TXN_LEN:\n\t\t\t// Read the length\n\t\t\tlength = (((unsigned long long)msg)<<2);\n\t\t\trecvd = 0;\n\t\t\toverflow = 0;\n\t\t\t// Check for address overflow\n\t\t\tmax_ptr = (unsigned long)(udata + offset + length - 1);\n\t\t\tif (max_ptr < udata) {\n\t\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, recv pointer address overflow\\n\", sc->id, chnl);\n\t\t\t\toverflow = length;\n\t\t\t\tlength = 0;\n\t\t\t}\n\t\t\t// Check for capacity overflow\n\t\t\tif ((offset + length) > capacity) {\n\t\t\t\tif (offset > capacity) {\n\t\t\t\t\toverflow = length;\n\t\t\t\t\tlength = 0;\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\toverflow = length + offset - capacity;\n\t\t\t\t\tlength = capacity - offset;\n\t\t\t\t}\n\t\t\t}\n\t\t\t// Use the recv common buffer to share the scatter gather elements.\n\t\t\tif (length > 0 || overflow > 0) {\n\t\t\t\tudata = udata + offset;\n\t\t\t\tsg_map = fill_sg_buf(sc, chnl, sc->recv[chnl]->buf_addr, udata, length, overflow, DMA_FROM_DEVICE);\n\t\t\t\tif (sg_map == NULL || sg_map->num_sg == 0)\n\t\t\t\t\treturn (unsigned int)(recvd>>2);\n\t\t\t\t// Update based on the sg_mapping\n\t\t\t\tudata += sg_map->length;\n\t\t\t\tlength -= sg_map->length;\n\t\t\t\toverflow -= sg_map->overflow;\n\t\t\t\tsc->recv[chnl]->sg_map_1 = sg_map;\n\t\t\t\t// Let FPGA know about the scatter gather buffer.\n\t\t\t\twrite_reg(sc, CHNL_REG(chnl, TX_SG_ADDR_LO_REG_OFF), (sc->recv[chnl]->buf_hw_addr & 0xFFFFFFFF));\n\t\t\t\twrite_reg(sc, CHNL_REG(chnl, TX_SG_ADDR_HI_REG_OFF), ((sc->recv[chnl]->buf_hw_addr>>32) & 0xFFFFFFFF));\n\t\t\t\twrite_reg(sc, CHNL_REG(chnl, TX_SG_LEN_REG_OFF), 4 * sg_map->num_sg);\n\t\t\t\tDEBUG_MSG(KERN_INFO \"riffa: fpga:%d chnl:%d, recv sg buf populated, %d sent\\n\", sc->id, chnl, sg_map->num_sg);\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase EVENT_SG_BUF_READ:\n\t\t\t// Ignore if we haven't received offlast/len.\n\t\t\tif (last == -1)\n\t\t\t\tbreak;\n\t\t\t// Release the previous scatter gather data.\n\t\t\tif (sc->recv[chnl]->sg_map_0 != NULL)\n\t\t\t\trecvd += sc->recv[chnl]->sg_map_0->length;\n\t\t\tfree_sg_buf(sc, sc->recv[chnl]->sg_map_0);\n\t\t\tsc->recv[chnl]->sg_map_0 = NULL;\n\t\t\t// Populate the common buffer with more scatter gather data?\n\t\t\tif (length > 0 || overflow > 0) {\n\t\t\t\tsg_map = fill_sg_buf(sc, chnl, sc->recv[chnl]->buf_addr, udata, length, overflow, DMA_FROM_DEVICE);\n\t\t\t\tif (sg_map == NULL || sg_map->num_sg == 0) {\n\t\t\t\t\tfree_sg_buf(sc, sc->recv[chnl]->sg_map_0);\n\t\t\t\t\tfree_sg_buf(sc, sc->recv[chnl]->sg_map_1);\n\t\t\t\t\treturn (unsigned int)(recvd>>2);\n\t\t\t\t}\n\t\t\t\t// Update based on the sg_mapping\n\t\t\t\tudata += sg_map->length;\n\t\t\t\tlength -= sg_map->length;\n\t\t\t\toverflow -= sg_map->overflow;\n\t\t\t\tsc->recv[chnl]->sg_map_0 = sc->recv[chnl]->sg_map_1;\n\t\t\t\tsc->recv[chnl]->sg_map_1 = sg_map;\n\t\t\t\twrite_reg(sc, CHNL_REG(chnl, TX_SG_ADDR_LO_REG_OFF), (sc->recv[chnl]->buf_hw_addr & 0xFFFFFFFF));\n\t\t\t\twrite_reg(sc, CHNL_REG(chnl, TX_SG_ADDR_HI_REG_OFF), ((sc->recv[chnl]->buf_hw_addr>>32) & 0xFFFFFFFF));\n\t\t\t\twrite_reg(sc, CHNL_REG(chnl, TX_SG_LEN_REG_OFF), 4 * sg_map->num_sg);\n\t\t\t\tDEBUG_MSG(KERN_INFO \"riffa: fpga:%d chnl:%d, recv sg buf populated, %d sent\\n\", sc->id, chnl, sg_map->num_sg);\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase EVENT_TXN_DONE:\n\t\t\t// Ignore if we haven't received offlast/len.\n\t\t\tif (last == -1)\n\t\t\t\tbreak;\n\t\t\t// Update with the true value of words transferred.\n\t\t\trecvd = (((unsigned long long)msg)<<2);\n\t\t\t// Return if this was the last transaction.\n\t\t\tfree_sg_buf(sc, sc->recv[chnl]->sg_map_0);\n\t\t\tfree_sg_buf(sc, sc->recv[chnl]->sg_map_1);\n\t\t\tsc->recv[chnl]->sg_map_0 = NULL;\n\t\t\tsc->recv[chnl]->sg_map_1 = NULL;\n\t\t\tDEBUG_MSG(KERN_INFO \"riffa: fpga:%d chnl:%d, received %d words\\n\", sc->id, chnl, (unsigned int)(recvd>>2));\n\t\t\tif (last)\n\t\t\t\treturn (unsigned int)(recvd>>2);\n\t\t\tbreak;\n\n\t\tdefault: \n\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, received unknown msg: %08x\\n\", sc->id, chnl, msg);\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn 0;\n}\n\n/**\n * Writes data to the FPGA channel specified. Will block until all the data is \n * sent to the FPGA unless a non-zero timeout is configured. If timeout is non-\n * zero, then the function will block until all data is sent or when the timeout\n * ms elapses. User data from the bufp pointer will be sent, up to len words\n * (each word == 32 bits). The channel will be told how much data to expect and \n * at what offset. If last == 1, the FPGA channel will recognize this \n * transaction as complete after sending. If last == 0, the FPGA channel will \n * expect additional transactions. On success, returns the number of words sent. \n * On error, returns a negative value. \n */\nstatic inline unsigned int chnl_send(struct fpga_state * sc, int chnl,\n\tconst char __user * bufp, unsigned int len, unsigned int offset, \n\tunsigned int last, unsigned long long timeout)\n{\n\tstruct sg_mapping * sg_map;\n\tlong tymeouto;\n\tlong tymeout;\n\tint nomsg;\n\tunsigned int msg_type;\n\tunsigned int msg;\n\tunsigned long long sent = 0;\n\tunsigned long long length = (((unsigned long long)len)<<2);\n\tunsigned long udata = (unsigned long)bufp;\n\tunsigned long max_ptr;\n\n\tDEFINE_WAIT(wait);\n\n\t// Validate the parameters.\n\tif (chnl >= sc->num_chnls || chnl < 0) {\n\t\tprintk(KERN_INFO \"riffa: fpga:%d chnl:%d, send channel invalid!\\n\", sc->id, chnl);\n\t\treturn 0;\n\t}\n\tmax_ptr = (unsigned long)(udata + length - 1);\n\tif (max_ptr < udata) {\n\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, send pointer address overflow\\n\", sc->id, chnl);\n\t\treturn -EINVAL;\n\t}\n\tif (udata & 0x3) {\n\t\tprintk(KERN_INFO \"riffa: fpga:%d chnl:%d, send user buffer must be 32 bit word aligned!\\n\", sc->id, chnl);\n\t\treturn -EINVAL;\n\t}\n\n\t// Convert timeout to jiffies.\n\ttymeout = (timeout == 0 ? MAX_SCHEDULE_TIMEOUT : (timeout * HZ/1000 > LONG_MAX ? LONG_MAX : timeout * HZ/1000));\n\ttymeouto = tymeout;\n\n\t// Clear the message queue.\n\twhile (!pop_circ_queue(sc->send[chnl]->msgs, &msg_type, &msg));\n\n\t// Initialize the sg_maps\n\tsc->send[chnl]->sg_map_0 = NULL;\n\tsc->send[chnl]->sg_map_1 = NULL;\n\n\t// Let FPGA know about transfer.\n\tDEBUG_MSG(KERN_INFO \"riffa: fpga:%d chnl:%d, send (len:%d off:%d last:%d)\\n\", sc->id, chnl, len, offset, last);\n\twrite_reg(sc, CHNL_REG(chnl, RX_OFFLAST_REG_OFF), ((offset<<1) | last));\n\twrite_reg(sc, CHNL_REG(chnl, RX_LEN_REG_OFF), len);\n\tif (len == 0)\n\t\treturn 0;\n\n\t// Use the send common buffer to share the scatter gather data\n\tsg_map = fill_sg_buf(sc, chnl, sc->send[chnl]->buf_addr, udata, length, 0, DMA_TO_DEVICE);\n\tif (sg_map == NULL || sg_map->num_sg == 0)\n\t\treturn (unsigned int)(sent>>2);\n\n\t// Update based on the sg_mapping\n\tudata += sg_map->length;\n\tlength -= sg_map->length;\n\tsc->send[chnl]->sg_map_1 = sg_map;\n\n\t// Let FPGA know about the scatter gather buffer.\n\twrite_reg(sc, CHNL_REG(chnl, RX_SG_ADDR_LO_REG_OFF), (sc->send[chnl]->buf_hw_addr & 0xFFFFFFFF));\n\twrite_reg(sc, CHNL_REG(chnl, RX_SG_ADDR_HI_REG_OFF), ((sc->send[chnl]->buf_hw_addr>>32) & 0xFFFFFFFF));\n\twrite_reg(sc, CHNL_REG(chnl, RX_SG_LEN_REG_OFF), 4 * sg_map->num_sg);\n\tDEBUG_MSG(KERN_INFO \"riffa: fpga:%d chnl:%d, send sg buf populated, %d sent\\n\", sc->id, chnl, sg_map->num_sg);\n\n\t// Continue until we get a message or timeout.\n\twhile (1) {\n\t\twhile ((nomsg = pop_circ_queue(sc->send[chnl]->msgs, &msg_type, &msg))) {\n\t\t\tprepare_to_wait(&sc->send[chnl]->waitq, &wait, TASK_INTERRUPTIBLE);\n\t\t\t// Another check before we schedule.\n\t\t\tif ((nomsg = pop_circ_queue(sc->send[chnl]->msgs, &msg_type, &msg)))\n\t\t\t\ttymeout = schedule_timeout(tymeout);\n\t\t\tfinish_wait(&sc->send[chnl]->waitq, &wait);\n\t\t\tif (signal_pending(current)) {\n\t\t\t\tfree_sg_buf(sc, sc->send[chnl]->sg_map_0);\n\t\t\t\tfree_sg_buf(sc, sc->send[chnl]->sg_map_1);\n\t\t\t\treturn -ERESTARTSYS;\n\t\t\t}\n\t\t\tif (!nomsg)\n\t\t\t\tbreak;\n\t\t\tif (tymeout == 0) {\n\t\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, send timed out\\n\", sc->id, chnl);\n\t\t\t\tfree_sg_buf(sc, sc->send[chnl]->sg_map_0);\n\t\t\t\tfree_sg_buf(sc, sc->send[chnl]->sg_map_1);\n\t\t\t\treturn (unsigned int)(sent>>2);\n\t\t\t}\n\t\t}\n\t\ttymeout = tymeouto;\n\n\t\t// Process the message.\n\t\tswitch (msg_type) {\n\t\tcase EVENT_SG_BUF_READ:\n\t\t\t// Release the previous scatter gather data?\n\t\t\tif (sc->send[chnl]->sg_map_0 != NULL)\n\t\t\t\tsent += sc->send[chnl]->sg_map_0->length;\n\t\t\tfree_sg_buf(sc, sc->send[chnl]->sg_map_0);\n\t\t\tsc->send[chnl]->sg_map_0 = NULL;\n\t\t\t// Populate the common buffer with more scatter gather data?\n\t\t\tif (length > 0) {\n\t\t\t\tsg_map = fill_sg_buf(sc, chnl, sc->send[chnl]->buf_addr, udata, length, 0, DMA_TO_DEVICE);\n\t\t\t\tif (sg_map == NULL || sg_map->num_sg == 0) {\n\t\t\t\t\tfree_sg_buf(sc, sc->send[chnl]->sg_map_0);\n\t\t\t\t\tfree_sg_buf(sc, sc->send[chnl]->sg_map_1);\n\t\t\t\t\treturn (unsigned int)(sent>>2);\n\t\t\t\t}\n\t\t\t\t// Update based on the sg_mapping\n\t\t\t\tudata += sg_map->length;\n\t\t\t\tlength -= sg_map->length;\n\t\t\t\tsc->send[chnl]->sg_map_0 = sc->send[chnl]->sg_map_1;\n\t\t\t\tsc->send[chnl]->sg_map_1 = sg_map;\n\t\t\t\twrite_reg(sc, CHNL_REG(chnl, RX_SG_ADDR_LO_REG_OFF), (sc->send[chnl]->buf_hw_addr & 0xFFFFFFFF));\n\t\t\t\twrite_reg(sc, CHNL_REG(chnl, RX_SG_ADDR_HI_REG_OFF), ((sc->send[chnl]->buf_hw_addr>>32) & 0xFFFFFFFF));\n\t\t\t\twrite_reg(sc, CHNL_REG(chnl, RX_SG_LEN_REG_OFF), 4 * sg_map->num_sg);\n\t\t\t\tDEBUG_MSG(KERN_INFO \"riffa: fpga:%d chnl:%d, send sg buf populated, %d sent\\n\", sc->id, chnl, sg_map->num_sg);\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase EVENT_TXN_DONE:\n\t\t\t// Update with the true value of words transferred.\n\t\t\tsent = (((unsigned long long)msg)<<2);\n\t\t\t// Return as this is the end of the transaction.\n\t\t\tfree_sg_buf(sc, sc->send[chnl]->sg_map_0);\n\t\t\tfree_sg_buf(sc, sc->send[chnl]->sg_map_1);\n\t\t\tDEBUG_MSG(KERN_INFO \"riffa: fpga:%d chnl:%d, sent %d words\\n\", sc->id, chnl, (unsigned int)(sent>>2));\n\t\t\treturn (unsigned int)(sent>>2);\n\t\t\tbreak;\n\n\t\tdefault: \n\t\t\tprintk(KERN_ERR \"riffa: fpga:%d chnl:%d, received unknown msg: %08x\\n\", sc->id, chnl, msg);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/**\n * Populates the fpga_info struct with the current FPGA state information. On \n * success, returns 0. On error, returns a negative value. \n */\nstatic inline int list_fpgas(fpga_info_list * list)\n{\n\tint i;\n\tint num_fpgas = 0;\n\tstruct fpga_state * sc;\n\n\tfor (i = 0; i < NUM_FPGAS; ++i) {\n\t\tif (atomic_read(&used_fpgas[i])) {\n\t\t\tsc = fpgas[i];\n\t\t\tlist->id[num_fpgas] = sc->id;\n\t\t\tlist->num_chnls[num_fpgas] = sc->num_chnls;\n\t\t\tlist->vendor_id[num_fpgas] = sc->vendor_id;\n\t\t\tlist->device_id[num_fpgas] = sc->device_id;\n\t\t\tmemcpy(list->name[num_fpgas], sc->name, 16*sizeof(char));\n\t\t\tnum_fpgas++;\n\t\t}\n\t}\n\t// Zero out the rest\n\tfor (i = num_fpgas; i < NUM_FPGAS; ++i) {\n\t\tlist->id[i] = -1;\n\t\tlist->num_chnls[i] = 0;\n\t\tlist->vendor_id[i] = 0;\n\t\tlist->device_id[i] = 0;\n\t\tmemset(list->name[i], 0, 16*sizeof(char));\n\t}\n\tlist->num_fpgas = num_fpgas;\n\n\treturn 0;\n}\n\n/**\n * Resets the driver for the specified FPGA. The fpga_state struct for all \n * channels will be reset as will the FPGA itself. \n */\nstatic inline void reset(int id)\n{\n\tint i;\n\tunsigned int dummy0;\n\tunsigned int dummy1;\n\tstruct fpga_state * sc;\n\n\tif (atomic_read(&used_fpgas[id])) {\n\t\tsc = fpgas[id];\n\t\t// Disable interrupts\n\t\tatomic_set(&sc->intr_disabled, 1);\n\t\t// Reset the FPGA\n\t\tread_reg(sc, INFO_REG_OFF);\n\n\t\t// Reset all the channels\n\t\tfor (i = 0; i < sc->num_chnls; ++i) {\n\t\t\twhile (!pop_circ_queue(sc->send[i]->msgs, &dummy0, &dummy1));\n\t\t\twhile (!pop_circ_queue(sc->recv[i]->msgs, &dummy0, &dummy1));\n\t\t\twake_up(&sc->send[i]->waitq);\n\t\t\twake_up(&sc->recv[i]->waitq);\n\t\t}\n\t\t// Enable interrupts\n\t\tatomic_set(&sc->intr_disabled, 0);\n\t}\n}\n\n/**\n * Main entry point for reading and writing on the device. Return value depends \n * on ioctlnum and expected behavior. See code for details.\n */\nstatic long fpga_ioctl(struct file *filp, unsigned int ioctlnum, \n\tunsigned long ioctlparam)\n{\t\n\tint rc;\n\tfpga_chnl_io io;\n\tfpga_info_list list;\n\n\tswitch (ioctlnum) {\n\t\tcase IOCTL_SEND:\n\t\t\tif ((rc = copy_from_user(&io, (void *)ioctlparam, sizeof(fpga_chnl_io)))) {\n\t\t\t\tprintk(KERN_ERR \"riffa: cannot read ioctl user parameter.\\n\");\n\t\t\t\treturn rc;\n\t\t\t}\n\t\t\tif (io.id < 0 || io.id >= NUM_FPGAS || !atomic_read(&used_fpgas[io.id]))\n\t\t\t\treturn 0;\n\t\t\treturn chnl_send(fpgas[io.id], io.chnl, io.data, io.len, io.offset, \n\t\t\t\tio.last, io.timeout);\n\t\tcase IOCTL_RECV:\n\t\t\tif ((rc = copy_from_user(&io, (void *)ioctlparam, sizeof(fpga_chnl_io)))) {\n\t\t\t\tprintk(KERN_ERR \"riffa: cannot read ioctl user parameter.\\n\");\n\t\t\t\treturn rc;\n\t\t\t}\n\t\t\tif (io.id < 0 || io.id >= NUM_FPGAS || !atomic_read(&used_fpgas[io.id]))\n\t\t\t\treturn 0;\n\t\t\treturn chnl_recv(fpgas[io.id], io.chnl, io.data, io.len, io.timeout);\n\t\tcase IOCTL_LIST:\n\t\t\tlist_fpgas(&list);\n\t\t\tif ((rc = copy_to_user((void *)ioctlparam, &list, sizeof(fpga_info_list))))\n\t\t\t\tprintk(KERN_ERR \"riffa: cannot write ioctl user parameter.\\n\");\n\t\t\treturn rc;\n\t\tcase IOCTL_RESET:\n\t\t\treset((int)ioctlparam);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t}\n\treturn 0;\n}\n\n\n///////////////////////////////////////////////////////\n// PCI DRIVER HANDLERS\n///////////////////////////////////////////////////////\n\n/**\n * Allocates and initializes chnl_dir structs for each channel. Returns the \n * number of chnl_dir structs allocated.\n */\nstatic inline int __devinit allocate_chnls(struct pci_dev *dev, struct fpga_state * sc) \n{\n\tint i;\n\tdma_addr_t hw_addr;\n\n\tfor (i = 0; i < sc->num_chnls; ++i) {\n\t\t// Allocate the recv struct\n\t\tsc->recv[i] = (struct chnl_dir *) kzalloc(sizeof(struct chnl_dir), GFP_KERNEL);\n\t\tif (sc->recv[i] == NULL)\n\t\t\treturn i;\n\t\tinit_waitqueue_head(&sc->recv[i]->waitq);\n\t\tif ((sc->recv[i]->msgs = init_circ_queue(5)) == NULL) {\n\t\t\tkfree(sc->recv[i]);\n\t\t\treturn i;\n\t\t}\n\t\tsc->recv[i]->buf_addr = pci_alloc_consistent(dev, sc->sg_buf_size, &hw_addr);\n\t\tsc->recv[i]->buf_hw_addr = hw_addr;\n\t\tif (sc->recv[i]->buf_addr == NULL) {\n\t\t\tfree_circ_queue(sc->recv[i]->msgs);\n\t\t\tkfree(sc->recv[i]);\n\t\t\treturn i;\n\t\t}\n\n\t\t// Allocate the send struct\n\t\tsc->send[i] = (struct chnl_dir *) kzalloc(sizeof(struct chnl_dir), GFP_KERNEL);\n\t\tif (sc->send[i] == NULL) {\n\t\t\tpci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, \n\t\t\t\t(dma_addr_t)sc->recv[i]->buf_hw_addr);\n\t\t\tfree_circ_queue(sc->recv[i]->msgs);\n\t\t\tkfree(sc->recv[i]);\n\t\t\treturn i;\n\t\t}\n\t\tinit_waitqueue_head(&sc->send[i]->waitq);\n\t\tif ((sc->send[i]->msgs = init_circ_queue(4)) == NULL) {\n\t\t\tkfree(sc->send[i]);\n\t\t\tpci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, \n\t\t\t\t(dma_addr_t)sc->recv[i]->buf_hw_addr);\n\t\t\tfree_circ_queue(sc->recv[i]->msgs);\n\t\t\tkfree(sc->recv[i]);\n\t\t\treturn i;\n\t\t}\n\t\tsc->send[i]->buf_addr = pci_alloc_consistent(dev, sc->sg_buf_size, &hw_addr);\n\t\tsc->send[i]->buf_hw_addr = hw_addr;\n\t\tif (sc->send[i]->buf_addr == NULL) {\n\t\t\tfree_circ_queue(sc->send[i]->msgs);\n\t\t\tkfree(sc->send[i]);\n\t\t\tpci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, \n\t\t\t\t(dma_addr_t)sc->recv[i]->buf_hw_addr);\n\t\t\tfree_circ_queue(sc->recv[i]->msgs);\n\t\t\tkfree(sc->recv[i]);\n\t\t\treturn i;\n\t\t}\n\t}\n\n\treturn i;\n}\n\n/**\n * Called by the OS when the device is ready for access. Returns 0 on success,\n * negative value on failure.\n */\nstatic int __devinit fpga_probe(struct pci_dev *dev, const struct pci_device_id *id) \n{\n\tint i;\n\tint j;\n\tint error;\n\tstruct fpga_state * sc;\n\tdma_addr_t hw_addr;\n\tunsigned int reg;\n\tu32 lnkctl_result;\n\tu32 devctl_result;\n\n\t// Setup the PCIe device.\n\terror = pci_enable_device(dev);\n\tif (error < 0) {\n\t\tprintk(KERN_ERR \"riffa: pci_enable_device returned %d\\n\", error);\n\t\treturn (-ENODEV);\n\t}\n\n\t// Enable bus master\n\tpci_set_master(dev);\n\n\t// Set the mask size\n\terror = pci_set_dma_mask(dev, DMA_BIT_MASK(64));\n\tif (!error)\n\t\terror = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));\n\tif (error) {\n\t\tprintk(KERN_ERR \"riffa: cannot set 64 bit DMA mode\\n\");\n\t\tpci_disable_device(dev);\n\t\treturn error;\n\t}\n\n\t// Allocate device structure.\n\tsc = kzalloc(sizeof(*sc), GFP_KERNEL);\n\tif (sc == NULL) {\n\t\tprintk(KERN_ERR \"riffa: not enough memory to allocate sc\\n\");\n\t\tpci_disable_device(dev);\n\t\treturn (-ENOMEM);\n\t}\n\tatomic_set(&sc->intr_disabled, 0);\n\tsnprintf(sc->name, sizeof(sc->name), \"%s%d\", pci_name(dev), 0);\n\tsc->vendor_id = dev->vendor;\n\tsc->device_id = dev->device;\n\tprintk(KERN_INFO \"riffa: found FPGA with name: %s\\n\", sc->name);\n\tprintk(KERN_INFO \"riffa: vendor id: 0x%04X\\n\", sc->vendor_id);\n\tprintk(KERN_INFO \"riffa: device id: 0x%04X\\n\", sc->device_id);\n\n\t// Setup the BAR memory regions\n\terror = pci_request_regions(dev, sc->name);\n\tif (error < 0) {\n\t\tprintk(KERN_ERR \"riffa: pci_request_regions returned error: %d\\n\", error);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn (-ENODEV);\n\t}\n\t\n\t// PCI BAR 0\n\tsc->bar0_addr = pci_resource_start(dev, 0);\n\tsc->bar0_len = pci_resource_len(dev, 0);\n\tsc->bar0_flags = pci_resource_flags(dev, 0);\n\tprintk(KERN_INFO \"riffa: BAR 0 address: %llx\\n\", sc->bar0_addr);\n\tprintk(KERN_INFO \"riffa: BAR 0 length: %lld bytes\\n\", sc->bar0_len);\n\tif (sc->bar0_len != 1024) {\n\t\tprintk(KERN_ERR \"riffa: BAR 0 incorrect length\\n\");\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn (-ENODEV);\n\t}\n\tsc->bar0 = ioremap(sc->bar0_addr, sc->bar0_len);\n\tif (!sc->bar0) {\n\t\tprintk(KERN_ERR \"riffa: could not ioremap BAR 0\\n\");\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn (-ENODEV);\n\t}\n\n\t// Setup MSI interrupts \n\terror = pci_enable_msi(dev);\n\tif (error != 0) {\n\t\tprintk(KERN_ERR \"riffa: pci_enable_msi returned error: %d\\n\", error);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn error;\n\t}\n\n\t// Request an interrupt\n\terror = request_irq(dev->irq, intrpt_handler, IRQF_SHARED, sc->name, sc);\n\tif (error != 0) {\n\t\tprintk(KERN_ERR \"riffa: request_irq(%d) returned error: %d\\n\", dev->irq, error);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn error;\n\t}\n\tsc->irq = dev->irq;\n\tprintk(KERN_INFO \"riffa: MSI setup on irq %d\\n\", dev->irq);\n\n\t// Set extended tag bit\n error = pcie_capability_read_dword(dev,PCI_EXP_DEVCTL,&devctl_result);\n\tif (error != 0) {\n\t\tprintk(KERN_ERR \"riffa: pcie_capability_read_dword returned error: %d\\n\", error);\n\t\tfree_irq(dev->irq, sc);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn error;\n\t}\n\tprintk(KERN_INFO \"riffa: PCIE_EXP_DEVCTL register: %x\\n\",devctl_result); \n\n\terror = pcie_capability_write_dword(dev,PCI_EXP_DEVCTL,(devctl_result|PCI_EXP_DEVCTL_EXT_TAG));\n\tif (error != 0) {\n\t\tprintk(KERN_ERR \"riffa: pcie_capability_write_dword returned error: %d\\n\", error);\n\t\tfree_irq(dev->irq, sc);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn error;\n\t}\n\n\t// Set RCB to 128\n error = pcie_capability_read_dword(dev,PCI_EXP_LNKCTL,&lnkctl_result);\n\tif (error != 0) {\n\t\tprintk(KERN_ERR \"riffa: pcie_capability_read_dword returned error: %d\\n\", error);\n\t\tfree_irq(dev->irq, sc);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn error;\n\t}\n\tprintk(KERN_INFO \"riffa: PCIE_EXP_LNKCTL register: %x\\n\",lnkctl_result); \n\n\terror = pcie_capability_write_dword(dev,PCI_EXP_LNKCTL,(lnkctl_result|PCI_EXP_LNKCTL_RCB));\n\tif (error != 0) {\n\t\tprintk(KERN_ERR \"riffa: pcie_capability_write_dword returned error: %d\\n\", error);\n\t\tpcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);\n\t\tfree_irq(dev->irq, sc);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn error;\n\t}\n\t// Read device configuration\n\treg = read_reg(sc, INFO_REG_OFF);\n\tsc->num_chnls = ((reg>>0) & 0xF);\n\tsc->num_sg = SG_ELEMS*((reg>>19) & 0xF);\n\tsc->sg_buf_size = SG_BUF_SIZE*((reg>>19) & 0xF);\n printk(KERN_INFO \"riffa: number of channels: %d\\n\", ((reg>>0) & 0xF));\n printk(KERN_INFO \"riffa: bus interface width: %d\\n\", ((reg>>19) & 0xF)<<5);\n printk(KERN_INFO \"riffa: bus master enabled: %d\\n\", ((reg>>4) & 0x1));\n printk(KERN_INFO \"riffa: negotiated link width: %d\\n\", ((reg>>5) & 0x3F));\n printk(KERN_INFO \"riffa: negotiated link rate: %d MTs\\n\", ((reg>>11) & 0x3)*2500);\n printk(KERN_INFO \"riffa: max downstream payload: %d bytes\\n\", 128<<((reg>>13) & 0x7) );\n printk(KERN_INFO \"riffa: max upstream payload: %d bytes\\n\", 128<<((reg>>16) & 0x7) );\n\n\tif (((reg>>4) & 0x1) != 1) {\n\t\tprintk(KERN_ERR \"riffa: bus master not enabled!\\n\");\n\t\tpcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);\n\t\tpcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);\n\t\tfree_irq(dev->irq, sc);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn (-ENODEV);\n\t}\n\n\tif (((reg>>5) & 0x3F) == 0 || ((reg>>11) & 0x3) == 0) {\n\t\tprintk(KERN_ERR \"riffa: bad link parameters!\\n\");\n\t\tpcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);\n\t\tpcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);\n\t\tfree_irq(dev->irq, sc);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn (-ENODEV);\n\t}\n\n\tif ((reg & 0xF) == 0 || (reg & 0xF) > MAX_CHNLS) {\n\t\tprintk(KERN_ERR \"riffa: bad number of channels!\\n\");\n\t\tpcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);\n\t\tpcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);\n\t\tfree_irq(dev->irq, sc);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn (-ENODEV);\n\t}\n\n\tif (((reg>>19) & 0xF) == 0 || ((reg>>19) & 0xF) > MAX_BUS_WIDTH_PARAM) {\n\t\tprintk(KERN_ERR \"riffa: bad bus width!\\n\");\n\t\tpcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);\n\t\tpcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);\n\t\tfree_irq(dev->irq, sc);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn (-ENODEV);\n\t}\n\n\t// Create chnl_dir structs.\n\tsc->recv = (struct chnl_dir **) kzalloc(sc->num_chnls*sizeof(struct chnl_dir*), GFP_KERNEL); \n\tsc->send = (struct chnl_dir **) kzalloc(sc->num_chnls*sizeof(struct chnl_dir*), GFP_KERNEL); \n\tif (sc->recv == NULL || sc->send == NULL) {\n\t\tprintk(KERN_ERR \"riffa: not enough memory to allocate chnl_dir arrays\\n\");\n\t\tif (sc->recv != NULL)\n\t\t\tkfree(sc->recv);\n\t\tif (sc->send != NULL)\n\t\t\tkfree(sc->send);\n\t\tpcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);\n\t\tpcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);\n\t\tfree_irq(dev->irq, sc);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn (-ENOMEM);\n\t}\n\tj = allocate_chnls(dev, sc);\n\tif (j < sc->num_chnls) {\n\t\tsc->num_chnls = j;\n\t\tprintk(KERN_ERR \"riffa: not enough memory to allocate chnl_dir structs\\n\");\n\t\tfor (i = 0; i < sc->num_chnls; ++i) {\n\t\t\tpci_free_consistent(dev, sc->sg_buf_size, sc->send[i]->buf_addr, \n\t\t\t\t(dma_addr_t)sc->send[i]->buf_hw_addr);\n\t\t\tpci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, \n\t\t\t\t(dma_addr_t)sc->recv[i]->buf_hw_addr);\n\t\t\tfree_circ_queue(sc->send[i]->msgs);\n\t\t\tfree_circ_queue(sc->recv[i]->msgs);\n\t\t\tkfree(sc->send[i]);\n\t\t\tkfree(sc->recv[i]);\n\t\t}\n\t\tkfree(sc->recv);\n\t\tkfree(sc->send);\n\t\tpcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);\n\t\tpcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);\n\t\tfree_irq(dev->irq, sc);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn (-ENOMEM);\n\t}\n\n\t// Create spill buffer (for overflow on receive).\n\tsc->spill_buf_addr = pci_alloc_consistent(dev, SPILL_BUF_SIZE, &hw_addr);\n\tsc->spill_buf_hw_addr = hw_addr;\n\tif (sc->spill_buf_addr == NULL) {\n\t\tprintk(KERN_ERR \"riffa: not enough memory to allocate spill buffer\\n\");\n\t\tfor (i = 0; i < sc->num_chnls; ++i) {\n\t\t\tpci_free_consistent(dev, sc->sg_buf_size, sc->send[i]->buf_addr, \n\t\t\t\t(dma_addr_t)sc->send[i]->buf_hw_addr);\n\t\t\tpci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, \n\t\t\t\t(dma_addr_t)sc->recv[i]->buf_hw_addr);\n\t\t\tfree_circ_queue(sc->send[i]->msgs);\n\t\t\tfree_circ_queue(sc->recv[i]->msgs);\n\t\t\tkfree(sc->send[i]);\n\t\t\tkfree(sc->recv[i]);\n\t\t}\n\t\tpcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);\n\t\tpcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);\n\t\tkfree(sc->recv);\n\t\tkfree(sc->send);\n\t\tfree_irq(dev->irq, sc);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t}\n\n\t// Save pointer to structure \n\tpci_set_drvdata(dev, sc);\n\tsc->dev = dev;\n\tsc->id = -1;\n\tfor (i = 0; i < NUM_FPGAS; i++) {\n\t\tif (!atomic_xchg(&used_fpgas[i], 1)) {\n\t\t\tsc->id = i;\n\t\t\tfpgas[i] = sc;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (sc->id == -1) {\n\t\tprintk(KERN_ERR \"riffa: could not save FPGA information, %d is limit.\\n\", NUM_FPGAS);\n\t\tfor (i = 0; i < sc->num_chnls; ++i) {\n\t\t\tpci_free_consistent(dev, sc->sg_buf_size, sc->send[i]->buf_addr, \n\t\t\t\t(dma_addr_t)sc->send[i]->buf_hw_addr);\n\t\t\tpci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, \n\t\t\t\t(dma_addr_t)sc->recv[i]->buf_hw_addr);\n\t\t\tfree_circ_queue(sc->send[i]->msgs);\n\t\t\tfree_circ_queue(sc->recv[i]->msgs);\n\t\t\tkfree(sc->send[i]);\n\t\t\tkfree(sc->recv[i]);\n\t\t}\n\t\tkfree(sc->recv);\n\t\tkfree(sc->send);\n\t\tpci_free_consistent(dev, SPILL_BUF_SIZE, sc->spill_buf_addr, \n\t\t\t(dma_addr_t)sc->spill_buf_hw_addr);\n\t\tpcie_capability_write_dword(dev,PCI_EXP_LNKCTL,lnkctl_result);\n\t\tpcie_capability_write_dword(dev,PCI_EXP_DEVCTL,devctl_result);\n\t\tfree_irq(dev->irq, sc);\n\t\tpci_disable_msi(dev);\n\t\tiounmap(sc->bar0);\n\t\tpci_release_regions(dev);\n\t\tpci_disable_device(dev);\n\t\tkfree(sc);\n\t\treturn (-ENOMEM);\n\t}\n\telse {\n\t\tprintk(KERN_INFO \"riffa: saved FPGA with id: %d\\n\", sc->id);\n\t}\n\n\treturn 0;\n}\n\n/**\n * Called when the device is unloaded.\n */\nstatic void __devexit fpga_remove(struct pci_dev *dev) \n{\n\tint i;\n\tu32 result;\n\tstruct fpga_state * sc;\n\n pcie_capability_read_dword(dev,PCI_EXP_DEVCTL,&result);\n\tpcie_capability_write_dword(dev,PCI_EXP_DEVCTL,result & (~PCI_EXP_DEVCTL_EXT_TAG));\n\n pcie_capability_read_dword(dev,PCI_EXP_DEVCTL,&result);\n\tpcie_capability_write_dword(dev,PCI_EXP_LNKCTL,result & (~PCI_EXP_LNKCTL_RCB));\n\n\tif ((sc = (struct fpga_state *)pci_get_drvdata(dev)) != NULL) {\n\t\t// Free structs, memory regions, etc.\n\t\tatomic_set(&used_fpgas[sc->id], 0);\n\t\tfor (i = 0; i < sc->num_chnls; ++i) {\n\t\t\tpci_free_consistent(dev, sc->sg_buf_size, sc->send[i]->buf_addr, \n\t\t\t\t(dma_addr_t)sc->send[i]->buf_hw_addr);\n\t\t\tpci_free_consistent(dev, sc->sg_buf_size, sc->recv[i]->buf_addr, \n\t\t\t\t(dma_addr_t)sc->recv[i]->buf_hw_addr);\n\t\t\tfree_circ_queue(sc->send[i]->msgs);\n\t\t\tfree_circ_queue(sc->recv[i]->msgs);\n\t\t\tkfree(sc->send[i]);\n\t\t\tkfree(sc->recv[i]);\n\t\t}\n\t\tkfree(sc->recv);\n\t\tkfree(sc->send);\n\t\tpci_free_consistent(dev, SPILL_BUF_SIZE, sc->spill_buf_addr, \n\t\t\t(dma_addr_t)sc->spill_buf_hw_addr);\n\t\tfree_irq(dev->irq, sc);\n\t\tiounmap(sc->bar0);\n\t\tkfree(sc);\n\t}\n\tpci_disable_msi(dev);\n\tpci_release_regions(dev);\n\tpci_disable_device(dev);\n\tpci_set_drvdata(dev, NULL);\n}\n\n\n///////////////////////////////////////////////////////\n// MODULE INIT/EXIT FUNCTIONS\n///////////////////////////////////////////////////////\n\nstatic DEFINE_PCI_DEVICE_TABLE(fpga_ids) = {\n\t{PCI_DEVICE(VENDOR_ID0, PCI_ANY_ID)},\n\t{PCI_DEVICE(VENDOR_ID1, PCI_ANY_ID)},\n\t{0},\n};\n\nMODULE_DEVICE_TABLE(pci, fpga_ids);\nstatic struct pci_driver fpga_driver = {\n\t.name\t\t= DEVICE_NAME,\n\t.id_table\t= fpga_ids,\n\t.probe\t\t= fpga_probe,\n\t.remove\t\t= __devexit_p(fpga_remove),\n};\n\nstatic const struct file_operations fpga_fops = {\n\t.owner\t\t\t= THIS_MODULE,\n\t.unlocked_ioctl\t= fpga_ioctl,\n};\n\n/**\n * Called to initialize the PCI device. \n */\nstatic int __init fpga_init(void) \n{\t\n\tint i;\n\tint error;\n\n\tfor (i = 0; i < NUM_FPGAS; i++)\n\t\tatomic_set(&used_fpgas[i], 0);\n\n\terror = pci_register_driver(&fpga_driver);\n\tif (error != 0) {\n\t\tprintk(KERN_ERR \"riffa: pci_module_register returned %d\\n\", error);\n\t\treturn (error);\n\t}\n\n\terror = register_chrdev(MAJOR_NUM, DEVICE_NAME, &fpga_fops);\n\tif (error < 0) {\n\t\tprintk(KERN_ERR \"riffa: register_chrdev returned %d\\n\", error);\n\t\treturn (error);\n\t}\n\n\tmymodule_class = class_create(THIS_MODULE, DEVICE_NAME);\n\tif (IS_ERR(mymodule_class)) {\n\t\terror = PTR_ERR(mymodule_class);\n\t\tprintk(KERN_ERR \"riffa: class_create() returned %d\\n\", error);\n\t\treturn (error);\n\t}\n\n\tdevt = MKDEV(MAJOR_NUM, 0);\n\tdevice_create(mymodule_class, NULL, devt, \"%s\", DEVICE_NAME);\n\n\treturn 0;\n}\n\n/**\n * Called to destroy the PCI device.\n */\nstatic void __exit fpga_exit(void)\n{\n\tdevice_destroy(mymodule_class, devt); \n\tclass_destroy(mymodule_class);\n\tpci_unregister_driver(&fpga_driver);\n\tunregister_chrdev(MAJOR_NUM, DEVICE_NAME);\n}\n\nmodule_init(fpga_init);\nmodule_exit(fpga_exit);\n\n" }, { "path": "sw/riffa_2.1/driver/linux/riffa_driver.h", "content": "/*******************************************************************************\n * This software is Copyright © 2012 The Regents of the University of\n * California. All Rights Reserved.\n *\n * Permission to copy, modify, and distribute this software and its\n * documentation for educational, research and non-profit purposes, without fee,\n * and without a written agreement is hereby granted, provided that the above\n * copyright notice, this paragraph and the following three paragraphs appear in\n * all copies.\n *\n * Permission to make commercial use of this software may be obtained by\n * contacting:\n * Technology Transfer Office\n * 9500 Gilman Drive, Mail Code 0910\n * University of California\n * La Jolla, CA 92093-0910\n * (858) 534-5815\n * invent@ucsd.edu\n *\n * This software program and documentation are copyrighted by The Regents of the\n * University of California. The software program and documentation are supplied\n * \"as is\", without any accompanying services from The Regents. The Regents does\n * not warrant that the operation of the program will be uninterrupted or error-\n * free. The end-user understands that the program was developed for research\n * purposes and is advised not to rely exclusively on the program for any\n * reason.\n *\n * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO\n * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR\n * CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING\n * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,\n * EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF\n * CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,\n * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n * THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS,\n * AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO\n * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR\n * MODIFICATIONS.\n */\n\n/*\n * Filename: riffa_driver.h\n * Version: 2.0\n * Description: Linux PCIe device driver for RIFFA. Uses Linux kernel APIs in\n * version 2.6.27+ (tested on version 2.6.32 - 3.3.0).\n * Author: Matthew Jacobsen\n * History: @mattj: Initial release. Version 2.0.\n */\n\n#ifndef RIFFA_DRIVER_H\n#define RIFFA_DRIVER_H\n\n#include \n\n#define DBUG 1\n\n#ifdef DEBUG\n#define DEBUG_MSG(...) printk(__VA_ARGS__)\n#else\n#define DEBUG_MSG(...)\n#endif\n\n\n// The major device number. We can't rely on dynamic registration because ioctls\n// need to know it.\n#define MAJOR_NUM 100\n#define DEVICE_NAME \"riffa\"\n#define VENDOR_ID0 0x10EE\n#define VENDOR_ID1 0x1172\n\n// Message events for readmsgs/writemsgs queues.\n#define EVENT_TXN_LEN\t\t\t\t1\n#define EVENT_TXN_OFFLAST\t\t\t2\n#define EVENT_TXN_DONE\t\t\t\t3\n#define EVENT_SG_BUF_READ\t\t\t4\n\n// Constants and device offsets\n#define NUM_FPGAS\t\t\t\t\t5 \t// max # of FPGAs to support in a single PC\n#define MAX_CHNLS\t\t\t\t\t12\t// max # of channels per FPGA\n#define MAX_BUS_WIDTH_PARAM\t\t\t4\t// max bus width parameter\n#define SG_BUF_SIZE\t\t\t\t\t(4*1024)\t// size of shared SG buffer\n#define SG_ELEMS\t\t\t\t\t200 // # of SG elements to transfer at a time\n#define SPILL_BUF_SIZE\t\t\t\t(4*1024)\t// size of shared spill common buffer\n\n#define RX_SG_LEN_REG_OFF\t\t\t0x0\t// config offset for RX SG buf length\n#define RX_SG_ADDR_LO_REG_OFF\t\t0x1\t// config offset for RX SG buf low addr\n#define RX_SG_ADDR_HI_REG_OFF\t\t0x2\t// config offset for RX SG buf high addr\n#define RX_LEN_REG_OFF\t\t\t\t0x3\t// config offset for RX txn length\n#define RX_OFFLAST_REG_OFF\t\t\t0x4\t// config offset for RX txn last/offset\n#define RX_TNFR_LEN_REG_OFF\t\t\t0xD\t// config offset for RX transfer length\n#define TX_SG_LEN_REG_OFF\t\t\t0x5\t// config offset for TX SG buf length\n#define TX_SG_ADDR_LO_REG_OFF\t\t0x6\t// config offset for TX SG buf low addr\n#define TX_SG_ADDR_HI_REG_OFF\t\t0x7\t// config offset for TX SG buf high addr\n#define TX_LEN_REG_OFF\t\t\t\t0x8\t// config offset for TX txn length\n#define TX_OFFLAST_REG_OFF\t\t\t0x9\t// config offset for TX txn last/offset\n#define TX_TNFR_LEN_REG_OFF\t\t\t0xE\t// config offset for TX transfer length\n\n#define INFO_REG_OFF\t\t\t\t0xA\t// config offset for link info\n\n#define IRQ_REG0_OFF\t\t\t\t0xB\t// config offset for interrupt reg 0\n#define IRQ_REG1_OFF\t\t\t\t0xC\t// config offset for interrupt reg 1\n\n\n// Structs\nstruct fpga_chnl_io\n{\n\tint id;\n\tint chnl;\n\tunsigned int len;\n\tunsigned int offset;\n\tunsigned int last;\n\tunsigned long long timeout;\n\tchar * data;\n};\ntypedef struct fpga_chnl_io fpga_chnl_io;\n\nstruct fpga_info_list\n{\n\tint num_fpgas;\n\tint id[NUM_FPGAS];\n\tint num_chnls[NUM_FPGAS];\n\tchar name[NUM_FPGAS][16];\n\tint vendor_id[NUM_FPGAS];\n\tint device_id[NUM_FPGAS];\n};\ntypedef struct fpga_info_list fpga_info_list;\n\n// IOCTLs\n#define IOCTL_SEND _IOW(MAJOR_NUM, 1, fpga_chnl_io *)\n#define IOCTL_RECV _IOR(MAJOR_NUM, 2, fpga_chnl_io *)\n#define IOCTL_LIST _IOR(MAJOR_NUM, 3, fpga_info_list *)\n#define IOCTL_RESET _IOW(MAJOR_NUM, 4, int)\n\n\n\n#endif\n" }, { "path": "sw/riffa_2.1/driver/windows/README.txt", "content": "To build the Windows driver:\r\n\r\n1) Install Windows Driver Development Kit supporting Windows 7 (tested on \r\n version 7600.16385.1).\r\n2) Open a DDK command window environment for Windows 7 (which ever version \r\n you're targeting).\r\n3) Move to the directory containing this README.txt and run: build -ceZ\r\n4) The driver should be built and ready in the output directory along with a\r\n Windows 7 catalog file and the coinstaller DLLs.\r\n\r\nA few notes:\r\n\r\n- You will need to sign the driver (riffa.sys) and catalog file (riffa.cat) \r\n before you can install it on a x64 Windows 7 or Vista computer. The build \r\n process will attempt to sign the catalog file with the UCSD certificate. You\r\n don't have that, so you won't get a signed driver simply by building. You'll\r\n need to get a certificate from a certificate authority that is capable of \r\n cross-certificate kernel driver signing. See this page for more details:\r\n http://msdn.microsoft.com/en-us/windows/hardware/gg487315.aspx\r\n \r\n- Debugging on Windows is difficult because there exists no kernel log file.\r\n Drivers are supposed to log messages using a trace events framework which is\r\n overly complex and requires developer tools to first collect the output and\r\n then more (different) tools to make the output human readable. Instead, this\r\n driver writes normal log messages via a kernel debugger facility. To see the\r\n messages you'll need the Windows Development Kit debugger (WinDbg) or a small\r\n utility called DbgView. DbgView is a standalone kernel debug viewer that can\r\n be downloaded from Microsoft here:\r\n http://technet.microsoft.com/en-us/sysinternals/bb896647.aspx\r\n Just start with administrator privileges and be sure to enable Capture Kernel, \r\n Capture Events, and Capture Verbose Kernel Output.\r\n\r\n- Building with the checked environment will produce a version of the driver\r\n with verbose debugging output. Building with the free environment will \r\n produce a version of the driver with minimal messaging output. The debug \r\n version will have a \"(Debug)\" label in the Windows device manager, so you \r\n can tell which version is installed.\r\n\r\n- Inno Setup scripts produce a Windows Installer. You may use our script if you\r\n like.\r\n" }, { "path": "sw/riffa_2.1/driver/windows/dirs", "content": "DIRS= \\\r\n sys" }, { "path": "sw/riffa_2.1/driver/windows/install/install.bat", "content": "@echo off\r\n\r\nrmdir /s /q build\r\nmd build\r\nmd build\\x86\r\nmd build\\x64\r\n\r\ncopy win7.iss .\\build\r\ncopy license.txt .\\build\r\n\r\nxcopy /E /H /K /I /Y %1 .\\build\\x86\r\nxcopy /E /H /K /I /Y %2 .\\build\\x64\r\nxcopy /E /H /K /I /Y ..\\..\\..\\c_c++\\windows .\\build\\c_c++\r\nxcopy /E /H /K /I /Y ..\\..\\..\\java .\\build\\java\r\nxcopy /E /H /K /I /Y ..\\..\\..\\python .\\build\\python\r\nxcopy /E /H /K /I /Y ..\\..\\..\\matlab .\\build\\matlab\r\n\r\nif \"%3\" == \"chk\" (\r\n \"c:\\program files\\inno setup 5\\iscc.exe\" /dDebug=\"1\" /o.\\build .\\build\\win7.iss \r\n) else (\r\n \"c:\\program files\\inno setup 5\\iscc.exe\" /o.\\build .\\build\\win7.iss \r\n)\r\nsigntool sign /v /s my /n \"University of California, San Diego\" /t http://timestamp.verisign.com/scripts/timestamp.dll .\\build\\setup.exe\r\n\r\n\r\n" }, { "path": "sw/riffa_2.1/driver/windows/install/license.txt", "content": "This software is Copyright 2012 The Regents of the University of California. All Rights Reserved.\n\nPermission to copy, modify, and distribute this software and its documentation for educational, research and non-profit purposes, without fee, and without a written agreement is hereby granted, provided that the above copyright notice, this paragraph and the following three paragraphs appear in all copies.\n\nPermission to make commercial use of this software may be obtained by contacting:\nTechnology Transfer Office\n9500 Gilman Drive, Mail Code 0910\nUniversity of California\nLa Jolla, CA 92093-0910\n(858) 534-5815\ninvent@ucsd.edu\n\nThis software program and documentation are copyrighted by The Regents of the University of California. The software program and documentation are supplied \"as is\", without any accompanying services from The Regents. The Regents does not warrant that the operation of the program will be uninterrupted or error-free. The end-user understands that the program was developed for research purposes and is advised not to rely exclusively on the program for any reason.\n\nIN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN \"AS IS\" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.\n" }, { "path": "sw/riffa_2.1/driver/windows/install/win7.iss", "content": "; -- 64Bit.iss --\r\n; Demonstrates installation of a program built for the x64 (a.k.a. AMD64)\r\n; architecture.\r\n; To successfully run this installation and the program it installs,\r\n; you must have a \"x64\" edition of Windows.\r\n\r\n; SEE THE DOCUMENTATION FOR DETAILS ON CREATING .ISS SCRIPT FILES!\r\n#ifdef Debug\r\n#define DebugMsg1 \"%n%nNOTE: This version has been compiled to output additional debug messages (with some performance overhead).\"\r\n#else\r\n#define DebugMsg1 \"\"\r\n#endif\r\n\r\n[Setup]\r\nAppName=RIFFA\r\nAppVersion=2.0\r\nAppPublisher=University of California, San Diego\r\nAppPublisherURL=https://sites.google.com/a/eng.ucsd.edu/matt-jacobsen/riffa\r\nAppCopyright=Copyright (C) 2012 The Regents of the University of California. All Rights Reserved.\r\nLicenseFile=license.txt\r\nPrivilegesRequired=admin\r\nMinVersion=6.1\r\nOnlyBelowVersion=6.2\r\nDisableProgramGroupPage=yes\r\nCompression=lzma2\r\nSolidCompression=yes\r\nUsePreviousAppDir=no\r\nDefaultDirName={pf}\\Riffa\r\nOutputDir=outputdir\r\n; \"ArchitecturesInstallIn64BitMode=x64\" requests that the install be\r\n; done in \"64-bit mode\" on x64, meaning it should use the native\r\n; 64-bit Program Files directory and the 64-bit view of the registry.\r\nArchitecturesInstallIn64BitMode=x64\r\n\r\n[Messages]\r\nWelcomeLabel1=Welcome to the [name] Setup Wizard\r\nWelcomeLabel2=This will install the [name/ver] FPGA drivers and C/C++ bindings on your computer.{#DebugMsg1}%n%nSee the install program directory for details on installing other language bindings.%n%nIt is recommended that you close all other applications and disable any anti virus before continuing.\r\nFinishedLabelNoIcons=Setup has finished installing [name/ver] on your computer.%n%nAny [name] compatible FPGA devices should be detected upon reboot.\r\n\r\n[Dirs]\r\nName: \"{app}\\c_c++\"; Permissions: users-modify\r\nName: \"{app}\\java\"; Permissions: users-modify\r\nName: \"{app}\\python\"; Permissions: users-modify\r\nName: \"{app}\\matlab\"; Permissions: users-modify\r\n\r\n[Files]\r\nSource: \"c_c++\\x86\\riffa.lib\"; DestDir: \"{app}\\c_c++\"; Check: \"not IsWin64\"\r\nSource: \"c_c++\\x86\\riffa.h\"; DestDir: \"{app}\\c_c++\"; Check: \"not IsWin64\"\r\nSource: \"c_c++\\x86\\sample_app\\README.txt\"; DestDir: \"{app}\\c_c++\"; Check: \"not IsWin64\"\r\nSource: \"c_c++\\x86\\sample_app\\timer.h\"; DestDir: \"{app}\\c_c++\"; Check: \"not IsWin64\"\r\nSource: \"c_c++\\x86\\sample_app\\testutil.c\"; DestDir: \"{app}\\c_c++\"; Check: \"not IsWin64\"\r\nSource: \"c_c++\\x86\\sample_app\\testutil.exe\"; DestDir: \"{app}\\c_c++\"; Check: \"not IsWin64\"\r\nSource: \"c_c++\\x64\\riffa.lib\"; DestDir: \"{app}\\c_c++\"; Check: IsWin64\r\nSource: \"c_c++\\x64\\riffa.h\"; DestDir: \"{app}\\c_c++\"; Check: IsWin64\r\nSource: \"c_c++\\x64\\sample_app\\README.txt\"; DestDir: \"{app}\\c_c++\"; Check: IsWin64\r\nSource: \"c_c++\\x64\\sample_app\\timer.h\"; DestDir: \"{app}\\c_c++\"; Check: IsWin64\r\nSource: \"c_c++\\x64\\sample_app\\testutil.c\"; DestDir: \"{app}\\c_c++\"; Check: IsWin64\r\nSource: \"c_c++\\x64\\sample_app\\testutil.exe\"; DestDir: \"{app}\\c_c++\"; Check: IsWin64\r\n\r\nSource: \"java\\README.txt\"; DestDir: \"{app}\\java\"\r\nSource: \"java\\riffa.jar\"; DestDir: \"{app}\\java\"\r\nSource: \"java\\SampleApp.java\"; DestDir: \"{app}\\java\"\r\n\r\nSource: \"matlab\\README.txt\"; DestDir: \"{app}\\matlab\"\r\nSource: \"matlab\\Riffa.m\"; DestDir: \"{app}\\matlab\"\r\n\r\nSource: \"python\\dist\\README.txt\"; DestDir: \"{app}\\python\"\r\nSource: \"python\\dist\\riffa-2.0.zip\"; DestDir: \"{app}\\python\"\r\nSource: \"python\\sample_app\\sampleapp.py\"; DestDir: \"{app}\\python\"\r\n\r\nSource: \"x86\\riffa.sys\"; DestDir: \"{tmp}\"; Check: \"not IsWin64\"\r\nSource: \"x86\\riffa.inf\"; DestDir: \"{tmp}\"; Check: \"not IsWin64\"\r\nSource: \"x86\\riffa.cat\"; DestDir: \"{tmp}\"; Check: \"not IsWin64\"\r\nSource: \"x86\\WdfCoInstaller01009.dll\"; DestDir: \"{tmp}\"; Check: \"not IsWin64\"\r\nSource: \"x86\\WdfCoInstaller01009_chk.dll\"; DestDir: \"{tmp}\"; Check: \"not IsWin64\"\r\nSource: \"x64\\riffa.sys\"; DestDir: \"{tmp}\"; Check: IsWin64\r\nSource: \"x64\\riffa.inf\"; DestDir: \"{tmp}\"; Check: IsWin64\r\nSource: \"x64\\riffa.cat\"; DestDir: \"{tmp}\"; Check: IsWin64\r\nSource: \"x64\\WdfCoInstaller01009.dll\"; DestDir: \"{tmp}\"; Check: IsWin64\r\nSource: \"x64\\WdfCoInstaller01009_chk.dll\"; DestDir: \"{tmp}\"; Check: IsWin64\r\n\r\nSource: \"c_c++\\x86\\riffa.dll\"; DestDir: {sys}; Flags: 32bit; Check: \"not IsWin64\"\r\nSource: \"c_c++\\x64\\riffa.dll\"; DestDir: {sys}; Flags: 64bit; Check: IsWin64\r\n\r\n[Run]\r\nFilename: \"{sys}\\pnputil.exe\"; Parameters: \" -i -a {tmp}\\riffa.inf\"; WorkingDir: \"{tmp}\"; Description: \"Install driver\"; StatusMsg: \"Installing drivers...\"; Flags: runascurrentuser runhidden;\r\n\r\n" }, { "path": "sw/riffa_2.1/driver/windows/sys/makefile", "content": "#\r\n# DO NOT EDIT THIS FILE!!! Edit .\\sources. if you want to add a new source\r\n# file to this component. This file merely indirects to the real make file\r\n# that is shared by all the components of Windows\r\n#\r\n!INCLUDE $(NTMAKEENV)\\makefile.def\r\n\r\n" }, { "path": "sw/riffa_2.1/driver/windows/sys/makefile.inc", "content": "_LNG=$(LANGUAGE)\r\n_INX=.\r\nSTAMP=stampinf -f $@ -a $(_BUILDARCH) -k $(KMDF_VERSION_MAJOR).$(KMDF_VERSION_MINOR)\r\n\r\n\r\n$(OBJ_PATH)\\$(O)\\$(INF_NAME).inf: $(_INX)\\$(INF_NAME).inx\r\n copy $(_INX)\\$(@B).inx $@\r\n $(STAMP)\r\n! if \"$(DDKBUILDENV)\" == \"chk\"\r\n echo RIFFA.DEBUG=\" (Debug)\" >> $@\r\n! else \r\n echo RIFFA.DEBUG=\"\" >> $@\r\n! endif \r\n\r\n\r\nPOST:\r\n copy $(BASEDIR)\\redist\\wdf\\$(_BUILDARCH)\\WdfCoInstaller*.dll $(OBJ_PATH)\\$(O)\r\n! if \"$(DDK_TARGET_OS)\" == \"Win7\"\r\n! if \"$(_BUILDARCH)\" == \"x86\"\r\n inf2cat /driver:$(OBJ_PATH)\\$(O) /os:7_x86\r\n! else \r\n inf2cat /driver:$(OBJ_PATH)\\$(O) /os:7_x64\r\n! endif \r\n! endif \r\n signtool sign /v /ac \"$(_INX)\\GlobalSign Root CA.crt\" /s my /n \"University of California, San Diego\" /t http://timestamp.verisign.com/scripts/timestamp.dll $(OBJ_PATH)\\$(O)\\$(INF_NAME).cat\r\n signtool sign /v /ac \"$(_INX)\\GlobalSign Root CA.crt\" /s my /n \"University of California, San Diego\" /t http://timestamp.verisign.com/scripts/timestamp.dll $(OBJ_PATH)\\$(O)\\$(INF_NAME).sys\r\n\r\n " }, { "path": "sw/riffa_2.1/driver/windows/sys/precomp.h", "content": "#define WIN9X_COMPAT_SPINLOCK\r\n#include \r\n#pragma warning(disable:4201) // nameless struct/union warning\r\n\r\n#include \r\n#include \r\n#include \r\n#include \r\n#include \r\n\r\n#pragma warning(default:4201)\r\n\r\n#include // required for GUID definitions\r\n#include // required for WMILIB_CONTEXT\r\n\r\n\r\n#include \"riffa_driver.h\"\r\n#include \"riffa_private.h\"\r\n#include \"trace.h\"\r\n\r\n\r\n" }, { "path": "sw/riffa_2.1/driver/windows/sys/riffa.c", "content": "#include \"precomp.h\"\r\n\r\n// The trace message header (.tmh) file must be included in a source file\r\n// before any WPP macro calls and after defining a WPP_CONTROL_GUIDS\r\n// macro (defined in toaster.h). During the compilation, WPP scans the source\r\n// files for DoTraceMessage() calls and builds a .tmh file which stores a unique\r\n// data GUID for each message, the text resource string for each message,\r\n// and the data types of the variables passed in for each message. This file\r\n// is automatically generated by the WPP preprocessor.\r\n//\r\n#include \"riffa.tmh\"\r\n\r\n\r\n#ifdef ALLOC_PRAGMA\r\n#pragma alloc_text (INIT, DriverEntry)\r\n#pragma alloc_text (PAGE, RiffaEvtDeviceAdd)\r\n#pragma alloc_text (PAGE, RiffaEvtDriverContextCleanup)\r\n#pragma alloc_text (PAGE, RiffaEvtDevicePrepareHardware)\r\n#pragma alloc_text (PAGE, RiffaEvtDeviceReleaseHardware)\r\n\r\n#endif\r\n\r\n/**\r\n * DriverEntry initializes the driver and is the first routine called by the\r\n * system after the driver is loaded. DriverEntry configures and creates a WDF driver\r\n * object.\r\n *\t.\r\n * DriverObject - represents the instance of the function driver that is loaded\r\n * into memory. DriverObject is allocated by the system before the\r\n * driver is loaded, and it is released by the system after the system unloads\r\n * the function driver from memory.\r\n *\r\n * RegistryPath - represents the driver specific path in the Registry.\r\n * The function driver can use the path to store driver related data between\r\n * reboots. The path does not store hardware instance specific data.\r\n *\r\n * Returns STATUS_SUCCESS if successful, STATUS_UNSUCCESSFUL otherwise.\r\n */\r\nNTSTATUS DriverEntry(IN PDRIVER_OBJECT DriverObject, IN PUNICODE_STRING RegistryPath)\r\n{\r\n\tNTSTATUS status = STATUS_SUCCESS;\r\n\tWDF_DRIVER_CONFIG config;\r\n\tWDF_OBJECT_ATTRIBUTES attributes;\r\n\r\n\t// Initialize WDF WPP tracing.\r\n\tWPP_INIT_TRACING(DriverObject, RegistryPath);\r\n\r\n\t// TraceEvents function is mapped to DoTraceMessage provided by\r\n\t// WPP by using a directive in the sources file.\r\n\tTraceEvents(TRACE_LEVEL_INFORMATION, DBG_INIT, \"RIFFA Driver.\");\r\n\tTraceEvents(TRACE_LEVEL_INFORMATION, DBG_INIT, \"Built %s %s\", __DATE__, __TIME__);\r\n\r\n\t// Initialize the Driver Config structure.\r\n\tWDF_DRIVER_CONFIG_INIT(&config, RiffaEvtDeviceAdd);\r\n\r\n\t// Register a cleanup callback so that we can call WPP_CLEANUP when\r\n\t// the framework driver object is deleted during driver unload.\r\n\tWDF_OBJECT_ATTRIBUTES_INIT(&attributes);\r\n\tattributes.EvtCleanupCallback = RiffaEvtDriverContextCleanup;\r\n\r\n\t// Create the WDFDRIVER object\r\n\tstatus = WdfDriverCreate(DriverObject, RegistryPath, &attributes, &config,\r\n\t\tWDF_NO_HANDLE);\r\n\r\n\tif (!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: WdfDriverCreate failed\\n\");\r\n\r\n\t\t// Cleanup tracing here because DriverContextCleanup will not be called\r\n\t\t// as we have failed to create WDFDRIVER object itself.\r\n\t\tWPP_CLEANUP(DriverObject);\r\n\t}\r\n\r\n\treturn status;\r\n}\r\n\r\n\r\n\r\n/******************************************************************************\r\n * PNP EVENT CALLBACKS\r\n *****************************************************************************/\r\n\r\n/**\r\n * Called by the framework in response to AddDevice call from the PnP manager.\r\n * We create and initialize a WDF device object to represent a new instance of\r\n * our device.\r\n *\t.\r\n * Driver - Handle to a framework driver object created in DriverEntry\r\n *\r\n * DeviceInit - Pointer to a framework-allocated WDFDEVICE_INIT structure.\r\n *\r\n * Returns STATUS_SUCCESS if successful, another status otherwise.\r\n */\r\nNTSTATUS RiffaEvtDeviceAdd(IN WDFDRIVER Driver, IN PWDFDEVICE_INIT DeviceInit) {\r\n\tNTSTATUS status = STATUS_SUCCESS;\r\n\tWDF_PNPPOWER_EVENT_CALLBACKS pnpPowerCallbacks;\r\n\tWDF_OBJECT_ATTRIBUTES attributes;\r\n\tWDF_IO_QUEUE_CONFIG queueConfig;\r\n\tWDF_DMA_ENABLER_CONFIG dmaConfig;\r\n\tWDF_INTERRUPT_CONFIG intrConfig;\r\n\tWDFDEVICE device;\r\n\tPDEVICE_EXTENSION devExt = NULL;\r\n\r\n\tUNREFERENCED_PARAMETER(Driver);\r\n\r\n\tPAGED_CODE();\r\n\r\n\t// Setup direct I/O for read & write operations\r\n\tWdfDeviceInitSetIoType(DeviceInit, WdfDeviceIoDirect);\r\n\r\n\t// Zero out the PnpPowerCallbacks structure.\r\n\tWDF_PNPPOWER_EVENT_CALLBACKS_INIT(&pnpPowerCallbacks);\r\n\r\n\t// Register the PnP Callbacks.\r\n\tpnpPowerCallbacks.EvtDevicePrepareHardware = RiffaEvtDevicePrepareHardware;\r\n\tpnpPowerCallbacks.EvtDeviceReleaseHardware = RiffaEvtDeviceReleaseHardware;\r\n\tWdfDeviceInitSetPnpPowerEventCallbacks(DeviceInit, &pnpPowerCallbacks);\r\n\r\n\t// Initialize FDO Request context.\r\n\tWDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, REQUEST_EXTENSION);\r\n\tWdfDeviceInitSetRequestAttributes(DeviceInit, &attributes);\r\n\r\n\t// Initialize FDO Attributes.\r\n\tWDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, DEVICE_EXTENSION);\r\n\r\n\t// Create the device\r\n\tstatus = WdfDeviceCreate(&DeviceInit, &attributes, &device);\r\n\tif (!NT_SUCCESS(status)) {\r\n\t\t// Device Initialization failed.\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: DeviceCreate failed\\n\");\r\n\t\treturn status;\r\n\t}\r\n\r\n\t// Get the DeviceExtension and initialize it. RiffaGetDeviceContext is an\r\n\t// inline function defined by the WDF_DECLARE_CONTEXT_TYPE_WITH_NAME macro\r\n\t// in the private header file. This function will do the type checking and\r\n\t// return the device context. If you pass a wrong object a wrong object handle\r\n\t// it will return NULL and assert if run under framework verifier mode.\r\n\tdevExt = RiffaGetDeviceContext(device);\r\n\tmemset(devExt->IntrData, 0, 2 * RIFFA_MAX_NUM_CHNLS * sizeof(INTR_CHNL_DIR_DATA));\r\n\tmemset(devExt->Chnl, 0, 2 * RIFFA_MAX_NUM_CHNLS * sizeof(CHNL_DIR_STATE));\r\n\tdevExt->Device = device;\r\n\r\n\t// Create a new IO Queue for IRP_MJ_DEVICE_CONTROL requests.\r\n\tWDF_IO_QUEUE_CONFIG_INIT(&queueConfig, WdfIoQueueDispatchParallel);\r\n\tqueueConfig.EvtIoDeviceControl = RiffaEvtIoDeviceControl;\r\n\tstatus = WdfIoQueueCreate(device, &queueConfig, WDF_NO_OBJECT_ATTRIBUTES,\r\n\t\t&devExt->IoctlQueue);\r\n\tif(!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: WdfIoQueueCreate failed\\n\");\r\n\t\treturn status;\r\n\t}\r\n\r\n\t// Set the Ioctl Queue forwarding for IRP_MJ_DEVICE_CONTROL requests.\r\n\tstatus = WdfDeviceConfigureRequestDispatching(device, devExt->IoctlQueue,\r\n\t\tWdfRequestTypeDeviceControl);\r\n\tif(!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: DeviceConfigureRequestDispatching failed\\n\");\r\n\t\treturn status;\r\n\t}\r\n\r\n\t// Create a WDFINTERRUPT object.\r\n\tWDF_INTERRUPT_CONFIG_INIT(&intrConfig, RiffaEvtInterruptIsr, RiffaEvtInterruptDpc);\r\n\tintrConfig.AutomaticSerialization = TRUE;\r\n\tstatus = WdfInterruptCreate(device, &intrConfig, WDF_NO_OBJECT_ATTRIBUTES,\r\n\t\t&devExt->Interrupt);\r\n\tif(!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: WdfInterruptCreate failed\\n\");\r\n\t\treturn status;\r\n\t}\r\n\r\n\t// Create a new DMA Enabler instance. Use Scatter/Gather, 64-bit Addresses,\r\n\t// Duplex-type profile, 4-byte alignment.\r\n\tWdfDeviceSetAlignmentRequirement(device, FILE_LONG_ALIGNMENT);\r\n\tWDF_DMA_ENABLER_CONFIG_INIT(&dmaConfig, WdfDmaProfileScatterGather64Duplex,\r\n\t\tRIFFA_MAX_TNFR_LEN);\r\n\tstatus = WdfDmaEnablerCreate(device, &dmaConfig, WDF_NO_OBJECT_ATTRIBUTES,\r\n\t\t&devExt->DmaEnabler);\r\n\tif (!NT_SUCCESS (status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: WdfDmaEnablerCreate failed\\n\");\r\n\t\treturn status;\r\n\t}\r\n\r\n\t// Tell the Framework that this device will need an interface\r\n\t// NOTE: See the note in public.h concerning this GUID value.\r\n\tstatus = WdfDeviceCreateDeviceInterface(device, &GUID_RIFFA_INTERFACE, NULL);\r\n\tif (!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: DeviceCreateDeviceInterface failed\\n\");\r\n\t\treturn status;\r\n\t}\r\n\r\n\treturn status;\r\n}\r\n\r\n\r\n\r\n/**\r\n * Free all the resources allocated in DriverEntry.\r\n *\t.\r\n * Driver - handle to a WDF Driver object.\r\n */\r\nVOID RiffaEvtDriverContextCleanup(IN WDFDRIVER Driver) {\r\n\tPAGED_CODE ();\r\n\r\n\tWPP_CLEANUP(WdfDriverWdmGetDriverObject(Driver));\r\n}\r\n\r\n\r\n\r\n/**\r\n * Performs whatever initialization is needed to setup the device, setting up\r\n * a DMA channel or mapping any I/O port resources. This will only be called\r\n * as a device starts or restarts, not every time the device moves into the D0\r\n * state.\r\n *\t.\r\n * Device - A handle to the WDFDEVICE\r\n *\r\n * Resources - The raw PnP resources associated with the device.\r\n *\r\n * ResourcesTranslated - The translated PnP resources associated with the device.\r\n *\r\n * Returns STATUS_SUCCESS if successful, another status otherwise. Failure will\r\n * result in the device stack being torn down.\r\n */\r\nNTSTATUS RiffaEvtDevicePrepareHardware(WDFDEVICE Device, WDFCMRESLIST Resources,\r\n\tWDFCMRESLIST ResourcesTranslated) {\r\n\tNTSTATUS status;\r\n\tPDEVICE_EXTENSION devExt;\r\n\tPTIMER_EXTENSION timerExt;\r\n\tWDF_TIMER_CONFIG timerConfig;\r\n\tWDF_OBJECT_ATTRIBUTES attributes;\r\n\tPCM_PARTIAL_RESOURCE_DESCRIPTOR desc;\r\n\tBOOLEAN foundBar0 = FALSE;\r\n\tUINT32 info;\r\n\tUINT32 i;\r\n\r\n\tUNREFERENCED_PARAMETER(Resources);\r\n\r\n\tPAGED_CODE();\r\n\r\n\t// Get the device extension\r\n\tdevExt = RiffaGetDeviceContext(Device);\r\n\r\n\t// Parse the resource list and save the resource information.\r\n\tfor (i=0; i < WdfCmResourceListGetCount(ResourcesTranslated); i++) {\r\n\t\tdesc = WdfCmResourceListGetDescriptor(ResourcesTranslated, i);\r\n\t\tif(!desc) {\r\n\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\"riffa: WdfResourceCmGetDescriptor failed\\n\");\r\n\t\t\treturn STATUS_DEVICE_CONFIGURATION_ERROR;\r\n\t\t}\r\n\r\n\t\tswitch (desc->Type) {\r\n\r\n\t\t\tcase CmResourceTypeMemory:\r\n\t\t\t\tif (!foundBar0 && desc->u.Memory.Length == 0x400) {\r\n\t\t\t\t\t// Map in the Registers Memory resource: BAR0\r\n\t\t\t\t\tdevExt->Bar0Length = desc->u.Memory.Length;\r\n\t\t\t\t\tdevExt->Bar0 = (PULONG)MmMapIoSpace(desc->u.Memory.Start,\r\n\t\t\t\t\t\tdesc->u.Memory.Length, MmNonCached);\r\n\t\t\t\t\tif (!devExt->Bar0) {\r\n\t\t\t\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\t\t\t\"riffa: unable to map BAR memory %08I64X, length %d\",\r\n\t\t\t\t\t\t\tdesc->u.Memory.Start.QuadPart, desc->u.Memory.Length);\r\n\t\t\t\t\t\treturn STATUS_INSUFFICIENT_RESOURCES;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tfoundBar0 = TRUE;\r\n\t\t\t\t}\r\n\t\t\t\tbreak;\r\n\r\n\t\t\tdefault:\r\n\t\t\t\tbreak;\r\n\t\t}\r\n\t}\r\n\r\n\t// Make sure we found BAR0\r\n\tif (!foundBar0) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL, \"riffa: missing BAR0\\n\");\r\n\t\treturn STATUS_DEVICE_CONFIGURATION_ERROR;\r\n\t}\r\n\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: BAR0 address: %p\\n\", devExt->Bar0);\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: BAR0 length: %u\\n\", devExt->Bar0Length);\r\n\r\n\t// Read the device ids\r\n\tstatus = RiffaReadHardwareIds(devExt);\r\n\tif(!NT_SUCCESS(status))\r\n\t\treturn status;\r\n\r\n\t// Read the configuration register (also resets the device)\r\n\tinfo = READ_REGISTER_ULONG(devExt->Bar0 + RIFFA_INFO_REG);\r\n\tdevExt->NumChnls = (info & 0xF);\r\n\tdevExt->MaxNumScatterGatherElems = RIFFA_MIN_NUM_SG_ELEMS*((info>>19) & 0xF);\r\n\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: found FPGA with name: %s\\n\", devExt->Name);\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: vendor id: 0x%04X\\n\", devExt->VendorId);\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: device id: 0x%04X\\n\", devExt->DeviceId);\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: number of channels: %d\\n\", (info & 0xF));\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: bus interface width: %d\\n\", ((info>>19) & 0xF)<<5);\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: bus master enabled: %d\\n\", ((info>>4) & 0x1));\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: negotiated link width: %d\\n\", ((info>>5) & 0x3F));\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: negotiated link rate: %d MTs\\n\", ((info>>11) & 0x3)*2500);\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: max downstream payload: %d bytes\\n\", 128<<((info>>13) & 0x7));\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: max upstream payload: %d bytes\\n\", 128<<((info>>16) & 0x7));\r\n\r\n\t// Check for bus master enabled\r\n\tif (((info>>4) & 0x1) != 1) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: bus master not enabled!\\n\");\r\n\t\treturn STATUS_DEVICE_CONFIGURATION_ERROR;\r\n\t}\r\n\r\n\t// Check for valid link parameters\r\n\tif (((info>>5) & 0x3F) == 0 || ((info>>11) & 0x3) == 0) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: bad link parameters!\\n\");\r\n\t\treturn STATUS_DEVICE_CONFIGURATION_ERROR;\r\n\t}\r\n\r\n\t// Check for valid number of channels\r\n\tif ((info & 0xF) == 0 || (info & 0xF) > RIFFA_MAX_NUM_CHNLS) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: bad number of channels!\\n\");\r\n\t\treturn STATUS_DEVICE_CONFIGURATION_ERROR;\r\n\t}\r\n\r\n\t// Check for valid bus width\r\n\tif (((info>>19) & 0xF) == 0 || ((info>>19) & 0xF) > RIFFA_MAX_BUS_WIDTH_PARAM) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: bad bus width!\\n\");\r\n\t\treturn STATUS_DEVICE_CONFIGURATION_ERROR;\r\n\t}\r\n\r\n // Allocate common buffers, DMA transactions, spin locks, timers for each channel.\r\n\tfor (i = 0; i < devExt->NumChnls; i++) {\r\n\t\t// Common buffer creation, not cached.\r\n\t\tstatus = WdfCommonBufferCreate(devExt->DmaEnabler, RIFFA_MIN_SG_BUF_SIZE*((info>>19) & 0xF),\r\n\t\t\tWDF_NO_OBJECT_ATTRIBUTES, &devExt->Chnl[i].CommonBuffer);\r\n\t\tif (!NT_SUCCESS(status)) {\r\n\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\"riffa: WdfCommonBufferCreate failed\\n\");\r\n\t\t\treturn status;\r\n\t\t}\r\n\t\tdevExt->Chnl[i].CommonBufferBase =\r\n\t\t\tWdfCommonBufferGetAlignedVirtualAddress(devExt->Chnl[i].CommonBuffer);\r\n\t\tdevExt->Chnl[i].CommonBufferBaseLA =\r\n\t\t\tWdfCommonBufferGetAlignedLogicalAddress(devExt->Chnl[i].CommonBuffer);\r\n\r\n\t\tstatus = WdfCommonBufferCreate(devExt->DmaEnabler, RIFFA_MIN_SG_BUF_SIZE*((info>>19) & 0x1F),\r\n\t\t\tWDF_NO_OBJECT_ATTRIBUTES, &devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].CommonBuffer);\r\n\t\tif (!NT_SUCCESS(status)) {\r\n\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\"riffa: WdfCommonBufferCreate failed\\n\");\r\n\t\t\treturn status;\r\n\t\t}\r\n\t\tdevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].CommonBufferBase =\r\n\t\t\tWdfCommonBufferGetAlignedVirtualAddress(devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].CommonBuffer);\r\n\t\tdevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].CommonBufferBaseLA =\r\n\t\t\tWdfCommonBufferGetAlignedLogicalAddress(devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].CommonBuffer);\r\n\r\n\t\t// Since we are using sequential queue and processing one request at\r\n\t\t// a time, we will create transaction objects upfront and reuse them\r\n\t\t// to do DMA transfer. Transactions objects are parented to the DMA\r\n\t\t// enabler object by default. They will be deleted along with the DMA\r\n\t\t// enabler object. No need to delete them explicitly.\r\n\t\tWDF_OBJECT_ATTRIBUTES_INIT(&attributes);\r\n\t\tstatus = WdfDmaTransactionCreate(devExt->DmaEnabler, &attributes,\r\n\t\t\t&devExt->Chnl[i].DmaTransaction);\r\n\t\tif(!NT_SUCCESS(status)) {\r\n\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\"riffa: WdfDmaTransactionCreate failed\\n\");\r\n\t\t\treturn status;\r\n\t\t}\r\n\r\n\t\tWDF_OBJECT_ATTRIBUTES_INIT(&attributes);\r\n\t\tstatus = WdfDmaTransactionCreate(devExt->DmaEnabler, &attributes,\r\n\t\t\t&devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].DmaTransaction);\r\n\t\tif(!NT_SUCCESS(status)) {\r\n\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\"riffa: WdfDmaTransactionCreate failed\\n\");\r\n\t\t\treturn status;\r\n\t\t}\r\n\r\n\t\t// Create spinlocks for each direction. Make the parent the IOCTL queue\r\n\t\t// so that the spinlocks will be automatically deleted when the queue is.\r\n\t\tWDF_OBJECT_ATTRIBUTES_INIT(&attributes);\r\n\t\tattributes.ParentObject = devExt->IoctlQueue;\r\n\t\tstatus = WdfSpinLockCreate(&attributes,\r\n\t\t\t&devExt->Chnl[i].SpinLock);\r\n\t\tif (!NT_SUCCESS(status)) {\r\n\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\"riffa: WdfSpinLockCreate failed\\n\");\r\n\t\t\treturn status;\r\n\t\t}\r\n\r\n\t\tWDF_OBJECT_ATTRIBUTES_INIT(&attributes);\r\n\t\tattributes.ParentObject = devExt->IoctlQueue;\r\n\t\tstatus = WdfSpinLockCreate(&attributes,\r\n\t\t\t&devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].SpinLock);\r\n\t\tif (!NT_SUCCESS(status)) {\r\n\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\"riffa: WdfSpinLockCreate failed\\n\");\r\n\t\t\treturn status;\r\n\t\t}\r\n\r\n\t\t// Create a timer for each direction. Set the parent as the IOCTL queue\r\n\t\t// so that we can get the device extension and have the timer deleted\r\n\t\t// when the queue is. Also set the timer's context to have the chnl num.\r\n\t\tWDF_TIMER_CONFIG_INIT(&timerConfig, RiffaEvtTimerFunc);\r\n\t\tWDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, TIMER_EXTENSION);\r\n\t\tattributes.ParentObject = devExt->IoctlQueue;\r\n\t\tstatus = WdfTimerCreate(&timerConfig, &attributes,\r\n\t\t\t&devExt->Chnl[i].Timer);\r\n\t\tif (!NT_SUCCESS(status)) {\r\n\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\"riffa: WdfTimerCreate failed\\n\");\r\n\t\t\treturn status;\r\n\t\t}\r\n\t\ttimerExt = RiffaGetTimerContext(devExt->Chnl[i].Timer);\r\n\t\ttimerExt->Chnl = i;\r\n\r\n\t\tWDF_TIMER_CONFIG_INIT(&timerConfig, RiffaEvtTimerFunc);\r\n\t\tWDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, TIMER_EXTENSION);\r\n\t\tattributes.ParentObject = devExt->IoctlQueue;\r\n\t\tstatus = WdfTimerCreate(&timerConfig, &attributes,\r\n\t\t\t&devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].Timer);\r\n\t\tif (!NT_SUCCESS(status)) {\r\n\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\"riffa: WdfTimerCreate failed\\n\");\r\n\t\t\treturn status;\r\n\t\t}\r\n\t\ttimerExt = RiffaGetTimerContext(devExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].Timer);\r\n\t\ttimerExt->Chnl = RIFFA_MAX_NUM_CHNLS + i;\r\n\t}\r\n\r\n\t// Create spill buffer, not cached.\r\n\tstatus = WdfCommonBufferCreate(devExt->DmaEnabler, RIFFA_SPILL_BUF_SIZE,\r\n\t\tWDF_NO_OBJECT_ATTRIBUTES, &devExt->SpillBuffer);\r\n\tif (!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: WdfCommonBufferCreate failed\\n\");\r\n\t\treturn status;\r\n\t}\r\n\tdevExt->SpillBufferBase =\r\n\t\tWdfCommonBufferGetAlignedVirtualAddress(devExt->SpillBuffer);\r\n\tdevExt->SpillBufferBaseLA =\r\n\t\tWdfCommonBufferGetAlignedLogicalAddress(devExt->SpillBuffer);\r\n\r\n\treturn STATUS_SUCCESS;\r\n}\r\n\r\n\r\n\r\n/**\r\n * Unmap the resources that were mapped in RiffaEvtDevicePrepareHardware.\r\n * This will only be called when the device stopped for resource rebalance,\r\n * surprise-removed or query-removed.\r\n *\t.\r\n * Device - A handle to the WDFDEVICE\r\n *\r\n * ResourcesTranslated - The translated PnP resources associated with the device.\r\n *\r\n * Returns STATUS_SUCCESS if successful, another status otherwise. Failure will\r\n * result in the device stack being torn down.\r\n */\r\nNTSTATUS RiffaEvtDeviceReleaseHardware(IN WDFDEVICE Device, IN WDFCMRESLIST ResourcesTranslated) {\r\n\tPDEVICE_EXTENSION devExt;\r\n\tNTSTATUS status = STATUS_SUCCESS;\r\n\r\n\tUNREFERENCED_PARAMETER(ResourcesTranslated);\r\n\r\n\tPAGED_CODE();\r\n\r\n\t// Get the device extension\r\n\tdevExt = RiffaGetDeviceContext(Device);\r\n\r\n\t// Unmap the I/O address space BAR0\r\n\tif (devExt->Bar0) {\r\n\t\tMmUnmapIoSpace(devExt->Bar0, devExt->Bar0Length);\r\n\t\tdevExt->Bar0 = NULL;\r\n\t}\r\n\r\n\treturn status;\r\n}\r\n\r\n\r\n\r\n/**\r\n * Attempts to read the hardware ids (vendor id, device id, bus num,\r\n * device num, function num) and set it in the PDEVICE_EXTENSION object.\r\n *\t.\r\n * DevExt - Pointer to the Device Extension\r\n *\r\n * Returns STATUS_SUCCESS if successful, another status otherwise.\r\n */\r\nNTSTATUS RiffaReadHardwareIds(IN PDEVICE_EXTENSION DevExt) {\r\n\tNTSTATUS status;\r\n\tPDEVICE_OBJECT pdo;\r\n\tUINT32 length;\r\n\tUINT32 pciBus;\r\n\tUINT32 pciAddr;\r\n\tUSHORT pciDev;\r\n\tUSHORT pciFxn;\r\n\tWCHAR hwIds[2048];\r\n\twchar_t * id;\r\n\r\n\t// Initialize the values\r\n\tDevExt->DeviceId = 0;\r\n\tDevExt->VendorId = 0;\r\n\tDevExt->Name[0] = 0;\r\n\r\n\t// Get the PDO from our FDO.\r\n\tpdo = WdfDeviceWdmGetPhysicalDevice(DevExt->Device);\r\n\r\n\t// Read DevicePropertyBusNumber.\r\n\tstatus = IoGetDeviceProperty(pdo, DevicePropertyBusNumber, sizeof(UINT32),\r\n\t\t(PVOID)&pciBus, &length);\r\n\tif(!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: IoGetDeviceProperty failed\\n\");\r\n\t\treturn status;\r\n\t}\r\n\r\n\t// Read DevicePropertyAddress (contains device and function).\r\n\tstatus = IoGetDeviceProperty(pdo, DevicePropertyAddress, sizeof(UINT32),\r\n\t\t(PVOID)&pciAddr, &length);\r\n\tif(!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: IoGetDeviceProperty failed\\n\");\r\n\t\treturn status;\r\n\t}\r\n\r\n\t// Parse the function and device values and create a name.\r\n\tpciFxn = (USHORT)((pciAddr) & 0x0000FFFF);\r\n\tpciDev = (USHORT)(((pciAddr)>>16) & 0x0000FFFF);\r\n\tsprintf_s(DevExt->Name, 16, \"%02x:%02x:%01x\", pciBus, pciDev, pciFxn);\r\n\r\n\t// Read Device HardwareID. Should be something like:\r\n\t// PCI\\VEN_10B5&DEV_515A&SUBSYS_905610B5&REV_02\r\n\tstatus = IoGetDeviceProperty(pdo, DevicePropertyHardwareID, 2048,\r\n\t\t(PVOID)hwIds, &length);\r\n\tif(!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: IoGetDeviceProperty failed\\n\");\r\n\t\treturn status;\r\n\t}\r\n\r\n\t// Null terminate the string.\r\n\thwIds[length] = 0; // Add null-char\r\n\r\n\t// Search for the device id.\r\n\tid = wcsstr(hwIds, L\"DEV_\");\r\n\tif (id == NULL) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: bad DevicePropertyHardwareID, no device id in: %S\\n\", hwIds);\r\n\t\treturn STATUS_DEVICE_CONFIGURATION_ERROR;\r\n\t}\r\n\r\n\t// Null terminate after the 4 char id and convert into an int.\r\n\thwIds[((int)(id - hwIds)) + 8] = 0; // Add null-char\r\n\tswscanf_s(id + 4, L\"%x\", &DevExt->DeviceId);\r\n\r\n\t// Search for the vendor id.\r\n\tid = wcsstr(hwIds, L\"VEN_\");\r\n\tif (id == NULL) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: bad DevicePropertyHardwareID, no vendor id in: %S\\n\", hwIds);\r\n\t\treturn STATUS_DEVICE_CONFIGURATION_ERROR;\r\n\t}\r\n\thwIds[((int)(id - hwIds)) + 8] = 0; // Add null-char\r\n\tswscanf_s(id + 4, L\"%x\", &DevExt->VendorId);\r\n\r\n\treturn STATUS_SUCCESS;\r\n}\r\n\r\n\r\n\r\n/******************************************************************************\r\n * INTERRUPT FUNCTIONS\r\n *****************************************************************************/\r\n\r\n/**\r\n * Interrupt handler for this driver. Called at DIRQL level when the\r\n * device or another device sharing the same interrupt line asserts\r\n * the interrupt. The driver first checks the device to make sure whether\r\n * this interrupt is generated by its device and if so clear the interrupt\r\n * register to disable further generation of interrupts and queue a\r\n * DPC to do other I/O work related to interrupt - such as reading\r\n * the device memory, starting a DMA transaction, coping it to\r\n * the request buffer and completing the request, etc.\r\n *\t.\r\n * Interupt - Handle to WDFINTERRUPT Object for this device.\r\n *\r\n * MessageID - MSI message ID (always 0 in this configuration)\r\n *\r\n * Returns TRUE if this device generated the interrupt, FALSE otherwise.\r\n */\r\nBOOLEAN RiffaEvtInterruptIsr(IN WDFINTERRUPT Interrupt, IN ULONG MessageID) {\r\n\tPDEVICE_EXTENSION devExt;\r\n\tUINT32 vect0 = 0;\r\n\tUINT32 vect1 = 0;\r\n\tBOOLEAN recog = FALSE;\r\n\r\n\tUNREFERENCED_PARAMETER(MessageID);\r\n\r\n\tdevExt = RiffaGetDeviceContext(WdfInterruptGetDevice(Interrupt));\r\n\r\n\t// Read the interrupt register\r\n\tvect0 = READ_REGISTER_ULONG(devExt->Bar0 + RIFFA_IRQ_0_REG);\r\n\tif (devExt->NumChnls > 6)\r\n\t\tvect1 = READ_REGISTER_ULONG(devExt->Bar0 + RIFFA_IRQ_1_REG);\r\n\r\n\t// Process the interrupt vector(s)\r\n\trecog = RiffaProcessInterrupt(devExt, 0, vect0);\r\n\tif (devExt->NumChnls > 6)\r\n\t\trecog = (recog | RiffaProcessInterrupt(devExt, 6, vect1));\r\n\r\n\t// Queue a callback for the DPC if needed.\r\n\tif (recog)\r\n\t\tWdfInterruptQueueDpcForIsr(Interrupt);\r\n\r\n\treturn recog;\r\n}\r\n\r\n\r\n\r\n/**\r\n * Processes the interrupt vector read from the device during the interrupt\r\n * service routine. The vectors are organized from right to left (LSB to MSB) as:\r\n * [ 0] TX_TXN\t\t\t for channel 0 in VECT_0, channel 6 in VECT_1\r\n * [ 1] TX_SG_BUF_RECVD\t for channel 0 in VECT_0, channel 6 in VECT_1\r\n * [ 2] TX_TXN_DONE\t\t for channel 0 in VECT_0, channel 6 in VECT_1\r\n * [ 3] RX_SG_BUF_RECVD\t for channel 0 in VECT_0, channel 6 in VECT_1\r\n * [ 4] RX_TXN_DONE\t\t for channel 0 in VECT_0, channel 6 in VECT_1\r\n * ...\r\n * [25] TX_TXN\t\t\t for channel 5 in VECT_0, channel 11 in VECT_1\r\n * [26] TX_SG_BUF_RECVD\t for channel 5 in VECT_0, channel 11 in VECT_1\r\n * [27] TX_TXN_DONE\t\t for channel 5 in VECT_0, channel 11 in VECT_1\r\n * [28] RX_SG_BUF_RECVD\t for channel 5 in VECT_0, channel 11 in VECT_1\r\n * [29] RX_TXN_DONE\t\t for channel 5 in VECT_0, channel 11 in VECT_1\r\n * Positions 30 - 31 in both VECT_0 and VECT_1 are zero.\r\n *\t.\r\n * DevExt - Pointer to the Device Extension\r\n *\r\n * Offset - Channel offset\r\n *\r\n * Vect - Interrupt vector\r\n *\r\n * Returns TRUE if a DPC should be queued to do more work, FALSE otherwise.\r\n */\r\nBOOLEAN RiffaProcessInterrupt(IN PDEVICE_EXTENSION DevExt, IN UINT32 Offset,\r\n\tIN UINT32 Vect) {\r\n\tBOOLEAN queueDpc = FALSE;\r\n\tUINT32 offlast;\r\n\tUINT32 len;\r\n\tint i;\r\n\tint chnl;\r\n\r\n\tif (Vect & 0xC0000000) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, received invalid interrupt:0x%08x\\n\", DevExt->Name, Vect);\r\n\t\treturn FALSE;\r\n\t}\r\n\r\n\tfor (i = 0; i < 6 && (i+Offset) < DevExt->NumChnls; i++) {\r\n\t\tchnl = i + Offset;\r\n\r\n\t\t// New TX (PC receive) transaction.\r\n\t\tif (Vect & (1<<((5*i)+0))) {\r\n\t\t\tqueueDpc = TRUE;\r\n\t\t\t// Read the offset/last and length\r\n\t\t\tofflast = READ_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(chnl, RIFFA_TX_OFFLAST_REG));\r\n\t\t\tlen = READ_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(chnl, RIFFA_TX_LEN_REG));\r\n\t\t\tDevExt->IntrData[RIFFA_MAX_NUM_CHNLS + chnl].OffLast = offlast;\r\n\t\t\tDevExt->IntrData[RIFFA_MAX_NUM_CHNLS + chnl].Length = len;\r\n\t\t\tDevExt->IntrData[RIFFA_MAX_NUM_CHNLS + chnl].NewTxn = TRUE;\r\n\t\t}\r\n\r\n\t\t// TX (PC receive) scatter gather buffer is read.\r\n\t\tif (Vect & (1<<((5*i)+1))) {\r\n\t\t\tqueueDpc = TRUE;\r\n\t\t\tDevExt->IntrData[RIFFA_MAX_NUM_CHNLS + chnl].SgRead = TRUE;\r\n\t\t}\r\n\r\n\t\t// TX (PC receive) transaction done.\r\n\t\tif (Vect & (1<<((5*i)+2))) {\r\n\t\t\tqueueDpc = TRUE;\r\n\t\t\tDevExt->IntrData[RIFFA_MAX_NUM_CHNLS + chnl].Done = TRUE;\r\n\t\t}\r\n\r\n\t\t// RX (PC send) scatter gather buffer is read.\r\n\t\tif (Vect & (1<<((5*i)+3))) {\r\n\t\t\tqueueDpc = TRUE;\r\n\t\t\tDevExt->IntrData[chnl].SgRead = TRUE;\r\n\t\t}\r\n\r\n\t\t// RX (PC send) transaction done.\r\n\t\tif (Vect & (1<<((5*i)+4))) {\r\n\t\t\tqueueDpc = TRUE;\r\n\t\t\tDevExt->IntrData[chnl].Done = TRUE;\r\n\t\t}\r\n\t}\r\n\r\n\treturn queueDpc;\r\n}\r\n\r\n\r\n\r\n/**\r\n * DPC callback for ISR. Please note that on a multiprocessor system,\r\n * you could have more than one DPCs running simulataneously on\r\n * multiple processors. So if you are accesing any global resources\r\n * make sure to synchrnonize the accesses with a spinlock.\r\n *\t.\r\n * Interupt - Handle to WDFINTERRUPT Object for this device.\r\n *\r\n * Device - WDFDEVICE object passed to InterruptCreate\r\n */\r\nVOID RiffaEvtInterruptDpc(IN WDFINTERRUPT Interrupt, IN WDFDEVICE Device) {\r\n\tNTSTATUS status;\r\n\tBOOLEAN txnComplete;\r\n\tBOOLEAN cont;\r\n\tPDEVICE_EXTENSION devExt;\r\n\tINTR_CHNL_DIR_DATA intrData[2 * RIFFA_MAX_NUM_CHNLS];\r\n\tUINT32 chnl;\r\n\tUINT32 tnfr;\r\n\tUINT64 length;\r\n\tLONG doneReqd;\r\n\r\n\tUNREFERENCED_PARAMETER(Device);\r\n\r\n\tdevExt = RiffaGetDeviceContext(WdfInterruptGetDevice(Interrupt));\r\n\r\n\t// Acquire this device's InterruptSpinLock.\r\n\tWdfInterruptAcquireLock(Interrupt);\r\n\r\n\t// Copy over the values and zero them out.\r\n\tmemcpy(&intrData, devExt->IntrData,\r\n\t\t2 * RIFFA_MAX_NUM_CHNLS * sizeof(INTR_CHNL_DIR_DATA));\r\n\tmemset(devExt->IntrData, 0,\r\n\t\t2 * RIFFA_MAX_NUM_CHNLS * sizeof(INTR_CHNL_DIR_DATA));\r\n\r\n\t// Release our interrupt spinlock\r\n\tWdfInterruptReleaseLock(Interrupt);\r\n\r\n\t// Update state for each channel\r\n\tfor (chnl = 0; chnl < devExt->NumChnls; chnl++) {\r\n\t\t// Send more scatter gather elements.\r\n\t\tif (intrData[RIFFA_MAX_NUM_CHNLS + chnl].SgRead == TRUE) {\r\n\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\"riffa: fpga:%s chnl:%d, recv sg buf read\\n\", devExt->Name, chnl));\r\n\t\t\tRiffaProgramScatterGather(devExt, RIFFA_MAX_NUM_CHNLS + chnl);\r\n\t\t}\r\n\r\n\t\t// Finished with upstream transfer.\r\n\t\tif (intrData[RIFFA_MAX_NUM_CHNLS + chnl].Done == TRUE) {\r\n\t\t\t// Acquire the channel lock, check if request is null, release.\r\n\t\t\tWdfSpinLockAcquire(devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].SpinLock);\r\n\t\t\tcont = (devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].Request != NULL);\r\n\t\t\tWdfSpinLockRelease(devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].SpinLock);\r\n\t\t\tif (cont) {\r\n\t\t\t\t// Check if we've requested a done (in the event of a split transaction)\r\n\t\t\t\tdoneReqd = InterlockedExchange(&devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].ReqdDone, 0);\r\n\t\t\t\t// Indicate this DMA operation has completed. This might result in\r\n\t\t\t\t// another transfer if there is still data to be transfered in the request.\r\n\t\t\t\ttxnComplete = WdfDmaTransactionDmaCompleted(\r\n\t\t\t\t\tdevExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].DmaTransaction, &status);\r\n\t\t\t\tif (txnComplete) {\r\n\t\t\t\t\t// Read the actual transfer length\r\n\t\t\t\t\ttnfr = READ_REGISTER_ULONG(devExt->Bar0 + CHNL_REG(chnl, RIFFA_TX_TNFR_LEN_REG));\r\n\t\t\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\t\t\"riffa: fpga:%s chnl:%d, recv txn done\\n\", devExt->Name, chnl));\r\n\t\t\t\t\tRiffaTransactionComplete(devExt, RIFFA_MAX_NUM_CHNLS + chnl, tnfr, status);\r\n\t\t\t\t}\r\n\t\t\t\telse {\r\n\t\t\t\t\tif (doneReqd == 0) {\r\n\t\t\t\t\t\t// Not complete and not expecting a done signal. Must be an error.\r\n\t\t\t\t\t\t// End the transaction early. Read the actual transfer length\r\n\t\t\t\t\t\ttnfr = READ_REGISTER_ULONG(devExt->Bar0 + CHNL_REG(chnl, RIFFA_TX_TNFR_LEN_REG));\r\n\t\t\t\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\t\t\t\"riffa: fpga:%s chnl:%d, recv txn done\\n\", devExt->Name, chnl));\r\n\t\t\t\t\t\tRiffaTransactionComplete(devExt, RIFFA_MAX_NUM_CHNLS + chnl, tnfr, STATUS_TRANSACTION_ABORTED);\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse {\r\n\t\t\t\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\t\t\t\"riffa: fpga:%s chnl:%d, recv txn split, registers remapped\\n\", devExt->Name, chnl));\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\t// New upstream transfer.\r\n\t\tif (intrData[RIFFA_MAX_NUM_CHNLS + chnl].NewTxn == TRUE) {\r\n\t\t\t// If the user has already called the receive function, start the\r\n\t\t\t// transaction. If not, set the transaction data and the \"ready\"\r\n\t\t\t// bit so that when the user calls the receive function, the\r\n\t\t\t// transaction can start.\r\n\t\t\tdevExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].Length =\r\n\t\t\t\t(((UINT64)intrData[RIFFA_MAX_NUM_CHNLS + chnl].Length)<<2);\r\n\t\t\tdevExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].Offset =\r\n\t\t\t\t(((UINT64)(intrData[RIFFA_MAX_NUM_CHNLS + chnl].OffLast>>1))<<2);\r\n\t\t\tdevExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].Last =\r\n\t\t\t\t(intrData[RIFFA_MAX_NUM_CHNLS + chnl].OffLast & 0x1);\r\n\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\"riffa: fpga:%s chnl:%d, new recv txn (len:%u off:%u last:%d)\\n\",\r\n\t\t\t\tdevExt->Name, chnl, intrData[RIFFA_MAX_NUM_CHNLS + chnl].Length,\r\n\t\t\t\tintrData[RIFFA_MAX_NUM_CHNLS + chnl].OffLast>>1,\r\n\t\t\t\tintrData[RIFFA_MAX_NUM_CHNLS + chnl].OffLast & 0x1));\r\n\t\t\tif (InterlockedExchange(&devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].Ready, 2) == 1) {\r\n\t\t\t\t// Clear the \"ready\" bit and start the transaction\r\n\t\t\t\tInterlockedExchange(&devExt->Chnl[RIFFA_MAX_NUM_CHNLS + chnl].Ready, 0);\r\n\t\t\t\tRiffaStartRecvTransaction(devExt, RIFFA_MAX_NUM_CHNLS + chnl);\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\t// Send more scatter gather elements.\r\n\t\tif (intrData[chnl].SgRead == TRUE) {\r\n\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\"riffa: fpga:%s chnl:%d, send sg buf read\\n\", devExt->Name, chnl));\r\n\t\t\tRiffaProgramScatterGather(devExt, chnl);\r\n\t\t}\r\n\r\n\t\t// Finished with downstream transfer.\r\n\t\tif (intrData[chnl].Done == TRUE) {\r\n\t\t\t// Acquire the channel lock, check if request is null, release.\r\n\t\t\tWdfSpinLockAcquire(devExt->Chnl[chnl].SpinLock);\r\n\t\t\tcont = (devExt->Chnl[chnl].Request != NULL);\r\n\t\t\tWdfSpinLockRelease(devExt->Chnl[chnl].SpinLock);\r\n\t\t\tif (cont) {\r\n\t\t\t\t// Check if we've requested a done (in the event of a split transaction)\r\n\t\t\t\tdoneReqd = InterlockedExchange(&devExt->Chnl[chnl].ReqdDone, 0);\r\n\t\t\t\t// Indicate this DMA operation has completed. This may result in\r\n\t\t\t\t// another transfer if there is still data to be transfered in the request.\r\n\t\t\t\ttxnComplete = WdfDmaTransactionDmaCompleted(\r\n\t\t\t\t\tdevExt->Chnl[chnl].DmaTransaction, &status);\r\n\t\t\t\tif (txnComplete) {\r\n\t\t\t\t\t// Read the actual transfer length\r\n\t\t\t\t\ttnfr = READ_REGISTER_ULONG(devExt->Bar0 + CHNL_REG(chnl, RIFFA_RX_TNFR_LEN_REG));\r\n\t\t\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\t\t\"riffa: fpga:%s chnl:%d, send txn done\\n\", devExt->Name, chnl));\r\n\t\t\t\t\tRiffaTransactionComplete(devExt, chnl, tnfr, status);\r\n\t\t\t\t}\r\n\t\t\t\telse {\r\n\t\t\t\t\tif (doneReqd == 0) {\r\n\t\t\t\t\t\t// Not complete and not expecting a done signal. Must be an error.\r\n\t\t\t\t\t\t// End the transaction early. Read the actual transfer length\r\n\t\t\t\t\t\ttnfr = READ_REGISTER_ULONG(devExt->Bar0 + CHNL_REG(chnl, RIFFA_RX_TNFR_LEN_REG));\r\n\t\t\t\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\t\t\t\"riffa: fpga:%s chnl:%d, send txn done\\n\", devExt->Name, chnl));\r\n\t\t\t\t\t\tRiffaTransactionComplete(devExt, chnl, tnfr, STATUS_TRANSACTION_ABORTED);\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse {\r\n\t\t\t\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\t\t\t\"riffa: fpga:%s chnl:%d, send txn split, registers remapped\\n\", devExt->Name, chnl));\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n}\r\n\r\n\r\n\r\n/******************************************************************************\r\n * IOCTL FUNCTIONS\r\n *****************************************************************************/\r\n\r\n/**\r\n * This event is called when the framework receives IRP_MJ_DEVICE_CONTROL\r\n * requests from the system.\r\n *\t.\r\n * Queue - Handle to the framework queue object that is associated with the\r\n * I/O request.\r\n *\r\n * Request - Handle to a framework request object.\r\n *\r\n * OutputBufferLength - Length of the request's output buffer,\r\n * if an output buffer is available.\r\n *\r\n * InputBufferLength - Length of the request's input buffer,\r\n * if an input buffer is available.\r\n *\r\n * IoControlCode - the driver-defined or system-defined I/O control code\r\n * (IOCTL) that is associated with the request.\r\n */\r\nVOID RiffaEvtIoDeviceControl(IN WDFQUEUE Queue, IN WDFREQUEST Request,\r\n\tIN size_t OutputBufferLength, IN size_t InputBufferLength,\r\n\tIN ULONG IoControlCode) {\r\n PDEVICE_EXTENSION devExt;\r\n\r\n devExt = RiffaGetDeviceContext(WdfIoQueueGetDevice(Queue));\r\n\r\n // Determine which I/O control code was specified.\r\n switch (IoControlCode) {\r\n\r\n case IOCTL_RIFFA_SEND: // (METHOD_OUT_DIRECT)\r\n \tRiffaIoctlSend(devExt, Request, OutputBufferLength, InputBufferLength);\r\n\t\tbreak;\r\n\r\n case IOCTL_RIFFA_RECV: // (METHOD_OUT_DIRECT)\r\n \tRiffaIoctlRecv(devExt, Request, OutputBufferLength, InputBufferLength);\r\n\t\tbreak;\r\n\r\n case IOCTL_RIFFA_LIST: // (METHOD_OUT_DIRECT)\r\n \tRiffaIoctlList(devExt, Request, OutputBufferLength, InputBufferLength);\r\n\t\tbreak;\r\n\r\n case IOCTL_RIFFA_RESET: // (METHOD_OUT_DIRECT)\r\n \tRiffaIoctlReset(devExt, Request);\r\n\t\tbreak;\r\n\r\n default:\r\n // The specified I/O control code is unrecognized by this driver.\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, invalid ioctl request type\\n\", devExt->Name);\r\n WdfRequestCompleteWithInformation(Request, STATUS_INVALID_DEVICE_REQUEST, 0);\r\n break;\r\n }\r\n}\r\n\r\n\r\n/**\r\n * Handles IRP_MJ_DEVICE_CONTROL requests for IOCTL_RIFFA_SEND.\r\n *\t.\r\n * DevExt - Handle to the device extension object.\r\n *\r\n * Request - Handle to a framework request object.\r\n *\r\n * OutputBufferLength - Length of the request's output buffer,\r\n * if an output buffer is available.\r\n *\r\n * InputBufferLength - Length of the request's input buffer,\r\n * if an input buffer is available.\r\n */\r\nVOID RiffaIoctlSend(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,\r\n\tIN size_t OutputBufferLength, IN size_t InputBufferLength) {\r\n NTSTATUS status = STATUS_SUCCESS;\r\n PREQUEST_EXTENSION reqExt;\r\n PRIFFA_FPGA_CHNL_IO io;\r\n\tUINT64 length;\r\n\tPCHAR buf = NULL;\r\n\tsize_t bufSize;\r\n\r\n\t// Input should be non-zero\r\n\tif(!InputBufferLength) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl send zero length input buffer\\n\", DevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\r\n\t// Get the input buffer\r\n\tstatus = WdfRequestRetrieveInputBuffer(Request, 0, &buf, &bufSize);\r\n\tif (!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl send WdfRequestRetrieveInputBuffer failed\\n\",\r\n\t\t\tDevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, status, 0);\r\n\t\treturn;\r\n\t}\r\n\tif (bufSize < sizeof(RIFFA_FPGA_CHNL_IO)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl send input buffer too small to contain RIFFA_FPGA_CHNL_IO\\n\",\r\n\t\t\tDevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\tio = (PRIFFA_FPGA_CHNL_IO)buf;\r\n\r\n\t// Validate the length, last, chnl\r\n\tlength = (io->Length < (OutputBufferLength>>2) ? io->Length : (OutputBufferLength>>2));\r\n\tif (io->Last > 1) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl send invalid last: %d\\n\", DevExt->Name, io->Last);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\tif (io->Chnl >= DevExt->NumChnls) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl send invalid channel: %d, device only has %d channel(s)\\n\",\r\n\t\t\tDevExt->Name, io->Chnl, DevExt->NumChnls);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\r\n\t// Check that this isn't an already running transaction\r\n\tif (InterlockedExchange(&DevExt->Chnl[io->Chnl].InUse, 1) == 1) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl send already in use on channel: %d\\n\",\r\n\t\t\tDevExt->Name, io->Chnl);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\r\n\t// Set the channel number in the request context for RiffaEvtRequestCancel.\r\n reqExt = RiffaGetRequestContext(Request);\r\n reqExt->Chnl = io->Chnl;\r\n\r\n\t// Start a send transaction.\r\n\tif (length) {\r\n\t\t// Start a DMA transaction for sending.\r\n\t\tDevExt->Chnl[io->Chnl].Timeout = io->Timeout;\r\n\t\tDevExt->Chnl[io->Chnl].Length = (length<<2);\r\n\t\tDevExt->Chnl[io->Chnl].SpillAfter = (length<<2);\r\n\t\tDevExt->Chnl[io->Chnl].Offset = (io->Offset<<2);\r\n\t\tDevExt->Chnl[io->Chnl].Last = io->Last;\r\n\t\tDevExt->Chnl[io->Chnl].Provided = 0;\r\n\t\tDevExt->Chnl[io->Chnl].ProvidedPrev = 0;\r\n\t\tDevExt->Chnl[io->Chnl].Confirmed = 0;\r\n\t\tDevExt->Chnl[io->Chnl].ConfirmedPrev = 0;\r\n\t\tDevExt->Chnl[io->Chnl].ActiveCount = 0;\r\n\t\tDevExt->Chnl[io->Chnl].Cancel = 0;\r\n\t\tDevExt->Chnl[io->Chnl].Request = Request;\r\n\t\tInterlockedExchange(&DevExt->Chnl[io->Chnl].ReqdDone, 0);\r\n\t\tstatus = RiffaStartDmaTransaction(DevExt, io->Chnl, (length<<2),\r\n\t\t\t0, WdfDmaDirectionWriteToDevice);\r\n\t\tif (!NT_SUCCESS(status)) {\r\n\t\t\tWdfRequestCompleteWithInformation(Request, status, 0);\r\n\t\t}\r\n\t\telse {\r\n\t\t\t// Mark the WDFREQUEST as cancellable.\r\n\t\t\tstatus = WdfRequestMarkCancelableEx(Request, RiffaEvtRequestCancel);\r\n\t\t\tif (!NT_SUCCESS(status)) {\r\n\t\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\t\"riffa: fpga:%s, ioctl send WdfRequestMarkCancelableEx failed\\n\",\r\n\t\t\t\t\tDevExt->Name);\r\n\t\t\t\tWdfRequestCompleteWithInformation(Request, status, 0);\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\telse if (io->Last) {\r\n\t\t// Program the device for zero length send (device RX) and complete\r\n\t\tRiffaProgramSend(DevExt, io->Chnl, (UINT32)length, io->Offset, io->Last);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_SUCCESS, 0);\r\n\t}\r\n\telse {\r\n\t\t// Invalid request, results in no send\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl send invalid, no length or last\\n\", DevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t}\r\n}\r\n\r\n\r\n\r\n/**\r\n * Handles IRP_MJ_DEVICE_CONTROL requests for IOCTL_RIFFA_RECV.\r\n *\t.\r\n * DevExt - Handle to the device extension object.\r\n *\r\n * Request - Handle to a framework request object.\r\n *\r\n * OutputBufferLength - Length of the request's output buffer,\r\n * if an output buffer is available.\r\n *\r\n * InputBufferLength - Length of the request's input buffer,\r\n * if an input buffer is available.\r\n */\r\nVOID RiffaIoctlRecv(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,\r\n\tIN size_t OutputBufferLength, IN size_t InputBufferLength) {\r\n NTSTATUS status = STATUS_SUCCESS;\r\n\tPREQUEST_EXTENSION reqExt;\r\n PRIFFA_FPGA_CHNL_IO io;\r\n\tUINT64 length;\r\n\tPCHAR buf = NULL;\r\n\tsize_t bufSize;\r\n\r\n\t// Input should be non-zero\r\n\tif(!InputBufferLength) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl recv zero length input buffer\\n\", DevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\r\n\t// Get the input buffer\r\n\tstatus = WdfRequestRetrieveInputBuffer(Request, 0, &buf, &bufSize);\r\n\tif (!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl recv WdfRequestRetrieveInputBuffer failed\\n\",\r\n\t\t\tDevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, status, 0);\r\n\t\treturn;\r\n\t}\r\n\tif (bufSize < sizeof(RIFFA_FPGA_CHNL_IO)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl recv input buffer too small to contain RIFFA_FPGA_CHNL_IO\\n\",\r\n\t\t\tDevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\tio = (PRIFFA_FPGA_CHNL_IO)buf;\r\n\r\n\t// Validate the length, chnl\r\n\tlength = (io->Length < (OutputBufferLength>>2) ? io->Length : (OutputBufferLength>>2));\r\n\tif (io->Chnl >= DevExt->NumChnls) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl recv invalid channel: %d, device only has %d channel(s)\\n\",\r\n\t\t\tDevExt->Name, io->Chnl, DevExt->NumChnls);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\r\n\t// Check that this isn't an already running transaction\r\n\tif (InterlockedExchange(&DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].InUse, 1) == 1) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl recv already in use on channel: %d\\n\",\r\n\t\t\tDevExt->Name, io->Chnl);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\r\n\t// Set the channel number in the request context for RiffaEvtRequestCancel.\r\n reqExt = RiffaGetRequestContext(Request);\r\n reqExt->Chnl = RIFFA_MAX_NUM_CHNLS + io->Chnl;\r\n\r\n\t// Start a receive transaction. If an interrupt with the transaction\r\n\t// info has already been received, start the transaction. If not, set\r\n\t// this transaction request and the \"ready\" bit so that when the\r\n\t// interrupt is received the transaction can start.\r\n\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Timeout = io->Timeout;\r\n\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Capacity = (length<<2);\r\n\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Provided = 0;\r\n\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].ProvidedPrev = 0;\r\n\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Confirmed = 0;\r\n\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].ConfirmedPrev = 0;\r\n\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].ActiveCount = 0;\r\n\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Cancel = 0;\r\n\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Request = Request;\r\n\tInterlockedExchange(&DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].ReqdDone, 0);\r\n\tif (InterlockedExchange(&DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Ready, 1) == 2) {\r\n\t\t// Clear the \"ready\" bit and start the transaction\r\n\t\tInterlockedExchange(&DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Ready, 0);\r\n\r\n\t\t// Start a recv transaction.\r\n\t\tif (DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Length) {\r\n\t\t\t// Calculate room in the user space buffer and what needs to be spilled\r\n\t\t\tif (DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Capacity >\r\n\t\t\t\t\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Offset) {\r\n\t\t\t\t// Some (possibly all) of the data can fit in the user buffer.\r\n\t\t\t\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].SpillAfter =\r\n\t\t\t\t\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Capacity -\r\n\t\t\t\t\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Offset;\r\n\t\t\t\tlength = (DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Capacity <\r\n\t\t\t\t\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Length ?\r\n\t\t\t\t\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Capacity :\r\n\t\t\t\t\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Length);\r\n\t\t\t\tstatus = RiffaStartDmaTransaction(DevExt, RIFFA_MAX_NUM_CHNLS + io->Chnl,\r\n\t\t\t\t\tlength + DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Offset,\r\n\t\t\t\t\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Offset,\r\n\t\t\t\t\tWdfDmaDirectionReadFromDevice);\r\n\t\t\t\tif (!NT_SUCCESS(status)) {\r\n\t\t\t\t\tWdfRequestCompleteWithInformation(Request, status, 0);\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse {\r\n\t\t\t\t// No room in user buffer, spill everything\r\n\t\t\t\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].SpillAfter = 0;\r\n\t\t\t\tRiffaProgramScatterGather(DevExt, RIFFA_MAX_NUM_CHNLS + io->Chnl);\r\n\t\t\t}\r\n\t\t}\r\n\t\telse if (DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Last) {\r\n\t\t\t// Recognize zero length receive and complete\r\n\t\t\tWdfRequestCompleteWithInformation(Request, STATUS_SUCCESS, 0);\r\n\t\t}\r\n\t\telse {\r\n\t\t\t// Invalid request, should never happen\r\n\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\"riffa: fpga:%s, ioctl recv invalid, no length or last\\n\", DevExt->Name);\r\n\t\t\tWdfRequestCompleteWithInformation(Request, STATUS_CANCELLED, 0);\r\n\t\t}\r\n\t}\r\n\telse {\r\n\t\t// Start the timer (if necessary)\r\n\t\tif (DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Timeout > 0)\r\n\t\t\tWdfTimerStart(DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Timer,\r\n\t\t\t\tWDF_REL_TIMEOUT_IN_MS(DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + io->Chnl].Timeout));\r\n\t}\r\n\r\n\t// Mark the WDFREQUEST as cancellable.\r\n\tstatus = WdfRequestMarkCancelableEx(Request, RiffaEvtRequestCancel);\r\n\tif (!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl send WdfRequestMarkCancelableEx failed\\n\", DevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, status, 0);\r\n\t}\r\n}\r\n\r\n\r\n\r\n/**\r\n * Handles IRP_MJ_DEVICE_CONTROL requests for IOCTL_RIFFA_LIST.\r\n *\t.\r\n * DevExt - Handle to the device extension object.\r\n *\r\n * Request - Handle to a framework request object.\r\n *\r\n * OutputBufferLength - Length of the request's output buffer,\r\n * if an output buffer is available.\r\n *\r\n * InputBufferLength - Length of the request's input buffer,\r\n * if an input buffer is available.\r\n */\r\nVOID RiffaIoctlList(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,\r\n\tIN size_t OutputBufferLength, IN size_t InputBufferLength) {\r\n NTSTATUS status = STATUS_SUCCESS;\r\n PRIFFA_FPGA_INFO info;\r\n\tPCHAR buf = NULL;\r\n\tsize_t bufSize;\r\n\tUINT32 i;\r\n\r\n\t// Input should be non-zero\r\n\tif(!InputBufferLength) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl list zero length input buffer\\n\", DevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\r\n\t// Get the input buffer\r\n\tstatus = WdfRequestRetrieveInputBuffer(Request, 0, &buf, &bufSize);\r\n\tif (!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl list WdfRequestRetrieveInputBuffer failed\\n\",\r\n\t\t\tDevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, status, 0);\r\n\t\treturn;\r\n\t}\r\n\tif (bufSize < sizeof(UINT32)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl list input buffer too small to contain fpga id\\n\",\r\n\t\t\tDevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\ti = *((UINT32 *)buf);\r\n\r\n\t// Validate the index value\r\n\tif (i >= RIFFA_MAX_NUM_FPGAS) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl list fpga id invalid\\n\", DevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\r\n\t// Output should be non-zero\r\n\tif(!OutputBufferLength) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl list zero length output buffer\\n\", DevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\r\n\t// Get the output buffer\r\n\tstatus = WdfRequestRetrieveOutputBuffer(Request, 0, &buf, &bufSize);\r\n\tif (!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl list WdfRequestRetrieveOutputBuffer failed\\n\",\r\n\t\t\tDevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, status, 0);\r\n\t\treturn;\r\n\t}\r\n\tif (bufSize < sizeof(RIFFA_FPGA_INFO)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s, ioctl list input buffer too small to contain RIFFA_FPGA_INFO\\n\",\r\n\t\t\tDevExt->Name);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_INVALID_PARAMETER, 0);\r\n\t\treturn;\r\n\t}\r\n\tinfo = (PRIFFA_FPGA_INFO)buf;\r\n\r\n\t// Fill in the information.\r\n\tinfo->id[i] = i;\r\n\tinfo->num_chnls[i] = DevExt->NumChnls;\r\n\tstrcpy_s(info->name[i], 16, DevExt->Name);\r\n\tinfo->vendor_id[i] = DevExt->VendorId;\r\n\tinfo->device_id[i] = DevExt->DeviceId;\r\n\tWdfRequestCompleteWithInformation(Request, status, 0);\r\n}\r\n\r\n\r\n\r\n/**\r\n * Handles IRP_MJ_DEVICE_CONTROL requests for IOCTL_RIFFA_RESET.\r\n *\t.\r\n * DevExt - Handle to the device extension object.\r\n *\r\n * Request - Handle to a framework request object.\r\n *\r\n * OutputBufferLength - Length of the request's output buffer,\r\n * if an output buffer is available.\r\n *\r\n * InputBufferLength - Length of the request's input buffer,\r\n * if an input buffer is available.\r\n */\r\nVOID RiffaIoctlReset(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request) {\r\n\tUINT32 i;\r\n\r\n\t// Reset the device by reading the info/status register\r\n\tREAD_REGISTER_ULONG(DevExt->Bar0 + RIFFA_INFO_REG);\r\n\r\n\t// Reset all the channels\r\n\tfor (i = 0; i < DevExt->NumChnls; i++) {\r\n\t\tInterlockedExchange(&DevExt->Chnl[i].Ready, 0);\r\n\t\tInterlockedExchange(&DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].Ready, 0);\r\n\t\tInterlockedExchange(&DevExt->Chnl[i].InUse, 0);\r\n\t\tInterlockedExchange(&DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].InUse, 0);\r\n\t\tInterlockedExchange(&DevExt->Chnl[i].ReqdDone, 0);\r\n\t\tInterlockedExchange(&DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].ReqdDone, 0);\r\n\t\tDevExt->Chnl[i].ActiveCount = 0;\r\n\t\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].ActiveCount = 0;\r\n\t\tDevExt->Chnl[i].Cancel = 0;\r\n\t\tDevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].Cancel = 0;\r\n\t\tWdfDmaTransactionRelease(DevExt->Chnl[i].DmaTransaction);\r\n\t\tWdfDmaTransactionRelease(DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].DmaTransaction);\r\n\t\tRiffaCompleteRequest(DevExt, i, STATUS_CANCELLED);\r\n\t\tRiffaCompleteRequest(DevExt, RIFFA_MAX_NUM_CHNLS + i, STATUS_CANCELLED);\r\n\t\tWdfTimerStop(DevExt->Chnl[i].Timer, FALSE);\r\n\t\tWdfTimerStop(DevExt->Chnl[RIFFA_MAX_NUM_CHNLS + i].Timer, FALSE);\r\n\t}\r\n\r\n\t// Reset the interrupt data\r\n\tmemset(DevExt->IntrData, 0, 2 * RIFFA_MAX_NUM_CHNLS * sizeof(INTR_CHNL_DIR_DATA));\r\n\r\n\t// Finish this request\r\n\tWdfRequestCompleteWithInformation(Request, STATUS_SUCCESS, 0);\r\n}\r\n\r\n\r\n\r\n/******************************************************************************\r\n * DMA ENTRY, EXIT, TIMER FUNCTIONS\r\n *****************************************************************************/\r\n\r\n/**\r\n * Called at the entry point of functions after the DMA has started. If the\r\n * WDFREQUEST is still valid, increments the active count and returns TRUE. IF\r\n * the WDFREQUEST is not valid (i.e. is NULL'd out), then the request has been\r\n * cancelled (by timeout timer or by user process termination), and FALSE is\r\n * returned (active count is not incremented).\r\n *\r\n * DevExt - Pointer to the Device Extension\r\n *\r\n * Chnl - Channel number on which the DMA is taking place\r\n */\r\nBOOLEAN RiffaThreadEnter(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl) {\r\n\tBOOLEAN cont;\r\n\r\n\t// Acquire the channel lock, check if request is null, increment, release.\r\n\tWdfSpinLockAcquire(DevExt->Chnl[Chnl].SpinLock);\r\n\tcont = (DevExt->Chnl[Chnl].Request != NULL);\r\n\tif (cont)\r\n\t\tDevExt->Chnl[Chnl].ActiveCount++;\r\n\tWdfSpinLockRelease(DevExt->Chnl[Chnl].SpinLock);\r\n\r\n\treturn cont;\r\n}\r\n\r\n\r\n\r\n/**\r\n * Called at the exit of functions where RiffaThreadEnter was called, after the\r\n * DMA has started. Decrements the active count. If this is the last thread, it\r\n * checks to see if a cancel request was set. If so, cancels the request (if\r\n * not already completed).\r\n *\r\n * DevExt - Pointer to the Device Extension\r\n *\r\n * Chnl - Channel number on which the DMA is taking place\r\n *\r\n * IsSend - TRUE if the thread is operating on a send DMA, FALSE otherwise\r\n */\r\nVOID RiffaThreadExit(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl) {\r\n\r\n\t// Acquire the channel lock, decrement, check for last exiting thread and a\r\n\t// cancel request, cancel if necessary, release.\r\n\tWdfSpinLockAcquire(DevExt->Chnl[Chnl].SpinLock);\r\n\tDevExt->Chnl[Chnl].ActiveCount--;\r\n\tif (DevExt->Chnl[Chnl].ActiveCount == 0 && DevExt->Chnl[Chnl].Cancel == 1)\r\n\t\tRiffaCompleteRequest(DevExt, Chnl, STATUS_CANCELLED);\r\n\tWdfSpinLockRelease(DevExt->Chnl[Chnl].SpinLock);\r\n}\r\n\r\n\r\n\r\n/**\r\n * Called when the WDFREQUEST object for the specified channel should be\r\n * completed with the specified status. The WDFREQUEST has been marked\r\n * cancelable so it must first be unmarked cancelable. After completion, the\r\n * pointer to the WDFREQUEST is NULL'd out to indicate that the WDFREQUEST is\r\n * no longer valid.\r\n *\r\n * DevExt - Pointer to the Device Extension\r\n *\r\n * Chnl - Channel number on which the DMA is taking place\r\n *\r\n * Status - NTSTATUS to set for completion\r\n */\r\nVOID RiffaCompleteRequest(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,\r\n\tIN NTSTATUS Status) {\r\n\tNTSTATUS status;\r\n\tWDFREQUEST request;\r\n\r\n\tif ((request = DevExt->Chnl[Chnl].Request) != NULL) {\r\n\t\t// Try to complete the request\r\n\t\tstatus = WdfRequestUnmarkCancelable(request);\r\n\t\tif (status != STATUS_CANCELLED) {\r\n\t\t\t// Complete the request (nobody has done it yet)\r\n\t\t\tDevExt->Chnl[Chnl].Request = NULL;\r\n\t\t\tWdfRequestCompleteWithInformation(request, Status,\r\n\t\t\t\t(ULONG_PTR)(DevExt->Chnl[Chnl].ConfirmedPrev +\r\n\t\t\t\tDevExt->Chnl[Chnl].Confirmed)>>2);\r\n\t\t}\r\n\t}\r\n}\r\n\r\n\r\n\r\n/**\r\n * EvtRequestCancel handler for WDFREQUEST objects for IOCTL sends/receives.\r\n * Called if the IO Manager or calling application needs to cancel the send.\r\n * In practice this should only happen when the user application hangs and the\r\n * user CTRL+C signals or Task Ends the application.\r\n *\r\n * Request - WDFREQUEST object from the IOCTL queue, representing the send\r\n */\r\nVOID RiffaEvtRequestCancel(IN WDFREQUEST Request) {\r\n\tPDEVICE_EXTENSION devExt;\r\n\tPREQUEST_EXTENSION reqExt;\r\n\tUINT32 chnl;\r\n\tBOOLEAN canCancel;\r\n\r\n devExt = RiffaGetDeviceContext(WdfIoQueueGetDevice(WdfRequestGetIoQueue(Request)));\r\n reqExt = RiffaGetRequestContext(Request);\r\n\r\n\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\"riffa: fpga:%s chnl:%d, request being cancelled\\n\", devExt->Name,\r\n\t\t(reqExt->Chnl >= RIFFA_MAX_NUM_CHNLS ? reqExt->Chnl - RIFFA_MAX_NUM_CHNLS : reqExt->Chnl)));\r\n\r\n\t// Acquire the channel lock\r\n\tWdfSpinLockAcquire(devExt->Chnl[reqExt->Chnl].SpinLock);\r\n\r\n\t// See if we can cancel right now.\r\n\tcanCancel = (devExt->Chnl[reqExt->Chnl].ActiveCount == 0);\r\n\tif (canCancel) {\r\n\t\t// NULL out the request so that no other threads use it\r\n\t\tdevExt->Chnl[reqExt->Chnl].Request = NULL;\r\n\t}\r\n\telse {\r\n\t\t// Set the cancel flag so that the last active thread cancels for us.\r\n\t\tdevExt->Chnl[reqExt->Chnl].Cancel = 1;\r\n\t}\r\n\r\n\t// Release the channel lock\r\n\tWdfSpinLockRelease(devExt->Chnl[reqExt->Chnl].SpinLock);\r\n\r\n\t// Cancel the request\r\n\tif (canCancel) {\r\n\t\tInterlockedExchange(&devExt->Chnl[reqExt->Chnl].Ready, 0);\r\n\t\tInterlockedExchange(&devExt->Chnl[reqExt->Chnl].InUse, 0);\r\n\t\tdevExt->Chnl[reqExt->Chnl].ActiveCount = 0;\r\n\t\tdevExt->Chnl[reqExt->Chnl].Cancel = 0;\r\n\t\tWdfDmaTransactionRelease(devExt->Chnl[reqExt->Chnl].DmaTransaction);\r\n\t\tWdfTimerStop(devExt->Chnl[reqExt->Chnl].Timer, FALSE);\r\n\t\tWdfRequestCompleteWithInformation(Request, STATUS_CANCELLED,\r\n\t\t\t(ULONG_PTR)(devExt->Chnl[reqExt->Chnl].ConfirmedPrev +\r\n\t\t\tdevExt->Chnl[reqExt->Chnl].Confirmed)>>2);\r\n\t}\r\n}\r\n\r\n\r\n\r\n/**\r\n * Called when the WDFTIMER expires. Used to handle timeouts from IOCTL calls.\r\n *\r\n * Timer - WDFTIMER that expired\r\n */\r\nVOID RiffaEvtTimerFunc(IN WDFTIMER Timer) {\r\n\tPDEVICE_EXTENSION devExt;\r\n\tPTIMER_EXTENSION timerExt;\r\n\tWDFREQUEST request;\r\n\tNTSTATUS status;\r\n\tBOOLEAN canCancel;\r\n\r\n timerExt = RiffaGetTimerContext(Timer);\r\n devExt = RiffaGetDeviceContext(WdfIoQueueGetDevice(WdfTimerGetParentObject(Timer)));\r\n\r\n\t// Acquire the channel lock\r\n\tWdfSpinLockAcquire(devExt->Chnl[timerExt->Chnl].SpinLock);\r\n\r\n\t// See if we can cancel right now.\r\n\trequest = devExt->Chnl[timerExt->Chnl].Request;\r\n\tif (request == NULL) {\r\n\t\tcanCancel = FALSE;\r\n\t}\r\n\telse {\r\n\t\tcanCancel = (devExt->Chnl[timerExt->Chnl].ActiveCount == 0);\r\n\t\tif (canCancel) {\r\n\t\t\t// NULL out the request so that no other threads use it\r\n\t\t\tdevExt->Chnl[timerExt->Chnl].Request = NULL;\r\n\t\t}\r\n\t\telse {\r\n\t\t\t// Set the cancel flag so that the last active thread cancels for us.\r\n\t\t\tdevExt->Chnl[timerExt->Chnl].Cancel = 1;\r\n\t\t}\r\n\t}\r\n\r\n\t// Release the channel lock\r\n\tWdfSpinLockRelease(devExt->Chnl[timerExt->Chnl].SpinLock);\r\n\r\n\t// Cancel the request\r\n\tif (canCancel) {\r\n\t\tif (timerExt->Chnl < RIFFA_MAX_NUM_CHNLS) {\r\n\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\"riffa: fpga:%s chnl:%d, send timed out\\n\", devExt->Name, timerExt->Chnl);\r\n\t\t}\r\n\t\telse {\r\n\t\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\t\"riffa: fpga:%s chnl:%d, recv timed out\\n\", devExt->Name,\r\n\t\t\t\ttimerExt->Chnl - RIFFA_MAX_NUM_CHNLS);\r\n\t\t}\r\n\t\tstatus = WdfRequestUnmarkCancelable(request);\r\n\t\tif (status != STATUS_CANCELLED) {\r\n\t\t\t// Complete the request (nobody has done it yet)\r\n\t\t\tInterlockedExchange(&devExt->Chnl[timerExt->Chnl].Ready, 0);\r\n\t\t\tInterlockedExchange(&devExt->Chnl[timerExt->Chnl].InUse, 0);\r\n\t\t\tdevExt->Chnl[timerExt->Chnl].ActiveCount = 0;\r\n\t\t\tdevExt->Chnl[timerExt->Chnl].Cancel = 0;\r\n\t\t\tWdfDmaTransactionRelease(devExt->Chnl[timerExt->Chnl].DmaTransaction);\r\n\t\t\tWdfTimerStop(devExt->Chnl[timerExt->Chnl].Timer, FALSE);\r\n\t\t\tWdfRequestCompleteWithInformation(request, STATUS_CANCELLED,\r\n\t\t\t\t(ULONG_PTR)(devExt->Chnl[timerExt->Chnl].ConfirmedPrev +\r\n\t\t\t\tdevExt->Chnl[timerExt->Chnl].Confirmed)>>2);\r\n\t\t}\r\n\t}\r\n}\r\n\r\n\r\n/******************************************************************************\r\n * DMA CALLBACKS\r\n *****************************************************************************/\r\n\r\n/**\r\n * Called after the user has called into the driver to receive data, from the\r\n * interrupt DPC when it detects a data receive event. Both conditions must be\r\n * met before this function will be called. The function initiates a receive\r\n * DMA operation then provides scatter gather information if necessary.\r\n *\r\n * DevExt - Pointer to the Device Extension\r\n *\r\n * Chnl - Channel number on which the DMA is taking place\r\n */\r\nVOID RiffaStartRecvTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl) {\r\n\tNTSTATUS status;\r\n\tUINT64 length;\r\n\r\n\t// Stop the timer (if set)\r\n\tWdfTimerStop(DevExt->Chnl[Chnl].Timer, FALSE);\r\n\r\n\t// Check that the request has not been cancelled.\r\n\tif (!RiffaThreadEnter(DevExt, Chnl))\r\n\t\treturn;\r\n\r\n\t// Start a recv transaction.\r\n\tif (DevExt->Chnl[Chnl].Length) {\r\n\t\t// Calculate room in the user space buffer and what needs to be spilled\r\n\t\tif (DevExt->Chnl[Chnl].Capacity > DevExt->Chnl[Chnl].Offset) {\r\n\t\t\t// Some (possibly all) of the data can fit in the user buffer.\r\n\t\t\tDevExt->Chnl[Chnl].SpillAfter =\r\n\t\t\t\tDevExt->Chnl[Chnl].Capacity - DevExt->Chnl[Chnl].Offset;\r\n\t\t\tlength = (DevExt->Chnl[Chnl].Capacity < DevExt->Chnl[Chnl].Length ?\r\n\t\t\t\tDevExt->Chnl[Chnl].Capacity : DevExt->Chnl[Chnl].Length);\r\n\t\t\tstatus = RiffaStartDmaTransaction(DevExt, Chnl,\r\n\t\t\t\tlength + DevExt->Chnl[Chnl].Offset, DevExt->Chnl[Chnl].Offset,\r\n\t\t\t\tWdfDmaDirectionReadFromDevice);\r\n\t\t\tif (!NT_SUCCESS(status)) {\r\n\t\t\t\tRiffaCompleteRequest(DevExt, Chnl, status);\r\n\t\t\t}\r\n\t\t}\r\n\t\telse {\r\n\t\t\t// No room in user buffer, spill everything\r\n\t\t\tDevExt->Chnl[Chnl].SpillAfter = 0;\r\n\t\t\tRiffaProgramScatterGather(DevExt, Chnl);\r\n\t\t}\r\n\t}\r\n\telse if (DevExt->Chnl[Chnl].Last) {\r\n\t\t// Recognize zero length receive and complete\r\n\t\tRiffaCompleteRequest(DevExt, Chnl, STATUS_SUCCESS);\r\n\t}\r\n\telse {\r\n\t\t// Invalid request, should never happen\r\n\t\tRiffaCompleteRequest(DevExt, Chnl, STATUS_CANCELLED);\r\n\t}\r\n\r\n\t// Check for a cancel request and service it.\r\n\tRiffaThreadExit(DevExt, Chnl);\r\n}\r\n\r\n\r\n/**\r\n * Starts a DMA transaction using the user pages specified in the IOCTL output\r\n * buffer as the source/receptical. This will result in RiffaEvtProgramDma\r\n * being called with the scatter gather list. If the amount of data to map is\r\n * too large, Windows will break up the transaction into multiple transfers.\r\n * Only a portion of the output buffer will be mapped each transfer (each call\r\n * to RiffaEvtProgramDma). Returns the status after starting the DMA transaction.\r\n *\r\n * Request - Pointer to the WDFREQUEST that was passed to IOCTl\r\n *\r\n * DevExt - Pointer to the Device Extension\r\n *\r\n * Chnl - Channel number on which the DMA transaction should take place\r\n *\r\n * Length - Length (in bytes) of the DMA\r\n *\r\n * Offset - Offset (in bytes) from the start of the IOCTL output buffer where\r\n * data should be read/written\r\n *\r\n * DmaDirection - Direction of the DMA\r\n *\r\n * Returns status after starting the DMA transaction.\r\n */\r\nNTSTATUS RiffaStartDmaTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,\r\n\tIN UINT64 Length, IN UINT64 Offset, IN WDF_DMA_DIRECTION DmaDirection) {\r\n\tNTSTATUS status = STATUS_SUCCESS;\r\n PMDL mdl;\r\n PVOID vaddr;\r\n UINT64 length;\r\n\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\"riffa: fpga:%s chnl:%d, starting txn (len:%lld, off:%lld, isSend?:%d)\\n\",\r\n\t\tDevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS),\r\n\t\tLength>>2, Offset, DmaDirection == WdfDmaDirectionWriteToDevice);\r\n\r\n\t// Get the user space memory.\r\n\tstatus = WdfRequestRetrieveOutputWdmMdl(DevExt->Chnl[Chnl].Request, &mdl);\r\n\tif (!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s chnl:%d, WdfRequestRetrieveOutputWdmMdl failed\\n\",\r\n\t\t\tDevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS));\r\n\t\treturn status;\r\n\t}\r\n\t// Move the virtual address forward to the offset\r\n\tvaddr = MmGetMdlVirtualAddress(mdl);\r\n\tvaddr = ((UINT32 *)vaddr) + Offset;\r\n\r\n\t// Reduce the length by the offset amount\r\n\tlength = MmGetMdlByteCount(mdl);\r\n\tlength = (Length < length ? Length : length);\r\n\tlength = length - Offset;\r\n\r\n\t// Reuse the DMA Transaction\r\n\tstatus = WdfDmaTransactionInitialize(DevExt->Chnl[Chnl].DmaTransaction,\r\n\t\tRiffaEvtProgramDma, DmaDirection, mdl, vaddr, (size_t)length);\r\n\tif(!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s chnl:%d, WdfDmaTransactionInitialize failed\\n\",\r\n\t\t\tDevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS));\r\n\t\treturn status;\r\n\t}\r\n\r\n\t// Execute the transaction\r\n\tstatus = WdfDmaTransactionExecute(DevExt->Chnl[Chnl].DmaTransaction,\r\n\t\t(WDFCONTEXT)Chnl);\r\n\tif (!NT_SUCCESS(status)) {\r\n\t\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\t\"riffa: fpga:%s chnl:%d, WdfDmaTransactionExecute failed\\n\",\r\n\t\t\tDevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS));\r\n\t\tWdfDmaTransactionRelease(DevExt->Chnl[Chnl].DmaTransaction);\r\n\t\treturn status;\r\n\t}\r\n\r\n\treturn status;\r\n}\r\n\r\n\r\n\r\n/**\r\n * Programs the device with scatter gather data. Will program the device with\r\n * spill buffer data (as scatter gather buffers) if the DMA length will overrun\r\n * the receptical user buffer.\r\n *\r\n * DevExt - Pointer to the Device Extension\r\n *\r\n * Chnl - Channel number on which the DMA transaction takes place\r\n *\r\n * IsSend - TRUE if the direction is a \"send\", FALSE otherwise\r\n */\r\nVOID RiffaProgramScatterGather(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl) {\r\n\tPSCATTER_GATHER_LIST sgList;\r\n\tPULONG bufBase;\r\n\tPHYSICAL_ADDRESS bufAddr;\r\n UINT32 pos;\r\n UINT32 i;\r\n UINT64 provided;\r\n UINT64 length;\r\n UINT64 spillAfter;\r\n\r\n\t// Stop the timer (if set)\r\n\tWdfTimerStop(DevExt->Chnl[Chnl].Timer, FALSE);\r\n\r\n\t// Check that the request has not been cancelled.\r\n\tif (!RiffaThreadEnter(DevExt, Chnl))\r\n\t\treturn;\r\n\r\n\t// OK, then get the variables.\r\n\tsgList = DevExt->Chnl[Chnl].SgList;\r\n\tbufBase = DevExt->Chnl[Chnl].CommonBufferBase;\r\n\tbufAddr = DevExt->Chnl[Chnl].CommonBufferBaseLA;\r\n\tpos = DevExt->Chnl[Chnl].SgPos;\r\n\tprovided = DevExt->Chnl[Chnl].Provided;\r\n\tlength = DevExt->Chnl[Chnl].Length;\r\n\tspillAfter = DevExt->Chnl[Chnl].SpillAfter;\r\n\r\n // Translate the System's SCATTER_GATHER_LIST elements\r\n // into the device's scatter gather elements.\r\n\tfor (i = 0; i < DevExt->MaxNumScatterGatherElems && provided < spillAfter; i++, pos++) {\r\n\t\tif (pos >= sgList->NumberOfElements)\r\n\t\t\tbreak;\r\n\t\tWRITE_REGISTER_ULONG(bufBase + (i*4) + 0, sgList->Elements[pos].Address.LowPart);\r\n\t\tWRITE_REGISTER_ULONG(bufBase + (i*4) + 1, sgList->Elements[pos].Address.HighPart);\r\n\t\tWRITE_REGISTER_ULONG(bufBase + (i*4) + 2, (sgList->Elements[pos].Length>>2)); // Words!\r\n\t\tprovided += sgList->Elements[pos].Length;\r\n\t}\r\n\r\n\t// Handle any spillage\r\n\tif (provided >= spillAfter) {\r\n\t\tfor (; i < DevExt->MaxNumScatterGatherElems && provided < length; i++) {\r\n\t\t\tWRITE_REGISTER_ULONG(bufBase + (i*4) + 0, DevExt->SpillBufferBaseLA.LowPart);\r\n\t\t\tWRITE_REGISTER_ULONG(bufBase + (i*4) + 1, DevExt->SpillBufferBaseLA.HighPart);\r\n\t\t\tWRITE_REGISTER_ULONG(bufBase + (i*4) + 2, (RIFFA_SPILL_BUF_SIZE>>2)); // Words!\r\n\t\t\tprovided += RIFFA_SPILL_BUF_SIZE;\r\n\t\t}\r\n\t}\r\n\r\n // Update the data structures\r\n DevExt->Chnl[Chnl].Confirmed += DevExt->Chnl[Chnl].ProvidedPrev;\r\n DevExt->Chnl[Chnl].ProvidedPrev = provided - DevExt->Chnl[Chnl].Provided;\r\n\tDevExt->Chnl[Chnl].Provided = provided;\r\n\tDevExt->Chnl[Chnl].SgPos = pos;\r\n\r\n\tif (i > 0) {\r\n\t\t// Let the device know about the new scatter gather data.\r\n\t\tif (Chnl < RIFFA_MAX_NUM_CHNLS) {\r\n\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\"riffa: fpga:%s chnl:%d, sg buf for send txn: %d elements\\n\",\r\n\t\t\t\tDevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS), i));\r\n\t\t\tWRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl, RIFFA_RX_SG_ADDR_LO_REG), bufAddr.LowPart);\r\n\t\t\tWRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl, RIFFA_RX_SG_ADDR_HI_REG), bufAddr.HighPart);\r\n\t\t\tWRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl, RIFFA_RX_SG_LEN_REG), (i*4*4)>>2); // Words!\r\n\t\t}\r\n\t\telse {\r\n\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\"riffa: fpga:%s chnl:%d, sg buf for recv txn: %d elements\\n\",\r\n\t\t\t\tDevExt->Name, (Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS), i));\r\n\t\t\tWRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl - RIFFA_MAX_NUM_CHNLS, RIFFA_TX_SG_ADDR_LO_REG), bufAddr.LowPart);\r\n\t\t\tWRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl - RIFFA_MAX_NUM_CHNLS, RIFFA_TX_SG_ADDR_HI_REG), bufAddr.HighPart);\r\n\t\t\tWRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl - RIFFA_MAX_NUM_CHNLS, RIFFA_TX_SG_LEN_REG), (i*4*4)>>2); // Words!\r\n\t\t}\r\n\t}\r\n\telse if (provided < length) {\r\n\t\t// Let the device know that no more scatter gather data will be provided\r\n\t\t// until a \"transfer done\" signal is received. This is initiated differently\r\n\t\t// for a send vs. a receive transaction.\r\n\t\tInterlockedExchange(&DevExt->Chnl[Chnl].ReqdDone, 1);\r\n\t\tif (Chnl < RIFFA_MAX_NUM_CHNLS) {\r\n\t\t\t// Write the length to signal request for \"done\" signal after all the\r\n\t\t\t// scatter gather regions have been used.\r\n\t\t WRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl, RIFFA_RX_LEN_REG),\r\n\t\t \t(ULONG)(provided>>2));\r\n\t\t}\r\n\t\telse {\r\n\t\t\t// Read the length to signal request for \"done\" signal after all the\r\n\t\t\t// scatter gather regions have been used.\r\n\t\t\tREAD_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(Chnl - RIFFA_MAX_NUM_CHNLS, RIFFA_TX_LEN_REG));\r\n\t\t}\r\n\t\tif (Chnl < RIFFA_MAX_NUM_CHNLS) {\r\n\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\"riffa: fpga:%s chnl:%d, splitting send txn\\n\", DevExt->Name, Chnl));\r\n\t\t}\r\n\t\telse {\r\n\t\t\tKdPrintEx((DPFLTR_IHVDRIVER_ID, DPFLTR_TRACE_LEVEL,\r\n\t\t\t\t\"riffa: fpga:%s chnl:%d, splitting recv txn\\n\", DevExt->Name, Chnl - RIFFA_MAX_NUM_CHNLS));\r\n\t\t}\r\n\t}\r\n\r\n\t// Check for a cancel request and service it.\r\n\tRiffaThreadExit(DevExt, Chnl);\r\n\r\n\t// Start the timer (if necessary)\r\n\tif (DevExt->Chnl[Chnl].Timeout > 0)\r\n\t\tWdfTimerStart(DevExt->Chnl[Chnl].Timer, WDF_REL_TIMEOUT_IN_MS(DevExt->Chnl[Chnl].Timeout));\r\n}\r\n\r\n\r\n\r\n/**\r\n * Called after the last DMA transfer for the DMA transaction is completed.\r\n * Sets the transferred bytes and completes the IOCTL call.\r\n *\r\n * DevExt - Pointer to the Device Extension\r\n *\r\n * Chnl - Channel number on which the DMA transaction takes place\r\n *\r\n * Transferred - Words transferred according to the hardware\r\n *\r\n * Status - Status after the last transfer has completed.\r\n */\r\nVOID RiffaTransactionComplete(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,\r\n\tIN UINT32 Transferred, IN NTSTATUS Status) {\r\n\r\n\t// Stop the timer (if set)\r\n\tWdfTimerStop(DevExt->Chnl[Chnl].Timer, FALSE);\r\n\r\n\t// Check that the request has not been cancelled.\r\n\tif (!RiffaThreadEnter(DevExt, Chnl))\r\n\t\treturn;\r\n\r\n\t// Release the DMA Transaction\r\n\tWdfDmaTransactionRelease(DevExt->Chnl[Chnl].DmaTransaction);\r\n\tDbgPrintEx(DPFLTR_IHVDRIVER_ID, DPFLTR_ERROR_LEVEL,\r\n\t\t\"riffa: fpga:%s chnl:%d, words transferred: %lu\\n\", DevExt->Name,\r\n\t\t(Chnl < RIFFA_MAX_NUM_CHNLS ? Chnl : Chnl - RIFFA_MAX_NUM_CHNLS), Transferred);\r\n\r\n\tif (Chnl < RIFFA_MAX_NUM_CHNLS) {\r\n\t\t// Update the total confirmed data\r\n\t\tDevExt->Chnl[Chnl].Confirmed = (((UINT64)Transferred)<<2);\r\n\r\n\t\t// Complete the send request\r\n\t\tInterlockedExchange(&DevExt->Chnl[Chnl].InUse, 0);\r\n\t\tRiffaCompleteRequest(DevExt, Chnl, Status);\r\n\t}\r\n\telse {\r\n\t\t// Complete or repeat\r\n\t\tif (DevExt->Chnl[Chnl].Last || !NT_SUCCESS(Status)) {\r\n\t\t\t// Update the total confirmed data\r\n\t\t\tDevExt->Chnl[Chnl].Confirmed = (((UINT64)Transferred)<<2);\r\n\r\n\t\t\t// Complete the receive request\r\n\t\t\tInterlockedExchange(&DevExt->Chnl[Chnl].InUse, 0);\r\n\t\t\tRiffaCompleteRequest(DevExt, Chnl, Status);\r\n\t\t}\r\n\t\telse {\r\n\t\t\t// Not the \"last\" transaction. Save the transferred amount.\r\n\t\t\tDevExt->Chnl[Chnl].ConfirmedPrev += (((UINT64)Transferred)<<2);\r\n\t\t\tDevExt->Chnl[Chnl].Confirmed = 0;\r\n\t\t\tDevExt->Chnl[Chnl].ProvidedPrev = 0;\r\n\t\t\tDevExt->Chnl[Chnl].Provided = 0;\r\n\r\n\t\t\t// Stay in the kernel and start another receive DMA transaction.\r\n\t\t\t// If an interrupt with transaction info has already been received,\r\n\t\t\t// start the transaction. If not, set the \"ready\" bit.\r\n\t\t\tif (InterlockedExchange(&DevExt->Chnl[Chnl].Ready, 1)) {\r\n\t\t\t\t// Clear the \"ready\" bit and start the transaction\r\n\t\t\t\tInterlockedExchange(&DevExt->Chnl[Chnl].Ready, 0);\r\n\t\t\t\tRiffaStartRecvTransaction(DevExt, Chnl);\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\r\n\t// Check for a cancel request and service it.\r\n\tRiffaThreadExit(DevExt, Chnl);\r\n}\r\n\r\n\r\n\r\n/**\r\n * Programs the device for DMA send transactions. Note, that there is no way to\r\n * program the device for receive transactions. Receive transactions can only\r\n * be initiated from the device.\r\n *\r\n * DevExt - Pointer to the Device Extension\r\n *\r\n * Chnl - Channel number on which the DMA transaction takes place\r\n *\r\n * Length - Length (in words) of the DMA\r\n *\r\n * Offset - Offset (in words) to send to the device\r\n *\r\n * Last - 1 if this is the last transaction for the device, 0 otherwise\r\n */\r\nVOID RiffaProgramSend(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl, IN UINT32 Length,\r\n\tIN UINT32 Offset, IN UINT32 Last) {\r\n UINT32 offlast;\r\n UINT32 chnl;\r\n\r\n // Let the device know about the new transfer.\r\n offlast = ((Offset<<1) | (Last & 0x1));\r\n chnl = (Chnl >= RIFFA_MAX_NUM_CHNLS ? Chnl - RIFFA_MAX_NUM_CHNLS : Chnl);\r\n WRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(chnl, RIFFA_RX_OFFLAST_REG), offlast);\r\n WRITE_REGISTER_ULONG(DevExt->Bar0 + CHNL_REG(chnl, RIFFA_RX_LEN_REG), Length);\r\n}\r\n\r\n\r\n\r\n/**\r\n * The framework calls a driver's EvtProgramDma event callback function\r\n * when the driver calls WdfDmaTransactionExecute and the system has\r\n * enough map registers to do the transfer. The callback function must\r\n * program the hardware to start the transfer. A single transaction\r\n * initiated by calling WdfDmaTransactionExecute may result in multiple\r\n * calls to this function if the buffer is too large and there aren't\r\n * enough map registers to do the whole transfer.\r\n *\r\n * Transaction - DMA transactions initialized and started in RiffaStartDmaTransaction\r\n *\r\n * Device - A handle to the WDFDEVICE\r\n *\r\n * Context - Value passed as the context parameter to WdfDmaTransactionExecute\r\n *\r\n * Direction - DMA direction of the transfer\r\n *\r\n * SgList - Scatter gather list of the mapped memory to use for transferring\r\n *\r\n * Returns TRUE\r\n */\r\nBOOLEAN RiffaEvtProgramDma(IN WDFDMATRANSACTION Transaction, IN WDFDEVICE Device,\r\n\tIN PVOID Context, IN WDF_DMA_DIRECTION Direction, IN PSCATTER_GATHER_LIST SgList) {\r\n PDEVICE_EXTENSION devExt;\r\n\tUINT32 chnl;\r\n\r\n // Initialize variables and structures\r\n devExt = RiffaGetDeviceContext(Device);\r\n\tchnl = (UINT32)Context;\r\n\r\n\t// Save the scatter gather list\r\n\tdevExt->Chnl[chnl].SgList = SgList;\r\n\tdevExt->Chnl[chnl].SgPos = 0;\r\n\r\n\tif (Direction == WdfDmaDirectionWriteToDevice &&\r\n\t\tWdfDmaTransactionGetBytesTransferred(Transaction) == 0) {\r\n\t\t// Program the start of a new transfer.\r\n\t\tRiffaProgramSend(devExt, chnl, (UINT32)(devExt->Chnl[chnl].Length>>2),\r\n\t\t\t(UINT32)(devExt->Chnl[chnl].Offset>>2), devExt->Chnl[chnl].Last);\r\n\t}\r\n\r\n\t// Write the initial scatter gather data and notify the device.\r\n\tRiffaProgramScatterGather(devExt, chnl);\r\n\r\n return TRUE;\r\n}\r\n\r\n" }, { "path": "sw/riffa_2.1/driver/windows/sys/riffa.inx", "content": "\r\n[Version]\r\nSignature=\"$WINDOWS NT$\"\r\nClass=FPGA\r\nClassGuid={78A1C341-4539-11d3-B88D-00C04FAD5171}\r\nProvider=%UCSD%\r\nDriverVer=03/20/2003,6.00.3790\r\nCatalogFile=riffa.cat\r\n\r\n[DestinationDirs]\r\nDefaultDestDir = 12\r\n\r\n; ================= Class section =====================\r\n\r\n[ClassInstall32]\r\nAddreg=FPGAClassReg \r\n\r\n[FPGAClassReg]\r\nHKR,,,0,%ClassName%\r\nHKR,,Icon,,-5\r\nHKR,,DeviceCharacteristics,0x10001,0x100 ;Use same security checks on relative opens\r\nHKR,,Security,,\"D:P(A;;GA;;;WD)\" ;Allow generic all access to all. \r\n;HKR,,Security,,\"D:P(A;;GA;;;SY)(A;;GA;;;BA)\" ;Allow generic all access to system and built-in Admin. \r\n\r\n; ================= Device Install section =====================\r\n\r\n[ControlFlags]\r\nExcludeFromSelect=*\r\n\r\n[Manufacturer]\r\n%UCSD%=UCSD,NT$ARCH$\r\n\r\n[SourceDisksFiles]\r\nriffa.sys=1\r\n\r\n[SourceDisksNames]\r\n1=%DISK_NAME%,\r\n\r\n; For Win2K\r\n[UCSD]\r\n; DisplayName Section DeviceId CompatibleId\r\n; ----------- ------- -------- ------------\r\n%RIFFA.XILINXDESC%%RIFFA.DEBUG%= RIFFA_Inst, PCI\\VEN_10EE, PCI\\VEN_10EE\r\n%RIFFA.ALTERADESC%%RIFFA.DEBUG%= RIFFA_Inst, PCI\\VEN_1172, PCI\\VEN_1172\r\n\r\n; For XP and later\r\n[UCSD.NT$ARCH$]\r\n; DisplayName Section DeviceId CompatibleId\r\n; ----------- ------- -------- ------------\r\n%RIFFA.XILINXDESC%%RIFFA.DEBUG%= RIFFA_Inst, PCI\\VEN_10EE, PCI\\VEN_10EE\r\n%RIFFA.ALTERADESC%%RIFFA.DEBUG%= RIFFA_Inst, PCI\\VEN_1172, PCI\\VEN_1172\r\n\r\n[RIFFA_Inst.NT]\r\nCopyFiles=RIFFA.CopyFiles\r\n\r\n[RIFFA.CopyFiles]\r\nriffa.sys\r\n\r\n[RIFFA_Inst.NT.HW]\r\nAddReg=RIFFA.HwReg \r\n\r\n[RIFFA.HwReg]\r\nHKR,\"Interrupt Management\",,0x00000010\r\nHKR,\"Interrupt Management\\MessageSignaledInterruptProperties\",,0x00000010\r\nHKR,\"Interrupt Management\\MessageSignaledInterruptProperties\",MSISupported,0x00010001,1\r\n\r\n[RIFFA_Inst.NT.Services]\r\nAddService=RIFFA,0x00000002,RIFFA_Service \r\n\r\n[RIFFA_Service]\r\nDisplayName = %RIFFA.SVCDESC% \r\nServiceType = 1 ; SERVICE_KERNEL_DRIVER\r\nStartType = 3 ; SERVICE_DEMAND_START\r\nErrorControl = 1 ; SERVICE_ERROR_NORMAL\r\nServiceBinary = %12%\\riffa.sys \r\nAddReg = RIFFA_Parameters_AddReg\r\n\r\n;-------------- Coinstaller installation\r\n[DestinationDirs]\r\nCoInstaller_CopyFiles = 11\r\n\r\n[RIFFA_Inst.NT.CoInstallers]\r\nAddReg=CoInstaller_AddReg\r\nCopyFiles=CoInstaller_CopyFiles\r\n\r\n[CoInstaller_CopyFiles]\r\nWdfCoInstaller$KMDFCOINSTALLERVERSION$.dll\r\n\r\n[SourceDisksFiles]\r\nWdfCoInstaller$KMDFCOINSTALLERVERSION$.dll=1 ; make sure the number matches with SourceDisksNames\r\n\r\n[CoInstaller_AddReg]\r\nHKR,,CoInstallers32,0x00010000, \"WdfCoInstaller$KMDFCOINSTALLERVERSION$.dll,WdfCoInstaller\"\r\n\r\n[RIFFA_Inst.NT.Wdf]\r\nKmdfService = RIFFA, RIFFA_wdfsect\r\n\r\n[RIFFA_wdfsect]\r\nKmdfLibraryVersion = $KMDFVERSION$\r\n\r\n[Strings]\r\nUCSD = \"University of California, San Diego\"\r\nClassName = \"RIFFA Devices\"\r\nRIFFA.SVCDESC = \"Driver Service for RIFFA FPGAs\"\r\nRIFFA.XILINXDESC = \"Xilinx(R) FPGA\"\r\nRIFFA.ALTERADESC = \"Altera(R) FPGA\"\r\nDISK_NAME = \"RIFFA Install Disk\"\r\n\r\n" }, { "path": "sw/riffa_2.1/driver/windows/sys/riffa.rc", "content": "#include \r\n\r\n#include \r\n\r\n#define VER_FILETYPE VFT_DRV\r\n#define VER_FILESUBTYPE VFT2_DRV_SYSTEM\r\n#define VER_FILEDESCRIPTION_STR \"WDF Driver for RIFFA\"\r\n#define VER_INTERNALNAME_STR \"riffa.sys\"\r\n#define VER_ORIGINALFILENAME_STR \"riffa.sys\"\r\n\r\n#include \"common.ver\"\r\n\r\n\r\n\r\n\r\n" }, { "path": "sw/riffa_2.1/driver/windows/sys/riffa_driver.h", "content": "//\r\n// The following value is arbitrarily chosen from the space defined\r\n// by Microsoft as being \"for non-Microsoft use\"\r\n//\r\n//\r\n// {40d49fb9-6085-4e1d-8753-822be944d7bb}\r\nDEFINE_GUID (GUID_RIFFA_INTERFACE,\r\n 0x40d49fb9, 0x6085, 0x4e1d, 0x87, 0x53, 0x82, 0x2b, 0xe9, 0x44, 0xd7, 0xbb);\r\n\r\n// The IOCTL function codes from 0x800 to 0xFFF are for customer use.\r\n#define IOCTL_RIFFA_SEND \\\r\n CTL_CODE(FILE_DEVICE_UNKNOWN, 0x900, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)\r\n#define IOCTL_RIFFA_RECV \\\r\n CTL_CODE(FILE_DEVICE_UNKNOWN, 0x901, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)\r\n#define IOCTL_RIFFA_LIST \\\r\n CTL_CODE(FILE_DEVICE_UNKNOWN, 0x902, METHOD_OUT_DIRECT ,FILE_ANY_ACCESS)\r\n#define IOCTL_RIFFA_RESET \\\r\n CTL_CODE(FILE_DEVICE_UNKNOWN, 0x903, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)\r\n\r\n" }, { "path": "sw/riffa_2.1/driver/windows/sys/riffa_private.h", "content": "#if !defined(_RIFFA_H_)\r\n#define _RIFFA_H_\r\n\r\n// Adjusts register offsets for each channel\r\n#define CHNL_REG(c, o) (((c)<<4) + o)\r\n\r\n// Register offsets\r\n#define RIFFA_RX_SG_LEN_REG\t\t\t0x0\r\n#define RIFFA_RX_SG_ADDR_LO_REG\t\t0x1\r\n#define RIFFA_RX_SG_ADDR_HI_REG\t\t0x2\r\n#define RIFFA_RX_LEN_REG\t\t\t0x3\r\n#define RIFFA_RX_OFFLAST_REG\t\t0x4\r\n#define RIFFA_TX_SG_LEN_REG\t\t\t0x5\r\n#define RIFFA_TX_SG_ADDR_LO_REG\t\t0x6\r\n#define RIFFA_TX_SG_ADDR_HI_REG\t\t0x7\r\n#define RIFFA_TX_LEN_REG\t\t\t0x8\r\n#define RIFFA_TX_OFFLAST_REG\t\t0x9\r\n#define RIFFA_INFO_REG\t\t\t\t0xA\r\n#define RIFFA_IRQ_0_REG\t\t\t\t0xB\r\n#define RIFFA_IRQ_1_REG\t\t\t\t0xC\r\n#define RIFFA_RX_TNFR_LEN_REG\t\t0xD\r\n#define RIFFA_TX_TNFR_LEN_REG\t\t0xE\r\n\r\n// Size of common buffer for scatter gather elements\r\n#define RIFFA_MIN_SG_BUF_SIZE (4*1024)\r\n\r\n// Size of common buffer for receive data spill\r\n#define RIFFA_SPILL_BUF_SIZE (4*1024)\r\n\r\n// Maximum number of scatter gather elements for each transfer\r\n#define RIFFA_MIN_NUM_SG_ELEMS (200)\r\n\r\n// Maximum bus width (multiply by 32 to get bit width)\r\n#define RIFFA_MAX_BUS_WIDTH_PARAM (4)\r\n\r\n// Maximum DMA transfer size (in bytes).\r\n#define RIFFA_MAX_TNFR_LEN (0xFFFFFFFF)\r\n\r\n// Number of DMA channels supported\r\n#define RIFFA_MAX_NUM_CHNLS (12)\r\n\r\n// Maximum number of RIFFA FPGAs\r\n#define RIFFA_MAX_NUM_FPGAS (5)\r\n\r\n// The structure used to hold data transfer information\r\ntypedef struct RIFFA_FPGA_CHNL_IO {\r\n\tUINT32\t\t\t\t\tId;\r\n\tUINT32\t\t\t\t\tChnl;\r\n\tUINT32\t\t\t\t\tLength;\r\n\tUINT32\t\t\t\t\tOffset;\r\n\tUINT32\t\t\t\t\tLast;\r\n\tUINT64\t\t\t\t\tTimeout;\r\n} RIFFA_FPGA_CHNL_IO, * PRIFFA_FPGA_CHNL_IO;\r\n\r\n// The structure used to hold FPGA information\r\ntypedef struct RIFFA_FPGA_INFO {\r\n\tUINT32\t\t\t\t\tnum_fpgas;\r\n\tUINT32\t\t\t\t\tid[RIFFA_MAX_NUM_FPGAS];\r\n\tUINT32\t\t\t\t\tnum_chnls[RIFFA_MAX_NUM_FPGAS];\r\n\tCHAR\t\t\t\t\tname[RIFFA_MAX_NUM_FPGAS][16];\r\n\tUINT32\t\t\t\t\tvendor_id[RIFFA_MAX_NUM_FPGAS];\r\n\tUINT32\t\t\t\t\tdevice_id[RIFFA_MAX_NUM_FPGAS];\r\n} RIFFA_FPGA_INFO, * PRIFFA_FPGA_INFO;\r\n\r\n// Struct for holding DMA transaction state\r\ntypedef struct CHNL_DIR_STATE {\r\n\tLONG\t\t\t\t\tReady;\r\n\tLONG\t\t\t\t\tInUse;\r\n\tLONG\t\t\t\t\tReqdDone;\r\n\tUINT64\t\t\t\t\tLength;\r\n\tUINT64\t\t\t\t\tOffset;\r\n\tUINT32\t\t\t\t\tLast;\r\n\tUINT64\t\t\t\t\tTimeout;\r\n\tUINT64\t\t\t\t\tCapacity;\r\n\tUINT64\t\t\t\t\tProvided;\r\n\tUINT64\t\t\t\t\tProvidedPrev;\r\n\tUINT64\t\t\t\t\tConfirmed;\r\n\tUINT64\t\t\t\t\tConfirmedPrev;\r\n\tUINT64\t\t\t\t\tSpillAfter;\r\n\tPSCATTER_GATHER_LIST\tSgList;\r\n\tUINT32\t\t\t\t\tSgPos;\r\n\tUINT32\t\t\t\t\tActiveCount;\r\n\tUINT32\t\t\t\t\tCancel;\r\n\tWDFSPINLOCK\t\t\t\tSpinLock;\r\n\tWDFTIMER\t\t\t\tTimer;\r\n\tWDFREQUEST\t\t\t\tRequest;\r\n\tWDFDMATRANSACTION \t\tDmaTransaction;\r\n\tWDFCOMMONBUFFER \t\tCommonBuffer;\r\n\tPULONG \t\t\t\t\tCommonBufferBase;\r\n\tPHYSICAL_ADDRESS \t\tCommonBufferBaseLA;\t// Logical Address\r\n} CHNL_DIR_STATE, *PCHNL_DIR_STATE;\r\n\r\n// Struct for holding interrupt signals and data\r\ntypedef struct INTR_CHNL_DIR_DATA {\r\n\tBOOLEAN \t\t\t\tNewTxn;\r\n\tUINT32 \t\t\t\t\tOffLast;\r\n\tUINT32 \t\t\t\t\tLength;\r\n\tBOOLEAN \t\t\t\tSgRead;\r\n\tBOOLEAN \t\t\t\tDone;\r\n} INTR_CHNL_DIR_DATA, *PINTR_CHNL_DIR_DATA;\r\n\r\n// The device extension for the device object\r\ntypedef struct _DEVICE_EXTENSION {\r\n\tWDFDEVICE \t\t\t\tDevice;\r\n\tPULONG \t\t\t\t\tBar0;\r\n\tUINT32 \t\t\t\t\tBar0Length;\r\n\tUINT32\t\t\t\t\tMaxNumScatterGatherElems;\r\n\tWDFINTERRUPT \t\t\tInterrupt;\r\n\tWDFDMAENABLER \t\t\tDmaEnabler;\r\n\tWDFQUEUE \t\t\t\tIoctlQueue;\r\n\tUINT32 \t\t\t\t\tNumChnls;\r\n\tUINT32 \t\t\t\t\tVendorId;\r\n\tUINT32 \t\t\t\t\tDeviceId;\r\n\tCHAR \t\t\t\t\tName[16];\r\n\tINTR_CHNL_DIR_DATA\t\tIntrData[2 * RIFFA_MAX_NUM_CHNLS];\t// Send is the first bank,\r\n\tCHNL_DIR_STATE\t\t\tChnl[(2*RIFFA_MAX_NUM_CHNLS)];\t\t// recv is the second bank\r\n\tWDFCOMMONBUFFER \t\tSpillBuffer;\r\n\tPUCHAR \t\t\t\t\tSpillBufferBase;\r\n\tPHYSICAL_ADDRESS \t\tSpillBufferBaseLA;\t// Logical Address\r\n} DEVICE_EXTENSION, *PDEVICE_EXTENSION;\r\n\r\n// The request extension for the request object\r\ntypedef struct _REQUEST_EXTENSION {\r\n\tUINT32 \t\t\t\t\tChnl;\r\n} REQUEST_EXTENSION, *PREQUEST_EXTENSION;\r\n\r\n// The timer extension for the timer object\r\ntypedef struct _TIMER_EXTENSION {\r\n\tUINT32 \t\t\t\t\tChnl;\r\n} TIMER_EXTENSION, *PTIMER_EXTENSION;\r\n\r\n// This will generate the function named RiffaGetDeviceContext to be used for\r\n// retreiving the DEVICE_EXTENSION pointer.\r\nWDF_DECLARE_CONTEXT_TYPE_WITH_NAME(DEVICE_EXTENSION, RiffaGetDeviceContext)\r\n\r\n// This will generate the function named RiffaGetTimerContext to be used for\r\n// retreiving the TIMER_EXTENSION pointer.\r\nWDF_DECLARE_CONTEXT_TYPE_WITH_NAME(TIMER_EXTENSION, RiffaGetTimerContext)\r\n\r\n// This will generate the function named RiffaGetRequestContext to be used for\r\n// retreiving the REQUEST_EXTENSION pointer.\r\nWDF_DECLARE_CONTEXT_TYPE_WITH_NAME(REQUEST_EXTENSION, RiffaGetRequestContext)\r\n\r\n\r\n// Function prototypes\r\nDRIVER_INITIALIZE DriverEntry;\r\n\r\nEVT_WDF_DRIVER_DEVICE_ADD RiffaEvtDeviceAdd;\r\nEVT_WDF_OBJECT_CONTEXT_CLEANUP RiffaEvtDriverContextCleanup;\r\n\r\nEVT_WDF_DEVICE_PREPARE_HARDWARE RiffaEvtDevicePrepareHardware;\r\nEVT_WDF_DEVICE_RELEASE_HARDWARE RiffaEvtDeviceReleaseHardware;\r\nNTSTATUS RiffaReadHardwareIds(IN PDEVICE_EXTENSION DevExt);\r\n\r\nEVT_WDF_INTERRUPT_ISR RiffaEvtInterruptIsr;\r\nEVT_WDF_INTERRUPT_DPC RiffaEvtInterruptDpc;\r\nBOOLEAN RiffaProcessInterrupt(IN PDEVICE_EXTENSION DevExt, IN UINT32 Offset, IN UINT32 Vect);\r\n\r\nEVT_WDF_IO_QUEUE_IO_DEVICE_CONTROL RiffaEvtIoDeviceControl;\r\nVOID RiffaIoctlSend(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,\r\n\tIN size_t OutputBufferLength, IN size_t InputBufferLength);\r\nVOID RiffaIoctlRecv(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,\r\n\tIN size_t OutputBufferLength, IN size_t InputBufferLength);\r\nVOID RiffaIoctlList(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,\r\n\tIN size_t OutputBufferLength, IN size_t InputBufferLength);\r\nVOID RiffaIoctlReset(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request);\r\n\r\nBOOLEAN RiffaThreadEnter(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);\r\nVOID RiffaThreadExit(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);\r\nVOID RiffaCompleteRequest(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl, IN NTSTATUS Status);\r\nEVT_WDF_REQUEST_CANCEL RiffaEvtRequestCancel;\r\nEVT_WDF_TIMER RiffaEvtTimerFunc;\r\n\r\nVOID RiffaStartRecvTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);\r\nNTSTATUS RiffaStartDmaTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,\r\n\tIN UINT64 Length, IN UINT64 Offset, IN WDF_DMA_DIRECTION DmaDirection);\r\nVOID RiffaProgramScatterGather(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl);\r\nVOID RiffaTransactionComplete(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,\r\n\tIN UINT32 Transferred, IN NTSTATUS Status);\r\nVOID RiffaProgramSend(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl, IN UINT32 Length,\r\n\tIN UINT32 Offset, IN UINT32 Last);\r\nEVT_WDF_PROGRAM_DMA RiffaEvtProgramDma;\r\n\r\n#pragma warning(disable:4127) // avoid conditional expression is constant error with W4\r\n\r\n#endif\r\n\r\n" }, { "path": "sw/riffa_2.1/driver/windows/sys/sources", "content": "TARGETNAME=riffa\r\nTARGETTYPE=DRIVER\r\n\r\n\r\nKMDF_VERSION_MAJOR=1\r\n\r\nINF_NAME=riffa\r\nNTTARGETFILE0=$(OBJ_PATH)\\$(O)\\$(INF_NAME).inf\r\nNTTARGETFILE2=POST\r\nPASS0_BINPLACE=$(NTTARGETFILE0)\r\n\r\nTARGETLIBS=$(TARGETLIBS) \\\r\n $(DDK_LIB_PATH)\\ntstrsafe.lib\r\n\r\nPRECOMPILED_INCLUDE=precomp.h\r\nPRECOMPILED_PCH=precomp.pch\r\nPRECOMPILED_OBJ=precomp.obj\r\n\r\n#C_DEFINES = $(C_DEFINES) -DASSOC_WRITE_REQUEST_WITH_DMA_TRANSACTION=1\r\n\r\nSOURCES= riffa.rc \\\r\n riffa.c\r\n \r\n# Generate WPP tracing code\r\n# $(SOURCES) -- run software preprocessor on files listed in SOURCES\r\n# -km -- use kernel mode\r\n# -func -- define function we'll use for tracing\r\n# This would map all TraceEvents calls to \r\n# DoTraceMessage.\r\n#\r\nRUN_WPP= $(SOURCES) \\\r\n -km \\\r\n -func:TraceEvents(LEVEL,FLAGS,MSG,...) \\\r\n -gen:{km-WdfDefault.tpl}*.tmh\r\n \r\nTARGET_DESTINATION=wdf\r\n\r\n# Temporarily excuse usage of serviceability impairing macros in code...\r\nALLOW_DATE_TIME=1\r\n\r\n" }, { "path": "sw/riffa_2.1/driver/windows/sys/trace.h", "content": "#include // For TRACE_LEVEL definitions\r\n\r\n//\r\n// If software tracing is defined in the sources file..\r\n// WPP_DEFINE_CONTROL_GUID specifies the GUID used for this driver.\r\n// *** REPLACE THE GUID WITH YOUR OWN UNIQUE ID ***\r\n// WPP_DEFINE_BIT allows setting debug bit masks to selectively print.\r\n// The names defined in the WPP_DEFINE_BIT call define the actual names\r\n// that are used to control the level of tracing for the control guid\r\n// specified.\r\n//\r\n// Name of the logger is RIFFA and the guid is\r\n// {CA630800-D4D4-4457-8983-DFBBFCAC5542}\r\n// (0xca630800, 0xd4d4, 0x4457, 0x89, 0x83, 0xdf, 0xbb, 0xfc, 0xac, 0x55, 0x42);\r\n//\r\n\r\n#define WPP_CHECK_FOR_NULL_STRING //to prevent exceptions due to NULL strings\r\n\r\n#define WPP_CONTROL_GUIDS \\\r\n WPP_DEFINE_CONTROL_GUID(RiffaTraceGuid, (ca630800, D4D4, 4457,8983, DFBBFCAC5542),\\\r\n WPP_DEFINE_BIT(DBG_INIT) /* bit 0 = 0x00000001 */ \\\r\n WPP_DEFINE_BIT(DBG_PNP) /* bit 1 = 0x00000002 */ \\\r\n /* You can have up to 32 defines. If you want more than that,\\\r\n you have to provide another trace control GUID */\\\r\n )\r\n\r\n\r\n#define WPP_LEVEL_FLAGS_LOGGER(lvl,flags) WPP_LEVEL_LOGGER(flags)\r\n#define WPP_LEVEL_FLAGS_ENABLED(lvl, flags) (WPP_LEVEL_ENABLED(flags) && WPP_CONTROL(WPP_BIT_ ## flags).Level >= lvl)\r\n\r\n\r\n" }, { "path": "sw/riffa_2.1/driver/windows/win7install.bat", "content": "@echo off\r\n\r\nset OLDDIR=%CD%\r\nset BDIR1=%CD%\\sys\\obj%_BUILDTYPE%_%DDK_TARGET_OS%_x86\\i386\r\nset BDIR2=%CD%\\sys\\obj%_BUILDTYPE%_%DDK_TARGET_OS%_amd64\\amd64\r\nchdir /d %CD%\\install\r\ncall install.bat %BDIR1% %BDIR2% %_BUILDTYPE%\r\nchdir /d %OLDDIR%" } ]