[ { "path": ".gitattributes", "content": "*.cpp text diff=cpp\n*.hpp text diff=cpp\n*.c text diff=cpp\n*.h text diff=cpp\n*.md text \nMakefile text\n*.mk text\n*.sh text\n*.command text\n*.svg text\n*.yml text\n*.py text\n*.pip text\n*.css text\n*.html text\n*.js text\n\n*.png binary\n*.jpg binary\n*.jpeg binary\n*.ttf binary\n\n" }, { "path": ".github/ISSUE_TEMPLATE/bug-report.md", "content": "---\nname: Bug report\nabout: Report unexpected or confusing behavior when using the modules inside VCV Rack\ntitle: \"[BUG REPORT]\"\nlabels: ''\nassignees: ''\n\n---\n\n** Platform/Version **\n - OS version:\n - Rack version:\n - Plugin version:\n\n**Describe the bug**\nDescribe the behavior you're seeing, and what you expected the behavior should have been.\n\n**VCV Rack logfile**\nAttach `log.txt` from your VCV Rack user folder ([Where is the VCV Rack user folder?](https://vcvrack.com/manual/FAQ#Where-is-the-Rack-user-folder))\n\n**How to Reproduce**\nSteps to reproduce the behavior:\n1. Go to '...'\n2. Click on '....'\n3. See error\n\n**Patch file**\nIf the steps to reproduce require a particular arrangement of several modules, please attach a VCV Rack patch that demonstrates the issue.\n\n**Additional context**\nAdd any other context, screenshots, etc., about the problem here.\n" }, { "path": ".github/ISSUE_TEMPLATE/build-error.md", "content": "---\nname: Build issue\nabout: Report a problem building the modules in your own environment\ntitle: \"[BUILD ISSUE]\"\nlabels: ''\nassignees: ''\n\n---\n\n** Platform/Version **\n- OS version:\n- Plugin version:\n- Rack SDK version:\n\n**Please run these commands and include the complete output:**\n```git status\ngit submodule status\nmake clean\nmake dep\nmake```\n\n**Please include any other details about your system and build environment, e.g. \"I'm trying to build for Mac ARM64 using Visual Studio Code\", etc.**\n" }, { "path": ".github/workflows/build-plugin.yaml", "content": "name: Build VCV Rack Plugin\non: \n push:\n paths-ignore:\n - 'docs/**'\n - '*.md'\n - 'mkdocs.yml'\n - 'LICENSE'\n - '.github/ISSUE_TEMPLATE/**'\n - '.github/workflows/deploy-pages.yaml'\n\nenv:\n rack-sdk-version: 2.4.0\n rack-plugin-toolchain-dir: /home/build/rack-plugin-toolchain\n\ndefaults:\n run:\n shell: bash\n\njobs:\n\n modify-plugin-version:\n name: Modify plugin version\n runs-on: ubuntu-latest\n steps:\n - uses: actions/checkout@v4\n - uses: actions/cache@v3\n id: plugin-version-cache\n with:\n path: plugin.json\n key: ${{ github.sha }}-${{ github.run_id }}\n - run: |\n gitrev=`git rev-parse --short HEAD`\n pluginversion=`jq -r '.version' plugin.json`\n echo \"Set plugin version from $pluginversion to $pluginversion-$gitrev\"\n cat <<< `jq --arg VERSION \"$pluginversion-$gitrev\" '.version=$VERSION' plugin.json` > plugin.json\n # only modify plugin version if no tag was created\n if: \"! startsWith(github.ref, 'refs/tags/v')\"\n build:\n name: ${{ matrix.platform }}\n needs: modify-plugin-version\n runs-on: ubuntu-latest\n container:\n image: ghcr.io/qno/rack-plugin-toolchain-win-linux\n options: --user root\n strategy:\n matrix:\n platform: [win-x64, lin-x64]\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n fetch-depth: 0\n - uses: actions/cache@v3\n id: plugin-version-cache\n with:\n path: plugin.json\n key: ${{ github.sha }}-${{ github.run_id }}\n - name: Build plugin\n run: |\n export PLUGIN_DIR=$GITHUB_WORKSPACE\n pushd ${{ env.rack-plugin-toolchain-dir }}\n sed -i 's/\\(RACK_SDK_VERSION \\:\\= \\)[0-9\\.]\\+$/\\1${{ env.rack-sdk-version }}/' Makefile\n make rack-sdk-clean\n make rack-sdk-${{ matrix.platform }}\n make plugin-build-${{ matrix.platform }}\n - name: Upload artifact\n uses: actions/upload-artifact@v4\n with:\n path: ${{ env.rack-plugin-toolchain-dir }}/plugin-build\n name: ${{ matrix.platform }}\n\n build-mac:\n name: mac-${{ matrix.platform }}\n needs: modify-plugin-version\n runs-on: macos-latest\n strategy:\n fail-fast: false\n matrix:\n platform: [x64, arm64]\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n fetch-depth: 0\n - uses: actions/cache@v3\n id: plugin-version-cache\n with:\n path: plugin.json\n key: ${{ github.sha }}-${{ github.run_id }}\n - name: Get Rack-SDK\n run: |\n pushd $HOME\n curl -o Rack-SDK.zip https://vcvrack.com/downloads/Rack-SDK-${{ env.rack-sdk-version }}-mac-${{ matrix.platform }}.zip\n unzip Rack-SDK.zip\n - name: Build plugin\n run: |\n CROSS_COMPILE_TARGET_x64=x86_64-apple-darwin\n CROSS_COMPILE_TARGET_arm64=arm64-apple-darwin\n export RACK_DIR=$HOME/Rack-SDK\n export CROSS_COMPILE=$CROSS_COMPILE_TARGET_${{ matrix.platform }}\n make dep\n make dist\n - name: Upload artifact\n uses: actions/upload-artifact@v4\n with:\n path: dist/*.vcvplugin\n name: mac-${{ matrix.platform }}\n\n publish:\n name: Publish plugin\n # only create a release if a tag was created that is called e.g. v1.2.3\n # see also https://vcvrack.com/manual/Manifest#version\n if: startsWith(github.ref, 'refs/tags/v')\n runs-on: ubuntu-latest\n permissions:\n contents: write\n needs: [build, build-mac]\n steps:\n - uses: actions/checkout@v4\n - uses: FranzDiebold/github-env-vars-action@v2\n - name: Check if plugin version matches tag\n run: |\n pluginversion=`jq -r '.version' plugin.json`\n if [ \"v$pluginversion\" != \"${{ env.CI_REF_NAME }}\" ]; then\n echo \"Plugin version from plugin.json 'v$pluginversion' doesn't match with tag version '${{ env.CI_REF_NAME }}'\"\n exit 1\n fi\n - name: Create Release\n uses: softprops/action-gh-release@v1\n with:\n tag_name: ${{ github.ref }}\n name: Release ${{ env.CI_REF_NAME }}\n body: |\n ${{ env.CI_REPOSITORY_NAME }} VCV Rack Plugin ${{ env.CI_REF_NAME }}\n draft: false\n prerelease: false\n - uses: actions/download-artifact@v4\n with:\n path: _artifacts\n - name: Upload release assets\n uses: svenstaro/upload-release-action@v2\n with:\n repo_token: ${{ secrets.GITHUB_TOKEN }}\n file: _artifacts/**/*.vcvplugin\n tag: ${{ github.ref }}\n file_glob: true\n" }, { "path": ".github/workflows/deploy-pages.yml", "content": "name: Update Docs Site\n\non:\n push:\n paths: \n - 'docs/**'\n - 'mkdocs.yml'\n - '.github/workflows/deploy-pages.yml'\n workflow_dispatch:\n\npermissions:\n contents: read\n pages: write\n id-token: write\n\nconcurrency:\n group: \"pages\"\n cancel-in-progress: false\n\njobs:\n build:\n name: \"Build MkDocs static site\"\n runs-on: ubuntu-latest\n steps:\n - name: Checkout\n uses: actions/checkout@v3\n - name: Setup MkDocs\n run: pip install -r docs/requirements.txt\n - name: Run MkDocs\n run: |\n mkdir -p build/docs\n mkdocs build\n - name: Upload artifact\n uses: actions/upload-pages-artifact@v1\n with:\n path: 'build/docs'\n\n deploy:\n needs: [ build ]\n if: github.ref == 'refs/heads/main'\n name: \"Deploy content to GitHub Pages\"\n environment:\n name: github-pages\n url: ${{ steps.deployment.outputs.page_url }}\n runs-on: ubuntu-latest\n steps:\n - name: Setup Pages\n uses: actions/configure-pages@v3\n - name: Deploy to GitHub Pages\n id: deployment\n uses: actions/deploy-pages@v1\n" }, { "path": ".gitignore", "content": "/build\nplugin*.dylib\nplugin*.dll\nplugin*.so\n.DS_Store\n/res/firmware\n/firmware/build\n/dist\n.vscode/ipch\n/Rack-SDK\nRack-SDK*.zip\n/dep\nragel*.tar.gz\n" }, { "path": ".gitmodules", "content": "[submodule \"firmware/whitewhale\"]\n\tpath = firmware/whitewhale\n\turl = https://github.com/Dewb/whitewhale\n\tbranch = vcvrack_pr\n[submodule \"firmware/teletype4\"]\n\tpath = firmware/teletype4\n\turl = https://github.com/Dewb/teletype\n\tbranch = vcvrack-4.0.0\n[submodule \"firmware/meadowphysics\"]\n\tpath = firmware/meadowphysics\n\turl = https://github.com/Dewb/meadowphysics\n\tbranch = vcvrack\n[submodule \"firmware/earthsea\"]\n\tpath = firmware/earthsea\n\turl = https://github.com/Dewb/earthsea\n\tbranch = vcvrack\n[submodule \"firmware/ansible\"]\n\tpath = firmware/ansible\n\turl = https://github.com/Dewb/ansible\n\tbranch = vcvrack\n[submodule \"firmware/teletype5\"]\n\tpath = firmware/teletype5\n\turl = https://github.com/monome/teletype\n\tbranch = main\n[submodule \"firmware/whitewhale-kria\"]\n\tpath = firmware/whitewhale-kria\n\turl = https://github.com/Dewb/kria\n\tbranch = vcvrack\n" }, { "path": ".vscode/c_cpp_properties.json", "content": "{\n \"configurations\": [\n {\n \"name\": \"Mac\",\n \"includePath\": [\n \"${workspaceFolder}/**\",\n \"${workspaceFolder}/Rack-SDK/dep/**\",\n \"${workspaceFolder}/Rack-SDK/include/**\",\n \"/Library/Developer/CommandLineTools/usr/include/c++/v1\",\n \"/usr/local/include\",\n \"/Library/Developer/CommandLineTools/usr/include\",\n \"/usr/include\"\n ],\n \"defines\": [],\n \"intelliSenseMode\": \"clang-x64\",\n \"browse\": {\n \"path\": [\n \"${workspaceFolder}/**\",\n \"${workspaceFolder}/Rack-SDK/dep/**\",\n \"${workspaceFolder}/Rack-SDK/include/**\",\n \"/Library/Developer/CommandLineTools/usr/include/c++/v1\",\n \"/usr/local/include\",\n \"/Library/Developer/CommandLineTools/usr/include\",\n \"/usr/include\"\n ],\n \"limitSymbolsToIncludedHeaders\": true,\n \"databaseFilename\": \"\"\n },\n \"macFrameworkPath\": [\n \"/System/Library/Frameworks\",\n \"/Library/Frameworks\"\n ],\n \"compilerPath\": \"/usr/bin/clang\",\n \"cStandard\": \"c11\",\n \"cppStandard\": \"c++17\"\n },\n {\n \"name\": \"Linux\",\n \"includePath\": [\n \"/usr/include\",\n \"/usr/local/include\",\n \"${workspaceFolder}/**\",\n \"${workspaceFolder}/Rack-SDK/dep/**\",\n \"${workspaceFolder}/Rack-SDK/include/**\"\n ],\n \"defines\": [],\n \"intelliSenseMode\": \"clang-x64\",\n \"browse\": {\n \"path\": [\n \"/usr/include\",\n \"/usr/local/include\",\n \"${workspaceFolder}\",\n \"${workspaceFolder}/../../include\"\n ],\n \"limitSymbolsToIncludedHeaders\": true,\n \"databaseFilename\": \"\"\n }\n },\n {\n \"name\": \"Win32\",\n \"includePath\": [\n \"${workspaceFolder}/**\",\n \"${workspaceFolder}/Rack-SDK/dep/**\",\n \"${workspaceFolder}/Rack-SDK/include/**\"\n ],\n \"defines\": [\n \"_DEBUG\",\n \"UNICODE\",\n \"_UNICODE\"\n ],\n \"windowsSdkVersion\": \"10.0.18362.0\",\n \"compilerPath\": \"C:\\\\msys64\\\\mingw64\\\\bin\\\\g++.exe\",\n \"intelliSenseMode\": \"windows-gcc-x64\",\n \"cStandard\": \"c11\",\n \"cppStandard\": \"c++17\"\n }\n ],\n \"version\": 4\n}" }, { "path": ".vscode/launch.json", "content": "{\n // Use IntelliSense to learn about possible attributes.\n // Hover to view descriptions of existing attributes.\n // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387\n \"version\": \"0.2.0\",\n \"configurations\": [\n {\n \"name\": \"Debug Plugin in VCV Rack\",\n \"type\": \"cppdbg\",\n \"request\": \"launch\",\n \"windows\": {\n \"program\": \"C:\\\\Program Files\\\\VCV\\\\Rack2Free\\\\Rack.exe\",\n \"args\": [\n ],\n \"MIMode\": \"gdb\",\n \"environment\": [\n \n ],\n \"miDebuggerPath\": \"c:\\\\msys64\\\\mingw64\\\\bin\\\\gdb.exe\",\n \"setupCommands\": [\n {\n \"description\": \"Enable pretty-printing for gdb\",\n \"text\": \"-enable-pretty-printing\",\n \"ignoreFailures\": true\n }\n ]\n },\n \"osx\" : {\n \"program\": \"/Applications/VCV Rack 2 Free.app/Contents/MacOS/Rack\",\n \"args\": [],\n \"MIMode\": \"lldb\",\n \"environment\": [\n {\n \"name\": \"DYLD_FALLBACK_LIBRARY_PATH\",\n \"value\": \"dep/lib\"\n },\n {\n \"name\": \"LD_LIBRARY_PATH\",\n \"value\": \"dep/lib\"\n }\n ]\n },\n \"stopAtEntry\": false,\n \"cwd\": \"${workspaceFolder}\",\n \"externalConsole\": false,\n }\n ]\n}" }, { "path": ".vscode/settings.json", "content": "{\n \"editor.tabSize\": 4,\n \"editor.insertSpaces\": true,\n \"editor.formatOnType\": true,\n \"editor.formatOnPaste\": true,\n \"C_Cpp.clang_format_style\": \"{ BasedOnStyle: WebKit, BreakBeforeBraces: Allman, IndentCaseLabels: true }\",\n \"files.associations\": {\n \"ios\": \"cpp\",\n \"random\": \"cpp\",\n \"*.ipp\": \"cpp\",\n \"typeinfo\": \"cpp\",\n \"stdexcept\": \"cpp\",\n \"string\": \"cpp\",\n \"chrono\": \"cpp\",\n \"istream\": \"cpp\",\n \"__bit_reference\": \"cpp\",\n \"__functional_base\": \"cpp\",\n \"algorithm\": \"cpp\",\n \"atomic\": \"cpp\",\n \"bitset\": \"cpp\",\n \"deque\": \"cpp\",\n \"functional\": \"cpp\",\n \"iterator\": \"cpp\",\n \"limits\": \"cpp\",\n \"memory\": \"cpp\",\n \"ratio\": \"cpp\",\n \"system_error\": \"cpp\",\n \"tuple\": \"cpp\",\n \"type_traits\": \"cpp\",\n \"vector\": \"cpp\",\n \"sstream\": \"cpp\",\n \"strstream\": \"cpp\",\n \"locale\": \"cpp\",\n \"__locale\": \"cpp\",\n \"stdint.h\": \"c\",\n \"globals.h\": \"c\",\n \"cmath\": \"cpp\",\n \"complex\": \"cpp\",\n \"cstdarg\": \"cpp\",\n \"cstddef\": \"cpp\",\n \"cstdint\": \"cpp\",\n \"cstdio\": \"cpp\",\n \"cstdlib\": \"cpp\",\n \"cstring\": \"cpp\",\n \"cwchar\": \"cpp\",\n \"exception\": \"cpp\",\n \"fstream\": \"cpp\",\n \"initializer_list\": \"cpp\",\n \"iosfwd\": \"cpp\",\n \"iostream\": \"cpp\",\n \"list\": \"cpp\",\n \"map\": \"cpp\",\n \"new\": \"cpp\",\n \"ostream\": \"cpp\",\n \"queue\": \"cpp\",\n \"set\": \"cpp\",\n \"streambuf\": \"cpp\",\n \"unordered_set\": \"cpp\",\n \"utility\": \"cpp\",\n \"xfacet\": \"cpp\",\n \"xhash\": \"cpp\",\n \"xiosbase\": \"cpp\",\n \"xlocale\": \"cpp\",\n \"xlocinfo\": \"cpp\",\n \"xlocnum\": \"cpp\",\n \"xmemory\": \"cpp\",\n \"xmemory0\": \"cpp\",\n \"xstddef\": \"cpp\",\n \"xstring\": \"cpp\",\n \"xtr1common\": \"cpp\",\n \"xtree\": \"cpp\",\n \"xutility\": \"cpp\",\n \"array\": \"cpp\",\n \"bit\": \"cpp\",\n \"*.tcc\": \"cpp\",\n \"cctype\": \"cpp\",\n \"clocale\": \"cpp\",\n \"compare\": \"cpp\",\n \"concepts\": \"cpp\",\n \"ctime\": \"cpp\",\n \"cwctype\": \"cpp\",\n \"unordered_map\": \"cpp\",\n \"memory_resource\": \"cpp\",\n \"numeric\": \"cpp\",\n \"optional\": \"cpp\",\n \"string_view\": \"cpp\",\n \"iomanip\": \"cpp\",\n \"ranges\": \"cpp\",\n \"stop_token\": \"cpp\",\n \"thread\": \"cpp\",\n \"cinttypes\": \"cpp\",\n \"variant\": \"cpp\",\n \"flash.h\": \"c\",\n \"codecvt\": \"cpp\",\n \"condition_variable\": \"cpp\",\n \"regex\": \"cpp\",\n \"shared_mutex\": \"cpp\",\n \"mock_hardware_api.h\": \"c\",\n \"__node_handle\": \"cpp\",\n \"mock_hardware_api_private.h\": \"c\",\n \"__functional_03\": \"cpp\",\n \"mutex\": \"cpp\",\n \"__config\": \"cpp\",\n \"__hash_table\": \"cpp\",\n \"__split_buffer\": \"cpp\",\n \"__threading_support\": \"cpp\",\n \"__tree\": \"cpp\",\n \"__verbose_abort\": \"cpp\",\n \"cfenv\": \"cpp\",\n \"charconv\": \"cpp\",\n \"execution\": \"cpp\",\n \"stack\": \"cpp\"\n }\n}" }, { "path": ".vscode/tasks.json", "content": "{\n // See https://go.microsoft.com/fwlink/?LinkId=733558\n // for the documentation about the tasks.json format\n \"version\": \"2.0.0\",\n \"tasks\": [\n {\n \"label\": \"Build Rack plugin with debug info\",\n \"type\": \"shell\",\n \"group\": {\n \"kind\": \"build\",\n \"isDefault\": true\n },\n \"presentation\": {\n \"echo\": true,\n \"reveal\": \"always\",\n \"focus\": false,\n \"panel\": \"shared\"\n },\n \"command\": \"RACK_DIR=$PWD/Rack-SDK make -j4 install\",\n \"options\": {\n \"cwd\": \"${workspaceRoot}\",\n \"env\": {\n \"STRIP\": \"echo\"\n }\n },\n \"windows\": {\n \"options\": {\n \"env\": {\n \"PATH\": \"C:\\\\msys64\\\\usr\\\\bin;c:\\\\msys64\\\\mingw64\\\\bin\",\n \"MSYSTEM\": \"MINGW64\",\n \"CC\": \"gcc\"\n },\n \"shell\": {\n \"executable\": \"C:\\\\msys64\\\\usr\\\\bin\\\\bash.exe\",\n \"args\": [\n \"-c\"\n ]\n }\n },\n \"problemMatcher\": {\n \"owner\": \"cpp\",\n \"fileLocation\": [\n \"absolute\"\n ],\n \"pattern\": {\n \"regexp\": \"^(.*):(\\\\d+):(\\\\d+):\\\\s+(warning|error):\\\\s+(.*)$\",\n \"file\": 1,\n \"line\": 2,\n \"column\": 3,\n \"severity\": 4,\n \"message\": 5\n }\n }\n },\n \"osx\": {\n\n },\n \"linux\": {\n \n }\n },\n {\n \"label\": \"Clean Rack plugin\",\n \"type\": \"shell\",\n \"group\": \"none\",\n \"presentation\": {\n \"echo\": true,\n \"reveal\": \"always\",\n \"focus\": false,\n \"panel\": \"shared\"\n },\n \"command\": \"make clean\",\n \"options\": {\n \"cwd\": \"${workspaceRoot}\",\n \"env\": {\n \"RACK_DIR\": \"${workspaceFolder}/Rack-SDK\",\n \"STRIP\": \"echo\"\n }\n },\n \"windows\": {\n \"options\": {\n \"env\": {\n \"PATH\": \"C:\\\\msys64\\\\usr\\\\bin;c:\\\\msys64\\\\mingw64\\\\bin\",\n \"MSYSTEM\": \"MINGW64\"\n },\n \"shell\": {\n \"executable\": \"C:\\\\msys64\\\\usr\\\\bin\\\\bash.exe\",\n \"args\": [\n \"-c\"\n ]\n }\n },\n \"problemMatcher\": []\n },\n \"osx\": {\n\n },\n \"linux\": {\n\n },\n \"problemMatcher\": []\n }\n ]\n}" }, { "path": "DEVELOPING.md", "content": "\n## Installing prerelease builds\n\nDownload a release for your platform from the [Releases page](../../releases) and place the .vcvplugin file into the plugins subfolder inside your Rack 2 user folder. The user folder on your OS can be opened from the Rack menu bar at **Help** > **Open user folder**. The plugins subfolder will be named `plugins--`\n\nMore detailed instructions for installing non-library plugins are available in the [Rack manual](https://vcvrack.com/manual/Installing#Installing-plugins-not-available-on-the-VCV-Library).\n\n## Building the plugin using the Rack SDK\n\n1. Set up a local [Rack development environment](https://vcvrack.com/manual/Building) as described in the Rack manual.\n2. Clone this repo.\n ```bash\n $ git clone https://github.com/Dewb/monome-rack\n ```\n3. Change into the `monome-rack` folder and clone the plugin's submodules with `git submodule update --init --recursive`\n ```bash\n $ cd monome-rack\n $ git submodule update --init --recursive\n ```\n4. Download the latest Rack 2.x SDK. (The URL will depend on your OS and CPU architecture, see https://vcvrack.com/downloads).\n ```bash\n $ curl -O https://vcvrack.com/downloads/Rack-SDK-2.4.0-mac-arm64.zip\n $ unzip Rack-SDK-2.5.0-mac-arm64.zip\n $ rm Rack-SDK-2.5.0-mac-arm64.zip\n ```\n5. Build dependencies with `make dep`.\n ```bash\n $ RACK_DIR=$(PWD)/Rack-SDK make dep\n ```\n6. Run `make install` to build the plugin and copy it into the Rack plugins folder. (Alternately, open the `monome-rack` folder in Visual Studio Code and select `Tasks > Run Build Task`.)\n ```bash\n $ RACK_DIR=$(PWD)/Rack-SDK make -j4 install\n ```\n\n## Building the plugin using the complete VCV Rack source\n\n1. Read the [VCVRack](https://github.com/VCVRack/Rack) build instructions for your platform and follow them carefully. Run and test Rack to make sure it works as expected.\n ```bash\n $ git clone -b v2 https://github.com/VCVRack/Rack\n $ cd Rack\n $ git submodule update --init --recursive\n $ make dep\n $ make\n $ make run\n ``` \n2. Clone this repo into the `plugins` folder under VCVRack.\n ```bash\n $ cd plugins\n $ git clone https://github.com/Dewb/monome-rack\n ```\n3. Change into the `monome-rack` folder and clone the plugin's submodules with `git submodule update --init --recursive`, then `make dep` to build dependencies.\n ```bash\n $ cd monome-rack\n $ git submodule update --init --recursive\n $ make dep\n ```\n4. Build with `make`, or open the `monome-rack` folder in Visual Studio Code and select `Tasks > Run Build Task`.\n ```bash\n $ make -j4\n ```\n\n## Updating documentation\n\nPrerequisites:\n* Recent `pip` and `python` 3.x\n* `mkdocs` and `mkdocs-terminal`. Install with:\n ```bash\n $ pip install -r docs/requirements.txt\n ```\n\nStart a hot-reload server with `mkdocs serve`, and run `mkdocs build` to produce the static site.\n\n## Using monome-rack as a development environment for module firmware\n\nThis plugin can be used to accelerate firmware development for the hardware. The cycle of rebuilding the plugin and restarting Rack is faster than reflashing hardware, and desktop software debuggers are easier to set up than an in-circuit debugger.\n\nFirst, some caveats: modifying the firmware can't change anything about the Rack \"virtual hardware\"; it will have the same panel, with the same inputs, outputs, and controls. If you want to making something new, pick as a starting point the module that best aligns with the I/O needs of your new idea. (The name of the firmware determines which module the firmware will be available for, and therefore which panel and I/O will be used, so when you create the new submodule, make sure your submodule folder name starts with the name of the base module.)\n\nSimilarly, if you want to change code that interacts directly with the physical hardware at a low level, like USB device detection or ADC/DAC timing, that code may not be executed in Rack. You'll have to skip to the last step and build and test directly on the hardware. \n\nFinally, keep in mind that a desktop computer has more resources than the AVR32 CPU inside each module. Memory is quite limited, and each module has limited time to compute its tasks inbetween event ticks. Taking too long on an operation risks delaying the next event, potentially throwing off the timing of sequences, or making input responses feel sluggish. Not everything that works on a desktop computer will easily translate to the hardware without further optimization. (It can be helpful to set these concerns aside during early development and brainstorming, of course -- first figure out if your idea works the way you want it to, and only then work on making it efficient.)\n\nLet's walk through setting up a development environment for one of the modules. This example will use Teletype as it's the most actively developed firmware.\n\n1. First, make sure you can build the monome-rack plugin using the instructions in either [Building the plugin using the Rack SDK](#building-the-plugin-using-the-rack-sdk) or [Building the plugin using the complete VCV Rack source](#building-the-plugin-using-the-complete-vcv-rack-source) above.\n2. Find the GitHub URL and branch name for the firmware you want to modify. Right now, only Teletype is fully \"Rack ready\" in the upstream repository; the others need Rack-specific branches off forks.\n | module | repository url | branch |\n | ------------- | ------------------------------------- | ---------- |\n | ansible | https://github.com/Dewb/ansible | vcvrack |\n | earthsea | https://github.com/Dewb/earthsea | vcvrack |\n | meadowphysics | https://github.com/Dewb/meadowphysics | vcvrack | \n | teletype | https://github.com/monome/teletype | main |\n | whitewhale | https://github.com/Dewb/whitewhale | vcvrack_pr |\n3. Optional: Sign up for a [GitHub](https://github.com) account if you don't already have one, and use the \"Fork\" button on one of the repository pages above corresponding to the module you want to modify. On the subsequent page, **uncheck** the \"Copy the main branch only\" checkbox, so you have access to the non-main branches in your fork (necessary for any module besides teletype.)\n * Note: If you don't do this, you can run the following commands with the URL and branch listed above directly, but it will be more complicated to share your work with others later.\n5. Use the `git submodule` command to create a new firmware submodule inside the `firmware` folder. Let's say we want to create a new development version of the teletype firmware and call it `teletype-dev` within the Rack environment.\n ```bash\n $ cd monome-rack\n $ cd firmware\n $ git submodule add -b main https://github.com//teletype teletype-dev\n ```\n6. Run `git submodule update` to fetch the submodule children of the new submodule.\n ```bash\n $ git submodule update --init --recursive\n ```\n7. Now we need to modify the plugin build process to include `teletype-dev` in our list of firmware binaries to build and add to the plugin. Edit `Makefile` in the monome-rack root folder and under the `firmware-build:` section, add the line:\n ```\n cd firmware && $(MAKE) -f teletype.mk TARGET_NAME=teletype-dev\n ```\n Make sure this line is indented with a single tab character, like the other lines in the section.\n8. Rebuild the plugin using `make install` or the Visual Studio Code **Run Build Task...** command, as in step 1.\n9. Run Rack and place a Teletype module. You should be able to see `teletype-dev` as one of the choices in the **Firmware Tools** > **Switch Firmware** right-click menu. Switch to it! You're now using the code from the new submodule folder you created in step 3.\n10. Let's make some changes to the code. Close Rack and open `firmware/teletype-dev/module/live_mode.c` in your favorite editor. Go to line 771 and change the string `\"TELETYPE \"` to something else, like `\"HELLO \"`. Leave the space at the end of the string.\n11. Rebuild the plugin again as in step 6.\n12. Run Rack again, and now any Teletype modules in your patch running the `teletype-dev` firmware should say **HELLO** on the startup screen instead of **TELETYPE**.\n13. Now you can make some more substantial changes. Fix a bug, add a new feature, or erase everything and create a completely new module. You can also repeat steps 4-7 more than once if you want to pursue multiple ideas in parallel; just make sure you give each new submodule folder a unique name.\n * Note: if your goal is to create new behavior for the module from scratch, you'll need to preserve the `initialize_module()` and `check_events()` functions, but most everything else is fair game. You'll need to use the `DECLARE_VRAM` and `DECLARE_NVRAM` macros on your key data structures to have them preserved in the Rack patch. Compare the `whitewhale` and `whitewhale-kria` submodules to see and example of two different firmware for the same module. \n14. When you have made something interesting and want to share it, you'll need to commit back to your firmware fork. It's probably a good idea to first create a branch:\n ```bash\n $ cd firmware/teletype-dev\n $ git checkout -b my_new_feature\n ```\n15. Now push that branch to your fork:\n ```bash\n $ git push -u origin my_new_feature\n ```\n16. Share your work! Note that this will *not* create any commits in your local copy of the monome-rack repo. This is okay, as you don't need to commit the changes to Rack to add your development firmware. You can share the firmware binaries from the `res` folder to other people and they won't have to build anything. Alternately, they can add your firmware to their build environment themselves by following steps 4-6, except instead of using the normal firmware URL and branch, they'll use your URL and branch in the `git submodule add` command:\n ```bash\n $ git submodule add -b my_new_feature https://github.com//teletype teletype-dev\n ```\n17. Finally, once your new fix or feature is tested and working inside Rack, you can try building it for the hardware. The hardware build process uses a `Makefile` *inside* the specific firmware subfolder, instead of the Rack makefiles in the root of the `firmware/` folder. Building with these Makefiles requires [the avr32 toolchain](https://github.com/monome/avr32-toolchain) to be installed and in your path, a potentially complex process. However, if you have Docker or Rancher Desktop you can use a preconfigured image to make this easy.\n ```bash\n $ cd firmware/teletype-dev\n $ nerdctl run -v $(pwd):/target -t dewb/monome-build \n ```\n See [the monome-build image README](https://github.com/Dewb/monome-build/blob/master/README.md) for more background on building with the image.\n * Note: The teletype Makefile runs git commands, but the Rack submodule structure moves the .git contents to the plugin root folder and puts it out of scope of the docker image. For now, to make the teletype build work, you'll need to comment out the last two lines of the Makefile, like so:\n ```make\n # Add the git commit id to a file for use when printing out the version\n #../module/gitversion.c: $(GIT_DIR)/HEAD $(GIT_DIR)/index\n #\techo \"const char *git_version = \\\"$(shell cut -d '-' -f 1 ...\n" }, { "path": "LICENSE", "content": "GNU GENERAL PUBLIC LICENSE\n Version 2, June 1991\n\n Copyright (C) 1989, 1991 Free Software Foundation, Inc., \n 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n Preamble\n\n The licenses for most software are designed to take away your\nfreedom to share and change it. By contrast, the GNU General Public\nLicense is intended to guarantee your freedom to share and change free\nsoftware--to make sure the software is free for all its users. This\nGeneral Public License applies to most of the Free Software\nFoundation's software and to any other program whose authors commit to\nusing it. (Some other Free Software Foundation software is covered by\nthe GNU Lesser General Public License instead.) You can apply it to\nyour programs, too.\n\n When we speak of free software, we are referring to freedom, not\nprice. Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthis service if you wish), that you receive source code or can get it\nif you want it, that you can change the software or use pieces of it\nin new free programs; and that you know you can do these things.\n\n To protect your rights, we need to make restrictions that forbid\nanyone to deny you these rights or to ask you to surrender the rights.\nThese restrictions translate to certain responsibilities for you if you\ndistribute copies of the software, or if you modify it.\n\n For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must give the recipients all the rights that\nyou have. You must make sure that they, too, receive or can get the\nsource code. And you must show them these terms so they know their\nrights.\n\n We protect your rights with two steps: (1) copyright the software, and\n(2) offer you this license which gives you legal permission to copy,\ndistribute and/or modify the software.\n\n Also, for each author's protection and ours, we want to make certain\nthat everyone understands that there is no warranty for this free\nsoftware. If the software is modified by someone else and passed on, we\nwant its recipients to know that what they have is not the original, so\nthat any problems introduced by others will not reflect on the original\nauthors' reputations.\n\n Finally, any free program is threatened constantly by software\npatents. We wish to avoid the danger that redistributors of a free\nprogram will individually obtain patent licenses, in effect making the\nprogram proprietary. To prevent this, we have made it clear that any\npatent must be licensed for everyone's free use or not licensed at all.\n\n The precise terms and conditions for copying, distribution and\nmodification follow.\n\n GNU GENERAL PUBLIC LICENSE\n TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\n\n 0. This License applies to any program or other work which contains\na notice placed by the copyright holder saying it may be distributed\nunder the terms of this General Public License. The \"Program\", below,\nrefers to any such program or work, and a \"work based on the Program\"\nmeans either the Program or any derivative work under copyright law:\nthat is to say, a work containing the Program or a portion of it,\neither verbatim or with modifications and/or translated into another\nlanguage. (Hereinafter, translation is included without limitation in\nthe term \"modification\".) Each licensee is addressed as \"you\".\n\nActivities other than copying, distribution and modification are not\ncovered by this License; they are outside its scope. The act of\nrunning the Program is not restricted, and the output from the Program\nis covered only if its contents constitute a work based on the\nProgram (independent of having been made by running the Program).\nWhether that is true depends on what the Program does.\n\n 1. You may copy and distribute verbatim copies of the Program's\nsource code as you receive it, in any medium, provided that you\nconspicuously and appropriately publish on each copy an appropriate\ncopyright notice and disclaimer of warranty; keep intact all the\nnotices that refer to this License and to the absence of any warranty;\nand give any other recipients of the Program a copy of this License\nalong with the Program.\n\nYou may charge a fee for the physical act of transferring a copy, and\nyou may at your option offer warranty protection in exchange for a fee.\n\n 2. You may modify your copy or copies of the Program or any portion\nof it, thus forming a work based on the Program, and copy and\ndistribute such modifications or work under the terms of Section 1\nabove, provided that you also meet all of these conditions:\n\n a) You must cause the modified files to carry prominent notices\n stating that you changed the files and the date of any change.\n\n b) You must cause any work that you distribute or publish, that in\n whole or in part contains or is derived from the Program or any\n part thereof, to be licensed as a whole at no charge to all third\n parties under the terms of this License.\n\n c) If the modified program normally reads commands interactively\n when run, you must cause it, when started running for such\n interactive use in the most ordinary way, to print or display an\n announcement including an appropriate copyright notice and a\n notice that there is no warranty (or else, saying that you provide\n a warranty) and that users may redistribute the program under\n these conditions, and telling the user how to view a copy of this\n License. (Exception: if the Program itself is interactive but\n does not normally print such an announcement, your work based on\n the Program is not required to print an announcement.)\n\nThese requirements apply to the modified work as a whole. If\nidentifiable sections of that work are not derived from the Program,\nand can be reasonably considered independent and separate works in\nthemselves, then this License, and its terms, do not apply to those\nsections when you distribute them as separate works. But when you\ndistribute the same sections as part of a whole which is a work based\non the Program, the distribution of the whole must be on the terms of\nthis License, whose permissions for other licensees extend to the\nentire whole, and thus to each and every part regardless of who wrote it.\n\nThus, it is not the intent of this section to claim rights or contest\nyour rights to work written entirely by you; rather, the intent is to\nexercise the right to control the distribution of derivative or\ncollective works based on the Program.\n\nIn addition, mere aggregation of another work not based on the Program\nwith the Program (or with a work based on the Program) on a volume of\na storage or distribution medium does not bring the other work under\nthe scope of this License.\n\n 3. You may copy and distribute the Program (or a work based on it,\nunder Section 2) in object code or executable form under the terms of\nSections 1 and 2 above provided that you also do one of the following:\n\n a) Accompany it with the complete corresponding machine-readable\n source code, which must be distributed under the terms of Sections\n 1 and 2 above on a medium customarily used for software interchange; or,\n\n b) Accompany it with a written offer, valid for at least three\n years, to give any third party, for a charge no more than your\n cost of physically performing source distribution, a complete\n machine-readable copy of the corresponding source code, to be\n distributed under the terms of Sections 1 and 2 above on a medium\n customarily used for software interchange; or,\n\n c) Accompany it with the information you received as to the offer\n to distribute corresponding source code. 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Any attempt\notherwise to copy, modify, sublicense or distribute the Program is\nvoid, and will automatically terminate your rights under this License.\nHowever, parties who have received copies, or rights, from you under\nthis License will not have their licenses terminated so long as such\nparties remain in full compliance.\n\n 5. You are not required to accept this License, since you have not\nsigned it. However, nothing else grants you permission to modify or\ndistribute the Program or its derivative works. These actions are\nprohibited by law if you do not accept this License. Therefore, by\nmodifying or distributing the Program (or any work based on the\nProgram), you indicate your acceptance of this License to do so, and\nall its terms and conditions for copying, distributing or modifying\nthe Program or works based on it.\n\n 6. Each time you redistribute the Program (or any work based on the\nProgram), the recipient automatically receives a license from the\noriginal licensor to copy, distribute or modify the Program subject to\nthese terms and conditions. You may not impose any further\nrestrictions on the recipients' exercise of the rights granted herein.\nYou are not responsible for enforcing compliance by third parties to\nthis License.\n\n 7. If, as a consequence of a court judgment or allegation of patent\ninfringement or for any other reason (not limited to patent issues),\nconditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License. If you cannot\ndistribute so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you\nmay not distribute the Program at all. For example, if a patent\nlicense would not permit royalty-free redistribution of the Program by\nall those who receive copies directly or indirectly through you, then\nthe only way you could satisfy both it and this License would be to\nrefrain entirely from distribution of the Program.\n\nIf any portion of this section is held invalid or unenforceable under\nany particular circumstance, the balance of the section is intended to\napply and the section as a whole is intended to apply in other\ncircumstances.\n\nIt is not the purpose of this section to induce you to infringe any\npatents or other property right claims or to contest validity of any\nsuch claims; this section has the sole purpose of protecting the\nintegrity of the free software distribution system, which is\nimplemented by public license practices. Many people have made\ngenerous contributions to the wide range of software distributed\nthrough that system in reliance on consistent application of that\nsystem; it is up to the author/donor to decide if he or she is willing\nto distribute software through any other system and a licensee cannot\nimpose that choice.\n\nThis section is intended to make thoroughly clear what is believed to\nbe a consequence of the rest of this License.\n\n 8. If the distribution and/or use of the Program is restricted in\ncertain countries either by patents or by copyrighted interfaces, the\noriginal copyright holder who places the Program under this License\nmay add an explicit geographical distribution limitation excluding\nthose countries, so that distribution is permitted only in or among\ncountries not thus excluded. In such case, this License incorporates\nthe limitation as if written in the body of this License.\n\n 9. The Free Software Foundation may publish revised and/or new versions\nof the General Public License from time to time. Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\nEach version is given a distinguishing version number. If the Program\nspecifies a version number of this License which applies to it and \"any\nlater version\", you have the option of following the terms and conditions\neither of that version or of any later version published by the Free\nSoftware Foundation. If the Program does not specify a version number of\nthis License, you may choose any version ever published by the Free Software\nFoundation.\n\n 10. If you wish to incorporate parts of the Program into other free\nprograms whose distribution conditions are different, write to the author\nto ask for permission. For software which is copyrighted by the Free\nSoftware Foundation, write to the Free Software Foundation; we sometimes\nmake exceptions for this. Our decision will be guided by the two goals\nof preserving the free status of all derivatives of our free software and\nof promoting the sharing and reuse of software generally.\n\n NO WARRANTY\n\n 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY\nFOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN\nOTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\nPROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\nOR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS\nTO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE\nPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\nREPAIR OR CORRECTION.\n\n 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR\nREDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,\nINCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING\nOUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED\nTO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY\nYOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER\nPROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGES.\n\n END OF TERMS AND CONDITIONS\n\n How to Apply These Terms to Your New Programs\n\n If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n To do so, attach the following notices to the program. It is safest\nto attach them to the start of each source file to most effectively\nconvey the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n {description}\n Copyright (C) {year} {fullname}\n\n This program is free software; you can redistribute it and/or modify\n it under the terms of the GNU General Public License as published by\n the Free Software Foundation; either version 2 of the License, or\n (at your option) any later version.\n\n This program is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n GNU General Public License for more details.\n\n You should have received a copy of the GNU General Public License along\n with this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n\nAlso add information on how to contact you by electronic and paper mail.\n\nIf the program is interactive, make it output a short notice like this\nwhen it starts in an interactive mode:\n\n Gnomovision version 69, Copyright (C) year name of author\n Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n This is free software, and you are welcome to redistribute it\n under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License. Of course, the commands you use may\nbe called something other than `show w' and `show c'; they could even be\nmouse-clicks or menu items--whatever suits your program.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the program, if\nnecessary. Here is a sample; alter the names:\n\n Yoyodyne, Inc., hereby disclaims all copyright interest in the program\n `Gnomovision' (which makes passes at compilers) written by James Hacker.\n\n {signature of Ty Coon}, 1 April 1989\n Ty Coon, President of Vice\n\nThis General Public License does not permit incorporating your program into\nproprietary programs. If your program is a subroutine library, you may\nconsider it more useful to permit linking proprietary applications with the\nlibrary. If this is what you want to do, use the GNU Lesser General\nPublic License instead of this License." }, { "path": "Makefile", "content": "SHELL:=/bin/bash -O extglob\nRACK_DIR ?= ../..\n\nFLAGS += \\\n\t-Isrc \\\n\t-Isrc/common \\\n\t-Isrc/common/core \\\n\t-Isrc/common/util \\\n\t-Isrc/common/widgets \\\n\t-Isrc/common/core/GridConnection \\\n\t-Isrc/virtualgrid \\\n\t-Isrc/whitewhale \\\n\t-Isrc/meadowphysics \\\n\t-Isrc/earthsea \\\n\t-Isrc/teletype \\\n\t-Isrc/ansible \\\n\t-Isrc/faderbank \\\n\t-Ilib/base64 \\\n\t-Ilib/oscpack \\\n\t-Ilib/serialosc \\\n\t-Ilib/simple-svg \\\n\t-Ifirmware/mock_hardware \\\n\t-g \\\n\nCFLAGS +=\nCXXFLAGS += \nLDFLAGS +=\n\nSOURCES += \\\n\tlib/base64/base64.cpp \\\n\t$(wildcard lib/oscpack/ip/*.cpp) \\\n\t$(wildcard lib/oscpack/osc/*.cpp) \\\n\t$(wildcard lib/serialosc/*.cpp) \\\n\t$(wildcard src/*.cpp) \\\n\t$(wildcard src/**/*.cpp) \\\n\t$(wildcard src/**/**/*.cpp) \\\n\t$(wildcard src/**/**/**/*.cpp) \\\n\ninclude $(RACK_DIR)/arch.mk\n\nifeq ($(ARCH_WIN), 1)\n\tSOURCES += $(wildcard lib/oscpack/ip/win32/*.cpp) \n\tLDFLAGS += -lws2_32 -lwinmm -lopengl32\nelse\n\tSOURCES += $(wildcard lib/oscpack/ip/posix/*.cpp) \nendif\n\n# Dependencies\nragel := dep/bin/ragel\nDEPS += $(ragel)\n\n$(ragel):\n\t$(WGET) http://www.colm.net/files/ragel/ragel-6.10.tar.gz\n\tcd dep && $(UNTAR) ../ragel-6.10.tar.gz\n\t# Temporarily override the cross-compilation build flags to build ragel on build host (since we don't want to cross-compile it).\n\tcd dep/ragel-6.10 && CC=gcc CXX=g++ STRIP=strip FLAGS= CFLAGS= CXXFLAGS= LDFLAGS= ./configure --prefix=\"$(DEP_PATH)\"\n\tcd dep/ragel-6.10 && $(MAKE) && $(MAKE) install\n\nfirmware-build: export PATH := $(PWD)/dep/bin:$(PATH)\nfirmware-build: export RACK_DIR := $(realpath $(RACK_DIR))\nfirmware-build:\n\tcd firmware && $(MAKE) -f whitewhale.mk TARGET_NAME=whitewhale GIT_VERSION=\"v1.5 6CD668C\"\n\tcd firmware && $(MAKE) -f whitewhale.mk TARGET_NAME=whitewhale-kria GIT_VERSION=\"v0.4 1E0E2FB\"\n\tcd firmware && $(MAKE) -f meadowphysics.mk GIT_VERSION=\"v2.1 39A2139\"\n\tcd firmware && $(MAKE) -f earthsea.mk GIT_VERSION=\"v1.9.4 4B88B2E\"\n\tcd firmware && $(MAKE) -f ansible.mk GIT_VERSION=\"v1.5.0 6EEF788\"\n\tcd firmware && $(MAKE) -f teletype.mk TARGET_NAME=teletype4 GIT_VERSION=\"v4.0.0 A34DA87\"\n\tcd firmware && $(MAKE) -f teletype.mk TARGET_NAME=teletype5 GIT_VERSION=\"v5.0.0 00F5FD2\"\n\nfirmware-clean:\n\trm -fv res/firmware/*.dll\n\trm -fv res/firmware/*.dylib\n\trm -fv res/firmware/*.so\n\nDISTRIBUTABLES += $(wildcard res)\nDISTRIBUTABLES += $(wildcard LICENSE*)\nDISTRIBUTABLES += $(wildcard presets)\n\ninclude $(RACK_DIR)/plugin.mk\n\nall: firmware-build\n\nclean: firmware-clean\n" }, { "path": "README.md", "content": "monome-rack \n---\n\nRead the manual here:\n* https://dewb.github.io/monome-rack\n\nmonome-rack is a plugin for the [VCVRack open-source virtual modular synthesizer](https://github.com/VCVRack/Rack) that emulates (some of) the open-source Eurorack modules and control hardware designed and manufactured by [monome](https://monome.org). This is an unofficial community-driven port, made with permission, but no support guarantees, warranties, or suitability for purpose are provided by anyone.\n\n\"monome\n\nThis plugin currently includes:\n* [teletype](https://monome.org/docs/teletype/), a dynamic, musical, scriptable event triggering platform.\n* [ansible](https://monome.org/docs/ansible/), a multi-mode sequencing and event-triggering module\n* [white whale](https://monome.org/docs/whitewhale/), a probabilistic step sequencer\n* [meadowphysics](https://monome.org/docs/meadowphysics/), an event sequencer for polyrhythms and rule-based evolving patterns\n* [earthsea](https://monome.org/docs/earthsea/), a live keyboard that can sequence melodies and recall CV with shape memory gestures\n* Support for [monome grid](https://monome.org/docs/grid/) and [monome arc](https://monome.org/docs/arc/) hardware controllers, both current editions and older models, plus virtual versions of the grid controller within VCV Rack, in 64, 128, and 256-key flavors.\n \nAll of the modules can connect to either a virtual grid or a real hardware grid controller. ([Serialosc](https://monome.org/docs/setup/) is required to use real hardware, but no drivers are required for the virtual grids.) \n\nThrough the virtual grid, all features of each module are accessible, but some features are awkward to use without multiple fingers on a real grid. [See the manual for tips on using virtual grids](https://dewb.github.io/monome-rack/modules/grids/).\n\n## How do I use this?\n\nTo install the latest library release:\n\n1. Visit the plugin's [page in the VCV Library](https://library.vcvrack.com/monome) and click **Add**.\n2. Start VCV Rack and run **Library > Update All** to install the new modules.\n3. Restart VCV Rack.\n2. Optional: to use monome grid and arc hardware, make sure to [install serialosc](https://monome.org/docs/setup/).\n\n### Connecting modules to grids\n\n* Start VCVRack. Add a `white whale` and `grid 128` module to your patch.\n* Right-click the `white whale` module and select your virtual grid from the list of devices. It should light up.\n* If you have a hardware grid connected, right-click the module and select your hardware grid from the list. The virtual grid should go dark and your physical grid should light up.\n\n### Deeper learning and getting help\n\nSee the [online manual](https://dewb.github.io/monome-rack), specifically the [Getting Help section](https://dewb.github.io/monome-rack/help/).\n\n### Installing prerelease builds\n\nFor instructions on installing prerelease builds, see [DEVELOPING.md](DEVELOPING.md).\n\n## How can I build the source myself?\n\nSee [DEVELOPING.md](DEVELOPING.md).\n\n## Who did this? How is it licensed?\n\nSee the [Credits & License](https://dewb.github.io/monome-rack/general/credits/).\n\n## What's next?\n\nSee the [release plan](https://github.com/users/Dewb/projects/1) for the current thinking, but no promises.\n\n## Why does this exist?\n\nIn order of importance, the initial goals of this project were/are:\n\n* Provide an easier environment for developing, debugging, and testing new and improved firmware features for the monome Eurorack modules\n* Allow users of the hardware modules to practice, experiment, and/or record while away from their systems\n* Expose new users to the monome hardware/software ecosystem\n* Accelerate development of completely new grid applications\n* \"Because it was there\"\n\n## How does this work?\n\nThe firmwares for the monome modules are written in C for the AVR32 platform. ([More details here](https://github.com/monome/libavr32).) In this project, these firmware repos are built into separate C shared libraries, together with stub I/O implementations for parts of the AVR32 API. The Rack plugin will load a new copy of this firmware library into memory for each module instance you place, so statics and globals work as expected within each copy of the module.\n" }, { "path": "docs/content/extra.css", "content": ".module-image-sixhp {\n margin: 0rem 2rem 1.5rem 0rem;\n width: 9.5rem;\n height: auto;\n float: left;\n}\n\n.module-image-eighteenhp {\n margin: 0rem 2rem 1.5rem 0rem;\n width: 28rem;\n height: auto;\n}\n\n.patch-image {\n margin: 0rem;\n width: 100% !important;\n}\n\n.patch-download-link:before {\n content: \"\\01F4BE\";\n text-decoration: none;\n padding: 4px;\n}\n\n/* Adjust module image sizes on mobile screens */\n@media (max-width: 32rem) {\n .module-image-sixhp {\n width: 7.8rem !important;\n margin: 0em 1.5rem 1.25rem 0em !important;\n }\n .module-image-eighteenhp {\n width: 18rem !important;\n }\n}\n\n/* hide blinking cursor in mkdocs-terminal theme */\n.terminal-prompt::after { animation: none; -webkit-animation: none; display: none; }\n\n/* hide footer horizontal rule in mkdocs-terminal theme */\nhr { visibility: hidden; }\n\n/* make side panel hr mode subtle */\n#terminal-mkdocs-side-panel hr {\n visibility: visible !important;\n border: 1px solid lightgray !important;\n width: 3rem;\n}\n" }, { "path": "docs/content/general/connections.md", "content": "# Connecting devices\n\nAll of the modules in this plugin are designed to be used alongside with non-Eurorack control interfaces.\n\n[Earthsea](../../modules/earthsea), [Meadowphysics](../../modules/meadowphysics), [White Whale](../../modules/whitewhale) require a [hardware grid](https://monome.org/docs/grid/) or [virtual grid](../../modules/grids) to function.\n\n[Ansible](../../modules/ansible) requires either a grid or a [hardware arc](https://monome.org/docs/arc/) controller.\n\n[Teletype](../../modules/teletype) uses a [computer keyboard](../../modules/teletype/#using-the-keyboard) for its primary interface, though it can also [take advantage of grids](../../modules/teletype/#teletype-and-grids). \n\n# Making connections\n\nPlace a grid-supporting module in your patch and right-click it. You'll see a list of hardware and virtual grids at the bottom of the menu.\n\n![connection menu](../images/connection-menu.png){: style=\"width: 20em;\"}\n\nHardware grid connections require [serialosc](https://monome.org/docs/serialosc/setup/). If serialosc is installed, the version will be shown in the menu; make sure yours is 1.4.1 or later. If the serialosc service is not detected, a link to install it will be shown instead.\n\nIf you don't see any connections, place a [virtual grid module](../../modules/grids) in your patch and open the menu again.\n\n![connection menu](../images/connection-made.png){: style=\"width: 10.5em; float: left; margin: 0em 2em 1.5em 0em;\"}\n\nOnce a connection has been established, the USB port on the module will be drawn with a \"wireless connection nub.\" (The skeuomorphism of VCV Rack requires us to invent these little fictions.)\n\n# Restoring connections\n\nIf you connect another module to the same grid, it will be \"unplugged\" from the original module and the USB jack will appear empty again. To reacquire the connection, click the USB jack, and the grid will be unplugged from its current module and reassigned back to this one.\n\nIf you disconnect a hardware grid and reconnect it, the patch will remember the assignment and reconnect the grid to its last connected module, no clicks required.\n\nIf you delete a virtual grid from your patch, Undo will bring it back and restore connections. But if you don't undo, you'll have to add a new virtual grid module and connect it again from the right-click menu.\n\n# Hardware support\n\nAny devices that are compatible with [serialosc](https://monome.org/docs/serialosc/setup/) should work, including all editions of the [monome grid](https://monome.org/docs/grid/editions/). Devices without support for variable brightness will have a slightly different experience; some modules fall back to non-varibright support better than others.\n\n# Tips and tricks\n\n* The USB jack is a VCV Rack switch parameter and can be mapped to a MIDI control with [VCV MIDI-MAP](https://vcvrack.com/manual/Core#MIDI-Map) or [Stoermelder MIDI-CAT](https://github.com/stoermelder/vcvrack-packone/blob/v2/docs/MidiCat.md) in order to provide hardware control over where a grid is connected. Consult the documentation for the mapping module for detailed instructions." }, { "path": "docs/content/general/credits.md", "content": "# Credits\n\nThe original hardware and firmware projects were initiated by [@tehn](https://github.com/tehn) at [monome](https://monome.org) and grew with contributions from members of the [lines community](https://llllllll.co), including [@csboling](https://github.com/csboling), [@ngwese](https://github.com/ngwese), [@scanner-darkly](https://github.com/scanner-darkly), [@samdoshi](https://github.com/samdoshi), [@burnsauce](https://github.com/burnsauce), and many others. See the [individual upstream submodule repositories](https://github.com/Dewb/monome-rack/tree/main/firmware) for more details. \n\nThe VCVRack-specific code is a separate community effort; the above parties should not be expected to support or warranty these ports or take any blame for its imperfections. [@dewb](https://github.com/Dewb) wrote the virtual grid module, the hardware simulation layer, and the VCV module wrappers and software UX for white whale, meadowphysics, earthsea, and teletype. Advice and encouragement from the [lines community](https://llllllll.co) and the adjacent Teletype Study Group Discord was instrumental.\n\n[@dndrks](https://github.com/dndrks) contributed a wealth of material to the documentation site, including the quick-start patches.\n\n## License\n\nThe firmware code for the hardware modules are licensed under the version 2 of the GPL. Panel graphics [incorporate elements](https://github.com/monome/teletype-hardware/blob/master/teletype-panel-graphic.pdf) of hardware panel PDFs licensed CC-BY-SA 3.0. \n\nFull source for the plugin is available at [https://github.com/Dewb/monome-rack](https://github.com/Dewb/monome-rack). The new code in this repository is also licensed under [version 2 of the GPL](https://github.com/Dewb/monome-rack/blob/main/LICENSE).\n\nThis project benefits from the inclusion of the following source libraries:\n\n* [base64](https://github.com/ReneNyffenegger/cpp-base64) by René Nyffenegger [License](https://github.com/Dewb/monome-rack/blob/main/lib/base64/LICENSE)\n* [simple-svg](https://github.com/adishavit/simple-svg) by adishavit [License](https://github.com/Dewb/monome-rack/blob/main/lib/simple-svg/LICENSE)\n* [oscpack](https://github.com/RossBencina/oscpack) by Ross Bencina [License](https://github.com/Dewb/monome-rack/blob/main/lib/oscpack/LICENSE)\n* [serialosc_example](https://github.com/daniel-bytes/serialosc_example) by Daniel Battaglia\n\nNaturally, this project wouldn't exist without the [VCV Rack SDK](https://github.com/VCVRack/Rack) and the [many open-source libraries](https://github.com/vcvrack/rack#software-libraries) that it depends on.\n" }, { "path": "docs/content/general/intro.md", "content": "# monome for VCV Rack\n\n![all modules](../images/all-modules-50.png)\n\nThis collection of modules for the [VCV Rack virtual modular synthesizer](https://vcvrack.com/rack) provides software ports of five digital hardware modules from [monome](https://monome.org).\n\nIt was made with the intention of representing the hardware versions as faithfully as possible within the constraints of the software environment.\n\nThese are deep, multi-modal sequencers and event generators. This documentation is intended as a reference and getting-started guide for using\nthese software ports in VCV Rack; for further study consulting the [original hardware documentation](https://monome.org/docs/) is essential.\n\nRead the [credits](../credits).\n\nGet the latest version of the plugin from the [VCV Rack Library](https://library.vcvrack.com/). Older versions and changelogs are available on the [GitHub Releases page](https://github.com/Dewb/monome-rack/releases).\n" }, { "path": "docs/content/general/voltage.md", "content": "# Voltage Standards: Inputs\n\nTrigger/gate inputs use [Schmitt triggers](https://vcvrack.com/manual/VoltageStandards#Triggers-and-Gates) with a low threshold of **0.8 V** and a high threshold of **2.21 V**, roughly matching observations on the hardware.\n\nCV inputs respond to a **0-10 V** range. To mimic the hardware behavior, CV inputs are internally sampled to 12 bits of resolution.\n\n# Outputs\n\nTR outs produce a gate or trigger at **8 V**, with pulse length dependent on the application. \n\nLike inputs, CV ouputs are unipolar with a range of **0-10 V**, and are produced by simulating 12-bit DAC conversion. In order to minimize the average error introduced by the 12-bit DAC simulation, outputs will have a small and harmless offset at 0V.\n\n# Timing\n\nAll of these modules produce control-rate modulation signals. Downsampling is enabled by default to save CPU. The amount of downsampling can be changed on a module-by-module basis by right-clicking the module and choosing **Firmware Tools > Input Rate** or **Output Rate**, ranging from **1x** (no downsampling, audio rate) to **/16** (the module ticks only every 16 samples.)\n\nThere's generally no benefit to reducing the downsampling and running at audio rate. Most modules process their internal event loops at much less than audio rate regardless of the downsampling setting. The one exception: [Teletype trigger inputs](modules/teletype/#trigger-inputs) will be responded to immediately on the sample they are triggered, so Teletype can theoretically be used for rudimentary audio synthesis if you trigger it at audio rates.\n\n# Sequencer Reset\n\nThe [VCV Rack voltage standards for sequencer timing](https://vcvrack.com/manual/VoltageStandards#Timing) describe the challenges in implementing a reset input when the reset and clock inputs might arrive on different samples. Ansible is the only module with a reset input, and rather than the Rack suggested fix, it implements the alternate \"Nord reset protocol\" strategy, where only clock triggers ever advance the clock, and a low-high transition on the reset input causes the sequence to reset on the next clock step. If a patch does not produce the expected reset behavior due to different propagation times on the clock and reset input, add logic delays to make sure your reset signal arrives *before* the clock signal.\n\n# Polyphony\n\nAll modules only carry monophonic signals on each jack, like their physical counterparts. If a polyphonic Rack cable is connected to an input, only the first channel will be used.\n\nHowever, in many modes the modules can be used to create polyphonic signals and sequences across several outputs. For polyphonic downstream patching, you can use the [VCV Merge](https://vcvrack.com/Fundamental#Split) module to combine multiple CV or TR outs from a single module into a single polyphonic cable. For example, when using the [Kria](https://monome.org/docs/ansible/kria/) app on [Ansible](../../modules/ansible), patching CV 1-4 into one Merge module and TR 1-4 into another Merge module would give you polyphonic CV and gate signals to control polyphonic VCOs and VCAs." }, { "path": "docs/content/help.md", "content": "# Learning resources\n\nThe official documentation for the original hardware versions of the modules is the best place to get in-depth information about how they work.\n\n * [ansible](https://monome.org/docs/ansible/)\n * [teletype](https://monome.org/docs/teletype/) + [manual](https://monome.org/docs/teletype/manual) + [command cheatsheet](https://monome.org/docs/teletype/TT_commands_4.0.pdf) + [teletype studies](https://monome.org/docs/teletype/studies-1/)\n * [earthsea](https://monome.org/docs/earthsea/)\n * [meadowphysics](https://monome.org/docs/meadowphysics/)\n * [white whale](https://monome.org/docs/whitewhale/)\n\nSee the \"Further reading\" and \"Tutorial videos\" sections for each module for additional learning material.\n\n# Communities of practice\n\n[//////// aka Lines](https://llllllll.co) is a nice place to discuss music making and music making tools and making tools for music. There is a [Lines thread on this plugin](https://llllllll.co/t/monome-vcv-rack-ports-development-log/10337). Some excellent and relevant lines threads include:\n\n * [a user's guide to the wonderful world of teletype](https://llllllll.co/t/a-users-guide-to-the-wonderful-world-of-teletype/35971)\n * [how do you use your ansible?](https://llllllll.co/t/how-do-you-use-your-ansible/46846/)\n * [kria strategies](https://llllllll.co/t/kria-strategies/17671)\n\nCheck out the recordings of past [flash crash livecoding events](https://flashcrash.net/) for examples of teletype in live performance.\n\n[The VCV Community Forum](https://community.vcvrack.com) is a community of VCV Rack users and module developers of all experience levels. [There is a thread for discussion of these modules there as well](https://community.vcvrack.com/t/monome-modules-beta-dev-log/3683).\n\n# Development information\n\nFor guides to building the plugin from scratch, or using the plugin as a development environment for changes to the module firmware, [see DEVELOPING.md on GitHub](https://github.com/Dewb/monome-rack/blob/main/DEVELOPING.md).\n\n# Reporting bugs\n\n[Create a new issue on GitHub here](https://github.com/Dewb/monome-rack/issues/new/choose). Choose the template that matches your situation, and be sure to fill in all the requested information. Thank you! Clear and complete bug reports are a gift." }, { "path": "docs/content/index.md", "content": "\n\n##\n\n
\n \n Ansible
\n \n \n
\n\n
\n \n Earthsea
\n \n \n
\n\n
\n \n Meadowphysics
\n \n \n
\n\n
\n \n Teletype
\n \n \n
\n\n
\n \n White Whale
\n \n \n
\n\n
\n \n Virtual Grids
\n \n \n
\n\n
\n \n Faderbank
\n \n \n
\n\n##\n\n[Introduction to the collection](general/intro)" }, { "path": "docs/content/modules/ansible.md", "content": "![ansible module screenshot](../images/ansible.png){: class=\"module-image-sixhp\" }\n## Ansible\n\nAnsible has multiple modes that change the personality and functions of the module. To select a mode, first [connect the module](../../general/connections) to a hardware or virtual grid, or a hardware arc controller. Different modes are available depending on whether the module is connected to a grid or arc.\n\n[Read the introduction to the hardware module](http://monome.org/docs/ansible/#basics).\n\nOnly one mode runs at a time, but you can disconnect a device and the previously active mode will continue running and responding to the panel controls and CV inputs.\n\nThe modes, each of which has its own detailed manual, are [Kria](https://monome.org/docs/ansible/kria/), [Meadowphysics](https://monome.org/docs/ansible/meadowphysics/), [Earthsea](https://monome.org/docs/ansible/earthsea/), [Cycles](https://monome.org/docs/ansible/cycles/), and [Levels](https://monome.org/docs/ansible/levels/). VCV Rack Ansible does not currently support the MIDI or Teletype Expander modes present on the hardware version.\n\nEarthsea and Meadowphysics are similar to their standalone versions, with some key differences. Ansible Meadowphysics has the ability to produce continuous voltages instead of just gates; Ansible's version of Earthsea drops the shape memory CV feature but adds four-voice polyphony.\n\nThe bottom left key is the **MODE** key. A short press in any app will bring up the Preset view ([grid version](https://monome.org/docs/ansible/kria/#presets), [arc version](https://monome.org/docs/ansible/cycles/#presets)). A long press will rotate through the modes available with your currently connected device. The LED next to it indicates which mode is currently active:\n\n| Mode LED color | Grid | Arc |\n|------------------|------------|---------|\n| Yellow-orange | [Kria](https://monome.org/docs/ansible/kria/) | [Levels](https://monome.org/docs/ansible/levels/) |\n| White | [Meadowphysics](https://monome.org/docs/ansible/meadowphysics/) | [Cycles](https://monome.org/docs/ansible/cycles/) |\n| Yellow-white | [Earthsea](https://monome.org/docs/ansible/earthsea/) | n/a |\n\n\n# Outputs\n\nEach Ansible mode produces four trigger/gate outputs from **TR 1-4** on the left side of the module, and four CV outputs on **CV 1-4** on the right side. TR outputs are 0 V low, 8 V high, and CV outputs range from 0-10 V.\n\n# KEY 1 & KEY 2\n\nThe two keys above the IN jacks have different functions depending on the mode and on whether you short-tap the buttons or long-hold them. To hold a button in VCV Rack using the mouse, Ctrl-click (Cmd-click on Mac) to lock them down so you can use the mouse for other things.\n\n| mode | KEY 1 | KEY 2 |\n|---------------|--------------|---------------------|\n| [Kria](https://monome.org/docs/ansible/kria/) | Time View (long) | Config View (long) |\n| [Meadowphysics](https://monome.org/docs/ansible/meadowphysics/) | Time View (long) | Config View (long) |\n| [Earthsea](https://monome.org/docs/ansible/earthsea/) | Previous Pattern (short) | Next Pattern (short) |\n| [Cycles](https://monome.org/docs/ansible/cycles/) | Friction | Reset Pattern (short)
Config View (long) |\n| [Levels](https://monome.org/docs/ansible/levels/) | Next Pattern (short)
Pattern View (long)
Change Parameter
(short tap while in Config View) | Reset Pattern (short)
Config View (long) |\n\n# Inputs\n\nAnsible **IN 1** and **IN 2** jacks accept trigger/gate inputs. Their function depends on the active mode:\n\n| Mode | IN 1 | IN 2 |\n|---------------|--------------|---------------------|\n| [Kria](https://monome.org/docs/ansible/kria/) | Clock | Reset |\n| [Meadowphysics](https://monome.org/docs/ansible/meadowphysics/) | Clock | Reset |\n| [Earthsea](https://monome.org/docs/ansible/earthsea/) | Clock | Start/reset pattern |\n| [Cycles](https://monome.org/docs/ansible/cycles/) | Add friction | IN 1 unconnected: Reset
IN 1 connected: Add force |\n| [Levels](https://monome.org/docs/ansible/levels/) | Clock | Reset |\n\n# Quickstart\n\nAll of these quickstart examples use Ansible alongside modules from VCV's [Free collection](https://vcvrack.com/Free).\n\n**Kria**\n\n![ansible kria quickstart screenshot](../images/ansible-kria-quickstart.png){: class=\"patch-image\" }\n*uses: Ansible, ADSR, VCA, VCO, AUDIO*\n\n[ansible-kria-quickstart.vcv](../patches/ansible-kria-quickstart.vcv){: class=\"patch-download-link\" }\n\n- Connect Ansible to a grid. (See [Making Connections](../../general/connections/#making-connections).)\n- The LED next to the **MODE** key should be *yellow-orange*. If it isn't, hold + release the **MODE** key to cycle through modes until Kria is active.\n- Patch **TR 1** to the GATE input of ADSR.\n- Patch **CV 1** to the V/OCT input of VCO.\n- Patch **CV 2** to the PWM input of VCO and add modulation using the attenuator.\n- Patch ADSR's ENV and VCO's SQR to a VCA, then to AUDIO's L input.\n- Press some pads in Kria's top row to create a rhythm on **TR 1**.\n- Switch to the NOTE page on the grid by pressing the 7th key on the bottom row, and set notes for **CV 1**.\n- Switch to Track 2 on the grid by pressing the 2nd key on the bottom row, and set notes for **CV 2**'s modulation of the VCO's pulse width.\n- Switch to the OCTAVE page on the grid by pressing the 8th key on the bottom row, and set different octaves for **CV 2**'s steps.\n\n**Meadowphysics**\n\n![ansible meadowphysics quickstart screenshot](../images/ansible-meadowphysics-quickstart.png){: class=\"patch-image\" }\n*uses: Ansible, ADSR, VCA, VCO, AUDIO*\n\n[ansible-meadowphysics-quickstart.vcv](../patches/ansible-meadowphysics-quickstart.vcv){: class=\"patch-download-link\" }\n\n- Connect Ansible to a grid. (See [Making Connections](../../general/connections/#making-connections).)\n- Hold + release the **MODE** key to move from Kria to Meadowphysics. The LED next to the **MODE** key should be *white*.\n- Ctrl-Shift-click (Cmd-Shift-click on Mac) **KEY 2** on Ansible's faceplate to open the [config interface](https://monome.org/docs/ansible/meadowphysics/#config).\n- Set the *voice mode* to *2 CV/TR voices*.\n- Patch **TR 1** to the GATE input of ADSR.\n- Patch **CV 1** to the V/OCT input of VCO.\n- Patch **CV 2** to the PWM input of VCO and add modulation using the attenuator.\n- Patch ADSR's ENV and VCO's SQR to a VCA, then to AUDIO's L input.\n- Hold down any pad outside of column 1 in any row and press another pad in the same row to create a [count range](https://monome.org/docs/ansible/meadowphysics/#basic) -- if you're using a virtual grid, Ctrl-click (Cmd-click on Mac) will hold a pressed pad until you release Ctrl / Cmd.\n\n**Earthsea**\n\n![ansible earthsea quickstart screenshot](../images/ansible-earthsea-quickstart.png){: class=\"patch-image\" }\n*uses: Ansible, ADSR (2x), VCO (2x), VCA MIX, AUDIO*\n\n[ansible-earthsea-quickstart.vcv](../patches/ansible-earthsea-quickstart.vcv){: class=\"patch-download-link\" }\n\n- Connect Ansible to a grid. (See [Making Connections](../../general/connections/#making-connections).)\n- Hold + release the **MODE** key to move from Kria to Meadowphysics and then Earthsea. The LED next to the **MODE** key should be *yellow-white*.\n- Hold the bottom-left pad on the grid to enter the [voice allocation interface](https://monome.org/docs/ansible/earthsea/#voice-allocation) and set the first two outputs to active on both *pattern* and *live*.\n- Instantiate two ADSR and two VCO modules.\n- Set one of the VCO's FREQ to 1/2 the FREQ of the other.\n- Patch **TR 1** and **TR 2** to the GATE input of each ADSR.\n- Patch **CV 1** and **CV 2** to the V/OCT input of each VCO.\n- Patch one output of each VCO to the first two inputs of VCA MIX.\n- Patch each ADSR's ENV output to the corresponding CV inputs of VCA MIX.\n- Patch the VCA MIX's MIX output to AUDIO's L input.\n- [Arm a pattern recorder](https://monome.org/docs/ansible/earthsea/#pattern-recording) by pressing the key in the third row of the leftmost column.\n- Record some chord shapes on the grid. Hit the pattern record arm key again to stop recording and play the pattern back.\n\n# Grid reference\n\nWhen using Kria, the bottom row of the grid controls the track/mode/view, and is consistent across modes (with a couple of exceptions.) The rest of the grid contents depend on the mode you're in. See [the hardware documentation](https://monome.org/docs/ansible/kria/) for more details.\n\n![ansible kria grid legend screenshot](../images/ansible-kria-grid-legend.png){: class=\"patch-image\" }\n\n[ansible-kria-grid-legend.vcv](../patches/ansible-kria-grid-legend.vcv){: class=\"patch-download-link\" } *(requires [Stoermelder Glue](https://library.vcvrack.com/Stoermelder-P1))*\n\nFor Meadowphysics, see the [grid legends for standalone Meadowphysics](../meadowphysics/#grid-reference).\n\nFor Earthsea, see the [grid legend for standalone Earthsea](../earthsea/#grid-reference). Ansible Earthsea is identical except the last two functions, Slew and Portamento, are replaced by the [Runes](https://monome.org/docs/ansible/earthsea/#runes) and [Voice Allocation](https://monome.org/docs/ansible/earthsea/#voice-allocation) screens.\n\n# Further reading\n\n* Ansible [hardware documentation](http://monome.org/docs/ansible/)\n* [Kria tutorial](https://llllllll.co/t/monome-ansible-kria-in-depth-overview-and-tutorial/34821) by [Puscha](https://puscha.bandcamp.com/)\n* [Kria strategies](https://llllllll.co/t/kria-strategies/17671)\n* [\"ansible\" search on llllllll.co](https://llllllll.co/search?q=ansible)" }, { "path": "docs/content/modules/earthsea.md", "content": "![earthsea module screenshot](../images/earthsea.png){: class=\"module-image-sixhp\" }\n## Earthsea\n\nEarthsea, [connected to a grid controller](../../general/connections), is an isomorphic keyboard and sequencer. \n\nWithout a grid connection it will not produce any output, but once a sequence has been played and recorded, you can disconnect the grid and the sequence will continue playing.\n\n[Read the introduction to the hardware module](http://monome.org/docs/earthsea/#introduction).\n\n# CV 1-3 knobs and outputs\n\nThe **CV 1-3** jacks each output a 0 V to 10 V signal that is initially controlled by the paired knob. When using a [shape memory gesture](https://monome.org/docs/earthsea/#shape-memories) on the grid, the previously stored CV values will be recalled, subject to the [slew settings](https://monome.org/docs/earthsea/#slew). These values are also displayed on the bottom three rows of a connected grid.\n\n# EDGE and POS outputs\n\n**EDGE** produces an 8 V gate when a note event is triggered, either by playing the keyboard or playing back a sequence. \n**POS** outputs a pitch CV from 0 V to 10 V corresponding to the scale position of the note being played.\n\n# Inputs\n\nEarthsea does not have any inputs.\n\n# Grid reference\n\nEarthsea uses the leftmost column for mode controls, leaving the entire rest of the grid as a playing surface (called the *keymap*.) Notes in the keymap are arranged by semitones on the x-axis and by fourths on the y-axis. The most recently played key is highlighted; the pitch of this key will be present on the *POS* output in V/oct format.\n\nVarious forms of information are shown on the grid as horizontal bars underneath the keymap. When the sequencer is playing, the top row will display the progress of the loop. The bottom three rows show the current value of CV 1-3.\n\n![earthsea grid legend screenshot](../images/earthsea-grid-legend.png){: class=\"patch-image\" }\n\n[earthsea-grid-legend.vcv](../patches/earthsea-grid-legend.vcv){: class=\"patch-download-link\" } *(requires [Stoermelder Glue](https://library.vcvrack.com/Stoermelder-P1))*\n\n# Quickstart\n\nThis quickstart example uses Earthsea alongside modules from VCV's [Free collection](https://vcvrack.com/Free).\n\n![earthsea quickstart screenshot](../images/earthsea-quickstart.png){: class=\"patch-image\" }\n*uses: Earthsea, ADSR, VCO, VCF, VCA MIX, AUDIO*\n\n[earthsea-quickstart.vcv](../patches/earthsea-quickstart.vcv){: class=\"patch-download-link\" }\n\n- Connect Earthsea to a grid. (See [Making Connections](../../general/connections/#making-connections).)\n- Patch Earthsea's **EDGE** output to ADSR's GATE input.\n- Patch Earthsea's **POS** output to VCO's V/OCT input.\n- Patch VCO's SQR output to VCF's IN.\n- Patch VCF's LPF output to IN 1 of VCA MIX.\n- Patch ADSR's ENV output to CV 1 of VCA MIX.\n- Patch VCA MIX's MIX output to AUDIO's L input.\n- Patch Earthsea's **CV 1** output to the PWM input of VCO and add modulation using the attenuator above the input.\n- Patch Earthsea's **CV 2** output to the CUT input of VCF and add modulation using the attenuator above the input.\n- [Arm a pattern recorder](https://monome.org/docs/earthsea/#patterns) by pressing the key in the third row of the first column. Record a melody by pressing keys on the grid in columns 2-16. Hit the third key in the first column again to start playing the pattern back.\n\nIf you have a hardware grid and can make simultaneous multi-finger gestures, you can try the shape memory feature:\n\n- Add voltage to Earthsea's **CV 1** and **CV 2** by turning their knobs clockwise, and perform a [shape-memory gesture](https://monome.org/docs/earthsea/#shape-memories) to store those settings and start editing the new shape.\n- Repeat the previous step for additional values and **triples** *shape-memories*.\n- As the pattern plays, switch between *shape-memories*.\n- [Add slew to a shape memory CV channel](https://monome.org/docs/earthsea/#slew) by holding down the 7th key in the first column and turning the CV 1 knob.\n\n# Further reading\n\n* Earthsea [hardware documentation](http://monome.org/docs/earthsea/)\n* [\"earthsea\" search on llllllll.co](https://llllllll.co/search?q=earthsea)\n\n# Video tutorials\n\n* [Earthsea introduction](https://vimeo.com/113231441)\n" }, { "path": "docs/content/modules/faderbank.md", "content": "##\n\n![faderbank module screenshot](../images/faderbank.png){: class=\"module-image-eighteenhp\" }\n\n## Faderbank\n\nThe faderbank module is a virtual control surface inspired by the open source [16n-faderbank hardware controller](https://16n-faderbank.github.io). The 16n was developed by Brian Crabtree, Sean Hellfritsch, Tom Armitage, and Brendon Cassidy.\n\nAt heart it's simple: sixteen faders, with 16 CV outputs. Output ranges are selectable from 0-10V, 0-5V, or +/-5V from the right-click menu.\n\nThis virtual version has two reasons for existing: to provide extra parameter inputs as an expander to Teletype, and to make it easy to use the 16n-faderbank and compatible hardware with VCV Rack.\n\n# Using with 16n hardware\n\nPlug in your faderbank via USB. Right-click the module and hover over the **MIDI connection** submenu. Select your driver and the 16n device. \n\nIf your 16n is set to use the default CC and channel mappings (CCs 32-47 on channel 1) then you're all set.\n\nIf your 16n has a custom configuration, right-click the module again and select the **Autodetect 16n configuration** command. Rack will interrogate the 16n via sysex and configure the virtual faders to respond to the configured MIDI events.\n\nThis command also has the side effect of requesting a CC update from every fader, so you can use it to bring the virtual and hardware faders back in sync after the controller has been disconnected.\n\nIf you are not connected to a device that responds to 16n sysex, then **Autodetect 16n configuration** will reset the MIDI mapping to the default (CCs 32-47 on channel 1.)\n\n# Using with non-16n hardware\n\nYou can also use the module with another MIDI controller. If you can configure your MIDI controller to use CC numbers 32-47 on channel 1, then you can connect it via the right-click menu on the module just like a 16n.\n\nIf you cannot configure your MIDI controller to use CC 32-47, then you can map the faders individually the normal way using the VCV Core [MIDI-Map](https://vcvrack.com/manual/Core#MIDI-Map) module.\n\n# Using with Teletype\n\nWhen a faderbank is placed immediately next to Teletype, it serves as a param expander. The fader values (0-16383) are available with the `FADER` op (or `FB` for short.) The voltage range option has no effect on the digital values seen by Teletype.\n\n`FADER.SCALE` is also helpful -- see the [teletype manual](https://monome.org/docs/teletype/manual/#n) for more details on using the faderbank OPs.\n\nTeletype 4.0 only supports a single faderbank (faders 1-16). Teletype 5.0 supports up to four separate devices (faders 1-64). \n\nMultiple connected faderbanks are addressed in order from left to right, on either side of Teletype. If you have more than four in a row, the fifth and subsequent faderbank modules will be ignored. If more than one Teletype module adjoins a set of adjacent faderbanks, the fader values will be available to both Teletype instances.\n\nFor example, here's a script to copy values from two faderbanks into slots 0-15 of tracker patterns 0 and 1. Put this in `M` and set `M 20` in LIVE mode.\n\n```\nL 0 15: PN 0 I FB + I 1\nL 0 15: PN 1 I FB + I 17\n```\n\n# Using with Stoermelder Glue\n\nRight click the module and change **Fader length** to 60mm in order to free up some space for resting your wrists, and/or for applying labels using [Stoermelder Glue](https://library.vcvrack.com/Stoermelder-P1/Glue), so you don't forget what the faders are connected to.\n\n![faderbank and Glue screenshot](../images/faderbank-glue.png)\n\n# Polyphonic mode\n\nRight-click the module and check **Polyphonic mode** to convert the #16 output into a polyphonic output that contains all 16 fader voltages on one cable.\n\n# Further reading\n\n* [16n-faderbank website](https://16n-faderbank.github.io)\n* [16n-faderbank GitHub repository](https://github.com/16n-faderbank/16n)\n* [16n is a bank of faders](https://llllllll.co/t/16n-is-a-bank-of-faders-release-thread/18620) lines thread\n* [\"16n\" search on llllllll.co](https://llllllll.co/search?q=16n)\n" }, { "path": "docs/content/modules/grids.md", "content": "# Virtual grids\n\n![original prototype virtual grid in VCV Rack 0.5](../images/prototype.jpg)\n\n# Sizes\n\nVirtual grids come in 64 (8x8), 128 (16x8), and 256 (16x16) key flavors. Most modules and modes are designed for the 128-key version, though all will work with every size; some features may not be available or might not work exactly the same way on the other sizes.\n\n# Limitations vs. hardware\n\nThe virtual grids are something of a compromise. They're never going to be as performable or tactile as a physical controller. \n\nUsing all features of these grid-supporting modules relies on gestures intended to be performed with two hands. Unfortunately, VCV Rack doesn't currently support multi-touch, so with a mouse alone you can only press one key at a time.\n\nHowever, using the mouse and computer keyboard together, we can approximate some multi-handed gestures.\n\n# Holding keys\n\nTo compensate for only having one pointer finger instead of ten, you can Ctrl-click keys (or Cmd-click on Mac) to hold them down momentarily. You can hold multiple grid keys while you hold down Ctrl (or Cmd) and all the held grid keys will be released when you stop holding it.\n\nThis is handy for typical gestures like [setting the loop length on White Whale](http://monome.org/docs/whitewhale/#position--clock). Ctrl-click a key in row 2 to set the loop start, and then while still holding Ctrl, click another key in row 2 to set the end point.\n\n![ctrl-clicking keys to set white whale loop length](../images/whitewhale-ctrl-click.webp){: }\n\n# Locking keys\n\nSometimes you need to hold a key down for a longer period of time. Ctrl-Shift-click a grid key (Cmd-Shift-click on Mac) to \"lock\" it down until you click it again. If you lock multiple keys, you can release them all at once by hitting Esc while hovering over the grid, or selecting **Release Locked Keys** from the right-click menu.\n\nLocked keys are indicated by a dot in the lower left corner. \n\nLocking a key allows you to use mode/settings pages, where you might need to hold a key down while pressing several other keys. For example, to enter [Edge Mode](http://monome.org/docs/earthsea/#edge) on [Earthsea](../modules/earthsea), Ctrl-Shift-click the 6th key in the first column to enter the mode, and then click the glyphs to change the gate method and time. Click the locked key again to unlock it and return to the main mode.\n\n![ctrl-shift-clicking keys to lock earthsea glyph mode](../images/earthsea-ctrl-shift-click.webp){: }\n\n# Combining gestures\n\nLocking and holding keys can work together. For example, to adjust loop length in Kria, Ctrl-Shift-click the [Loop Modifier key](https://monome.org/docs/ansible/kria/#modifiers) in row 8 to edit loop lengths, then Ctrl-click the start and end of the loop in rows 1-4.\n\n![ctrl-shift-clicking to lock kria loop modifier mode, then ctrl-clicking to set loop length](../images/kria-combined-gestures.webp){: style=\"border-right: 0.2em solid #bfbfbf; border-bottom: 0.1em solid #bfbfbf;\" }\n\n# Theme and protocol options\n\nFrom the right-click menu, you can change the *Theme* of a individual grid instance to differentiate it from other grids in your patch, or just for personal style preference. The four themes are *loosely* based on the various eras of grid controller hardware. They don't have identical brightness curves and some themes may be more satisfying than others for certain modules and modes.\n\nThere is also a menu option to change the protocol the grid is simulating. This might be useful if you have an older-protocol hardware grid and you want to practice with the same non-varibright behavior on a virtual grid, or if you are developing new module firmware and want to test against older, non-varibright grids. Most users should leave this set to *Mext (varibright)*.\n\n" }, { "path": "docs/content/modules/meadowphysics.md", "content": "![meadowphysics module screenshot](../images/meadowphysics.png){: class=\"module-image-sixhp\" }\n## Meadowphysics\n\nMeadowphysics generates eight interrelated gate sequences. Without a grid connected, it will output eight gate sequences driven by the CLOCK knob or the external clock patched to the clock input. With a [grid connected](../../general/connections), the individual timing, rules, and complex triggering conditions of the sequences can be manipulated.\n\n[Read the introduction to the hardware module](http://monome.org/docs/meadowphysics/#introduction).\n\nThe trigger outputs from Meadowphysics are suitable for firing off ADSR envelopes, pinging LPGs or filters, clocking or resetting sequencers, triggering drum modules or samplers, or whatever complex events you have in your patch. Meadowphysics was originally designed as a script-triggering companion to [Teletype](../teletype), so try using them together once you're familiar with both.\n\n# Main outputs\n\nOutputs 1-8 produce gates at 8 V according to the counters on rows 1-8 of the grid. Outputs follow the pulse length of the clock; the built-in clock has a 50% duty cycle.\n\n# CLOCK knob & jacks\n\nThe **CLOCK** knob controls the timing of clock pulses that drive the counters. The knob ranges from a period of 1 second to a period of 23ms. Patching a signal into **CLOCK IN** will override the timing and [every low/high transition](../../general/voltage/#inputs) on the input will pulse the counters. Very fast clocks approaching a 1ms period may result in skipped pulses; the module will not go into audio rate.\n\nWhen an external clock is patched, the knob becomes a clock divider/multiplier, from a 1/16 division to a 16x multiplier. **CLOCK OUT** outputs the internal clock when it is active or external clock, post division/multiplication, if one is patched.\n\n# PRESET key\n\nVCV Rack will remember the current working memory in your patch, but the **PRESET** key can be used to store and recall 16 different states to the module's \"internal memory.\" Press and hold to quicksave the current state to the active slot, or short-press to [enter Preset mode](http://monome.org/docs/meadowphysics/#preset).\n\n# Quickstart\n\nThis quickstart example uses Meadowphysics alongside modules from VCV's [Free collection](https://vcvrack.com/Free). \n\n![meadowphysics quickstart screenshot](../images/meadowphysics-quickstart.png){: class=\"patch-image\" }\n*uses: Meadowphysics, VCO (2x), VCA MIX (2x), FADE, LFO, AUDIO*\n\n[meadowphysics-quickstart.vcv](../patches/meadowphysics-quickstart.vcv){: class=\"patch-download-link\" }\n\n- Connect Meadowphysics to a grid\n- Patch the four outputs of each VCO to the four inputs of each ADSR\n- Patch the eight **TR** outputs of Meadowphysics to the CV inputs of each ADSR\n- Patch the MIX outputs of each ADSR to the inputs of FADE\n- Patch any LFO output to FADE's X FADE input and add modulation using the Crossfade CV attenuator above\n- Patch the output of FADE to the L/MON input of AUDIO\n- To set a different count for each row, press any pad beyond the first column in that row\n- Hold down any pad outside of column 1 in any row and press another pad in the same row to create a [count range](https://monome.org/docs/ansible/meadowphysics/#basic)\n- Change the [rule](https://monome.org/docs/meadowphysics/#rules--ranges) for each range\n\n# Grid reference\n\n![meadowphysics grid legend screenshot](../images/meadowphysics-grid-legend.png){: class=\"patch-image\" }\n![meadowphysics grid legend links screenshot](../images/meadowphysics-grid-legend-links.png){: class=\"patch-image\" }\n![meadowphysics grid legend rules screenshot](../images/meadowphysics-grid-legend-rules.png){: class=\"patch-image\" }\n\n[meadowphysics-grid-legends.vcv](../patches/meadowphysics-grid-legends.vcv){: class=\"patch-download-link\" } *(requires [Stoermelder Glue](https://library.vcvrack.com/Stoermelder-P1))*\n\n# Further reading\n\n* Meadowphysics [hardware documentation](http://monome.org/docs/meadowphysics/)\n* [\"meadowphysics\" search on llllllll.co](https://llllllll.co/search?q=meadowphysics)\n\n# Video tutorials\n\n* [meadowphysics possibilities](https://vimeo.com/107582557)\n* [meadowphysics tutorial](https://vimeo.com/107586549)\n* [meadowphysics two](https://vimeo.com/146731772)" }, { "path": "docs/content/modules/teletype.md", "content": "##\n\n![teletype module screenshot](../images/teletype.png){: class=\"module-image-eighteenhp\" }\n\n## Teletype\n\nTeletype is a generative scripting system and sequencing toolkit designed for live coding and musical exploration. It can serve lots of roles in a patch including a simple tracker-style sequencer, a random gate processor, or a development platform for complex grid-enabled applications. It can be the brain of your entire patch, or it can just provide some custom utility glue.\n\n# Modes, Scripts, and OPs\n\nTeletype has three main modes: [LIVE](http://monome.org/docs/teletype/manual/#live-mode) mode, where commands are executed immediately, [EDIT](http://monome.org/docs/teletype/manual/#edit-mode) mode, where code is assembled into stored scripts, and [TRACKER](http://monome.org/docs/teletype/manual/#patterns) mode, where pattern data can be edited visually. Pressing the TAB key will cycle between these three main modes. \n\nScripts can be simple or intricate, but there are just ten of them, and each one is only six lines long. Scripts `1-8` are triggered by the eight trigger inputs. The ninth script, `M` for metronome, is triggered by the internal clock, and the tenth `I` script runs when a preset is loaded. Scripts can also be triggered by F1-F10 on the keyboard, or with a connected grid. Scripts can also trigger other scripts with the `SCRIPT n` operator.\n\nScripts are made up of operators or [OPs](http://monome.org/docs/teletype/manual/#ops-and-mods). *OPs* may have one or more arguments that could be numbers or the outputs of other OPs. OPs and values are combined in [prefix notation](https://en.wikipedia.org/wiki/Polish_notation). Hit Alt-H (Option-H on Mac) on the keyboard to enter **HELP** mode, an on-device reference for OPs and their arguments.\n\n# Using the keyboard\n\nTo send keyboard input to Teletype, click the screen with your mouse or trackpad. A highlight ring will be drawn around the screen to indicate keyboard focus. Keystrokes will go into Teletype instead of Rack until you click away to un-focus the screen. \n\nNote that your operating system may intercept some keyboard combinations (like Alt-Esc to enter **SCENE WRITE** mode). If that happens, Alt-Esc and other critical key combinations can also be triggered via the right-click menu.\n\nThe VCV Rack version of Teletype defers keycode processing to the firmware, so like the hardware, it operates directly on fixed USB HID scancodes. The translation of Rack keystrokes to HID keystrokes can be customized for different keyboard layouts. Right-click the module and select **Keyboard layout** to change the layout for all Teletype instances. \n\nThese layout options are defined with JSON files in your Rack2 user folder, under `Rack2/plugin--/monome/res/keymaps`. Adding or modifying files here will allow you to customize this translation process for international keyboards or other alternate layouts. [See GitHub for details](https://github.com/Dewb/monome-rack/tree/main/res/keymaps).\n\n# TRIGGER inputs\n\nEach trigger input **1-8** across the top of the module corresponds to scripts `1-8`. These respond to rising edges of voltage greater than 2.21 V, as outlined in the [Voltage Standards](../../general/voltage/). \n\n# IN jack & PARAM knob\n\nThe **IN** jack and **PARAM** knob can be used to set and replace values. Each returns a value in the range 0-16383, representing 0 V to 10 V. See [the Teletype manual](https://monome.org/docs/teletype/manual/#hardware/) for more information.\n\nThe value at **IN** can be queried using the `IN` operator. \nThe value of the **PARAM** knob can be queried using the `PARAM` operator (or `PRM` for short.)\n\n# TR 1-4 outputs\n\nTeletype has four trigger/gate outputs, **TR 1-4**. TR outputs are 0 V low, 10 V high. The `TR` operators in the [the Hardware section](https://monome.org/docs/teletype/manual/#hardware/) interact with the trigger outputs. \n\n# CV 1-4 outputs\n\nTeletype has four CV outputs, **CV 1-4**. CV outputs are 0 V low, 10 V high. The `CV` operators in the [the Hardware section](https://monome.org/docs/teletype/manual/#hardware/) interact with the CV outputs. \n\n# Saving, loading, and the SCENE key\n\nA *scene* is a complete set of scripts and patterns. The physical module can save up to 32 scenes to its flash memory, and can import and export scenes from a USB drive. The VCV Rack version will save both the current working memory of Teletype *and* up to 32 scenes in your patch. \n\nTo write a scene, press Alt + Esc (Option + Esc on Mac) or right-click Teletype and choose \"SCENE WRITE mode\". Use the bracket keys (`[` and `]`) on your keyboard to select the destination save position. Title and describe your scene, then press Alt + Esc (Option + Esc on Mac) to store it. You can write up to 32 scenes in any one virtual instance of Teletype.\n\nYou can also save the entire module state -- the active scene and all saved scenes -- for future recall, using VCV Rack's general Preset system. Right-click the Teletype module and navigate to *Preset > Save as*. This will save everything about this copy of Teletype as a single preset file under `Rack 2 > presets > monome > teletype`.\n\nTo recall a preset, right-click the Teletype module and navigate to *Preset*. You'll see your saved presets under *User presets*. The **SCENE** key at the bottom of the module allows you to quickly access the scenes stored within the loaded preset.\n\nYou can also save and load scenes as text files, which can be transferred in and out of physical Teletype modules. Right-click Teletype and you'll see *Import scenes* and *Export scenes*. These will import and export standard `.txt` files, same as those seen in the [Teletype Code Exchange](https://llllllll.co/t/teletype-code-exchange/839). From this menu you can also copy and paste scenes from the clipboard (including partial scene fragments.)\n\nSee [the Teletype manual](https://monome.org/docs/teletype/manual/#scenes) for more information about scenes.\n\n\n# Quickstart 1\n\nThis quickstart example uses Teletype alongside modules from VCV's [Free collection](https://vcvrack.com/Free).\nWe'll use Teletype's internally-clocked `M` script and as little typing as possible to start sequencing some notes.\n\n![teletype quickstart 1 screenshot](../images/teletype-quickstart-1.png){: class=\"patch-image\" }\n*uses: Teletype, VCO, ADSR, VCA, AUDIO*\n\n[teletype-quickstart-1.vcv](../patches/teletype-quickstart-1.vcv){: class=\"patch-download-link\" }\n\n- Patch Teletype's **CV 1** output to the VCO's V/8 input\n- Patch Teletype's **TR 1** output to the ADSR's GATE input\n- Patch the SAW output of the VCO to the audio input of the VCA\n- Patch the ADSR's ENV output to the CV input of the VCA \n- Patch the VCA output to the L/MON input of the AUDIO module\n- Turn down the VCO Freq knob to 32.703 Hz (or right-click the knob and type `C1`).\n- Now, click on the Teletype screen. You should see a highlight ring appear around it, signaling that Teletype has keyboard focus.\n- Hit TAB until you are in EDIT mode (there will be a script number in the lower left-hand corner) or right-click Teletype and choose `EDIT MODE`.\n- Hit the [ and ] keys until the `M` script is visible (it will be empty.) \n- Enter the command `CV 1 N.B RRAND 1 7` and hit Enter. That line should now appear as the first line of the `M` script.\n- Enter a second command `TR.PULSE 1` and hit Enter. That line should now appear as the second line of the `M` script.\n\nAt this point you should start to hear notes coming out, once per second, which is the default period of the metronome that triggers `M`. The first line is selecting a random note from the C Major scale and sending it out as a V/oct pitch value on CV 1. The second line is triggers a short pulse on the TR 1 output.\n\nTo add some variety, add a third script line: `PROB 20: CV.OFF 1 V RRAND 0 3` to randomly switch octaves.\n\nTo make the clock speed controllable with the *PARAM* knob, try adding the following lines:\n```\nPARAM.SCALE 60 240\nM BPM PARAM\nTR.TIME / M 2\n```\n\nThe first line tells Teletype to interpret the *PARAM* knob as ranging from 60 to 240. The second line sets the new `M` period to a value that would result in the BPM specified by the `PARAM` value. The third line sets the TR pulse time to one-half the clock period so the notes scale with the clock rather than running together.\n\n# Quickstart 2\n\nThis quickstart example uses Teletype alongside modules from VCV's [Free collection](https://vcvrack.com/Free). In addition to using Teletype's internal clock, we'll also trigger scripts with external input to sequence exciting changes to our patch. [Meadowphysics](../meadowphysics) was originally designed as a script-triggering companion to Teletype, so that's exactly what we'll use it to do.\n\n![teletype quickstart 2 screenshot](../images/teletype-quickstart-2.png){: class=\"patch-image\" }\n*uses: Meadowphysics, Teletype, grid (optional), VCO (2x), ADSR (2x), VCA MIX, AUDIO*\n\n[teletype-quickstart-2.vcv](../patches/teletype-quickstart-2.vcv){: class=\"patch-download-link\" }\n\n- Load the `TRIANGLE MOUNTAIN` factory preset by right-clicking Teletype and hovering over the *Preset* submenu, then clicking `TRIANGLE MOUNTAIN`.\n- Patch **CV 1** to the first VCO's V/8 input, and **CV 2** to the other's\n- Patch **TR 1** to the first ADSR's GATE input, and **TR 2** to the other's\n- Patch the TRI output of the first VCO to the first input of VCA MIX\n- Patch the SAW output of the second VCO to the second input of VCA MIX\n- Patch the first ADSR's ENV to CV 1 of VCA MIX\n- Patch the second ADSR's ENV to CV 2 of VCA MIX\n\nIf all went well, you'll start hearing a cycling arpeggio from the first VCO. Experiment with patching outputs from Meadowphysics into each of Teletype's eight trigger inputs. We recommend starting with trigger input `5` to get a sequence going on the second VCO, then explore from there! Be sure to play with running Meadowphysics and Teletype at different rates, with the *CLOCK* knob on Meadowphysics and the *PARAM* knob on Teletype.\n\nClick the Teletype screen and hit Tab to look at the pattern values in TRACKER mode and the scripts in EDIT mode. The TRIANGLE MOUNTAIN scene demonstrates several Teletype features, including the `P` [pattern ops](https://monome.org/docs/teletype/manual/#patterns-1), the `S` [stack ops](https://monome.org/docs/teletype/manual/#stack), and the [preconditions](https://monome.org/docs/teletype/manual/#control-flow) `IF:`, `ELSE:` and `L:` (for Loop).\n\n\n# Teletype and grids\n\nUnlike the other modules in this collection, Teletype can be used close to fully without a grid controller. But it does have two optional ways to interact with a connected grid.\n\nThe first is \"Grid Control Mode\" which is always available, without special scripting. Connect a grid and press the `PRESET` button twice to enable grid control mode. It will only take up an 8x8 section of the grid, so on larger grids the rest of the grid will show whatever the scene has scripted (or nothing.) From the grid control mode interface, you can jump to scripts in the editor, toggle and mute them, edit patterns, mute individual lines of code, and manage scenes. See the [GRID INTEGRATION guide section on Grid Control Mode](https://github.com/scanner-darkly/teletype/wiki/GRID-CONTROL-MODE) for the details.\n\nThe second way to interact with grids is to script your own interface. The `G` series of operators allow creating scenes that can light up individual LEDs, draw shapes, and create controls (such as buttons and faders) that can be used to trigger and control scripts. \n\nFor the basics, see [the Teletype manual](https://monome.org/docs/teletype/manual/#grid).\n\nFor advanced scripting techniques, see [@scanner-darkly](https://github.com/scanner-darkly)'s [GRID INTEGRATION studies](https://github.com/scanner-darkly/teletype/wiki/GRID-INTEGRATION).\n\nYou can use either a physical or virtual grid to take advantage of the grid operators or Grid Control Mode. Hardware versions of Teletype can't use both the grid and the keyboard at the same time, and there are [some precautions to follow](https://monome.org/docs/grid/grid-modular/#teletype) regarding power loads, but thankfully the software version has none of these restrictions, making it an excellent environment for developing complex grid scenes that you can later transfer to hardware.\n\n# Alternate firmware\n\nChoose **Firmware Tools > Switch Firmware** to see alternate firmware options for Teletype.\n\nCurrently there are firmware options for the Teletype 4.x and 5.x release streams. Older versions of monome-rack used Teletype 4.x by default; as of monome-rack 2.2.5, newly placed modules will default to 5.x, but modules already placed in your patch will stay on whatever they're currently using.\n\nSwitching firmware will reset the active scene VRAM and the stored scenes NVRAM for the module. Make sure to export any scenes you want to keep before switching firmware editions.\n\n# Further reading\n\n* Teletype [hardware documentation](http://monome.org/docs/teletype/)\n* Teletype manual [on the web](https://monome.org/docs/teletype/manual) and [in PDF format](https://monome.org/docs/teletype/manual.pdf)\n* Printable Teletype 5.0 [command cheat sheet](https://monome.org/docs/teletype/TT_commands_5.0.pdf)\n* [Teletype Studies](https://monome.org/docs/teletype/studies-1/)\n* [A user's guide to the wonderful world of teletype](https://llllllll.co/t/a-users-guide-to-the-wonderful-world-of-teletype/35971)\n* [Teletype workflow, basics, and questions](https://llllllll.co/t/teletype-workflow-basics-and-questions/12392)\n* [Teletype code exchange](https://llllllll.co/t/teletype-code-exchange/839)\n* [Teletype grid integration](https://github.com/scanner-darkly/teletype/wiki/GRID-INTEGRATION)\n* [\"teletype\" search on llllllll.co](https://llllllll.co/search?q=teletype)\n\n# Video tutorials\n\n* [VCV Rack Teletype tutorial by Jakub Ciupinski](https://www.youtube.com/watch?v=AMldf2W0mUw)\n* [VCV Rack Teletype Microtutorials by Obakegaku](https://youtube.com/playlist?list=PLt9Y2vOdxouMOWfxDrgVIY0hMZvFCSBw7) and [patch files](https://patchstorage.com/author/obakegaku/)\n* [\"Teletype Talk\" series by Joe Filbrun](https://www.youtube.com/watch?v=mMAhjRKrpZE&list=PLoxHBVkj2rip4Ce4kxdz_k7mK9Z8Wygo-)\n* [Teletype videos by The Ghost Saboteur](https://www.youtube.com/playlist?list=PLMHhQKTYXU657VGx48aj-0rs_tjoz7-Eo)\n* [Teletype & generative 201](https://www.youtube.com/watch?v=cVHhZkG-pck) from mcpm - [slides and code](https://docs.google.com/presentation/d/1NpNET1D4FlF4zljdo58_u29eLRYLV7yAbxGCsyR12hA/edit#slide=id.gf9647da6be_0_189)\n\n" }, { "path": "docs/content/modules/whitewhale.md", "content": "![white whale module screenshot](../images/whitewhale.png){: class=\"module-image-sixhp\" }\n\n## White Whale\n\nWhite Whale, [connected to a grid controller](../../general/connections), is a live probabilistic step sequencer. It is the culmination of methods and experiments based on a decade of step sequencer design for the grid.\n\nWithout a grid connection it will not produce any output besides a clock, but once a sequence has been entered, you can disconnect the grid and the sequence will continue playing.\n\n[Read the introduction to the hardware module](http://monome.org/docs/whitewhale/#introduction).\n\n# CV A-B & TR 1-4 outputs\n\nWhite Whale produces two continuous CV outputs on **CV A** and **CV B** on the left side of the module and four trigger/gate outputs from **TR 1-4** on the right side. CV outputs range from 0 V to 10 V and TR outputs are 0 V low, 8 V high.\n\nCV's are quantized to the nearest semitone by default, for easier melodic tuning. They can also be un-quantized in conjunction with the **PARAM** knob [as described in the hardware docs](https://monome.org/docs/whitewhale/#cv-map).\n\nTriggers may be swapped for gates by entering [gate mode](https://monome.org/docs/whitewhale/#gate-mode).\n\n# CLOCK knob & jacks\n\nThe **CLOCK** knob controls the timing of clock pulses that drive the four triggers and two CV values. The knob ranges from a period of 2 second to a period of 47ms. Patching a signal into **CLOCK IN** will override the timing and [every low/high transition](../../general/voltage/#inputs) on the input will pulse the counters. (Very fast clocks approaching a 1ms period may result in skipped pulses; the module will not go into audio rate.) The pulse width of the clock in sets the trigger time for individual trigger outs. The sequencer can be stopped altogether by inserting an unconnected patch cable to clock in.\n\nThe **CLOCK OUT** jack sends a gate signal out according to the current clock following the internal or external clock as appropriate. This output is ideal for linking multiple sequencers, or for a regular rhythmic pulse in your system.\n\n# PARAM knob\n\nA multi-purpose control which changes its mode depending on the grid interface. Generally, if there is a continuous value represented by a grid key or row, holding that key and turning *PARAM* will allow you to edit it.\n\n# Grid reference\n\n![white whale grid legend screenshot](../images/whitewhale-grid-legend.png){: class=\"patch-image\" }\n\n[whitewhale-grid-legend.vcv](../patches/whitewhale-grid-legend.vcv){: class=\"patch-download-link\" } *(requires [Stoermelder Glue](https://library.vcvrack.com/Stoermelder-P1))*\n\nPressing a key in the first row will swap between three data views: the *TR 1-4* trigger outs, the *CV A* output, or the *CV B* output. In the Triggers view, pressing a key will turn the gate on or off for that step.\n\nThe *CV A & B* modes are more complex. They can either be in [Curves](http://monome.org/docs/whitewhale/#cv-curves) mode for unquantized outputs, or [CV Map](http://monome.org/docs/whitewhale/#cv-map) mode for outputs quantized to a scale. \n\nIn the default [Curves](http://monome.org/docs/whitewhale/#cv-curves) mode, you can change CV values while in the *CV A* or *CV B* region by either:\n\n- pressing any pad in the bottom 4 rows to set that step's CV value to the **PARAM** knob's position\n- holding any one pad in the bottom 4 rows and using **PARAM** to adjust that step's CV value\n- holding ALT and the bottom-right key to live-record the **PARAM** knob's value to each step in realtime\n - note: values overwrite as soon as you hold the ALT + bottom-right key combo\n\nIn [CV Map](http://monome.org/docs/whitewhale/#cv-map) mode, you can change CV values by selecting a step on the fifth row, and selecting one of the 16 values in the map on the bottom row.\n\n# Quickstart\n\nThis quickstart example uses White Whale alongside modules from VCV's [Free collection](https://vcvrack.com/Free).\n\n![white whale quickstart screenshot](../images/whitewhale-quickstart.png){: class=\"patch-image\" }\n*uses: White Whale, ADSR, VCO, VCF, VCA MIX, AUDIO*\n\n[whitewhale-quickstart.vcv](../patches/whitewhale-quickstart.vcv){: class=\"patch-download-link\" }\n\n- Connect White Whale to a grid (See [Making Connections](../../general/connections/#making-connections).)\n- Patch White Whale's **TR 1** to ADSR's GATE input.\n- Patch VCO's TRI output to VCF's IN.\n- Patch VCF's LPF output to IN 1 of VCA MIX.\n- Patch ADSR's ENV output to CV 1 of VCA MIX.\n- Patch VCA MIX's MIX output to AUDIO's L input.\n- Create a sequence of triggers on White Whale's first channel to open the envelope.\n- Patch White Whale's **CV A** to VCF's CUT input and add modulation using the attenuator above the input (you won't hear changes yet.)\n- Enter the **CV A** region on grid by pressing the fourth key in the top row. Now enter CV values for a few steps by holding a key on the bottom row and turning the **PARAM** knob.\n- Adjust VCF's CUTOFF and RES to hear **CV A**'s affect.\n- Hold *ALT* on the grid and enter the **CV B** region on grid -- this will show put **CV B** into a [Scale Map](https://monome.org/docs/whitewhale/#cv-map), which quantizes **CV B**'s output to a musical note range.\n- As the pattern plays, enter new notes for each step in the *Scale Map*.\n\n# Alternate firmware\n\nChoose **Firmware Tools > Switch Firmware** to see alternate firmware options for White Whale.\n\nWhite Whale offers the standard firmware plus the Kria alternate firmware, an early form of the Kria sequencer mode in Ansible. [Read about the original version of Kria here](https://llllllll.co/t/kria-0-3-initial-release/2409).\n\n# Further reading\n\n* White Whale [hardware documentation](http://monome.org/docs/whitewhale/)\n* [\"white whale\" search on llllllll.co](https://llllllll.co/search?q=white%20whale)\n\n# Video tutorials\n\n* [white whale possibilities](https://vimeo.com/104881064)\n* [white whale tutorial part 1](https://vimeo.com/105368808)\n* [white whale tutorial part 2](https://vimeo.com/105368874)\n* [white whale tutorial part 3](https://vimeo.com/105408057)\n* [white whale tutorial part 4](https://vimeo.com/105408747)\n* [kria demo](https://vimeo.com/152756139)\n* [kria lesson](https://vimeo.com/153923660)\n" }, { "path": "docs/custom-theme/main.html", "content": "{% extends \"base.html\" %}\n\n{% block footer %}\n{% endblock %}" }, { "path": "docs/custom-theme/partials/search/mkdocs/search-modal.html", "content": "
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These are removed with `strip`.\nFLAGS += -g\n# Optimization\nFLAGS += -O3 -funsafe-math-optimizations -fno-omit-frame-pointer\n# Warnings\nFLAGS += -Wall -Wextra -Wno-unused-parameter\n# C++ standard\nCXXFLAGS += -std=c++11\n\n# Define compiler/linker target if cross-compiling\nifdef CROSS_COMPILE\n\tFLAGS += --target=$(MACHINE)\n\tLDFLAGS += --target=$(MACHINE)\nendif\n\n# Architecture-independent flags\nifdef ARCH_X64\n\tFLAGS += -DARCH_X64\n\tFLAGS += -march=nehalem\nendif\nifdef ARCH_ARM64\n\tFLAGS += -DARCH_ARM64\n\tFLAGS += -march=armv8-a+fp+simd\nendif\n\nifdef ARCH_LIN\n\tFLAGS += -DARCH_LIN\n\tCXXFLAGS += -Wsuggest-override\nendif\nifdef ARCH_MAC\n\tFLAGS += -DARCH_MAC\n\tCXXFLAGS += -stdlib=libc++\n\tLDFLAGS += -stdlib=libc++\n\tMAC_SDK_FLAGS := -mmacosx-version-min=10.9\n\tFLAGS += $(MAC_SDK_FLAGS)\n\tLDFLAGS += $(MAC_SDK_FLAGS)\nendif\nifdef ARCH_WIN\n\tFLAGS += -DARCH_WIN\n\tFLAGS += -D_USE_MATH_DEFINES\n\tFLAGS += -municode\n\tCXXFLAGS += -Wsuggest-override\nendif\n\n# Allow *appending* rather than prepending to common flags.\n# This is useful to force-redefine compiler settings instead of merely setting defaults that may be overwritten.\nFLAGS += $(EXTRA_FLAGS)\nCFLAGS += $(EXTRA_CFLAGS)\nCXXFLAGS += $(EXTRA_CXXFLAGS)\nLDFLAGS += $(EXTRA_LDFLAGS)\n\n# Apply FLAGS to language-specific flags\nCFLAGS += $(FLAGS)\nCXXFLAGS += $(FLAGS)\n\n# Derive object files from sources and place them before user-defined objects\nOBJECTS := $(patsubst %, $(BUILD_DIR)/%.o, $(SOURCES)) $(OBJECTS)\nOBJECTS += $(patsubst %, $(BUILD_DIR)/%.bin.o, $(BINARIES))\nDEPENDENCIES := $(patsubst %, $(BUILD_DIR)/%.d, $(SOURCES))\n\n# Final targets\n\n$(TARGET): $(OBJECTS)\n\t$(CXX) -o $@ $^ $(LDFLAGS)\n\n-include $(DEPENDENCIES)\n\n$(BUILD_DIR)/%.c.o: %.c\n\t@mkdir -p $(@D)\n\t$(CC) $(CFLAGS) -c -o $@ $<\n\n$(BUILD_DIR)/%.cpp.o: %.cpp\n\t@mkdir -p $(@D)\n\t$(CXX) $(CXXFLAGS) -c -o $@ $<\n\n$(BUILD_DIR)/%.cc.o: %.cc\n\t@mkdir -p $(@D)\n\t$(CXX) $(CXXFLAGS) -c -o $@ $<\n\n$(BUILD_DIR)/%.m.o: %.m\n\t@mkdir -p $(@D)\n\t$(CC) $(CFLAGS) -c -o $@ $<\n\n$(BUILD_DIR)/%.bin.o: %\n\t@mkdir -p $(@D)\nifdef ARCH_LIN\n\t$(OBJCOPY) -I binary -O elf64-x86-64 -B i386:x86-64 --rename-section .data=.rodata,alloc,load,readonly,data,contents $< $@\nendif\nifdef ARCH_WIN\n\t$(OBJCOPY) -I binary -O pe-x86-64 -B i386:x86-64 --rename-section .data=.rodata,alloc,load,readonly,data,contents $< $@\nendif\nifdef ARCH_MAC\n\t@# Apple makes this needlessly complicated, so just generate a C file with an array.\n\txxd -i $< | $(CC) $(MAC_SDK_FLAGS) -c -o $@ -xc -\nendif\n\n$(BUILD_DIR)/%.html: %.md\n\tmarkdown $< > $@\n" }, { "path": "firmware/earthsea.mk", "content": "TARGET_NAME := earthsea\n\nFLAGS += \\\n\t-D__AVR32_UC3B0256__ \\\n\t-Imock_hardware \\\n\t-Imock_hardware/include \\\n\t-Iearthsea/libavr32/src \\\n\t-Iearthsea/libavr32/src/usb/midi \\\n\t-Iearthsea/libavr32/src/usb/hid \\\n\t-Iearthsea/libavr32/src/usb/cdc \\\n\t-Iearthsea/libavr32/asf/common/services/usb \\\n\t-Iearthsea/libavr32/asf/common/services/usb/uhc \\\n\t-Iearthsea/libavr32/conf \\\n\t-Iearthsea/libavr32/conf/trilogy \\\n\t\nSOURCES = \\\n\tearthsea/src/main.c \\\n\tearthsea/libavr32/src/arp.c \\\n\tearthsea/libavr32/src/euclidean/data.c \\\n\tearthsea/libavr32/src/euclidean/euclidean.c \\\n\tearthsea/libavr32/src/events.c \\\n\tearthsea/libavr32/src/notes.c \\\n\tearthsea/libavr32/src/random.c \\\n\tearthsea/libavr32/src/timers.c \\\n\tearthsea/libavr32/src/util.c \\\n\t$(wildcard mock_hardware/*.c) \\\n\t$(wildcard mock_hardware/common/*.c) \\\n\t$(wildcard mock_hardware/modules/trilogy/*.c) \\\n\nFLAGS += -DGIT_VERSION=\"\\\"$(GIT_VERSION)\\\"\"\n\ninclude common.mk\n" }, { "path": "firmware/meadowphysics.mk", "content": "TARGET_NAME := meadowphysics\n\nFLAGS += \\\n\t-D__AVR32_UC3B0256__ \\\n\t-Imock_hardware \\\n\t-Imock_hardware/include \\\n\t-Imeadowphysics/libavr32/src \\\n\t-Imeadowphysics/libavr32/src/usb/midi \\\n\t-Imeadowphysics/libavr32/src/usb/hid \\\n\t-Imeadowphysics/libavr32/src/usb/cdc \\\n\t-Imeadowphysics/libavr32/asf/common/services/usb \\\n\t-Imeadowphysics/libavr32/asf/common/services/usb/uhc \\\n\t-Imeadowphysics/libavr32/conf \\\n\t-Imeadowphysics/libavr32/conf/trilogy \\\n\t\t\nSOURCES = \\\n\tmeadowphysics/src/main.c \\\n\tmeadowphysics/libavr32/src/events.c \\\n\tmeadowphysics/libavr32/src/timers.c \\\n\tmeadowphysics/libavr32/src/util.c \\\n\t$(wildcard mock_hardware/*.c) \\\n\t$(wildcard mock_hardware/common/*.c) \\\n\t$(wildcard mock_hardware/modules/trilogy/*.c) \\\n\nFLAGS += -DGIT_VERSION=\"\\\"$(GIT_VERSION)\\\"\"\n\n\ninclude common.mk\n" }, { "path": "firmware/mock_hardware/common/adc.c", "content": "#include \"mock_hardware_api.h\"\n#include \"types.h\"\n\nvoid adc_convert(u16 (*adc)[4])\n{\n (*adc)[0] = hardware_getADC(0);\n (*adc)[1] = hardware_getADC(1);\n (*adc)[2] = hardware_getADC(2);\n (*adc)[3] = hardware_getADC(3);\n}" }, { "path": "firmware/mock_hardware/common/cdc.c", "content": "#include \"types.h\"\n\nvoid cdc_write(uint8_t* data, uint32_t bytes)\n{\n}\n\nvoid cdc_read(void)\n{\n}\n\nvoid cdc_setup(void)\n{\n}\n\nu8* cdc_rx_buf(void)\n{\n return 0;\n}\n\nu8 cdc_rx_bytes(void)\n{\n return 0;\n}\n\nu8 cdc_rx_busy(void) { return 0; }\nu8 cdc_tx_busy(void) { return 0; }\n\nu8 cdc_connected(void)\n{\n return 0;\n}" }, { "path": "firmware/mock_hardware/common/flashc.c", "content": "#include \"mock_hardware_api.h\"\n#include \"types.h\"\n#include \n\nvoid* flashc_memset64(void* dst, uint64_t src, size_t nbytes, bool erase)\n{\n (*(uint64_t*)dst) = src;\n return dst;\n}\n\nvoid* flashc_memset32(void* dst, uint32_t src, size_t nbytes, bool erase)\n{\n (*(uint32_t*)dst) = src;\n return dst;\n}\n\nvoid* flashc_memset16(void* dst, uint16_t src, size_t nbytes, bool erase)\n{\n (*(uint16_t*)dst) = src;\n return dst;\n}\n\nvoid* flashc_memset8(void* dst, uint8_t src, size_t nbytes, bool erase)\n{\n (*(uint8_t*)dst) = src;\n return dst;\n}\n\nvoid* flashc_memcpy(void* dst, const void* src, size_t nbytes, bool erase)\n{\n memcpy(dst, src, nbytes);\n return dst;\n}" }, { "path": "firmware/mock_hardware/common/ftdi.c", "content": "#include \"types.h\"\n\nvoid ftdi_write(uint8_t* data, uint32_t bytes)\n{\n}\n\nvoid ftdi_read(void)\n{\n}\n\nvoid ftdi_setup(void)\n{\n}\n\nu8* ftdi_rx_buf(void)\n{\n return 0;\n}\n\nvolatile u8 ftdi_rx_bytes(void)\n{\n return 0;\n}\n\nvolatile u8 ftdi_rx_busy(void) { return 0; }\nvolatile u8 ftdi_tx_busy(void) { return 0; }\n\nu8 ftdi_connected(void)\n{\n return 0;\n}" }, { "path": "firmware/mock_hardware/common/gpio.c", "content": "#include \"mock_hardware_api.h\"\n#include \"types.h\"\n\nvoid gpio_set_gpio_pin(u32 pin)\n{\n hardware_setGPIO(pin, true);\n}\n\nvoid gpio_clr_gpio_pin(u32 pin)\n{\n hardware_setGPIO(pin, false);\n}\n\nvoid gpio_set_pin_high(u32 pin)\n{\n hardware_setGPIO(pin, true);\n}\n\nvoid gpio_set_pin_low(u32 pin)\n{\n hardware_setGPIO(pin, false);\n}\n\nint gpio_get_pin_value(u32 pin)\n{\n return hardware_getGPIO(pin);\n}\n" }, { "path": "firmware/mock_hardware/common/i2c.c", "content": "#include \"i2c.h\"\n#include \"mock_hardware_api.h\"\n#include \"types.h\"\n\nuint8_t last_port = 0;\nint i2c_leader_tx(uint8_t addr, uint8_t* data, uint8_t l)\n{\n hardware_iiPushMessage(addr, data, l);\n if (l >= 1)\n {\n last_port = data[0];\n }\n\n return 0;\n}\n\nint i2c_leader_rx(uint8_t addr, uint8_t* data, uint8_t l)\n{\n if (l == 2)\n {\n uint16_t value = hardware_iiGetFollowerData(addr, last_port);\n data[0] = value >> 8;\n data[1] = value & 0xFF;\n }\n\n return 0;\n}\n\nvoid twi_follower_rx(uint8_t u8_value) { }\nuint8_t twi_follower_tx(void) { return 0; }\nvoid twi_follower_stop(void) { }\n\nvoid ii_tx_queue(uint8_t u8_value) { }\n\nvolatile process_ii_t process_ii;\n" }, { "path": "firmware/mock_hardware/common/init_common.c", "content": "#include \"types.h\"\n\nvoid init_gpio() { }\nvoid init_spi() { }\nvoid init_adc() { }\nvoid init_tc(void) { }\nvoid init_usb_host(void) { }\n\nvoid init_i2c_follower(uint8_t addr) { }\nvoid init_i2c_leader(void) { }\n\nvoid register_interrupts() { }\nvoid sysclk_init() { }\n\nvoid init_dbg_rs232(long pba_hz) { }\n\n\n\n" }, { "path": "firmware/mock_hardware/common/interrupts.c", "content": "#include \"types.h\"\n\nu8 irqs_pause(void) { return 0; }\nvoid irqs_resume(u8 irq_flags) { }\n" }, { "path": "firmware/mock_hardware/common/midi.c", "content": "#include \"types.h\"\n#include \n#include \"uhc.h\"\n\nvoid midi_read(void) { }\nbool midi_write(const u8* data, u32 bytes) { return true; }\nvoid midi_change(uhc_device_t* dev, u8 plug) { }" }, { "path": "firmware/mock_hardware/common/monome.c", "content": "#include \"delay.h\"\n#include \"print_funcs.h\"\n#include \n\n#include \"events.h\"\n#include \"ftdi.h\"\n#include \"cdc.h\"\n#include \"monome.h\"\n\n\n//------ defines\n\n// manufacturer string length\n#define MONOME_MANSTR_LEN 6\n// product string lengthextern\n#define MONOME_PRODSTR_LEN 8\n// serial string length\n#define MONOME_SERSTR_LEN 9\n// tx buffer length\n#define MONOME_TX_BUF_LEN 72\n\n// level above which an LED must be set to be displayed on mono-brightness grid\n#define VB_CUTOFF 7\n\nvoid (*serial_read)(void) = ftdi_read;\nvoid (*serial_write)(u8*, u32) = ftdi_write;\nvolatile u8 (*tx_busy)(void);\nvolatile u8 (*rx_busy)(void);\nvolatile u8 (*rx_bytes)(void);\nu8* (*rx_buf)(void);\nu8 (*serial_connected)(void);\n\n//------- typedefs\n//--- descriptor types\n\n// protocol enumeration\ntypedef enum {\n eProtocol40h, /// 40h and arduinome protocol (pre-2007)\n eProtocolSeries, /// series protocol (2007-2011)\n eProtocolMext, /// extended protocol (2011 - ? ), arcs + grids\n eProtocolNumProtocols // dummy and count\n} eMonomeProtocol;\n\n\n// device descriptor\ntypedef struct e_monomeDesc {\n eMonomeProtocol protocol;\n eMonomeDevice device;\n u8 cols; // number of columns\n u8 rows; // number of rows\n u8 encs; // number of encoders\n u8 tilt; // has tilt (??)\n u8 vari; // is variable brightness, true/false\n} monomeDesc;\n\n\n//// dummy functions\nstatic void read_serial_dummy(void) { return; }\n\n//-------------------------------------\n//------ extern variables\n\n// connected flag\n// u8 monomeConnect = 0;\n\n// dirty flags for each quadrant or knob (bitwise)\nu8 monomeFrameDirty = 0;\n// a buffer big enough to hold all l data for 256 or arc4\n// each led gets a full byte\nu8 defaultLedBuffer[MONOME_MAX_LED_BYTES];\nu8 *monomeLedBuffer = defaultLedBuffer;\n\n// global pointers to send functions.\nread_serial_t monome_read_serial = &read_serial_dummy;\nset_intense_t monome_set_intense;\n// grid_led_t monome_grid_led;\ngrid_map_t monome_grid_map;\ngrid_level_map_t monome_grid_level_map;\nring_map_t monome_ring_map;\nrefresh_t monome_refresh;\n//-----------------------------------------\n//----- static variables\n\n// descriptor for connected device\nmonomeDesc mdesc = {\n .protocol = eProtocolNumProtocols, // dummy\n .device = eDeviceNumDevices, // dummy\n .cols = 16,\n .rows = 8,\n .encs = 4,\n .tilt = 0,\n};\n\n// local rx byte count\nstatic u8 rxBytes;\n// event data\nstatic event_t ev;\n// local tx buffer\nstatic u8 txBuf[MONOME_TX_BUF_LEN];\n\n//---------------------------------------------\n//------ static function declarations\n\n// setup for each protocol\nstatic void setup_40h(u8 cols, u8 rows);\nstatic void setup_series(u8 cols, u8 rows);\nstatic u8 setup_mext(void);\n\n// rx for each protocol\nstatic void read_serial_40h(void);\nstatic void read_serial_series(void);\nstatic void read_serial_mext(void);\n\n\n// set intensity\nstatic void set_intense_series(u8 level);\nstatic void set_intense_mext(u8 level);\n\n\n// tx for each protocol\n///// no real reason not to use only grid/map at the moment\n/* static void grid_led_40h(u8 x, u8 y, u8 val); */\n/* static void grid_led_series(u8 x, u8 y, u8 val); */\n/* static void grid_led_mext(u8 x, u8 y, u8 val); */\n\nstatic void grid_map_40h(u8 x, u8 y, const u8* data);\nstatic void grid_map_series(u8 x, u8 y, const u8* data);\nstatic void grid_map_mext(u8 x, u8 y, const u8* data);\n\n/// TODO: varibright\n//static void grid_map_level_40h(u8 x, u8 val);\n//static void grid_map_level_series(u8 x, u8 y, u8* data);\n// static void grid_map_level_mext(u8 x, u8 y, const u8* data);\n\n//static void ring_set_mext(u8 n, u8 rho, u8 val);\nstatic void ring_map_mext(u8 n, u8* data);\n\n//static void connect_write_event(void);\nstatic inline void monome_grid_key_write_event( u8 x, u8 y, u8 val);\nstatic inline void monome_grid_adc_write_event( u8 n, u16 val);\nstatic inline void monome_ring_enc_write_event( u8 n, u8 val);\nstatic inline void monome_ring_key_write_event( u8 n, u8 val);\n\n\n\n\n//---------------------------------\n//----- static variables\n\n//---- function pointer arrays\n\n// read serial and spawn events\nstatic const read_serial_t readSerialFuncs[eProtocolNumProtocols] = {\n &read_serial_40h,\n &read_serial_series,\n &read_serial_mext,\n};\n\n// set intensity\nstatic const set_intense_t intenseFuncs[eProtocolNumProtocols] = {\n NULL, // unsupported\n &set_intense_series,\n &set_intense_mext,\n};\n\n\n// grid/led\n/* static grid_led_t gridLedFuncs[eProtocolNumProtocols] = { */\n/* &grid_led_40h, */\n/* &grid_led_series, */\n/* &grid_led_mext, */\n/* }; */\n\n// grid/map\nstatic const grid_map_t gridMapFuncs[eProtocolNumProtocols] = {\n &grid_map_40h,\n &grid_map_series,\n &grid_map_mext,\n};\n\n// grid/level/map\n/* static grid_level_map_t gridMapLevelFuncs[eProtocolNumProtavr32_lib/src/ocols] = { */\n/* NULL, // unsupported */\n/* NULL, // unsupported */\n/* &grid_map_level_mext, */\n/* }; */\n\nstatic const ring_map_t ringMapFuncs[eProtocolNumProtocols] = {\n NULL, // unsupported\n NULL, // unsupported\n &ring_map_mext,\n};\n\n// grid vs arc refresh\nstatic const refresh_t refreshFuncs[eProtocolNumProtocols] = {\n &monome_grid_refresh,\n &monome_arc_refresh\n};\n\n//================================================\n//----- extern function definitions\n\n// init\nvoid init_monome(void) {\n u32 i;\n for(i=0; i 7 ) {\n while( busy ) { busy = tx_busy(); }\n (*monome_grid_map)(8, 0, monomeLedBuffer + 8);\n monomeFrameDirty &= 0b1101;\n busy = 1;\n }\n }\n // check quad 2\n if( monomeFrameDirty & 0b0100 ) {\n if( mdesc.rows > 7 ) {\n while( busy ) { busy = tx_busy(); }\n (*monome_grid_map)(0, 8, monomeLedBuffer + 128);\n monomeFrameDirty &= 0b1011;\n busy = 1;\n }\n }\n // check quad 3\n if( monomeFrameDirty & 0b1000 ) {\n if( (mdesc.rows > 7) && (mdesc.cols > 7) ) {\n while( busy ) { busy = tx_busy(); }\n (*monome_grid_map)(8, 8, monomeLedBuffer + 136);\n monomeFrameDirty &= 0b0111;\n busy = 1;\n }\n }\n while( busy ) { busy = tx_busy(); }\n}\n\n\n// check flags and refresh arc\nvoid monome_arc_refresh(void) {\n // may need to wait after each quad until tx transfer is complete\n u8 busy = tx_busy();\n u8 i;\n\n for(i=0;i 7) {\n if (y > 7) {\n monomeFrameDirty |= 0b1000;\n }\n else {\n monomeFrameDirty |= 0b0010;\n }\n } else {\n if (y > 7) {\n monomeFrameDirty |= 0b0100;\n }\n else {\n monomeFrameDirty |= 0b0001;\n }\n }\n}\n\n// set given quadrant dirty flag\nextern void monome_set_quadrant_flag(u8 q) {\n monomeFrameDirty |= (1 << q);\n}\n\n\n// convert flat framebuffer idx to x,y\nvoid monome_idx_xy(u32 idx, u8* x, u8* y) {\n *x = idx & 0xf;\n *y = (idx >> 4);\n}\n\n// convert x,y to framebuffer idx\nu32 monome_xy_idx(u8 x, u8 y) {\n return x | (y << 4);\n}\n\n// top-level led/set function\nvoid monome_led_set(u8 x, u8 y, u8 z) {\n monomeLedBuffer[monome_xy_idx(x, y)] = z;\n monome_calc_quadrant_flag(x, y);\n}\n\n// top-level led/toggle function\nvoid monome_led_toggle(u8 x, u8 y) {\n monomeLedBuffer[monome_xy_idx(x,y)] ^= 0xff;\n monome_calc_quadrant_flag(x, y);\n}\n\n// arc led/set function\nvoid monome_arc_led_set(u8 enc, u8 ring, u8 val) {\n monomeLedBuffer[ring + (enc << 6)] = val;\n monomeFrameDirty |= (1 << enc);\n}\n\n\n\n\neMonomeDevice monome_device(void) { return mdesc.device; }\nu8 monome_size_x(void) { return mdesc.cols; }\nu8 monome_size_y(void) { return mdesc.rows; }\nu8 monome_is_vari(void) { return mdesc.vari; }\nu8 monome_encs(void) { return mdesc.encs; }\n\n//=============================================\n//------ static function definitions\n\n// set function pointers\nvoid set_funcs(void) {\n // print_dbg(\"\\r\\n setting monome functions, protocol idx: \");\n // print_dbg_ulong(mdesc.protocol);\n monome_read_serial = readSerialFuncs[mdesc.protocol];\n monome_grid_map = gridMapFuncs[mdesc.protocol];\n monome_grid_level_map = gridMapFuncs[mdesc.protocol];\n monome_ring_map = ringMapFuncs[mdesc.protocol];\n monome_set_intense = intenseFuncs[mdesc.protocol];\n monome_refresh = refreshFuncs[mdesc.device == eDeviceArc]; // toggle on grid vs arc\n}\n\n/////////////////////////////////////////////////////\n/////////////////////////////////////////////////////\n///// protocol - specific functions\n\n\n/////////////////////////////\n// setup\n\n// setup 40h-protocol device\nstatic void setup_40h(u8 cols, u8 rows) {\n // print_dbg(\"\\r\\n setup 40h device\");\n mdesc.protocol = eProtocol40h;\n mdesc.device = eDeviceGrid;\n mdesc.cols = 8;\n mdesc.rows = 8;\n mdesc.vari = 0;\n set_funcs();\n monome_connect_write_event();\n}\n\n// setup series device\nstatic void setup_series(u8 cols, u8 rows) {\n // print_dbg(\"\\r\\n setup series device\");\n mdesc.protocol = eProtocolSeries;\n mdesc.device = eDeviceGrid;\n mdesc.cols = cols;\n mdesc.rows = rows;\n mdesc.vari = 0;\n mdesc.tilt = 1;\n set_funcs();\n monome_connect_write_event();\n // monomeConnect = 1;\n // test_draw();\n}\n\n// setup extended device, return success /failure of query\nstatic u8 setup_mext(void) {\n u8* prx;\n u8 w = 0;\n u8 busy;\n\n print_dbg(\"\\r\\n setup mext device\");\n mdesc.protocol = eProtocolMext;\n\n mdesc.vari = 1;\n\n\n // clear out rxbuf\n rxBytes = 1;\n while(rxBytes != 0 && serial_connected()) {\n serial_read();\n\n delay_us(500);\n busy = 1;\n\n while(busy)\n busy = rx_busy();\n\n rxBytes = rx_bytes();\n }\n\n rxBytes = 0;\n\n while(rxBytes != 6 && serial_connected()) {\n // FIXME: fuck these delays\n serial_write(&w, 1);\t// query\n\n delay_us(500);\n serial_read();\n\n delay_us(500);\n busy = 1;\n\n while(busy)\n busy = rx_busy();\n\n rxBytes = rx_bytes();\n\n if(rxBytes != 6 ){\n print_dbg(\"e\");\n /*\n print_dbg(\"\\r\\n got unexpected byte count in response to mext setup request; \\r\\n\");\n prx = rx_buf();\n\n for(;rxBytes != 0; rxBytes--) {\n print_dbg_ulong(*(++prx));\n print_dbg(\" \");\n }\n */\n\n // return 0;\n }\n }\n\n prx = rx_buf();\n prx++; // 1st returned byte is 0\n if(*prx == 1) {\n mdesc.device = eDeviceGrid;\n prx++;\n if(*prx == 1) {\n // print_dbg(\"\\r\\n monome 64\");\n mdesc.rows = 8;\n mdesc.cols = 8;\n }\n else if(*prx == 2) {\n // print_dbg(\"\\r\\n monome 128\");\n mdesc.rows = 8;\n mdesc.cols = 16;\n }\n else if(*prx == 4) {\n // print_dbg(\"\\r\\n monome 256\");\n mdesc.rows = 16;\n mdesc.cols = 16;\n }\n else {\n return 0; // bail\n }\n mdesc.tilt = 1;\n }\n else if(*prx == 5) {\n mdesc.device = eDeviceArc;\n mdesc.encs = *(++prx);\n print_dbg(\"\\r\\n monome arc \");\n print_dbg_ulong(*prx);\n } else {\n print_dbg_hex(*prx);\n print_dbg_hex(*(++prx));\n print_dbg_hex(*(++prx));\n return 0; // bail\n }\n\n // get id\n w = 1;\n delay_ms(1);\n serial_write(&w, 1);\n delay_ms(1);\n serial_read();\n delay_ms(1);\n busy = 1;\n while(busy) {\n busy = rx_busy();\n }\n rxBytes = rx_bytes();\n prx = rx_buf();\n if(*(prx+2) == 'k')\n mdesc.vari = 0;\n // print_dbg(\"\\r\\ndone waiting. bytes read: \");\n // print_dbg_ulong(rxBytes);\n // print_dbg(\"\\r\\ndata: \");\n // print_dbg_char(*prx);\n // for(;rxBytes != 0; rxBytes--) {\n // print_dbg_char(*(++prx));\n // }\n\n set_funcs();\n monome_connect_write_event();\n // monomeConnect = 1;\n print_dbg(\"\\r\\n connected monome device, mext protocol\");\n // test_draw();\n return 1;\n}\n\n////////////////////////////\n//--- rx\n// rx for each protocol\n/// parse serial input from device\n/// should be called when read is complete\n/// (e.g. from usb transfer callback )\n\nstatic void read_serial_40h(void) {\n u8* prx = rx_buf();\n u8 i;\n rxBytes = rx_bytes();\n // print_dbg(\"\\r\\n read_serial_40h, byte count: \");\n // print_dbg_ulong(rxBytes);\n // print_dbg(\" ; data : [ 0x\");\n // print_dbg_hex(prx[0]);\n // print_dbg(\" , 0x\");\n // print_dbg_hex(prx[1]);\n // print_dbg(\" ]\");\n i = 0;\n while(i < rxBytes) {\n // FIXME: can we expect other event types? (besides press/lift)\n // print_dbg(\" ; x : 0x\");\n // print_dbg_hex((prx[1] & 0xf0) >> 4);\n // print_dbg(\"; y : 0x\");\n // print_dbg_hex(prx[1] & 0xf);\n // print_dbg(\" ; z : 0x\");\n // print_dbg_hex( ((prx[0] & 0xf) != 0) );\n\n // press event\n if ((prx[0] & 0xf0) == 0) {\n monome_grid_key_write_event(\n ((prx[1] & 0xf0) >> 4),\n prx[1] & 0xf,\n ((prx[0] & 0xf) != 0)\n );\n }\n\n i += 2;\n prx += 2;\n }\n}\n\nstatic void read_serial_series(void) {\n u8* prx = rx_buf();\n u8 i;\n rxBytes = rx_bytes();\n // print_dbg(\"\\r\\n read_serial_series, byte count: \");\n // print_dbg_ulong(rxBytes);\n // print_dbg(\" ; data : [ 0x\");\n // print_dbg_hex(prx[0]);\n // print_dbg(\" , 0x\");\n // print_dbg_hex(prx[1]);\n // print_dbg(\" ]\");\n i = 0;\n while(i < rxBytes) {\n // FIXME: can we expect other event types? (besides press/lift)\n /* print_dbg(\" ; x : 0x\"); */\n /* print_dbg_hex((prx[1] & 0xf0) >> 4); */\n /* print_dbg(\"; y : 0x\"); */\n /* print_dbg_hex(prx[1] & 0xf); */\n /* print_dbg(\" ; z : 0x\"); */\n /* print_dbg_hex(\t ((prx[0] & 0xf0) == 0) ); */\n\n // process consecutive pairs of bytes\n monome_grid_key_write_event( ((prx[1] & 0xf0) >> 4) ,\n prx[1] & 0xf,\n ((prx[0] & 0xf0) == 0)\n );\n i += 2;\n prx += 2;\n }\n\n}\n\nstatic void read_serial_mext(void) {\n // static u8 nbr; // number of bytes read\n static u8 nbp; // number of bytes processed\n static u8* prx; // pointer to rx buf\n static u8 com;\n\n rxBytes = rx_bytes();\n if( rxBytes ) {\n nbp = 0;\n prx = rx_buf();\n while(nbp < rxBytes) {\n com = (u8)(*(prx++));\n nbp++;\n switch(com) {\n case 0x20: // grid key up\n monome_grid_key_write_event( *prx, *(prx+1), 0);\n nbp += 2;\n prx += 2;\n break;\n case 0x21: // grid key down\n monome_grid_key_write_event( *prx, *(prx+1), 1);\n nbp += 2;\n prx += 2;\n break;\n case 0x50: // ring delta\n monome_ring_enc_write_event( *prx, *(prx+1));\n nbp += 2;\n prx += 2;\n break;\n case 0x51 : // ring key up\n monome_ring_key_write_event( *prx++, 0);\n prx++;\n break;\n case 0x52 : // ring key down\n monome_ring_key_write_event( *prx++, 1);\n nbp++;\n break;\n /// TODO: more commands...\n default:\n return;\n }\n }\n }\n}\n\n//--- tx\n\n///// not using per-led updates.\n/* static void grid_led_40h(u8 x, u8 y, u8 val) { */\n/* // TODO */\n/* } */\n\n/* static void grid_led_series(u8 x, u8 y, u8 val) { */\n/* // static u8 tx[2]; */\n/* txBuf[0] = 0x20 & ((val > 0) << 4); */\n/* txBuf[1] = (x << 4) | y; */\n/* serial_write(txBuf, 2); */\n/* } */\n\n/* static void grid_led_mext(u8 x, u8 y, u8 val) { */\n/* // static u8 tx[3]; */\n/* txBuf[0] = 0x10 | (val > 0); */\n/* txBuf[1] = x; */\n/* txBuf[2] = y; */\n/* serial_write(txBuf, 3); */\n/* } */\n\n// update a whole frame\n// . note that our input data is one byte per led!!\n// this will hopefully help optimize operator routines,\n// which cannot be called less often than refresh/tx, and are therefore prioritized.\n////////////////////////////////////////////////\n// HACKED to always do var-bright update\n////////////////////////////////////////////////\nstatic void grid_map_mext( u8 x, u8 y, const u8* data ) {\n // static u8 tx[11] = { 0x14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };\n static u8* ptx;\n static u8 i, j;\n\n txBuf[0] = 0x1A;\n txBuf[1] = x;\n txBuf[2] = y;\n\n ptx = txBuf + 3;\n\n // copy and convert\n for(i=0; i 0) << j);\n *ptx = (*data) << 4;\n data++;\n *ptx |= *data;\n data++;\n ptx++;\n }\n data += MONOME_QUAD_LEDS; // skip the rest of the row to get back in target quad\n // ptx++;\n }\n serial_write(txBuf, 32 + 3);\n}\n\n\nstatic void grid_map_40h(u8 x, u8 y, const u8* data) {\n // print_dbg(\"\\n\\r=== grid_map_40h ===\");\n static u8 i, j;\n // ignore all but first quadrant -- do any devices larger than 8x8 speak 40h?\n if (x != 0 || y != 0) {\n return;\n }\n for(i=0; i 0) << j);\n // advance data to next bit\n ++data;\n }\n // skip next 8 bytes to get to next row\n data += MONOME_QUAD_LEDS;\n // print_dbg(\"\\n\\r 40h: send led_row command: \");\n // print_dbg_hex(txBuf[i*2]);\n // print_dbg(\" row data: 0x\");\n // print_dbg_hex(txBuf[(i*2) + 1]);\n }\n serial_write(txBuf, 16);\n}\n\nstatic void grid_map_series(u8 x, u8 y, const u8* data) {\n static u8 * ptx;\n static u8 i, j;\n // command (upper nibble)\n txBuf[0] = 0x80;\n // quadrant index (lower nibble, 0-3)\n txBuf[0] |= ( (x > 7) | ((y > 7) << 1) );\n\n // print_dbg(\"\\n\\r series map: \");\n // print_dbg_hex(txBuf[0]);\n\n // pointer to tx data\n ptx = txBuf + 1;\n\n // copy and convert\n for(i=0; i VB_CUTOFF) << j);\n ++data;\n }\n // print_dbg(\" \");\n // print_dbg_hex(*ptx);\n\n data += MONOME_QUAD_LEDS; // skip the rest of the row to get back in target quad\n ++ptx;\n }\n serial_write(txBuf, MONOME_QUAD_LEDS + 1);\n}\n\n/* static void grid_map_level_mext(u8 x, u8 y, const u8* data) { */\n/* // TODO */\n/* } */\n\nstatic void ring_map_mext(u8 n, u8* data) {\n // static u8 tx[11] = { 0x14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };\n static u8* ptx;\n static u8 i;\n\n txBuf[0] = 0x92;\n txBuf[1] = n;\n\n ptx = txBuf + 2;\n\n // smash 64 LEDs together, nibbles\n for(i=0; i<32; i++) {\n *ptx = *data << 4;\n data++;\n *ptx |= *data;\n data++;\n ptx++;\n }\n\n serial_write(txBuf, 32 + 2);\n}\n\nstatic void set_intense_series(u8 v) {\n /*\n message id:\t(10) intensity\nbytes:\t\t1\nformat:\t\tiiiibbbb\ni (message id) = 10\nb (brightness) = 0-15 (4 bits)\nencode:\t\tbyte 0 = ((id) << 4) | b = 160 + b\n */\n txBuf[0] = 0xa0;\n txBuf[0] |= (v & 0x0f);\n serial_write(txBuf, 1);\n}\n\nstatic void set_intense_mext(u8 v) {\n // TODO\n}\n\n// setup mext direct (for cdc)\nvoid monome_setup_mext() {\n // set rxtx funcs\n serial_read = &cdc_read;\n serial_write = &cdc_write;\n tx_busy = &cdc_tx_busy;\n rx_busy = &cdc_rx_busy;\n rx_buf = &cdc_rx_buf;\n rx_bytes = &cdc_rx_bytes;\n serial_connected = &cdc_connected;\n\n mdesc.device = eDeviceGrid;\n mdesc.protocol = eProtocolMext;\n mdesc.rows = 8;\n mdesc.cols = 16;\n mdesc.vari = 1;\n\n set_funcs();\n monome_connect_write_event();\n}\n" }, { "path": "firmware/mock_hardware/common/print_funcs.c", "content": "#include \n#include \n\n#ifdef FIRMWARE_DEBUG_OUTPUT\nstatic void print_dbg(const char* str) { fprintf(stderr, \"%s\", str); }\nstatic void print_dbg_char(int c) { fprintf(stderr, \"%d\", c); }\nstatic void print_dbg_ulong(unsigned long n) { fprintf(stderr, \"%ld\", n); }\nstatic void print_dbg_char_hex(unsigned char n) { fprintf(stderr, \"%x\", n); }\nstatic void print_dbg_short_hex(unsigned short n) { fprintf(stderr, \"%d\", n); }\nstatic void print_dbg_hex(unsigned long n) { fprintf(stderr, \"%lx\", n); }\n#else\nstatic void print_dbg(const char* str) { }\nstatic void print_dbg_char(int c) { }\nstatic void print_dbg_ulong(unsigned long n) { }\nstatic void print_dbg_char_hex(unsigned char n) { }\nstatic void print_dbg_short_hex(unsigned short n) { }\nstatic void print_dbg_hex(unsigned long n) { }\n#endif" }, { "path": "firmware/mock_hardware/common/screen.c", "content": "#include \"mock_hardware_api.h\"\n#include \"mock_hardware_api_private.h\"\n#include \"types.h\"\n#include \n\nu8 _is_screen_flipped = 0;\n\nvoid init_oled(void) { }\nvoid screen_startup(void) { }\n\nvoid screen_draw_region(u8 x, u8 y, u8 w, u8 h, u8* data)\n{\n u8* screen;\n uint16_t width = 128, height = 64;\n hardware_getScreenBuffer(&screen, &width, &height);\n\n if (screen == NULL || width == 0 || height == 0)\n {\n return;\n }\n\n if (!_is_screen_flipped)\n {\n screen += y * width + x;\n for (int j = 0; j < h; j++)\n {\n memcpy(screen, data, w);\n data += w;\n screen += width;\n }\n }\n else\n {\n screen += (height - y) * width - x - 1;\n for (int j = 0; j < h; j++)\n {\n for (int i = 0; i < w; i++)\n {\n memcpy(screen--, data++, 1);\n }\n screen -= (width - w);\n }\n }\n}\n\nvoid screen_draw_region_offset(u8 x, u8 y, u8 w, u8 h, u32 len, u8* data, u32 off)\n{\n // this is implemented in libavr32 but not called by TT -- no need to implement at present\n}\n\nvoid screen_set_direction(u8 flipped)\n{\n _is_screen_flipped = flipped;\n}\n\nvoid screen_clear(void)\n{\n u8* screen;\n uint16_t width, height;\n hardware_getScreenBuffer(&screen, &width, &height);\n\n if (screen == NULL || width == 0 || height == 0)\n {\n return;\n }\n\n memset(screen, 0, sizeof(uint8_t) * width * height);\n}\n" }, { "path": "firmware/mock_hardware/common/spi.c", "content": "#include \"mock_hardware_api.h\"\n#include \"types.h\"\n\ntypedef enum\n{\n WAITING,\n WRITING_CHANNEL1_HIGH,\n WRITING_CHANNEL1_LOW,\n WRITING_CHANNEL2_HIGH,\n WRITING_CHANNEL2_LOW,\n WRITING_CHANNEL3_HIGH,\n WRITING_CHANNEL3_LOW,\n WRITING_CHANNEL4_HIGH,\n WRITING_CHANNEL4_LOW,\n WAITING_SECOND_WRITE,\n ARG1,\n ARG2\n} spi_dac_state_t;\n\nspi_dac_state_t spi_dac_state = WAITING;\nu32 spi_word;\nint spi_num_devices = 1;\n\nvoid spi_write(u32 chip, u32 byte)\n{\n switch (spi_dac_state)\n {\n case WAITING:\n {\n if (byte == 0x31)\n {\n spi_dac_state = WRITING_CHANNEL1_HIGH;\n }\n else if (byte == 0x38)\n {\n spi_dac_state = WRITING_CHANNEL2_HIGH;\n }\n else if (byte == 0x80)\n {\n spi_num_devices = 2;\n spi_dac_state = ARG1;\n }\n break;\n }\n case WAITING_SECOND_WRITE:\n {\n if (byte == 0x31)\n {\n spi_dac_state = WRITING_CHANNEL3_HIGH;\n }\n else if (byte == 0x38)\n {\n spi_dac_state = WRITING_CHANNEL4_HIGH;\n }\n else if (byte == 0x80)\n {\n spi_num_devices = 2;\n spi_dac_state = ARG1;\n }\n break;\n }\n case WRITING_CHANNEL1_HIGH:\n {\n spi_word = byte << 8;\n spi_dac_state = WRITING_CHANNEL1_LOW;\n break;\n }\n case WRITING_CHANNEL1_LOW:\n {\n spi_word |= byte;\n hardware_setDAC(0, spi_word);\n if (spi_num_devices == 1)\n {\n spi_dac_state = WAITING;\n }\n else\n {\n spi_dac_state = WAITING_SECOND_WRITE;\n }\n break;\n }\n case WRITING_CHANNEL2_HIGH:\n {\n spi_word = byte << 8;\n spi_dac_state = WRITING_CHANNEL2_LOW;\n break;\n }\n case WRITING_CHANNEL2_LOW:\n {\n spi_word |= byte;\n hardware_setDAC(1, spi_word);\n if (spi_num_devices == 1)\n {\n spi_dac_state = WAITING;\n }\n else\n {\n spi_dac_state = WAITING_SECOND_WRITE;\n }\n break;\n }\n case WRITING_CHANNEL3_HIGH:\n {\n spi_word = byte << 8;\n spi_dac_state = WRITING_CHANNEL3_LOW;\n break;\n }\n case WRITING_CHANNEL3_LOW:\n {\n spi_word |= byte;\n hardware_setDAC(2, spi_word);\n spi_dac_state = WAITING;\n break;\n }\n case WRITING_CHANNEL4_HIGH:\n {\n spi_word = byte << 8;\n spi_dac_state = WRITING_CHANNEL4_LOW;\n break;\n }\n case WRITING_CHANNEL4_LOW:\n {\n spi_word |= byte;\n hardware_setDAC(3, spi_word);\n spi_dac_state = WAITING;\n break;\n }\n case ARG1:\n {\n spi_dac_state = ARG2;\n }\n case ARG2:\n {\n spi_dac_state = WAITING;\n }\n }\n}\n\nvoid spi_selectChip(u32 arg1, u32 arg2) {};\nvoid spi_unselectChip(u32 arg1, u32 arg2) {};\n" }, { "path": "firmware/mock_hardware/include/adc.h", "content": "#include \"types.h\"\n\nvoid init_adc(void);\nvoid adc_convert(u16 (*dst)[4]);" }, { "path": "firmware/mock_hardware/include/avr32/abi.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n * Revision : $Revision: 62595 $\n * Checkin Date : $Date: 2009-10-21 13:31:31 +0200 (Wed, 21 Oct 2009) $\n *\n ****************************************************************************/\n#ifndef AVR32_ABI_H_INCLUDED\n#define AVR32_ABI_H_INCLUDED\n\n\n/* The GNU assembler is ABI compliant*/\n#ifndef __AVR32_ABI_ASSEMBLER__\n# ifdef __GNUC__\n# ifdef __ASSEMBLER__\n# define __AVR32_ABI_ASSEMBLER__\n# endif\n# endif\n#endif\n\n/* The GNU C/C++ compiler is ABI compliant */\n#ifndef __AVR32_ABI_COMPILER__\n# ifdef __GNUC__\n# ifndef __ASSEMBLER__\n# define __AVR32_ABI_COMPILER__\n# endif\n# endif\n#endif\n\n\n/* The IAR Systems C/C++ Compiler is ABI compliant */\n#ifndef __AVR32_ABI_COMPILER__\n# ifdef __ICCAVR32__\n# define __AVR32_ABI_COMPILER__\n# endif\n#endif\n\n/* The IAR Systems Assembler is ABI compliant */\n#ifndef __AVR32_ABI_ASSEMBLER__\n# ifdef __AAVR32__\n# define __AVR32_ABI_ASSEMBLER__\n# endif\n#endif\n\n\n\n/*#ifndef AVR32_ABI_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/adc_200.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3A3128\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_ADC_200_H_INCLUDED\n#define AVR32_ADC_200_H_INCLUDED\n\n#define AVR32_ADC_H_VERSION 200\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_ADC_\n - Bitfield mask: AVR32_ADC__\n - Bitfield offset: AVR32_ADC___OFFSET\n - Bitfield size: AVR32_ADC___SIZE\n - Bitfield values: AVR32_ADC___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_ADC_\n - Bitfield offset: AVR32_ADC__OFFSET\n - Bitfield size: AVR32_ADC__SIZE\n - Bitfield values: AVR32_ADC__\n - Bitfield values: AVR32_ADC_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_ADC_CDR0 0x00000030\n#define AVR32_ADC_CDR0_DATA 0\n#define AVR32_ADC_CDR0_DATA_MASK 0x000003ff\n#define AVR32_ADC_CDR0_DATA_OFFSET 0\n#define AVR32_ADC_CDR0_DATA_SIZE 10\n#define AVR32_ADC_CDR1 0x00000034\n#define AVR32_ADC_CDR1_DATA 0\n#define AVR32_ADC_CDR1_DATA_MASK 0x000003ff\n#define AVR32_ADC_CDR1_DATA_OFFSET 0\n#define AVR32_ADC_CDR1_DATA_SIZE 10\n#define AVR32_ADC_CDR2 0x00000038\n#define AVR32_ADC_CDR2_DATA 0\n#define AVR32_ADC_CDR2_DATA_MASK 0x000003ff\n#define AVR32_ADC_CDR2_DATA_OFFSET 0\n#define AVR32_ADC_CDR2_DATA_SIZE 10\n#define AVR32_ADC_CDR3 0x0000003c\n#define AVR32_ADC_CDR3_DATA 0\n#define AVR32_ADC_CDR3_DATA_MASK 0x000003ff\n#define AVR32_ADC_CDR3_DATA_OFFSET 0\n#define AVR32_ADC_CDR3_DATA_SIZE 10\n#define AVR32_ADC_CDR4 0x00000040\n#define AVR32_ADC_CDR4_DATA 0\n#define AVR32_ADC_CDR4_DATA_MASK 0x000003ff\n#define AVR32_ADC_CDR4_DATA_OFFSET 0\n#define AVR32_ADC_CDR4_DATA_SIZE 10\n#define AVR32_ADC_CDR5 0x00000044\n#define AVR32_ADC_CDR5_DATA 0\n#define AVR32_ADC_CDR5_DATA_MASK 0x000003ff\n#define AVR32_ADC_CDR5_DATA_OFFSET 0\n#define AVR32_ADC_CDR5_DATA_SIZE 10\n#define AVR32_ADC_CDR6 0x00000048\n#define AVR32_ADC_CDR6_DATA 0\n#define AVR32_ADC_CDR6_DATA_MASK 0x000003ff\n#define AVR32_ADC_CDR6_DATA_OFFSET 0\n#define AVR32_ADC_CDR6_DATA_SIZE 10\n#define AVR32_ADC_CDR7 0x0000004c\n#define AVR32_ADC_CDR7_DATA 0\n#define AVR32_ADC_CDR7_DATA_MASK 0x000003ff\n#define AVR32_ADC_CDR7_DATA_OFFSET 0\n#define AVR32_ADC_CDR7_DATA_SIZE 10\n#define AVR32_ADC_CH0 0\n#define AVR32_ADC_CH0_MASK 0x00000001\n#define AVR32_ADC_CH0_OFFSET 0\n#define AVR32_ADC_CH0_SIZE 1\n#define AVR32_ADC_CH1 1\n#define AVR32_ADC_CH1_MASK 0x00000002\n#define AVR32_ADC_CH1_OFFSET 1\n#define AVR32_ADC_CH1_SIZE 1\n#define AVR32_ADC_CH2 2\n#define AVR32_ADC_CH2_MASK 0x00000004\n#define AVR32_ADC_CH2_OFFSET 2\n#define AVR32_ADC_CH2_SIZE 1\n#define AVR32_ADC_CH3 3\n#define AVR32_ADC_CH3_MASK 0x00000008\n#define AVR32_ADC_CH3_OFFSET 3\n#define AVR32_ADC_CH3_SIZE 1\n#define AVR32_ADC_CH4 4\n#define AVR32_ADC_CH4_MASK 0x00000010\n#define AVR32_ADC_CH4_OFFSET 4\n#define AVR32_ADC_CH4_SIZE 1\n#define AVR32_ADC_CH5 5\n#define AVR32_ADC_CH5_MASK 0x00000020\n#define AVR32_ADC_CH5_OFFSET 5\n#define AVR32_ADC_CH5_SIZE 1\n#define AVR32_ADC_CH6 6\n#define AVR32_ADC_CH6_MASK 0x00000040\n#define AVR32_ADC_CH6_OFFSET 6\n#define AVR32_ADC_CH6_SIZE 1\n#define AVR32_ADC_CH7 7\n#define AVR32_ADC_CH7_MASK 0x00000080\n#define AVR32_ADC_CH7_OFFSET 7\n#define AVR32_ADC_CH7_SIZE 1\n#define AVR32_ADC_CHDR 0x00000014\n#define AVR32_ADC_CHDR_CH0 0\n#define AVR32_ADC_CHDR_CH0_MASK 0x00000001\n#define AVR32_ADC_CHDR_CH0_OFFSET 0\n#define AVR32_ADC_CHDR_CH0_SIZE 1\n#define AVR32_ADC_CHDR_CH1 1\n#define AVR32_ADC_CHDR_CH1_MASK 0x00000002\n#define AVR32_ADC_CHDR_CH1_OFFSET 1\n#define AVR32_ADC_CHDR_CH1_SIZE 1\n#define AVR32_ADC_CHDR_CH2 2\n#define AVR32_ADC_CHDR_CH2_MASK 0x00000004\n#define AVR32_ADC_CHDR_CH2_OFFSET 2\n#define AVR32_ADC_CHDR_CH2_SIZE 1\n#define AVR32_ADC_CHDR_CH3 3\n#define AVR32_ADC_CHDR_CH3_MASK 0x00000008\n#define AVR32_ADC_CHDR_CH3_OFFSET 3\n#define AVR32_ADC_CHDR_CH3_SIZE 1\n#define AVR32_ADC_CHDR_CH4 4\n#define AVR32_ADC_CHDR_CH4_MASK 0x00000010\n#define AVR32_ADC_CHDR_CH4_OFFSET 4\n#define AVR32_ADC_CHDR_CH4_SIZE 1\n#define AVR32_ADC_CHDR_CH5 5\n#define AVR32_ADC_CHDR_CH5_MASK 0x00000020\n#define AVR32_ADC_CHDR_CH5_OFFSET 5\n#define AVR32_ADC_CHDR_CH5_SIZE 1\n#define AVR32_ADC_CHDR_CH6 6\n#define AVR32_ADC_CHDR_CH6_MASK 0x00000040\n#define AVR32_ADC_CHDR_CH6_OFFSET 6\n#define AVR32_ADC_CHDR_CH6_SIZE 1\n#define AVR32_ADC_CHDR_CH7 7\n#define AVR32_ADC_CHDR_CH7_MASK 0x00000080\n#define AVR32_ADC_CHDR_CH7_OFFSET 7\n#define AVR32_ADC_CHDR_CH7_SIZE 1\n#define AVR32_ADC_CHER 0x00000010\n#define AVR32_ADC_CHER_CH0 0\n#define AVR32_ADC_CHER_CH0_MASK 0x00000001\n#define AVR32_ADC_CHER_CH0_OFFSET 0\n#define AVR32_ADC_CHER_CH0_SIZE 1\n#define AVR32_ADC_CHER_CH1 1\n#define AVR32_ADC_CHER_CH1_MASK 0x00000002\n#define AVR32_ADC_CHER_CH1_OFFSET 1\n#define AVR32_ADC_CHER_CH1_SIZE 1\n#define AVR32_ADC_CHER_CH2 2\n#define AVR32_ADC_CHER_CH2_MASK 0x00000004\n#define AVR32_ADC_CHER_CH2_OFFSET 2\n#define AVR32_ADC_CHER_CH2_SIZE 1\n#define AVR32_ADC_CHER_CH3 3\n#define AVR32_ADC_CHER_CH3_MASK 0x00000008\n#define AVR32_ADC_CHER_CH3_OFFSET 3\n#define AVR32_ADC_CHER_CH3_SIZE 1\n#define AVR32_ADC_CHER_CH4 4\n#define AVR32_ADC_CHER_CH4_MASK 0x00000010\n#define AVR32_ADC_CHER_CH4_OFFSET 4\n#define AVR32_ADC_CHER_CH4_SIZE 1\n#define AVR32_ADC_CHER_CH5 5\n#define AVR32_ADC_CHER_CH5_MASK 0x00000020\n#define AVR32_ADC_CHER_CH5_OFFSET 5\n#define AVR32_ADC_CHER_CH5_SIZE 1\n#define AVR32_ADC_CHER_CH6 6\n#define AVR32_ADC_CHER_CH6_MASK 0x00000040\n#define AVR32_ADC_CHER_CH6_OFFSET 6\n#define AVR32_ADC_CHER_CH6_SIZE 1\n#define AVR32_ADC_CHER_CH7 7\n#define AVR32_ADC_CHER_CH7_MASK 0x00000080\n#define AVR32_ADC_CHER_CH7_OFFSET 7\n#define AVR32_ADC_CHER_CH7_SIZE 1\n#define AVR32_ADC_CHSR 0x00000018\n#define AVR32_ADC_CHSR_CH0 0\n#define AVR32_ADC_CHSR_CH0_MASK 0x00000001\n#define AVR32_ADC_CHSR_CH0_OFFSET 0\n#define AVR32_ADC_CHSR_CH0_SIZE 1\n#define AVR32_ADC_CHSR_CH1 1\n#define AVR32_ADC_CHSR_CH1_MASK 0x00000002\n#define AVR32_ADC_CHSR_CH1_OFFSET 1\n#define AVR32_ADC_CHSR_CH1_SIZE 1\n#define AVR32_ADC_CHSR_CH2 2\n#define AVR32_ADC_CHSR_CH2_MASK 0x00000004\n#define AVR32_ADC_CHSR_CH2_OFFSET 2\n#define AVR32_ADC_CHSR_CH2_SIZE 1\n#define AVR32_ADC_CHSR_CH3 3\n#define AVR32_ADC_CHSR_CH3_MASK 0x00000008\n#define AVR32_ADC_CHSR_CH3_OFFSET 3\n#define AVR32_ADC_CHSR_CH3_SIZE 1\n#define AVR32_ADC_CHSR_CH4 4\n#define AVR32_ADC_CHSR_CH4_MASK 0x00000010\n#define AVR32_ADC_CHSR_CH4_OFFSET 4\n#define AVR32_ADC_CHSR_CH4_SIZE 1\n#define AVR32_ADC_CHSR_CH5 5\n#define AVR32_ADC_CHSR_CH5_MASK 0x00000020\n#define AVR32_ADC_CHSR_CH5_OFFSET 5\n#define AVR32_ADC_CHSR_CH5_SIZE 1\n#define AVR32_ADC_CHSR_CH6 6\n#define AVR32_ADC_CHSR_CH6_MASK 0x00000040\n#define AVR32_ADC_CHSR_CH6_OFFSET 6\n#define AVR32_ADC_CHSR_CH6_SIZE 1\n#define AVR32_ADC_CHSR_CH7 7\n#define AVR32_ADC_CHSR_CH7_MASK 0x00000080\n#define AVR32_ADC_CHSR_CH7_OFFSET 7\n#define AVR32_ADC_CHSR_CH7_SIZE 1\n#define AVR32_ADC_CR 0x00000000\n#define AVR32_ADC_CR_START 1\n#define AVR32_ADC_CR_START_MASK 0x00000002\n#define AVR32_ADC_CR_START_OFFSET 1\n#define AVR32_ADC_CR_START_SIZE 1\n#define AVR32_ADC_CR_SWRST 0\n#define AVR32_ADC_CR_SWRST_MASK 0x00000001\n#define AVR32_ADC_CR_SWRST_OFFSET 0\n#define AVR32_ADC_CR_SWRST_SIZE 1\n#define AVR32_ADC_DATA 0\n#define AVR32_ADC_DATA_MASK 0x000003ff\n#define AVR32_ADC_DATA_OFFSET 0\n#define AVR32_ADC_DATA_SIZE 10\n#define AVR32_ADC_DRDY 16\n#define AVR32_ADC_DRDY_MASK 0x00010000\n#define AVR32_ADC_DRDY_OFFSET 16\n#define AVR32_ADC_DRDY_SIZE 1\n#define AVR32_ADC_ENDRX 18\n#define AVR32_ADC_ENDRX_MASK 0x00040000\n#define AVR32_ADC_ENDRX_OFFSET 18\n#define AVR32_ADC_ENDRX_SIZE 1\n#define AVR32_ADC_EOC0 0\n#define AVR32_ADC_EOC0_MASK 0x00000001\n#define AVR32_ADC_EOC0_OFFSET 0\n#define AVR32_ADC_EOC0_SIZE 1\n#define AVR32_ADC_EOC1 1\n#define AVR32_ADC_EOC1_MASK 0x00000002\n#define AVR32_ADC_EOC1_OFFSET 1\n#define AVR32_ADC_EOC1_SIZE 1\n#define AVR32_ADC_EOC2 2\n#define AVR32_ADC_EOC2_MASK 0x00000004\n#define AVR32_ADC_EOC2_OFFSET 2\n#define AVR32_ADC_EOC2_SIZE 1\n#define AVR32_ADC_EOC3 3\n#define AVR32_ADC_EOC3_MASK 0x00000008\n#define AVR32_ADC_EOC3_OFFSET 3\n#define AVR32_ADC_EOC3_SIZE 1\n#define AVR32_ADC_EOC4 4\n#define AVR32_ADC_EOC4_MASK 0x00000010\n#define AVR32_ADC_EOC4_OFFSET 4\n#define AVR32_ADC_EOC4_SIZE 1\n#define AVR32_ADC_EOC5 5\n#define AVR32_ADC_EOC5_MASK 0x00000020\n#define AVR32_ADC_EOC5_OFFSET 5\n#define AVR32_ADC_EOC5_SIZE 1\n#define AVR32_ADC_EOC6 6\n#define AVR32_ADC_EOC6_MASK 0x00000040\n#define AVR32_ADC_EOC6_OFFSET 6\n#define AVR32_ADC_EOC6_SIZE 1\n#define AVR32_ADC_EOC7 7\n#define AVR32_ADC_EOC7_MASK 0x00000080\n#define AVR32_ADC_EOC7_OFFSET 7\n#define AVR32_ADC_EOC7_SIZE 1\n#define AVR32_ADC_GOVRE 17\n#define AVR32_ADC_GOVRE_MASK 0x00020000\n#define AVR32_ADC_GOVRE_OFFSET 17\n#define AVR32_ADC_GOVRE_SIZE 1\n#define AVR32_ADC_IDR 0x00000028\n#define AVR32_ADC_IDR_DRDY 16\n#define AVR32_ADC_IDR_DRDY_MASK 0x00010000\n#define AVR32_ADC_IDR_DRDY_OFFSET 16\n#define AVR32_ADC_IDR_DRDY_SIZE 1\n#define AVR32_ADC_IDR_ENDRX 18\n#define AVR32_ADC_IDR_ENDRX_MASK 0x00040000\n#define AVR32_ADC_IDR_ENDRX_OFFSET 18\n#define AVR32_ADC_IDR_ENDRX_SIZE 1\n#define AVR32_ADC_IDR_EOC0 0\n#define AVR32_ADC_IDR_EOC0_MASK 0x00000001\n#define AVR32_ADC_IDR_EOC0_OFFSET 0\n#define AVR32_ADC_IDR_EOC0_SIZE 1\n#define AVR32_ADC_IDR_EOC1 1\n#define AVR32_ADC_IDR_EOC1_MASK 0x00000002\n#define AVR32_ADC_IDR_EOC1_OFFSET 1\n#define AVR32_ADC_IDR_EOC1_SIZE 1\n#define AVR32_ADC_IDR_EOC2 2\n#define AVR32_ADC_IDR_EOC2_MASK 0x00000004\n#define AVR32_ADC_IDR_EOC2_OFFSET 2\n#define AVR32_ADC_IDR_EOC2_SIZE 1\n#define AVR32_ADC_IDR_EOC3 3\n#define AVR32_ADC_IDR_EOC3_MASK 0x00000008\n#define AVR32_ADC_IDR_EOC3_OFFSET 3\n#define AVR32_ADC_IDR_EOC3_SIZE 1\n#define AVR32_ADC_IDR_EOC4 4\n#define AVR32_ADC_IDR_EOC4_MASK 0x00000010\n#define AVR32_ADC_IDR_EOC4_OFFSET 4\n#define AVR32_ADC_IDR_EOC4_SIZE 1\n#define AVR32_ADC_IDR_EOC5 5\n#define AVR32_ADC_IDR_EOC5_MASK 0x00000020\n#define AVR32_ADC_IDR_EOC5_OFFSET 5\n#define AVR32_ADC_IDR_EOC5_SIZE 1\n#define AVR32_ADC_IDR_EOC6 6\n#define AVR32_ADC_IDR_EOC6_MASK 0x00000040\n#define AVR32_ADC_IDR_EOC6_OFFSET 6\n#define AVR32_ADC_IDR_EOC6_SIZE 1\n#define AVR32_ADC_IDR_EOC7 7\n#define AVR32_ADC_IDR_EOC7_MASK 0x00000080\n#define AVR32_ADC_IDR_EOC7_OFFSET 7\n#define AVR32_ADC_IDR_EOC7_SIZE 1\n#define AVR32_ADC_IDR_GOVRE 17\n#define AVR32_ADC_IDR_GOVRE_MASK 0x00020000\n#define AVR32_ADC_IDR_GOVRE_OFFSET 17\n#define AVR32_ADC_IDR_GOVRE_SIZE 1\n#define AVR32_ADC_IDR_OVRE0 8\n#define AVR32_ADC_IDR_OVRE0_MASK 0x00000100\n#define AVR32_ADC_IDR_OVRE0_OFFSET 8\n#define AVR32_ADC_IDR_OVRE0_SIZE 1\n#define AVR32_ADC_IDR_OVRE1 9\n#define AVR32_ADC_IDR_OVRE1_MASK 0x00000200\n#define AVR32_ADC_IDR_OVRE1_OFFSET 9\n#define AVR32_ADC_IDR_OVRE1_SIZE 1\n#define AVR32_ADC_IDR_OVRE2 10\n#define AVR32_ADC_IDR_OVRE2_MASK 0x00000400\n#define AVR32_ADC_IDR_OVRE2_OFFSET 10\n#define AVR32_ADC_IDR_OVRE2_SIZE 1\n#define AVR32_ADC_IDR_OVRE3 11\n#define AVR32_ADC_IDR_OVRE3_MASK 0x00000800\n#define AVR32_ADC_IDR_OVRE3_OFFSET 11\n#define AVR32_ADC_IDR_OVRE3_SIZE 1\n#define AVR32_ADC_IDR_OVRE4 12\n#define AVR32_ADC_IDR_OVRE4_MASK 0x00001000\n#define AVR32_ADC_IDR_OVRE4_OFFSET 12\n#define AVR32_ADC_IDR_OVRE4_SIZE 1\n#define AVR32_ADC_IDR_OVRE5 13\n#define AVR32_ADC_IDR_OVRE5_MASK 0x00002000\n#define AVR32_ADC_IDR_OVRE5_OFFSET 13\n#define AVR32_ADC_IDR_OVRE5_SIZE 1\n#define AVR32_ADC_IDR_OVRE6 14\n#define AVR32_ADC_IDR_OVRE6_MASK 0x00004000\n#define AVR32_ADC_IDR_OVRE6_OFFSET 14\n#define AVR32_ADC_IDR_OVRE6_SIZE 1\n#define AVR32_ADC_IDR_OVRE7 15\n#define AVR32_ADC_IDR_OVRE7_MASK 0x00008000\n#define AVR32_ADC_IDR_OVRE7_OFFSET 15\n#define AVR32_ADC_IDR_OVRE7_SIZE 1\n#define AVR32_ADC_IDR_RXBUFF 19\n#define AVR32_ADC_IDR_RXBUFF_MASK 0x00080000\n#define AVR32_ADC_IDR_RXBUFF_OFFSET 19\n#define AVR32_ADC_IDR_RXBUFF_SIZE 1\n#define AVR32_ADC_IER 0x00000024\n#define AVR32_ADC_IER_DRDY 16\n#define AVR32_ADC_IER_DRDY_MASK 0x00010000\n#define AVR32_ADC_IER_DRDY_OFFSET 16\n#define AVR32_ADC_IER_DRDY_SIZE 1\n#define AVR32_ADC_IER_ENDRX 18\n#define AVR32_ADC_IER_ENDRX_MASK 0x00040000\n#define AVR32_ADC_IER_ENDRX_OFFSET 18\n#define AVR32_ADC_IER_ENDRX_SIZE 1\n#define AVR32_ADC_IER_EOC0 0\n#define AVR32_ADC_IER_EOC0_MASK 0x00000001\n#define AVR32_ADC_IER_EOC0_OFFSET 0\n#define AVR32_ADC_IER_EOC0_SIZE 1\n#define AVR32_ADC_IER_EOC1 1\n#define AVR32_ADC_IER_EOC1_MASK 0x00000002\n#define AVR32_ADC_IER_EOC1_OFFSET 1\n#define AVR32_ADC_IER_EOC1_SIZE 1\n#define AVR32_ADC_IER_EOC2 2\n#define AVR32_ADC_IER_EOC2_MASK 0x00000004\n#define AVR32_ADC_IER_EOC2_OFFSET 2\n#define AVR32_ADC_IER_EOC2_SIZE 1\n#define AVR32_ADC_IER_EOC3 3\n#define AVR32_ADC_IER_EOC3_MASK 0x00000008\n#define AVR32_ADC_IER_EOC3_OFFSET 3\n#define AVR32_ADC_IER_EOC3_SIZE 1\n#define AVR32_ADC_IER_EOC4 4\n#define AVR32_ADC_IER_EOC4_MASK 0x00000010\n#define AVR32_ADC_IER_EOC4_OFFSET 4\n#define AVR32_ADC_IER_EOC4_SIZE 1\n#define AVR32_ADC_IER_EOC5 5\n#define AVR32_ADC_IER_EOC5_MASK 0x00000020\n#define AVR32_ADC_IER_EOC5_OFFSET 5\n#define AVR32_ADC_IER_EOC5_SIZE 1\n#define AVR32_ADC_IER_EOC6 6\n#define AVR32_ADC_IER_EOC6_MASK 0x00000040\n#define AVR32_ADC_IER_EOC6_OFFSET 6\n#define AVR32_ADC_IER_EOC6_SIZE 1\n#define AVR32_ADC_IER_EOC7 7\n#define AVR32_ADC_IER_EOC7_MASK 0x00000080\n#define AVR32_ADC_IER_EOC7_OFFSET 7\n#define AVR32_ADC_IER_EOC7_SIZE 1\n#define AVR32_ADC_IER_GOVRE 17\n#define AVR32_ADC_IER_GOVRE_MASK 0x00020000\n#define AVR32_ADC_IER_GOVRE_OFFSET 17\n#define AVR32_ADC_IER_GOVRE_SIZE 1\n#define AVR32_ADC_IER_OVRE0 8\n#define AVR32_ADC_IER_OVRE0_MASK 0x00000100\n#define AVR32_ADC_IER_OVRE0_OFFSET 8\n#define AVR32_ADC_IER_OVRE0_SIZE 1\n#define AVR32_ADC_IER_OVRE1 9\n#define AVR32_ADC_IER_OVRE1_MASK 0x00000200\n#define AVR32_ADC_IER_OVRE1_OFFSET 9\n#define AVR32_ADC_IER_OVRE1_SIZE 1\n#define AVR32_ADC_IER_OVRE2 10\n#define AVR32_ADC_IER_OVRE2_MASK 0x00000400\n#define AVR32_ADC_IER_OVRE2_OFFSET 10\n#define AVR32_ADC_IER_OVRE2_SIZE 1\n#define AVR32_ADC_IER_OVRE3 11\n#define AVR32_ADC_IER_OVRE3_MASK 0x00000800\n#define AVR32_ADC_IER_OVRE3_OFFSET 11\n#define AVR32_ADC_IER_OVRE3_SIZE 1\n#define AVR32_ADC_IER_OVRE4 12\n#define AVR32_ADC_IER_OVRE4_MASK 0x00001000\n#define AVR32_ADC_IER_OVRE4_OFFSET 12\n#define AVR32_ADC_IER_OVRE4_SIZE 1\n#define AVR32_ADC_IER_OVRE5 13\n#define AVR32_ADC_IER_OVRE5_MASK 0x00002000\n#define AVR32_ADC_IER_OVRE5_OFFSET 13\n#define AVR32_ADC_IER_OVRE5_SIZE 1\n#define AVR32_ADC_IER_OVRE6 14\n#define AVR32_ADC_IER_OVRE6_MASK 0x00004000\n#define AVR32_ADC_IER_OVRE6_OFFSET 14\n#define AVR32_ADC_IER_OVRE6_SIZE 1\n#define AVR32_ADC_IER_OVRE7 15\n#define AVR32_ADC_IER_OVRE7_MASK 0x00008000\n#define AVR32_ADC_IER_OVRE7_OFFSET 15\n#define AVR32_ADC_IER_OVRE7_SIZE 1\n#define AVR32_ADC_IER_RXBUFF 19\n#define AVR32_ADC_IER_RXBUFF_MASK 0x00080000\n#define AVR32_ADC_IER_RXBUFF_OFFSET 19\n#define AVR32_ADC_IER_RXBUFF_SIZE 1\n#define AVR32_ADC_IMR 0x0000002c\n#define AVR32_ADC_IMR_DRDY 16\n#define AVR32_ADC_IMR_DRDY_MASK 0x00010000\n#define AVR32_ADC_IMR_DRDY_OFFSET 16\n#define AVR32_ADC_IMR_DRDY_SIZE 1\n#define AVR32_ADC_IMR_ENDRX 18\n#define AVR32_ADC_IMR_ENDRX_MASK 0x00040000\n#define AVR32_ADC_IMR_ENDRX_OFFSET 18\n#define AVR32_ADC_IMR_ENDRX_SIZE 1\n#define AVR32_ADC_IMR_EOC0 0\n#define AVR32_ADC_IMR_EOC0_MASK 0x00000001\n#define AVR32_ADC_IMR_EOC0_OFFSET 0\n#define AVR32_ADC_IMR_EOC0_SIZE 1\n#define AVR32_ADC_IMR_EOC1 1\n#define AVR32_ADC_IMR_EOC1_MASK 0x00000002\n#define AVR32_ADC_IMR_EOC1_OFFSET 1\n#define AVR32_ADC_IMR_EOC1_SIZE 1\n#define AVR32_ADC_IMR_EOC2 2\n#define AVR32_ADC_IMR_EOC2_MASK 0x00000004\n#define AVR32_ADC_IMR_EOC2_OFFSET 2\n#define AVR32_ADC_IMR_EOC2_SIZE 1\n#define AVR32_ADC_IMR_EOC3 3\n#define AVR32_ADC_IMR_EOC3_MASK 0x00000008\n#define AVR32_ADC_IMR_EOC3_OFFSET 3\n#define AVR32_ADC_IMR_EOC3_SIZE 1\n#define AVR32_ADC_IMR_EOC4 4\n#define AVR32_ADC_IMR_EOC4_MASK 0x00000010\n#define AVR32_ADC_IMR_EOC4_OFFSET 4\n#define AVR32_ADC_IMR_EOC4_SIZE 1\n#define AVR32_ADC_IMR_EOC5 5\n#define AVR32_ADC_IMR_EOC5_MASK 0x00000020\n#define AVR32_ADC_IMR_EOC5_OFFSET 5\n#define AVR32_ADC_IMR_EOC5_SIZE 1\n#define AVR32_ADC_IMR_EOC6 6\n#define AVR32_ADC_IMR_EOC6_MASK 0x00000040\n#define AVR32_ADC_IMR_EOC6_OFFSET 6\n#define AVR32_ADC_IMR_EOC6_SIZE 1\n#define AVR32_ADC_IMR_EOC7 7\n#define AVR32_ADC_IMR_EOC7_MASK 0x00000080\n#define AVR32_ADC_IMR_EOC7_OFFSET 7\n#define AVR32_ADC_IMR_EOC7_SIZE 1\n#define AVR32_ADC_IMR_GOVRE 17\n#define AVR32_ADC_IMR_GOVRE_MASK 0x00020000\n#define AVR32_ADC_IMR_GOVRE_OFFSET 17\n#define AVR32_ADC_IMR_GOVRE_SIZE 1\n#define AVR32_ADC_IMR_OVRE0 8\n#define AVR32_ADC_IMR_OVRE0_MASK 0x00000100\n#define AVR32_ADC_IMR_OVRE0_OFFSET 8\n#define AVR32_ADC_IMR_OVRE0_SIZE 1\n#define AVR32_ADC_IMR_OVRE1 9\n#define AVR32_ADC_IMR_OVRE1_MASK 0x00000200\n#define AVR32_ADC_IMR_OVRE1_OFFSET 9\n#define AVR32_ADC_IMR_OVRE1_SIZE 1\n#define AVR32_ADC_IMR_OVRE2 10\n#define AVR32_ADC_IMR_OVRE2_MASK 0x00000400\n#define AVR32_ADC_IMR_OVRE2_OFFSET 10\n#define AVR32_ADC_IMR_OVRE2_SIZE 1\n#define AVR32_ADC_IMR_OVRE3 11\n#define AVR32_ADC_IMR_OVRE3_MASK 0x00000800\n#define AVR32_ADC_IMR_OVRE3_OFFSET 11\n#define AVR32_ADC_IMR_OVRE3_SIZE 1\n#define AVR32_ADC_IMR_OVRE4 12\n#define AVR32_ADC_IMR_OVRE4_MASK 0x00001000\n#define AVR32_ADC_IMR_OVRE4_OFFSET 12\n#define AVR32_ADC_IMR_OVRE4_SIZE 1\n#define AVR32_ADC_IMR_OVRE5 13\n#define AVR32_ADC_IMR_OVRE5_MASK 0x00002000\n#define AVR32_ADC_IMR_OVRE5_OFFSET 13\n#define AVR32_ADC_IMR_OVRE5_SIZE 1\n#define AVR32_ADC_IMR_OVRE6 14\n#define AVR32_ADC_IMR_OVRE6_MASK 0x00004000\n#define AVR32_ADC_IMR_OVRE6_OFFSET 14\n#define AVR32_ADC_IMR_OVRE6_SIZE 1\n#define AVR32_ADC_IMR_OVRE7 15\n#define AVR32_ADC_IMR_OVRE7_MASK 0x00008000\n#define AVR32_ADC_IMR_OVRE7_OFFSET 15\n#define AVR32_ADC_IMR_OVRE7_SIZE 1\n#define AVR32_ADC_IMR_RXBUFF 19\n#define AVR32_ADC_IMR_RXBUFF_MASK 0x00080000\n#define AVR32_ADC_IMR_RXBUFF_OFFSET 19\n#define AVR32_ADC_IMR_RXBUFF_SIZE 1\n#define AVR32_ADC_LCDR 0x00000020\n#define AVR32_ADC_LCDR_LDATA 0\n#define AVR32_ADC_LCDR_LDATA_MASK 0x000003ff\n#define AVR32_ADC_LCDR_LDATA_OFFSET 0\n#define AVR32_ADC_LCDR_LDATA_SIZE 10\n#define AVR32_ADC_LDATA 0\n#define AVR32_ADC_LDATA_MASK 0x000003ff\n#define AVR32_ADC_LDATA_OFFSET 0\n#define AVR32_ADC_LDATA_SIZE 10\n#define AVR32_ADC_LOWRES 4\n#define AVR32_ADC_LOWRES_MASK 0x00000010\n#define AVR32_ADC_LOWRES_OFFSET 4\n#define AVR32_ADC_LOWRES_SIZE 1\n#define AVR32_ADC_MR 0x00000004\n#define AVR32_ADC_MR_LOWRES 4\n#define AVR32_ADC_MR_LOWRES_MASK 0x00000010\n#define AVR32_ADC_MR_LOWRES_OFFSET 4\n#define AVR32_ADC_MR_LOWRES_SIZE 1\n#define AVR32_ADC_MR_PRESCAL 8\n#define AVR32_ADC_MR_PRESCAL_MASK 0x0000ff00\n#define AVR32_ADC_MR_PRESCAL_OFFSET 8\n#define AVR32_ADC_MR_PRESCAL_SIZE 8\n#define AVR32_ADC_MR_SHTIM 24\n#define AVR32_ADC_MR_SHTIM_MASK 0x0f000000\n#define AVR32_ADC_MR_SHTIM_OFFSET 24\n#define AVR32_ADC_MR_SHTIM_SIZE 4\n#define AVR32_ADC_MR_SLEEP 5\n#define AVR32_ADC_MR_SLEEP_MASK 0x00000020\n#define AVR32_ADC_MR_SLEEP_OFFSET 5\n#define AVR32_ADC_MR_SLEEP_SIZE 1\n#define AVR32_ADC_MR_STARTUP 16\n#define AVR32_ADC_MR_STARTUP_MASK 0x007f0000\n#define AVR32_ADC_MR_STARTUP_OFFSET 16\n#define AVR32_ADC_MR_STARTUP_SIZE 7\n#define AVR32_ADC_MR_TRGEN 0\n#define AVR32_ADC_MR_TRGEN_MASK 0x00000001\n#define AVR32_ADC_MR_TRGEN_OFFSET 0\n#define AVR32_ADC_MR_TRGEN_SIZE 1\n#define AVR32_ADC_MR_TRGSEL 1\n#define AVR32_ADC_MR_TRGSEL_MASK 0x0000000e\n#define AVR32_ADC_MR_TRGSEL_OFFSET 1\n#define AVR32_ADC_MR_TRGSEL_SIZE 3\n#define AVR32_ADC_OVRE0 8\n#define AVR32_ADC_OVRE0_MASK 0x00000100\n#define AVR32_ADC_OVRE0_OFFSET 8\n#define AVR32_ADC_OVRE0_SIZE 1\n#define AVR32_ADC_OVRE1 9\n#define AVR32_ADC_OVRE1_MASK 0x00000200\n#define AVR32_ADC_OVRE1_OFFSET 9\n#define AVR32_ADC_OVRE1_SIZE 1\n#define AVR32_ADC_OVRE2 10\n#define AVR32_ADC_OVRE2_MASK 0x00000400\n#define AVR32_ADC_OVRE2_OFFSET 10\n#define AVR32_ADC_OVRE2_SIZE 1\n#define AVR32_ADC_OVRE3 11\n#define AVR32_ADC_OVRE3_MASK 0x00000800\n#define AVR32_ADC_OVRE3_OFFSET 11\n#define AVR32_ADC_OVRE3_SIZE 1\n#define AVR32_ADC_OVRE4 12\n#define AVR32_ADC_OVRE4_MASK 0x00001000\n#define AVR32_ADC_OVRE4_OFFSET 12\n#define AVR32_ADC_OVRE4_SIZE 1\n#define AVR32_ADC_OVRE5 13\n#define AVR32_ADC_OVRE5_MASK 0x00002000\n#define AVR32_ADC_OVRE5_OFFSET 13\n#define AVR32_ADC_OVRE5_SIZE 1\n#define AVR32_ADC_OVRE6 14\n#define AVR32_ADC_OVRE6_MASK 0x00004000\n#define AVR32_ADC_OVRE6_OFFSET 14\n#define AVR32_ADC_OVRE6_SIZE 1\n#define AVR32_ADC_OVRE7 15\n#define AVR32_ADC_OVRE7_MASK 0x00008000\n#define AVR32_ADC_OVRE7_OFFSET 15\n#define AVR32_ADC_OVRE7_SIZE 1\n#define AVR32_ADC_PRESCAL 8\n#define AVR32_ADC_PRESCAL_MASK 0x0000ff00\n#define AVR32_ADC_PRESCAL_OFFSET 8\n#define AVR32_ADC_PRESCAL_SIZE 8\n#define AVR32_ADC_RXBUFF 19\n#define AVR32_ADC_RXBUFF_MASK 0x00080000\n#define AVR32_ADC_RXBUFF_OFFSET 19\n#define AVR32_ADC_RXBUFF_SIZE 1\n#define AVR32_ADC_SHTIM 24\n#define AVR32_ADC_SHTIM_MASK 0x0f000000\n#define AVR32_ADC_SHTIM_OFFSET 24\n#define AVR32_ADC_SHTIM_SIZE 4\n#define AVR32_ADC_SLEEP 5\n#define AVR32_ADC_SLEEP_MASK 0x00000020\n#define AVR32_ADC_SLEEP_OFFSET 5\n#define AVR32_ADC_SLEEP_SIZE 1\n#define AVR32_ADC_SR 0x0000001c\n#define AVR32_ADC_SR_DRDY 16\n#define AVR32_ADC_SR_DRDY_MASK 0x00010000\n#define AVR32_ADC_SR_DRDY_OFFSET 16\n#define AVR32_ADC_SR_DRDY_SIZE 1\n#define AVR32_ADC_SR_ENDRX 18\n#define AVR32_ADC_SR_ENDRX_MASK 0x00040000\n#define AVR32_ADC_SR_ENDRX_OFFSET 18\n#define AVR32_ADC_SR_ENDRX_SIZE 1\n#define AVR32_ADC_SR_EOC0 0\n#define AVR32_ADC_SR_EOC0_MASK 0x00000001\n#define AVR32_ADC_SR_EOC0_OFFSET 0\n#define AVR32_ADC_SR_EOC0_SIZE 1\n#define AVR32_ADC_SR_EOC1 1\n#define AVR32_ADC_SR_EOC1_MASK 0x00000002\n#define AVR32_ADC_SR_EOC1_OFFSET 1\n#define AVR32_ADC_SR_EOC1_SIZE 1\n#define AVR32_ADC_SR_EOC2 2\n#define AVR32_ADC_SR_EOC2_MASK 0x00000004\n#define AVR32_ADC_SR_EOC2_OFFSET 2\n#define AVR32_ADC_SR_EOC2_SIZE 1\n#define AVR32_ADC_SR_EOC3 3\n#define AVR32_ADC_SR_EOC3_MASK 0x00000008\n#define AVR32_ADC_SR_EOC3_OFFSET 3\n#define AVR32_ADC_SR_EOC3_SIZE 1\n#define AVR32_ADC_SR_EOC4 4\n#define AVR32_ADC_SR_EOC4_MASK 0x00000010\n#define AVR32_ADC_SR_EOC4_OFFSET 4\n#define AVR32_ADC_SR_EOC4_SIZE 1\n#define AVR32_ADC_SR_EOC5 5\n#define AVR32_ADC_SR_EOC5_MASK 0x00000020\n#define AVR32_ADC_SR_EOC5_OFFSET 5\n#define AVR32_ADC_SR_EOC5_SIZE 1\n#define AVR32_ADC_SR_EOC6 6\n#define AVR32_ADC_SR_EOC6_MASK 0x00000040\n#define AVR32_ADC_SR_EOC6_OFFSET 6\n#define AVR32_ADC_SR_EOC6_SIZE 1\n#define AVR32_ADC_SR_EOC7 7\n#define AVR32_ADC_SR_EOC7_MASK 0x00000080\n#define AVR32_ADC_SR_EOC7_OFFSET 7\n#define AVR32_ADC_SR_EOC7_SIZE 1\n#define AVR32_ADC_SR_GOVRE 17\n#define AVR32_ADC_SR_GOVRE_MASK 0x00020000\n#define AVR32_ADC_SR_GOVRE_OFFSET 17\n#define AVR32_ADC_SR_GOVRE_SIZE 1\n#define AVR32_ADC_SR_OVRE0 8\n#define AVR32_ADC_SR_OVRE0_MASK 0x00000100\n#define AVR32_ADC_SR_OVRE0_OFFSET 8\n#define AVR32_ADC_SR_OVRE0_SIZE 1\n#define AVR32_ADC_SR_OVRE1 9\n#define AVR32_ADC_SR_OVRE1_MASK 0x00000200\n#define AVR32_ADC_SR_OVRE1_OFFSET 9\n#define AVR32_ADC_SR_OVRE1_SIZE 1\n#define AVR32_ADC_SR_OVRE2 10\n#define AVR32_ADC_SR_OVRE2_MASK 0x00000400\n#define AVR32_ADC_SR_OVRE2_OFFSET 10\n#define AVR32_ADC_SR_OVRE2_SIZE 1\n#define AVR32_ADC_SR_OVRE3 11\n#define AVR32_ADC_SR_OVRE3_MASK 0x00000800\n#define AVR32_ADC_SR_OVRE3_OFFSET 11\n#define AVR32_ADC_SR_OVRE3_SIZE 1\n#define AVR32_ADC_SR_OVRE4 12\n#define AVR32_ADC_SR_OVRE4_MASK 0x00001000\n#define AVR32_ADC_SR_OVRE4_OFFSET 12\n#define AVR32_ADC_SR_OVRE4_SIZE 1\n#define AVR32_ADC_SR_OVRE5 13\n#define AVR32_ADC_SR_OVRE5_MASK 0x00002000\n#define AVR32_ADC_SR_OVRE5_OFFSET 13\n#define AVR32_ADC_SR_OVRE5_SIZE 1\n#define AVR32_ADC_SR_OVRE6 14\n#define AVR32_ADC_SR_OVRE6_MASK 0x00004000\n#define AVR32_ADC_SR_OVRE6_OFFSET 14\n#define AVR32_ADC_SR_OVRE6_SIZE 1\n#define AVR32_ADC_SR_OVRE7 15\n#define AVR32_ADC_SR_OVRE7_MASK 0x00008000\n#define AVR32_ADC_SR_OVRE7_OFFSET 15\n#define AVR32_ADC_SR_OVRE7_SIZE 1\n#define AVR32_ADC_SR_RXBUFF 19\n#define AVR32_ADC_SR_RXBUFF_MASK 0x00080000\n#define AVR32_ADC_SR_RXBUFF_OFFSET 19\n#define AVR32_ADC_SR_RXBUFF_SIZE 1\n#define AVR32_ADC_START 1\n#define AVR32_ADC_STARTUP 16\n#define AVR32_ADC_STARTUP_MASK 0x007f0000\n#define AVR32_ADC_STARTUP_OFFSET 16\n#define AVR32_ADC_STARTUP_SIZE 7\n#define AVR32_ADC_START_MASK 0x00000002\n#define AVR32_ADC_START_OFFSET 1\n#define AVR32_ADC_START_SIZE 1\n#define AVR32_ADC_SWRST 0\n#define AVR32_ADC_SWRST_MASK 0x00000001\n#define AVR32_ADC_SWRST_OFFSET 0\n#define AVR32_ADC_SWRST_SIZE 1\n#define AVR32_ADC_TRGEN 0\n#define AVR32_ADC_TRGEN_MASK 0x00000001\n#define AVR32_ADC_TRGEN_OFFSET 0\n#define AVR32_ADC_TRGEN_SIZE 1\n#define AVR32_ADC_TRGSEL 1\n#define AVR32_ADC_TRGSEL_MASK 0x0000000e\n#define AVR32_ADC_TRGSEL_OFFSET 1\n#define AVR32_ADC_TRGSEL_SIZE 3\n#define AVR32_ADC_VARIANT 16\n#define AVR32_ADC_VARIANT_MASK 0x00070000\n#define AVR32_ADC_VARIANT_OFFSET 16\n#define AVR32_ADC_VARIANT_SIZE 3\n#define AVR32_ADC_VERSION 0x000000fc\n#define AVR32_ADC_VERSION_MASK 0x00000fff\n#define AVR32_ADC_VERSION_OFFSET 0\n#define AVR32_ADC_VERSION_SIZE 12\n#define AVR32_ADC_VERSION_VARIANT 16\n#define AVR32_ADC_VERSION_VARIANT_MASK 0x00070000\n#define AVR32_ADC_VERSION_VARIANT_OFFSET 16\n#define AVR32_ADC_VERSION_VARIANT_SIZE 3\n#define AVR32_ADC_VERSION_VERSION 0\n#define AVR32_ADC_VERSION_VERSION_MASK 0x00000fff\n#define AVR32_ADC_VERSION_VERSION_OFFSET 0\n#define AVR32_ADC_VERSION_VERSION_SIZE 12\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_adc_cr_t {\n unsigned int :30;\n unsigned int start : 1;\n unsigned int swrst : 1;\n} avr32_adc_cr_t;\n\n\n\ntypedef struct avr32_adc_mr_t {\n unsigned int : 4;\n unsigned int shtim : 4;\n unsigned int : 1;\n unsigned int startup : 7;\n unsigned int prescal : 8;\n unsigned int : 2;\n unsigned int sleep : 1;\n unsigned int lowres : 1;\n unsigned int trgsel : 3;\n unsigned int trgen : 1;\n} avr32_adc_mr_t;\n\n\n\ntypedef struct avr32_adc_cher_t {\n unsigned int :24;\n unsigned int ch7 : 1;\n unsigned int ch6 : 1;\n unsigned int ch5 : 1;\n unsigned int ch4 : 1;\n unsigned int ch3 : 1;\n unsigned int ch2 : 1;\n unsigned int ch1 : 1;\n unsigned int ch0 : 1;\n} avr32_adc_cher_t;\n\n\n\ntypedef struct avr32_adc_chdr_t {\n unsigned int :24;\n unsigned int ch7 : 1;\n unsigned int ch6 : 1;\n unsigned int ch5 : 1;\n unsigned int ch4 : 1;\n unsigned int ch3 : 1;\n unsigned int ch2 : 1;\n unsigned int ch1 : 1;\n unsigned int ch0 : 1;\n} avr32_adc_chdr_t;\n\n\n\ntypedef struct avr32_adc_chsr_t {\n unsigned int :24;\n unsigned int ch7 : 1;\n unsigned int ch6 : 1;\n unsigned int ch5 : 1;\n unsigned int ch4 : 1;\n unsigned int ch3 : 1;\n unsigned int ch2 : 1;\n unsigned int ch1 : 1;\n unsigned int ch0 : 1;\n} avr32_adc_chsr_t;\n\n\n\ntypedef struct avr32_adc_sr_t {\n unsigned int :12;\n unsigned int rxbuff : 1;\n unsigned int endrx : 1;\n unsigned int govre : 1;\n unsigned int drdy : 1;\n unsigned int ovre7 : 1;\n unsigned int ovre6 : 1;\n unsigned int ovre5 : 1;\n unsigned int ovre4 : 1;\n unsigned int ovre3 : 1;\n unsigned int ovre2 : 1;\n unsigned int ovre1 : 1;\n unsigned int ovre0 : 1;\n unsigned int eoc7 : 1;\n unsigned int eoc6 : 1;\n unsigned int eoc5 : 1;\n unsigned int eoc4 : 1;\n unsigned int eoc3 : 1;\n unsigned int eoc2 : 1;\n unsigned int eoc1 : 1;\n unsigned int eoc0 : 1;\n} avr32_adc_sr_t;\n\n\n\ntypedef struct avr32_adc_lcdr_t {\n unsigned int :22;\n unsigned int ldata :10;\n} avr32_adc_lcdr_t;\n\n\n\ntypedef struct avr32_adc_ier_t {\n unsigned int :12;\n unsigned int rxbuff : 1;\n unsigned int endrx : 1;\n unsigned int govre : 1;\n unsigned int drdy : 1;\n unsigned int ovre7 : 1;\n unsigned int ovre6 : 1;\n unsigned int ovre5 : 1;\n unsigned int ovre4 : 1;\n unsigned int ovre3 : 1;\n unsigned int ovre2 : 1;\n unsigned int ovre1 : 1;\n unsigned int ovre0 : 1;\n unsigned int eoc7 : 1;\n unsigned int eoc6 : 1;\n unsigned int eoc5 : 1;\n unsigned int eoc4 : 1;\n unsigned int eoc3 : 1;\n unsigned int eoc2 : 1;\n unsigned int eoc1 : 1;\n unsigned int eoc0 : 1;\n} avr32_adc_ier_t;\n\n\n\ntypedef struct avr32_adc_idr_t {\n unsigned int :12;\n unsigned int rxbuff : 1;\n unsigned int endrx : 1;\n unsigned int govre : 1;\n unsigned int drdy : 1;\n unsigned int ovre7 : 1;\n unsigned int ovre6 : 1;\n unsigned int ovre5 : 1;\n unsigned int ovre4 : 1;\n unsigned int ovre3 : 1;\n unsigned int ovre2 : 1;\n unsigned int ovre1 : 1;\n unsigned int ovre0 : 1;\n unsigned int eoc7 : 1;\n unsigned int eoc6 : 1;\n unsigned int eoc5 : 1;\n unsigned int eoc4 : 1;\n unsigned int eoc3 : 1;\n unsigned int eoc2 : 1;\n unsigned int eoc1 : 1;\n unsigned int eoc0 : 1;\n} avr32_adc_idr_t;\n\n\n\ntypedef struct avr32_adc_imr_t {\n unsigned int :12;\n unsigned int rxbuff : 1;\n unsigned int endrx : 1;\n unsigned int govre : 1;\n unsigned int drdy : 1;\n unsigned int ovre7 : 1;\n unsigned int ovre6 : 1;\n unsigned int ovre5 : 1;\n unsigned int ovre4 : 1;\n unsigned int ovre3 : 1;\n unsigned int ovre2 : 1;\n unsigned int ovre1 : 1;\n unsigned int ovre0 : 1;\n unsigned int eoc7 : 1;\n unsigned int eoc6 : 1;\n unsigned int eoc5 : 1;\n unsigned int eoc4 : 1;\n unsigned int eoc3 : 1;\n unsigned int eoc2 : 1;\n unsigned int eoc1 : 1;\n unsigned int eoc0 : 1;\n} avr32_adc_imr_t;\n\n\n\ntypedef struct avr32_adc_cdr0_t {\n unsigned int :22;\n unsigned int data :10;\n} avr32_adc_cdr0_t;\n\n\n\ntypedef struct avr32_adc_cdr1_t {\n unsigned int :22;\n unsigned int data :10;\n} avr32_adc_cdr1_t;\n\n\n\ntypedef struct avr32_adc_cdr2_t {\n unsigned int :22;\n unsigned int data :10;\n} avr32_adc_cdr2_t;\n\n\n\ntypedef struct avr32_adc_cdr3_t {\n unsigned int :22;\n unsigned int data :10;\n} avr32_adc_cdr3_t;\n\n\n\ntypedef struct avr32_adc_cdr4_t {\n unsigned int :22;\n unsigned int data :10;\n} avr32_adc_cdr4_t;\n\n\n\ntypedef struct avr32_adc_cdr5_t {\n unsigned int :22;\n unsigned int data :10;\n} avr32_adc_cdr5_t;\n\n\n\ntypedef struct avr32_adc_cdr6_t {\n unsigned int :22;\n unsigned int data :10;\n} avr32_adc_cdr6_t;\n\n\n\ntypedef struct avr32_adc_cdr7_t {\n unsigned int :22;\n unsigned int data :10;\n} avr32_adc_cdr7_t;\n\n\n\ntypedef struct avr32_adc_version_t {\n unsigned int :13;\n unsigned int variant : 3;\n unsigned int : 4;\n unsigned int version :12;\n} avr32_adc_version_t;\n\n\n\ntypedef struct avr32_adc_t {\n union {\n unsigned long cr ;//0x0000\n avr32_adc_cr_t CR ;\n };\n union {\n unsigned long mr ;//0x0004\n avr32_adc_mr_t MR ;\n };\n unsigned int :32 ;//0x0008\n unsigned int :32 ;//0x000c\n union {\n unsigned long cher ;//0x0010\n avr32_adc_cher_t CHER ;\n };\n union {\n unsigned long chdr ;//0x0014\n avr32_adc_chdr_t CHDR ;\n };\n union {\n const unsigned long chsr ;//0x0018\n const avr32_adc_chsr_t CHSR ;\n };\n union {\n const unsigned long sr ;//0x001c\n const avr32_adc_sr_t SR ;\n };\n union {\n const unsigned long lcdr ;//0x0020\n const avr32_adc_lcdr_t LCDR ;\n };\n union {\n unsigned long ier ;//0x0024\n avr32_adc_ier_t IER ;\n };\n union {\n unsigned long idr ;//0x0028\n avr32_adc_idr_t IDR ;\n };\n union {\n const unsigned long imr ;//0x002c\n const avr32_adc_imr_t IMR ;\n };\n union {\n const unsigned long cdr0 ;//0x0030\n const avr32_adc_cdr0_t CDR0 ;\n };\n union {\n const unsigned long cdr1 ;//0x0034\n const avr32_adc_cdr1_t CDR1 ;\n };\n union {\n const unsigned long cdr2 ;//0x0038\n const avr32_adc_cdr2_t CDR2 ;\n };\n union {\n const unsigned long cdr3 ;//0x003c\n const avr32_adc_cdr3_t CDR3 ;\n };\n union {\n const unsigned long cdr4 ;//0x0040\n const avr32_adc_cdr4_t CDR4 ;\n };\n union {\n const unsigned long cdr5 ;//0x0044\n const avr32_adc_cdr5_t CDR5 ;\n };\n union {\n const unsigned long cdr6 ;//0x0048\n const avr32_adc_cdr6_t CDR6 ;\n };\n union {\n const unsigned long cdr7 ;//0x004c\n const avr32_adc_cdr7_t CDR7 ;\n };\n unsigned int :32 ;//0x0050\n unsigned int :32 ;//0x0054\n unsigned int :32 ;//0x0058\n unsigned int :32 ;//0x005c\n unsigned int :32 ;//0x0060\n unsigned int :32 ;//0x0064\n unsigned int :32 ;//0x0068\n unsigned int :32 ;//0x006c\n unsigned int :32 ;//0x0070\n unsigned int :32 ;//0x0074\n unsigned int :32 ;//0x0078\n unsigned int :32 ;//0x007c\n unsigned int :32 ;//0x0080\n unsigned int :32 ;//0x0084\n unsigned int :32 ;//0x0088\n unsigned int :32 ;//0x008c\n unsigned int :32 ;//0x0090\n unsigned int :32 ;//0x0094\n unsigned int :32 ;//0x0098\n unsigned int :32 ;//0x009c\n unsigned int :32 ;//0x00a0\n unsigned int :32 ;//0x00a4\n unsigned int :32 ;//0x00a8\n unsigned int :32 ;//0x00ac\n unsigned int :32 ;//0x00b0\n unsigned int :32 ;//0x00b4\n unsigned int :32 ;//0x00b8\n unsigned int :32 ;//0x00bc\n unsigned int :32 ;//0x00c0\n unsigned int :32 ;//0x00c4\n unsigned int :32 ;//0x00c8\n unsigned int :32 ;//0x00cc\n unsigned int :32 ;//0x00d0\n unsigned int :32 ;//0x00d4\n unsigned int :32 ;//0x00d8\n unsigned int :32 ;//0x00dc\n unsigned int :32 ;//0x00e0\n unsigned int :32 ;//0x00e4\n unsigned int :32 ;//0x00e8\n unsigned int :32 ;//0x00ec\n unsigned int :32 ;//0x00f0\n unsigned int :32 ;//0x00f4\n unsigned int :32 ;//0x00f8\n union {\n const unsigned long version ;//0x00fc\n const avr32_adc_version_t VERSION ;\n };\n} avr32_adc_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n/*#ifdef AVR32_ADC_200_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/core_sc0_130.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3000\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_CORE_SC0_130_H_INCLUDED\n#define AVR32_CORE_SC0_130_H_INCLUDED\n\n#define AVR32_CORE_SC0_H_VERSION 130\n\n#include \"avr32/abi.h\"\n\n#define AVR32_CORE_ID \"SC0\"\n\n#define AVR32_ACBA 0x00000008\n#define AVR32_BEAR 0x0000013c\n#define AVR32_COMPARE 0x0000010c\n#define AVR32_CONFIG0 0x00000100\n#define AVR32_CONFIG0_AR 10\n#define AVR32_CONFIG0_AR_MASK 0x00001c00\n#define AVR32_CONFIG0_AR_OFFSET 10\n#define AVR32_CONFIG0_AR_SIZE 3\n#define AVR32_CONFIG0_AT 13\n#define AVR32_CONFIG0_AT_AVR32A 0x00000000\n#define AVR32_CONFIG0_AT_AVR32B 0x00000001\n#define AVR32_CONFIG0_AT_MASK 0x0000e000\n#define AVR32_CONFIG0_AT_OFFSET 13\n#define AVR32_CONFIG0_AT_SIZE 3\n#define AVR32_CONFIG0_D 1\n#define AVR32_CONFIG0_D_MASK 0x00000002\n#define AVR32_CONFIG0_D_OFFSET 1\n#define AVR32_CONFIG0_D_SIZE 1\n#define AVR32_CONFIG0_F 6\n#define AVR32_CONFIG0_F_MASK 0x00000040\n#define AVR32_CONFIG0_F_OFFSET 6\n#define AVR32_CONFIG0_F_SIZE 1\n#define AVR32_CONFIG0_J 5\n#define AVR32_CONFIG0_J_MASK 0x00000020\n#define AVR32_CONFIG0_J_OFFSET 5\n#define AVR32_CONFIG0_J_SIZE 1\n#define AVR32_CONFIG0_MMUT 7\n#define AVR32_CONFIG0_MMUT_ITLB_DTLB 0x00000001\n#define AVR32_CONFIG0_MMUT_MASK 0x00000380\n#define AVR32_CONFIG0_MMUT_MPU 0x00000003\n#define AVR32_CONFIG0_MMUT_NONE 0x00000000\n#define AVR32_CONFIG0_MMUT_OFFSET 7\n#define AVR32_CONFIG0_MMUT_SHARED_TLB 0x00000002\n#define AVR32_CONFIG0_MMUT_SIZE 3\n#define AVR32_CONFIG0_O 3\n#define AVR32_CONFIG0_O_MASK 0x00000008\n#define AVR32_CONFIG0_O_OFFSET 3\n#define AVR32_CONFIG0_O_SIZE 1\n#define AVR32_CONFIG0_P 4\n#define AVR32_CONFIG0_PROCESSORID 24\n#define AVR32_CONFIG0_PROCESSORID_AP7 0x00000001\n#define AVR32_CONFIG0_PROCESSORID_MASK 0xff000000\n#define AVR32_CONFIG0_PROCESSORID_OFFSET 24\n#define AVR32_CONFIG0_PROCESSORID_SIZE 8\n#define AVR32_CONFIG0_PROCESSORID_UC3 0x00000002\n#define AVR32_CONFIG0_PROCESSORREVISION 16\n#define AVR32_CONFIG0_PROCESSORREVISION_MASK 0x000f0000\n#define AVR32_CONFIG0_PROCESSORREVISION_OFFSET 16\n#define AVR32_CONFIG0_PROCESSORREVISION_SIZE 4\n#define AVR32_CONFIG0_P_MASK 0x00000010\n#define AVR32_CONFIG0_P_OFFSET 4\n#define AVR32_CONFIG0_P_SIZE 1\n#define AVR32_CONFIG0_R 0\n#define AVR32_CONFIG0_R_MASK 0x00000001\n#define AVR32_CONFIG0_R_OFFSET 0\n#define AVR32_CONFIG0_R_SIZE 1\n#define AVR32_CONFIG0_S 2\n#define AVR32_CONFIG0_S_MASK 0x00000004\n#define AVR32_CONFIG0_S_OFFSET 2\n#define AVR32_CONFIG0_S_SIZE 1\n#define AVR32_CONFIG1 0x00000104\n#define AVR32_CONFIG1_DASS 0\n#define AVR32_CONFIG1_DASS_MASK 0x00000007\n#define AVR32_CONFIG1_DASS_OFFSET 0\n#define AVR32_CONFIG1_DASS_SIZE 3\n#define AVR32_CONFIG1_DLSZ 3\n#define AVR32_CONFIG1_DLSZ_MASK 0x00000038\n#define AVR32_CONFIG1_DLSZ_OFFSET 3\n#define AVR32_CONFIG1_DLSZ_SIZE 3\n#define AVR32_CONFIG1_DMMUSZ 20\n#define AVR32_CONFIG1_DMMUSZ_MASK 0x03f00000\n#define AVR32_CONFIG1_DMMUSZ_OFFSET 20\n#define AVR32_CONFIG1_DMMUSZ_SIZE 6\n#define AVR32_CONFIG1_DSET 6\n#define AVR32_CONFIG1_DSET_MASK 0x000003c0\n#define AVR32_CONFIG1_DSET_OFFSET 6\n#define AVR32_CONFIG1_DSET_SIZE 4\n#define AVR32_CONFIG1_IASS 10\n#define AVR32_CONFIG1_IASS_MASK 0x00001c00\n#define AVR32_CONFIG1_IASS_OFFSET 10\n#define AVR32_CONFIG1_IASS_SIZE 3\n#define AVR32_CONFIG1_ILSZ 13\n#define AVR32_CONFIG1_ILSZ_MASK 0x0000e000\n#define AVR32_CONFIG1_ILSZ_OFFSET 13\n#define AVR32_CONFIG1_ILSZ_SIZE 3\n#define AVR32_CONFIG1_IMMUSZ 26\n#define AVR32_CONFIG1_IMMUSZ_MASK 0xfc000000\n#define AVR32_CONFIG1_IMMUSZ_OFFSET 26\n#define AVR32_CONFIG1_IMMUSZ_SIZE 6\n#define AVR32_CONFIG1_ISET 16\n#define AVR32_CONFIG1_ISET_MASK 0x000f0000\n#define AVR32_CONFIG1_ISET_OFFSET 16\n#define AVR32_CONFIG1_ISET_SIZE 4\n#define AVR32_COUNT 0x00000108\n#define AVR32_CPUCR 0x0000000c\n#define AVR32_CPUCR_COP 1\n#define AVR32_CPUCR_COP_MASK 0x0000003e\n#define AVR32_CPUCR_COP_OFFSET 1\n#define AVR32_CPUCR_COP_SIZE 5\n#define AVR32_CPUCR_CPL 6\n#define AVR32_CPUCR_CPL_MASK 0x000007c0\n#define AVR32_CPUCR_CPL_OFFSET 6\n#define AVR32_CPUCR_CPL_SIZE 5\n#define AVR32_CPUCR_LOCEN 16\n#define AVR32_CPUCR_LOCEN_MASK 0x00010000\n#define AVR32_CPUCR_LOCEN_OFFSET 16\n#define AVR32_CPUCR_LOCEN_SIZE 1\n#define AVR32_CPUCR_SIE 0\n#define AVR32_CPUCR_SIE_MASK 0x00000001\n#define AVR32_CPUCR_SIE_OFFSET 0\n#define AVR32_CPUCR_SIE_SIZE 1\n#define AVR32_CPUCR_SPL 11\n#define AVR32_CPUCR_SPL_MASK 0x0000f800\n#define AVR32_CPUCR_SPL_OFFSET 11\n#define AVR32_CPUCR_SPL_SIZE 5\n#define AVR32_ECR 0x00000010\n#define AVR32_ECR_ECR 0\n#define AVR32_ECR_ECR_ADDR_ALIGN_R 0x0000000d\n#define AVR32_ECR_ECR_ADDR_ALIGN_W 0x0000000e\n#define AVR32_ECR_ECR_ADDR_ALIGN_X 0x00000005\n#define AVR32_ECR_ECR_BUS_ERROR_READ 0x00000003\n#define AVR32_ECR_ECR_BUS_ERROR_WRITE 0x00000002\n#define AVR32_ECR_ECR_COPROC_ABSENT 0x0000000c\n#define AVR32_ECR_ECR_DEBUG 0x00000007\n#define AVR32_ECR_ECR_DTLB_MODIFIED 0x00000011\n#define AVR32_ECR_ECR_FPE 0x0000000b\n#define AVR32_ECR_ECR_ILLEGAL_OPCODE 0x00000008\n#define AVR32_ECR_ECR_MASK 0xffffffff\n#define AVR32_ECR_ECR_NMI 0x00000004\n#define AVR32_ECR_ECR_OFFSET 0\n#define AVR32_ECR_ECR_PRIVILEGE_VIOLATION 0x0000000a\n#define AVR32_ECR_ECR_PROTECTION_R 0x0000000f\n#define AVR32_ECR_ECR_PROTECTION_W 0x00000010\n#define AVR32_ECR_ECR_PROTECTION_X 0x00000006\n#define AVR32_ECR_ECR_SIZE 32\n#define AVR32_ECR_ECR_TLB_MISS_R 0x00000018\n#define AVR32_ECR_ECR_TLB_MISS_W 0x0000001c\n#define AVR32_ECR_ECR_TLB_MISS_X 0x00000014\n#define AVR32_ECR_ECR_TLB_MULTIPLE 0x00000001\n#define AVR32_ECR_ECR_UNIMPL_INSTRUCTION 0x00000009\n#define AVR32_ECR_ECR_UNRECOVERABLE 0x00000000\n#define AVR32_EVBA 0x00000004\n#define AVR32_MPUAPRA 0x00000190\n#define AVR32_MPUAPRA_AP0 0\n#define AVR32_MPUAPRA_AP0_MASK 0x0000000f\n#define AVR32_MPUAPRA_AP0_OFFSET 0\n#define AVR32_MPUAPRA_AP0_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRA_AP0_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRA_AP0_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRA_AP0_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRA_AP0_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRA_AP0_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRA_AP0_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRA_AP0_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRA_AP0_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRA_AP0_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRA_AP0_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRA_AP0_SIZE 4\n#define AVR32_MPUAPRA_AP1 4\n#define AVR32_MPUAPRA_AP1_MASK 0x000000f0\n#define AVR32_MPUAPRA_AP1_OFFSET 4\n#define AVR32_MPUAPRA_AP1_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRA_AP1_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRA_AP1_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRA_AP1_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRA_AP1_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRA_AP1_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRA_AP1_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRA_AP1_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRA_AP1_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRA_AP1_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRA_AP1_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRA_AP1_SIZE 4\n#define AVR32_MPUAPRA_AP2 8\n#define AVR32_MPUAPRA_AP2_MASK 0x00000f00\n#define AVR32_MPUAPRA_AP2_OFFSET 8\n#define AVR32_MPUAPRA_AP2_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRA_AP2_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRA_AP2_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRA_AP2_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRA_AP2_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRA_AP2_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRA_AP2_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRA_AP2_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRA_AP2_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRA_AP2_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRA_AP2_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRA_AP2_SIZE 4\n#define AVR32_MPUAPRA_AP3 12\n#define AVR32_MPUAPRA_AP3_MASK 0x0000f000\n#define AVR32_MPUAPRA_AP3_OFFSET 12\n#define AVR32_MPUAPRA_AP3_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRA_AP3_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRA_AP3_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRA_AP3_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRA_AP3_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRA_AP3_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRA_AP3_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRA_AP3_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRA_AP3_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRA_AP3_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRA_AP3_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRA_AP3_SIZE 4\n#define AVR32_MPUAPRA_AP4 16\n#define AVR32_MPUAPRA_AP4_MASK 0x000f0000\n#define AVR32_MPUAPRA_AP4_OFFSET 16\n#define AVR32_MPUAPRA_AP4_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRA_AP4_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRA_AP4_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRA_AP4_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRA_AP4_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRA_AP4_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRA_AP4_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRA_AP4_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRA_AP4_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRA_AP4_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRA_AP4_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRA_AP4_SIZE 4\n#define AVR32_MPUAPRA_AP5 20\n#define AVR32_MPUAPRA_AP5_MASK 0x00f00000\n#define AVR32_MPUAPRA_AP5_OFFSET 20\n#define AVR32_MPUAPRA_AP5_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRA_AP5_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRA_AP5_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRA_AP5_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRA_AP5_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRA_AP5_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRA_AP5_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRA_AP5_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRA_AP5_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRA_AP5_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRA_AP5_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRA_AP5_SIZE 4\n#define AVR32_MPUAPRA_AP6 24\n#define AVR32_MPUAPRA_AP6_MASK 0x0f000000\n#define AVR32_MPUAPRA_AP6_OFFSET 24\n#define AVR32_MPUAPRA_AP6_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRA_AP6_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRA_AP6_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRA_AP6_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRA_AP6_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRA_AP6_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRA_AP6_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRA_AP6_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRA_AP6_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRA_AP6_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRA_AP6_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRA_AP6_SIZE 4\n#define AVR32_MPUAPRA_AP7 28\n#define AVR32_MPUAPRA_AP7_MASK 0xf0000000\n#define AVR32_MPUAPRA_AP7_OFFSET 28\n#define AVR32_MPUAPRA_AP7_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRA_AP7_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRA_AP7_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRA_AP7_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRA_AP7_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRA_AP7_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRA_AP7_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRA_AP7_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRA_AP7_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRA_AP7_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRA_AP7_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRA_AP7_SIZE 4\n#define AVR32_MPUAPRB 0x00000194\n#define AVR32_MPUAPRB_AP0 0\n#define AVR32_MPUAPRB_AP0_MASK 0x0000000f\n#define AVR32_MPUAPRB_AP0_OFFSET 0\n#define AVR32_MPUAPRB_AP0_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRB_AP0_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRB_AP0_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRB_AP0_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRB_AP0_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRB_AP0_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRB_AP0_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRB_AP0_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRB_AP0_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRB_AP0_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRB_AP0_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRB_AP0_SIZE 4\n#define AVR32_MPUAPRB_AP1 4\n#define AVR32_MPUAPRB_AP1_MASK 0x000000f0\n#define AVR32_MPUAPRB_AP1_OFFSET 4\n#define AVR32_MPUAPRB_AP1_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRB_AP1_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRB_AP1_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRB_AP1_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRB_AP1_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRB_AP1_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRB_AP1_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRB_AP1_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRB_AP1_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRB_AP1_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRB_AP1_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRB_AP1_SIZE 4\n#define AVR32_MPUAPRB_AP2 8\n#define AVR32_MPUAPRB_AP2_MASK 0x00000f00\n#define AVR32_MPUAPRB_AP2_OFFSET 8\n#define AVR32_MPUAPRB_AP2_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRB_AP2_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRB_AP2_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRB_AP2_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRB_AP2_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRB_AP2_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRB_AP2_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRB_AP2_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRB_AP2_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRB_AP2_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRB_AP2_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRB_AP2_SIZE 4\n#define AVR32_MPUAPRB_AP3 12\n#define AVR32_MPUAPRB_AP3_MASK 0x0000f000\n#define AVR32_MPUAPRB_AP3_OFFSET 12\n#define AVR32_MPUAPRB_AP3_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRB_AP3_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRB_AP3_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRB_AP3_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRB_AP3_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRB_AP3_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRB_AP3_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRB_AP3_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRB_AP3_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRB_AP3_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRB_AP3_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRB_AP3_SIZE 4\n#define AVR32_MPUAPRB_AP4 16\n#define AVR32_MPUAPRB_AP4_MASK 0x000f0000\n#define AVR32_MPUAPRB_AP4_OFFSET 16\n#define AVR32_MPUAPRB_AP4_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRB_AP4_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRB_AP4_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRB_AP4_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRB_AP4_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRB_AP4_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRB_AP4_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRB_AP4_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRB_AP4_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRB_AP4_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRB_AP4_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRB_AP4_SIZE 4\n#define AVR32_MPUAPRB_AP5 20\n#define AVR32_MPUAPRB_AP5_MASK 0x00f00000\n#define AVR32_MPUAPRB_AP5_OFFSET 20\n#define AVR32_MPUAPRB_AP5_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRB_AP5_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRB_AP5_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRB_AP5_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRB_AP5_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRB_AP5_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRB_AP5_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRB_AP5_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRB_AP5_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRB_AP5_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRB_AP5_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRB_AP5_SIZE 4\n#define AVR32_MPUAPRB_AP6 24\n#define AVR32_MPUAPRB_AP6_MASK 0x0f000000\n#define AVR32_MPUAPRB_AP6_OFFSET 24\n#define AVR32_MPUAPRB_AP6_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRB_AP6_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRB_AP6_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRB_AP6_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRB_AP6_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRB_AP6_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRB_AP6_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRB_AP6_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRB_AP6_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRB_AP6_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRB_AP6_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRB_AP6_SIZE 4\n#define AVR32_MPUAPRB_AP7 28\n#define AVR32_MPUAPRB_AP7_MASK 0xf0000000\n#define AVR32_MPUAPRB_AP7_OFFSET 28\n#define AVR32_MPUAPRB_AP7_PRIV_NONE_UNPRIV_NONE 0x0000000a\n#define AVR32_MPUAPRB_AP7_PRIV_RWX_UNPRIV_NONE 0x00000003\n#define AVR32_MPUAPRB_AP7_PRIV_RWX_UNPRIV_RWX 0x00000007\n#define AVR32_MPUAPRB_AP7_PRIV_RW_UNPRIV_NONE 0x00000002\n#define AVR32_MPUAPRB_AP7_PRIV_RW_UNPRIV_R 0x00000008\n#define AVR32_MPUAPRB_AP7_PRIV_RW_UNPRIV_RW 0x00000006\n#define AVR32_MPUAPRB_AP7_PRIV_RW_UNPRIV_RX 0x00000009\n#define AVR32_MPUAPRB_AP7_PRIV_RX_UNPRIV_NONE 0x00000001\n#define AVR32_MPUAPRB_AP7_PRIV_RX_UNPRIV_RX 0x00000005\n#define AVR32_MPUAPRB_AP7_PRIV_R_UNPRIV_NONE 0x00000000\n#define AVR32_MPUAPRB_AP7_PRIV_R_UNPRIV_R 0x00000004\n#define AVR32_MPUAPRB_AP7_SIZE 4\n#define AVR32_MPUAR0 0x00000140\n#define AVR32_MPUAR0_BASE 12\n#define AVR32_MPUAR0_BASE_MASK 0xfffff000\n#define AVR32_MPUAR0_BASE_OFFSET 12\n#define AVR32_MPUAR0_BASE_SIZE 20\n#define AVR32_MPUAR0_SIZE 1\n#define AVR32_MPUAR0_SIZE_MASK 0x0000003e\n#define AVR32_MPUAR0_SIZE_OFFSET 1\n#define AVR32_MPUAR0_SIZE_SIZE 5\n#define AVR32_MPUAR0_V 0\n#define AVR32_MPUAR0_V_MASK 0x00000001\n#define AVR32_MPUAR0_V_OFFSET 0\n#define AVR32_MPUAR0_V_SIZE 1\n#define AVR32_MPUAR1 0x00000144\n#define AVR32_MPUAR1_BASE 12\n#define AVR32_MPUAR1_BASE_MASK 0xfffff000\n#define AVR32_MPUAR1_BASE_OFFSET 12\n#define AVR32_MPUAR1_BASE_SIZE 20\n#define AVR32_MPUAR1_SIZE 1\n#define AVR32_MPUAR1_SIZE_MASK 0x0000003e\n#define AVR32_MPUAR1_SIZE_OFFSET 1\n#define AVR32_MPUAR1_SIZE_SIZE 5\n#define AVR32_MPUAR1_V 0\n#define AVR32_MPUAR1_V_MASK 0x00000001\n#define AVR32_MPUAR1_V_OFFSET 0\n#define AVR32_MPUAR1_V_SIZE 1\n#define AVR32_MPUAR2 0x00000148\n#define AVR32_MPUAR2_BASE 12\n#define AVR32_MPUAR2_BASE_MASK 0xfffff000\n#define AVR32_MPUAR2_BASE_OFFSET 12\n#define AVR32_MPUAR2_BASE_SIZE 20\n#define AVR32_MPUAR2_SIZE 1\n#define AVR32_MPUAR2_SIZE_MASK 0x0000003e\n#define AVR32_MPUAR2_SIZE_OFFSET 1\n#define AVR32_MPUAR2_SIZE_SIZE 5\n#define AVR32_MPUAR2_V 0\n#define AVR32_MPUAR2_V_MASK 0x00000001\n#define AVR32_MPUAR2_V_OFFSET 0\n#define AVR32_MPUAR2_V_SIZE 1\n#define AVR32_MPUAR3 0x0000014c\n#define AVR32_MPUAR3_BASE 12\n#define AVR32_MPUAR3_BASE_MASK 0xfffff000\n#define AVR32_MPUAR3_BASE_OFFSET 12\n#define AVR32_MPUAR3_BASE_SIZE 20\n#define AVR32_MPUAR3_SIZE 1\n#define AVR32_MPUAR3_SIZE_MASK 0x0000003e\n#define AVR32_MPUAR3_SIZE_OFFSET 1\n#define AVR32_MPUAR3_SIZE_SIZE 5\n#define AVR32_MPUAR3_V 0\n#define AVR32_MPUAR3_V_MASK 0x00000001\n#define AVR32_MPUAR3_V_OFFSET 0\n#define AVR32_MPUAR3_V_SIZE 1\n#define AVR32_MPUAR4 0x00000150\n#define AVR32_MPUAR4_BASE 12\n#define AVR32_MPUAR4_BASE_MASK 0xfffff000\n#define AVR32_MPUAR4_BASE_OFFSET 12\n#define AVR32_MPUAR4_BASE_SIZE 20\n#define AVR32_MPUAR4_SIZE 1\n#define AVR32_MPUAR4_SIZE_MASK 0x0000003e\n#define AVR32_MPUAR4_SIZE_OFFSET 1\n#define AVR32_MPUAR4_SIZE_SIZE 5\n#define AVR32_MPUAR4_V 0\n#define AVR32_MPUAR4_V_MASK 0x00000001\n#define AVR32_MPUAR4_V_OFFSET 0\n#define AVR32_MPUAR4_V_SIZE 1\n#define AVR32_MPUAR5 0x00000154\n#define AVR32_MPUAR5_BASE 12\n#define AVR32_MPUAR5_BASE_MASK 0xfffff000\n#define AVR32_MPUAR5_BASE_OFFSET 12\n#define AVR32_MPUAR5_BASE_SIZE 20\n#define AVR32_MPUAR5_SIZE 1\n#define AVR32_MPUAR5_SIZE_MASK 0x0000003e\n#define AVR32_MPUAR5_SIZE_OFFSET 1\n#define AVR32_MPUAR5_SIZE_SIZE 5\n#define AVR32_MPUAR5_V 0\n#define AVR32_MPUAR5_V_MASK 0x00000001\n#define AVR32_MPUAR5_V_OFFSET 0\n#define AVR32_MPUAR5_V_SIZE 1\n#define AVR32_MPUAR6 0x00000158\n#define AVR32_MPUAR6_BASE 12\n#define AVR32_MPUAR6_BASE_MASK 0xfffff000\n#define AVR32_MPUAR6_BASE_OFFSET 12\n#define AVR32_MPUAR6_BASE_SIZE 20\n#define AVR32_MPUAR6_SIZE 1\n#define AVR32_MPUAR6_SIZE_MASK 0x0000003e\n#define AVR32_MPUAR6_SIZE_OFFSET 1\n#define AVR32_MPUAR6_SIZE_SIZE 5\n#define AVR32_MPUAR6_V 0\n#define AVR32_MPUAR6_V_MASK 0x00000001\n#define AVR32_MPUAR6_V_OFFSET 0\n#define AVR32_MPUAR6_V_SIZE 1\n#define AVR32_MPUAR7 0x0000015c\n#define AVR32_MPUAR7_BASE 12\n#define AVR32_MPUAR7_BASE_MASK 0xfffff000\n#define AVR32_MPUAR7_BASE_OFFSET 12\n#define AVR32_MPUAR7_BASE_SIZE 20\n#define AVR32_MPUAR7_SIZE 1\n#define AVR32_MPUAR7_SIZE_MASK 0x0000003e\n#define AVR32_MPUAR7_SIZE_OFFSET 1\n#define AVR32_MPUAR7_SIZE_SIZE 5\n#define AVR32_MPUAR7_V 0\n#define AVR32_MPUAR7_V_MASK 0x00000001\n#define AVR32_MPUAR7_V_OFFSET 0\n#define AVR32_MPUAR7_V_SIZE 1\n#define AVR32_MPUBRA 0x00000188\n#define AVR32_MPUBRA_B0 0\n#define AVR32_MPUBRA_B0_MASK 0x00000001\n#define AVR32_MPUBRA_B0_OFFSET 0\n#define AVR32_MPUBRA_B0_SIZE 1\n#define AVR32_MPUBRA_B1 1\n#define AVR32_MPUBRA_B1_MASK 0x00000002\n#define AVR32_MPUBRA_B1_OFFSET 1\n#define AVR32_MPUBRA_B1_SIZE 1\n#define AVR32_MPUBRA_B2 2\n#define AVR32_MPUBRA_B2_MASK 0x00000004\n#define AVR32_MPUBRA_B2_OFFSET 2\n#define AVR32_MPUBRA_B2_SIZE 1\n#define AVR32_MPUBRA_B3 3\n#define AVR32_MPUBRA_B3_MASK 0x00000008\n#define AVR32_MPUBRA_B3_OFFSET 3\n#define AVR32_MPUBRA_B3_SIZE 1\n#define AVR32_MPUBRA_B4 4\n#define AVR32_MPUBRA_B4_MASK 0x00000010\n#define AVR32_MPUBRA_B4_OFFSET 4\n#define AVR32_MPUBRA_B4_SIZE 1\n#define AVR32_MPUBRA_B5 5\n#define AVR32_MPUBRA_B5_MASK 0x00000020\n#define AVR32_MPUBRA_B5_OFFSET 5\n#define AVR32_MPUBRA_B5_SIZE 1\n#define AVR32_MPUBRA_B6 6\n#define AVR32_MPUBRA_B6_MASK 0x00000040\n#define AVR32_MPUBRA_B6_OFFSET 6\n#define AVR32_MPUBRA_B6_SIZE 1\n#define AVR32_MPUBRA_B7 7\n#define AVR32_MPUBRA_B7_MASK 0x00000080\n#define AVR32_MPUBRA_B7_OFFSET 7\n#define AVR32_MPUBRA_B7_SIZE 1\n#define AVR32_MPUBRB 0x0000018c\n#define AVR32_MPUBRB_B0 0\n#define AVR32_MPUBRB_B0_MASK 0x00000001\n#define AVR32_MPUBRB_B0_OFFSET 0\n#define AVR32_MPUBRB_B0_SIZE 1\n#define AVR32_MPUBRB_B1 1\n#define AVR32_MPUBRB_B1_MASK 0x00000002\n#define AVR32_MPUBRB_B1_OFFSET 1\n#define AVR32_MPUBRB_B1_SIZE 1\n#define AVR32_MPUBRB_B2 2\n#define AVR32_MPUBRB_B2_MASK 0x00000004\n#define AVR32_MPUBRB_B2_OFFSET 2\n#define AVR32_MPUBRB_B2_SIZE 1\n#define AVR32_MPUBRB_B3 3\n#define AVR32_MPUBRB_B3_MASK 0x00000008\n#define AVR32_MPUBRB_B3_OFFSET 3\n#define AVR32_MPUBRB_B3_SIZE 1\n#define AVR32_MPUBRB_B4 4\n#define AVR32_MPUBRB_B4_MASK 0x00000010\n#define AVR32_MPUBRB_B4_OFFSET 4\n#define AVR32_MPUBRB_B4_SIZE 1\n#define AVR32_MPUBRB_B5 5\n#define AVR32_MPUBRB_B5_MASK 0x00000020\n#define AVR32_MPUBRB_B5_OFFSET 5\n#define AVR32_MPUBRB_B5_SIZE 1\n#define AVR32_MPUBRB_B6 6\n#define AVR32_MPUBRB_B6_MASK 0x00000040\n#define AVR32_MPUBRB_B6_OFFSET 6\n#define AVR32_MPUBRB_B6_SIZE 1\n#define AVR32_MPUBRB_B7 7\n#define AVR32_MPUBRB_B7_MASK 0x00000080\n#define AVR32_MPUBRB_B7_OFFSET 7\n#define AVR32_MPUBRB_B7_SIZE 1\n#define AVR32_MPUCR 0x00000198\n#define AVR32_MPUCRA 0x00000180\n#define AVR32_MPUCRA_C0 0\n#define AVR32_MPUCRA_C0_MASK 0x00000001\n#define AVR32_MPUCRA_C0_OFFSET 0\n#define AVR32_MPUCRA_C0_SIZE 1\n#define AVR32_MPUCRA_C1 1\n#define AVR32_MPUCRA_C1_MASK 0x00000002\n#define AVR32_MPUCRA_C1_OFFSET 1\n#define AVR32_MPUCRA_C1_SIZE 1\n#define AVR32_MPUCRA_C2 2\n#define AVR32_MPUCRA_C2_MASK 0x00000004\n#define AVR32_MPUCRA_C2_OFFSET 2\n#define AVR32_MPUCRA_C2_SIZE 1\n#define AVR32_MPUCRA_C3 3\n#define AVR32_MPUCRA_C3_MASK 0x00000008\n#define AVR32_MPUCRA_C3_OFFSET 3\n#define AVR32_MPUCRA_C3_SIZE 1\n#define AVR32_MPUCRA_C4 4\n#define AVR32_MPUCRA_C4_MASK 0x00000010\n#define AVR32_MPUCRA_C4_OFFSET 4\n#define AVR32_MPUCRA_C4_SIZE 1\n#define AVR32_MPUCRA_C5 5\n#define AVR32_MPUCRA_C5_MASK 0x00000020\n#define AVR32_MPUCRA_C5_OFFSET 5\n#define AVR32_MPUCRA_C5_SIZE 1\n#define AVR32_MPUCRA_C6 6\n#define AVR32_MPUCRA_C6_MASK 0x00000040\n#define AVR32_MPUCRA_C6_OFFSET 6\n#define AVR32_MPUCRA_C6_SIZE 1\n#define AVR32_MPUCRA_C7 7\n#define AVR32_MPUCRA_C7_MASK 0x00000080\n#define AVR32_MPUCRA_C7_OFFSET 7\n#define AVR32_MPUCRA_C7_SIZE 1\n#define AVR32_MPUCRB 0x00000184\n#define AVR32_MPUCRB_C0 0\n#define AVR32_MPUCRB_C0_MASK 0x00000001\n#define AVR32_MPUCRB_C0_OFFSET 0\n#define AVR32_MPUCRB_C0_SIZE 1\n#define AVR32_MPUCRB_C1 1\n#define AVR32_MPUCRB_C1_MASK 0x00000002\n#define AVR32_MPUCRB_C1_OFFSET 1\n#define AVR32_MPUCRB_C1_SIZE 1\n#define AVR32_MPUCRB_C2 2\n#define AVR32_MPUCRB_C2_MASK 0x00000004\n#define AVR32_MPUCRB_C2_OFFSET 2\n#define AVR32_MPUCRB_C2_SIZE 1\n#define AVR32_MPUCRB_C3 3\n#define AVR32_MPUCRB_C3_MASK 0x00000008\n#define AVR32_MPUCRB_C3_OFFSET 3\n#define AVR32_MPUCRB_C3_SIZE 1\n#define AVR32_MPUCRB_C4 4\n#define AVR32_MPUCRB_C4_MASK 0x00000010\n#define AVR32_MPUCRB_C4_OFFSET 4\n#define AVR32_MPUCRB_C4_SIZE 1\n#define AVR32_MPUCRB_C5 5\n#define AVR32_MPUCRB_C5_MASK 0x00000020\n#define AVR32_MPUCRB_C5_OFFSET 5\n#define AVR32_MPUCRB_C5_SIZE 1\n#define AVR32_MPUCRB_C6 6\n#define AVR32_MPUCRB_C6_MASK 0x00000040\n#define AVR32_MPUCRB_C6_OFFSET 6\n#define AVR32_MPUCRB_C6_SIZE 1\n#define AVR32_MPUCRB_C7 7\n#define AVR32_MPUCRB_C7_MASK 0x00000080\n#define AVR32_MPUCRB_C7_OFFSET 7\n#define AVR32_MPUCRB_C7_SIZE 1\n#define AVR32_MPUCR_E 0\n#define AVR32_MPUCR_E_MASK 0x00000001\n#define AVR32_MPUCR_E_OFFSET 0\n#define AVR32_MPUCR_E_SIZE 1\n#define AVR32_MPUPSR0 0x00000160\n#define AVR32_MPUPSR0_P0 0\n#define AVR32_MPUPSR0_P0_MASK 0x00000001\n#define AVR32_MPUPSR0_P0_OFFSET 0\n#define AVR32_MPUPSR0_P0_SIZE 1\n#define AVR32_MPUPSR0_P1 1\n#define AVR32_MPUPSR0_P10 10\n#define AVR32_MPUPSR0_P10_MASK 0x00000400\n#define AVR32_MPUPSR0_P10_OFFSET 10\n#define AVR32_MPUPSR0_P10_SIZE 1\n#define AVR32_MPUPSR0_P11 11\n#define AVR32_MPUPSR0_P11_MASK 0x00000800\n#define AVR32_MPUPSR0_P11_OFFSET 11\n#define AVR32_MPUPSR0_P11_SIZE 1\n#define AVR32_MPUPSR0_P12 12\n#define AVR32_MPUPSR0_P12_MASK 0x00001000\n#define AVR32_MPUPSR0_P12_OFFSET 12\n#define AVR32_MPUPSR0_P12_SIZE 1\n#define AVR32_MPUPSR0_P13 13\n#define AVR32_MPUPSR0_P13_MASK 0x00002000\n#define AVR32_MPUPSR0_P13_OFFSET 13\n#define AVR32_MPUPSR0_P13_SIZE 1\n#define AVR32_MPUPSR0_P14 14\n#define AVR32_MPUPSR0_P14_MASK 0x00004000\n#define AVR32_MPUPSR0_P14_OFFSET 14\n#define AVR32_MPUPSR0_P14_SIZE 1\n#define AVR32_MPUPSR0_P15 15\n#define AVR32_MPUPSR0_P15_MASK 0x00008000\n#define AVR32_MPUPSR0_P15_OFFSET 15\n#define AVR32_MPUPSR0_P15_SIZE 1\n#define AVR32_MPUPSR0_P1_MASK 0x00000002\n#define AVR32_MPUPSR0_P1_OFFSET 1\n#define AVR32_MPUPSR0_P1_SIZE 1\n#define AVR32_MPUPSR0_P2 2\n#define AVR32_MPUPSR0_P2_MASK 0x00000004\n#define AVR32_MPUPSR0_P2_OFFSET 2\n#define AVR32_MPUPSR0_P2_SIZE 1\n#define AVR32_MPUPSR0_P3 3\n#define AVR32_MPUPSR0_P3_MASK 0x00000008\n#define AVR32_MPUPSR0_P3_OFFSET 3\n#define AVR32_MPUPSR0_P3_SIZE 1\n#define AVR32_MPUPSR0_P4 4\n#define AVR32_MPUPSR0_P4_MASK 0x00000010\n#define AVR32_MPUPSR0_P4_OFFSET 4\n#define AVR32_MPUPSR0_P4_SIZE 1\n#define AVR32_MPUPSR0_P5 5\n#define AVR32_MPUPSR0_P5_MASK 0x00000020\n#define AVR32_MPUPSR0_P5_OFFSET 5\n#define AVR32_MPUPSR0_P5_SIZE 1\n#define AVR32_MPUPSR0_P6 6\n#define AVR32_MPUPSR0_P6_MASK 0x00000040\n#define AVR32_MPUPSR0_P6_OFFSET 6\n#define AVR32_MPUPSR0_P6_SIZE 1\n#define AVR32_MPUPSR0_P7 7\n#define AVR32_MPUPSR0_P7_MASK 0x00000080\n#define AVR32_MPUPSR0_P7_OFFSET 7\n#define AVR32_MPUPSR0_P7_SIZE 1\n#define AVR32_MPUPSR0_P8 8\n#define AVR32_MPUPSR0_P8_MASK 0x00000100\n#define AVR32_MPUPSR0_P8_OFFSET 8\n#define AVR32_MPUPSR0_P8_SIZE 1\n#define AVR32_MPUPSR0_P9 9\n#define AVR32_MPUPSR0_P9_MASK 0x00000200\n#define AVR32_MPUPSR0_P9_OFFSET 9\n#define AVR32_MPUPSR0_P9_SIZE 1\n#define AVR32_MPUPSR1 0x00000164\n#define AVR32_MPUPSR1_P0 0\n#define AVR32_MPUPSR1_P0_MASK 0x00000001\n#define AVR32_MPUPSR1_P0_OFFSET 0\n#define AVR32_MPUPSR1_P0_SIZE 1\n#define AVR32_MPUPSR1_P1 1\n#define AVR32_MPUPSR1_P10 10\n#define AVR32_MPUPSR1_P10_MASK 0x00000400\n#define AVR32_MPUPSR1_P10_OFFSET 10\n#define AVR32_MPUPSR1_P10_SIZE 1\n#define AVR32_MPUPSR1_P11 11\n#define AVR32_MPUPSR1_P11_MASK 0x00000800\n#define AVR32_MPUPSR1_P11_OFFSET 11\n#define AVR32_MPUPSR1_P11_SIZE 1\n#define AVR32_MPUPSR1_P12 12\n#define AVR32_MPUPSR1_P12_MASK 0x00001000\n#define AVR32_MPUPSR1_P12_OFFSET 12\n#define AVR32_MPUPSR1_P12_SIZE 1\n#define AVR32_MPUPSR1_P13 13\n#define AVR32_MPUPSR1_P13_MASK 0x00002000\n#define AVR32_MPUPSR1_P13_OFFSET 13\n#define AVR32_MPUPSR1_P13_SIZE 1\n#define AVR32_MPUPSR1_P14 14\n#define AVR32_MPUPSR1_P14_MASK 0x00004000\n#define AVR32_MPUPSR1_P14_OFFSET 14\n#define AVR32_MPUPSR1_P14_SIZE 1\n#define AVR32_MPUPSR1_P15 15\n#define AVR32_MPUPSR1_P15_MASK 0x00008000\n#define AVR32_MPUPSR1_P15_OFFSET 15\n#define AVR32_MPUPSR1_P15_SIZE 1\n#define AVR32_MPUPSR1_P1_MASK 0x00000002\n#define AVR32_MPUPSR1_P1_OFFSET 1\n#define AVR32_MPUPSR1_P1_SIZE 1\n#define AVR32_MPUPSR1_P2 2\n#define AVR32_MPUPSR1_P2_MASK 0x00000004\n#define AVR32_MPUPSR1_P2_OFFSET 2\n#define AVR32_MPUPSR1_P2_SIZE 1\n#define AVR32_MPUPSR1_P3 3\n#define AVR32_MPUPSR1_P3_MASK 0x00000008\n#define AVR32_MPUPSR1_P3_OFFSET 3\n#define AVR32_MPUPSR1_P3_SIZE 1\n#define AVR32_MPUPSR1_P4 4\n#define AVR32_MPUPSR1_P4_MASK 0x00000010\n#define AVR32_MPUPSR1_P4_OFFSET 4\n#define AVR32_MPUPSR1_P4_SIZE 1\n#define AVR32_MPUPSR1_P5 5\n#define AVR32_MPUPSR1_P5_MASK 0x00000020\n#define AVR32_MPUPSR1_P5_OFFSET 5\n#define AVR32_MPUPSR1_P5_SIZE 1\n#define AVR32_MPUPSR1_P6 6\n#define AVR32_MPUPSR1_P6_MASK 0x00000040\n#define AVR32_MPUPSR1_P6_OFFSET 6\n#define AVR32_MPUPSR1_P6_SIZE 1\n#define AVR32_MPUPSR1_P7 7\n#define AVR32_MPUPSR1_P7_MASK 0x00000080\n#define AVR32_MPUPSR1_P7_OFFSET 7\n#define AVR32_MPUPSR1_P7_SIZE 1\n#define AVR32_MPUPSR1_P8 8\n#define AVR32_MPUPSR1_P8_MASK 0x00000100\n#define AVR32_MPUPSR1_P8_OFFSET 8\n#define AVR32_MPUPSR1_P8_SIZE 1\n#define AVR32_MPUPSR1_P9 9\n#define AVR32_MPUPSR1_P9_MASK 0x00000200\n#define AVR32_MPUPSR1_P9_OFFSET 9\n#define AVR32_MPUPSR1_P9_SIZE 1\n#define AVR32_MPUPSR2 0x00000168\n#define AVR32_MPUPSR2_P0 0\n#define AVR32_MPUPSR2_P0_MASK 0x00000001\n#define AVR32_MPUPSR2_P0_OFFSET 0\n#define AVR32_MPUPSR2_P0_SIZE 1\n#define AVR32_MPUPSR2_P1 1\n#define AVR32_MPUPSR2_P10 10\n#define AVR32_MPUPSR2_P10_MASK 0x00000400\n#define AVR32_MPUPSR2_P10_OFFSET 10\n#define AVR32_MPUPSR2_P10_SIZE 1\n#define AVR32_MPUPSR2_P11 11\n#define AVR32_MPUPSR2_P11_MASK 0x00000800\n#define AVR32_MPUPSR2_P11_OFFSET 11\n#define AVR32_MPUPSR2_P11_SIZE 1\n#define AVR32_MPUPSR2_P12 12\n#define AVR32_MPUPSR2_P12_MASK 0x00001000\n#define AVR32_MPUPSR2_P12_OFFSET 12\n#define AVR32_MPUPSR2_P12_SIZE 1\n#define AVR32_MPUPSR2_P13 13\n#define AVR32_MPUPSR2_P13_MASK 0x00002000\n#define AVR32_MPUPSR2_P13_OFFSET 13\n#define AVR32_MPUPSR2_P13_SIZE 1\n#define AVR32_MPUPSR2_P14 14\n#define AVR32_MPUPSR2_P14_MASK 0x00004000\n#define AVR32_MPUPSR2_P14_OFFSET 14\n#define AVR32_MPUPSR2_P14_SIZE 1\n#define AVR32_MPUPSR2_P15 15\n#define AVR32_MPUPSR2_P15_MASK 0x00008000\n#define AVR32_MPUPSR2_P15_OFFSET 15\n#define AVR32_MPUPSR2_P15_SIZE 1\n#define AVR32_MPUPSR2_P1_MASK 0x00000002\n#define AVR32_MPUPSR2_P1_OFFSET 1\n#define AVR32_MPUPSR2_P1_SIZE 1\n#define AVR32_MPUPSR2_P2 2\n#define AVR32_MPUPSR2_P2_MASK 0x00000004\n#define AVR32_MPUPSR2_P2_OFFSET 2\n#define AVR32_MPUPSR2_P2_SIZE 1\n#define AVR32_MPUPSR2_P3 3\n#define AVR32_MPUPSR2_P3_MASK 0x00000008\n#define AVR32_MPUPSR2_P3_OFFSET 3\n#define AVR32_MPUPSR2_P3_SIZE 1\n#define AVR32_MPUPSR2_P4 4\n#define AVR32_MPUPSR2_P4_MASK 0x00000010\n#define AVR32_MPUPSR2_P4_OFFSET 4\n#define AVR32_MPUPSR2_P4_SIZE 1\n#define AVR32_MPUPSR2_P5 5\n#define AVR32_MPUPSR2_P5_MASK 0x00000020\n#define AVR32_MPUPSR2_P5_OFFSET 5\n#define AVR32_MPUPSR2_P5_SIZE 1\n#define AVR32_MPUPSR2_P6 6\n#define AVR32_MPUPSR2_P6_MASK 0x00000040\n#define AVR32_MPUPSR2_P6_OFFSET 6\n#define AVR32_MPUPSR2_P6_SIZE 1\n#define AVR32_MPUPSR2_P7 7\n#define AVR32_MPUPSR2_P7_MASK 0x00000080\n#define AVR32_MPUPSR2_P7_OFFSET 7\n#define AVR32_MPUPSR2_P7_SIZE 1\n#define AVR32_MPUPSR2_P8 8\n#define AVR32_MPUPSR2_P8_MASK 0x00000100\n#define AVR32_MPUPSR2_P8_OFFSET 8\n#define AVR32_MPUPSR2_P8_SIZE 1\n#define AVR32_MPUPSR2_P9 9\n#define AVR32_MPUPSR2_P9_MASK 0x00000200\n#define AVR32_MPUPSR2_P9_OFFSET 9\n#define AVR32_MPUPSR2_P9_SIZE 1\n#define AVR32_MPUPSR3 0x0000016c\n#define AVR32_MPUPSR3_P0 0\n#define AVR32_MPUPSR3_P0_MASK 0x00000001\n#define AVR32_MPUPSR3_P0_OFFSET 0\n#define AVR32_MPUPSR3_P0_SIZE 1\n#define AVR32_MPUPSR3_P1 1\n#define AVR32_MPUPSR3_P10 10\n#define AVR32_MPUPSR3_P10_MASK 0x00000400\n#define AVR32_MPUPSR3_P10_OFFSET 10\n#define AVR32_MPUPSR3_P10_SIZE 1\n#define AVR32_MPUPSR3_P11 11\n#define AVR32_MPUPSR3_P11_MASK 0x00000800\n#define AVR32_MPUPSR3_P11_OFFSET 11\n#define AVR32_MPUPSR3_P11_SIZE 1\n#define AVR32_MPUPSR3_P12 12\n#define AVR32_MPUPSR3_P12_MASK 0x00001000\n#define AVR32_MPUPSR3_P12_OFFSET 12\n#define AVR32_MPUPSR3_P12_SIZE 1\n#define AVR32_MPUPSR3_P13 13\n#define AVR32_MPUPSR3_P13_MASK 0x00002000\n#define AVR32_MPUPSR3_P13_OFFSET 13\n#define AVR32_MPUPSR3_P13_SIZE 1\n#define AVR32_MPUPSR3_P14 14\n#define AVR32_MPUPSR3_P14_MASK 0x00004000\n#define AVR32_MPUPSR3_P14_OFFSET 14\n#define AVR32_MPUPSR3_P14_SIZE 1\n#define AVR32_MPUPSR3_P15 15\n#define AVR32_MPUPSR3_P15_MASK 0x00008000\n#define AVR32_MPUPSR3_P15_OFFSET 15\n#define AVR32_MPUPSR3_P15_SIZE 1\n#define AVR32_MPUPSR3_P1_MASK 0x00000002\n#define AVR32_MPUPSR3_P1_OFFSET 1\n#define AVR32_MPUPSR3_P1_SIZE 1\n#define AVR32_MPUPSR3_P2 2\n#define AVR32_MPUPSR3_P2_MASK 0x00000004\n#define AVR32_MPUPSR3_P2_OFFSET 2\n#define AVR32_MPUPSR3_P2_SIZE 1\n#define AVR32_MPUPSR3_P3 3\n#define AVR32_MPUPSR3_P3_MASK 0x00000008\n#define AVR32_MPUPSR3_P3_OFFSET 3\n#define AVR32_MPUPSR3_P3_SIZE 1\n#define AVR32_MPUPSR3_P4 4\n#define AVR32_MPUPSR3_P4_MASK 0x00000010\n#define AVR32_MPUPSR3_P4_OFFSET 4\n#define AVR32_MPUPSR3_P4_SIZE 1\n#define AVR32_MPUPSR3_P5 5\n#define AVR32_MPUPSR3_P5_MASK 0x00000020\n#define AVR32_MPUPSR3_P5_OFFSET 5\n#define AVR32_MPUPSR3_P5_SIZE 1\n#define AVR32_MPUPSR3_P6 6\n#define AVR32_MPUPSR3_P6_MASK 0x00000040\n#define AVR32_MPUPSR3_P6_OFFSET 6\n#define AVR32_MPUPSR3_P6_SIZE 1\n#define AVR32_MPUPSR3_P7 7\n#define AVR32_MPUPSR3_P7_MASK 0x00000080\n#define AVR32_MPUPSR3_P7_OFFSET 7\n#define AVR32_MPUPSR3_P7_SIZE 1\n#define AVR32_MPUPSR3_P8 8\n#define AVR32_MPUPSR3_P8_MASK 0x00000100\n#define AVR32_MPUPSR3_P8_OFFSET 8\n#define AVR32_MPUPSR3_P8_SIZE 1\n#define AVR32_MPUPSR3_P9 9\n#define AVR32_MPUPSR3_P9_MASK 0x00000200\n#define AVR32_MPUPSR3_P9_OFFSET 9\n#define AVR32_MPUPSR3_P9_SIZE 1\n#define AVR32_MPUPSR4 0x00000170\n#define AVR32_MPUPSR4_P0 0\n#define AVR32_MPUPSR4_P0_MASK 0x00000001\n#define AVR32_MPUPSR4_P0_OFFSET 0\n#define AVR32_MPUPSR4_P0_SIZE 1\n#define AVR32_MPUPSR4_P1 1\n#define AVR32_MPUPSR4_P10 10\n#define AVR32_MPUPSR4_P10_MASK 0x00000400\n#define AVR32_MPUPSR4_P10_OFFSET 10\n#define AVR32_MPUPSR4_P10_SIZE 1\n#define AVR32_MPUPSR4_P11 11\n#define AVR32_MPUPSR4_P11_MASK 0x00000800\n#define AVR32_MPUPSR4_P11_OFFSET 11\n#define AVR32_MPUPSR4_P11_SIZE 1\n#define AVR32_MPUPSR4_P12 12\n#define AVR32_MPUPSR4_P12_MASK 0x00001000\n#define AVR32_MPUPSR4_P12_OFFSET 12\n#define AVR32_MPUPSR4_P12_SIZE 1\n#define AVR32_MPUPSR4_P13 13\n#define AVR32_MPUPSR4_P13_MASK 0x00002000\n#define AVR32_MPUPSR4_P13_OFFSET 13\n#define AVR32_MPUPSR4_P13_SIZE 1\n#define AVR32_MPUPSR4_P14 14\n#define AVR32_MPUPSR4_P14_MASK 0x00004000\n#define AVR32_MPUPSR4_P14_OFFSET 14\n#define AVR32_MPUPSR4_P14_SIZE 1\n#define AVR32_MPUPSR4_P15 15\n#define AVR32_MPUPSR4_P15_MASK 0x00008000\n#define AVR32_MPUPSR4_P15_OFFSET 15\n#define AVR32_MPUPSR4_P15_SIZE 1\n#define AVR32_MPUPSR4_P1_MASK 0x00000002\n#define AVR32_MPUPSR4_P1_OFFSET 1\n#define AVR32_MPUPSR4_P1_SIZE 1\n#define AVR32_MPUPSR4_P2 2\n#define AVR32_MPUPSR4_P2_MASK 0x00000004\n#define AVR32_MPUPSR4_P2_OFFSET 2\n#define AVR32_MPUPSR4_P2_SIZE 1\n#define AVR32_MPUPSR4_P3 3\n#define AVR32_MPUPSR4_P3_MASK 0x00000008\n#define AVR32_MPUPSR4_P3_OFFSET 3\n#define AVR32_MPUPSR4_P3_SIZE 1\n#define AVR32_MPUPSR4_P4 4\n#define AVR32_MPUPSR4_P4_MASK 0x00000010\n#define AVR32_MPUPSR4_P4_OFFSET 4\n#define AVR32_MPUPSR4_P4_SIZE 1\n#define AVR32_MPUPSR4_P5 5\n#define AVR32_MPUPSR4_P5_MASK 0x00000020\n#define AVR32_MPUPSR4_P5_OFFSET 5\n#define AVR32_MPUPSR4_P5_SIZE 1\n#define AVR32_MPUPSR4_P6 6\n#define AVR32_MPUPSR4_P6_MASK 0x00000040\n#define AVR32_MPUPSR4_P6_OFFSET 6\n#define AVR32_MPUPSR4_P6_SIZE 1\n#define AVR32_MPUPSR4_P7 7\n#define AVR32_MPUPSR4_P7_MASK 0x00000080\n#define AVR32_MPUPSR4_P7_OFFSET 7\n#define AVR32_MPUPSR4_P7_SIZE 1\n#define AVR32_MPUPSR4_P8 8\n#define AVR32_MPUPSR4_P8_MASK 0x00000100\n#define AVR32_MPUPSR4_P8_OFFSET 8\n#define AVR32_MPUPSR4_P8_SIZE 1\n#define AVR32_MPUPSR4_P9 9\n#define AVR32_MPUPSR4_P9_MASK 0x00000200\n#define AVR32_MPUPSR4_P9_OFFSET 9\n#define AVR32_MPUPSR4_P9_SIZE 1\n#define AVR32_MPUPSR5 0x00000174\n#define AVR32_MPUPSR5_P0 0\n#define AVR32_MPUPSR5_P0_MASK 0x00000001\n#define AVR32_MPUPSR5_P0_OFFSET 0\n#define AVR32_MPUPSR5_P0_SIZE 1\n#define AVR32_MPUPSR5_P1 1\n#define AVR32_MPUPSR5_P10 10\n#define AVR32_MPUPSR5_P10_MASK 0x00000400\n#define AVR32_MPUPSR5_P10_OFFSET 10\n#define AVR32_MPUPSR5_P10_SIZE 1\n#define AVR32_MPUPSR5_P11 11\n#define AVR32_MPUPSR5_P11_MASK 0x00000800\n#define AVR32_MPUPSR5_P11_OFFSET 11\n#define AVR32_MPUPSR5_P11_SIZE 1\n#define AVR32_MPUPSR5_P12 12\n#define AVR32_MPUPSR5_P12_MASK 0x00001000\n#define AVR32_MPUPSR5_P12_OFFSET 12\n#define AVR32_MPUPSR5_P12_SIZE 1\n#define AVR32_MPUPSR5_P13 13\n#define AVR32_MPUPSR5_P13_MASK 0x00002000\n#define AVR32_MPUPSR5_P13_OFFSET 13\n#define AVR32_MPUPSR5_P13_SIZE 1\n#define AVR32_MPUPSR5_P14 14\n#define AVR32_MPUPSR5_P14_MASK 0x00004000\n#define AVR32_MPUPSR5_P14_OFFSET 14\n#define AVR32_MPUPSR5_P14_SIZE 1\n#define AVR32_MPUPSR5_P15 15\n#define AVR32_MPUPSR5_P15_MASK 0x00008000\n#define AVR32_MPUPSR5_P15_OFFSET 15\n#define AVR32_MPUPSR5_P15_SIZE 1\n#define AVR32_MPUPSR5_P1_MASK 0x00000002\n#define AVR32_MPUPSR5_P1_OFFSET 1\n#define AVR32_MPUPSR5_P1_SIZE 1\n#define AVR32_MPUPSR5_P2 2\n#define AVR32_MPUPSR5_P2_MASK 0x00000004\n#define AVR32_MPUPSR5_P2_OFFSET 2\n#define AVR32_MPUPSR5_P2_SIZE 1\n#define AVR32_MPUPSR5_P3 3\n#define AVR32_MPUPSR5_P3_MASK 0x00000008\n#define AVR32_MPUPSR5_P3_OFFSET 3\n#define AVR32_MPUPSR5_P3_SIZE 1\n#define AVR32_MPUPSR5_P4 4\n#define AVR32_MPUPSR5_P4_MASK 0x00000010\n#define AVR32_MPUPSR5_P4_OFFSET 4\n#define AVR32_MPUPSR5_P4_SIZE 1\n#define AVR32_MPUPSR5_P5 5\n#define AVR32_MPUPSR5_P5_MASK 0x00000020\n#define AVR32_MPUPSR5_P5_OFFSET 5\n#define AVR32_MPUPSR5_P5_SIZE 1\n#define AVR32_MPUPSR5_P6 6\n#define AVR32_MPUPSR5_P6_MASK 0x00000040\n#define AVR32_MPUPSR5_P6_OFFSET 6\n#define AVR32_MPUPSR5_P6_SIZE 1\n#define AVR32_MPUPSR5_P7 7\n#define AVR32_MPUPSR5_P7_MASK 0x00000080\n#define AVR32_MPUPSR5_P7_OFFSET 7\n#define AVR32_MPUPSR5_P7_SIZE 1\n#define AVR32_MPUPSR5_P8 8\n#define AVR32_MPUPSR5_P8_MASK 0x00000100\n#define AVR32_MPUPSR5_P8_OFFSET 8\n#define AVR32_MPUPSR5_P8_SIZE 1\n#define AVR32_MPUPSR5_P9 9\n#define AVR32_MPUPSR5_P9_MASK 0x00000200\n#define AVR32_MPUPSR5_P9_OFFSET 9\n#define AVR32_MPUPSR5_P9_SIZE 1\n#define AVR32_MPUPSR6 0x00000178\n#define AVR32_MPUPSR6_P0 0\n#define AVR32_MPUPSR6_P0_MASK 0x00000001\n#define AVR32_MPUPSR6_P0_OFFSET 0\n#define AVR32_MPUPSR6_P0_SIZE 1\n#define AVR32_MPUPSR6_P1 1\n#define AVR32_MPUPSR6_P10 10\n#define AVR32_MPUPSR6_P10_MASK 0x00000400\n#define AVR32_MPUPSR6_P10_OFFSET 10\n#define AVR32_MPUPSR6_P10_SIZE 1\n#define AVR32_MPUPSR6_P11 11\n#define AVR32_MPUPSR6_P11_MASK 0x00000800\n#define AVR32_MPUPSR6_P11_OFFSET 11\n#define AVR32_MPUPSR6_P11_SIZE 1\n#define AVR32_MPUPSR6_P12 12\n#define AVR32_MPUPSR6_P12_MASK 0x00001000\n#define AVR32_MPUPSR6_P12_OFFSET 12\n#define AVR32_MPUPSR6_P12_SIZE 1\n#define AVR32_MPUPSR6_P13 13\n#define AVR32_MPUPSR6_P13_MASK 0x00002000\n#define AVR32_MPUPSR6_P13_OFFSET 13\n#define AVR32_MPUPSR6_P13_SIZE 1\n#define AVR32_MPUPSR6_P14 14\n#define AVR32_MPUPSR6_P14_MASK 0x00004000\n#define AVR32_MPUPSR6_P14_OFFSET 14\n#define AVR32_MPUPSR6_P14_SIZE 1\n#define AVR32_MPUPSR6_P15 15\n#define AVR32_MPUPSR6_P15_MASK 0x00008000\n#define AVR32_MPUPSR6_P15_OFFSET 15\n#define AVR32_MPUPSR6_P15_SIZE 1\n#define AVR32_MPUPSR6_P1_MASK 0x00000002\n#define AVR32_MPUPSR6_P1_OFFSET 1\n#define AVR32_MPUPSR6_P1_SIZE 1\n#define AVR32_MPUPSR6_P2 2\n#define AVR32_MPUPSR6_P2_MASK 0x00000004\n#define AVR32_MPUPSR6_P2_OFFSET 2\n#define AVR32_MPUPSR6_P2_SIZE 1\n#define AVR32_MPUPSR6_P3 3\n#define AVR32_MPUPSR6_P3_MASK 0x00000008\n#define AVR32_MPUPSR6_P3_OFFSET 3\n#define AVR32_MPUPSR6_P3_SIZE 1\n#define AVR32_MPUPSR6_P4 4\n#define AVR32_MPUPSR6_P4_MASK 0x00000010\n#define AVR32_MPUPSR6_P4_OFFSET 4\n#define AVR32_MPUPSR6_P4_SIZE 1\n#define AVR32_MPUPSR6_P5 5\n#define AVR32_MPUPSR6_P5_MASK 0x00000020\n#define AVR32_MPUPSR6_P5_OFFSET 5\n#define AVR32_MPUPSR6_P5_SIZE 1\n#define AVR32_MPUPSR6_P6 6\n#define AVR32_MPUPSR6_P6_MASK 0x00000040\n#define AVR32_MPUPSR6_P6_OFFSET 6\n#define AVR32_MPUPSR6_P6_SIZE 1\n#define AVR32_MPUPSR6_P7 7\n#define AVR32_MPUPSR6_P7_MASK 0x00000080\n#define AVR32_MPUPSR6_P7_OFFSET 7\n#define AVR32_MPUPSR6_P7_SIZE 1\n#define AVR32_MPUPSR6_P8 8\n#define AVR32_MPUPSR6_P8_MASK 0x00000100\n#define AVR32_MPUPSR6_P8_OFFSET 8\n#define AVR32_MPUPSR6_P8_SIZE 1\n#define AVR32_MPUPSR6_P9 9\n#define AVR32_MPUPSR6_P9_MASK 0x00000200\n#define AVR32_MPUPSR6_P9_OFFSET 9\n#define AVR32_MPUPSR6_P9_SIZE 1\n#define AVR32_MPUPSR7 0x0000017c\n#define AVR32_MPUPSR7_P0 0\n#define AVR32_MPUPSR7_P0_MASK 0x00000001\n#define AVR32_MPUPSR7_P0_OFFSET 0\n#define AVR32_MPUPSR7_P0_SIZE 1\n#define AVR32_MPUPSR7_P1 1\n#define AVR32_MPUPSR7_P10 10\n#define AVR32_MPUPSR7_P10_MASK 0x00000400\n#define AVR32_MPUPSR7_P10_OFFSET 10\n#define AVR32_MPUPSR7_P10_SIZE 1\n#define AVR32_MPUPSR7_P11 11\n#define AVR32_MPUPSR7_P11_MASK 0x00000800\n#define AVR32_MPUPSR7_P11_OFFSET 11\n#define AVR32_MPUPSR7_P11_SIZE 1\n#define AVR32_MPUPSR7_P12 12\n#define AVR32_MPUPSR7_P12_MASK 0x00001000\n#define AVR32_MPUPSR7_P12_OFFSET 12\n#define AVR32_MPUPSR7_P12_SIZE 1\n#define AVR32_MPUPSR7_P13 13\n#define AVR32_MPUPSR7_P13_MASK 0x00002000\n#define AVR32_MPUPSR7_P13_OFFSET 13\n#define AVR32_MPUPSR7_P13_SIZE 1\n#define AVR32_MPUPSR7_P14 14\n#define AVR32_MPUPSR7_P14_MASK 0x00004000\n#define AVR32_MPUPSR7_P14_OFFSET 14\n#define AVR32_MPUPSR7_P14_SIZE 1\n#define AVR32_MPUPSR7_P15 15\n#define AVR32_MPUPSR7_P15_MASK 0x00008000\n#define AVR32_MPUPSR7_P15_OFFSET 15\n#define AVR32_MPUPSR7_P15_SIZE 1\n#define AVR32_MPUPSR7_P1_MASK 0x00000002\n#define AVR32_MPUPSR7_P1_OFFSET 1\n#define AVR32_MPUPSR7_P1_SIZE 1\n#define AVR32_MPUPSR7_P2 2\n#define AVR32_MPUPSR7_P2_MASK 0x00000004\n#define AVR32_MPUPSR7_P2_OFFSET 2\n#define AVR32_MPUPSR7_P2_SIZE 1\n#define AVR32_MPUPSR7_P3 3\n#define AVR32_MPUPSR7_P3_MASK 0x00000008\n#define AVR32_MPUPSR7_P3_OFFSET 3\n#define AVR32_MPUPSR7_P3_SIZE 1\n#define AVR32_MPUPSR7_P4 4\n#define AVR32_MPUPSR7_P4_MASK 0x00000010\n#define AVR32_MPUPSR7_P4_OFFSET 4\n#define AVR32_MPUPSR7_P4_SIZE 1\n#define AVR32_MPUPSR7_P5 5\n#define AVR32_MPUPSR7_P5_MASK 0x00000020\n#define AVR32_MPUPSR7_P5_OFFSET 5\n#define AVR32_MPUPSR7_P5_SIZE 1\n#define AVR32_MPUPSR7_P6 6\n#define AVR32_MPUPSR7_P6_MASK 0x00000040\n#define AVR32_MPUPSR7_P6_OFFSET 6\n#define AVR32_MPUPSR7_P6_SIZE 1\n#define AVR32_MPUPSR7_P7 7\n#define AVR32_MPUPSR7_P7_MASK 0x00000080\n#define AVR32_MPUPSR7_P7_OFFSET 7\n#define AVR32_MPUPSR7_P7_SIZE 1\n#define AVR32_MPUPSR7_P8 8\n#define AVR32_MPUPSR7_P8_MASK 0x00000100\n#define AVR32_MPUPSR7_P8_OFFSET 8\n#define AVR32_MPUPSR7_P8_SIZE 1\n#define AVR32_MPUPSR7_P9 9\n#define AVR32_MPUPSR7_P9_MASK 0x00000200\n#define AVR32_MPUPSR7_P9_OFFSET 9\n#define AVR32_MPUPSR7_P9_SIZE 1\n\n#define AVR32_MSU_ADDRHI 0x000003E0\n#define AVR32_MSU_ADDRHI_MASK 0x0000000F\n#define AVR32_MSU_ADDRHI_RESETVALUE 0x00000000\n#define AVR32_MSU_ADDRLO 0x000003E4\n#define AVR32_MSU_ADDRLO_MASK 0xFFFFFFFC\n#define AVR32_MSU_ADDRLO_RESETVALUE 0x00000000\n#define AVR32_MSU_LENGTH 0x000003E8\n#define AVR32_MSU_LENGTH_MASK 0xFFFFFFFC\n#define AVR32_MSU_LENGTH_RESETVALUE 0x00000000\n#define AVR32_MSU_CTRL 0x000003EC\n#define AVR32_MSU_CTRL_OP_MASK 0x0000000F\n#define AVR32_MSU_CTRL_NTBC_MASK 0x00000030\n#define AVR32_MSU_CTRL_RESETVALUE 0x00000000\n#define AVR32_MSU_STATUS 0x000003F0\n#define AVR32_MSU_STATUS_RESULT_MASK 0x00000007\n#define AVR32_MSU_STATUS_WRAP_MASK 0x00000008\n#define AVR32_MSU_STATUS_RESETVALUE 0x00000000\n#define AVR32_MSU_DATA 0x000003F4\n#define AVR32_MSU_DATA_MASK 0xFFFFFFFF\n#define AVR32_MSU_DATA_RESETVALUE 0x00000000\n#define AVR32_MSU_TAIL 0x000003F8\n#define AVR32_MSU_TAIL_MASK 0xFFFFFFFC\n#define AVR32_MSU_TAIL_RESETVALUE 0x00000000\n\n#define AVR32_RAR_DBG 0x00000050\n#define AVR32_RSR_DBG 0x00000030\n#define AVR32_SR 0x00000000\n#define AVR32_SR_C 0\n#define AVR32_SR_C_MASK 0x00000001\n#define AVR32_SR_C_OFFSET 0\n#define AVR32_SR_C_SIZE 1\n#define AVR32_SR_D 26\n#define AVR32_SR_DM 27\n#define AVR32_SR_DM_MASK 0x08000000\n#define AVR32_SR_DM_OFFSET 27\n#define AVR32_SR_DM_SIZE 1\n#define AVR32_SR_D_MASK 0x04000000\n#define AVR32_SR_D_OFFSET 26\n#define AVR32_SR_D_SIZE 1\n#define AVR32_SR_EM 21\n#define AVR32_SR_EM_MASK 0x00200000\n#define AVR32_SR_EM_OFFSET 21\n#define AVR32_SR_EM_SIZE 1\n#define AVR32_SR_GM 16\n#define AVR32_SR_GM_MASK 0x00010000\n#define AVR32_SR_GM_OFFSET 16\n#define AVR32_SR_GM_SIZE 1\n#define AVR32_SR_I0M 17\n#define AVR32_SR_I0M_MASK 0x00020000\n#define AVR32_SR_I0M_OFFSET 17\n#define AVR32_SR_I0M_SIZE 1\n#define AVR32_SR_I1M 18\n#define AVR32_SR_I1M_MASK 0x00040000\n#define AVR32_SR_I1M_OFFSET 18\n#define AVR32_SR_I1M_SIZE 1\n#define AVR32_SR_I2M 19\n#define AVR32_SR_I2M_MASK 0x00080000\n#define AVR32_SR_I2M_OFFSET 19\n#define AVR32_SR_I2M_SIZE 1\n#define AVR32_SR_I3M 20\n#define AVR32_SR_I3M_MASK 0x00100000\n#define AVR32_SR_I3M_OFFSET 20\n#define AVR32_SR_I3M_SIZE 1\n#define AVR32_SR_L 5\n#define AVR32_SR_L_MASK 0x00000020\n#define AVR32_SR_L_OFFSET 5\n#define AVR32_SR_L_SIZE 1\n#define AVR32_SR_M0 22\n#define AVR32_SR_M0_MASK 0x00400000\n#define AVR32_SR_M0_OFFSET 22\n#define AVR32_SR_M0_SIZE 1\n#define AVR32_SR_M1 23\n#define AVR32_SR_M1_MASK 0x00800000\n#define AVR32_SR_M1_OFFSET 23\n#define AVR32_SR_M1_SIZE 1\n#define AVR32_SR_M2 24\n#define AVR32_SR_M2_MASK 0x01000000\n#define AVR32_SR_M2_OFFSET 24\n#define AVR32_SR_M2_SIZE 1\n#define AVR32_SR_M 22\n#define AVR32_SR_M_APP 0x00000000\n#define AVR32_SR_M_EX 0x00000006\n#define AVR32_SR_M_INT0 0x00000002\n#define AVR32_SR_M_INT1 0x00000003\n#define AVR32_SR_M_INT2 0x00000004\n#define AVR32_SR_M_INT3 0x00000005\n#define AVR32_SR_M_MASK 0x01c00000\n#define AVR32_SR_M_NMI 0x00000007\n#define AVR32_SR_M_OFFSET 22\n#define AVR32_SR_M_SIZE 3\n#define AVR32_SR_M_SUP 0x00000001\n#define AVR32_SR_N 2\n#define AVR32_SR_N_MASK 0x00000004\n#define AVR32_SR_N_OFFSET 2\n#define AVR32_SR_N_SIZE 1\n#define AVR32_SR_Q 4\n#define AVR32_SR_Q_MASK 0x00000010\n#define AVR32_SR_Q_OFFSET 4\n#define AVR32_SR_Q_SIZE 1\n#define AVR32_SR_T 14\n#define AVR32_SR_T_MASK 0x00004000\n#define AVR32_SR_T_OFFSET 14\n#define AVR32_SR_T_SIZE 1\n#define AVR32_SR_V 3\n#define AVR32_SR_V_MASK 0x00000008\n#define AVR32_SR_V_OFFSET 3\n#define AVR32_SR_V_SIZE 1\n#define AVR32_SR_Z 1\n#define AVR32_SR_Z_MASK 0x00000002\n#define AVR32_SR_Z_OFFSET 1\n#define AVR32_SR_Z_SIZE 1\n\n#define AVR32_EVBA_OFFSET_BREAKPOINT 0x0000001c\n#define AVR32_EVBA_OFFSET_BUS_ERROR_DATA 0x00000008\n#define AVR32_EVBA_OFFSET_BUS_ERROR_INSTR 0x0000000c\n#define AVR32_EVBA_OFFSET_COP_ABSENT 0x00000030\n#define AVR32_EVBA_OFFSET_DATA_ADDR_R 0x00000034\n#define AVR32_EVBA_OFFSET_DATA_ADDR_W 0x00000038\n#define AVR32_EVBA_OFFSET_DTLB_MISS_R 0x00000060\n#define AVR32_EVBA_OFFSET_DTLB_MISS_W 0x00000070\n#define AVR32_EVBA_OFFSET_DTLB_MODIFIED 0x00000044\n#define AVR32_EVBA_OFFSET_DTLB_PROT_R 0x0000003c\n#define AVR32_EVBA_OFFSET_DTLB_PROT_W 0x00000040\n#define AVR32_EVBA_OFFSET_FLOATING_POINT 0x0000002c\n#define AVR32_EVBA_OFFSET_ILLEGAL_OPCODE 0x00000020\n#define AVR32_EVBA_OFFSET_INSTR_ADDR 0x00000014\n#define AVR32_EVBA_OFFSET_ITLB_MISS 0x00000050\n#define AVR32_EVBA_OFFSET_ITLB_PROT 0x00000018\n#define AVR32_EVBA_OFFSET_NMI 0x00000010\n#define AVR32_EVBA_OFFSET_PRIVILEGE_VIOL 0x00000028\n#define AVR32_EVBA_OFFSET_SCALL 0x00000100\n#define AVR32_EVBA_OFFSET_TLB_MULTIPLE 0x00000004\n#define AVR32_EVBA_OFFSET_UNIMPLEMENTED 0x00000024\n#define AVR32_EVBA_OFFSET_UNRECOVERABLE 0x00000000\n#define AVR32_RESET_VECTOR 0x80000000\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_sr_t {\n unsigned int : 4;\n unsigned int dm : 1;\n unsigned int d : 1;\n unsigned int : 1;\n unsigned int m2 : 1;\n unsigned int m1 : 1;\n unsigned int m0 : 1;\n unsigned int em : 1;\n unsigned int i3m : 1;\n unsigned int i2m : 1;\n unsigned int i1m : 1;\n unsigned int i0m : 1;\n unsigned int gm : 1;\n unsigned int : 1;\n unsigned int t : 1;\n unsigned int : 8;\n unsigned int l : 1;\n unsigned int q : 1;\n unsigned int v : 1;\n unsigned int n : 1;\n unsigned int z : 1;\n unsigned int c : 1;\n} avr32_sr_t;\n\n\n\ntypedef struct avr32_cpucr_t {\n unsigned int :15;\n unsigned int locen : 1;\n unsigned int spl : 5;\n unsigned int cpl : 5;\n unsigned int cop : 5;\n unsigned int sie : 1;\n} avr32_cpucr_t;\n\n\n\ntypedef struct avr32_config0_t {\n unsigned int processorid : 8;\n unsigned int : 4;\n unsigned int processorrevision : 4;\n unsigned int at : 3;\n unsigned int ar : 3;\n unsigned int mmut : 3;\n unsigned int f : 1;\n unsigned int j : 1;\n unsigned int p : 1;\n unsigned int o : 1;\n unsigned int s : 1;\n unsigned int d : 1;\n unsigned int r : 1;\n} avr32_config0_t;\n\n\n\ntypedef struct avr32_config1_t {\n unsigned int immusz : 6;\n unsigned int dmmusz : 6;\n unsigned int iset : 4;\n unsigned int ilsz : 3;\n unsigned int iass : 3;\n unsigned int dset : 4;\n unsigned int dlsz : 3;\n unsigned int dass : 3;\n} avr32_config1_t;\n\n\n\ntypedef struct avr32_mpuar0_t {\n unsigned int base :20;\n unsigned int : 6;\n unsigned int size : 5;\n unsigned int v : 1;\n} avr32_mpuar0_t;\n\n\n\ntypedef struct avr32_mpuar1_t {\n unsigned int base :20;\n unsigned int : 6;\n unsigned int size : 5;\n unsigned int v : 1;\n} avr32_mpuar1_t;\n\n\n\ntypedef struct avr32_mpuar2_t {\n unsigned int base :20;\n unsigned int : 6;\n unsigned int size : 5;\n unsigned int v : 1;\n} avr32_mpuar2_t;\n\n\n\ntypedef struct avr32_mpuar3_t {\n unsigned int base :20;\n unsigned int : 6;\n unsigned int size : 5;\n unsigned int v : 1;\n} avr32_mpuar3_t;\n\n\n\ntypedef struct avr32_mpuar4_t {\n unsigned int base :20;\n unsigned int : 6;\n unsigned int size : 5;\n unsigned int v : 1;\n} avr32_mpuar4_t;\n\n\n\ntypedef struct avr32_mpuar5_t {\n unsigned int base :20;\n unsigned int : 6;\n unsigned int size : 5;\n unsigned int v : 1;\n} avr32_mpuar5_t;\n\n\n\ntypedef struct avr32_mpuar6_t {\n unsigned int base :20;\n unsigned int : 6;\n unsigned int size : 5;\n unsigned int v : 1;\n} avr32_mpuar6_t;\n\n\n\ntypedef struct avr32_mpuar7_t {\n unsigned int base :20;\n unsigned int : 6;\n unsigned int size : 5;\n unsigned int v : 1;\n} avr32_mpuar7_t;\n\n\n\ntypedef struct avr32_mpupsr0_t {\n unsigned int :16;\n unsigned int p15 : 1;\n unsigned int p14 : 1;\n unsigned int p13 : 1;\n unsigned int p12 : 1;\n unsigned int p11 : 1;\n unsigned int p10 : 1;\n unsigned int p9 : 1;\n unsigned int p8 : 1;\n unsigned int p7 : 1;\n unsigned int p6 : 1;\n unsigned int p5 : 1;\n unsigned int p4 : 1;\n unsigned int p3 : 1;\n unsigned int p2 : 1;\n unsigned int p1 : 1;\n unsigned int p0 : 1;\n} avr32_mpupsr0_t;\n\n\n\ntypedef struct avr32_mpupsr1_t {\n unsigned int :16;\n unsigned int p15 : 1;\n unsigned int p14 : 1;\n unsigned int p13 : 1;\n unsigned int p12 : 1;\n unsigned int p11 : 1;\n unsigned int p10 : 1;\n unsigned int p9 : 1;\n unsigned int p8 : 1;\n unsigned int p7 : 1;\n unsigned int p6 : 1;\n unsigned int p5 : 1;\n unsigned int p4 : 1;\n unsigned int p3 : 1;\n unsigned int p2 : 1;\n unsigned int p1 : 1;\n unsigned int p0 : 1;\n} avr32_mpupsr1_t;\n\n\n\ntypedef struct avr32_mpupsr2_t {\n unsigned int :16;\n unsigned int p15 : 1;\n unsigned int p14 : 1;\n unsigned int p13 : 1;\n unsigned int p12 : 1;\n unsigned int p11 : 1;\n unsigned int p10 : 1;\n unsigned int p9 : 1;\n unsigned int p8 : 1;\n unsigned int p7 : 1;\n unsigned int p6 : 1;\n unsigned int p5 : 1;\n unsigned int p4 : 1;\n unsigned int p3 : 1;\n unsigned int p2 : 1;\n unsigned int p1 : 1;\n unsigned int p0 : 1;\n} avr32_mpupsr2_t;\n\n\n\ntypedef struct avr32_mpupsr3_t {\n unsigned int :16;\n unsigned int p15 : 1;\n unsigned int p14 : 1;\n unsigned int p13 : 1;\n unsigned int p12 : 1;\n unsigned int p11 : 1;\n unsigned int p10 : 1;\n unsigned int p9 : 1;\n unsigned int p8 : 1;\n unsigned int p7 : 1;\n unsigned int p6 : 1;\n unsigned int p5 : 1;\n unsigned int p4 : 1;\n unsigned int p3 : 1;\n unsigned int p2 : 1;\n unsigned int p1 : 1;\n unsigned int p0 : 1;\n} avr32_mpupsr3_t;\n\n\n\ntypedef struct avr32_mpupsr4_t {\n unsigned int :16;\n unsigned int p15 : 1;\n unsigned int p14 : 1;\n unsigned int p13 : 1;\n unsigned int p12 : 1;\n unsigned int p11 : 1;\n unsigned int p10 : 1;\n unsigned int p9 : 1;\n unsigned int p8 : 1;\n unsigned int p7 : 1;\n unsigned int p6 : 1;\n unsigned int p5 : 1;\n unsigned int p4 : 1;\n unsigned int p3 : 1;\n unsigned int p2 : 1;\n unsigned int p1 : 1;\n unsigned int p0 : 1;\n} avr32_mpupsr4_t;\n\n\n\ntypedef struct avr32_mpupsr5_t {\n unsigned int :16;\n unsigned int p15 : 1;\n unsigned int p14 : 1;\n unsigned int p13 : 1;\n unsigned int p12 : 1;\n unsigned int p11 : 1;\n unsigned int p10 : 1;\n unsigned int p9 : 1;\n unsigned int p8 : 1;\n unsigned int p7 : 1;\n unsigned int p6 : 1;\n unsigned int p5 : 1;\n unsigned int p4 : 1;\n unsigned int p3 : 1;\n unsigned int p2 : 1;\n unsigned int p1 : 1;\n unsigned int p0 : 1;\n} avr32_mpupsr5_t;\n\n\n\ntypedef struct avr32_mpupsr6_t {\n unsigned int :16;\n unsigned int p15 : 1;\n unsigned int p14 : 1;\n unsigned int p13 : 1;\n unsigned int p12 : 1;\n unsigned int p11 : 1;\n unsigned int p10 : 1;\n unsigned int p9 : 1;\n unsigned int p8 : 1;\n unsigned int p7 : 1;\n unsigned int p6 : 1;\n unsigned int p5 : 1;\n unsigned int p4 : 1;\n unsigned int p3 : 1;\n unsigned int p2 : 1;\n unsigned int p1 : 1;\n unsigned int p0 : 1;\n} avr32_mpupsr6_t;\n\n\n\ntypedef struct avr32_mpupsr7_t {\n unsigned int :16;\n unsigned int p15 : 1;\n unsigned int p14 : 1;\n unsigned int p13 : 1;\n unsigned int p12 : 1;\n unsigned int p11 : 1;\n unsigned int p10 : 1;\n unsigned int p9 : 1;\n unsigned int p8 : 1;\n unsigned int p7 : 1;\n unsigned int p6 : 1;\n unsigned int p5 : 1;\n unsigned int p4 : 1;\n unsigned int p3 : 1;\n unsigned int p2 : 1;\n unsigned int p1 : 1;\n unsigned int p0 : 1;\n} avr32_mpupsr7_t;\n\n\n\ntypedef struct avr32_mpucra_t {\n unsigned int :24;\n unsigned int c7 : 1;\n unsigned int c6 : 1;\n unsigned int c5 : 1;\n unsigned int c4 : 1;\n unsigned int c3 : 1;\n unsigned int c2 : 1;\n unsigned int c1 : 1;\n unsigned int c0 : 1;\n} avr32_mpucra_t;\n\n\n\ntypedef struct avr32_mpucrb_t {\n unsigned int :24;\n unsigned int c7 : 1;\n unsigned int c6 : 1;\n unsigned int c5 : 1;\n unsigned int c4 : 1;\n unsigned int c3 : 1;\n unsigned int c2 : 1;\n unsigned int c1 : 1;\n unsigned int c0 : 1;\n} avr32_mpucrb_t;\n\n\n\ntypedef struct avr32_mpubra_t {\n unsigned int :24;\n unsigned int b7 : 1;\n unsigned int b6 : 1;\n unsigned int b5 : 1;\n unsigned int b4 : 1;\n unsigned int b3 : 1;\n unsigned int b2 : 1;\n unsigned int b1 : 1;\n unsigned int b0 : 1;\n} avr32_mpubra_t;\n\n\n\ntypedef struct avr32_mpubrb_t {\n unsigned int :24;\n unsigned int b7 : 1;\n unsigned int b6 : 1;\n unsigned int b5 : 1;\n unsigned int b4 : 1;\n unsigned int b3 : 1;\n unsigned int b2 : 1;\n unsigned int b1 : 1;\n unsigned int b0 : 1;\n} avr32_mpubrb_t;\n\n\n\ntypedef struct avr32_mpuapra_t {\n unsigned int ap7 : 4;\n unsigned int ap6 : 4;\n unsigned int ap5 : 4;\n unsigned int ap4 : 4;\n unsigned int ap3 : 4;\n unsigned int ap2 : 4;\n unsigned int ap1 : 4;\n unsigned int ap0 : 4;\n} avr32_mpuapra_t;\n\n\n\ntypedef struct avr32_mpuaprb_t {\n unsigned int ap7 : 4;\n unsigned int ap6 : 4;\n unsigned int ap5 : 4;\n unsigned int ap4 : 4;\n unsigned int ap3 : 4;\n unsigned int ap2 : 4;\n unsigned int ap1 : 4;\n unsigned int ap0 : 4;\n} avr32_mpuaprb_t;\n\n\n\ntypedef struct avr32_mpucr_t {\n unsigned int :31;\n unsigned int e : 1;\n} avr32_mpucr_t;\n\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n\n#if !defined (DEPRECATED_DISABLE)\n\n#define AVR32_MPUAPRA_AP0_EXECUTE 0x00000001\n#define AVR32_MPUAPRA_AP0_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRA_AP0_USER 0x00000004\n#define AVR32_MPUAPRA_AP0_WRITE 0x00000002\n\n#define AVR32_MPUAPRA_AP1_EXECUTE 0x00000001\n#define AVR32_MPUAPRA_AP1_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRA_AP1_USER 0x00000004\n#define AVR32_MPUAPRA_AP1_WRITE 0x00000002\n\n#define AVR32_MPUAPRA_AP2_EXECUTE 0x00000001\n#define AVR32_MPUAPRA_AP2_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRA_AP2_USER 0x00000004\n#define AVR32_MPUAPRA_AP2_WRITE 0x00000002\n\n#define AVR32_MPUAPRA_AP3_EXECUTE 0x00000001\n#define AVR32_MPUAPRA_AP3_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRA_AP3_USER 0x00000004\n#define AVR32_MPUAPRA_AP3_WRITE 0x00000002\n\n#define AVR32_MPUAPRA_AP4_EXECUTE 0x00000001\n#define AVR32_MPUAPRA_AP4_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRA_AP4_USER 0x00000004\n#define AVR32_MPUAPRA_AP4_WRITE 0x00000002\n\n#define AVR32_MPUAPRA_AP5_EXECUTE 0x00000001\n#define AVR32_MPUAPRA_AP5_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRA_AP5_USER 0x00000004\n#define AVR32_MPUAPRA_AP5_WRITE 0x00000002\n\n#define AVR32_MPUAPRA_AP6_EXECUTE 0x00000001\n#define AVR32_MPUAPRA_AP6_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRA_AP6_USER 0x00000004\n#define AVR32_MPUAPRA_AP6_WRITE 0x00000002\n\n#define AVR32_MPUAPRA_AP7_EXECUTE 0x00000001\n#define AVR32_MPUAPRA_AP7_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRA_AP7_USER 0x00000004\n#define AVR32_MPUAPRA_AP7_WRITE 0x00000002\n\n#define AVR32_MPUAPRB_AP0_EXECUTE 0x00000001\n#define AVR32_MPUAPRB_AP0_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRB_AP0_USER 0x00000004\n#define AVR32_MPUAPRB_AP0_WRITE 0x00000002\n\n#define AVR32_MPUAPRB_AP1_EXECUTE 0x00000001\n#define AVR32_MPUAPRB_AP1_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRB_AP1_USER 0x00000004\n#define AVR32_MPUAPRB_AP1_WRITE 0x00000002\n\n#define AVR32_MPUAPRB_AP2_EXECUTE 0x00000001\n#define AVR32_MPUAPRB_AP2_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRB_AP2_USER 0x00000004\n#define AVR32_MPUAPRB_AP2_WRITE 0x00000002\n\n#define AVR32_MPUAPRB_AP3_EXECUTE 0x00000001\n#define AVR32_MPUAPRB_AP3_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRB_AP3_USER 0x00000004\n#define AVR32_MPUAPRB_AP3_WRITE 0x00000002\n\n#define AVR32_MPUAPRB_AP4_EXECUTE 0x00000001\n#define AVR32_MPUAPRB_AP4_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRB_AP4_USER 0x00000004\n#define AVR32_MPUAPRB_AP4_WRITE 0x00000002\n\n#define AVR32_MPUAPRB_AP5_EXECUTE 0x00000001\n#define AVR32_MPUAPRB_AP5_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRB_AP5_USER 0x00000004\n#define AVR32_MPUAPRB_AP5_WRITE 0x00000002\n\n#define AVR32_MPUAPRB_AP6_EXECUTE 0x00000001\n#define AVR32_MPUAPRB_AP6_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRB_AP6_USER 0x00000004\n#define AVR32_MPUAPRB_AP6_WRITE 0x00000002\n\n#define AVR32_MPUAPRB_AP7_EXECUTE 0x00000001\n#define AVR32_MPUAPRB_AP7_SUP_WRITE 0x00000008\n#define AVR32_MPUAPRB_AP7_USER 0x00000004\n#define AVR32_MPUAPRB_AP7_WRITE 0x00000002\n\n\n#endif\n\n\n/*#ifdef AVR32_CORE_SC0_130_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/eic_230.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3000\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_EIC_230_H_INCLUDED\n#define AVR32_EIC_230_H_INCLUDED\n\n#define AVR32_EIC_H_VERSION 230\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_EIC_\n - Bitfield mask: AVR32_EIC__\n - Bitfield offset: AVR32_EIC___OFFSET\n - Bitfield size: AVR32_EIC___SIZE\n - Bitfield values: AVR32_EIC___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_EIC_\n - Bitfield offset: AVR32_EIC__OFFSET\n - Bitfield size: AVR32_EIC__SIZE\n - Bitfield values: AVR32_EIC__\n - Bitfield values: AVR32_EIC_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_EIC_ASYNC 0x00000028\n#define AVR32_EIC_ASYNC_INT0 0\n#define AVR32_EIC_ASYNC_INT0_MASK 0x00000001\n#define AVR32_EIC_ASYNC_INT0_OFFSET 0\n#define AVR32_EIC_ASYNC_INT0_SIZE 1\n#define AVR32_EIC_ASYNC_INT1 1\n#define AVR32_EIC_ASYNC_INT1_MASK 0x00000002\n#define AVR32_EIC_ASYNC_INT1_OFFSET 1\n#define AVR32_EIC_ASYNC_INT1_SIZE 1\n#define AVR32_EIC_ASYNC_INT2 2\n#define AVR32_EIC_ASYNC_INT2_MASK 0x00000004\n#define AVR32_EIC_ASYNC_INT2_OFFSET 2\n#define AVR32_EIC_ASYNC_INT2_SIZE 1\n#define AVR32_EIC_ASYNC_INT3 3\n#define AVR32_EIC_ASYNC_INT3_MASK 0x00000008\n#define AVR32_EIC_ASYNC_INT3_OFFSET 3\n#define AVR32_EIC_ASYNC_INT3_SIZE 1\n#define AVR32_EIC_ASYNC_INT4 4\n#define AVR32_EIC_ASYNC_INT4_MASK 0x00000010\n#define AVR32_EIC_ASYNC_INT4_OFFSET 4\n#define AVR32_EIC_ASYNC_INT4_SIZE 1\n#define AVR32_EIC_ASYNC_INT5 5\n#define AVR32_EIC_ASYNC_INT5_MASK 0x00000020\n#define AVR32_EIC_ASYNC_INT5_OFFSET 5\n#define AVR32_EIC_ASYNC_INT5_SIZE 1\n#define AVR32_EIC_ASYNC_INT6 6\n#define AVR32_EIC_ASYNC_INT6_MASK 0x00000040\n#define AVR32_EIC_ASYNC_INT6_OFFSET 6\n#define AVR32_EIC_ASYNC_INT6_SIZE 1\n#define AVR32_EIC_ASYNC_INT7 7\n#define AVR32_EIC_ASYNC_INT7_MASK 0x00000080\n#define AVR32_EIC_ASYNC_INT7_OFFSET 7\n#define AVR32_EIC_ASYNC_INT7_SIZE 1\n#define AVR32_EIC_ASYNC_NMI 8\n#define AVR32_EIC_ASYNC_NMI_MASK 0x00000100\n#define AVR32_EIC_ASYNC_NMI_OFFSET 8\n#define AVR32_EIC_ASYNC_NMI_SIZE 1\n#define AVR32_EIC_CTRL 0x00000038\n#define AVR32_EIC_CTRL_INT0 0\n#define AVR32_EIC_CTRL_INT0_MASK 0x00000001\n#define AVR32_EIC_CTRL_INT0_OFFSET 0\n#define AVR32_EIC_CTRL_INT0_SIZE 1\n#define AVR32_EIC_CTRL_INT1 1\n#define AVR32_EIC_CTRL_INT1_MASK 0x00000002\n#define AVR32_EIC_CTRL_INT1_OFFSET 1\n#define AVR32_EIC_CTRL_INT1_SIZE 1\n#define AVR32_EIC_CTRL_INT2 2\n#define AVR32_EIC_CTRL_INT2_MASK 0x00000004\n#define AVR32_EIC_CTRL_INT2_OFFSET 2\n#define AVR32_EIC_CTRL_INT2_SIZE 1\n#define AVR32_EIC_CTRL_INT3 3\n#define AVR32_EIC_CTRL_INT3_MASK 0x00000008\n#define AVR32_EIC_CTRL_INT3_OFFSET 3\n#define AVR32_EIC_CTRL_INT3_SIZE 1\n#define AVR32_EIC_CTRL_INT4 4\n#define AVR32_EIC_CTRL_INT4_MASK 0x00000010\n#define AVR32_EIC_CTRL_INT4_OFFSET 4\n#define AVR32_EIC_CTRL_INT4_SIZE 1\n#define AVR32_EIC_CTRL_INT5 5\n#define AVR32_EIC_CTRL_INT5_MASK 0x00000020\n#define AVR32_EIC_CTRL_INT5_OFFSET 5\n#define AVR32_EIC_CTRL_INT5_SIZE 1\n#define AVR32_EIC_CTRL_INT6 6\n#define AVR32_EIC_CTRL_INT6_MASK 0x00000040\n#define AVR32_EIC_CTRL_INT6_OFFSET 6\n#define AVR32_EIC_CTRL_INT6_SIZE 1\n#define AVR32_EIC_CTRL_INT7 7\n#define AVR32_EIC_CTRL_INT7_MASK 0x00000080\n#define AVR32_EIC_CTRL_INT7_OFFSET 7\n#define AVR32_EIC_CTRL_INT7_SIZE 1\n#define AVR32_EIC_CTRL_NMI 8\n#define AVR32_EIC_CTRL_NMI_MASK 0x00000100\n#define AVR32_EIC_CTRL_NMI_OFFSET 8\n#define AVR32_EIC_CTRL_NMI_SIZE 1\n#define AVR32_EIC_DIS 0x00000034\n#define AVR32_EIC_DIS_INT0 0\n#define AVR32_EIC_DIS_INT0_MASK 0x00000001\n#define AVR32_EIC_DIS_INT0_OFFSET 0\n#define AVR32_EIC_DIS_INT0_SIZE 1\n#define AVR32_EIC_DIS_INT1 1\n#define AVR32_EIC_DIS_INT1_MASK 0x00000002\n#define AVR32_EIC_DIS_INT1_OFFSET 1\n#define AVR32_EIC_DIS_INT1_SIZE 1\n#define AVR32_EIC_DIS_INT2 2\n#define AVR32_EIC_DIS_INT2_MASK 0x00000004\n#define AVR32_EIC_DIS_INT2_OFFSET 2\n#define AVR32_EIC_DIS_INT2_SIZE 1\n#define AVR32_EIC_DIS_INT3 3\n#define AVR32_EIC_DIS_INT3_MASK 0x00000008\n#define AVR32_EIC_DIS_INT3_OFFSET 3\n#define AVR32_EIC_DIS_INT3_SIZE 1\n#define AVR32_EIC_DIS_INT4 4\n#define AVR32_EIC_DIS_INT4_MASK 0x00000010\n#define AVR32_EIC_DIS_INT4_OFFSET 4\n#define AVR32_EIC_DIS_INT4_SIZE 1\n#define AVR32_EIC_DIS_INT5 5\n#define AVR32_EIC_DIS_INT5_MASK 0x00000020\n#define AVR32_EIC_DIS_INT5_OFFSET 5\n#define AVR32_EIC_DIS_INT5_SIZE 1\n#define AVR32_EIC_DIS_INT6 6\n#define AVR32_EIC_DIS_INT6_MASK 0x00000040\n#define AVR32_EIC_DIS_INT6_OFFSET 6\n#define AVR32_EIC_DIS_INT6_SIZE 1\n#define AVR32_EIC_DIS_INT7 7\n#define AVR32_EIC_DIS_INT7_MASK 0x00000080\n#define AVR32_EIC_DIS_INT7_OFFSET 7\n#define AVR32_EIC_DIS_INT7_SIZE 1\n#define AVR32_EIC_DIS_NMI 8\n#define AVR32_EIC_DIS_NMI_MASK 0x00000100\n#define AVR32_EIC_DIS_NMI_OFFSET 8\n#define AVR32_EIC_DIS_NMI_SIZE 1\n#define AVR32_EIC_EDGE 0x00000018\n#define AVR32_EIC_EDGE_INT0 0\n#define AVR32_EIC_EDGE_INT0_MASK 0x00000001\n#define AVR32_EIC_EDGE_INT0_OFFSET 0\n#define AVR32_EIC_EDGE_INT0_SIZE 1\n#define AVR32_EIC_EDGE_INT1 1\n#define AVR32_EIC_EDGE_INT1_MASK 0x00000002\n#define AVR32_EIC_EDGE_INT1_OFFSET 1\n#define AVR32_EIC_EDGE_INT1_SIZE 1\n#define AVR32_EIC_EDGE_INT2 2\n#define AVR32_EIC_EDGE_INT2_MASK 0x00000004\n#define AVR32_EIC_EDGE_INT2_OFFSET 2\n#define AVR32_EIC_EDGE_INT2_SIZE 1\n#define AVR32_EIC_EDGE_INT3 3\n#define AVR32_EIC_EDGE_INT3_MASK 0x00000008\n#define AVR32_EIC_EDGE_INT3_OFFSET 3\n#define AVR32_EIC_EDGE_INT3_SIZE 1\n#define AVR32_EIC_EDGE_INT4 4\n#define AVR32_EIC_EDGE_INT4_MASK 0x00000010\n#define AVR32_EIC_EDGE_INT4_OFFSET 4\n#define AVR32_EIC_EDGE_INT4_SIZE 1\n#define AVR32_EIC_EDGE_INT5 5\n#define AVR32_EIC_EDGE_INT5_MASK 0x00000020\n#define AVR32_EIC_EDGE_INT5_OFFSET 5\n#define AVR32_EIC_EDGE_INT5_SIZE 1\n#define AVR32_EIC_EDGE_INT6 6\n#define AVR32_EIC_EDGE_INT6_MASK 0x00000040\n#define AVR32_EIC_EDGE_INT6_OFFSET 6\n#define AVR32_EIC_EDGE_INT6_SIZE 1\n#define AVR32_EIC_EDGE_INT7 7\n#define AVR32_EIC_EDGE_INT7_MASK 0x00000080\n#define AVR32_EIC_EDGE_INT7_OFFSET 7\n#define AVR32_EIC_EDGE_INT7_SIZE 1\n#define AVR32_EIC_EDGE_NMI 8\n#define AVR32_EIC_EDGE_NMI_MASK 0x00000100\n#define AVR32_EIC_EDGE_NMI_OFFSET 8\n#define AVR32_EIC_EDGE_NMI_SIZE 1\n#define AVR32_EIC_EN 0x00000030\n#define AVR32_EIC_EN_INT0 0\n#define AVR32_EIC_EN_INT0_MASK 0x00000001\n#define AVR32_EIC_EN_INT0_OFFSET 0\n#define AVR32_EIC_EN_INT0_SIZE 1\n#define AVR32_EIC_EN_INT1 1\n#define AVR32_EIC_EN_INT1_MASK 0x00000002\n#define AVR32_EIC_EN_INT1_OFFSET 1\n#define AVR32_EIC_EN_INT1_SIZE 1\n#define AVR32_EIC_EN_INT2 2\n#define AVR32_EIC_EN_INT2_MASK 0x00000004\n#define AVR32_EIC_EN_INT2_OFFSET 2\n#define AVR32_EIC_EN_INT2_SIZE 1\n#define AVR32_EIC_EN_INT3 3\n#define AVR32_EIC_EN_INT3_MASK 0x00000008\n#define AVR32_EIC_EN_INT3_OFFSET 3\n#define AVR32_EIC_EN_INT3_SIZE 1\n#define AVR32_EIC_EN_INT4 4\n#define AVR32_EIC_EN_INT4_MASK 0x00000010\n#define AVR32_EIC_EN_INT4_OFFSET 4\n#define AVR32_EIC_EN_INT4_SIZE 1\n#define AVR32_EIC_EN_INT5 5\n#define AVR32_EIC_EN_INT5_MASK 0x00000020\n#define AVR32_EIC_EN_INT5_OFFSET 5\n#define AVR32_EIC_EN_INT5_SIZE 1\n#define AVR32_EIC_EN_INT6 6\n#define AVR32_EIC_EN_INT6_MASK 0x00000040\n#define AVR32_EIC_EN_INT6_OFFSET 6\n#define AVR32_EIC_EN_INT6_SIZE 1\n#define AVR32_EIC_EN_INT7 7\n#define AVR32_EIC_EN_INT7_MASK 0x00000080\n#define AVR32_EIC_EN_INT7_OFFSET 7\n#define AVR32_EIC_EN_INT7_SIZE 1\n#define AVR32_EIC_EN_MASK 0x00000001\n#define AVR32_EIC_EN_NMI 8\n#define AVR32_EIC_EN_NMI_MASK 0x00000100\n#define AVR32_EIC_EN_NMI_OFFSET 8\n#define AVR32_EIC_EN_NMI_SIZE 1\n#define AVR32_EIC_EN_OFFSET 0\n#define AVR32_EIC_EN_SIZE 1\n#define AVR32_EIC_FILTER 0x00000020\n#define AVR32_EIC_FILTER_INT0 0\n#define AVR32_EIC_FILTER_INT0_MASK 0x00000001\n#define AVR32_EIC_FILTER_INT0_OFFSET 0\n#define AVR32_EIC_FILTER_INT0_SIZE 1\n#define AVR32_EIC_FILTER_INT1 1\n#define AVR32_EIC_FILTER_INT1_MASK 0x00000002\n#define AVR32_EIC_FILTER_INT1_OFFSET 1\n#define AVR32_EIC_FILTER_INT1_SIZE 1\n#define AVR32_EIC_FILTER_INT2 2\n#define AVR32_EIC_FILTER_INT2_MASK 0x00000004\n#define AVR32_EIC_FILTER_INT2_OFFSET 2\n#define AVR32_EIC_FILTER_INT2_SIZE 1\n#define AVR32_EIC_FILTER_INT3 3\n#define AVR32_EIC_FILTER_INT3_MASK 0x00000008\n#define AVR32_EIC_FILTER_INT3_OFFSET 3\n#define AVR32_EIC_FILTER_INT3_SIZE 1\n#define AVR32_EIC_FILTER_INT4 4\n#define AVR32_EIC_FILTER_INT4_MASK 0x00000010\n#define AVR32_EIC_FILTER_INT4_OFFSET 4\n#define AVR32_EIC_FILTER_INT4_SIZE 1\n#define AVR32_EIC_FILTER_INT5 5\n#define AVR32_EIC_FILTER_INT5_MASK 0x00000020\n#define AVR32_EIC_FILTER_INT5_OFFSET 5\n#define AVR32_EIC_FILTER_INT5_SIZE 1\n#define AVR32_EIC_FILTER_INT6 6\n#define AVR32_EIC_FILTER_INT6_MASK 0x00000040\n#define AVR32_EIC_FILTER_INT6_OFFSET 6\n#define AVR32_EIC_FILTER_INT6_SIZE 1\n#define AVR32_EIC_FILTER_INT7 7\n#define AVR32_EIC_FILTER_INT7_MASK 0x00000080\n#define AVR32_EIC_FILTER_INT7_OFFSET 7\n#define AVR32_EIC_FILTER_INT7_SIZE 1\n#define AVR32_EIC_FILTER_NMI 8\n#define AVR32_EIC_FILTER_NMI_MASK 0x00000100\n#define AVR32_EIC_FILTER_NMI_OFFSET 8\n#define AVR32_EIC_FILTER_NMI_SIZE 1\n#define AVR32_EIC_ICR 0x00000010\n#define AVR32_EIC_ICR_INT0 0\n#define AVR32_EIC_ICR_INT0_MASK 0x00000001\n#define AVR32_EIC_ICR_INT0_OFFSET 0\n#define AVR32_EIC_ICR_INT0_SIZE 1\n#define AVR32_EIC_ICR_INT1 1\n#define AVR32_EIC_ICR_INT1_MASK 0x00000002\n#define AVR32_EIC_ICR_INT1_OFFSET 1\n#define AVR32_EIC_ICR_INT1_SIZE 1\n#define AVR32_EIC_ICR_INT2 2\n#define AVR32_EIC_ICR_INT2_MASK 0x00000004\n#define AVR32_EIC_ICR_INT2_OFFSET 2\n#define AVR32_EIC_ICR_INT2_SIZE 1\n#define AVR32_EIC_ICR_INT3 3\n#define AVR32_EIC_ICR_INT3_MASK 0x00000008\n#define AVR32_EIC_ICR_INT3_OFFSET 3\n#define AVR32_EIC_ICR_INT3_SIZE 1\n#define AVR32_EIC_ICR_INT4 4\n#define AVR32_EIC_ICR_INT4_MASK 0x00000010\n#define AVR32_EIC_ICR_INT4_OFFSET 4\n#define AVR32_EIC_ICR_INT4_SIZE 1\n#define AVR32_EIC_ICR_INT5 5\n#define AVR32_EIC_ICR_INT5_MASK 0x00000020\n#define AVR32_EIC_ICR_INT5_OFFSET 5\n#define AVR32_EIC_ICR_INT5_SIZE 1\n#define AVR32_EIC_ICR_INT6 6\n#define AVR32_EIC_ICR_INT6_MASK 0x00000040\n#define AVR32_EIC_ICR_INT6_OFFSET 6\n#define AVR32_EIC_ICR_INT6_SIZE 1\n#define AVR32_EIC_ICR_INT7 7\n#define AVR32_EIC_ICR_INT7_MASK 0x00000080\n#define AVR32_EIC_ICR_INT7_OFFSET 7\n#define AVR32_EIC_ICR_INT7_SIZE 1\n#define AVR32_EIC_ICR_NMI 8\n#define AVR32_EIC_ICR_NMI_MASK 0x00000100\n#define AVR32_EIC_ICR_NMI_OFFSET 8\n#define AVR32_EIC_ICR_NMI_SIZE 1\n#define AVR32_EIC_IDR 0x00000004\n#define AVR32_EIC_IDR_INT0 0\n#define AVR32_EIC_IDR_INT0_MASK 0x00000001\n#define AVR32_EIC_IDR_INT0_OFFSET 0\n#define AVR32_EIC_IDR_INT0_SIZE 1\n#define AVR32_EIC_IDR_INT1 1\n#define AVR32_EIC_IDR_INT1_MASK 0x00000002\n#define AVR32_EIC_IDR_INT1_OFFSET 1\n#define AVR32_EIC_IDR_INT1_SIZE 1\n#define AVR32_EIC_IDR_INT2 2\n#define AVR32_EIC_IDR_INT2_MASK 0x00000004\n#define AVR32_EIC_IDR_INT2_OFFSET 2\n#define AVR32_EIC_IDR_INT2_SIZE 1\n#define AVR32_EIC_IDR_INT3 3\n#define AVR32_EIC_IDR_INT3_MASK 0x00000008\n#define AVR32_EIC_IDR_INT3_OFFSET 3\n#define AVR32_EIC_IDR_INT3_SIZE 1\n#define AVR32_EIC_IDR_INT4 4\n#define AVR32_EIC_IDR_INT4_MASK 0x00000010\n#define AVR32_EIC_IDR_INT4_OFFSET 4\n#define AVR32_EIC_IDR_INT4_SIZE 1\n#define AVR32_EIC_IDR_INT5 5\n#define AVR32_EIC_IDR_INT5_MASK 0x00000020\n#define AVR32_EIC_IDR_INT5_OFFSET 5\n#define AVR32_EIC_IDR_INT5_SIZE 1\n#define AVR32_EIC_IDR_INT6 6\n#define AVR32_EIC_IDR_INT6_MASK 0x00000040\n#define AVR32_EIC_IDR_INT6_OFFSET 6\n#define AVR32_EIC_IDR_INT6_SIZE 1\n#define AVR32_EIC_IDR_INT7 7\n#define AVR32_EIC_IDR_INT7_MASK 0x00000080\n#define AVR32_EIC_IDR_INT7_OFFSET 7\n#define AVR32_EIC_IDR_INT7_SIZE 1\n#define AVR32_EIC_IDR_NMI 8\n#define AVR32_EIC_IDR_NMI_MASK 0x00000100\n#define AVR32_EIC_IDR_NMI_OFFSET 8\n#define AVR32_EIC_IDR_NMI_SIZE 1\n#define AVR32_EIC_IER 0x00000000\n#define AVR32_EIC_IER_INT0 0\n#define AVR32_EIC_IER_INT0_MASK 0x00000001\n#define AVR32_EIC_IER_INT0_OFFSET 0\n#define AVR32_EIC_IER_INT0_SIZE 1\n#define AVR32_EIC_IER_INT1 1\n#define AVR32_EIC_IER_INT1_MASK 0x00000002\n#define AVR32_EIC_IER_INT1_OFFSET 1\n#define AVR32_EIC_IER_INT1_SIZE 1\n#define AVR32_EIC_IER_INT2 2\n#define AVR32_EIC_IER_INT2_MASK 0x00000004\n#define AVR32_EIC_IER_INT2_OFFSET 2\n#define AVR32_EIC_IER_INT2_SIZE 1\n#define AVR32_EIC_IER_INT3 3\n#define AVR32_EIC_IER_INT3_MASK 0x00000008\n#define AVR32_EIC_IER_INT3_OFFSET 3\n#define AVR32_EIC_IER_INT3_SIZE 1\n#define AVR32_EIC_IER_INT4 4\n#define AVR32_EIC_IER_INT4_MASK 0x00000010\n#define AVR32_EIC_IER_INT4_OFFSET 4\n#define AVR32_EIC_IER_INT4_SIZE 1\n#define AVR32_EIC_IER_INT5 5\n#define AVR32_EIC_IER_INT5_MASK 0x00000020\n#define AVR32_EIC_IER_INT5_OFFSET 5\n#define AVR32_EIC_IER_INT5_SIZE 1\n#define AVR32_EIC_IER_INT6 6\n#define AVR32_EIC_IER_INT6_MASK 0x00000040\n#define AVR32_EIC_IER_INT6_OFFSET 6\n#define AVR32_EIC_IER_INT6_SIZE 1\n#define AVR32_EIC_IER_INT7 7\n#define AVR32_EIC_IER_INT7_MASK 0x00000080\n#define AVR32_EIC_IER_INT7_OFFSET 7\n#define AVR32_EIC_IER_INT7_SIZE 1\n#define AVR32_EIC_IER_NMI 8\n#define AVR32_EIC_IER_NMI_MASK 0x00000100\n#define AVR32_EIC_IER_NMI_OFFSET 8\n#define AVR32_EIC_IER_NMI_SIZE 1\n#define AVR32_EIC_IMR 0x00000008\n#define AVR32_EIC_IMR_INT0 0\n#define AVR32_EIC_IMR_INT0_MASK 0x00000001\n#define AVR32_EIC_IMR_INT0_OFFSET 0\n#define AVR32_EIC_IMR_INT0_SIZE 1\n#define AVR32_EIC_IMR_INT1 1\n#define AVR32_EIC_IMR_INT1_MASK 0x00000002\n#define AVR32_EIC_IMR_INT1_OFFSET 1\n#define AVR32_EIC_IMR_INT1_SIZE 1\n#define AVR32_EIC_IMR_INT2 2\n#define AVR32_EIC_IMR_INT2_MASK 0x00000004\n#define AVR32_EIC_IMR_INT2_OFFSET 2\n#define AVR32_EIC_IMR_INT2_SIZE 1\n#define AVR32_EIC_IMR_INT3 3\n#define AVR32_EIC_IMR_INT3_MASK 0x00000008\n#define AVR32_EIC_IMR_INT3_OFFSET 3\n#define AVR32_EIC_IMR_INT3_SIZE 1\n#define AVR32_EIC_IMR_INT4 4\n#define AVR32_EIC_IMR_INT4_MASK 0x00000010\n#define AVR32_EIC_IMR_INT4_OFFSET 4\n#define AVR32_EIC_IMR_INT4_SIZE 1\n#define AVR32_EIC_IMR_INT5 5\n#define AVR32_EIC_IMR_INT5_MASK 0x00000020\n#define AVR32_EIC_IMR_INT5_OFFSET 5\n#define AVR32_EIC_IMR_INT5_SIZE 1\n#define AVR32_EIC_IMR_INT6 6\n#define AVR32_EIC_IMR_INT6_MASK 0x00000040\n#define AVR32_EIC_IMR_INT6_OFFSET 6\n#define AVR32_EIC_IMR_INT6_SIZE 1\n#define AVR32_EIC_IMR_INT7 7\n#define AVR32_EIC_IMR_INT7_MASK 0x00000080\n#define AVR32_EIC_IMR_INT7_OFFSET 7\n#define AVR32_EIC_IMR_INT7_SIZE 1\n#define AVR32_EIC_IMR_NMI 8\n#define AVR32_EIC_IMR_NMI_MASK 0x00000100\n#define AVR32_EIC_IMR_NMI_OFFSET 8\n#define AVR32_EIC_IMR_NMI_SIZE 1\n#define AVR32_EIC_INT0 0\n#define AVR32_EIC_INT0_MASK 0x00000001\n#define AVR32_EIC_INT0_OFFSET 0\n#define AVR32_EIC_INT0_SIZE 1\n#define AVR32_EIC_INT1 1\n#define AVR32_EIC_INT1_MASK 0x00000002\n#define AVR32_EIC_INT1_OFFSET 1\n#define AVR32_EIC_INT1_SIZE 1\n#define AVR32_EIC_INT2 2\n#define AVR32_EIC_INT2_MASK 0x00000004\n#define AVR32_EIC_INT2_OFFSET 2\n#define AVR32_EIC_INT2_SIZE 1\n#define AVR32_EIC_INT3 3\n#define AVR32_EIC_INT3_MASK 0x00000008\n#define AVR32_EIC_INT3_OFFSET 3\n#define AVR32_EIC_INT3_SIZE 1\n#define AVR32_EIC_INT4 4\n#define AVR32_EIC_INT4_MASK 0x00000010\n#define AVR32_EIC_INT4_OFFSET 4\n#define AVR32_EIC_INT4_SIZE 1\n#define AVR32_EIC_INT5 5\n#define AVR32_EIC_INT5_MASK 0x00000020\n#define AVR32_EIC_INT5_OFFSET 5\n#define AVR32_EIC_INT5_SIZE 1\n#define AVR32_EIC_INT6 6\n#define AVR32_EIC_INT6_MASK 0x00000040\n#define AVR32_EIC_INT6_OFFSET 6\n#define AVR32_EIC_INT6_SIZE 1\n#define AVR32_EIC_INT7 7\n#define AVR32_EIC_INT7_MASK 0x00000080\n#define AVR32_EIC_INT7_OFFSET 7\n#define AVR32_EIC_INT7_SIZE 1\n#define AVR32_EIC_ISR 0x0000000c\n#define AVR32_EIC_ISR_INT0 0\n#define AVR32_EIC_ISR_INT0_MASK 0x00000001\n#define AVR32_EIC_ISR_INT0_OFFSET 0\n#define AVR32_EIC_ISR_INT0_SIZE 1\n#define AVR32_EIC_ISR_INT1 1\n#define AVR32_EIC_ISR_INT1_MASK 0x00000002\n#define AVR32_EIC_ISR_INT1_OFFSET 1\n#define AVR32_EIC_ISR_INT1_SIZE 1\n#define AVR32_EIC_ISR_INT2 2\n#define AVR32_EIC_ISR_INT2_MASK 0x00000004\n#define AVR32_EIC_ISR_INT2_OFFSET 2\n#define AVR32_EIC_ISR_INT2_SIZE 1\n#define AVR32_EIC_ISR_INT3 3\n#define AVR32_EIC_ISR_INT3_MASK 0x00000008\n#define AVR32_EIC_ISR_INT3_OFFSET 3\n#define AVR32_EIC_ISR_INT3_SIZE 1\n#define AVR32_EIC_ISR_INT4 4\n#define AVR32_EIC_ISR_INT4_MASK 0x00000010\n#define AVR32_EIC_ISR_INT4_OFFSET 4\n#define AVR32_EIC_ISR_INT4_SIZE 1\n#define AVR32_EIC_ISR_INT5 5\n#define AVR32_EIC_ISR_INT5_MASK 0x00000020\n#define AVR32_EIC_ISR_INT5_OFFSET 5\n#define AVR32_EIC_ISR_INT5_SIZE 1\n#define AVR32_EIC_ISR_INT6 6\n#define AVR32_EIC_ISR_INT6_MASK 0x00000040\n#define AVR32_EIC_ISR_INT6_OFFSET 6\n#define AVR32_EIC_ISR_INT6_SIZE 1\n#define AVR32_EIC_ISR_INT7 7\n#define AVR32_EIC_ISR_INT7_MASK 0x00000080\n#define AVR32_EIC_ISR_INT7_OFFSET 7\n#define AVR32_EIC_ISR_INT7_SIZE 1\n#define AVR32_EIC_ISR_NMI 8\n#define AVR32_EIC_ISR_NMI_MASK 0x00000100\n#define AVR32_EIC_ISR_NMI_OFFSET 8\n#define AVR32_EIC_ISR_NMI_SIZE 1\n#define AVR32_EIC_LEVEL 0x0000001c\n#define AVR32_EIC_LEVEL_INT0 0\n#define AVR32_EIC_LEVEL_INT0_MASK 0x00000001\n#define AVR32_EIC_LEVEL_INT0_OFFSET 0\n#define AVR32_EIC_LEVEL_INT0_SIZE 1\n#define AVR32_EIC_LEVEL_INT1 1\n#define AVR32_EIC_LEVEL_INT1_MASK 0x00000002\n#define AVR32_EIC_LEVEL_INT1_OFFSET 1\n#define AVR32_EIC_LEVEL_INT1_SIZE 1\n#define AVR32_EIC_LEVEL_INT2 2\n#define AVR32_EIC_LEVEL_INT2_MASK 0x00000004\n#define AVR32_EIC_LEVEL_INT2_OFFSET 2\n#define AVR32_EIC_LEVEL_INT2_SIZE 1\n#define AVR32_EIC_LEVEL_INT3 3\n#define AVR32_EIC_LEVEL_INT3_MASK 0x00000008\n#define AVR32_EIC_LEVEL_INT3_OFFSET 3\n#define AVR32_EIC_LEVEL_INT3_SIZE 1\n#define AVR32_EIC_LEVEL_INT4 4\n#define AVR32_EIC_LEVEL_INT4_MASK 0x00000010\n#define AVR32_EIC_LEVEL_INT4_OFFSET 4\n#define AVR32_EIC_LEVEL_INT4_SIZE 1\n#define AVR32_EIC_LEVEL_INT5 5\n#define AVR32_EIC_LEVEL_INT5_MASK 0x00000020\n#define AVR32_EIC_LEVEL_INT5_OFFSET 5\n#define AVR32_EIC_LEVEL_INT5_SIZE 1\n#define AVR32_EIC_LEVEL_INT6 6\n#define AVR32_EIC_LEVEL_INT6_MASK 0x00000040\n#define AVR32_EIC_LEVEL_INT6_OFFSET 6\n#define AVR32_EIC_LEVEL_INT6_SIZE 1\n#define AVR32_EIC_LEVEL_INT7 7\n#define AVR32_EIC_LEVEL_INT7_MASK 0x00000080\n#define AVR32_EIC_LEVEL_INT7_OFFSET 7\n#define AVR32_EIC_LEVEL_INT7_SIZE 1\n#define AVR32_EIC_LEVEL_NMI 8\n#define AVR32_EIC_LEVEL_NMI_MASK 0x00000100\n#define AVR32_EIC_LEVEL_NMI_OFFSET 8\n#define AVR32_EIC_LEVEL_NMI_SIZE 1\n#define AVR32_EIC_MODE 0x00000014\n#define AVR32_EIC_MODE_INT0 0\n#define AVR32_EIC_MODE_INT0_MASK 0x00000001\n#define AVR32_EIC_MODE_INT0_OFFSET 0\n#define AVR32_EIC_MODE_INT0_SIZE 1\n#define AVR32_EIC_MODE_INT1 1\n#define AVR32_EIC_MODE_INT1_MASK 0x00000002\n#define AVR32_EIC_MODE_INT1_OFFSET 1\n#define AVR32_EIC_MODE_INT1_SIZE 1\n#define AVR32_EIC_MODE_INT2 2\n#define AVR32_EIC_MODE_INT2_MASK 0x00000004\n#define AVR32_EIC_MODE_INT2_OFFSET 2\n#define AVR32_EIC_MODE_INT2_SIZE 1\n#define AVR32_EIC_MODE_INT3 3\n#define AVR32_EIC_MODE_INT3_MASK 0x00000008\n#define AVR32_EIC_MODE_INT3_OFFSET 3\n#define AVR32_EIC_MODE_INT3_SIZE 1\n#define AVR32_EIC_MODE_INT4 4\n#define AVR32_EIC_MODE_INT4_MASK 0x00000010\n#define AVR32_EIC_MODE_INT4_OFFSET 4\n#define AVR32_EIC_MODE_INT4_SIZE 1\n#define AVR32_EIC_MODE_INT5 5\n#define AVR32_EIC_MODE_INT5_MASK 0x00000020\n#define AVR32_EIC_MODE_INT5_OFFSET 5\n#define AVR32_EIC_MODE_INT5_SIZE 1\n#define AVR32_EIC_MODE_INT6 6\n#define AVR32_EIC_MODE_INT6_MASK 0x00000040\n#define AVR32_EIC_MODE_INT6_OFFSET 6\n#define AVR32_EIC_MODE_INT6_SIZE 1\n#define AVR32_EIC_MODE_INT7 7\n#define AVR32_EIC_MODE_INT7_MASK 0x00000080\n#define AVR32_EIC_MODE_INT7_OFFSET 7\n#define AVR32_EIC_MODE_INT7_SIZE 1\n#define AVR32_EIC_MODE_NMI 8\n#define AVR32_EIC_MODE_NMI_MASK 0x00000100\n#define AVR32_EIC_MODE_NMI_OFFSET 8\n#define AVR32_EIC_MODE_NMI_SIZE 1\n#define AVR32_EIC_NMI 8\n#define AVR32_EIC_NMI_MASK 0x00000100\n#define AVR32_EIC_NMI_OFFSET 8\n#define AVR32_EIC_NMI_SIZE 1\n#define AVR32_EIC_PIN 24\n#define AVR32_EIC_PIN_MASK 0x07000000\n#define AVR32_EIC_PIN_OFFSET 24\n#define AVR32_EIC_PIN_SIZE 3\n#define AVR32_EIC_PRESC 8\n#define AVR32_EIC_PRESC_MASK 0x00001f00\n#define AVR32_EIC_PRESC_OFFSET 8\n#define AVR32_EIC_PRESC_SIZE 5\n#define AVR32_EIC_SCAN 0x0000002c\n#define AVR32_EIC_SCAN_EN 0\n#define AVR32_EIC_SCAN_EN_MASK 0x00000001\n#define AVR32_EIC_SCAN_EN_OFFSET 0\n#define AVR32_EIC_SCAN_EN_SIZE 1\n#define AVR32_EIC_SCAN_PIN 24\n#define AVR32_EIC_SCAN_PIN_MASK 0x07000000\n#define AVR32_EIC_SCAN_PIN_OFFSET 24\n#define AVR32_EIC_SCAN_PIN_SIZE 3\n#define AVR32_EIC_SCAN_PRESC 8\n#define AVR32_EIC_SCAN_PRESC_MASK 0x00001f00\n#define AVR32_EIC_SCAN_PRESC_OFFSET 8\n#define AVR32_EIC_SCAN_PRESC_SIZE 5\n#define AVR32_EIC_TEST 0x00000024\n#define AVR32_EIC_TEST_EN 31\n#define AVR32_EIC_TEST_EN_MASK 0x80000000\n#define AVR32_EIC_TEST_EN_OFFSET 31\n#define AVR32_EIC_TEST_EN_SIZE 1\n#define AVR32_EIC_TEST_INT0 0\n#define AVR32_EIC_TEST_INT0_MASK 0x00000001\n#define AVR32_EIC_TEST_INT0_OFFSET 0\n#define AVR32_EIC_TEST_INT0_SIZE 1\n#define AVR32_EIC_TEST_INT1 1\n#define AVR32_EIC_TEST_INT1_MASK 0x00000002\n#define AVR32_EIC_TEST_INT1_OFFSET 1\n#define AVR32_EIC_TEST_INT1_SIZE 1\n#define AVR32_EIC_TEST_INT2 2\n#define AVR32_EIC_TEST_INT2_MASK 0x00000004\n#define AVR32_EIC_TEST_INT2_OFFSET 2\n#define AVR32_EIC_TEST_INT2_SIZE 1\n#define AVR32_EIC_TEST_INT3 3\n#define AVR32_EIC_TEST_INT3_MASK 0x00000008\n#define AVR32_EIC_TEST_INT3_OFFSET 3\n#define AVR32_EIC_TEST_INT3_SIZE 1\n#define AVR32_EIC_TEST_INT4 4\n#define AVR32_EIC_TEST_INT4_MASK 0x00000010\n#define AVR32_EIC_TEST_INT4_OFFSET 4\n#define AVR32_EIC_TEST_INT4_SIZE 1\n#define AVR32_EIC_TEST_INT5 5\n#define AVR32_EIC_TEST_INT5_MASK 0x00000020\n#define AVR32_EIC_TEST_INT5_OFFSET 5\n#define AVR32_EIC_TEST_INT5_SIZE 1\n#define AVR32_EIC_TEST_INT6 6\n#define AVR32_EIC_TEST_INT6_MASK 0x00000040\n#define AVR32_EIC_TEST_INT6_OFFSET 6\n#define AVR32_EIC_TEST_INT6_SIZE 1\n#define AVR32_EIC_TEST_INT7 7\n#define AVR32_EIC_TEST_INT7_MASK 0x00000080\n#define AVR32_EIC_TEST_INT7_OFFSET 7\n#define AVR32_EIC_TEST_INT7_SIZE 1\n#define AVR32_EIC_TEST_NMI 8\n#define AVR32_EIC_TEST_NMI_MASK 0x00000100\n#define AVR32_EIC_TEST_NMI_OFFSET 8\n#define AVR32_EIC_TEST_NMI_SIZE 1\n#define AVR32_EIC_TEST_TEST_EN 31\n#define AVR32_EIC_TEST_TEST_EN_MASK 0x80000000\n#define AVR32_EIC_TEST_TEST_EN_OFFSET 31\n#define AVR32_EIC_TEST_TEST_EN_SIZE 1\n\n#define AVR32_EIC_EDGE_IRQ 0x00000000\n#define AVR32_EIC_FALLING_EDGE 0x00000000\n#define AVR32_EIC_FILTER_OFF 0x00000000\n#define AVR32_EIC_FILTER_ON 0x00000001\n#define AVR32_EIC_HIGH_LEVEL 0x00000001\n#define AVR32_EIC_LEVEL_IRQ 0x00000001\n#define AVR32_EIC_LOW_LEVEL 0x00000000\n#define AVR32_EIC_RISING_EDGE 0x00000001\n#define AVR32_EIC_SYNC 0x00000000\n#define AVR32_EIC_USE_ASYNC 0x00000001\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_eic_ier_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_ier_t;\n\n\n\ntypedef struct avr32_eic_idr_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_idr_t;\n\n\n\ntypedef struct avr32_eic_imr_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_imr_t;\n\n\n\ntypedef struct avr32_eic_isr_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_isr_t;\n\n\n\ntypedef struct avr32_eic_icr_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_icr_t;\n\n\n\ntypedef struct avr32_eic_mode_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_mode_t;\n\n\n\ntypedef struct avr32_eic_edge_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_edge_t;\n\n\n\ntypedef struct avr32_eic_level_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_level_t;\n\n\n\ntypedef struct avr32_eic_filter_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_filter_t;\n\n\n\ntypedef struct avr32_eic_test_t {\n unsigned int test_en : 1;\n unsigned int :22;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_test_t;\n\n\n\ntypedef struct avr32_eic_async_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_async_t;\n\n\n\ntypedef struct avr32_eic_scan_t {\n unsigned int : 5;\n unsigned int pin : 3;\n unsigned int :11;\n unsigned int presc : 5;\n unsigned int : 7;\n unsigned int en : 1;\n} avr32_eic_scan_t;\n\n\n\ntypedef struct avr32_eic_en_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_en_t;\n\n\n\ntypedef struct avr32_eic_dis_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_dis_t;\n\n\n\ntypedef struct avr32_eic_ctrl_t {\n unsigned int :23;\n unsigned int nmi : 1;\n unsigned int int7 : 1;\n unsigned int int6 : 1;\n unsigned int int5 : 1;\n unsigned int int4 : 1;\n unsigned int int3 : 1;\n unsigned int int2 : 1;\n unsigned int int1 : 1;\n unsigned int int0 : 1;\n} avr32_eic_ctrl_t;\n\n\n\ntypedef struct avr32_eic_t {\n union {\n unsigned long ier ;//0x0000\n avr32_eic_ier_t IER ;\n };\n union {\n unsigned long idr ;//0x0004\n avr32_eic_idr_t IDR ;\n };\n union {\n const unsigned long imr ;//0x0008\n const avr32_eic_imr_t IMR ;\n };\n union {\n const unsigned long isr ;//0x000c\n const avr32_eic_isr_t ISR ;\n };\n union {\n unsigned long icr ;//0x0010\n avr32_eic_icr_t ICR ;\n };\n union {\n unsigned long mode ;//0x0014\n avr32_eic_mode_t MODE ;\n };\n union {\n unsigned long edge ;//0x0018\n avr32_eic_edge_t EDGE ;\n };\n union {\n unsigned long level ;//0x001c\n avr32_eic_level_t LEVEL ;\n };\n union {\n unsigned long filter ;//0x0020\n avr32_eic_filter_t FILTER ;\n };\n union {\n unsigned long test ;//0x0024\n avr32_eic_test_t TEST ;\n };\n union {\n unsigned long async ;//0x0028\n avr32_eic_async_t ASYNC ;\n };\n union {\n unsigned long scan ;//0x002c\n avr32_eic_scan_t SCAN ;\n };\n union {\n unsigned long en ;//0x0030\n avr32_eic_en_t EN ;\n };\n union {\n unsigned long dis ;//0x0034\n avr32_eic_dis_t DIS ;\n };\n union {\n unsigned long ctrl ;//0x0038\n avr32_eic_ctrl_t CTRL ;\n };\n} avr32_eic_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n/*#ifdef AVR32_EIC_230_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/flashc_200.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3A0512\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_FLASHC_200_H_INCLUDED\n#define AVR32_FLASHC_200_H_INCLUDED\n\n#define AVR32_FLASHC_H_VERSION 200\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_FLASHC_\n - Bitfield mask: AVR32_FLASHC__\n - Bitfield offset: AVR32_FLASHC___OFFSET\n - Bitfield size: AVR32_FLASHC___SIZE\n - Bitfield values: AVR32_FLASHC___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_FLASHC_\n - Bitfield offset: AVR32_FLASHC__OFFSET\n - Bitfield size: AVR32_FLASHC__SIZE\n - Bitfield values: AVR32_FLASHC__\n - Bitfield values: AVR32_FLASHC_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_FLASHC_1024 0x00000007\n#define AVR32_FLASHC_128 0x00000002\n#define AVR32_FLASHC_256 0x00000003\n#define AVR32_FLASHC_32 0x00000000\n#define AVR32_FLASHC_384 0x00000004\n#define AVR32_FLASHC_512 0x00000005\n#define AVR32_FLASHC_64 0x00000001\n#define AVR32_FLASHC_768 0x00000006\n#define AVR32_FLASHC_BOOTPROT 17\n#define AVR32_FLASHC_BOOTPROT_MASK 0x000e0000\n#define AVR32_FLASHC_BOOTPROT_OFFSET 17\n#define AVR32_FLASHC_BOOTPROT_SIZE 3\n#define AVR32_FLASHC_CMD 0\n#define AVR32_FLASHC_CMD_CPB 0x00000003\n#define AVR32_FLASHC_CMD_EA 0x00000006\n#define AVR32_FLASHC_CMD_EAGPF 0x0000000b\n#define AVR32_FLASHC_CMD_EGPB 0x00000008\n#define AVR32_FLASHC_CMD_EP 0x00000002\n#define AVR32_FLASHC_CMD_EUP 0x0000000e\n#define AVR32_FLASHC_CMD_LP 0x00000004\n#define AVR32_FLASHC_CMD_MASK 0x0000003f\n#define AVR32_FLASHC_CMD_NOP 0x00000000\n#define AVR32_FLASHC_CMD_OFFSET 0\n#define AVR32_FLASHC_CMD_PGPFB 0x0000000a\n#define AVR32_FLASHC_CMD_QPR 0x0000000c\n#define AVR32_FLASHC_CMD_QPRUP 0x0000000f\n#define AVR32_FLASHC_CMD_SIZE 6\n#define AVR32_FLASHC_CMD_SSB 0x00000009\n#define AVR32_FLASHC_CMD_UP 0x00000005\n#define AVR32_FLASHC_CMD_WGPB 0x00000007\n#define AVR32_FLASHC_CMD_WP 0x00000001\n#define AVR32_FLASHC_CMD_WUP 0x0000000d\n#define AVR32_FLASHC_CPB 0x00000003\n#define AVR32_FLASHC_EA 0x00000006\n#define AVR32_FLASHC_EAGPF 0x0000000b\n#define AVR32_FLASHC_EGPB 0x00000008\n#define AVR32_FLASHC_EP 0x00000002\n#define AVR32_FLASHC_EPFL 16\n#define AVR32_FLASHC_EPFL_MASK 0x00010000\n#define AVR32_FLASHC_EPFL_OFFSET 16\n#define AVR32_FLASHC_EPFL_SIZE 1\n#define AVR32_FLASHC_EUP 0x0000000e\n#define AVR32_FLASHC_FCMD 0x00000004\n#define AVR32_FLASHC_FCMD_CMD 0\n#define AVR32_FLASHC_FCMD_CMD_CPB 0x00000003\n#define AVR32_FLASHC_FCMD_CMD_EA 0x00000006\n#define AVR32_FLASHC_FCMD_CMD_EAGPF 0x0000000b\n#define AVR32_FLASHC_FCMD_CMD_EGPB 0x00000008\n#define AVR32_FLASHC_FCMD_CMD_EP 0x00000002\n#define AVR32_FLASHC_FCMD_CMD_EUP 0x0000000e\n#define AVR32_FLASHC_FCMD_CMD_LP 0x00000004\n#define AVR32_FLASHC_FCMD_CMD_MASK 0x0000003f\n#define AVR32_FLASHC_FCMD_CMD_NOP 0x00000000\n#define AVR32_FLASHC_FCMD_CMD_OFFSET 0\n#define AVR32_FLASHC_FCMD_CMD_PGPFB 0x0000000a\n#define AVR32_FLASHC_FCMD_CMD_QPR 0x0000000c\n#define AVR32_FLASHC_FCMD_CMD_QPRUP 0x0000000f\n#define AVR32_FLASHC_FCMD_CMD_SIZE 6\n#define AVR32_FLASHC_FCMD_CMD_SSB 0x00000009\n#define AVR32_FLASHC_FCMD_CMD_UP 0x00000005\n#define AVR32_FLASHC_FCMD_CMD_WGPB 0x00000007\n#define AVR32_FLASHC_FCMD_CMD_WP 0x00000001\n#define AVR32_FLASHC_FCMD_CMD_WUP 0x0000000d\n#define AVR32_FLASHC_FCMD_KEY 24\n#define AVR32_FLASHC_FCMD_KEY_KEY 0x000000a5\n#define AVR32_FLASHC_FCMD_KEY_MASK 0xff000000\n#define AVR32_FLASHC_FCMD_KEY_OFFSET 24\n#define AVR32_FLASHC_FCMD_KEY_SIZE 8\n#define AVR32_FLASHC_FCMD_PAGEN 8\n#define AVR32_FLASHC_FCMD_PAGEN_MASK 0x00ffff00\n#define AVR32_FLASHC_FCMD_PAGEN_OFFSET 8\n#define AVR32_FLASHC_FCMD_PAGEN_SIZE 16\n#define AVR32_FLASHC_FCR 0x00000000\n#define AVR32_FLASHC_FCR_FRDY 0\n#define AVR32_FLASHC_FCR_FRDY_MASK 0x00000001\n#define AVR32_FLASHC_FCR_FRDY_OFFSET 0\n#define AVR32_FLASHC_FCR_FRDY_SIZE 1\n#define AVR32_FLASHC_FCR_FWS 6\n#define AVR32_FLASHC_FCR_FWS_MASK 0x00000040\n#define AVR32_FLASHC_FCR_FWS_OFFSET 6\n#define AVR32_FLASHC_FCR_FWS_SIZE 1\n#define AVR32_FLASHC_FCR_LOCKE 2\n#define AVR32_FLASHC_FCR_LOCKE_MASK 0x00000004\n#define AVR32_FLASHC_FCR_LOCKE_OFFSET 2\n#define AVR32_FLASHC_FCR_LOCKE_SIZE 1\n#define AVR32_FLASHC_FCR_PROGE 3\n#define AVR32_FLASHC_FCR_PROGE_MASK 0x00000008\n#define AVR32_FLASHC_FCR_PROGE_OFFSET 3\n#define AVR32_FLASHC_FCR_PROGE_SIZE 1\n#define AVR32_FLASHC_FGPFRHI 0x0000000c\n#define AVR32_FLASHC_FGPFRHI_GPF32 0\n#define AVR32_FLASHC_FGPFRHI_GPF32_MASK 0x00000001\n#define AVR32_FLASHC_FGPFRHI_GPF32_OFFSET 0\n#define AVR32_FLASHC_FGPFRHI_GPF32_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF33 1\n#define AVR32_FLASHC_FGPFRHI_GPF33_MASK 0x00000002\n#define AVR32_FLASHC_FGPFRHI_GPF33_OFFSET 1\n#define AVR32_FLASHC_FGPFRHI_GPF33_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF34 2\n#define AVR32_FLASHC_FGPFRHI_GPF34_MASK 0x00000004\n#define AVR32_FLASHC_FGPFRHI_GPF34_OFFSET 2\n#define AVR32_FLASHC_FGPFRHI_GPF34_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF35 3\n#define AVR32_FLASHC_FGPFRHI_GPF35_MASK 0x00000008\n#define AVR32_FLASHC_FGPFRHI_GPF35_OFFSET 3\n#define AVR32_FLASHC_FGPFRHI_GPF35_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF36 4\n#define AVR32_FLASHC_FGPFRHI_GPF36_MASK 0x00000010\n#define AVR32_FLASHC_FGPFRHI_GPF36_OFFSET 4\n#define AVR32_FLASHC_FGPFRHI_GPF36_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF37 5\n#define AVR32_FLASHC_FGPFRHI_GPF37_MASK 0x00000020\n#define AVR32_FLASHC_FGPFRHI_GPF37_OFFSET 5\n#define AVR32_FLASHC_FGPFRHI_GPF37_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF38 6\n#define AVR32_FLASHC_FGPFRHI_GPF38_MASK 0x00000040\n#define AVR32_FLASHC_FGPFRHI_GPF38_OFFSET 6\n#define AVR32_FLASHC_FGPFRHI_GPF38_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF39 7\n#define AVR32_FLASHC_FGPFRHI_GPF39_MASK 0x00000080\n#define AVR32_FLASHC_FGPFRHI_GPF39_OFFSET 7\n#define AVR32_FLASHC_FGPFRHI_GPF39_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF40 8\n#define AVR32_FLASHC_FGPFRHI_GPF40_MASK 0x00000100\n#define AVR32_FLASHC_FGPFRHI_GPF40_OFFSET 8\n#define AVR32_FLASHC_FGPFRHI_GPF40_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF41 9\n#define AVR32_FLASHC_FGPFRHI_GPF41_MASK 0x00000200\n#define AVR32_FLASHC_FGPFRHI_GPF41_OFFSET 9\n#define AVR32_FLASHC_FGPFRHI_GPF41_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF42 10\n#define AVR32_FLASHC_FGPFRHI_GPF42_MASK 0x00000400\n#define AVR32_FLASHC_FGPFRHI_GPF42_OFFSET 10\n#define AVR32_FLASHC_FGPFRHI_GPF42_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF43 11\n#define AVR32_FLASHC_FGPFRHI_GPF43_MASK 0x00000800\n#define AVR32_FLASHC_FGPFRHI_GPF43_OFFSET 11\n#define AVR32_FLASHC_FGPFRHI_GPF43_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF44 12\n#define AVR32_FLASHC_FGPFRHI_GPF44_MASK 0x00001000\n#define AVR32_FLASHC_FGPFRHI_GPF44_OFFSET 12\n#define AVR32_FLASHC_FGPFRHI_GPF44_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF45 13\n#define AVR32_FLASHC_FGPFRHI_GPF45_MASK 0x00002000\n#define AVR32_FLASHC_FGPFRHI_GPF45_OFFSET 13\n#define AVR32_FLASHC_FGPFRHI_GPF45_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF46 14\n#define AVR32_FLASHC_FGPFRHI_GPF46_MASK 0x00004000\n#define AVR32_FLASHC_FGPFRHI_GPF46_OFFSET 14\n#define AVR32_FLASHC_FGPFRHI_GPF46_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF47 15\n#define AVR32_FLASHC_FGPFRHI_GPF47_MASK 0x00008000\n#define AVR32_FLASHC_FGPFRHI_GPF47_OFFSET 15\n#define AVR32_FLASHC_FGPFRHI_GPF47_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF48 16\n#define AVR32_FLASHC_FGPFRHI_GPF48_MASK 0x00010000\n#define AVR32_FLASHC_FGPFRHI_GPF48_OFFSET 16\n#define AVR32_FLASHC_FGPFRHI_GPF48_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF49 17\n#define AVR32_FLASHC_FGPFRHI_GPF49_MASK 0x00020000\n#define AVR32_FLASHC_FGPFRHI_GPF49_OFFSET 17\n#define AVR32_FLASHC_FGPFRHI_GPF49_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF50 18\n#define AVR32_FLASHC_FGPFRHI_GPF50_MASK 0x00040000\n#define AVR32_FLASHC_FGPFRHI_GPF50_OFFSET 18\n#define AVR32_FLASHC_FGPFRHI_GPF50_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF51 19\n#define AVR32_FLASHC_FGPFRHI_GPF51_MASK 0x00080000\n#define AVR32_FLASHC_FGPFRHI_GPF51_OFFSET 19\n#define AVR32_FLASHC_FGPFRHI_GPF51_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF52 20\n#define AVR32_FLASHC_FGPFRHI_GPF52_MASK 0x00100000\n#define AVR32_FLASHC_FGPFRHI_GPF52_OFFSET 20\n#define AVR32_FLASHC_FGPFRHI_GPF52_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF53 21\n#define AVR32_FLASHC_FGPFRHI_GPF53_MASK 0x00200000\n#define AVR32_FLASHC_FGPFRHI_GPF53_OFFSET 21\n#define AVR32_FLASHC_FGPFRHI_GPF53_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF54 22\n#define AVR32_FLASHC_FGPFRHI_GPF54_MASK 0x00400000\n#define AVR32_FLASHC_FGPFRHI_GPF54_OFFSET 22\n#define AVR32_FLASHC_FGPFRHI_GPF54_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF55 23\n#define AVR32_FLASHC_FGPFRHI_GPF55_MASK 0x00800000\n#define AVR32_FLASHC_FGPFRHI_GPF55_OFFSET 23\n#define AVR32_FLASHC_FGPFRHI_GPF55_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF56 24\n#define AVR32_FLASHC_FGPFRHI_GPF56_MASK 0x01000000\n#define AVR32_FLASHC_FGPFRHI_GPF56_OFFSET 24\n#define AVR32_FLASHC_FGPFRHI_GPF56_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF57 25\n#define AVR32_FLASHC_FGPFRHI_GPF57_MASK 0x02000000\n#define AVR32_FLASHC_FGPFRHI_GPF57_OFFSET 25\n#define AVR32_FLASHC_FGPFRHI_GPF57_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF58 26\n#define AVR32_FLASHC_FGPFRHI_GPF58_MASK 0x04000000\n#define AVR32_FLASHC_FGPFRHI_GPF58_OFFSET 26\n#define AVR32_FLASHC_FGPFRHI_GPF58_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF59 27\n#define AVR32_FLASHC_FGPFRHI_GPF59_MASK 0x08000000\n#define AVR32_FLASHC_FGPFRHI_GPF59_OFFSET 27\n#define AVR32_FLASHC_FGPFRHI_GPF59_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF60 28\n#define AVR32_FLASHC_FGPFRHI_GPF60_MASK 0x10000000\n#define AVR32_FLASHC_FGPFRHI_GPF60_OFFSET 28\n#define AVR32_FLASHC_FGPFRHI_GPF60_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF61 29\n#define AVR32_FLASHC_FGPFRHI_GPF61_MASK 0x20000000\n#define AVR32_FLASHC_FGPFRHI_GPF61_OFFSET 29\n#define AVR32_FLASHC_FGPFRHI_GPF61_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF62 30\n#define AVR32_FLASHC_FGPFRHI_GPF62_MASK 0x40000000\n#define AVR32_FLASHC_FGPFRHI_GPF62_OFFSET 30\n#define AVR32_FLASHC_FGPFRHI_GPF62_SIZE 1\n#define AVR32_FLASHC_FGPFRHI_GPF63 31\n#define AVR32_FLASHC_FGPFRHI_GPF63_MASK 0x80000000\n#define AVR32_FLASHC_FGPFRHI_GPF63_OFFSET 31\n#define AVR32_FLASHC_FGPFRHI_GPF63_SIZE 1\n#define AVR32_FLASHC_FGPFRLO 0x00000010\n#define AVR32_FLASHC_FGPFRLO_BOOTPROT 17\n#define AVR32_FLASHC_FGPFRLO_BOOTPROT_MASK 0x000e0000\n#define AVR32_FLASHC_FGPFRLO_BOOTPROT_OFFSET 17\n#define AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE 3\n#define AVR32_FLASHC_FGPFRLO_EPFL 16\n#define AVR32_FLASHC_FGPFRLO_EPFL_MASK 0x00010000\n#define AVR32_FLASHC_FGPFRLO_EPFL_OFFSET 16\n#define AVR32_FLASHC_FGPFRLO_EPFL_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_GPF20 20\n#define AVR32_FLASHC_FGPFRLO_GPF20_MASK 0x00100000\n#define AVR32_FLASHC_FGPFRLO_GPF20_OFFSET 20\n#define AVR32_FLASHC_FGPFRLO_GPF20_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_GPF21 21\n#define AVR32_FLASHC_FGPFRLO_GPF21_MASK 0x00200000\n#define AVR32_FLASHC_FGPFRLO_GPF21_OFFSET 21\n#define AVR32_FLASHC_FGPFRLO_GPF21_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_GPF22 22\n#define AVR32_FLASHC_FGPFRLO_GPF22_MASK 0x00400000\n#define AVR32_FLASHC_FGPFRLO_GPF22_OFFSET 22\n#define AVR32_FLASHC_FGPFRLO_GPF22_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_GPF23 23\n#define AVR32_FLASHC_FGPFRLO_GPF23_MASK 0x00800000\n#define AVR32_FLASHC_FGPFRLO_GPF23_OFFSET 23\n#define AVR32_FLASHC_FGPFRLO_GPF23_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_GPF24 24\n#define AVR32_FLASHC_FGPFRLO_GPF24_MASK 0x01000000\n#define AVR32_FLASHC_FGPFRLO_GPF24_OFFSET 24\n#define AVR32_FLASHC_FGPFRLO_GPF24_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_GPF25 25\n#define AVR32_FLASHC_FGPFRLO_GPF25_MASK 0x02000000\n#define AVR32_FLASHC_FGPFRLO_GPF25_OFFSET 25\n#define AVR32_FLASHC_FGPFRLO_GPF25_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_GPF26 26\n#define AVR32_FLASHC_FGPFRLO_GPF26_MASK 0x04000000\n#define AVR32_FLASHC_FGPFRLO_GPF26_OFFSET 26\n#define AVR32_FLASHC_FGPFRLO_GPF26_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_GPF27 27\n#define AVR32_FLASHC_FGPFRLO_GPF27_MASK 0x08000000\n#define AVR32_FLASHC_FGPFRLO_GPF27_OFFSET 27\n#define AVR32_FLASHC_FGPFRLO_GPF27_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_GPF28 28\n#define AVR32_FLASHC_FGPFRLO_GPF28_MASK 0x10000000\n#define AVR32_FLASHC_FGPFRLO_GPF28_OFFSET 28\n#define AVR32_FLASHC_FGPFRLO_GPF28_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_GPF29 29\n#define AVR32_FLASHC_FGPFRLO_GPF29_MASK 0x20000000\n#define AVR32_FLASHC_FGPFRLO_GPF29_OFFSET 29\n#define AVR32_FLASHC_FGPFRLO_GPF29_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_GPF30 30\n#define AVR32_FLASHC_FGPFRLO_GPF30_MASK 0x40000000\n#define AVR32_FLASHC_FGPFRLO_GPF30_OFFSET 30\n#define AVR32_FLASHC_FGPFRLO_GPF30_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_GPF31 31\n#define AVR32_FLASHC_FGPFRLO_GPF31_MASK 0x80000000\n#define AVR32_FLASHC_FGPFRLO_GPF31_OFFSET 31\n#define AVR32_FLASHC_FGPFRLO_GPF31_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK0 0\n#define AVR32_FLASHC_FGPFRLO_LOCK0_MASK 0x00000001\n#define AVR32_FLASHC_FGPFRLO_LOCK0_OFFSET 0\n#define AVR32_FLASHC_FGPFRLO_LOCK0_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK1 1\n#define AVR32_FLASHC_FGPFRLO_LOCK10 10\n#define AVR32_FLASHC_FGPFRLO_LOCK10_MASK 0x00000400\n#define AVR32_FLASHC_FGPFRLO_LOCK10_OFFSET 10\n#define AVR32_FLASHC_FGPFRLO_LOCK10_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK11 11\n#define AVR32_FLASHC_FGPFRLO_LOCK11_MASK 0x00000800\n#define AVR32_FLASHC_FGPFRLO_LOCK11_OFFSET 11\n#define AVR32_FLASHC_FGPFRLO_LOCK11_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK12 12\n#define AVR32_FLASHC_FGPFRLO_LOCK12_MASK 0x00001000\n#define AVR32_FLASHC_FGPFRLO_LOCK12_OFFSET 12\n#define AVR32_FLASHC_FGPFRLO_LOCK12_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK13 13\n#define AVR32_FLASHC_FGPFRLO_LOCK13_MASK 0x00002000\n#define AVR32_FLASHC_FGPFRLO_LOCK13_OFFSET 13\n#define AVR32_FLASHC_FGPFRLO_LOCK13_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK14 14\n#define AVR32_FLASHC_FGPFRLO_LOCK14_MASK 0x00004000\n#define AVR32_FLASHC_FGPFRLO_LOCK14_OFFSET 14\n#define AVR32_FLASHC_FGPFRLO_LOCK14_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK15 15\n#define AVR32_FLASHC_FGPFRLO_LOCK15_MASK 0x00008000\n#define AVR32_FLASHC_FGPFRLO_LOCK15_OFFSET 15\n#define AVR32_FLASHC_FGPFRLO_LOCK15_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK1_MASK 0x00000002\n#define AVR32_FLASHC_FGPFRLO_LOCK1_OFFSET 1\n#define AVR32_FLASHC_FGPFRLO_LOCK1_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK2 2\n#define AVR32_FLASHC_FGPFRLO_LOCK2_MASK 0x00000004\n#define AVR32_FLASHC_FGPFRLO_LOCK2_OFFSET 2\n#define AVR32_FLASHC_FGPFRLO_LOCK2_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK3 3\n#define AVR32_FLASHC_FGPFRLO_LOCK3_MASK 0x00000008\n#define AVR32_FLASHC_FGPFRLO_LOCK3_OFFSET 3\n#define AVR32_FLASHC_FGPFRLO_LOCK3_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK4 4\n#define AVR32_FLASHC_FGPFRLO_LOCK4_MASK 0x00000010\n#define AVR32_FLASHC_FGPFRLO_LOCK4_OFFSET 4\n#define AVR32_FLASHC_FGPFRLO_LOCK4_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK5 5\n#define AVR32_FLASHC_FGPFRLO_LOCK5_MASK 0x00000020\n#define AVR32_FLASHC_FGPFRLO_LOCK5_OFFSET 5\n#define AVR32_FLASHC_FGPFRLO_LOCK5_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK6 6\n#define AVR32_FLASHC_FGPFRLO_LOCK6_MASK 0x00000040\n#define AVR32_FLASHC_FGPFRLO_LOCK6_OFFSET 6\n#define AVR32_FLASHC_FGPFRLO_LOCK6_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK7 7\n#define AVR32_FLASHC_FGPFRLO_LOCK7_MASK 0x00000080\n#define AVR32_FLASHC_FGPFRLO_LOCK7_OFFSET 7\n#define AVR32_FLASHC_FGPFRLO_LOCK7_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK8 8\n#define AVR32_FLASHC_FGPFRLO_LOCK8_MASK 0x00000100\n#define AVR32_FLASHC_FGPFRLO_LOCK8_OFFSET 8\n#define AVR32_FLASHC_FGPFRLO_LOCK8_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_LOCK9 9\n#define AVR32_FLASHC_FGPFRLO_LOCK9_MASK 0x00000200\n#define AVR32_FLASHC_FGPFRLO_LOCK9_OFFSET 9\n#define AVR32_FLASHC_FGPFRLO_LOCK9_SIZE 1\n#define AVR32_FLASHC_FRDY 0\n#define AVR32_FLASHC_FRDY_MASK 0x00000001\n#define AVR32_FLASHC_FRDY_OFFSET 0\n#define AVR32_FLASHC_FRDY_SIZE 1\n#define AVR32_FLASHC_FSR 0x00000008\n#define AVR32_FLASHC_FSR_FRDY 0\n#define AVR32_FLASHC_FSR_FRDY_MASK 0x00000001\n#define AVR32_FLASHC_FSR_FRDY_OFFSET 0\n#define AVR32_FLASHC_FSR_FRDY_SIZE 1\n#define AVR32_FLASHC_FSR_FSZ 13\n#define AVR32_FLASHC_FSR_FSZ_1024 0x00000007\n#define AVR32_FLASHC_FSR_FSZ_128 0x00000002\n#define AVR32_FLASHC_FSR_FSZ_256 0x00000003\n#define AVR32_FLASHC_FSR_FSZ_32 0x00000000\n#define AVR32_FLASHC_FSR_FSZ_384 0x00000004\n#define AVR32_FLASHC_FSR_FSZ_512 0x00000005\n#define AVR32_FLASHC_FSR_FSZ_64 0x00000001\n#define AVR32_FLASHC_FSR_FSZ_768 0x00000006\n#define AVR32_FLASHC_FSR_FSZ_MASK 0x0000e000\n#define AVR32_FLASHC_FSR_FSZ_OFFSET 13\n#define AVR32_FLASHC_FSR_FSZ_SIZE 3\n#define AVR32_FLASHC_FSR_LOCK0 16\n#define AVR32_FLASHC_FSR_LOCK0_MASK 0x00010000\n#define AVR32_FLASHC_FSR_LOCK0_OFFSET 16\n#define AVR32_FLASHC_FSR_LOCK0_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK1 17\n#define AVR32_FLASHC_FSR_LOCK10 26\n#define AVR32_FLASHC_FSR_LOCK10_MASK 0x04000000\n#define AVR32_FLASHC_FSR_LOCK10_OFFSET 26\n#define AVR32_FLASHC_FSR_LOCK10_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK11 27\n#define AVR32_FLASHC_FSR_LOCK11_MASK 0x08000000\n#define AVR32_FLASHC_FSR_LOCK11_OFFSET 27\n#define AVR32_FLASHC_FSR_LOCK11_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK12 28\n#define AVR32_FLASHC_FSR_LOCK12_MASK 0x10000000\n#define AVR32_FLASHC_FSR_LOCK12_OFFSET 28\n#define AVR32_FLASHC_FSR_LOCK12_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK13 29\n#define AVR32_FLASHC_FSR_LOCK13_MASK 0x20000000\n#define AVR32_FLASHC_FSR_LOCK13_OFFSET 29\n#define AVR32_FLASHC_FSR_LOCK13_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK14 30\n#define AVR32_FLASHC_FSR_LOCK14_MASK 0x40000000\n#define AVR32_FLASHC_FSR_LOCK14_OFFSET 30\n#define AVR32_FLASHC_FSR_LOCK14_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK15 31\n#define AVR32_FLASHC_FSR_LOCK15_MASK 0x80000000\n#define AVR32_FLASHC_FSR_LOCK15_OFFSET 31\n#define AVR32_FLASHC_FSR_LOCK15_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK1_MASK 0x00020000\n#define AVR32_FLASHC_FSR_LOCK1_OFFSET 17\n#define AVR32_FLASHC_FSR_LOCK1_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK2 18\n#define AVR32_FLASHC_FSR_LOCK2_MASK 0x00040000\n#define AVR32_FLASHC_FSR_LOCK2_OFFSET 18\n#define AVR32_FLASHC_FSR_LOCK2_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK3 19\n#define AVR32_FLASHC_FSR_LOCK3_MASK 0x00080000\n#define AVR32_FLASHC_FSR_LOCK3_OFFSET 19\n#define AVR32_FLASHC_FSR_LOCK3_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK4 20\n#define AVR32_FLASHC_FSR_LOCK4_MASK 0x00100000\n#define AVR32_FLASHC_FSR_LOCK4_OFFSET 20\n#define AVR32_FLASHC_FSR_LOCK4_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK5 21\n#define AVR32_FLASHC_FSR_LOCK5_MASK 0x00200000\n#define AVR32_FLASHC_FSR_LOCK5_OFFSET 21\n#define AVR32_FLASHC_FSR_LOCK5_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK6 22\n#define AVR32_FLASHC_FSR_LOCK6_MASK 0x00400000\n#define AVR32_FLASHC_FSR_LOCK6_OFFSET 22\n#define AVR32_FLASHC_FSR_LOCK6_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK7 23\n#define AVR32_FLASHC_FSR_LOCK7_MASK 0x00800000\n#define AVR32_FLASHC_FSR_LOCK7_OFFSET 23\n#define AVR32_FLASHC_FSR_LOCK7_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK8 24\n#define AVR32_FLASHC_FSR_LOCK8_MASK 0x01000000\n#define AVR32_FLASHC_FSR_LOCK8_OFFSET 24\n#define AVR32_FLASHC_FSR_LOCK8_SIZE 1\n#define AVR32_FLASHC_FSR_LOCK9 25\n#define AVR32_FLASHC_FSR_LOCK9_MASK 0x02000000\n#define AVR32_FLASHC_FSR_LOCK9_OFFSET 25\n#define AVR32_FLASHC_FSR_LOCK9_SIZE 1\n#define AVR32_FLASHC_FSR_LOCKE 2\n#define AVR32_FLASHC_FSR_LOCKE_MASK 0x00000004\n#define AVR32_FLASHC_FSR_LOCKE_OFFSET 2\n#define AVR32_FLASHC_FSR_LOCKE_SIZE 1\n#define AVR32_FLASHC_FSR_PROGE 3\n#define AVR32_FLASHC_FSR_PROGE_MASK 0x00000008\n#define AVR32_FLASHC_FSR_PROGE_OFFSET 3\n#define AVR32_FLASHC_FSR_PROGE_SIZE 1\n#define AVR32_FLASHC_FSR_QPRR 5\n#define AVR32_FLASHC_FSR_QPRR_MASK 0x00000020\n#define AVR32_FLASHC_FSR_QPRR_OFFSET 5\n#define AVR32_FLASHC_FSR_QPRR_SIZE 1\n#define AVR32_FLASHC_FSR_SECURITY 4\n#define AVR32_FLASHC_FSR_SECURITY_MASK 0x00000010\n#define AVR32_FLASHC_FSR_SECURITY_OFFSET 4\n#define AVR32_FLASHC_FSR_SECURITY_SIZE 1\n#define AVR32_FLASHC_FSZ 13\n#define AVR32_FLASHC_FSZ_1024 0x00000007\n#define AVR32_FLASHC_FSZ_128 0x00000002\n#define AVR32_FLASHC_FSZ_256 0x00000003\n#define AVR32_FLASHC_FSZ_32 0x00000000\n#define AVR32_FLASHC_FSZ_384 0x00000004\n#define AVR32_FLASHC_FSZ_512 0x00000005\n#define AVR32_FLASHC_FSZ_64 0x00000001\n#define AVR32_FLASHC_FSZ_768 0x00000006\n#define AVR32_FLASHC_FSZ_MASK 0x0000e000\n#define AVR32_FLASHC_FSZ_OFFSET 13\n#define AVR32_FLASHC_FSZ_SIZE 3\n#define AVR32_FLASHC_FWS 6\n#define AVR32_FLASHC_FWS_MASK 0x00000040\n#define AVR32_FLASHC_FWS_OFFSET 6\n#define AVR32_FLASHC_FWS_SIZE 1\n#define AVR32_FLASHC_GPF20 20\n#define AVR32_FLASHC_GPF20_MASK 0x00100000\n#define AVR32_FLASHC_GPF20_OFFSET 20\n#define AVR32_FLASHC_GPF20_SIZE 1\n#define AVR32_FLASHC_GPF21 21\n#define AVR32_FLASHC_GPF21_MASK 0x00200000\n#define AVR32_FLASHC_GPF21_OFFSET 21\n#define AVR32_FLASHC_GPF21_SIZE 1\n#define AVR32_FLASHC_GPF22 22\n#define AVR32_FLASHC_GPF22_MASK 0x00400000\n#define AVR32_FLASHC_GPF22_OFFSET 22\n#define AVR32_FLASHC_GPF22_SIZE 1\n#define AVR32_FLASHC_GPF23 23\n#define AVR32_FLASHC_GPF23_MASK 0x00800000\n#define AVR32_FLASHC_GPF23_OFFSET 23\n#define AVR32_FLASHC_GPF23_SIZE 1\n#define AVR32_FLASHC_GPF24 24\n#define AVR32_FLASHC_GPF24_MASK 0x01000000\n#define AVR32_FLASHC_GPF24_OFFSET 24\n#define AVR32_FLASHC_GPF24_SIZE 1\n#define AVR32_FLASHC_GPF25 25\n#define AVR32_FLASHC_GPF25_MASK 0x02000000\n#define AVR32_FLASHC_GPF25_OFFSET 25\n#define AVR32_FLASHC_GPF25_SIZE 1\n#define AVR32_FLASHC_GPF26 26\n#define AVR32_FLASHC_GPF26_MASK 0x04000000\n#define AVR32_FLASHC_GPF26_OFFSET 26\n#define AVR32_FLASHC_GPF26_SIZE 1\n#define AVR32_FLASHC_GPF27 27\n#define AVR32_FLASHC_GPF27_MASK 0x08000000\n#define AVR32_FLASHC_GPF27_OFFSET 27\n#define AVR32_FLASHC_GPF27_SIZE 1\n#define AVR32_FLASHC_GPF28 28\n#define AVR32_FLASHC_GPF28_MASK 0x10000000\n#define AVR32_FLASHC_GPF28_OFFSET 28\n#define AVR32_FLASHC_GPF28_SIZE 1\n#define AVR32_FLASHC_GPF29 29\n#define AVR32_FLASHC_GPF29_MASK 0x20000000\n#define AVR32_FLASHC_GPF29_OFFSET 29\n#define AVR32_FLASHC_GPF29_SIZE 1\n#define AVR32_FLASHC_GPF30 30\n#define AVR32_FLASHC_GPF30_MASK 0x40000000\n#define AVR32_FLASHC_GPF30_OFFSET 30\n#define AVR32_FLASHC_GPF30_SIZE 1\n#define AVR32_FLASHC_GPF31 31\n#define AVR32_FLASHC_GPF31_MASK 0x80000000\n#define AVR32_FLASHC_GPF31_OFFSET 31\n#define AVR32_FLASHC_GPF31_SIZE 1\n#define AVR32_FLASHC_GPF32 0\n#define AVR32_FLASHC_GPF32_MASK 0x00000001\n#define AVR32_FLASHC_GPF32_OFFSET 0\n#define AVR32_FLASHC_GPF32_SIZE 1\n#define AVR32_FLASHC_GPF33 1\n#define AVR32_FLASHC_GPF33_MASK 0x00000002\n#define AVR32_FLASHC_GPF33_OFFSET 1\n#define AVR32_FLASHC_GPF33_SIZE 1\n#define AVR32_FLASHC_GPF34 2\n#define AVR32_FLASHC_GPF34_MASK 0x00000004\n#define AVR32_FLASHC_GPF34_OFFSET 2\n#define AVR32_FLASHC_GPF34_SIZE 1\n#define AVR32_FLASHC_GPF35 3\n#define AVR32_FLASHC_GPF35_MASK 0x00000008\n#define AVR32_FLASHC_GPF35_OFFSET 3\n#define AVR32_FLASHC_GPF35_SIZE 1\n#define AVR32_FLASHC_GPF36 4\n#define AVR32_FLASHC_GPF36_MASK 0x00000010\n#define AVR32_FLASHC_GPF36_OFFSET 4\n#define AVR32_FLASHC_GPF36_SIZE 1\n#define AVR32_FLASHC_GPF37 5\n#define AVR32_FLASHC_GPF37_MASK 0x00000020\n#define AVR32_FLASHC_GPF37_OFFSET 5\n#define AVR32_FLASHC_GPF37_SIZE 1\n#define AVR32_FLASHC_GPF38 6\n#define AVR32_FLASHC_GPF38_MASK 0x00000040\n#define AVR32_FLASHC_GPF38_OFFSET 6\n#define AVR32_FLASHC_GPF38_SIZE 1\n#define AVR32_FLASHC_GPF39 7\n#define AVR32_FLASHC_GPF39_MASK 0x00000080\n#define AVR32_FLASHC_GPF39_OFFSET 7\n#define AVR32_FLASHC_GPF39_SIZE 1\n#define AVR32_FLASHC_GPF40 8\n#define AVR32_FLASHC_GPF40_MASK 0x00000100\n#define AVR32_FLASHC_GPF40_OFFSET 8\n#define AVR32_FLASHC_GPF40_SIZE 1\n#define AVR32_FLASHC_GPF41 9\n#define AVR32_FLASHC_GPF41_MASK 0x00000200\n#define AVR32_FLASHC_GPF41_OFFSET 9\n#define AVR32_FLASHC_GPF41_SIZE 1\n#define AVR32_FLASHC_GPF42 10\n#define AVR32_FLASHC_GPF42_MASK 0x00000400\n#define AVR32_FLASHC_GPF42_OFFSET 10\n#define AVR32_FLASHC_GPF42_SIZE 1\n#define AVR32_FLASHC_GPF43 11\n#define AVR32_FLASHC_GPF43_MASK 0x00000800\n#define AVR32_FLASHC_GPF43_OFFSET 11\n#define AVR32_FLASHC_GPF43_SIZE 1\n#define AVR32_FLASHC_GPF44 12\n#define AVR32_FLASHC_GPF44_MASK 0x00001000\n#define AVR32_FLASHC_GPF44_OFFSET 12\n#define AVR32_FLASHC_GPF44_SIZE 1\n#define AVR32_FLASHC_GPF45 13\n#define AVR32_FLASHC_GPF45_MASK 0x00002000\n#define AVR32_FLASHC_GPF45_OFFSET 13\n#define AVR32_FLASHC_GPF45_SIZE 1\n#define AVR32_FLASHC_GPF46 14\n#define AVR32_FLASHC_GPF46_MASK 0x00004000\n#define AVR32_FLASHC_GPF46_OFFSET 14\n#define AVR32_FLASHC_GPF46_SIZE 1\n#define AVR32_FLASHC_GPF47 15\n#define AVR32_FLASHC_GPF47_MASK 0x00008000\n#define AVR32_FLASHC_GPF47_OFFSET 15\n#define AVR32_FLASHC_GPF47_SIZE 1\n#define AVR32_FLASHC_GPF48 16\n#define AVR32_FLASHC_GPF48_MASK 0x00010000\n#define AVR32_FLASHC_GPF48_OFFSET 16\n#define AVR32_FLASHC_GPF48_SIZE 1\n#define AVR32_FLASHC_GPF49 17\n#define AVR32_FLASHC_GPF49_MASK 0x00020000\n#define AVR32_FLASHC_GPF49_OFFSET 17\n#define AVR32_FLASHC_GPF49_SIZE 1\n#define AVR32_FLASHC_GPF50 18\n#define AVR32_FLASHC_GPF50_MASK 0x00040000\n#define AVR32_FLASHC_GPF50_OFFSET 18\n#define AVR32_FLASHC_GPF50_SIZE 1\n#define AVR32_FLASHC_GPF51 19\n#define AVR32_FLASHC_GPF51_MASK 0x00080000\n#define AVR32_FLASHC_GPF51_OFFSET 19\n#define AVR32_FLASHC_GPF51_SIZE 1\n#define AVR32_FLASHC_GPF52 20\n#define AVR32_FLASHC_GPF52_MASK 0x00100000\n#define AVR32_FLASHC_GPF52_OFFSET 20\n#define AVR32_FLASHC_GPF52_SIZE 1\n#define AVR32_FLASHC_GPF53 21\n#define AVR32_FLASHC_GPF53_MASK 0x00200000\n#define AVR32_FLASHC_GPF53_OFFSET 21\n#define AVR32_FLASHC_GPF53_SIZE 1\n#define AVR32_FLASHC_GPF54 22\n#define AVR32_FLASHC_GPF54_MASK 0x00400000\n#define AVR32_FLASHC_GPF54_OFFSET 22\n#define AVR32_FLASHC_GPF54_SIZE 1\n#define AVR32_FLASHC_GPF55 23\n#define AVR32_FLASHC_GPF55_MASK 0x00800000\n#define AVR32_FLASHC_GPF55_OFFSET 23\n#define AVR32_FLASHC_GPF55_SIZE 1\n#define AVR32_FLASHC_GPF56 24\n#define AVR32_FLASHC_GPF56_MASK 0x01000000\n#define AVR32_FLASHC_GPF56_OFFSET 24\n#define AVR32_FLASHC_GPF56_SIZE 1\n#define AVR32_FLASHC_GPF57 25\n#define AVR32_FLASHC_GPF57_MASK 0x02000000\n#define AVR32_FLASHC_GPF57_OFFSET 25\n#define AVR32_FLASHC_GPF57_SIZE 1\n#define AVR32_FLASHC_GPF58 26\n#define AVR32_FLASHC_GPF58_MASK 0x04000000\n#define AVR32_FLASHC_GPF58_OFFSET 26\n#define AVR32_FLASHC_GPF58_SIZE 1\n#define AVR32_FLASHC_GPF59 27\n#define AVR32_FLASHC_GPF59_MASK 0x08000000\n#define AVR32_FLASHC_GPF59_OFFSET 27\n#define AVR32_FLASHC_GPF59_SIZE 1\n#define AVR32_FLASHC_GPF60 28\n#define AVR32_FLASHC_GPF60_MASK 0x10000000\n#define AVR32_FLASHC_GPF60_OFFSET 28\n#define AVR32_FLASHC_GPF60_SIZE 1\n#define AVR32_FLASHC_GPF61 29\n#define AVR32_FLASHC_GPF61_MASK 0x20000000\n#define AVR32_FLASHC_GPF61_OFFSET 29\n#define AVR32_FLASHC_GPF61_SIZE 1\n#define AVR32_FLASHC_GPF62 30\n#define AVR32_FLASHC_GPF62_MASK 0x40000000\n#define AVR32_FLASHC_GPF62_OFFSET 30\n#define AVR32_FLASHC_GPF62_SIZE 1\n#define AVR32_FLASHC_GPF63 31\n#define AVR32_FLASHC_GPF63_MASK 0x80000000\n#define AVR32_FLASHC_GPF63_OFFSET 31\n#define AVR32_FLASHC_GPF63_SIZE 1\n#define AVR32_FLASHC_KEY_KEY 0x000000a5\n#define AVR32_FLASHC_KEY_MASK 0xff000000\n#define AVR32_FLASHC_KEY_OFFSET 24\n#define AVR32_FLASHC_KEY_SIZE 8\n#define AVR32_FLASHC_LOCK0_SIZE 1\n#define AVR32_FLASHC_LOCK10_SIZE 1\n#define AVR32_FLASHC_LOCK11_SIZE 1\n#define AVR32_FLASHC_LOCK12_SIZE 1\n#define AVR32_FLASHC_LOCK13_SIZE 1\n#define AVR32_FLASHC_LOCK14_SIZE 1\n#define AVR32_FLASHC_LOCK15_SIZE 1\n#define AVR32_FLASHC_LOCK1_SIZE 1\n#define AVR32_FLASHC_LOCK2_SIZE 1\n#define AVR32_FLASHC_LOCK3_SIZE 1\n#define AVR32_FLASHC_LOCK4_SIZE 1\n#define AVR32_FLASHC_LOCK5_SIZE 1\n#define AVR32_FLASHC_LOCK6_SIZE 1\n#define AVR32_FLASHC_LOCK7_SIZE 1\n#define AVR32_FLASHC_LOCK8_SIZE 1\n#define AVR32_FLASHC_LOCK9_SIZE 1\n#define AVR32_FLASHC_LOCKE 2\n#define AVR32_FLASHC_LOCKE_MASK 0x00000004\n#define AVR32_FLASHC_LOCKE_OFFSET 2\n#define AVR32_FLASHC_LOCKE_SIZE 1\n#define AVR32_FLASHC_LP 0x00000004\n#define AVR32_FLASHC_NOP 0x00000000\n#define AVR32_FLASHC_PAGEN 8\n#define AVR32_FLASHC_PAGEN_MASK 0x00ffff00\n#define AVR32_FLASHC_PAGEN_OFFSET 8\n#define AVR32_FLASHC_PAGEN_SIZE 16\n#define AVR32_FLASHC_PGPFB 0x0000000a\n#define AVR32_FLASHC_PROGE 3\n#define AVR32_FLASHC_PROGE_MASK 0x00000008\n#define AVR32_FLASHC_PROGE_OFFSET 3\n#define AVR32_FLASHC_PROGE_SIZE 1\n#define AVR32_FLASHC_QPR 0x0000000c\n#define AVR32_FLASHC_QPRR 5\n#define AVR32_FLASHC_QPRR_MASK 0x00000020\n#define AVR32_FLASHC_QPRR_OFFSET 5\n#define AVR32_FLASHC_QPRR_SIZE 1\n#define AVR32_FLASHC_QPRUP 0x0000000f\n#define AVR32_FLASHC_SECURITY 4\n#define AVR32_FLASHC_SECURITY_MASK 0x00000010\n#define AVR32_FLASHC_SECURITY_OFFSET 4\n#define AVR32_FLASHC_SECURITY_SIZE 1\n#define AVR32_FLASHC_SSB 0x00000009\n#define AVR32_FLASHC_UP 0x00000005\n#define AVR32_FLASHC_WGPB 0x00000007\n#define AVR32_FLASHC_WP 0x00000001\n#define AVR32_FLASHC_WUP 0x0000000d\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_flashc_fcr_t {\n unsigned int :25;\n unsigned int fws : 1;\n unsigned int : 2;\n unsigned int proge : 1;\n unsigned int locke : 1;\n unsigned int : 1;\n unsigned int frdy : 1;\n} avr32_flashc_fcr_t;\n\n\n\ntypedef struct avr32_flashc_fcmd_t {\n unsigned int key : 8;\n unsigned int pagen :16;\n unsigned int : 2;\n unsigned int cmd : 6;\n} avr32_flashc_fcmd_t;\n\n\n\ntypedef struct avr32_flashc_fsr_t {\n unsigned int lock15 : 1;\n unsigned int lock14 : 1;\n unsigned int lock13 : 1;\n unsigned int lock12 : 1;\n unsigned int lock11 : 1;\n unsigned int lock10 : 1;\n unsigned int lock9 : 1;\n unsigned int lock8 : 1;\n unsigned int lock7 : 1;\n unsigned int lock6 : 1;\n unsigned int lock5 : 1;\n unsigned int lock4 : 1;\n unsigned int lock3 : 1;\n unsigned int lock2 : 1;\n unsigned int lock1 : 1;\n unsigned int lock0 : 1;\n unsigned int fsz : 3;\n unsigned int : 7;\n unsigned int qprr : 1;\n unsigned int security : 1;\n unsigned int proge : 1;\n unsigned int locke : 1;\n unsigned int : 1;\n unsigned int frdy : 1;\n} avr32_flashc_fsr_t;\n\n\n\ntypedef struct avr32_flashc_fgpfrhi_t {\n unsigned int gpf63 : 1;\n unsigned int gpf62 : 1;\n unsigned int gpf61 : 1;\n unsigned int gpf60 : 1;\n unsigned int gpf59 : 1;\n unsigned int gpf58 : 1;\n unsigned int gpf57 : 1;\n unsigned int gpf56 : 1;\n unsigned int gpf55 : 1;\n unsigned int gpf54 : 1;\n unsigned int gpf53 : 1;\n unsigned int gpf52 : 1;\n unsigned int gpf51 : 1;\n unsigned int gpf50 : 1;\n unsigned int gpf49 : 1;\n unsigned int gpf48 : 1;\n unsigned int gpf47 : 1;\n unsigned int gpf46 : 1;\n unsigned int gpf45 : 1;\n unsigned int gpf44 : 1;\n unsigned int gpf43 : 1;\n unsigned int gpf42 : 1;\n unsigned int gpf41 : 1;\n unsigned int gpf40 : 1;\n unsigned int gpf39 : 1;\n unsigned int gpf38 : 1;\n unsigned int gpf37 : 1;\n unsigned int gpf36 : 1;\n unsigned int gpf35 : 1;\n unsigned int gpf34 : 1;\n unsigned int gpf33 : 1;\n unsigned int gpf32 : 1;\n} avr32_flashc_fgpfrhi_t;\n\n\n\ntypedef struct avr32_flashc_fgpfrlo_t {\n unsigned int gpf31 : 1;\n unsigned int gpf30 : 1;\n unsigned int gpf29 : 1;\n unsigned int gpf28 : 1;\n unsigned int gpf27 : 1;\n unsigned int gpf26 : 1;\n unsigned int gpf25 : 1;\n unsigned int gpf24 : 1;\n unsigned int gpf23 : 1;\n unsigned int gpf22 : 1;\n unsigned int gpf21 : 1;\n unsigned int gpf20 : 1;\n unsigned int bootprot : 3;\n unsigned int epfl : 1;\n unsigned int lock15 : 1;\n unsigned int lock14 : 1;\n unsigned int lock13 : 1;\n unsigned int lock12 : 1;\n unsigned int lock11 : 1;\n unsigned int lock10 : 1;\n unsigned int lock9 : 1;\n unsigned int lock8 : 1;\n unsigned int lock7 : 1;\n unsigned int lock6 : 1;\n unsigned int lock5 : 1;\n unsigned int lock4 : 1;\n unsigned int lock3 : 1;\n unsigned int lock2 : 1;\n unsigned int lock1 : 1;\n unsigned int lock0 : 1;\n} avr32_flashc_fgpfrlo_t;\n\n\n\ntypedef struct avr32_flashc_t {\n union {\n unsigned long fcr ;//0x0000\n avr32_flashc_fcr_t FCR ;\n };\n union {\n unsigned long fcmd ;//0x0004\n avr32_flashc_fcmd_t FCMD ;\n };\n union {\n unsigned long fsr ;//0x0008\n avr32_flashc_fsr_t FSR ;\n };\n union {\n const unsigned long fgpfrhi ;//0x000c\n const avr32_flashc_fgpfrhi_t FGPFRHI ;\n };\n union {\n const unsigned long fgpfrlo ;//0x0010\n const avr32_flashc_fgpfrlo_t FGPFRLO ;\n };\n} avr32_flashc_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n/*#ifdef AVR32_FLASHC_200_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/freqm_230.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3000\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_FREQM_230_H_INCLUDED\n#define AVR32_FREQM_230_H_INCLUDED\n\n#define AVR32_FREQM_H_VERSION 230\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_FREQM_\n - Bitfield mask: AVR32_FREQM__\n - Bitfield offset: AVR32_FREQM___OFFSET\n - Bitfield size: AVR32_FREQM___SIZE\n - Bitfield values: AVR32_FREQM___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_FREQM_\n - Bitfield offset: AVR32_FREQM__OFFSET\n - Bitfield size: AVR32_FREQM__SIZE\n - Bitfield values: AVR32_FREQM__\n - Bitfield values: AVR32_FREQM_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_FREQM_BUSY 0\n#define AVR32_FREQM_BUSY_MASK 0x00000001\n#define AVR32_FREQM_BUSY_OFFSET 0\n#define AVR32_FREQM_BUSY_SIZE 1\n#define AVR32_FREQM_CLKSEL 16\n#define AVR32_FREQM_CLKSEL_CPU 0x00000000\n#define AVR32_FREQM_CLKSEL_CRIPLEL 0x0000000a\n#define AVR32_FREQM_CLKSEL_GENCLK0 0x0000000b\n#define AVR32_FREQM_CLKSEL_GENCLK1 0x0000000c\n#define AVR32_FREQM_CLKSEL_GENCLK2 0x0000000d\n#define AVR32_FREQM_CLKSEL_GENCLK3 0x0000000e\n#define AVR32_FREQM_CLKSEL_GENCLK4 0x0000000f\n#define AVR32_FREQM_CLKSEL_GENCLK5 0x00000010\n#define AVR32_FREQM_CLKSEL_HSB 0x00000001\n#define AVR32_FREQM_CLKSEL_MASK 0x001f0000\n#define AVR32_FREQM_CLKSEL_OFFSET 16\n#define AVR32_FREQM_CLKSEL_OSC0 0x00000004\n#define AVR32_FREQM_CLKSEL_OSC1 0x00000005\n#define AVR32_FREQM_CLKSEL_OSC32 0x00000006\n#define AVR32_FREQM_CLKSEL_PBA 0x00000002\n#define AVR32_FREQM_CLKSEL_PBB 0x00000003\n#define AVR32_FREQM_CLKSEL_PLL0 0x00000008\n#define AVR32_FREQM_CLKSEL_PLL1 0x00000009\n#define AVR32_FREQM_CLKSEL_RCOSC 0x00000007\n#define AVR32_FREQM_CLKSEL_SIZE 5\n#define AVR32_FREQM_CPU 0x00000000\n#define AVR32_FREQM_CRIPLEL 0x0000000a\n#define AVR32_FREQM_CTRL 0x00000000\n#define AVR32_FREQM_CTRL_START 0\n#define AVR32_FREQM_CTRL_START_MASK 0x00000001\n#define AVR32_FREQM_CTRL_START_OFFSET 0\n#define AVR32_FREQM_CTRL_START_SIZE 1\n#define AVR32_FREQM_DONE 0\n#define AVR32_FREQM_DONE_MASK 0x00000001\n#define AVR32_FREQM_DONE_OFFSET 0\n#define AVR32_FREQM_DONE_SIZE 1\n#define AVR32_FREQM_GENCLK0 0x0000000b\n#define AVR32_FREQM_GENCLK1 0x0000000c\n#define AVR32_FREQM_GENCLK2 0x0000000d\n#define AVR32_FREQM_GENCLK3 0x0000000e\n#define AVR32_FREQM_GENCLK4 0x0000000f\n#define AVR32_FREQM_GENCLK5 0x00000010\n#define AVR32_FREQM_HSB 0x00000001\n#define AVR32_FREQM_ICR 0x00000020\n#define AVR32_FREQM_ICR_DONE 0\n#define AVR32_FREQM_ICR_DONE_MASK 0x00000001\n#define AVR32_FREQM_ICR_DONE_OFFSET 0\n#define AVR32_FREQM_ICR_DONE_SIZE 1\n#define AVR32_FREQM_IDR 0x00000014\n#define AVR32_FREQM_IDR_DONE 0\n#define AVR32_FREQM_IDR_DONE_MASK 0x00000001\n#define AVR32_FREQM_IDR_DONE_OFFSET 0\n#define AVR32_FREQM_IDR_DONE_SIZE 1\n#define AVR32_FREQM_IER 0x00000010\n#define AVR32_FREQM_IER_DONE 0\n#define AVR32_FREQM_IER_DONE_MASK 0x00000001\n#define AVR32_FREQM_IER_DONE_OFFSET 0\n#define AVR32_FREQM_IER_DONE_SIZE 1\n#define AVR32_FREQM_IMR 0x00000018\n#define AVR32_FREQM_IMR_DONE 0\n#define AVR32_FREQM_IMR_DONE_MASK 0x00000001\n#define AVR32_FREQM_IMR_DONE_OFFSET 0\n#define AVR32_FREQM_IMR_DONE_SIZE 1\n#define AVR32_FREQM_ISR 0x0000001c\n#define AVR32_FREQM_ISR_DONE 0\n#define AVR32_FREQM_ISR_DONE_MASK 0x00000001\n#define AVR32_FREQM_ISR_DONE_OFFSET 0\n#define AVR32_FREQM_ISR_DONE_SIZE 1\n#define AVR32_FREQM_MODE 0x00000004\n#define AVR32_FREQM_MODE_CLKSEL 16\n#define AVR32_FREQM_MODE_CLKSEL_CPU 0x00000000\n#define AVR32_FREQM_MODE_CLKSEL_CRIPLEL 0x0000000a\n#define AVR32_FREQM_MODE_CLKSEL_GENCLK0 0x0000000b\n#define AVR32_FREQM_MODE_CLKSEL_GENCLK1 0x0000000c\n#define AVR32_FREQM_MODE_CLKSEL_GENCLK2 0x0000000d\n#define AVR32_FREQM_MODE_CLKSEL_GENCLK3 0x0000000e\n#define AVR32_FREQM_MODE_CLKSEL_GENCLK4 0x0000000f\n#define AVR32_FREQM_MODE_CLKSEL_GENCLK5 0x00000010\n#define AVR32_FREQM_MODE_CLKSEL_HSB 0x00000001\n#define AVR32_FREQM_MODE_CLKSEL_MASK 0x001f0000\n#define AVR32_FREQM_MODE_CLKSEL_OFFSET 16\n#define AVR32_FREQM_MODE_CLKSEL_OSC0 0x00000004\n#define AVR32_FREQM_MODE_CLKSEL_OSC1 0x00000005\n#define AVR32_FREQM_MODE_CLKSEL_OSC32 0x00000006\n#define AVR32_FREQM_MODE_CLKSEL_PBA 0x00000002\n#define AVR32_FREQM_MODE_CLKSEL_PBB 0x00000003\n#define AVR32_FREQM_MODE_CLKSEL_PLL0 0x00000008\n#define AVR32_FREQM_MODE_CLKSEL_PLL1 0x00000009\n#define AVR32_FREQM_MODE_CLKSEL_RCOSC 0x00000007\n#define AVR32_FREQM_MODE_CLKSEL_SIZE 5\n#define AVR32_FREQM_MODE_REFNUM 8\n#define AVR32_FREQM_MODE_REFNUM_MASK 0x0000ff00\n#define AVR32_FREQM_MODE_REFNUM_OFFSET 8\n#define AVR32_FREQM_MODE_REFNUM_SIZE 8\n#define AVR32_FREQM_MODE_REFSEL 0\n#define AVR32_FREQM_MODE_REFSEL_MASK 0x00000001\n#define AVR32_FREQM_MODE_REFSEL_OFFSET 0\n#define AVR32_FREQM_MODE_REFSEL_REF_OSC32 0x00000001\n#define AVR32_FREQM_MODE_REFSEL_REF_RCOSC 0x00000000\n#define AVR32_FREQM_MODE_REFSEL_SIZE 1\n#define AVR32_FREQM_OSC0 0x00000004\n#define AVR32_FREQM_OSC1 0x00000005\n#define AVR32_FREQM_OSC32 0x00000006\n#define AVR32_FREQM_PBA 0x00000002\n#define AVR32_FREQM_PBB 0x00000003\n#define AVR32_FREQM_PLL0 0x00000008\n#define AVR32_FREQM_PLL1 0x00000009\n#define AVR32_FREQM_RCOSC 0x00000007\n#define AVR32_FREQM_REFNUM 8\n#define AVR32_FREQM_REFNUM_MASK 0x0000ff00\n#define AVR32_FREQM_REFNUM_OFFSET 8\n#define AVR32_FREQM_REFNUM_SIZE 8\n#define AVR32_FREQM_REFSEL 0\n#define AVR32_FREQM_REFSEL_MASK 0x00000001\n#define AVR32_FREQM_REFSEL_OFFSET 0\n#define AVR32_FREQM_REFSEL_REF_OSC32 0x00000001\n#define AVR32_FREQM_REFSEL_REF_RCOSC 0x00000000\n#define AVR32_FREQM_REFSEL_SIZE 1\n#define AVR32_FREQM_REF_OSC32 0x00000001\n#define AVR32_FREQM_REF_RCOSC 0x00000000\n#define AVR32_FREQM_START 0\n#define AVR32_FREQM_START_MASK 0x00000001\n#define AVR32_FREQM_START_OFFSET 0\n#define AVR32_FREQM_START_SIZE 1\n#define AVR32_FREQM_STATUS 0x00000008\n#define AVR32_FREQM_STATUS_BUSY 0\n#define AVR32_FREQM_STATUS_BUSY_MASK 0x00000001\n#define AVR32_FREQM_STATUS_BUSY_OFFSET 0\n#define AVR32_FREQM_STATUS_BUSY_SIZE 1\n#define AVR32_FREQM_VALUE 0x0000000c\n#define AVR32_FREQM_VALUE_MASK 0x00ffffff\n#define AVR32_FREQM_VALUE_OFFSET 0\n#define AVR32_FREQM_VALUE_SIZE 24\n#define AVR32_FREQM_VALUE_VALUE 0\n#define AVR32_FREQM_VALUE_VALUE_MASK 0x00ffffff\n#define AVR32_FREQM_VALUE_VALUE_OFFSET 0\n#define AVR32_FREQM_VALUE_VALUE_SIZE 24\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_freqm_ctrl_t {\n unsigned int :31;\n unsigned int start : 1;\n} avr32_freqm_ctrl_t;\n\n\n\ntypedef struct avr32_freqm_mode_t {\n unsigned int :11;\n unsigned int clksel : 5;\n unsigned int refnum : 8;\n unsigned int : 7;\n unsigned int refsel : 1;\n} avr32_freqm_mode_t;\n\n\n\ntypedef struct avr32_freqm_status_t {\n unsigned int :31;\n unsigned int busy : 1;\n} avr32_freqm_status_t;\n\n\n\ntypedef struct avr32_freqm_value_t {\n unsigned int : 8;\n unsigned int value :24;\n} avr32_freqm_value_t;\n\n\n\ntypedef struct avr32_freqm_ier_t {\n unsigned int :31;\n unsigned int done : 1;\n} avr32_freqm_ier_t;\n\n\n\ntypedef struct avr32_freqm_idr_t {\n unsigned int :31;\n unsigned int done : 1;\n} avr32_freqm_idr_t;\n\n\n\ntypedef struct avr32_freqm_imr_t {\n unsigned int :31;\n unsigned int done : 1;\n} avr32_freqm_imr_t;\n\n\n\ntypedef struct avr32_freqm_isr_t {\n unsigned int :31;\n unsigned int done : 1;\n} avr32_freqm_isr_t;\n\n\n\ntypedef struct avr32_freqm_icr_t {\n unsigned int :31;\n unsigned int done : 1;\n} avr32_freqm_icr_t;\n\n\n\ntypedef struct avr32_freqm_t {\n union {\n unsigned long ctrl ;//0x0000\n avr32_freqm_ctrl_t CTRL ;\n };\n union {\n unsigned long mode ;//0x0004\n avr32_freqm_mode_t MODE ;\n };\n union {\n const unsigned long status ;//0x0008\n const avr32_freqm_status_t STATUS ;\n };\n union {\n unsigned long value ;//0x000c\n avr32_freqm_value_t VALUE ;\n };\n union {\n unsigned long ier ;//0x0010\n avr32_freqm_ier_t IER ;\n };\n union {\n unsigned long idr ;//0x0014\n avr32_freqm_idr_t IDR ;\n };\n union {\n const unsigned long imr ;//0x0018\n const avr32_freqm_imr_t IMR ;\n };\n union {\n const unsigned long isr ;//0x001c\n const avr32_freqm_isr_t ISR ;\n };\n union {\n unsigned long icr ;//0x0020\n avr32_freqm_icr_t ICR ;\n };\n} avr32_freqm_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n/*#ifdef AVR32_FREQM_230_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/gpio_110.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3A3128\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_GPIO_110_H_INCLUDED\n#define AVR32_GPIO_110_H_INCLUDED\n\n#define AVR32_GPIO_H_VERSION 110\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_GPIO_\n - Bitfield mask: AVR32_GPIO__\n - Bitfield offset: AVR32_GPIO___OFFSET\n - Bitfield size: AVR32_GPIO___SIZE\n - Bitfield values: AVR32_GPIO___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_GPIO_\n - Bitfield offset: AVR32_GPIO__OFFSET\n - Bitfield size: AVR32_GPIO__SIZE\n - Bitfield values: AVR32_GPIO__\n - Bitfield values: AVR32_GPIO_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_GPIO_GFER 0x000000c0\n#define AVR32_GPIO_GFERC 0x000000c8\n#define AVR32_GPIO_GFERS 0x000000c4\n#define AVR32_GPIO_GFERT 0x000000cc\n#define AVR32_GPIO_GPER 0x00000000\n#define AVR32_GPIO_GPERC 0x00000008\n#define AVR32_GPIO_GPERS 0x00000004\n#define AVR32_GPIO_GPERT 0x0000000c\n#define AVR32_GPIO_IER 0x00000090\n#define AVR32_GPIO_IERC 0x00000098\n#define AVR32_GPIO_IERS 0x00000094\n#define AVR32_GPIO_IERT 0x0000009c\n#define AVR32_GPIO_IFR 0x000000d0\n#define AVR32_GPIO_IFRC 0x000000d8\n#define AVR32_GPIO_IMR0 0x000000a0\n#define AVR32_GPIO_IMR0C 0x000000a8\n#define AVR32_GPIO_IMR0S 0x000000a4\n#define AVR32_GPIO_IMR0T 0x000000ac\n#define AVR32_GPIO_IMR1 0x000000b0\n#define AVR32_GPIO_IMR1C 0x000000b8\n#define AVR32_GPIO_IMR1S 0x000000b4\n#define AVR32_GPIO_IMR1T 0x000000bc\n#define AVR32_GPIO_LOCAL_ODER 0x00000040\n#define AVR32_GPIO_LOCAL_ODERC 0x00000048\n#define AVR32_GPIO_LOCAL_ODERS 0x00000044\n#define AVR32_GPIO_LOCAL_ODERT 0x0000004c\n#define AVR32_GPIO_LOCAL_OVR 0x00000050\n#define AVR32_GPIO_LOCAL_OVRC 0x00000058\n#define AVR32_GPIO_LOCAL_OVRS 0x00000054\n#define AVR32_GPIO_LOCAL_OVRT 0x0000005c\n#define AVR32_GPIO_LOCAL_PVR 0x00000060\n#define AVR32_GPIO_ODER 0x00000040\n#define AVR32_GPIO_ODERC 0x00000048\n#define AVR32_GPIO_ODERS 0x00000044\n#define AVR32_GPIO_ODERT 0x0000004c\n#define AVR32_GPIO_ODMER 0x00000080\n#define AVR32_GPIO_ODMERC 0x00000088\n#define AVR32_GPIO_ODMERS 0x00000084\n#define AVR32_GPIO_ODMERT 0x0000008c\n#define AVR32_GPIO_OVR 0x00000050\n#define AVR32_GPIO_OVRC 0x00000058\n#define AVR32_GPIO_OVRS 0x00000054\n#define AVR32_GPIO_OVRT 0x0000005c\n#define AVR32_GPIO_PMR0 0x00000010\n#define AVR32_GPIO_PMR0C 0x00000018\n#define AVR32_GPIO_PMR0S 0x00000014\n#define AVR32_GPIO_PMR0T 0x0000001c\n#define AVR32_GPIO_PMR1 0x00000020\n#define AVR32_GPIO_PMR1C 0x00000028\n#define AVR32_GPIO_PMR1S 0x00000024\n#define AVR32_GPIO_PMR1T 0x0000002c\n#define AVR32_GPIO_PUER 0x00000070\n#define AVR32_GPIO_PUERC 0x00000078\n#define AVR32_GPIO_PUERS 0x00000074\n#define AVR32_GPIO_PUERT 0x0000007c\n#define AVR32_GPIO_PVR 0x00000060\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\ntypedef struct avr32_gpio_local_port_t {\n unsigned int :32 ;//0x0000\n unsigned int :32 ;//0x0004\n unsigned int :32 ;//0x0008\n unsigned int :32 ;//0x000c\n unsigned int :32 ;//0x0010\n unsigned int :32 ;//0x0014\n unsigned int :32 ;//0x0018\n unsigned int :32 ;//0x001c\n unsigned int :32 ;//0x0020\n unsigned int :32 ;//0x0024\n unsigned int :32 ;//0x0028\n unsigned int :32 ;//0x002c\n unsigned int :32 ;//0x0030\n unsigned int :32 ;//0x0034\n unsigned int :32 ;//0x0038\n unsigned int :32 ;//0x003c\n unsigned long oder ;//0x0040\n unsigned long oders ;//0x0044\n unsigned long oderc ;//0x0048\n unsigned long odert ;//0x004c\n unsigned long ovr ;//0x0050\n unsigned long ovrs ;//0x0054\n unsigned long ovrc ;//0x0058\n unsigned long ovrt ;//0x005c\n const unsigned long pvr ;//0x0060\n unsigned int :32 ;//0x0064\n unsigned int :32 ;//0x0068\n unsigned int :32 ;//0x006c\n unsigned int :32 ;//0x0070\n unsigned int :32 ;//0x0074\n unsigned int :32 ;//0x0078\n unsigned int :32 ;//0x007c\n unsigned int :32 ;//0x0080\n unsigned int :32 ;//0x0084\n unsigned int :32 ;//0x0088\n unsigned int :32 ;//0x008c\n unsigned int :32 ;//0x0090\n unsigned int :32 ;//0x0094\n unsigned int :32 ;//0x0098\n unsigned int :32 ;//0x009c\n unsigned int :32 ;//0x00a0\n unsigned int :32 ;//0x00a4\n unsigned int :32 ;//0x00a8\n unsigned int :32 ;//0x00ac\n unsigned int :32 ;//0x00b0\n unsigned int :32 ;//0x00b4\n unsigned int :32 ;//0x00b8\n unsigned int :32 ;//0x00bc\n unsigned int :32 ;//0x00c0\n unsigned int :32 ;//0x00c4\n unsigned int :32 ;//0x00c8\n unsigned int :32 ;//0x00cc\n unsigned int :32 ;//0x00d0\n unsigned int :32 ;//0x00d4\n unsigned int :32 ;//0x00d8\n unsigned int :32 ;//0x00dc\n unsigned int :32 ;//0x00e0\n unsigned int :32 ;//0x00e4\n unsigned int :32 ;//0x00e8\n unsigned int :32 ;//0x00ec\n unsigned int :32 ;//0x00f0\n unsigned int :32 ;//0x00f4\n unsigned int :32 ;//0x00f8\n unsigned int :32 ;//0x00fc\n} avr32_gpio_local_port_t;\n\n\ntypedef struct avr32_gpio_local_t {\n avr32_gpio_local_port_t port[AVR32_GPIO_PORT_LENGTH];//0x0\n} avr32_gpio_local_t;\n\n\n\ntypedef struct avr32_gpio_port_t {\n unsigned long gper ;//0x0000\n unsigned long gpers ;//0x0004\n unsigned long gperc ;//0x0008\n unsigned long gpert ;//0x000c\n unsigned long pmr0 ;//0x0010\n unsigned long pmr0s ;//0x0014\n unsigned long pmr0c ;//0x0018\n unsigned long pmr0t ;//0x001c\n unsigned long pmr1 ;//0x0020\n unsigned long pmr1s ;//0x0024\n unsigned long pmr1c ;//0x0028\n unsigned long pmr1t ;//0x002c\n unsigned int :32 ;//0x0030\n unsigned int :32 ;//0x0034\n unsigned int :32 ;//0x0038\n unsigned int :32 ;//0x003c\n unsigned long oder ;//0x0040\n unsigned long oders ;//0x0044\n unsigned long oderc ;//0x0048\n unsigned long odert ;//0x004c\n unsigned long ovr ;//0x0050\n unsigned long ovrs ;//0x0054\n unsigned long ovrc ;//0x0058\n unsigned long ovrt ;//0x005c\n const unsigned long pvr ;//0x0060\n unsigned int :32 ;//0x0064\n unsigned int :32 ;//0x0068\n unsigned int :32 ;//0x006c\n unsigned long puer ;//0x0070\n unsigned long puers ;//0x0074\n unsigned long puerc ;//0x0078\n unsigned long puert ;//0x007c\n unsigned long odmer ;//0x0080\n unsigned long odmers ;//0x0084\n unsigned long odmerc ;//0x0088\n unsigned long odmert ;//0x008c\n unsigned long ier ;//0x0090\n unsigned long iers ;//0x0094\n unsigned long ierc ;//0x0098\n unsigned long iert ;//0x009c\n unsigned long imr0 ;//0x00a0\n unsigned long imr0s ;//0x00a4\n unsigned long imr0c ;//0x00a8\n unsigned long imr0t ;//0x00ac\n unsigned long imr1 ;//0x00b0\n unsigned long imr1s ;//0x00b4\n unsigned long imr1c ;//0x00b8\n unsigned long imr1t ;//0x00bc\n unsigned long gfer ;//0x00c0\n unsigned long gfers ;//0x00c4\n unsigned long gferc ;//0x00c8\n unsigned long gfert ;//0x00cc\n const unsigned long ifr ;//0x00d0\n unsigned int :32 ;//0x00d4\n unsigned long ifrc ;//0x00d8\n unsigned int :32 ;//0x00dc\n unsigned int :32 ;//0x00e0\n unsigned int :32 ;//0x00e4\n unsigned int :32 ;//0x00e8\n unsigned int :32 ;//0x00ec\n unsigned int :32 ;//0x00f0\n unsigned int :32 ;//0x00f4\n unsigned int :32 ;//0x00f8\n unsigned int :32 ;//0x00fc\n} avr32_gpio_port_t;\n\n\ntypedef struct avr32_gpio_t {\n avr32_gpio_port_t port[AVR32_GPIO_PORT_LENGTH];//0x0\n} avr32_gpio_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n/*#ifdef AVR32_GPIO_110_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/hmatrix_230.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : AP7200\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_HMATRIX_230_H_INCLUDED\n#define AVR32_HMATRIX_230_H_INCLUDED\n\n#define AVR32_HMATRIX_H_VERSION 230\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_HMATRIX_\n - Bitfield mask: AVR32_HMATRIX__\n - Bitfield offset: AVR32_HMATRIX___OFFSET\n - Bitfield size: AVR32_HMATRIX___SIZE\n - Bitfield values: AVR32_HMATRIX___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_HMATRIX_\n - Bitfield offset: AVR32_HMATRIX__OFFSET\n - Bitfield size: AVR32_HMATRIX__SIZE\n - Bitfield values: AVR32_HMATRIX__\n - Bitfield values: AVR32_HMATRIX_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_HMATRIX_ARBT 24\n#define AVR32_HMATRIX_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_ARBT_OFFSET 24\n#define AVR32_HMATRIX_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_ARBT_SIZE 1\n#define AVR32_HMATRIX_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_INFINITE 0x00000000\n#define AVR32_HMATRIX_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_M0PR 0\n#define AVR32_HMATRIX_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_M0PR_OFFSET 0\n#define AVR32_HMATRIX_M0PR_SIZE 4\n#define AVR32_HMATRIX_M10PR 8\n#define AVR32_HMATRIX_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_M10PR_OFFSET 8\n#define AVR32_HMATRIX_M10PR_SIZE 4\n#define AVR32_HMATRIX_M11PR 12\n#define AVR32_HMATRIX_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_M11PR_OFFSET 12\n#define AVR32_HMATRIX_M11PR_SIZE 4\n#define AVR32_HMATRIX_M12PR 16\n#define AVR32_HMATRIX_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_M12PR_OFFSET 16\n#define AVR32_HMATRIX_M12PR_SIZE 4\n#define AVR32_HMATRIX_M13PR 20\n#define AVR32_HMATRIX_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_M13PR_OFFSET 20\n#define AVR32_HMATRIX_M13PR_SIZE 4\n#define AVR32_HMATRIX_M14PR 24\n#define AVR32_HMATRIX_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_M14PR_OFFSET 24\n#define AVR32_HMATRIX_M14PR_SIZE 4\n#define AVR32_HMATRIX_M15PR 28\n#define AVR32_HMATRIX_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_M15PR_OFFSET 28\n#define AVR32_HMATRIX_M15PR_SIZE 4\n#define AVR32_HMATRIX_M1PR 4\n#define AVR32_HMATRIX_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_M1PR_OFFSET 4\n#define AVR32_HMATRIX_M1PR_SIZE 4\n#define AVR32_HMATRIX_M2PR 8\n#define AVR32_HMATRIX_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_M2PR_OFFSET 8\n#define AVR32_HMATRIX_M2PR_SIZE 4\n#define AVR32_HMATRIX_M3PR 12\n#define AVR32_HMATRIX_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_M3PR_OFFSET 12\n#define AVR32_HMATRIX_M3PR_SIZE 4\n#define AVR32_HMATRIX_M4PR 16\n#define AVR32_HMATRIX_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_M4PR_OFFSET 16\n#define AVR32_HMATRIX_M4PR_SIZE 4\n#define AVR32_HMATRIX_M5PR 20\n#define AVR32_HMATRIX_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_M5PR_OFFSET 20\n#define AVR32_HMATRIX_M5PR_SIZE 4\n#define AVR32_HMATRIX_M6PR 24\n#define AVR32_HMATRIX_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_M6PR_OFFSET 24\n#define AVR32_HMATRIX_M6PR_SIZE 4\n#define AVR32_HMATRIX_M7PR 28\n#define AVR32_HMATRIX_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_M7PR_OFFSET 28\n#define AVR32_HMATRIX_M7PR_SIZE 4\n#define AVR32_HMATRIX_M8PR 0\n#define AVR32_HMATRIX_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_M8PR_OFFSET 0\n#define AVR32_HMATRIX_M8PR_SIZE 4\n#define AVR32_HMATRIX_M9PR 4\n#define AVR32_HMATRIX_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_M9PR_OFFSET 4\n#define AVR32_HMATRIX_M9PR_SIZE 4\n#define AVR32_HMATRIX_MCFG0 0x00000000\n#define AVR32_HMATRIX_MCFG0_ULBT 0\n#define AVR32_HMATRIX_MCFG0_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG0_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG0_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG0_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG0_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG0_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG0_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG0_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG1 0x00000004\n#define AVR32_HMATRIX_MCFG10 0x00000028\n#define AVR32_HMATRIX_MCFG10_ULBT 0\n#define AVR32_HMATRIX_MCFG10_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG10_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG10_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG10_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG10_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG10_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG10_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG10_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG11 0x0000002c\n#define AVR32_HMATRIX_MCFG11_ULBT 0\n#define AVR32_HMATRIX_MCFG11_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG11_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG11_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG11_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG11_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG11_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG11_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG11_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG12 0x00000030\n#define AVR32_HMATRIX_MCFG12_ULBT 0\n#define AVR32_HMATRIX_MCFG12_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG12_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG12_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG12_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG12_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG12_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG12_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG12_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG13 0x00000034\n#define AVR32_HMATRIX_MCFG13_ULBT 0\n#define AVR32_HMATRIX_MCFG13_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG13_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG13_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG13_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG13_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG13_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG13_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG13_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG14 0x00000038\n#define AVR32_HMATRIX_MCFG14_ULBT 0\n#define AVR32_HMATRIX_MCFG14_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG14_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG14_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG14_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG14_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG14_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG14_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG14_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG15 0x0000003c\n#define AVR32_HMATRIX_MCFG15_ULBT 0\n#define AVR32_HMATRIX_MCFG15_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG15_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG15_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG15_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG15_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG15_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG15_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG15_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG1_ULBT 0\n#define AVR32_HMATRIX_MCFG1_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG1_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG1_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG1_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG1_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG1_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG1_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG1_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG2 0x00000008\n#define AVR32_HMATRIX_MCFG2_ULBT 0\n#define AVR32_HMATRIX_MCFG2_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG2_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG2_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG2_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG2_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG2_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG2_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG2_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG3 0x0000000c\n#define AVR32_HMATRIX_MCFG3_ULBT 0\n#define AVR32_HMATRIX_MCFG3_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG3_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG3_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG3_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG3_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG3_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG3_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG3_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG4 0x00000010\n#define AVR32_HMATRIX_MCFG4_ULBT 0\n#define AVR32_HMATRIX_MCFG4_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG4_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG4_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG4_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG4_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG4_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG4_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG4_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG5 0x00000014\n#define AVR32_HMATRIX_MCFG5_ULBT 0\n#define AVR32_HMATRIX_MCFG5_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG5_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG5_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG5_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG5_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG5_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG5_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG5_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG6 0x00000018\n#define AVR32_HMATRIX_MCFG6_ULBT 0\n#define AVR32_HMATRIX_MCFG6_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG6_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG6_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG6_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG6_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG6_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG6_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG6_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG7 0x0000001c\n#define AVR32_HMATRIX_MCFG7_ULBT 0\n#define AVR32_HMATRIX_MCFG7_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG7_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG7_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG7_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG7_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG7_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG7_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG7_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG8 0x00000020\n#define AVR32_HMATRIX_MCFG8_ULBT 0\n#define AVR32_HMATRIX_MCFG8_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG8_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG8_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG8_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG8_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG8_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG8_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG8_ULBT_SIZE 3\n#define AVR32_HMATRIX_MCFG9 0x00000024\n#define AVR32_HMATRIX_MCFG9_ULBT 0\n#define AVR32_HMATRIX_MCFG9_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_MCFG9_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_MCFG9_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_MCFG9_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_MCFG9_ULBT_OFFSET 0\n#define AVR32_HMATRIX_MCFG9_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_MCFG9_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_MCFG9_ULBT_SIZE 3\n#define AVR32_HMATRIX_MRCR 0x00000100\n#define AVR32_HMATRIX_MRCR_RCB0 0\n#define AVR32_HMATRIX_MRCR_RCB0_MASK 0x00000001\n#define AVR32_HMATRIX_MRCR_RCB0_OFFSET 0\n#define AVR32_HMATRIX_MRCR_RCB0_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB1 1\n#define AVR32_HMATRIX_MRCR_RCB10 10\n#define AVR32_HMATRIX_MRCR_RCB10_MASK 0x00000400\n#define AVR32_HMATRIX_MRCR_RCB10_OFFSET 10\n#define AVR32_HMATRIX_MRCR_RCB10_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB11 11\n#define AVR32_HMATRIX_MRCR_RCB11_MASK 0x00000800\n#define AVR32_HMATRIX_MRCR_RCB11_OFFSET 11\n#define AVR32_HMATRIX_MRCR_RCB11_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB12 12\n#define AVR32_HMATRIX_MRCR_RCB12_MASK 0x00001000\n#define AVR32_HMATRIX_MRCR_RCB12_OFFSET 12\n#define AVR32_HMATRIX_MRCR_RCB12_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB13 13\n#define AVR32_HMATRIX_MRCR_RCB13_MASK 0x00002000\n#define AVR32_HMATRIX_MRCR_RCB13_OFFSET 13\n#define AVR32_HMATRIX_MRCR_RCB13_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB14 14\n#define AVR32_HMATRIX_MRCR_RCB14_MASK 0x00004000\n#define AVR32_HMATRIX_MRCR_RCB14_OFFSET 14\n#define AVR32_HMATRIX_MRCR_RCB14_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB15 15\n#define AVR32_HMATRIX_MRCR_RCB15_MASK 0x00008000\n#define AVR32_HMATRIX_MRCR_RCB15_OFFSET 15\n#define AVR32_HMATRIX_MRCR_RCB15_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB1_MASK 0x00000002\n#define AVR32_HMATRIX_MRCR_RCB1_OFFSET 1\n#define AVR32_HMATRIX_MRCR_RCB1_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB2 2\n#define AVR32_HMATRIX_MRCR_RCB2_MASK 0x00000004\n#define AVR32_HMATRIX_MRCR_RCB2_OFFSET 2\n#define AVR32_HMATRIX_MRCR_RCB2_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB3 3\n#define AVR32_HMATRIX_MRCR_RCB3_MASK 0x00000008\n#define AVR32_HMATRIX_MRCR_RCB3_OFFSET 3\n#define AVR32_HMATRIX_MRCR_RCB3_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB4 4\n#define AVR32_HMATRIX_MRCR_RCB4_MASK 0x00000010\n#define AVR32_HMATRIX_MRCR_RCB4_OFFSET 4\n#define AVR32_HMATRIX_MRCR_RCB4_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB5 5\n#define AVR32_HMATRIX_MRCR_RCB5_MASK 0x00000020\n#define AVR32_HMATRIX_MRCR_RCB5_OFFSET 5\n#define AVR32_HMATRIX_MRCR_RCB5_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB6 6\n#define AVR32_HMATRIX_MRCR_RCB6_MASK 0x00000040\n#define AVR32_HMATRIX_MRCR_RCB6_OFFSET 6\n#define AVR32_HMATRIX_MRCR_RCB6_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB7 7\n#define AVR32_HMATRIX_MRCR_RCB7_MASK 0x00000080\n#define AVR32_HMATRIX_MRCR_RCB7_OFFSET 7\n#define AVR32_HMATRIX_MRCR_RCB7_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB8 8\n#define AVR32_HMATRIX_MRCR_RCB8_MASK 0x00000100\n#define AVR32_HMATRIX_MRCR_RCB8_OFFSET 8\n#define AVR32_HMATRIX_MRCR_RCB8_SIZE 1\n#define AVR32_HMATRIX_MRCR_RCB9 9\n#define AVR32_HMATRIX_MRCR_RCB9_MASK 0x00000200\n#define AVR32_HMATRIX_MRCR_RCB9_OFFSET 9\n#define AVR32_HMATRIX_MRCR_RCB9_SIZE 1\n#define AVR32_HMATRIX_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_PRAS0 0x00000080\n#define AVR32_HMATRIX_PRAS0_M0PR 0\n#define AVR32_HMATRIX_PRAS0_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS0_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS0_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS0_M1PR 4\n#define AVR32_HMATRIX_PRAS0_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS0_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS0_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS0_M2PR 8\n#define AVR32_HMATRIX_PRAS0_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS0_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS0_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS0_M3PR 12\n#define AVR32_HMATRIX_PRAS0_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS0_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS0_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS0_M4PR 16\n#define AVR32_HMATRIX_PRAS0_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS0_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS0_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS0_M5PR 20\n#define AVR32_HMATRIX_PRAS0_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS0_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS0_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS0_M6PR 24\n#define AVR32_HMATRIX_PRAS0_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS0_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS0_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS0_M7PR 28\n#define AVR32_HMATRIX_PRAS0_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS0_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS0_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS1 0x00000088\n#define AVR32_HMATRIX_PRAS10 0x000000d0\n#define AVR32_HMATRIX_PRAS10_M0PR 0\n#define AVR32_HMATRIX_PRAS10_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS10_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS10_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS10_M1PR 4\n#define AVR32_HMATRIX_PRAS10_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS10_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS10_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS10_M2PR 8\n#define AVR32_HMATRIX_PRAS10_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS10_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS10_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS10_M3PR 12\n#define AVR32_HMATRIX_PRAS10_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS10_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS10_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS10_M4PR 16\n#define AVR32_HMATRIX_PRAS10_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS10_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS10_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS10_M5PR 20\n#define AVR32_HMATRIX_PRAS10_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS10_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS10_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS10_M6PR 24\n#define AVR32_HMATRIX_PRAS10_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS10_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS10_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS10_M7PR 28\n#define AVR32_HMATRIX_PRAS10_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS10_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS10_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS11 0x000000d8\n#define AVR32_HMATRIX_PRAS11_M0PR 0\n#define AVR32_HMATRIX_PRAS11_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS11_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS11_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS11_M1PR 4\n#define AVR32_HMATRIX_PRAS11_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS11_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS11_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS11_M2PR 8\n#define AVR32_HMATRIX_PRAS11_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS11_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS11_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS11_M3PR 12\n#define AVR32_HMATRIX_PRAS11_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS11_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS11_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS11_M4PR 16\n#define AVR32_HMATRIX_PRAS11_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS11_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS11_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS11_M5PR 20\n#define AVR32_HMATRIX_PRAS11_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS11_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS11_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS11_M6PR 24\n#define AVR32_HMATRIX_PRAS11_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS11_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS11_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS11_M7PR 28\n#define AVR32_HMATRIX_PRAS11_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS11_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS11_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS12 0x000000e0\n#define AVR32_HMATRIX_PRAS12_M0PR 0\n#define AVR32_HMATRIX_PRAS12_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS12_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS12_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS12_M1PR 4\n#define AVR32_HMATRIX_PRAS12_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS12_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS12_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS12_M2PR 8\n#define AVR32_HMATRIX_PRAS12_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS12_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS12_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS12_M3PR 12\n#define AVR32_HMATRIX_PRAS12_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS12_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS12_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS12_M4PR 16\n#define AVR32_HMATRIX_PRAS12_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS12_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS12_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS12_M5PR 20\n#define AVR32_HMATRIX_PRAS12_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS12_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS12_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS12_M6PR 24\n#define AVR32_HMATRIX_PRAS12_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS12_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS12_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS12_M7PR 28\n#define AVR32_HMATRIX_PRAS12_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS12_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS12_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS13 0x000000e8\n#define AVR32_HMATRIX_PRAS13_M0PR 0\n#define AVR32_HMATRIX_PRAS13_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS13_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS13_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS13_M1PR 4\n#define AVR32_HMATRIX_PRAS13_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS13_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS13_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS13_M2PR 8\n#define AVR32_HMATRIX_PRAS13_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS13_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS13_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS13_M3PR 12\n#define AVR32_HMATRIX_PRAS13_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS13_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS13_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS13_M4PR 16\n#define AVR32_HMATRIX_PRAS13_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS13_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS13_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS13_M5PR 20\n#define AVR32_HMATRIX_PRAS13_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS13_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS13_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS13_M6PR 24\n#define AVR32_HMATRIX_PRAS13_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS13_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS13_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS13_M7PR 28\n#define AVR32_HMATRIX_PRAS13_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS13_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS13_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS14 0x000000f0\n#define AVR32_HMATRIX_PRAS14_M0PR 0\n#define AVR32_HMATRIX_PRAS14_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS14_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS14_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS14_M1PR 4\n#define AVR32_HMATRIX_PRAS14_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS14_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS14_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS14_M2PR 8\n#define AVR32_HMATRIX_PRAS14_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS14_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS14_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS14_M3PR 12\n#define AVR32_HMATRIX_PRAS14_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS14_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS14_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS14_M4PR 16\n#define AVR32_HMATRIX_PRAS14_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS14_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS14_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS14_M5PR 20\n#define AVR32_HMATRIX_PRAS14_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS14_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS14_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS14_M6PR 24\n#define AVR32_HMATRIX_PRAS14_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS14_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS14_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS14_M7PR 28\n#define AVR32_HMATRIX_PRAS14_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS14_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS14_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS15 0x000000f8\n#define AVR32_HMATRIX_PRAS15_M0PR 0\n#define AVR32_HMATRIX_PRAS15_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS15_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS15_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS15_M1PR 4\n#define AVR32_HMATRIX_PRAS15_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS15_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS15_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS15_M2PR 8\n#define AVR32_HMATRIX_PRAS15_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS15_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS15_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS15_M3PR 12\n#define AVR32_HMATRIX_PRAS15_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS15_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS15_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS15_M4PR 16\n#define AVR32_HMATRIX_PRAS15_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS15_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS15_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS15_M5PR 20\n#define AVR32_HMATRIX_PRAS15_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS15_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS15_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS15_M6PR 24\n#define AVR32_HMATRIX_PRAS15_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS15_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS15_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS15_M7PR 28\n#define AVR32_HMATRIX_PRAS15_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS15_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS15_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS1_M0PR 0\n#define AVR32_HMATRIX_PRAS1_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS1_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS1_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS1_M1PR 4\n#define AVR32_HMATRIX_PRAS1_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS1_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS1_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS1_M2PR 8\n#define AVR32_HMATRIX_PRAS1_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS1_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS1_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS1_M3PR 12\n#define AVR32_HMATRIX_PRAS1_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS1_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS1_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS1_M4PR 16\n#define AVR32_HMATRIX_PRAS1_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS1_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS1_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS1_M5PR 20\n#define AVR32_HMATRIX_PRAS1_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS1_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS1_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS1_M6PR 24\n#define AVR32_HMATRIX_PRAS1_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS1_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS1_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS1_M7PR 28\n#define AVR32_HMATRIX_PRAS1_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS1_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS1_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS2 0x00000090\n#define AVR32_HMATRIX_PRAS2_M0PR 0\n#define AVR32_HMATRIX_PRAS2_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS2_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS2_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS2_M1PR 4\n#define AVR32_HMATRIX_PRAS2_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS2_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS2_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS2_M2PR 8\n#define AVR32_HMATRIX_PRAS2_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS2_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS2_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS2_M3PR 12\n#define AVR32_HMATRIX_PRAS2_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS2_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS2_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS2_M4PR 16\n#define AVR32_HMATRIX_PRAS2_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS2_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS2_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS2_M5PR 20\n#define AVR32_HMATRIX_PRAS2_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS2_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS2_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS2_M6PR 24\n#define AVR32_HMATRIX_PRAS2_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS2_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS2_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS2_M7PR 28\n#define AVR32_HMATRIX_PRAS2_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS2_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS2_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS3 0x00000098\n#define AVR32_HMATRIX_PRAS3_M0PR 0\n#define AVR32_HMATRIX_PRAS3_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS3_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS3_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS3_M1PR 4\n#define AVR32_HMATRIX_PRAS3_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS3_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS3_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS3_M2PR 8\n#define AVR32_HMATRIX_PRAS3_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS3_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS3_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS3_M3PR 12\n#define AVR32_HMATRIX_PRAS3_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS3_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS3_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS3_M4PR 16\n#define AVR32_HMATRIX_PRAS3_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS3_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS3_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS3_M5PR 20\n#define AVR32_HMATRIX_PRAS3_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS3_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS3_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS3_M6PR 24\n#define AVR32_HMATRIX_PRAS3_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS3_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS3_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS3_M7PR 28\n#define AVR32_HMATRIX_PRAS3_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS3_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS3_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS4 0x000000a0\n#define AVR32_HMATRIX_PRAS4_M0PR 0\n#define AVR32_HMATRIX_PRAS4_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS4_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS4_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS4_M1PR 4\n#define AVR32_HMATRIX_PRAS4_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS4_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS4_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS4_M2PR 8\n#define AVR32_HMATRIX_PRAS4_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS4_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS4_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS4_M3PR 12\n#define AVR32_HMATRIX_PRAS4_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS4_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS4_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS4_M4PR 16\n#define AVR32_HMATRIX_PRAS4_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS4_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS4_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS4_M5PR 20\n#define AVR32_HMATRIX_PRAS4_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS4_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS4_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS4_M6PR 24\n#define AVR32_HMATRIX_PRAS4_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS4_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS4_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS4_M7PR 28\n#define AVR32_HMATRIX_PRAS4_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS4_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS4_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS5 0x000000a8\n#define AVR32_HMATRIX_PRAS5_M0PR 0\n#define AVR32_HMATRIX_PRAS5_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS5_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS5_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS5_M1PR 4\n#define AVR32_HMATRIX_PRAS5_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS5_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS5_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS5_M2PR 8\n#define AVR32_HMATRIX_PRAS5_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS5_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS5_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS5_M3PR 12\n#define AVR32_HMATRIX_PRAS5_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS5_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS5_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS5_M4PR 16\n#define AVR32_HMATRIX_PRAS5_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS5_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS5_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS5_M5PR 20\n#define AVR32_HMATRIX_PRAS5_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS5_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS5_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS5_M6PR 24\n#define AVR32_HMATRIX_PRAS5_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS5_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS5_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS5_M7PR 28\n#define AVR32_HMATRIX_PRAS5_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS5_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS5_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS6 0x000000b0\n#define AVR32_HMATRIX_PRAS6_M0PR 0\n#define AVR32_HMATRIX_PRAS6_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS6_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS6_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS6_M1PR 4\n#define AVR32_HMATRIX_PRAS6_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS6_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS6_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS6_M2PR 8\n#define AVR32_HMATRIX_PRAS6_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS6_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS6_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS6_M3PR 12\n#define AVR32_HMATRIX_PRAS6_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS6_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS6_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS6_M4PR 16\n#define AVR32_HMATRIX_PRAS6_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS6_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS6_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS6_M5PR 20\n#define AVR32_HMATRIX_PRAS6_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS6_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS6_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS6_M6PR 24\n#define AVR32_HMATRIX_PRAS6_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS6_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS6_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS6_M7PR 28\n#define AVR32_HMATRIX_PRAS6_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS6_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS6_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS7 0x000000b8\n#define AVR32_HMATRIX_PRAS7_M0PR 0\n#define AVR32_HMATRIX_PRAS7_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS7_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS7_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS7_M1PR 4\n#define AVR32_HMATRIX_PRAS7_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS7_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS7_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS7_M2PR 8\n#define AVR32_HMATRIX_PRAS7_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS7_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS7_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS7_M3PR 12\n#define AVR32_HMATRIX_PRAS7_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS7_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS7_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS7_M4PR 16\n#define AVR32_HMATRIX_PRAS7_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS7_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS7_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS7_M5PR 20\n#define AVR32_HMATRIX_PRAS7_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS7_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS7_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS7_M6PR 24\n#define AVR32_HMATRIX_PRAS7_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS7_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS7_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS7_M7PR 28\n#define AVR32_HMATRIX_PRAS7_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS7_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS7_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS8 0x000000c0\n#define AVR32_HMATRIX_PRAS8_M0PR 0\n#define AVR32_HMATRIX_PRAS8_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS8_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS8_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS8_M1PR 4\n#define AVR32_HMATRIX_PRAS8_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS8_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS8_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS8_M2PR 8\n#define AVR32_HMATRIX_PRAS8_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS8_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS8_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS8_M3PR 12\n#define AVR32_HMATRIX_PRAS8_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS8_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS8_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS8_M4PR 16\n#define AVR32_HMATRIX_PRAS8_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS8_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS8_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS8_M5PR 20\n#define AVR32_HMATRIX_PRAS8_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS8_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS8_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS8_M6PR 24\n#define AVR32_HMATRIX_PRAS8_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS8_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS8_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS8_M7PR 28\n#define AVR32_HMATRIX_PRAS8_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS8_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS8_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRAS9 0x000000c8\n#define AVR32_HMATRIX_PRAS9_M0PR 0\n#define AVR32_HMATRIX_PRAS9_M0PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRAS9_M0PR_OFFSET 0\n#define AVR32_HMATRIX_PRAS9_M0PR_SIZE 4\n#define AVR32_HMATRIX_PRAS9_M1PR 4\n#define AVR32_HMATRIX_PRAS9_M1PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRAS9_M1PR_OFFSET 4\n#define AVR32_HMATRIX_PRAS9_M1PR_SIZE 4\n#define AVR32_HMATRIX_PRAS9_M2PR 8\n#define AVR32_HMATRIX_PRAS9_M2PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRAS9_M2PR_OFFSET 8\n#define AVR32_HMATRIX_PRAS9_M2PR_SIZE 4\n#define AVR32_HMATRIX_PRAS9_M3PR 12\n#define AVR32_HMATRIX_PRAS9_M3PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRAS9_M3PR_OFFSET 12\n#define AVR32_HMATRIX_PRAS9_M3PR_SIZE 4\n#define AVR32_HMATRIX_PRAS9_M4PR 16\n#define AVR32_HMATRIX_PRAS9_M4PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRAS9_M4PR_OFFSET 16\n#define AVR32_HMATRIX_PRAS9_M4PR_SIZE 4\n#define AVR32_HMATRIX_PRAS9_M5PR 20\n#define AVR32_HMATRIX_PRAS9_M5PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRAS9_M5PR_OFFSET 20\n#define AVR32_HMATRIX_PRAS9_M5PR_SIZE 4\n#define AVR32_HMATRIX_PRAS9_M6PR 24\n#define AVR32_HMATRIX_PRAS9_M6PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRAS9_M6PR_OFFSET 24\n#define AVR32_HMATRIX_PRAS9_M6PR_SIZE 4\n#define AVR32_HMATRIX_PRAS9_M7PR 28\n#define AVR32_HMATRIX_PRAS9_M7PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRAS9_M7PR_OFFSET 28\n#define AVR32_HMATRIX_PRAS9_M7PR_SIZE 4\n#define AVR32_HMATRIX_PRBS0 0x00000084\n#define AVR32_HMATRIX_PRBS0_M10PR 8\n#define AVR32_HMATRIX_PRBS0_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS0_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS0_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS0_M11PR 12\n#define AVR32_HMATRIX_PRBS0_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS0_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS0_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS0_M12PR 16\n#define AVR32_HMATRIX_PRBS0_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS0_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS0_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS0_M13PR 20\n#define AVR32_HMATRIX_PRBS0_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS0_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS0_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS0_M14PR 24\n#define AVR32_HMATRIX_PRBS0_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS0_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS0_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS0_M15PR 28\n#define AVR32_HMATRIX_PRBS0_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS0_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS0_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS0_M8PR 0\n#define AVR32_HMATRIX_PRBS0_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS0_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS0_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS0_M9PR 4\n#define AVR32_HMATRIX_PRBS0_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS0_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS0_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS1 0x0000008c\n#define AVR32_HMATRIX_PRBS10 0x000000d4\n#define AVR32_HMATRIX_PRBS10_M10PR 8\n#define AVR32_HMATRIX_PRBS10_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS10_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS10_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS10_M11PR 12\n#define AVR32_HMATRIX_PRBS10_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS10_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS10_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS10_M12PR 16\n#define AVR32_HMATRIX_PRBS10_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS10_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS10_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS10_M13PR 20\n#define AVR32_HMATRIX_PRBS10_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS10_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS10_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS10_M14PR 24\n#define AVR32_HMATRIX_PRBS10_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS10_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS10_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS10_M15PR 28\n#define AVR32_HMATRIX_PRBS10_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS10_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS10_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS10_M8PR 0\n#define AVR32_HMATRIX_PRBS10_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS10_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS10_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS10_M9PR 4\n#define AVR32_HMATRIX_PRBS10_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS10_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS10_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS11 0x000000dc\n#define AVR32_HMATRIX_PRBS11_M10PR 8\n#define AVR32_HMATRIX_PRBS11_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS11_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS11_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS11_M11PR 12\n#define AVR32_HMATRIX_PRBS11_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS11_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS11_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS11_M12PR 16\n#define AVR32_HMATRIX_PRBS11_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS11_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS11_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS11_M13PR 20\n#define AVR32_HMATRIX_PRBS11_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS11_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS11_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS11_M14PR 24\n#define AVR32_HMATRIX_PRBS11_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS11_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS11_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS11_M15PR 28\n#define AVR32_HMATRIX_PRBS11_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS11_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS11_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS11_M8PR 0\n#define AVR32_HMATRIX_PRBS11_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS11_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS11_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS11_M9PR 4\n#define AVR32_HMATRIX_PRBS11_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS11_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS11_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS12 0x000000e4\n#define AVR32_HMATRIX_PRBS12_M10PR 8\n#define AVR32_HMATRIX_PRBS12_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS12_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS12_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS12_M11PR 12\n#define AVR32_HMATRIX_PRBS12_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS12_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS12_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS12_M12PR 16\n#define AVR32_HMATRIX_PRBS12_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS12_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS12_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS12_M13PR 20\n#define AVR32_HMATRIX_PRBS12_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS12_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS12_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS12_M14PR 24\n#define AVR32_HMATRIX_PRBS12_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS12_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS12_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS12_M15PR 28\n#define AVR32_HMATRIX_PRBS12_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS12_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS12_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS12_M8PR 0\n#define AVR32_HMATRIX_PRBS12_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS12_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS12_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS12_M9PR 4\n#define AVR32_HMATRIX_PRBS12_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS12_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS12_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS13 0x000000ec\n#define AVR32_HMATRIX_PRBS13_M10PR 8\n#define AVR32_HMATRIX_PRBS13_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS13_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS13_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS13_M11PR 12\n#define AVR32_HMATRIX_PRBS13_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS13_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS13_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS13_M12PR 16\n#define AVR32_HMATRIX_PRBS13_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS13_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS13_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS13_M13PR 20\n#define AVR32_HMATRIX_PRBS13_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS13_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS13_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS13_M14PR 24\n#define AVR32_HMATRIX_PRBS13_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS13_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS13_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS13_M15PR 28\n#define AVR32_HMATRIX_PRBS13_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS13_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS13_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS13_M8PR 0\n#define AVR32_HMATRIX_PRBS13_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS13_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS13_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS13_M9PR 4\n#define AVR32_HMATRIX_PRBS13_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS13_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS13_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS14 0x000000f4\n#define AVR32_HMATRIX_PRBS14_M10PR 8\n#define AVR32_HMATRIX_PRBS14_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS14_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS14_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS14_M11PR 12\n#define AVR32_HMATRIX_PRBS14_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS14_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS14_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS14_M12PR 16\n#define AVR32_HMATRIX_PRBS14_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS14_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS14_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS14_M13PR 20\n#define AVR32_HMATRIX_PRBS14_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS14_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS14_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS14_M14PR 24\n#define AVR32_HMATRIX_PRBS14_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS14_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS14_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS14_M15PR 28\n#define AVR32_HMATRIX_PRBS14_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS14_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS14_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS14_M8PR 0\n#define AVR32_HMATRIX_PRBS14_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS14_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS14_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS14_M9PR 4\n#define AVR32_HMATRIX_PRBS14_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS14_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS14_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS15 0x000000fc\n#define AVR32_HMATRIX_PRBS15_M10PR 8\n#define AVR32_HMATRIX_PRBS15_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS15_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS15_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS15_M11PR 12\n#define AVR32_HMATRIX_PRBS15_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS15_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS15_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS15_M12PR 16\n#define AVR32_HMATRIX_PRBS15_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS15_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS15_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS15_M13PR 20\n#define AVR32_HMATRIX_PRBS15_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS15_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS15_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS15_M14PR 24\n#define AVR32_HMATRIX_PRBS15_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS15_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS15_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS15_M15PR 28\n#define AVR32_HMATRIX_PRBS15_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS15_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS15_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS15_M8PR 0\n#define AVR32_HMATRIX_PRBS15_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS15_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS15_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS15_M9PR 4\n#define AVR32_HMATRIX_PRBS15_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS15_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS15_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS1_M10PR 8\n#define AVR32_HMATRIX_PRBS1_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS1_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS1_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS1_M11PR 12\n#define AVR32_HMATRIX_PRBS1_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS1_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS1_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS1_M12PR 16\n#define AVR32_HMATRIX_PRBS1_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS1_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS1_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS1_M13PR 20\n#define AVR32_HMATRIX_PRBS1_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS1_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS1_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS1_M14PR 24\n#define AVR32_HMATRIX_PRBS1_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS1_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS1_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS1_M15PR 28\n#define AVR32_HMATRIX_PRBS1_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS1_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS1_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS1_M8PR 0\n#define AVR32_HMATRIX_PRBS1_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS1_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS1_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS1_M9PR 4\n#define AVR32_HMATRIX_PRBS1_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS1_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS1_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS2 0x00000094\n#define AVR32_HMATRIX_PRBS2_M10PR 8\n#define AVR32_HMATRIX_PRBS2_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS2_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS2_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS2_M11PR 12\n#define AVR32_HMATRIX_PRBS2_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS2_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS2_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS2_M12PR 16\n#define AVR32_HMATRIX_PRBS2_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS2_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS2_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS2_M13PR 20\n#define AVR32_HMATRIX_PRBS2_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS2_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS2_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS2_M14PR 24\n#define AVR32_HMATRIX_PRBS2_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS2_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS2_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS2_M15PR 28\n#define AVR32_HMATRIX_PRBS2_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS2_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS2_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS2_M8PR 0\n#define AVR32_HMATRIX_PRBS2_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS2_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS2_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS2_M9PR 4\n#define AVR32_HMATRIX_PRBS2_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS2_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS2_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS3 0x0000009c\n#define AVR32_HMATRIX_PRBS3_M10PR 8\n#define AVR32_HMATRIX_PRBS3_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS3_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS3_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS3_M11PR 12\n#define AVR32_HMATRIX_PRBS3_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS3_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS3_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS3_M12PR 16\n#define AVR32_HMATRIX_PRBS3_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS3_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS3_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS3_M13PR 20\n#define AVR32_HMATRIX_PRBS3_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS3_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS3_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS3_M14PR 24\n#define AVR32_HMATRIX_PRBS3_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS3_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS3_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS3_M15PR 28\n#define AVR32_HMATRIX_PRBS3_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS3_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS3_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS3_M8PR 0\n#define AVR32_HMATRIX_PRBS3_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS3_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS3_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS3_M9PR 4\n#define AVR32_HMATRIX_PRBS3_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS3_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS3_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS4 0x000000a4\n#define AVR32_HMATRIX_PRBS4_M10PR 8\n#define AVR32_HMATRIX_PRBS4_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS4_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS4_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS4_M11PR 12\n#define AVR32_HMATRIX_PRBS4_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS4_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS4_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS4_M12PR 16\n#define AVR32_HMATRIX_PRBS4_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS4_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS4_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS4_M13PR 20\n#define AVR32_HMATRIX_PRBS4_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS4_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS4_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS4_M14PR 24\n#define AVR32_HMATRIX_PRBS4_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS4_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS4_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS4_M15PR 28\n#define AVR32_HMATRIX_PRBS4_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS4_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS4_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS4_M8PR 0\n#define AVR32_HMATRIX_PRBS4_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS4_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS4_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS4_M9PR 4\n#define AVR32_HMATRIX_PRBS4_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS4_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS4_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS5 0x000000ac\n#define AVR32_HMATRIX_PRBS5_M10PR 8\n#define AVR32_HMATRIX_PRBS5_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS5_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS5_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS5_M11PR 12\n#define AVR32_HMATRIX_PRBS5_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS5_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS5_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS5_M12PR 16\n#define AVR32_HMATRIX_PRBS5_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS5_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS5_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS5_M13PR 20\n#define AVR32_HMATRIX_PRBS5_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS5_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS5_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS5_M14PR 24\n#define AVR32_HMATRIX_PRBS5_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS5_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS5_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS5_M15PR 28\n#define AVR32_HMATRIX_PRBS5_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS5_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS5_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS5_M8PR 0\n#define AVR32_HMATRIX_PRBS5_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS5_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS5_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS5_M9PR 4\n#define AVR32_HMATRIX_PRBS5_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS5_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS5_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS6 0x000000b4\n#define AVR32_HMATRIX_PRBS6_M10PR 8\n#define AVR32_HMATRIX_PRBS6_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS6_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS6_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS6_M11PR 12\n#define AVR32_HMATRIX_PRBS6_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS6_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS6_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS6_M12PR 16\n#define AVR32_HMATRIX_PRBS6_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS6_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS6_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS6_M13PR 20\n#define AVR32_HMATRIX_PRBS6_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS6_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS6_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS6_M14PR 24\n#define AVR32_HMATRIX_PRBS6_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS6_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS6_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS6_M15PR 28\n#define AVR32_HMATRIX_PRBS6_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS6_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS6_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS6_M8PR 0\n#define AVR32_HMATRIX_PRBS6_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS6_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS6_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS6_M9PR 4\n#define AVR32_HMATRIX_PRBS6_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS6_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS6_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS7 0x000000bc\n#define AVR32_HMATRIX_PRBS7_M10PR 8\n#define AVR32_HMATRIX_PRBS7_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS7_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS7_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS7_M11PR 12\n#define AVR32_HMATRIX_PRBS7_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS7_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS7_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS7_M12PR 16\n#define AVR32_HMATRIX_PRBS7_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS7_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS7_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS7_M13PR 20\n#define AVR32_HMATRIX_PRBS7_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS7_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS7_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS7_M14PR 24\n#define AVR32_HMATRIX_PRBS7_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS7_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS7_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS7_M15PR 28\n#define AVR32_HMATRIX_PRBS7_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS7_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS7_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS7_M8PR 0\n#define AVR32_HMATRIX_PRBS7_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS7_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS7_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS7_M9PR 4\n#define AVR32_HMATRIX_PRBS7_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS7_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS7_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS8 0x000000c4\n#define AVR32_HMATRIX_PRBS8_M10PR 8\n#define AVR32_HMATRIX_PRBS8_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS8_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS8_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS8_M11PR 12\n#define AVR32_HMATRIX_PRBS8_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS8_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS8_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS8_M12PR 16\n#define AVR32_HMATRIX_PRBS8_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS8_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS8_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS8_M13PR 20\n#define AVR32_HMATRIX_PRBS8_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS8_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS8_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS8_M14PR 24\n#define AVR32_HMATRIX_PRBS8_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS8_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS8_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS8_M15PR 28\n#define AVR32_HMATRIX_PRBS8_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS8_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS8_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS8_M8PR 0\n#define AVR32_HMATRIX_PRBS8_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS8_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS8_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS8_M9PR 4\n#define AVR32_HMATRIX_PRBS8_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS8_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS8_M9PR_SIZE 4\n#define AVR32_HMATRIX_PRBS9 0x000000cc\n#define AVR32_HMATRIX_PRBS9_M10PR 8\n#define AVR32_HMATRIX_PRBS9_M10PR_MASK 0x00000f00\n#define AVR32_HMATRIX_PRBS9_M10PR_OFFSET 8\n#define AVR32_HMATRIX_PRBS9_M10PR_SIZE 4\n#define AVR32_HMATRIX_PRBS9_M11PR 12\n#define AVR32_HMATRIX_PRBS9_M11PR_MASK 0x0000f000\n#define AVR32_HMATRIX_PRBS9_M11PR_OFFSET 12\n#define AVR32_HMATRIX_PRBS9_M11PR_SIZE 4\n#define AVR32_HMATRIX_PRBS9_M12PR 16\n#define AVR32_HMATRIX_PRBS9_M12PR_MASK 0x000f0000\n#define AVR32_HMATRIX_PRBS9_M12PR_OFFSET 16\n#define AVR32_HMATRIX_PRBS9_M12PR_SIZE 4\n#define AVR32_HMATRIX_PRBS9_M13PR 20\n#define AVR32_HMATRIX_PRBS9_M13PR_MASK 0x00f00000\n#define AVR32_HMATRIX_PRBS9_M13PR_OFFSET 20\n#define AVR32_HMATRIX_PRBS9_M13PR_SIZE 4\n#define AVR32_HMATRIX_PRBS9_M14PR 24\n#define AVR32_HMATRIX_PRBS9_M14PR_MASK 0x0f000000\n#define AVR32_HMATRIX_PRBS9_M14PR_OFFSET 24\n#define AVR32_HMATRIX_PRBS9_M14PR_SIZE 4\n#define AVR32_HMATRIX_PRBS9_M15PR 28\n#define AVR32_HMATRIX_PRBS9_M15PR_MASK 0xf0000000\n#define AVR32_HMATRIX_PRBS9_M15PR_OFFSET 28\n#define AVR32_HMATRIX_PRBS9_M15PR_SIZE 4\n#define AVR32_HMATRIX_PRBS9_M8PR 0\n#define AVR32_HMATRIX_PRBS9_M8PR_MASK 0x0000000f\n#define AVR32_HMATRIX_PRBS9_M8PR_OFFSET 0\n#define AVR32_HMATRIX_PRBS9_M8PR_SIZE 4\n#define AVR32_HMATRIX_PRBS9_M9PR 4\n#define AVR32_HMATRIX_PRBS9_M9PR_MASK 0x000000f0\n#define AVR32_HMATRIX_PRBS9_M9PR_OFFSET 4\n#define AVR32_HMATRIX_PRBS9_M9PR_SIZE 4\n#define AVR32_HMATRIX_RCB0 0\n#define AVR32_HMATRIX_RCB0_MASK 0x00000001\n#define AVR32_HMATRIX_RCB0_OFFSET 0\n#define AVR32_HMATRIX_RCB0_SIZE 1\n#define AVR32_HMATRIX_RCB1 1\n#define AVR32_HMATRIX_RCB10 10\n#define AVR32_HMATRIX_RCB10_MASK 0x00000400\n#define AVR32_HMATRIX_RCB10_OFFSET 10\n#define AVR32_HMATRIX_RCB10_SIZE 1\n#define AVR32_HMATRIX_RCB11 11\n#define AVR32_HMATRIX_RCB11_MASK 0x00000800\n#define AVR32_HMATRIX_RCB11_OFFSET 11\n#define AVR32_HMATRIX_RCB11_SIZE 1\n#define AVR32_HMATRIX_RCB12 12\n#define AVR32_HMATRIX_RCB12_MASK 0x00001000\n#define AVR32_HMATRIX_RCB12_OFFSET 12\n#define AVR32_HMATRIX_RCB12_SIZE 1\n#define AVR32_HMATRIX_RCB13 13\n#define AVR32_HMATRIX_RCB13_MASK 0x00002000\n#define AVR32_HMATRIX_RCB13_OFFSET 13\n#define AVR32_HMATRIX_RCB13_SIZE 1\n#define AVR32_HMATRIX_RCB14 14\n#define AVR32_HMATRIX_RCB14_MASK 0x00004000\n#define AVR32_HMATRIX_RCB14_OFFSET 14\n#define AVR32_HMATRIX_RCB14_SIZE 1\n#define AVR32_HMATRIX_RCB15 15\n#define AVR32_HMATRIX_RCB15_MASK 0x00008000\n#define AVR32_HMATRIX_RCB15_OFFSET 15\n#define AVR32_HMATRIX_RCB15_SIZE 1\n#define AVR32_HMATRIX_RCB1_MASK 0x00000002\n#define AVR32_HMATRIX_RCB1_OFFSET 1\n#define AVR32_HMATRIX_RCB1_SIZE 1\n#define AVR32_HMATRIX_RCB2 2\n#define AVR32_HMATRIX_RCB2_MASK 0x00000004\n#define AVR32_HMATRIX_RCB2_OFFSET 2\n#define AVR32_HMATRIX_RCB2_SIZE 1\n#define AVR32_HMATRIX_RCB3 3\n#define AVR32_HMATRIX_RCB3_MASK 0x00000008\n#define AVR32_HMATRIX_RCB3_OFFSET 3\n#define AVR32_HMATRIX_RCB3_SIZE 1\n#define AVR32_HMATRIX_RCB4 4\n#define AVR32_HMATRIX_RCB4_MASK 0x00000010\n#define AVR32_HMATRIX_RCB4_OFFSET 4\n#define AVR32_HMATRIX_RCB4_SIZE 1\n#define AVR32_HMATRIX_RCB5 5\n#define AVR32_HMATRIX_RCB5_MASK 0x00000020\n#define AVR32_HMATRIX_RCB5_OFFSET 5\n#define AVR32_HMATRIX_RCB5_SIZE 1\n#define AVR32_HMATRIX_RCB6 6\n#define AVR32_HMATRIX_RCB6_MASK 0x00000040\n#define AVR32_HMATRIX_RCB6_OFFSET 6\n#define AVR32_HMATRIX_RCB6_SIZE 1\n#define AVR32_HMATRIX_RCB7 7\n#define AVR32_HMATRIX_RCB7_MASK 0x00000080\n#define AVR32_HMATRIX_RCB7_OFFSET 7\n#define AVR32_HMATRIX_RCB7_SIZE 1\n#define AVR32_HMATRIX_RCB8 8\n#define AVR32_HMATRIX_RCB8_MASK 0x00000100\n#define AVR32_HMATRIX_RCB8_OFFSET 8\n#define AVR32_HMATRIX_RCB8_SIZE 1\n#define AVR32_HMATRIX_RCB9 9\n#define AVR32_HMATRIX_RCB9_MASK 0x00000200\n#define AVR32_HMATRIX_RCB9_OFFSET 9\n#define AVR32_HMATRIX_RCB9_SIZE 1\n#define AVR32_HMATRIX_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG0 0x00000040\n#define AVR32_HMATRIX_SCFG0_ARBT 24\n#define AVR32_HMATRIX_SCFG0_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG0_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG0_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG0_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG0_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG0_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG0_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG0_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG0_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG0_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG0_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG0_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG0_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG0_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG0_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG0_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG0_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG0_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG0_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG0_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG1 0x00000044\n#define AVR32_HMATRIX_SCFG10 0x00000068\n#define AVR32_HMATRIX_SCFG10_ARBT 24\n#define AVR32_HMATRIX_SCFG10_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG10_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG10_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG10_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG10_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG10_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG10_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG10_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG10_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG10_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG10_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG10_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG10_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG10_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG10_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG10_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG10_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG10_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG10_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG10_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG11 0x0000006c\n#define AVR32_HMATRIX_SCFG11_ARBT 24\n#define AVR32_HMATRIX_SCFG11_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG11_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG11_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG11_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG11_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG11_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG11_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG11_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG11_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG11_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG11_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG11_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG11_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG11_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG11_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG11_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG11_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG11_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG11_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG11_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG12 0x00000070\n#define AVR32_HMATRIX_SCFG12_ARBT 24\n#define AVR32_HMATRIX_SCFG12_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG12_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG12_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG12_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG12_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG12_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG12_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG12_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG12_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG12_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG12_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG12_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG12_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG12_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG12_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG12_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG12_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG12_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG12_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG12_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG13 0x00000074\n#define AVR32_HMATRIX_SCFG13_ARBT 24\n#define AVR32_HMATRIX_SCFG13_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG13_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG13_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG13_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG13_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG13_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG13_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG13_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG13_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG13_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG13_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG13_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG13_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG13_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG13_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG13_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG13_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG13_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG13_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG13_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG14 0x00000078\n#define AVR32_HMATRIX_SCFG14_ARBT 24\n#define AVR32_HMATRIX_SCFG14_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG14_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG14_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG14_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG14_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG14_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG14_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG14_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG14_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG14_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG14_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG14_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG14_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG14_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG14_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG14_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG14_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG14_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG14_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG14_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG15 0x0000007c\n#define AVR32_HMATRIX_SCFG15_ARBT 24\n#define AVR32_HMATRIX_SCFG15_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG15_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG15_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG15_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG15_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG15_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG15_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG15_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG15_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG15_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG15_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG15_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG15_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG15_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG15_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG15_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG15_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG15_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG15_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG15_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG1_ARBT 24\n#define AVR32_HMATRIX_SCFG1_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG1_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG1_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG1_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG1_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG1_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG1_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG1_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG1_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG1_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG1_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG1_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG1_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG1_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG1_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG1_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG1_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG1_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG1_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG1_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG2 0x00000048\n#define AVR32_HMATRIX_SCFG2_ARBT 24\n#define AVR32_HMATRIX_SCFG2_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG2_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG2_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG2_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG2_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG2_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG2_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG2_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG2_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG2_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG2_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG2_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG2_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG2_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG2_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG2_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG2_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG2_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG2_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG2_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG3 0x0000004c\n#define AVR32_HMATRIX_SCFG3_ARBT 24\n#define AVR32_HMATRIX_SCFG3_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG3_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG3_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG3_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG3_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG3_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG3_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG3_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG3_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG3_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG3_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG3_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG3_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG3_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG3_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG3_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG3_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG3_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG3_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG3_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG4 0x00000050\n#define AVR32_HMATRIX_SCFG4_ARBT 24\n#define AVR32_HMATRIX_SCFG4_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG4_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG4_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG4_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG4_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG4_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG4_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG4_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG4_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG4_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG4_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG4_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG4_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG4_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG4_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG4_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG4_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG4_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG4_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG4_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG5 0x00000054\n#define AVR32_HMATRIX_SCFG5_ARBT 24\n#define AVR32_HMATRIX_SCFG5_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG5_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG5_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG5_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG5_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG5_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG5_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG5_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG5_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG5_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG5_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG5_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG5_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG5_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG5_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG5_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG5_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG5_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG5_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG5_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG6 0x00000058\n#define AVR32_HMATRIX_SCFG6_ARBT 24\n#define AVR32_HMATRIX_SCFG6_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG6_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG6_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG6_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG6_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG6_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG6_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG6_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG6_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG6_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG6_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG6_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG6_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG6_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG6_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG6_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG6_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG6_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG6_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG6_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG7 0x0000005c\n#define AVR32_HMATRIX_SCFG7_ARBT 24\n#define AVR32_HMATRIX_SCFG7_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG7_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG7_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG7_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG7_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG7_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG7_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG7_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG7_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG7_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG7_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG7_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG7_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG7_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG7_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG7_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG7_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG7_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG7_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG7_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG8 0x00000060\n#define AVR32_HMATRIX_SCFG8_ARBT 24\n#define AVR32_HMATRIX_SCFG8_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG8_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG8_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG8_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG8_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG8_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG8_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG8_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG8_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG8_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG8_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG8_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG8_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG8_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG8_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG8_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG8_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG8_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG8_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG8_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SCFG9 0x00000064\n#define AVR32_HMATRIX_SCFG9_ARBT 24\n#define AVR32_HMATRIX_SCFG9_ARBT_FIXED_PRIORITY 0x00000001\n#define AVR32_HMATRIX_SCFG9_ARBT_MASK 0x01000000\n#define AVR32_HMATRIX_SCFG9_ARBT_OFFSET 24\n#define AVR32_HMATRIX_SCFG9_ARBT_ROUND_ROBIN 0x00000000\n#define AVR32_HMATRIX_SCFG9_ARBT_SIZE 1\n#define AVR32_HMATRIX_SCFG9_DEFMSTR_TYPE 16\n#define AVR32_HMATRIX_SCFG9_DEFMSTR_TYPE_FIXED_DEFAULT 0x00000002\n#define AVR32_HMATRIX_SCFG9_DEFMSTR_TYPE_LAST_DEFAULT 0x00000001\n#define AVR32_HMATRIX_SCFG9_DEFMSTR_TYPE_MASK 0x00030000\n#define AVR32_HMATRIX_SCFG9_DEFMSTR_TYPE_NO_DEFAULT 0x00000000\n#define AVR32_HMATRIX_SCFG9_DEFMSTR_TYPE_OFFSET 16\n#define AVR32_HMATRIX_SCFG9_DEFMSTR_TYPE_SIZE 2\n#define AVR32_HMATRIX_SCFG9_FIXED_DEFMSTR 18\n#define AVR32_HMATRIX_SCFG9_FIXED_DEFMSTR_MASK 0x003c0000\n#define AVR32_HMATRIX_SCFG9_FIXED_DEFMSTR_OFFSET 18\n#define AVR32_HMATRIX_SCFG9_FIXED_DEFMSTR_SIZE 4\n#define AVR32_HMATRIX_SCFG9_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SCFG9_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SCFG9_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SCFG9_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_SFR 0\n#define AVR32_HMATRIX_SFR0 0x00000110\n#define AVR32_HMATRIX_SFR0_SFR 0\n#define AVR32_HMATRIX_SFR0_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR0_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR0_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR1 0x00000114\n#define AVR32_HMATRIX_SFR10 0x00000138\n#define AVR32_HMATRIX_SFR10_SFR 0\n#define AVR32_HMATRIX_SFR10_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR10_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR10_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR11 0x0000013c\n#define AVR32_HMATRIX_SFR11_SFR 0\n#define AVR32_HMATRIX_SFR11_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR11_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR11_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR12 0x00000140\n#define AVR32_HMATRIX_SFR12_SFR 0\n#define AVR32_HMATRIX_SFR12_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR12_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR12_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR13 0x00000144\n#define AVR32_HMATRIX_SFR13_SFR 0\n#define AVR32_HMATRIX_SFR13_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR13_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR13_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR14 0x00000148\n#define AVR32_HMATRIX_SFR14_SFR 0\n#define AVR32_HMATRIX_SFR14_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR14_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR14_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR15 0x0000014c\n#define AVR32_HMATRIX_SFR15_SFR 0\n#define AVR32_HMATRIX_SFR15_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR15_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR15_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR1_SFR 0\n#define AVR32_HMATRIX_SFR1_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR1_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR1_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR2 0x00000118\n#define AVR32_HMATRIX_SFR2_SFR 0\n#define AVR32_HMATRIX_SFR2_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR2_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR2_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR3 0x0000011c\n#define AVR32_HMATRIX_SFR3_SFR 0\n#define AVR32_HMATRIX_SFR3_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR3_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR3_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR4 0x00000120\n#define AVR32_HMATRIX_SFR4_SFR 0\n#define AVR32_HMATRIX_SFR4_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR4_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR4_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR5 0x00000124\n#define AVR32_HMATRIX_SFR5_SFR 0\n#define AVR32_HMATRIX_SFR5_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR5_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR5_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR6 0x00000128\n#define AVR32_HMATRIX_SFR6_SFR 0\n#define AVR32_HMATRIX_SFR6_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR6_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR6_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR7 0x0000012c\n#define AVR32_HMATRIX_SFR7_SFR 0\n#define AVR32_HMATRIX_SFR7_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR7_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR7_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR8 0x00000130\n#define AVR32_HMATRIX_SFR8_SFR 0\n#define AVR32_HMATRIX_SFR8_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR8_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR8_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR9 0x00000134\n#define AVR32_HMATRIX_SFR9_SFR 0\n#define AVR32_HMATRIX_SFR9_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR9_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR9_SFR_SIZE 32\n#define AVR32_HMATRIX_SFR_MASK 0xffffffff\n#define AVR32_HMATRIX_SFR_OFFSET 0\n#define AVR32_HMATRIX_SFR_SIZE 32\n#define AVR32_HMATRIX_SINGLE 0x00000001\n#define AVR32_HMATRIX_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_SLOT_CYCLE 0\n#define AVR32_HMATRIX_SLOT_CYCLE_MASK 0x000000ff\n#define AVR32_HMATRIX_SLOT_CYCLE_OFFSET 0\n#define AVR32_HMATRIX_SLOT_CYCLE_SIZE 8\n#define AVR32_HMATRIX_ULBT 0\n#define AVR32_HMATRIX_ULBT_EIGHT_BEAT 0x00000003\n#define AVR32_HMATRIX_ULBT_FOUR_BEAT 0x00000002\n#define AVR32_HMATRIX_ULBT_INFINITE 0x00000000\n#define AVR32_HMATRIX_ULBT_MASK 0x00000007\n#define AVR32_HMATRIX_ULBT_OFFSET 0\n#define AVR32_HMATRIX_ULBT_SINGLE 0x00000001\n#define AVR32_HMATRIX_ULBT_SIXTEEN_BEAT 0x00000004\n#define AVR32_HMATRIX_ULBT_SIZE 3\n#define AVR32_HMATRIX_VARIANT 16\n#define AVR32_HMATRIX_VARIANT_MASK 0x00070000\n#define AVR32_HMATRIX_VARIANT_OFFSET 16\n#define AVR32_HMATRIX_VARIANT_SIZE 3\n#define AVR32_HMATRIX_VERSION 0x000001fc\n#define AVR32_HMATRIX_VERSION_MASK 0x00000fff\n#define AVR32_HMATRIX_VERSION_OFFSET 0\n#define AVR32_HMATRIX_VERSION_SIZE 12\n#define AVR32_HMATRIX_VERSION_VARIANT 16\n#define AVR32_HMATRIX_VERSION_VARIANT_MASK 0x00070000\n#define AVR32_HMATRIX_VERSION_VARIANT_OFFSET 16\n#define AVR32_HMATRIX_VERSION_VARIANT_SIZE 3\n#define AVR32_HMATRIX_VERSION_VERSION 0\n#define AVR32_HMATRIX_VERSION_VERSION_MASK 0x00000fff\n#define AVR32_HMATRIX_VERSION_VERSION_OFFSET 0\n#define AVR32_HMATRIX_VERSION_VERSION_SIZE 12\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_hmatrix_mcfg_t {\n unsigned int :29;\n unsigned int ulbt : 3;\n} avr32_hmatrix_mcfg_t;\n\n\n\ntypedef struct avr32_hmatrix_scfg_t {\n unsigned int : 7;\n unsigned int arbt : 1;\n unsigned int : 2;\n unsigned int fixed_defmstr : 4;\n unsigned int defmstr_type : 2;\n unsigned int : 8;\n unsigned int slot_cycle : 8;\n} avr32_hmatrix_scfg_t;\n\n\n\ntypedef struct avr32_hmatrix_pras_t {\n unsigned int m7pr : 4;\n unsigned int m6pr : 4;\n unsigned int m5pr : 4;\n unsigned int m4pr : 4;\n unsigned int m3pr : 4;\n unsigned int m2pr : 4;\n unsigned int m1pr : 4;\n unsigned int m0pr : 4;\n} avr32_hmatrix_pras_t;\n\n\n\ntypedef struct avr32_hmatrix_prbs_t {\n unsigned int m15pr : 4;\n unsigned int m14pr : 4;\n unsigned int m13pr : 4;\n unsigned int m12pr : 4;\n unsigned int m11pr : 4;\n unsigned int m10pr : 4;\n unsigned int m9pr : 4;\n unsigned int m8pr : 4;\n} avr32_hmatrix_prbs_t;\n\n\n\ntypedef struct avr32_hmatrix_mrcr_t {\n unsigned int :16;\n unsigned int rcb15 : 1;\n unsigned int rcb14 : 1;\n unsigned int rcb13 : 1;\n unsigned int rcb12 : 1;\n unsigned int rcb11 : 1;\n unsigned int rcb10 : 1;\n unsigned int rcb9 : 1;\n unsigned int rcb8 : 1;\n unsigned int rcb7 : 1;\n unsigned int rcb6 : 1;\n unsigned int rcb5 : 1;\n unsigned int rcb4 : 1;\n unsigned int rcb3 : 1;\n unsigned int rcb2 : 1;\n unsigned int rcb1 : 1;\n unsigned int rcb0 : 1;\n} avr32_hmatrix_mrcr_t;\n\n\n\ntypedef struct avr32_hmatrix_version_t {\n unsigned int :13;\n unsigned int variant : 3;\n unsigned int : 4;\n unsigned int version :12;\n} avr32_hmatrix_version_t;\n\n\ntypedef struct avr32_hmatrix_prs_t {\n union {\n unsigned long pras ;//0x0000\n avr32_hmatrix_pras_t PRAS ;\n };\n union {\n unsigned long prbs ;//0x0004\n avr32_hmatrix_prbs_t PRBS ;\n };\n} avr32_hmatrix_prs_t;\n\n\ntypedef struct avr32_hmatrix_t {\n union {\n unsigned long mcfg [16];//0x0000\n avr32_hmatrix_mcfg_t MCFG [16];\n };\n union {\n unsigned long scfg [16];//0x0040\n avr32_hmatrix_scfg_t SCFG [16];\n };\n avr32_hmatrix_prs_t prs[16];//0x80\n union {\n unsigned long mrcr ;//0x0100\n avr32_hmatrix_mrcr_t MRCR ;\n };\n unsigned int :32 ;//0x0104\n unsigned int :32 ;//0x0108\n unsigned int :32 ;//0x010c\n unsigned long sfr [16];//0x0110\n unsigned int :32 ;//0x0150\n unsigned int :32 ;//0x0154\n unsigned int :32 ;//0x0158\n unsigned int :32 ;//0x015c\n unsigned int :32 ;//0x0160\n unsigned int :32 ;//0x0164\n unsigned int :32 ;//0x0168\n unsigned int :32 ;//0x016c\n unsigned int :32 ;//0x0170\n unsigned int :32 ;//0x0174\n unsigned int :32 ;//0x0178\n unsigned int :32 ;//0x017c\n unsigned int :32 ;//0x0180\n unsigned int :32 ;//0x0184\n unsigned int :32 ;//0x0188\n unsigned int :32 ;//0x018c\n unsigned int :32 ;//0x0190\n unsigned int :32 ;//0x0194\n unsigned int :32 ;//0x0198\n unsigned int :32 ;//0x019c\n unsigned int :32 ;//0x01a0\n unsigned int :32 ;//0x01a4\n unsigned int :32 ;//0x01a8\n unsigned int :32 ;//0x01ac\n unsigned int :32 ;//0x01b0\n unsigned int :32 ;//0x01b4\n unsigned int :32 ;//0x01b8\n unsigned int :32 ;//0x01bc\n unsigned int :32 ;//0x01c0\n unsigned int :32 ;//0x01c4\n unsigned int :32 ;//0x01c8\n unsigned int :32 ;//0x01cc\n unsigned int :32 ;//0x01d0\n unsigned int :32 ;//0x01d4\n unsigned int :32 ;//0x01d8\n unsigned int :32 ;//0x01dc\n unsigned int :32 ;//0x01e0\n unsigned int :32 ;//0x01e4\n unsigned int :32 ;//0x01e8\n unsigned int :32 ;//0x01ec\n unsigned int :32 ;//0x01f0\n unsigned int :32 ;//0x01f4\n unsigned int :32 ;//0x01f8\n union {\n const unsigned long version ;//0x01fc\n const avr32_hmatrix_version_t VERSION ;\n };\n} avr32_hmatrix_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n/*#ifdef AVR32_HMATRIX_230_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/intc_101.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : AP7200\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_INTC_101_H_INCLUDED\n#define AVR32_INTC_101_H_INCLUDED\n\n#define AVR32_INTC_H_VERSION 101\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_INTC_\n - Bitfield mask: AVR32_INTC__\n - Bitfield offset: AVR32_INTC___OFFSET\n - Bitfield size: AVR32_INTC___SIZE\n - Bitfield values: AVR32_INTC___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_INTC_\n - Bitfield offset: AVR32_INTC__OFFSET\n - Bitfield size: AVR32_INTC__SIZE\n - Bitfield values: AVR32_INTC__\n - Bitfield values: AVR32_INTC_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_INTC_AUTOVECTOR 0\n#define AVR32_INTC_AUTOVECTOR_MASK 0x00003fff\n#define AVR32_INTC_AUTOVECTOR_OFFSET 0\n#define AVR32_INTC_AUTOVECTOR_SIZE 14\n#define AVR32_INTC_CAUSE 0\n#define AVR32_INTC_CAUSE_MASK 0x0000003f\n#define AVR32_INTC_CAUSE_OFFSET 0\n#define AVR32_INTC_CAUSE_SIZE 6\n#define AVR32_INTC_ICR 0x00000200\n#define AVR32_INTC_ICR_CAUSE 0\n#define AVR32_INTC_ICR_CAUSE_MASK 0x0000003f\n#define AVR32_INTC_ICR_CAUSE_OFFSET 0\n#define AVR32_INTC_ICR_CAUSE_SIZE 6\n#define AVR32_INTC_INT0 0x00000000\n#define AVR32_INTC_INT1 0x00000001\n#define AVR32_INTC_INT2 0x00000002\n#define AVR32_INTC_INT3 0x00000003\n#define AVR32_INTC_INTLEVEL 30\n#define AVR32_INTC_INTLEVEL_INT0 0x00000000\n#define AVR32_INTC_INTLEVEL_INT1 0x00000001\n#define AVR32_INTC_INTLEVEL_INT2 0x00000002\n#define AVR32_INTC_INTLEVEL_INT3 0x00000003\n#define AVR32_INTC_INTLEVEL_MASK 0xc0000000\n#define AVR32_INTC_INTLEVEL_OFFSET 30\n#define AVR32_INTC_INTLEVEL_SIZE 2\n#define AVR32_INTC_IPR 0x00000000\n#define AVR32_INTC_IPR_AUTOVECTOR 0\n#define AVR32_INTC_IPR_AUTOVECTOR_MASK 0x00003fff\n#define AVR32_INTC_IPR_AUTOVECTOR_OFFSET 0\n#define AVR32_INTC_IPR_AUTOVECTOR_SIZE 14\n#define AVR32_INTC_IPR_INTLEVEL 30\n#define AVR32_INTC_IPR_INTLEVEL_INT0 0x00000000\n#define AVR32_INTC_IPR_INTLEVEL_INT1 0x00000001\n#define AVR32_INTC_IPR_INTLEVEL_INT2 0x00000002\n#define AVR32_INTC_IPR_INTLEVEL_INT3 0x00000003\n#define AVR32_INTC_IPR_INTLEVEL_MASK 0xc0000000\n#define AVR32_INTC_IPR_INTLEVEL_OFFSET 30\n#define AVR32_INTC_IPR_INTLEVEL_SIZE 2\n#define AVR32_INTC_IRR 0x00000100\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_intc_ipr_t {\n unsigned int intlevel : 2;\n unsigned int :16;\n unsigned int autovector :14;\n} avr32_intc_ipr_t;\n\n\n\ntypedef struct avr32_intc_icr_t {\n unsigned int :26;\n unsigned int cause : 6;\n} avr32_intc_icr_t;\n\n\n\ntypedef struct avr32_intc_t {\n union {\n unsigned long ipr [AVR32_INTC_NUM_INT_GRPS];//0x0000\n avr32_intc_ipr_t IPR [AVR32_INTC_NUM_INT_GRPS];\n };\n union {\n unsigned long ipr_reserved[64 - AVR32_INTC_NUM_INT_GRPS];//Padding\n avr32_intc_ipr_t IPR_RESERVED[64 - AVR32_INTC_NUM_INT_GRPS];\n };\n const unsigned long irr [AVR32_INTC_NUM_INT_GRPS];//0x0100\n const unsigned long irr_reserved[64 - AVR32_INTC_NUM_INT_GRPS];//Padding\n union {\n const unsigned long icr [4];//0x0200\n const avr32_intc_icr_t ICR [4];\n };\n} avr32_intc_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n\n#if !defined (DEPRECATED_DISABLE)\n\n#define AVR32_INTC_ICR_CAUSEGRP 0\n#define AVR32_INTC_ICR_CAUSEGRP_MASK 0x0000003f\n#define AVR32_INTC_ICR_CAUSEGRP_OFFSET 0\n#define AVR32_INTC_ICR_CAUSEGRP_SIZE 6\n\n#define AVR32_INTC_INTLEV 30\n#define AVR32_INTC_INTLEV_INT0 0x00000000\n#define AVR32_INTC_INTLEV_INT1 0x00000001\n#define AVR32_INTC_INTLEV_INT2 0x00000002\n#define AVR32_INTC_INTLEV_INT3 0x00000003\n#define AVR32_INTC_INTLEV_MASK 0xc0000000\n#define AVR32_INTC_INTLEV_OFFSET 30\n#define AVR32_INTC_INTLEV_SIZE 2\n\n#define AVR32_INTC_IPR_INTLEV 30\n#define AVR32_INTC_IPR_INTLEV_INT0 0x00000000\n#define AVR32_INTC_IPR_INTLEV_INT1 0x00000001\n#define AVR32_INTC_IPR_INTLEV_INT2 0x00000002\n#define AVR32_INTC_IPR_INTLEV_INT3 0x00000003\n#define AVR32_INTC_IPR_INTLEV_MASK 0xc0000000\n#define AVR32_INTC_IPR_INTLEV_OFFSET 30\n#define AVR32_INTC_IPR_INTLEV_SIZE 2\n#define AVR32_INTC_IPR_OFFSET 0\n#define AVR32_INTC_IPR_OFFSET_MASK 0x00003fff\n#define AVR32_INTC_IPR_OFFSET_OFFSET 0\n#define AVR32_INTC_IPR_OFFSET_SIZE 14\n\n#define AVR32_INTC_OFFSET 0\n#define AVR32_INTC_OFFSET_MASK 0x00003fff\n#define AVR32_INTC_OFFSET_OFFSET 0\n#define AVR32_INTC_OFFSET_SIZE 14\n\n#endif\n\n\n/*#ifdef AVR32_INTC_101_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/io.h", "content": "#ifdef __AVR32_UC3B0256__\n#include \"uc3b0256.h\"\n#endif\n#ifdef __AVR32_UC3B0512__\n#include \"uc3b0512.h\"\n#endif" }, { "path": "firmware/mock_hardware/include/avr32/ocd_s0_130.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3000\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_OCD_S0_130_H_INCLUDED\n#define AVR32_OCD_S0_130_H_INCLUDED\n\n#define AVR32_OCD_S0_H_VERSION 130\n\n#include \"avr32/abi.h\"\n\n#define AVR32_OCD_ID \"S0\"\n\n#define AVR32_AXC 0x00000130\n#define AVR32_AXC_AXE 8\n#define AVR32_AXC_AXE_MASK 0x00000100\n#define AVR32_AXC_AXE_OFFSET 8\n#define AVR32_AXC_AXE_SIZE 1\n#define AVR32_AXC_AXO 9\n#define AVR32_AXC_AXO_MASK 0x00000200\n#define AVR32_AXC_AXO_OFFSET 9\n#define AVR32_AXC_AXO_SIZE 1\n#define AVR32_AXC_AXS 14\n#define AVR32_AXC_AXS_MASK 0x0000c000\n#define AVR32_AXC_AXS_OFFSET 14\n#define AVR32_AXC_AXS_SIZE 2\n#define AVR32_AXC_DDR 10\n#define AVR32_AXC_DDR_MASK 0x00000400\n#define AVR32_AXC_DDR_OFFSET 10\n#define AVR32_AXC_DDR_SIZE 1\n#define AVR32_AXC_DIV 0\n#define AVR32_AXC_DIV_MASK 0x0000000f\n#define AVR32_AXC_DIV_OFFSET 0\n#define AVR32_AXC_DIV_SIZE 4\n#define AVR32_AXC_LS 11\n#define AVR32_AXC_LS_MASK 0x00000800\n#define AVR32_AXC_LS_OFFSET 11\n#define AVR32_AXC_LS_SIZE 1\n#define AVR32_BWA0A 0x00000078\n#define AVR32_BWA0A_BWA 0\n#define AVR32_BWA0A_BWA_MASK 0xffffffff\n#define AVR32_BWA0A_BWA_OFFSET 0\n#define AVR32_BWA0A_BWA_SIZE 32\n#define AVR32_BWA0B 0x0000007c\n#define AVR32_BWA0B_BWA 0\n#define AVR32_BWA0B_BWA_MASK 0xffffffff\n#define AVR32_BWA0B_BWA_OFFSET 0\n#define AVR32_BWA0B_BWA_SIZE 32\n#define AVR32_BWA1A 0x00000080\n#define AVR32_BWA1A_BWA 0\n#define AVR32_BWA1A_BWA_MASK 0xffffffff\n#define AVR32_BWA1A_BWA_OFFSET 0\n#define AVR32_BWA1A_BWA_SIZE 32\n#define AVR32_BWA1B 0x00000084\n#define AVR32_BWA1B_BWA 0\n#define AVR32_BWA1B_BWA_MASK 0xffffffff\n#define AVR32_BWA1B_BWA_OFFSET 0\n#define AVR32_BWA1B_BWA_SIZE 32\n#define AVR32_BWA2A 0x00000088\n#define AVR32_BWA2A_BWA 0\n#define AVR32_BWA2A_BWA_MASK 0xffffffff\n#define AVR32_BWA2A_BWA_OFFSET 0\n#define AVR32_BWA2A_BWA_SIZE 32\n#define AVR32_BWA2B 0x0000008c\n#define AVR32_BWA2B_BWA 0\n#define AVR32_BWA2B_BWA_MASK 0xffffffff\n#define AVR32_BWA2B_BWA_OFFSET 0\n#define AVR32_BWA2B_BWA_SIZE 32\n#define AVR32_BWA3A 0x00000090\n#define AVR32_BWA3A_BWA 0\n#define AVR32_BWA3A_BWA_MASK 0xffffffff\n#define AVR32_BWA3A_BWA_OFFSET 0\n#define AVR32_BWA3A_BWA_SIZE 32\n#define AVR32_BWA3B 0x00000094\n#define AVR32_BWA3B_BWA 0\n#define AVR32_BWA3B_BWA_MASK 0xffffffff\n#define AVR32_BWA3B_BWA_OFFSET 0\n#define AVR32_BWA3B_BWA_SIZE 32\n#define AVR32_BWC0A 0x00000058\n#define AVR32_BWC0A_AME 25\n#define AVR32_BWC0A_AME_MASK 0x02000000\n#define AVR32_BWC0A_AME_OFFSET 25\n#define AVR32_BWC0A_AME_SIZE 1\n#define AVR32_BWC0A_BWE 30\n#define AVR32_BWC0A_BWE_BREAKPOINT_ENABLED 0x00000001\n#define AVR32_BWC0A_BWE_DISABLED 0x00000000\n#define AVR32_BWC0A_BWE_MASK 0xc0000000\n#define AVR32_BWC0A_BWE_OFFSET 30\n#define AVR32_BWC0A_BWE_SIZE 2\n#define AVR32_BWC0A_BWE_WATCHPOINT_ENABLED 0x00000003\n#define AVR32_BWC0A_EOC 14\n#define AVR32_BWC0A_EOC_MASK 0x00004000\n#define AVR32_BWC0A_EOC_OFFSET 14\n#define AVR32_BWC0A_EOC_SIZE 1\n#define AVR32_BWC0B 0x0000005c\n#define AVR32_BWC0B_BWE 30\n#define AVR32_BWC0B_BWE_BREAKPOINT_ENABLED 0x00000001\n#define AVR32_BWC0B_BWE_DISABLED 0x00000000\n#define AVR32_BWC0B_BWE_MASK 0xc0000000\n#define AVR32_BWC0B_BWE_OFFSET 30\n#define AVR32_BWC0B_BWE_SIZE 2\n#define AVR32_BWC0B_BWE_WATCHPOINT_ENABLED 0x00000003\n#define AVR32_BWC0B_EOC 14\n#define AVR32_BWC0B_EOC_MASK 0x00004000\n#define AVR32_BWC0B_EOC_OFFSET 14\n#define AVR32_BWC0B_EOC_SIZE 1\n#define AVR32_BWC1A 0x00000060\n#define AVR32_BWC1A_AME 25\n#define AVR32_BWC1A_AME_MASK 0x02000000\n#define AVR32_BWC1A_AME_OFFSET 25\n#define AVR32_BWC1A_AME_SIZE 1\n#define AVR32_BWC1A_BWE 30\n#define AVR32_BWC1A_BWE_BREAKPOINT_ENABLED 0x00000001\n#define AVR32_BWC1A_BWE_DISABLED 0x00000000\n#define AVR32_BWC1A_BWE_MASK 0xc0000000\n#define AVR32_BWC1A_BWE_OFFSET 30\n#define AVR32_BWC1A_BWE_SIZE 2\n#define AVR32_BWC1A_BWE_WATCHPOINT_ENABLED 0x00000003\n#define AVR32_BWC1A_EOC 14\n#define AVR32_BWC1A_EOC_MASK 0x00004000\n#define AVR32_BWC1A_EOC_OFFSET 14\n#define AVR32_BWC1A_EOC_SIZE 1\n#define AVR32_BWC1B 0x00000064\n#define AVR32_BWC1B_BWE 30\n#define AVR32_BWC1B_BWE_BREAKPOINT_ENABLED 0x00000001\n#define AVR32_BWC1B_BWE_DISABLED 0x00000000\n#define AVR32_BWC1B_BWE_MASK 0xc0000000\n#define AVR32_BWC1B_BWE_OFFSET 30\n#define AVR32_BWC1B_BWE_SIZE 2\n#define AVR32_BWC1B_BWE_WATCHPOINT_ENABLED 0x00000003\n#define AVR32_BWC1B_EOC 14\n#define AVR32_BWC1B_EOC_MASK 0x00004000\n#define AVR32_BWC1B_EOC_OFFSET 14\n#define AVR32_BWC1B_EOC_SIZE 1\n#define AVR32_BWC2A 0x00000068\n#define AVR32_BWC2A_AME 25\n#define AVR32_BWC2A_AME_MASK 0x02000000\n#define AVR32_BWC2A_AME_OFFSET 25\n#define AVR32_BWC2A_AME_SIZE 1\n#define AVR32_BWC2A_BWE 30\n#define AVR32_BWC2A_BWE_BREAKPOINT_ENABLED 0x00000001\n#define AVR32_BWC2A_BWE_DISABLED 0x00000000\n#define AVR32_BWC2A_BWE_MASK 0xc0000000\n#define AVR32_BWC2A_BWE_OFFSET 30\n#define AVR32_BWC2A_BWE_SIZE 2\n#define AVR32_BWC2A_BWE_WATCHPOINT_ENABLED 0x00000003\n#define AVR32_BWC2A_EOC 14\n#define AVR32_BWC2A_EOC_MASK 0x00004000\n#define AVR32_BWC2A_EOC_OFFSET 14\n#define AVR32_BWC2A_EOC_SIZE 1\n#define AVR32_BWC2B 0x0000006c\n#define AVR32_BWC2B_BWE 30\n#define AVR32_BWC2B_BWE_BREAKPOINT_ENABLED 0x00000001\n#define AVR32_BWC2B_BWE_DISABLED 0x00000000\n#define AVR32_BWC2B_BWE_MASK 0xc0000000\n#define AVR32_BWC2B_BWE_OFFSET 30\n#define AVR32_BWC2B_BWE_SIZE 2\n#define AVR32_BWC2B_BWE_WATCHPOINT_ENABLED 0x00000003\n#define AVR32_BWC2B_EOC 14\n#define AVR32_BWC2B_EOC_MASK 0x00004000\n#define AVR32_BWC2B_EOC_OFFSET 14\n#define AVR32_BWC2B_EOC_SIZE 1\n#define AVR32_BWC3A 0x00000070\n#define AVR32_BWC3A_BME 20\n#define AVR32_BWC3A_BME_MASK 0x00f00000\n#define AVR32_BWC3A_BME_OFFSET 20\n#define AVR32_BWC3A_BME_SIZE 4\n#define AVR32_BWC3A_BRW 28\n#define AVR32_BWC3A_BRW_ANY_ACCESS_BREAK 0x00000002\n#define AVR32_BWC3A_BRW_MASK 0x30000000\n#define AVR32_BWC3A_BRW_OFFSET 28\n#define AVR32_BWC3A_BRW_READ_BREAK 0x00000000\n#define AVR32_BWC3A_BRW_SIZE 2\n#define AVR32_BWC3A_BRW_WRITE_BREAK 0x00000001\n#define AVR32_BWC3A_BWE 30\n#define AVR32_BWC3A_BWE_BREAKPOINT_ENABLED 0x00000001\n#define AVR32_BWC3A_BWE_DISABLED 0x00000000\n#define AVR32_BWC3A_BWE_MASK 0xc0000000\n#define AVR32_BWC3A_BWE_OFFSET 30\n#define AVR32_BWC3A_BWE_SIZE 2\n#define AVR32_BWC3A_BWE_WATCHPOINT_ENABLED 0x00000003\n#define AVR32_BWC3A_BWO 16\n#define AVR32_BWC3A_BWO_BWA 0x00000002\n#define AVR32_BWC3A_BWO_BWD 0x00000001\n#define AVR32_BWC3A_BWO_MASK 0x00030000\n#define AVR32_BWC3A_BWO_OFFSET 16\n#define AVR32_BWC3A_BWO_SIZE 2\n#define AVR32_BWC3A_EOC 14\n#define AVR32_BWC3A_EOC_MASK 0x00004000\n#define AVR32_BWC3A_EOC_OFFSET 14\n#define AVR32_BWC3A_EOC_SIZE 1\n#define AVR32_BWC3A_SIZE 9\n#define AVR32_BWC3A_SIZE_BYTE_ACCESS 0x00000004\n#define AVR32_BWC3A_SIZE_DISREGARD 0x00000000\n#define AVR32_BWC3A_SIZE_HALFWORD_ACCESS 0x00000005\n#define AVR32_BWC3A_SIZE_MASK 0x00000e00\n#define AVR32_BWC3A_SIZE_OFFSET 9\n#define AVR32_BWC3A_SIZE_SIZE 3\n#define AVR32_BWC3A_SIZE_WORD_ACCESS 0x00000006\n#define AVR32_BWC3B 0x00000074\n#define AVR32_BWC3B_BME 20\n#define AVR32_BWC3B_BME_MASK 0x00f00000\n#define AVR32_BWC3B_BME_OFFSET 20\n#define AVR32_BWC3B_BME_SIZE 4\n#define AVR32_BWC3B_BRW 28\n#define AVR32_BWC3B_BRW_ANY_ACCESS_BREAK 0x00000002\n#define AVR32_BWC3B_BRW_MASK 0x30000000\n#define AVR32_BWC3B_BRW_OFFSET 28\n#define AVR32_BWC3B_BRW_READ_BREAK 0x00000000\n#define AVR32_BWC3B_BRW_SIZE 2\n#define AVR32_BWC3B_BRW_WRITE_BREAK 0x00000001\n#define AVR32_BWC3B_BWE 30\n#define AVR32_BWC3B_BWE_BREAKPOINT_ENABLED 0x00000001\n#define AVR32_BWC3B_BWE_DISABLED 0x00000000\n#define AVR32_BWC3B_BWE_MASK 0xc0000000\n#define AVR32_BWC3B_BWE_OFFSET 30\n#define AVR32_BWC3B_BWE_SIZE 2\n#define AVR32_BWC3B_BWE_WATCHPOINT_ENABLED 0x00000003\n#define AVR32_BWC3B_BWO 16\n#define AVR32_BWC3B_BWO_BWA 0x00000002\n#define AVR32_BWC3B_BWO_BWD 0x00000001\n#define AVR32_BWC3B_BWO_MASK 0x00030000\n#define AVR32_BWC3B_BWO_OFFSET 16\n#define AVR32_BWC3B_BWO_SIZE 2\n#define AVR32_BWC3B_EOC 14\n#define AVR32_BWC3B_EOC_MASK 0x00004000\n#define AVR32_BWC3B_EOC_OFFSET 14\n#define AVR32_BWC3B_EOC_SIZE 1\n#define AVR32_BWC3B_SIZE 9\n#define AVR32_BWC3B_SIZE_BYTE_ACCESS 0x00000004\n#define AVR32_BWC3B_SIZE_DISREGARD 0x00000000\n#define AVR32_BWC3B_SIZE_HALFWORD_ACCESS 0x00000005\n#define AVR32_BWC3B_SIZE_MASK 0x00000e00\n#define AVR32_BWC3B_SIZE_OFFSET 9\n#define AVR32_BWC3B_SIZE_SIZE 3\n#define AVR32_BWC3B_SIZE_WORD_ACCESS 0x00000006\n#define AVR32_BWD3A 0x00000098\n#define AVR32_BWD3A_BWD 0\n#define AVR32_BWD3A_BWD_MASK 0xffffffff\n#define AVR32_BWD3A_BWD_OFFSET 0\n#define AVR32_BWD3A_BWD_SIZE 32\n#define AVR32_BWD3B 0x0000009c\n#define AVR32_BWD3B_BWD 0\n#define AVR32_BWD3B_BWD_MASK 0xffffffff\n#define AVR32_BWD3B_BWD_OFFSET 0\n#define AVR32_BWD3B_BWD_SIZE 32\n#define AVR32_DC 0x00000008\n#define AVR32_DCCPU 0x00000110\n#define AVR32_DCCPU_DATA 0\n#define AVR32_DCCPU_DATA_MASK 0xffffffff\n#define AVR32_DCCPU_DATA_OFFSET 0\n#define AVR32_DCCPU_DATA_SIZE 32\n#define AVR32_DCEMU 0x00000114\n#define AVR32_DCEMU_DATA 0\n#define AVR32_DCEMU_DATA_MASK 0xffffffff\n#define AVR32_DCEMU_DATA_OFFSET 0\n#define AVR32_DCEMU_DATA_SIZE 32\n#define AVR32_DCSR 0x00000118\n#define AVR32_DCSR_CPUD 0\n#define AVR32_DCSR_CPUD_MASK 0x00000001\n#define AVR32_DCSR_CPUD_OFFSET 0\n#define AVR32_DCSR_CPUD_SIZE 1\n#define AVR32_DCSR_EMUD 1\n#define AVR32_DCSR_EMUD_MASK 0x00000002\n#define AVR32_DCSR_EMUD_OFFSET 1\n#define AVR32_DCSR_EMUD_SIZE 1\n#define AVR32_DC_ABORT 31\n#define AVR32_DC_ABORT_MASK 0x80000000\n#define AVR32_DC_ABORT_OFFSET 31\n#define AVR32_DC_ABORT_SIZE 1\n#define AVR32_DC_DBE 13\n#define AVR32_DC_DBE_MASK 0x00002000\n#define AVR32_DC_DBE_OFFSET 13\n#define AVR32_DC_DBE_SIZE 1\n#define AVR32_DC_DBR 12\n#define AVR32_DC_DBR_MASK 0x00001000\n#define AVR32_DC_DBR_OFFSET 12\n#define AVR32_DC_DBR_SIZE 1\n#define AVR32_DC_EIC 3\n#define AVR32_DC_EIC_BREAKPOINT 0x00000001\n#define AVR32_DC_EIC_MASK 0x00000018\n#define AVR32_DC_EIC_NOP 0x00000002\n#define AVR32_DC_EIC_OFFSET 3\n#define AVR32_DC_EIC_PROGRAM_AND_DATA_TRACE 0x00000000\n#define AVR32_DC_EIC_SIZE 2\n#define AVR32_DC_EOS 20\n#define AVR32_DC_EOS_BREAKPOINT_WATCHPOINT 0x00000002\n#define AVR32_DC_EOS_DEBUG_MODE 0x00000001\n#define AVR32_DC_EOS_MASK 0x00300000\n#define AVR32_DC_EOS_NOP 0x00000000\n#define AVR32_DC_EOS_OFFSET 20\n#define AVR32_DC_EOS_SIZE 2\n#define AVR32_DC_EOS_TXQ 0x00000003\n#define AVR32_DC_IFM 24\n#define AVR32_DC_IFM_MASK 0x01000000\n#define AVR32_DC_IFM_OFFSET 24\n#define AVR32_DC_IFM_SIZE 1\n#define AVR32_DC_IRP 23\n#define AVR32_DC_IRP_MASK 0x00800000\n#define AVR32_DC_IRP_OFFSET 23\n#define AVR32_DC_IRP_SIZE 1\n#define AVR32_DC_MM 29\n#define AVR32_DC_MM_MASK 0x20000000\n#define AVR32_DC_MM_OFFSET 29\n#define AVR32_DC_MM_SIZE 1\n#define AVR32_DC_ORP 28\n#define AVR32_DC_ORP_MASK 0x10000000\n#define AVR32_DC_ORP_OFFSET 28\n#define AVR32_DC_ORP_SIZE 1\n#define AVR32_DC_OVC 5\n#define AVR32_DC_OVC_DELAY_CPU_BTM 0x00000001\n#define AVR32_DC_OVC_DELAY_CPU_BTM_DTM 0x00000003\n#define AVR32_DC_OVC_DELAY_CPU_DTM 0x00000002\n#define AVR32_DC_OVC_MASK 0x000000e0\n#define AVR32_DC_OVC_OFFSET 5\n#define AVR32_DC_OVC_OVERRUN 0x00000000\n#define AVR32_DC_OVC_SIZE 3\n#define AVR32_DC_RES 30\n#define AVR32_DC_RES_MASK 0x40000000\n#define AVR32_DC_RES_OFFSET 30\n#define AVR32_DC_RES_SIZE 1\n#define AVR32_DC_RID 27\n#define AVR32_DC_RID_MASK 0x08000000\n#define AVR32_DC_RID_OFFSET 27\n#define AVR32_DC_RID_SIZE 1\n#define AVR32_DC_SQA 22\n#define AVR32_DC_SQA_MASK 0x00400000\n#define AVR32_DC_SQA_OFFSET 22\n#define AVR32_DC_SQA_SIZE 1\n#define AVR32_DC_SS 8\n#define AVR32_DC_SS_MASK 0x00000100\n#define AVR32_DC_SS_OFFSET 8\n#define AVR32_DC_SS_SIZE 1\n#define AVR32_DC_TM 0\n#define AVR32_DC_TM_BTM 0x00000004\n#define AVR32_DC_TM_DTM 0x00000002\n#define AVR32_DC_TM_MASK 0x00000007\n#define AVR32_DC_TM_NO_TRACE 0x00000000\n#define AVR32_DC_TM_OFFSET 0\n#define AVR32_DC_TM_OTM 0x00000001\n#define AVR32_DC_TM_SIZE 3\n#define AVR32_DC_TOZ 25\n#define AVR32_DC_TOZ_MASK 0x02000000\n#define AVR32_DC_TOZ_OFFSET 25\n#define AVR32_DC_TOZ_SIZE 1\n#define AVR32_DID 0x00000000\n#define AVR32_DID_MID 1\n#define AVR32_DID_MID_ATMEL 0x0000001f\n#define AVR32_DID_MID_MASK 0x00000ffe\n#define AVR32_DID_MID_OFFSET 1\n#define AVR32_DID_MID_SIZE 11\n#define AVR32_DID_PN 12\n#define AVR32_DID_PN_MASK 0x0ffff000\n#define AVR32_DID_PN_OFFSET 12\n#define AVR32_DID_PN_SIZE 16\n#define AVR32_DID_RN 28\n#define AVR32_DID_RN_MASK 0xf0000000\n#define AVR32_DID_RN_OFFSET 28\n#define AVR32_DID_RN_SIZE 4\n#define AVR32_DINST 0x00000104\n#define AVR32_DINST_DINST 0\n#define AVR32_DINST_DINST_MASK 0xffffffff\n#define AVR32_DINST_DINST_OFFSET 0\n#define AVR32_DINST_DINST_SIZE 32\n#define AVR32_DPC 0x00000108\n#define AVR32_DS 0x00000010\n#define AVR32_DS_BOZ 25\n#define AVR32_DS_BOZ_MASK 0x02000000\n#define AVR32_DS_BOZ_OFFSET 25\n#define AVR32_DS_BOZ_SIZE 1\n#define AVR32_DS_BP 8\n#define AVR32_DS_BP_MASK 0x0000ff00\n#define AVR32_DS_BP_OFFSET 8\n#define AVR32_DS_BP_SIZE 8\n#define AVR32_DS_DBA 26\n#define AVR32_DS_DBA_MASK 0x04000000\n#define AVR32_DS_DBA_OFFSET 26\n#define AVR32_DS_DBA_SIZE 1\n#define AVR32_DS_DBS 5\n#define AVR32_DS_DBS_MASK 0x00000020\n#define AVR32_DS_DBS_OFFSET 5\n#define AVR32_DS_DBS_SIZE 1\n#define AVR32_DS_EXB 27\n#define AVR32_DS_EXB_MASK 0x08000000\n#define AVR32_DS_EXB_OFFSET 27\n#define AVR32_DS_EXB_SIZE 1\n#define AVR32_DS_HWB 2\n#define AVR32_DS_HWB_MASK 0x00000004\n#define AVR32_DS_HWB_OFFSET 2\n#define AVR32_DS_HWB_SIZE 1\n#define AVR32_DS_INC 24\n#define AVR32_DS_INC_MASK 0x01000000\n#define AVR32_DS_INC_OFFSET 24\n#define AVR32_DS_INC_SIZE 1\n#define AVR32_DS_NTBF 28\n#define AVR32_DS_NTBF_MASK 0x10000000\n#define AVR32_DS_NTBF_OFFSET 28\n#define AVR32_DS_NTBF_SIZE 1\n#define AVR32_DS_SSS 0\n#define AVR32_DS_SSS_MASK 0x00000001\n#define AVR32_DS_SSS_OFFSET 0\n#define AVR32_DS_SSS_SIZE 1\n#define AVR32_DS_STP 4\n#define AVR32_DS_STP_MASK 0x00000010\n#define AVR32_DS_STP_OFFSET 4\n#define AVR32_DS_STP_SIZE 1\n#define AVR32_DS_SWB 1\n#define AVR32_DS_SWB_MASK 0x00000002\n#define AVR32_DS_SWB_OFFSET 1\n#define AVR32_DS_SWB_SIZE 1\n#define AVR32_DTC 0x00000034\n#define AVR32_DTC_RWT0 30\n#define AVR32_DTC_RWT0_DATA_READ 0x00000001\n#define AVR32_DTC_RWT0_DATA_READ_WRITE 0x00000003\n#define AVR32_DTC_RWT0_DATA_WRITE 0x00000002\n#define AVR32_DTC_RWT0_MASK 0xc0000000\n#define AVR32_DTC_RWT0_NO_TRACE 0x00000000\n#define AVR32_DTC_RWT0_OFFSET 30\n#define AVR32_DTC_RWT0_SIZE 2\n#define AVR32_DTC_RWT1 28\n#define AVR32_DTC_RWT1_DATA_READ 0x00000001\n#define AVR32_DTC_RWT1_DATA_READ_WRITE 0x00000003\n#define AVR32_DTC_RWT1_DATA_WRITE 0x00000002\n#define AVR32_DTC_RWT1_MASK 0x30000000\n#define AVR32_DTC_RWT1_NO_TRACE 0x00000000\n#define AVR32_DTC_RWT1_OFFSET 28\n#define AVR32_DTC_RWT1_SIZE 2\n#define AVR32_DTC_T0WP 0\n#define AVR32_DTC_T0WP_MASK 0x00000001\n#define AVR32_DTC_T0WP_OFFSET 0\n#define AVR32_DTC_T0WP_SIZE 1\n#define AVR32_DTC_T1WP 1\n#define AVR32_DTC_T1WP_MASK 0x00000002\n#define AVR32_DTC_T1WP_OFFSET 1\n#define AVR32_DTC_T1WP_SIZE 1\n#define AVR32_DTEA0 0x00000048\n#define AVR32_DTEA0_DTEA 0\n#define AVR32_DTEA0_DTEA_MASK 0xffffffff\n#define AVR32_DTEA0_DTEA_OFFSET 0\n#define AVR32_DTEA0_DTEA_SIZE 32\n#define AVR32_DTEA1 0x0000004c\n#define AVR32_DTEA1_DTEA 0\n#define AVR32_DTEA1_DTEA_MASK 0xffffffff\n#define AVR32_DTEA1_DTEA_OFFSET 0\n#define AVR32_DTEA1_DTEA_SIZE 32\n#define AVR32_DTSA0 0x00000038\n#define AVR32_DTSA0_DTSA 0\n#define AVR32_DTSA0_DTSA_MASK 0xffffffff\n#define AVR32_DTSA0_DTSA_OFFSET 0\n#define AVR32_DTSA0_DTSA_SIZE 32\n#define AVR32_DTSA1 0x0000003c\n#define AVR32_DTSA1_DTSA 0\n#define AVR32_DTSA1_DTSA_MASK 0xffffffff\n#define AVR32_DTSA1_DTSA_OFFSET 0\n#define AVR32_DTSA1_DTSA_SIZE 32\n#define AVR32_NXCFG 0x00000100\n#define AVR32_NXCFG_NXARCH 0\n#define AVR32_NXCFG_NXARCH_AVR32A 0x00000001\n#define AVR32_NXCFG_NXARCH_AVR32B 0x00000000\n#define AVR32_NXCFG_NXARCH_MASK 0x0000000f\n#define AVR32_NXCFG_NXARCH_OFFSET 0\n#define AVR32_NXCFG_NXARCH_SIZE 4\n#define AVR32_NXCFG_NXDB 12\n#define AVR32_NXCFG_NXDB_MASK 0x0000f000\n#define AVR32_NXCFG_NXDB_OFFSET 12\n#define AVR32_NXCFG_NXDB_SIZE 4\n#define AVR32_NXCFG_NXDMA 28\n#define AVR32_NXCFG_NXDMA_MASK 0x10000000\n#define AVR32_NXCFG_NXDMA_OFFSET 28\n#define AVR32_NXCFG_NXDMA_SIZE 1\n#define AVR32_NXCFG_NXDRT 24\n#define AVR32_NXCFG_NXDRT_MASK 0x01000000\n#define AVR32_NXCFG_NXDRT_OFFSET 24\n#define AVR32_NXCFG_NXDRT_SIZE 1\n#define AVR32_NXCFG_NXDTC 25\n#define AVR32_NXCFG_NXDTC_MASK 0x0e000000\n#define AVR32_NXCFG_NXDTC_OFFSET 25\n#define AVR32_NXCFG_NXDTC_SIZE 3\n#define AVR32_NXCFG_NXDWT 23\n#define AVR32_NXCFG_NXDWT_MASK 0x00800000\n#define AVR32_NXCFG_NXDWT_OFFSET 23\n#define AVR32_NXCFG_NXDWT_SIZE 1\n#define AVR32_NXCFG_NXMDO 17\n#define AVR32_NXCFG_NXMDO_MASK 0x001e0000\n#define AVR32_NXCFG_NXMDO_OFFSET 17\n#define AVR32_NXCFG_NXMDO_SIZE 4\n#define AVR32_NXCFG_NXMSEO 16\n#define AVR32_NXCFG_NXMSEO_MASK 0x00010000\n#define AVR32_NXCFG_NXMSEO_OFFSET 16\n#define AVR32_NXCFG_NXMSEO_SIZE 1\n#define AVR32_NXCFG_NXOCD 4\n#define AVR32_NXCFG_NXOCD_AVR32AP 0x00000000\n#define AVR32_NXCFG_NXOCD_AVR32UC 0x00000001\n#define AVR32_NXCFG_NXOCD_MASK 0x000000f0\n#define AVR32_NXCFG_NXOCD_OFFSET 4\n#define AVR32_NXCFG_NXOCD_SIZE 4\n#define AVR32_NXCFG_NXOT 22\n#define AVR32_NXCFG_NXOT_MASK 0x00400000\n#define AVR32_NXCFG_NXOT_OFFSET 22\n#define AVR32_NXCFG_NXOT_SIZE 1\n#define AVR32_NXCFG_NXPCB 8\n#define AVR32_NXCFG_NXPCB_MASK 0x00000f00\n#define AVR32_NXCFG_NXPCB_OFFSET 8\n#define AVR32_NXCFG_NXPCB_SIZE 4\n#define AVR32_NXCFG_NXPT 21\n#define AVR32_NXCFG_NXPT_MASK 0x00200000\n#define AVR32_NXCFG_NXPT_OFFSET 21\n#define AVR32_NXCFG_NXPT_SIZE 1\n#define AVR32_PID 0x0000011c\n#define AVR32_PID_PROCESS 0\n#define AVR32_PID_PROCESS_MASK 0xffffffff\n#define AVR32_PID_PROCESS_OFFSET 0\n#define AVR32_PID_PROCESS_SIZE 32\n#define AVR32_WT 0x0000002c\n#define AVR32_WT_DTE 20\n#define AVR32_WT_DTE_DATA_3A 0x00000006\n#define AVR32_WT_DTE_DATA_3B 0x00000007\n#define AVR32_WT_DTE_DISABLED 0x00000000\n#define AVR32_WT_DTE_MASK 0x00700000\n#define AVR32_WT_DTE_OFFSET 20\n#define AVR32_WT_DTE_PROGRAM_0B 0x00000001\n#define AVR32_WT_DTE_PROGRAM_1A 0x00000002\n#define AVR32_WT_DTE_PROGRAM_1B 0x00000003\n#define AVR32_WT_DTE_PROGRAM_2A 0x00000004\n#define AVR32_WT_DTE_PROGRAM_2B 0x00000005\n#define AVR32_WT_DTE_SIZE 3\n#define AVR32_WT_DTS 23\n#define AVR32_WT_DTS_DATA_3A 0x00000006\n#define AVR32_WT_DTS_DATA_3B 0x00000007\n#define AVR32_WT_DTS_DISABLED 0x00000000\n#define AVR32_WT_DTS_MASK 0x03800000\n#define AVR32_WT_DTS_OFFSET 23\n#define AVR32_WT_DTS_PROGRAM_0B 0x00000001\n#define AVR32_WT_DTS_PROGRAM_1A 0x00000002\n#define AVR32_WT_DTS_PROGRAM_1B 0x00000003\n#define AVR32_WT_DTS_PROGRAM_2A 0x00000004\n#define AVR32_WT_DTS_PROGRAM_2B 0x00000005\n#define AVR32_WT_DTS_SIZE 3\n#define AVR32_WT_PTE 26\n#define AVR32_WT_PTE_DATA_3A 0x00000006\n#define AVR32_WT_PTE_DATA_3B 0x00000007\n#define AVR32_WT_PTE_DISABLED 0x00000000\n#define AVR32_WT_PTE_MASK 0x1c000000\n#define AVR32_WT_PTE_OFFSET 26\n#define AVR32_WT_PTE_PROGRAM_0B 0x00000001\n#define AVR32_WT_PTE_PROGRAM_1A 0x00000002\n#define AVR32_WT_PTE_PROGRAM_1B 0x00000003\n#define AVR32_WT_PTE_PROGRAM_2A 0x00000004\n#define AVR32_WT_PTE_PROGRAM_2B 0x00000005\n#define AVR32_WT_PTE_SIZE 3\n#define AVR32_WT_PTS 29\n#define AVR32_WT_PTS_DATA_3A 0x00000006\n#define AVR32_WT_PTS_DATA_3B 0x00000007\n#define AVR32_WT_PTS_DISABLED 0x00000000\n#define AVR32_WT_PTS_MASK 0xe0000000\n#define AVR32_WT_PTS_OFFSET 29\n#define AVR32_WT_PTS_PROGRAM_0B 0x00000001\n#define AVR32_WT_PTS_PROGRAM_1A 0x00000002\n#define AVR32_WT_PTS_PROGRAM_1B 0x00000003\n#define AVR32_WT_PTS_PROGRAM_2A 0x00000004\n#define AVR32_WT_PTS_PROGRAM_2B 0x00000005\n#define AVR32_WT_PTS_SIZE 3\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_did_t {\n unsigned int rn : 4;\n unsigned int pn :16;\n unsigned int mid :11;\n unsigned int : 1;\n} avr32_did_t;\n\n\n\ntypedef struct avr32_dc_t {\n unsigned int abort : 1;\n unsigned int res : 1;\n unsigned int mm : 1;\n unsigned int orp : 1;\n unsigned int rid : 1;\n unsigned int : 1;\n unsigned int toz : 1;\n unsigned int ifm : 1;\n unsigned int irp : 1;\n unsigned int sqa : 1;\n unsigned int eos : 2;\n unsigned int : 6;\n unsigned int dbe : 1;\n unsigned int dbr : 1;\n unsigned int : 3;\n unsigned int ss : 1;\n unsigned int ovc : 3;\n unsigned int eic : 2;\n unsigned int tm : 3;\n} avr32_dc_t;\n\n\n\ntypedef struct avr32_ds_t {\n unsigned int : 3;\n unsigned int ntbf : 1;\n unsigned int exb : 1;\n unsigned int dba : 1;\n unsigned int boz : 1;\n unsigned int inc : 1;\n unsigned int : 8;\n unsigned int bp : 8;\n unsigned int : 2;\n unsigned int dbs : 1;\n unsigned int stp : 1;\n unsigned int : 1;\n unsigned int hwb : 1;\n unsigned int swb : 1;\n unsigned int sss : 1;\n} avr32_ds_t;\n\n\n\ntypedef struct avr32_wt_t {\n unsigned int pts : 3;\n unsigned int pte : 3;\n unsigned int dts : 3;\n unsigned int dte : 3;\n unsigned int :20;\n} avr32_wt_t;\n\n\n\ntypedef struct avr32_dtc_t {\n unsigned int rwt0 : 2;\n unsigned int rwt1 : 2;\n unsigned int :26;\n unsigned int t1wp : 1;\n unsigned int t0wp : 1;\n} avr32_dtc_t;\n\n\n\ntypedef struct avr32_bwc0a_t {\n unsigned int bwe : 2;\n unsigned int : 4;\n unsigned int ame : 1;\n unsigned int :10;\n unsigned int eoc : 1;\n unsigned int :14;\n} avr32_bwc0a_t;\n\n\n\ntypedef struct avr32_bwc0b_t {\n unsigned int bwe : 2;\n unsigned int :15;\n unsigned int eoc : 1;\n unsigned int :14;\n} avr32_bwc0b_t;\n\n\n\ntypedef struct avr32_bwc1a_t {\n unsigned int bwe : 2;\n unsigned int : 4;\n unsigned int ame : 1;\n unsigned int :10;\n unsigned int eoc : 1;\n unsigned int :14;\n} avr32_bwc1a_t;\n\n\n\ntypedef struct avr32_bwc1b_t {\n unsigned int bwe : 2;\n unsigned int :15;\n unsigned int eoc : 1;\n unsigned int :14;\n} avr32_bwc1b_t;\n\n\n\ntypedef struct avr32_bwc2a_t {\n unsigned int bwe : 2;\n unsigned int : 4;\n unsigned int ame : 1;\n unsigned int :10;\n unsigned int eoc : 1;\n unsigned int :14;\n} avr32_bwc2a_t;\n\n\n\ntypedef struct avr32_bwc2b_t {\n unsigned int bwe : 2;\n unsigned int :15;\n unsigned int eoc : 1;\n unsigned int :14;\n} avr32_bwc2b_t;\n\n\n\ntypedef struct avr32_bwc3a_t {\n unsigned int bwe : 2;\n unsigned int brw : 2;\n unsigned int : 4;\n unsigned int bme : 4;\n unsigned int : 2;\n unsigned int bwo : 2;\n unsigned int : 1;\n unsigned int eoc : 1;\n unsigned int : 2;\n unsigned int size : 3;\n unsigned int : 9;\n} avr32_bwc3a_t;\n\n\n\ntypedef struct avr32_bwc3b_t {\n unsigned int bwe : 2;\n unsigned int brw : 2;\n unsigned int : 4;\n unsigned int bme : 4;\n unsigned int : 2;\n unsigned int bwo : 2;\n unsigned int : 1;\n unsigned int eoc : 1;\n unsigned int : 2;\n unsigned int size : 3;\n unsigned int : 9;\n} avr32_bwc3b_t;\n\n\n\ntypedef struct avr32_nxcfg_t {\n unsigned int : 3;\n unsigned int nxdma : 1;\n unsigned int nxdtc : 3;\n unsigned int nxdrt : 1;\n unsigned int nxdwt : 1;\n unsigned int nxot : 1;\n unsigned int nxpt : 1;\n unsigned int nxmdo : 4;\n unsigned int nxmseo : 1;\n unsigned int nxdb : 4;\n unsigned int nxpcb : 4;\n unsigned int nxocd : 4;\n unsigned int nxarch : 4;\n} avr32_nxcfg_t;\n\n\n\ntypedef struct avr32_dcsr_t {\n unsigned int :30;\n unsigned int emud : 1;\n unsigned int cpud : 1;\n} avr32_dcsr_t;\n\n\n\ntypedef struct avr32_axc_t {\n unsigned int :16;\n unsigned int axs : 2;\n unsigned int : 2;\n unsigned int ls : 1;\n unsigned int ddr : 1;\n unsigned int axo : 1;\n unsigned int axe : 1;\n unsigned int : 4;\n unsigned int div : 4;\n} avr32_axc_t;\n\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n\n#if !defined (DEPRECATED_DISABLE)\n\n#define AVR32_BWC3A_BRW_ANY_ACCES_BREAK 0x00000002\n\n#define AVR32_BWC3B_BRW_ANY_ACCES_BREAK 0x00000002\n\n#define AVR32_BWD3A_BITFIELD_0 0\n#define AVR32_BWD3A_BITFIELD_0_MASK 0xffffffff\n#define AVR32_BWD3A_BITFIELD_0_OFFSET 0\n#define AVR32_BWD3A_BITFIELD_0_SIZE 32\n\n#define AVR32_DC_EOS_THQ 0x00000003\n\n#define AVR32_NXCFG_MXMSEO 16\n#define AVR32_NXCFG_MXMSEO_MASK 0x00010000\n#define AVR32_NXCFG_MXMSEO_OFFSET 16\n#define AVR32_NXCFG_MXMSEO_SIZE 1\n\n#endif\n\n/*#ifdef AVR32_OCD_S0_130_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/pdca_102.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3A0512\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_PDCA_102_H_INCLUDED\n#define AVR32_PDCA_102_H_INCLUDED\n\n#define AVR32_PDCA_H_VERSION 102\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_PDCA_\n - Bitfield mask: AVR32_PDCA__\n - Bitfield offset: AVR32_PDCA___OFFSET\n - Bitfield size: AVR32_PDCA___SIZE\n - Bitfield values: AVR32_PDCA___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_PDCA_\n - Bitfield offset: AVR32_PDCA__OFFSET\n - Bitfield size: AVR32_PDCA__SIZE\n - Bitfield values: AVR32_PDCA__\n - Bitfield values: AVR32_PDCA_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_PDCA_BYTE 0x00000000\n#define AVR32_PDCA_CR 0x00000014\n#define AVR32_PDCA_CR_ECLR 8\n#define AVR32_PDCA_CR_ECLR_MASK 0x00000100\n#define AVR32_PDCA_CR_ECLR_OFFSET 8\n#define AVR32_PDCA_CR_ECLR_SIZE 1\n#define AVR32_PDCA_CR_TDIS 1\n#define AVR32_PDCA_CR_TDIS_MASK 0x00000002\n#define AVR32_PDCA_CR_TDIS_OFFSET 1\n#define AVR32_PDCA_CR_TDIS_SIZE 1\n#define AVR32_PDCA_CR_TEN 0\n#define AVR32_PDCA_CR_TEN_MASK 0x00000001\n#define AVR32_PDCA_CR_TEN_OFFSET 0\n#define AVR32_PDCA_CR_TEN_SIZE 1\n#define AVR32_PDCA_ECLR 8\n#define AVR32_PDCA_ECLR_MASK 0x00000100\n#define AVR32_PDCA_ECLR_OFFSET 8\n#define AVR32_PDCA_ECLR_SIZE 1\n#define AVR32_PDCA_HALF_WORD 0x00000001\n#define AVR32_PDCA_IDR 0x00000024\n#define AVR32_PDCA_IDR_RCZ 0\n#define AVR32_PDCA_IDR_RCZ_MASK 0x00000001\n#define AVR32_PDCA_IDR_RCZ_OFFSET 0\n#define AVR32_PDCA_IDR_RCZ_SIZE 1\n#define AVR32_PDCA_IDR_TERR 2\n#define AVR32_PDCA_IDR_TERR_MASK 0x00000004\n#define AVR32_PDCA_IDR_TERR_OFFSET 2\n#define AVR32_PDCA_IDR_TERR_SIZE 1\n#define AVR32_PDCA_IDR_TRC 1\n#define AVR32_PDCA_IDR_TRC_MASK 0x00000002\n#define AVR32_PDCA_IDR_TRC_OFFSET 1\n#define AVR32_PDCA_IDR_TRC_SIZE 1\n#define AVR32_PDCA_IER 0x00000020\n#define AVR32_PDCA_IER_RCZ 0\n#define AVR32_PDCA_IER_RCZ_MASK 0x00000001\n#define AVR32_PDCA_IER_RCZ_OFFSET 0\n#define AVR32_PDCA_IER_RCZ_SIZE 1\n#define AVR32_PDCA_IER_TERR 2\n#define AVR32_PDCA_IER_TERR_MASK 0x00000004\n#define AVR32_PDCA_IER_TERR_OFFSET 2\n#define AVR32_PDCA_IER_TERR_SIZE 1\n#define AVR32_PDCA_IER_TRC 1\n#define AVR32_PDCA_IER_TRC_MASK 0x00000002\n#define AVR32_PDCA_IER_TRC_OFFSET 1\n#define AVR32_PDCA_IER_TRC_SIZE 1\n#define AVR32_PDCA_IMR 0x00000028\n#define AVR32_PDCA_IMR_RCZ 0\n#define AVR32_PDCA_IMR_RCZ_MASK 0x00000001\n#define AVR32_PDCA_IMR_RCZ_OFFSET 0\n#define AVR32_PDCA_IMR_RCZ_SIZE 1\n#define AVR32_PDCA_IMR_TERR 2\n#define AVR32_PDCA_IMR_TERR_MASK 0x00000004\n#define AVR32_PDCA_IMR_TERR_OFFSET 2\n#define AVR32_PDCA_IMR_TERR_SIZE 1\n#define AVR32_PDCA_IMR_TRC 1\n#define AVR32_PDCA_IMR_TRC_MASK 0x00000002\n#define AVR32_PDCA_IMR_TRC_OFFSET 1\n#define AVR32_PDCA_IMR_TRC_SIZE 1\n#define AVR32_PDCA_ISR 0x0000002c\n#define AVR32_PDCA_ISR_RCZ 0\n#define AVR32_PDCA_ISR_RCZ_MASK 0x00000001\n#define AVR32_PDCA_ISR_RCZ_OFFSET 0\n#define AVR32_PDCA_ISR_RCZ_SIZE 1\n#define AVR32_PDCA_ISR_TERR 2\n#define AVR32_PDCA_ISR_TERR_MASK 0x00000004\n#define AVR32_PDCA_ISR_TERR_OFFSET 2\n#define AVR32_PDCA_ISR_TERR_SIZE 1\n#define AVR32_PDCA_ISR_TRC 1\n#define AVR32_PDCA_ISR_TRC_MASK 0x00000002\n#define AVR32_PDCA_ISR_TRC_OFFSET 1\n#define AVR32_PDCA_ISR_TRC_SIZE 1\n#define AVR32_PDCA_MADDR 0\n#define AVR32_PDCA_MADDR_MASK 0xffffffff\n#define AVR32_PDCA_MADDR_OFFSET 0\n#define AVR32_PDCA_MADDR_SIZE 32\n#define AVR32_PDCA_MAR 0x00000000\n#define AVR32_PDCA_MAR_MADDR 0\n#define AVR32_PDCA_MAR_MADDR_MASK 0xffffffff\n#define AVR32_PDCA_MAR_MADDR_OFFSET 0\n#define AVR32_PDCA_MAR_MADDR_SIZE 32\n#define AVR32_PDCA_MARR 0x0000000c\n#define AVR32_PDCA_MARR_MARV 0\n#define AVR32_PDCA_MARR_MARV_MASK 0xffffffff\n#define AVR32_PDCA_MARR_MARV_OFFSET 0\n#define AVR32_PDCA_MARR_MARV_SIZE 32\n#define AVR32_PDCA_MARV 0\n#define AVR32_PDCA_MARV_MASK 0xffffffff\n#define AVR32_PDCA_MARV_OFFSET 0\n#define AVR32_PDCA_MARV_SIZE 32\n#define AVR32_PDCA_MR 0x00000018\n#define AVR32_PDCA_MR_SIZE 0\n#define AVR32_PDCA_MR_SIZE_BYTE 0x00000000\n#define AVR32_PDCA_MR_SIZE_HALF_WORD 0x00000001\n#define AVR32_PDCA_MR_SIZE_MASK 0x00000003\n#define AVR32_PDCA_MR_SIZE_OFFSET 0\n#define AVR32_PDCA_MR_SIZE_SIZE 2\n#define AVR32_PDCA_MR_SIZE_WORD 0x00000002\n#define AVR32_PDCA_PID 0\n#define AVR32_PDCA_PID_MASK 0x000000ff\n#define AVR32_PDCA_PID_OFFSET 0\n#define AVR32_PDCA_PID_SIZE 8\n#define AVR32_PDCA_PSR 0x00000004\n#define AVR32_PDCA_PSR_PID 0\n#define AVR32_PDCA_PSR_PID_MASK 0x000000ff\n#define AVR32_PDCA_PSR_PID_OFFSET 0\n#define AVR32_PDCA_PSR_PID_SIZE 8\n#define AVR32_PDCA_RCZ 0\n#define AVR32_PDCA_RCZ_MASK 0x00000001\n#define AVR32_PDCA_RCZ_OFFSET 0\n#define AVR32_PDCA_RCZ_SIZE 1\n#define AVR32_PDCA_SIZE 0\n#define AVR32_PDCA_SIZE_BYTE 0x00000000\n#define AVR32_PDCA_SIZE_HALF_WORD 0x00000001\n#define AVR32_PDCA_SIZE_MASK 0x00000003\n#define AVR32_PDCA_SIZE_OFFSET 0\n#define AVR32_PDCA_SIZE_SIZE 2\n#define AVR32_PDCA_SIZE_WORD 0x00000002\n#define AVR32_PDCA_SR 0x0000001c\n#define AVR32_PDCA_SR_TEN 0\n#define AVR32_PDCA_SR_TEN_MASK 0x00000001\n#define AVR32_PDCA_SR_TEN_OFFSET 0\n#define AVR32_PDCA_SR_TEN_SIZE 1\n#define AVR32_PDCA_TCR 0x00000008\n#define AVR32_PDCA_TCR_TCV 0\n#define AVR32_PDCA_TCR_TCV_MASK 0x0000ffff\n#define AVR32_PDCA_TCR_TCV_OFFSET 0\n#define AVR32_PDCA_TCR_TCV_SIZE 16\n#define AVR32_PDCA_TCRR 0x00000010\n#define AVR32_PDCA_TCRR_TCRV 0\n#define AVR32_PDCA_TCRR_TCRV_MASK 0x0000ffff\n#define AVR32_PDCA_TCRR_TCRV_OFFSET 0\n#define AVR32_PDCA_TCRR_TCRV_SIZE 16\n#define AVR32_PDCA_TCRV 0\n#define AVR32_PDCA_TCRV_MASK 0x0000ffff\n#define AVR32_PDCA_TCRV_OFFSET 0\n#define AVR32_PDCA_TCRV_SIZE 16\n#define AVR32_PDCA_TCV 0\n#define AVR32_PDCA_TCV_MASK 0x0000ffff\n#define AVR32_PDCA_TCV_OFFSET 0\n#define AVR32_PDCA_TCV_SIZE 16\n#define AVR32_PDCA_TDIS 1\n#define AVR32_PDCA_TDIS_MASK 0x00000002\n#define AVR32_PDCA_TDIS_OFFSET 1\n#define AVR32_PDCA_TDIS_SIZE 1\n#define AVR32_PDCA_TEN 0\n#define AVR32_PDCA_TEN_MASK 0x00000001\n#define AVR32_PDCA_TEN_OFFSET 0\n#define AVR32_PDCA_TEN_SIZE 1\n#define AVR32_PDCA_TERR 2\n#define AVR32_PDCA_TERR_MASK 0x00000004\n#define AVR32_PDCA_TERR_OFFSET 2\n#define AVR32_PDCA_TERR_SIZE 1\n#define AVR32_PDCA_TRC 1\n#define AVR32_PDCA_TRC_MASK 0x00000002\n#define AVR32_PDCA_TRC_OFFSET 1\n#define AVR32_PDCA_TRC_SIZE 1\n#define AVR32_PDCA_WORD 0x00000002\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_pdca_psr_t {\n unsigned int :24;\n unsigned int pid : 8;\n} avr32_pdca_psr_t;\n\n\n\ntypedef struct avr32_pdca_tcr_t {\n unsigned int :16;\n unsigned int tcv :16;\n} avr32_pdca_tcr_t;\n\n\n\ntypedef struct avr32_pdca_tcrr_t {\n unsigned int :16;\n unsigned int tcrv :16;\n} avr32_pdca_tcrr_t;\n\n\n\ntypedef struct avr32_pdca_cr_t {\n unsigned int :23;\n unsigned int eclr : 1;\n unsigned int : 6;\n unsigned int tdis : 1;\n unsigned int ten : 1;\n} avr32_pdca_cr_t;\n\n\n\ntypedef struct avr32_pdca_mr_t {\n unsigned int :30;\n unsigned int size : 2;\n} avr32_pdca_mr_t;\n\n\n\ntypedef struct avr32_pdca_sr_t {\n unsigned int :31;\n unsigned int ten : 1;\n} avr32_pdca_sr_t;\n\n\n\ntypedef struct avr32_pdca_ier_t {\n unsigned int :29;\n unsigned int terr : 1;\n unsigned int trc : 1;\n unsigned int rcz : 1;\n} avr32_pdca_ier_t;\n\n\n\ntypedef struct avr32_pdca_idr_t {\n unsigned int :29;\n unsigned int terr : 1;\n unsigned int trc : 1;\n unsigned int rcz : 1;\n} avr32_pdca_idr_t;\n\n\n\ntypedef struct avr32_pdca_imr_t {\n unsigned int :29;\n unsigned int terr : 1;\n unsigned int trc : 1;\n unsigned int rcz : 1;\n} avr32_pdca_imr_t;\n\n\n\ntypedef struct avr32_pdca_isr_t {\n unsigned int :29;\n unsigned int terr : 1;\n unsigned int trc : 1;\n unsigned int rcz : 1;\n} avr32_pdca_isr_t;\n\n\ntypedef struct avr32_pdca_channel_t {\n unsigned long mar ;//0x0000\n union {\n unsigned long psr ;//0x0004\n avr32_pdca_psr_t PSR ;\n };\n union {\n unsigned long tcr ;//0x0008\n avr32_pdca_tcr_t TCR ;\n };\n unsigned long marr ;//0x000c\n union {\n unsigned long tcrr ;//0x0010\n avr32_pdca_tcrr_t TCRR ;\n };\n union {\n unsigned long cr ;//0x0014\n avr32_pdca_cr_t CR ;\n };\n union {\n unsigned long mr ;//0x0018\n avr32_pdca_mr_t MR ;\n };\n union {\n const unsigned long sr ;//0x001c\n const avr32_pdca_sr_t SR ;\n };\n union {\n unsigned long ier ;//0x0020\n avr32_pdca_ier_t IER ;\n };\n union {\n unsigned long idr ;//0x0024\n avr32_pdca_idr_t IDR ;\n };\n union {\n const unsigned long imr ;//0x0028\n const avr32_pdca_imr_t IMR ;\n };\n union {\n const unsigned long isr ;//0x002c\n const avr32_pdca_isr_t ISR ;\n };\n unsigned int :32 ;//0x0030\n unsigned int :32 ;//0x0034\n unsigned int :32 ;//0x0038\n unsigned int :32 ;//0x003c\n} avr32_pdca_channel_t;\n\n\ntypedef struct avr32_pdca_t {\n avr32_pdca_channel_t channel[AVR32_PDCA_CHANNEL_LENGTH];//0x0\n} avr32_pdca_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n\n#if !defined (DEPRECATED_DISABLE)\n\n#define AVR32_PDCA_CR0 0x00000014\n#define AVR32_PDCA_CR0_ECLR 8\n#define AVR32_PDCA_CR0_ECLR_MASK 0x00000100\n#define AVR32_PDCA_CR0_ECLR_OFFSET 8\n#define AVR32_PDCA_CR0_ECLR_SIZE 1\n#define AVR32_PDCA_CR0_TDIS 1\n#define AVR32_PDCA_CR0_TDIS_MASK 0x00000002\n#define AVR32_PDCA_CR0_TDIS_OFFSET 1\n#define AVR32_PDCA_CR0_TDIS_SIZE 1\n#define AVR32_PDCA_CR0_TEN 0\n#define AVR32_PDCA_CR0_TEN_MASK 0x00000001\n#define AVR32_PDCA_CR0_TEN_OFFSET 0\n#define AVR32_PDCA_CR0_TEN_SIZE 1\n\n#define AVR32_PDCA_IDR0 0x00000024\n#define AVR32_PDCA_IDR0_RCZ 0\n#define AVR32_PDCA_IDR0_RCZ_MASK 0x00000001\n#define AVR32_PDCA_IDR0_RCZ_OFFSET 0\n#define AVR32_PDCA_IDR0_RCZ_SIZE 1\n#define AVR32_PDCA_IDR0_TERR 2\n#define AVR32_PDCA_IDR0_TERR_MASK 0x00000004\n#define AVR32_PDCA_IDR0_TERR_OFFSET 2\n#define AVR32_PDCA_IDR0_TERR_SIZE 1\n#define AVR32_PDCA_IDR0_TRC 1\n#define AVR32_PDCA_IDR0_TRC_MASK 0x00000002\n#define AVR32_PDCA_IDR0_TRC_OFFSET 1\n#define AVR32_PDCA_IDR0_TRC_SIZE 1\n\n#define AVR32_PDCA_IER0 0x00000020\n#define AVR32_PDCA_IER0_RCZ 0\n#define AVR32_PDCA_IER0_RCZ_MASK 0x00000001\n#define AVR32_PDCA_IER0_RCZ_OFFSET 0\n#define AVR32_PDCA_IER0_RCZ_SIZE 1\n#define AVR32_PDCA_IER0_TERR 2\n#define AVR32_PDCA_IER0_TERR_MASK 0x00000004\n#define AVR32_PDCA_IER0_TERR_OFFSET 2\n#define AVR32_PDCA_IER0_TERR_SIZE 1\n#define AVR32_PDCA_IER0_TRC 1\n#define AVR32_PDCA_IER0_TRC_MASK 0x00000002\n#define AVR32_PDCA_IER0_TRC_OFFSET 1\n#define AVR32_PDCA_IER0_TRC_SIZE 1\n\n#define AVR32_PDCA_IMR0 0x00000028\n#define AVR32_PDCA_IMR0_RCZ 0\n#define AVR32_PDCA_IMR0_RCZ_MASK 0x00000001\n#define AVR32_PDCA_IMR0_RCZ_OFFSET 0\n#define AVR32_PDCA_IMR0_RCZ_SIZE 1\n#define AVR32_PDCA_IMR0_TERR 2\n#define AVR32_PDCA_IMR0_TERR_MASK 0x00000004\n#define AVR32_PDCA_IMR0_TERR_OFFSET 2\n#define AVR32_PDCA_IMR0_TERR_SIZE 1\n#define AVR32_PDCA_IMR0_TRC 1\n#define AVR32_PDCA_IMR0_TRC_MASK 0x00000002\n#define AVR32_PDCA_IMR0_TRC_OFFSET 1\n#define AVR32_PDCA_IMR0_TRC_SIZE 1\n\n#define AVR32_PDCA_ISR0 0x0000002c\n#define AVR32_PDCA_ISR0_RCZ 0\n#define AVR32_PDCA_ISR0_RCZ_MASK 0x00000001\n#define AVR32_PDCA_ISR0_RCZ_OFFSET 0\n#define AVR32_PDCA_ISR0_RCZ_SIZE 1\n#define AVR32_PDCA_ISR0_TERR 2\n#define AVR32_PDCA_ISR0_TERR_MASK 0x00000004\n#define AVR32_PDCA_ISR0_TERR_OFFSET 2\n#define AVR32_PDCA_ISR0_TERR_SIZE 1\n#define AVR32_PDCA_ISR0_TRC 1\n#define AVR32_PDCA_ISR0_TRC_MASK 0x00000002\n#define AVR32_PDCA_ISR0_TRC_OFFSET 1\n#define AVR32_PDCA_ISR0_TRC_SIZE 1\n\n#define AVR32_PDCA_MAR0 0x00000000\n#define AVR32_PDCA_MAR0_MADDR 0\n#define AVR32_PDCA_MAR0_MADDR_MASK 0xffffffff\n#define AVR32_PDCA_MAR0_MADDR_OFFSET 0\n#define AVR32_PDCA_MAR0_MADDR_SIZE 32\n\n#define AVR32_PDCA_MARR0 0x0000000c\n#define AVR32_PDCA_MARR0_MARV 0\n#define AVR32_PDCA_MARR0_MARV_MASK 0xffffffff\n#define AVR32_PDCA_MARR0_MARV_OFFSET 0\n#define AVR32_PDCA_MARR0_MARV_SIZE 32\n\n#define AVR32_PDCA_MR0 0x00000018\n#define AVR32_PDCA_MR0_SIZE 0\n#define AVR32_PDCA_MR0_SIZE_BYTE 0x00000000\n#define AVR32_PDCA_MR0_SIZE_HALF_WORD 0x00000001\n#define AVR32_PDCA_MR0_SIZE_MASK 0x00000003\n#define AVR32_PDCA_MR0_SIZE_OFFSET 0\n#define AVR32_PDCA_MR0_SIZE_SIZE 2\n#define AVR32_PDCA_MR0_SIZE_WORD 0x00000002\n\n#define AVR32_PDCA_PSR0 0x00000004\n#define AVR32_PDCA_PSR0_PID 0\n#define AVR32_PDCA_PSR0_PID_MASK 0x000000ff\n#define AVR32_PDCA_PSR0_PID_OFFSET 0\n#define AVR32_PDCA_PSR0_PID_SIZE 8\n\n#define AVR32_PDCA_SR0 0x0000001c\n#define AVR32_PDCA_SR0_TEN 0\n#define AVR32_PDCA_SR0_TEN_MASK 0x00000001\n#define AVR32_PDCA_SR0_TEN_OFFSET 0\n#define AVR32_PDCA_SR0_TEN_SIZE 1\n\n#define AVR32_PDCA_TCR0 0x00000008\n#define AVR32_PDCA_TCR0_TCV 0\n#define AVR32_PDCA_TCR0_TCV_MASK 0x0000ffff\n#define AVR32_PDCA_TCR0_TCV_OFFSET 0\n#define AVR32_PDCA_TCR0_TCV_SIZE 16\n\n#define AVR32_PDCA_TCRR0 0x00000010\n#define AVR32_PDCA_TCRR0_TCRV 0\n#define AVR32_PDCA_TCRR0_TCRV_MASK 0x0000ffff\n#define AVR32_PDCA_TCRR0_TCRV_OFFSET 0\n#define AVR32_PDCA_TCRR0_TCRV_SIZE 16\n\n#endif\n\n\n/*#ifdef AVR32_PDCA_102_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/pm_230.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3A0512\n * Revision : $Revision: 74808 $\n * Checkin Date : $Date: 2010-05-16 22:06:32 +0200 (Sun, 16 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_PM_230_H_INCLUDED\n#define AVR32_PM_230_H_INCLUDED\n\n#define AVR32_PM_H_VERSION 230\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_PM_\n - Bitfield mask: AVR32_PM__\n - Bitfield offset: AVR32_PM___OFFSET\n - Bitfield size: AVR32_PM___SIZE\n - Bitfield values: AVR32_PM___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_PM_\n - Bitfield offset: AVR32_PM__OFFSET\n - Bitfield size: AVR32_PM__SIZE\n - Bitfield values: AVR32_PM__\n - Bitfield values: AVR32_PM_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_PM_AWEN 0x00000144\n#define AVR32_PM_AWEN_USB_WAKEN 0\n#define AVR32_PM_AWEN_USB_WAKEN_MASK 0x00000001\n#define AVR32_PM_AWEN_USB_WAKEN_OFFSET 0\n#define AVR32_PM_AWEN_USB_WAKEN_SIZE 1\n#define AVR32_PM_BGCR 0x000000c4\n#define AVR32_PM_BGCR_CALIB 0\n#define AVR32_PM_BGCR_CALIB_MASK 0x00000007\n#define AVR32_PM_BGCR_CALIB_OFFSET 0\n#define AVR32_PM_BGCR_CALIB_SIZE 3\n#define AVR32_PM_BGCR_FCD 16\n#define AVR32_PM_BGCR_FCD_MASK 0x00010000\n#define AVR32_PM_BGCR_FCD_OFFSET 16\n#define AVR32_PM_BGCR_FCD_SIZE 1\n#define AVR32_PM_BGCR_KEY 24\n#define AVR32_PM_BGCR_KEY_MASK 0xff000000\n#define AVR32_PM_BGCR_KEY_OFFSET 24\n#define AVR32_PM_BGCR_KEY_SIZE 8\n#define AVR32_PM_BOD 0x000000d0\n#define AVR32_PM_BODDET 16\n#define AVR32_PM_BODDET_MASK 0x00010000\n#define AVR32_PM_BODDET_OFFSET 16\n#define AVR32_PM_BODDET_SIZE 1\n#define AVR32_PM_BOD_CTRL 8\n#define AVR32_PM_BOD_CTRL_ENABLED 0x00000001\n#define AVR32_PM_BOD_CTRL_ENABLED_NORESET 0x00000002\n#define AVR32_PM_BOD_CTRL_MASK 0x00000300\n#define AVR32_PM_BOD_CTRL_OFF1 0x00000000\n#define AVR32_PM_BOD_CTRL_OFF2 0x00000003\n#define AVR32_PM_BOD_CTRL_OFFSET 8\n#define AVR32_PM_BOD_CTRL_SIZE 2\n#define AVR32_PM_BOD_FCD 16\n#define AVR32_PM_BOD_FCD_MASK 0x00010000\n#define AVR32_PM_BOD_FCD_OFFSET 16\n#define AVR32_PM_BOD_FCD_SIZE 1\n#define AVR32_PM_BOD_HYST 6\n#define AVR32_PM_BOD_HYST_MASK 0x00000040\n#define AVR32_PM_BOD_HYST_OFFSET 6\n#define AVR32_PM_BOD_HYST_SIZE 1\n#define AVR32_PM_BOD_KEY 24\n#define AVR32_PM_BOD_KEY_MASK 0xff000000\n#define AVR32_PM_BOD_KEY_OFFSET 24\n#define AVR32_PM_BOD_KEY_SIZE 8\n#define AVR32_PM_BOD_LEVEL 0\n#define AVR32_PM_BOD_LEVEL_MASK 0x0000003f\n#define AVR32_PM_BOD_LEVEL_OFFSET 0\n#define AVR32_PM_BOD_LEVEL_SIZE 6\n#define AVR32_PM_BOD_MASK 0x00000002\n#define AVR32_PM_BOD_OFFSET 1\n#define AVR32_PM_BOD_SIZE 1\n#define AVR32_PM_CALIB 0\n#define AVR32_PM_CALIB_OFFSET 0\n#define AVR32_PM_CEN 2\n#define AVR32_PM_CEN_MASK 0x00000004\n#define AVR32_PM_CEN_OFFSET 2\n#define AVR32_PM_CEN_SIZE 1\n#define AVR32_PM_CKRDY 5\n#define AVR32_PM_CKRDY_MASK 0x00000020\n#define AVR32_PM_CKRDY_OFFSET 5\n#define AVR32_PM_CKRDY_SIZE 1\n#define AVR32_PM_CKSEL 0x00000004\n#define AVR32_PM_CKSEL_CPUDIV 7\n#define AVR32_PM_CKSEL_CPUDIV_MASK 0x00000080\n#define AVR32_PM_CKSEL_CPUDIV_OFFSET 7\n#define AVR32_PM_CKSEL_CPUDIV_SIZE 1\n#define AVR32_PM_CKSEL_CPUSEL 0\n#define AVR32_PM_CKSEL_CPUSEL_MASK 0x00000007\n#define AVR32_PM_CKSEL_CPUSEL_OFFSET 0\n#define AVR32_PM_CKSEL_CPUSEL_SIZE 3\n#define AVR32_PM_CKSEL_HSBDIV 15\n#define AVR32_PM_CKSEL_HSBDIV_MASK 0x00008000\n#define AVR32_PM_CKSEL_HSBDIV_OFFSET 15\n#define AVR32_PM_CKSEL_HSBDIV_SIZE 1\n#define AVR32_PM_CKSEL_HSBSEL 8\n#define AVR32_PM_CKSEL_HSBSEL_MASK 0x00000700\n#define AVR32_PM_CKSEL_HSBSEL_OFFSET 8\n#define AVR32_PM_CKSEL_HSBSEL_SIZE 3\n#define AVR32_PM_CKSEL_PBADIV 23\n#define AVR32_PM_CKSEL_PBADIV_MASK 0x00800000\n#define AVR32_PM_CKSEL_PBADIV_OFFSET 23\n#define AVR32_PM_CKSEL_PBADIV_SIZE 1\n#define AVR32_PM_CKSEL_PBASEL 16\n#define AVR32_PM_CKSEL_PBASEL_MASK 0x00070000\n#define AVR32_PM_CKSEL_PBASEL_OFFSET 16\n#define AVR32_PM_CKSEL_PBASEL_SIZE 3\n#define AVR32_PM_CKSEL_PBBDIV 31\n#define AVR32_PM_CKSEL_PBBDIV_MASK 0x80000000\n#define AVR32_PM_CKSEL_PBBDIV_OFFSET 31\n#define AVR32_PM_CKSEL_PBBDIV_SIZE 1\n#define AVR32_PM_CKSEL_PBBSEL 24\n#define AVR32_PM_CKSEL_PBBSEL_MASK 0x07000000\n#define AVR32_PM_CKSEL_PBBSEL_OFFSET 24\n#define AVR32_PM_CKSEL_PBBSEL_SIZE 3\n#define AVR32_PM_CLKMASK 0x00000008\n#define AVR32_PM_CPUDIV 7\n#define AVR32_PM_CPUDIV_MASK 0x00000080\n#define AVR32_PM_CPUDIV_OFFSET 7\n#define AVR32_PM_CPUDIV_SIZE 1\n#define AVR32_PM_CPUERR 7\n#define AVR32_PM_CPUERR_MASK 0x00000080\n#define AVR32_PM_CPUERR_OFFSET 7\n#define AVR32_PM_CPUERR_SIZE 1\n#define AVR32_PM_CPUMASK 0x00000008\n#define AVR32_PM_CPUSEL 0\n#define AVR32_PM_CPUSEL_MASK 0x00000007\n#define AVR32_PM_CPUSEL_OFFSET 0\n#define AVR32_PM_CPUSEL_SIZE 3\n#define AVR32_PM_CRYSTAL 0x00000001\n#define AVR32_PM_CRYSTAL_G0 0x00000004\n#define AVR32_PM_CRYSTAL_G1 0x00000005\n#define AVR32_PM_CRYSTAL_G2 0x00000006\n#define AVR32_PM_CRYSTAL_G3 0x00000007\n#define AVR32_PM_CTRL 8\n#define AVR32_PM_CTRL_ENABLED 0x00000001\n#define AVR32_PM_CTRL_ENABLED_NORESET 0x00000002\n#define AVR32_PM_CTRL_MASK 0x00000300\n#define AVR32_PM_CTRL_OFF1 0x00000000\n#define AVR32_PM_CTRL_OFF2 0x00000003\n#define AVR32_PM_CTRL_OFFSET 8\n#define AVR32_PM_CTRL_SIZE 2\n#define AVR32_PM_DIV 8\n#define AVR32_PM_DIVEN 4\n#define AVR32_PM_DIVEN_MASK 0x00000010\n#define AVR32_PM_DIVEN_OFFSET 4\n#define AVR32_PM_DIVEN_SIZE 1\n#define AVR32_PM_DIV_MASK 0x0000ff00\n#define AVR32_PM_DIV_OFFSET 8\n#define AVR32_PM_DIV_SIZE 8\n#define AVR32_PM_ENABLED 0x00000001\n#define AVR32_PM_ENABLED_NORESET 0x00000002\n#define AVR32_PM_EXT 2\n#define AVR32_PM_EXT_CLOCK 0x00000000\n#define AVR32_PM_EXT_MASK 0x00000004\n#define AVR32_PM_EXT_OFFSET 2\n#define AVR32_PM_EXT_SIZE 1\n#define AVR32_PM_FCD 16\n#define AVR32_PM_FCD_MASK 0x00010000\n#define AVR32_PM_FCD_OFFSET 16\n#define AVR32_PM_FCD_SIZE 1\n#define AVR32_PM_GCCTRL 0x00000060\n#define AVR32_PM_GCCTRL_CEN 2\n#define AVR32_PM_GCCTRL_CEN_MASK 0x00000004\n#define AVR32_PM_GCCTRL_CEN_OFFSET 2\n#define AVR32_PM_GCCTRL_CEN_SIZE 1\n#define AVR32_PM_GCCTRL_DIV 8\n#define AVR32_PM_GCCTRL_DIVEN 4\n#define AVR32_PM_GCCTRL_DIVEN_MASK 0x00000010\n#define AVR32_PM_GCCTRL_DIVEN_OFFSET 4\n#define AVR32_PM_GCCTRL_DIVEN_SIZE 1\n#define AVR32_PM_GCCTRL_DIV_MASK 0x0000ff00\n#define AVR32_PM_GCCTRL_DIV_OFFSET 8\n#define AVR32_PM_GCCTRL_DIV_SIZE 8\n#define AVR32_PM_GCCTRL_OSCSEL 0\n#define AVR32_PM_GCCTRL_OSCSEL_MASK 0x00000001\n#define AVR32_PM_GCCTRL_OSCSEL_OFFSET 0\n#define AVR32_PM_GCCTRL_OSCSEL_SIZE 1\n#define AVR32_PM_GCCTRL_PLLSEL 1\n#define AVR32_PM_GCCTRL_PLLSEL_MASK 0x00000002\n#define AVR32_PM_GCCTRL_PLLSEL_OFFSET 1\n#define AVR32_PM_GCCTRL_PLLSEL_SIZE 1\n#define AVR32_PM_GPLP 0x00000200\n#define AVR32_PM_HSBDIV 15\n#define AVR32_PM_HSBDIV_MASK 0x00008000\n#define AVR32_PM_HSBDIV_OFFSET 15\n#define AVR32_PM_HSBDIV_SIZE 1\n#define AVR32_PM_HSBMASK 0x0000000c\n#define AVR32_PM_HSBSEL 8\n#define AVR32_PM_HSBSEL_MASK 0x00000700\n#define AVR32_PM_HSBSEL_OFFSET 8\n#define AVR32_PM_HSBSEL_SIZE 3\n#define AVR32_PM_HYST 6\n#define AVR32_PM_HYST_MASK 0x00000040\n#define AVR32_PM_HYST_OFFSET 6\n#define AVR32_PM_HYST_SIZE 1\n#define AVR32_PM_ICR 0x00000050\n#define AVR32_PM_ICR_BODDET 16\n#define AVR32_PM_ICR_BODDET_MASK 0x00010000\n#define AVR32_PM_ICR_BODDET_OFFSET 16\n#define AVR32_PM_ICR_BODDET_SIZE 1\n#define AVR32_PM_ICR_CKRDY 5\n#define AVR32_PM_ICR_CKRDY_MASK 0x00000020\n#define AVR32_PM_ICR_CKRDY_OFFSET 5\n#define AVR32_PM_ICR_CKRDY_SIZE 1\n#define AVR32_PM_ICR_LOCK0 0\n#define AVR32_PM_ICR_LOCK0_MASK 0x00000001\n#define AVR32_PM_ICR_LOCK0_OFFSET 0\n#define AVR32_PM_ICR_LOCK0_SIZE 1\n#define AVR32_PM_ICR_LOCK1 1\n#define AVR32_PM_ICR_LOCK1_MASK 0x00000002\n#define AVR32_PM_ICR_LOCK1_OFFSET 1\n#define AVR32_PM_ICR_LOCK1_SIZE 1\n#define AVR32_PM_ICR_MSKRDY 6\n#define AVR32_PM_ICR_MSKRDY_MASK 0x00000040\n#define AVR32_PM_ICR_MSKRDY_OFFSET 6\n#define AVR32_PM_ICR_MSKRDY_SIZE 1\n#define AVR32_PM_ICR_OSC0RDY 7\n#define AVR32_PM_ICR_OSC0RDY_MASK 0x00000080\n#define AVR32_PM_ICR_OSC0RDY_OFFSET 7\n#define AVR32_PM_ICR_OSC0RDY_SIZE 1\n#define AVR32_PM_ICR_OSC1RDY 8\n#define AVR32_PM_ICR_OSC1RDY_MASK 0x00000100\n#define AVR32_PM_ICR_OSC1RDY_OFFSET 8\n#define AVR32_PM_ICR_OSC1RDY_SIZE 1\n#define AVR32_PM_ICR_OSC32RDY 9\n#define AVR32_PM_ICR_OSC32RDY_MASK 0x00000200\n#define AVR32_PM_ICR_OSC32RDY_OFFSET 9\n#define AVR32_PM_ICR_OSC32RDY_SIZE 1\n#define AVR32_PM_IDR 0x00000044\n#define AVR32_PM_IDR_BODDET 16\n#define AVR32_PM_IDR_BODDET_MASK 0x00010000\n#define AVR32_PM_IDR_BODDET_OFFSET 16\n#define AVR32_PM_IDR_BODDET_SIZE 1\n#define AVR32_PM_IDR_CKRDY 5\n#define AVR32_PM_IDR_CKRDY_MASK 0x00000020\n#define AVR32_PM_IDR_CKRDY_OFFSET 5\n#define AVR32_PM_IDR_CKRDY_SIZE 1\n#define AVR32_PM_IDR_LOCK0 0\n#define AVR32_PM_IDR_LOCK0_MASK 0x00000001\n#define AVR32_PM_IDR_LOCK0_OFFSET 0\n#define AVR32_PM_IDR_LOCK0_SIZE 1\n#define AVR32_PM_IDR_LOCK1 1\n#define AVR32_PM_IDR_LOCK1_MASK 0x00000002\n#define AVR32_PM_IDR_LOCK1_OFFSET 1\n#define AVR32_PM_IDR_LOCK1_SIZE 1\n#define AVR32_PM_IDR_MSKRDY 6\n#define AVR32_PM_IDR_MSKRDY_MASK 0x00000040\n#define AVR32_PM_IDR_MSKRDY_OFFSET 6\n#define AVR32_PM_IDR_MSKRDY_SIZE 1\n#define AVR32_PM_IDR_OSC0RDY 7\n#define AVR32_PM_IDR_OSC0RDY_MASK 0x00000080\n#define AVR32_PM_IDR_OSC0RDY_OFFSET 7\n#define AVR32_PM_IDR_OSC0RDY_SIZE 1\n#define AVR32_PM_IDR_OSC1RDY 8\n#define AVR32_PM_IDR_OSC1RDY_MASK 0x00000100\n#define AVR32_PM_IDR_OSC1RDY_OFFSET 8\n#define AVR32_PM_IDR_OSC1RDY_SIZE 1\n#define AVR32_PM_IDR_OSC32RDY 9\n#define AVR32_PM_IDR_OSC32RDY_MASK 0x00000200\n#define AVR32_PM_IDR_OSC32RDY_OFFSET 9\n#define AVR32_PM_IDR_OSC32RDY_SIZE 1\n#define AVR32_PM_IER 0x00000040\n#define AVR32_PM_IER_BODDET 16\n#define AVR32_PM_IER_BODDET_MASK 0x00010000\n#define AVR32_PM_IER_BODDET_OFFSET 16\n#define AVR32_PM_IER_BODDET_SIZE 1\n#define AVR32_PM_IER_CKRDY 5\n#define AVR32_PM_IER_CKRDY_MASK 0x00000020\n#define AVR32_PM_IER_CKRDY_OFFSET 5\n#define AVR32_PM_IER_CKRDY_SIZE 1\n#define AVR32_PM_IER_LOCK0 0\n#define AVR32_PM_IER_LOCK0_MASK 0x00000001\n#define AVR32_PM_IER_LOCK0_OFFSET 0\n#define AVR32_PM_IER_LOCK0_SIZE 1\n#define AVR32_PM_IER_LOCK1 1\n#define AVR32_PM_IER_LOCK1_MASK 0x00000002\n#define AVR32_PM_IER_LOCK1_OFFSET 1\n#define AVR32_PM_IER_LOCK1_SIZE 1\n#define AVR32_PM_IER_MSKRDY 6\n#define AVR32_PM_IER_MSKRDY_MASK 0x00000040\n#define AVR32_PM_IER_MSKRDY_OFFSET 6\n#define AVR32_PM_IER_MSKRDY_SIZE 1\n#define AVR32_PM_IER_OSC0RDY 7\n#define AVR32_PM_IER_OSC0RDY_MASK 0x00000080\n#define AVR32_PM_IER_OSC0RDY_OFFSET 7\n#define AVR32_PM_IER_OSC0RDY_SIZE 1\n#define AVR32_PM_IER_OSC1RDY 8\n#define AVR32_PM_IER_OSC1RDY_MASK 0x00000100\n#define AVR32_PM_IER_OSC1RDY_OFFSET 8\n#define AVR32_PM_IER_OSC1RDY_SIZE 1\n#define AVR32_PM_IER_OSC32RDY 9\n#define AVR32_PM_IER_OSC32RDY_MASK 0x00000200\n#define AVR32_PM_IER_OSC32RDY_OFFSET 9\n#define AVR32_PM_IER_OSC32RDY_SIZE 1\n#define AVR32_PM_IMR 0x00000048\n#define AVR32_PM_IMR_BODDET 16\n#define AVR32_PM_IMR_BODDET_MASK 0x00010000\n#define AVR32_PM_IMR_BODDET_OFFSET 16\n#define AVR32_PM_IMR_BODDET_SIZE 1\n#define AVR32_PM_IMR_CKRDY 5\n#define AVR32_PM_IMR_CKRDY_MASK 0x00000020\n#define AVR32_PM_IMR_CKRDY_OFFSET 5\n#define AVR32_PM_IMR_CKRDY_SIZE 1\n#define AVR32_PM_IMR_LOCK0 0\n#define AVR32_PM_IMR_LOCK0_MASK 0x00000001\n#define AVR32_PM_IMR_LOCK0_OFFSET 0\n#define AVR32_PM_IMR_LOCK0_SIZE 1\n#define AVR32_PM_IMR_LOCK1 1\n#define AVR32_PM_IMR_LOCK1_MASK 0x00000002\n#define AVR32_PM_IMR_LOCK1_OFFSET 1\n#define AVR32_PM_IMR_LOCK1_SIZE 1\n#define AVR32_PM_IMR_MSKRDY 6\n#define AVR32_PM_IMR_MSKRDY_MASK 0x00000040\n#define AVR32_PM_IMR_MSKRDY_OFFSET 6\n#define AVR32_PM_IMR_MSKRDY_SIZE 1\n#define AVR32_PM_IMR_OSC0RDY 7\n#define AVR32_PM_IMR_OSC0RDY_MASK 0x00000080\n#define AVR32_PM_IMR_OSC0RDY_OFFSET 7\n#define AVR32_PM_IMR_OSC0RDY_SIZE 1\n#define AVR32_PM_IMR_OSC1RDY 8\n#define AVR32_PM_IMR_OSC1RDY_MASK 0x00000100\n#define AVR32_PM_IMR_OSC1RDY_OFFSET 8\n#define AVR32_PM_IMR_OSC1RDY_SIZE 1\n#define AVR32_PM_IMR_OSC32RDY 9\n#define AVR32_PM_IMR_OSC32RDY_MASK 0x00000200\n#define AVR32_PM_IMR_OSC32RDY_OFFSET 9\n#define AVR32_PM_IMR_OSC32RDY_SIZE 1\n#define AVR32_PM_ISR 0x0000004c\n#define AVR32_PM_ISR_BODDET 16\n#define AVR32_PM_ISR_BODDET_MASK 0x00010000\n#define AVR32_PM_ISR_BODDET_OFFSET 16\n#define AVR32_PM_ISR_BODDET_SIZE 1\n#define AVR32_PM_ISR_CKRDY 5\n#define AVR32_PM_ISR_CKRDY_MASK 0x00000020\n#define AVR32_PM_ISR_CKRDY_OFFSET 5\n#define AVR32_PM_ISR_CKRDY_SIZE 1\n#define AVR32_PM_ISR_LOCK0 0\n#define AVR32_PM_ISR_LOCK0_MASK 0x00000001\n#define AVR32_PM_ISR_LOCK0_OFFSET 0\n#define AVR32_PM_ISR_LOCK0_SIZE 1\n#define AVR32_PM_ISR_LOCK1 1\n#define AVR32_PM_ISR_LOCK1_MASK 0x00000002\n#define AVR32_PM_ISR_LOCK1_OFFSET 1\n#define AVR32_PM_ISR_LOCK1_SIZE 1\n#define AVR32_PM_ISR_MSKRDY 6\n#define AVR32_PM_ISR_MSKRDY_MASK 0x00000040\n#define AVR32_PM_ISR_MSKRDY_OFFSET 6\n#define AVR32_PM_ISR_MSKRDY_SIZE 1\n#define AVR32_PM_ISR_OSC0RDY 7\n#define AVR32_PM_ISR_OSC0RDY_MASK 0x00000080\n#define AVR32_PM_ISR_OSC0RDY_OFFSET 7\n#define AVR32_PM_ISR_OSC0RDY_SIZE 1\n#define AVR32_PM_ISR_OSC1RDY 8\n#define AVR32_PM_ISR_OSC1RDY_MASK 0x00000100\n#define AVR32_PM_ISR_OSC1RDY_OFFSET 8\n#define AVR32_PM_ISR_OSC1RDY_SIZE 1\n#define AVR32_PM_ISR_OSC32RDY 9\n#define AVR32_PM_ISR_OSC32RDY_MASK 0x00000200\n#define AVR32_PM_ISR_OSC32RDY_OFFSET 9\n#define AVR32_PM_ISR_OSC32RDY_SIZE 1\n#define AVR32_PM_JTAG 4\n#define AVR32_PM_JTAGHARD 9\n#define AVR32_PM_JTAGHARD_MASK 0x00000200\n#define AVR32_PM_JTAGHARD_OFFSET 9\n#define AVR32_PM_JTAGHARD_SIZE 1\n#define AVR32_PM_JTAG_MASK 0x00000010\n#define AVR32_PM_JTAG_OFFSET 4\n#define AVR32_PM_JTAG_SIZE 1\n#define AVR32_PM_KEY 24\n#define AVR32_PM_KEY_MASK 0xff000000\n#define AVR32_PM_KEY_OFFSET 24\n#define AVR32_PM_KEY_SIZE 8\n#define AVR32_PM_LEVEL 0\n#define AVR32_PM_LEVEL_MASK 0x0000003f\n#define AVR32_PM_LEVEL_OFFSET 0\n#define AVR32_PM_LEVEL_SIZE 6\n#define AVR32_PM_LOCK0 0\n#define AVR32_PM_LOCK0_MASK 0x00000001\n#define AVR32_PM_LOCK0_OFFSET 0\n#define AVR32_PM_LOCK0_SIZE 1\n#define AVR32_PM_LOCK1 1\n#define AVR32_PM_LOCK1_MASK 0x00000002\n#define AVR32_PM_LOCK1_OFFSET 1\n#define AVR32_PM_LOCK1_SIZE 1\n#define AVR32_PM_MCCTRL 0x00000000\n#define AVR32_PM_MCCTRL_MCSEL 0\n#define AVR32_PM_MCCTRL_MCSEL_MASK 0x00000003\n#define AVR32_PM_MCCTRL_MCSEL_OFFSET 0\n#define AVR32_PM_MCCTRL_MCSEL_OSC0 0x00000001\n#define AVR32_PM_MCCTRL_MCSEL_PLL0 0x00000002\n#define AVR32_PM_MCCTRL_MCSEL_SIZE 2\n#define AVR32_PM_MCCTRL_MCSEL_SLOW 0x00000000\n#define AVR32_PM_MCCTRL_OSC0EN 2\n#define AVR32_PM_MCCTRL_OSC0EN_MASK 0x00000004\n#define AVR32_PM_MCCTRL_OSC0EN_OFFSET 2\n#define AVR32_PM_MCCTRL_OSC0EN_SIZE 1\n#define AVR32_PM_MCCTRL_OSC1EN 3\n#define AVR32_PM_MCCTRL_OSC1EN_MASK 0x00000008\n#define AVR32_PM_MCCTRL_OSC1EN_OFFSET 3\n#define AVR32_PM_MCCTRL_OSC1EN_SIZE 1\n#define AVR32_PM_MCSEL 0\n#define AVR32_PM_MCSEL_MASK 0x00000003\n#define AVR32_PM_MCSEL_OFFSET 0\n#define AVR32_PM_MCSEL_OSC0 0x00000001\n#define AVR32_PM_MCSEL_PLL0 0x00000002\n#define AVR32_PM_MCSEL_SIZE 2\n#define AVR32_PM_MCSEL_SLOW 0x00000000\n#define AVR32_PM_MODE_CRYSTAL 0x00000001\n#define AVR32_PM_MODE_CRYSTAL_G0 0x00000004\n#define AVR32_PM_MODE_CRYSTAL_G1 0x00000005\n#define AVR32_PM_MODE_CRYSTAL_G2 0x00000006\n#define AVR32_PM_MODE_CRYSTAL_G3 0x00000007\n#define AVR32_PM_MODE_EXT_CLOCK 0x00000000\n#define AVR32_PM_MODE_SIZE 3\n#define AVR32_PM_MSKRDY 6\n#define AVR32_PM_MSKRDY_MASK 0x00000040\n#define AVR32_PM_MSKRDY_OFFSET 6\n#define AVR32_PM_MSKRDY_SIZE 1\n#define AVR32_PM_OCDRST 8\n#define AVR32_PM_OCDRST_MASK 0x00000100\n#define AVR32_PM_OCDRST_OFFSET 8\n#define AVR32_PM_OCDRST_SIZE 1\n#define AVR32_PM_OFF1 0x00000000\n#define AVR32_PM_OFF2 0x00000003\n#define AVR32_PM_OSC0 0x00000001\n#define AVR32_PM_OSC0EN 2\n#define AVR32_PM_OSC0EN_MASK 0x00000004\n#define AVR32_PM_OSC0EN_OFFSET 2\n#define AVR32_PM_OSC0EN_SIZE 1\n#define AVR32_PM_OSC0RDY 7\n#define AVR32_PM_OSC0RDY_MASK 0x00000080\n#define AVR32_PM_OSC0RDY_OFFSET 7\n#define AVR32_PM_OSC0RDY_SIZE 1\n#define AVR32_PM_OSC1EN 3\n#define AVR32_PM_OSC1EN_MASK 0x00000008\n#define AVR32_PM_OSC1EN_OFFSET 3\n#define AVR32_PM_OSC1EN_SIZE 1\n#define AVR32_PM_OSC1RDY 8\n#define AVR32_PM_OSC1RDY_MASK 0x00000100\n#define AVR32_PM_OSC1RDY_OFFSET 8\n#define AVR32_PM_OSC1RDY_SIZE 1\n#define AVR32_PM_OSC32EN 0\n#define AVR32_PM_OSC32EN_MASK 0x00000001\n#define AVR32_PM_OSC32EN_OFFSET 0\n#define AVR32_PM_OSC32EN_SIZE 1\n#define AVR32_PM_OSC32RDY 9\n#define AVR32_PM_OSC32RDY_MASK 0x00000200\n#define AVR32_PM_OSC32RDY_OFFSET 9\n#define AVR32_PM_OSC32RDY_SIZE 1\n#define AVR32_PM_OSCCTRL0 0x00000028\n#define AVR32_PM_OSCCTRL0_MODE 0\n#define AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G0 0x00000004\n#define AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G1 0x00000005\n#define AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 0x00000006\n#define AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3 0x00000007\n#define AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK 0x00000000\n#define AVR32_PM_OSCCTRL0_MODE_MASK 0x00000007\n#define AVR32_PM_OSCCTRL0_MODE_OFFSET 0\n#define AVR32_PM_OSCCTRL0_MODE_SIZE 3\n#define AVR32_PM_OSCCTRL0_STARTUP 8\n#define AVR32_PM_OSCCTRL0_STARTUP_0_RCOSC 0x00000000\n#define AVR32_PM_OSCCTRL0_STARTUP_128_RCOSC 0x00000002\n#define AVR32_PM_OSCCTRL0_STARTUP_16384_RCOSC 0x00000006\n#define AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC 0x00000003\n#define AVR32_PM_OSCCTRL0_STARTUP_4096_RCOSC 0x00000004\n#define AVR32_PM_OSCCTRL0_STARTUP_64_RCOSC 0x00000001\n#define AVR32_PM_OSCCTRL0_STARTUP_8192_RCOSC 0x00000005\n#define AVR32_PM_OSCCTRL0_STARTUP_MASK 0x00000700\n#define AVR32_PM_OSCCTRL0_STARTUP_OFFSET 8\n#define AVR32_PM_OSCCTRL0_STARTUP_SIZE 3\n#define AVR32_PM_OSCCTRL1 0x0000002c\n#define AVR32_PM_OSCCTRL1_MODE 0\n#define AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G0 0x00000004\n#define AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G1 0x00000005\n#define AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 0x00000006\n#define AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3 0x00000007\n#define AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK 0x00000000\n#define AVR32_PM_OSCCTRL1_MODE_MASK 0x00000007\n#define AVR32_PM_OSCCTRL1_MODE_OFFSET 0\n#define AVR32_PM_OSCCTRL1_MODE_SIZE 3\n#define AVR32_PM_OSCCTRL1_STARTUP 8\n#define AVR32_PM_OSCCTRL1_STARTUP_0_RCOSC 0x00000000\n#define AVR32_PM_OSCCTRL1_STARTUP_128_RCOSC 0x00000002\n#define AVR32_PM_OSCCTRL1_STARTUP_16384_RCOSC 0x00000006\n#define AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC 0x00000003\n#define AVR32_PM_OSCCTRL1_STARTUP_4096_RCOSC 0x00000004\n#define AVR32_PM_OSCCTRL1_STARTUP_64_RCOSC 0x00000001\n#define AVR32_PM_OSCCTRL1_STARTUP_8192_RCOSC 0x00000005\n#define AVR32_PM_OSCCTRL1_STARTUP_MASK 0x00000700\n#define AVR32_PM_OSCCTRL1_STARTUP_OFFSET 8\n#define AVR32_PM_OSCCTRL1_STARTUP_SIZE 3\n#define AVR32_PM_OSCCTRL32 0x00000030\n#define AVR32_PM_OSCCTRL32_MODE 8\n#define AVR32_PM_OSCCTRL32_MODE_CRYSTAL 0x00000001\n#define AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK 0x00000000\n#define AVR32_PM_OSCCTRL32_MODE_MASK 0x00000700\n#define AVR32_PM_OSCCTRL32_MODE_OFFSET 8\n#define AVR32_PM_OSCCTRL32_MODE_SIZE 3\n#define AVR32_PM_OSCCTRL32_OSC32EN 0\n#define AVR32_PM_OSCCTRL32_OSC32EN_MASK 0x00000001\n#define AVR32_PM_OSCCTRL32_OSC32EN_OFFSET 0\n#define AVR32_PM_OSCCTRL32_OSC32EN_SIZE 1\n#define AVR32_PM_OSCCTRL32_STARTUP 16\n#define AVR32_PM_OSCCTRL32_STARTUP_0_RCOSC 0x00000000\n#define AVR32_PM_OSCCTRL32_STARTUP_128_RCOSC 0x00000001\n#define AVR32_PM_OSCCTRL32_STARTUP_131072_RCOSC 0x00000005\n#define AVR32_PM_OSCCTRL32_STARTUP_16384_RCOSC 0x00000003\n#define AVR32_PM_OSCCTRL32_STARTUP_262144_RCOSC 0x00000006\n#define AVR32_PM_OSCCTRL32_STARTUP_524288_RCOSC 0x00000007\n#define AVR32_PM_OSCCTRL32_STARTUP_65536_RCOSC 0x00000004\n#define AVR32_PM_OSCCTRL32_STARTUP_8192_RCOSC 0x00000002\n#define AVR32_PM_OSCCTRL32_STARTUP_MASK 0x00070000\n#define AVR32_PM_OSCCTRL32_STARTUP_OFFSET 16\n#define AVR32_PM_OSCCTRL32_STARTUP_SIZE 3\n#define AVR32_PM_OSCSEL 0\n#define AVR32_PM_OSCSEL_MASK 0x00000001\n#define AVR32_PM_OSCSEL_OFFSET 0\n#define AVR32_PM_OSCSEL_SIZE 1\n#define AVR32_PM_PBADIV 23\n#define AVR32_PM_PBADIV_MASK 0x00800000\n#define AVR32_PM_PBADIV_OFFSET 23\n#define AVR32_PM_PBADIV_SIZE 1\n#define AVR32_PM_PBAMASK 0x00000010\n#define AVR32_PM_PBASEL 16\n#define AVR32_PM_PBASEL_MASK 0x00070000\n#define AVR32_PM_PBASEL_OFFSET 16\n#define AVR32_PM_PBASEL_SIZE 3\n#define AVR32_PM_PBBDIV 31\n#define AVR32_PM_PBBDIV_MASK 0x80000000\n#define AVR32_PM_PBBDIV_OFFSET 31\n#define AVR32_PM_PBBDIV_SIZE 1\n#define AVR32_PM_PBBMASK 0x00000014\n#define AVR32_PM_PBBSEL 24\n#define AVR32_PM_PBBSEL_MASK 0x07000000\n#define AVR32_PM_PBBSEL_OFFSET 24\n#define AVR32_PM_PBBSEL_SIZE 3\n#define AVR32_PM_PLL0 0x00000020\n#define AVR32_PM_PLL0_PLLBPL 7\n#define AVR32_PM_PLL0_PLLBPL_MASK 0x00000080\n#define AVR32_PM_PLL0_PLLBPL_OFFSET 7\n#define AVR32_PM_PLL0_PLLBPL_SIZE 1\n#define AVR32_PM_PLL0_PLLCOUNT 24\n#define AVR32_PM_PLL0_PLLCOUNT_MASK 0x3f000000\n#define AVR32_PM_PLL0_PLLCOUNT_OFFSET 24\n#define AVR32_PM_PLL0_PLLCOUNT_SIZE 6\n#define AVR32_PM_PLL0_PLLDIV 8\n#define AVR32_PM_PLL0_PLLDIV_MASK 0x00000f00\n#define AVR32_PM_PLL0_PLLDIV_OFFSET 8\n#define AVR32_PM_PLL0_PLLDIV_SIZE 4\n#define AVR32_PM_PLL0_PLLEN 0\n#define AVR32_PM_PLL0_PLLEN_MASK 0x00000001\n#define AVR32_PM_PLL0_PLLEN_OFFSET 0\n#define AVR32_PM_PLL0_PLLEN_SIZE 1\n#define AVR32_PM_PLL0_PLLIOTESTEN 30\n#define AVR32_PM_PLL0_PLLIOTESTEN_MASK 0x40000000\n#define AVR32_PM_PLL0_PLLIOTESTEN_OFFSET 30\n#define AVR32_PM_PLL0_PLLIOTESTEN_SIZE 1\n#define AVR32_PM_PLL0_PLLMUL 16\n#define AVR32_PM_PLL0_PLLMUL_MASK 0x000f0000\n#define AVR32_PM_PLL0_PLLMUL_OFFSET 16\n#define AVR32_PM_PLL0_PLLMUL_SIZE 4\n#define AVR32_PM_PLL0_PLLOPT 2\n#define AVR32_PM_PLL0_PLLOPT_MASK 0x0000001c\n#define AVR32_PM_PLL0_PLLOPT_OFFSET 2\n#define AVR32_PM_PLL0_PLLOPT_SIZE 3\n#define AVR32_PM_PLL0_PLLOSC 1\n#define AVR32_PM_PLL0_PLLOSC_MASK 0x00000002\n#define AVR32_PM_PLL0_PLLOSC_OFFSET 1\n#define AVR32_PM_PLL0_PLLOSC_SIZE 1\n#define AVR32_PM_PLL0_PLLTEST 31\n#define AVR32_PM_PLL0_PLLTEST_MASK 0x80000000\n#define AVR32_PM_PLL0_PLLTEST_OFFSET 31\n#define AVR32_PM_PLL0_PLLTEST_SIZE 1\n#define AVR32_PM_PLL1 0x00000024\n#define AVR32_PM_PLL1_PLLBPL 7\n#define AVR32_PM_PLL1_PLLBPL_MASK 0x00000080\n#define AVR32_PM_PLL1_PLLBPL_OFFSET 7\n#define AVR32_PM_PLL1_PLLBPL_SIZE 1\n#define AVR32_PM_PLL1_PLLCOUNT 24\n#define AVR32_PM_PLL1_PLLCOUNT_MASK 0x3f000000\n#define AVR32_PM_PLL1_PLLCOUNT_OFFSET 24\n#define AVR32_PM_PLL1_PLLCOUNT_SIZE 6\n#define AVR32_PM_PLL1_PLLDIV 8\n#define AVR32_PM_PLL1_PLLDIV_MASK 0x00000f00\n#define AVR32_PM_PLL1_PLLDIV_OFFSET 8\n#define AVR32_PM_PLL1_PLLDIV_SIZE 4\n#define AVR32_PM_PLL1_PLLEN 0\n#define AVR32_PM_PLL1_PLLEN_MASK 0x00000001\n#define AVR32_PM_PLL1_PLLEN_OFFSET 0\n#define AVR32_PM_PLL1_PLLEN_SIZE 1\n#define AVR32_PM_PLL1_PLLIOTESTEN 30\n#define AVR32_PM_PLL1_PLLIOTESTEN_MASK 0x40000000\n#define AVR32_PM_PLL1_PLLIOTESTEN_OFFSET 30\n#define AVR32_PM_PLL1_PLLIOTESTEN_SIZE 1\n#define AVR32_PM_PLL1_PLLMUL 16\n#define AVR32_PM_PLL1_PLLMUL_MASK 0x000f0000\n#define AVR32_PM_PLL1_PLLMUL_OFFSET 16\n#define AVR32_PM_PLL1_PLLMUL_SIZE 4\n#define AVR32_PM_PLL1_PLLOPT 2\n#define AVR32_PM_PLL1_PLLOPT_MASK 0x0000001c\n#define AVR32_PM_PLL1_PLLOPT_OFFSET 2\n#define AVR32_PM_PLL1_PLLOPT_SIZE 3\n#define AVR32_PM_PLL1_PLLOSC 1\n#define AVR32_PM_PLL1_PLLOSC_MASK 0x00000002\n#define AVR32_PM_PLL1_PLLOSC_OFFSET 1\n#define AVR32_PM_PLL1_PLLOSC_SIZE 1\n#define AVR32_PM_PLL1_PLLTEST 31\n#define AVR32_PM_PLL1_PLLTEST_MASK 0x80000000\n#define AVR32_PM_PLL1_PLLTEST_OFFSET 31\n#define AVR32_PM_PLL1_PLLTEST_SIZE 1\n#define AVR32_PM_PLLBPL 7\n#define AVR32_PM_PLLBPL_MASK 0x00000080\n#define AVR32_PM_PLLBPL_OFFSET 7\n#define AVR32_PM_PLLBPL_SIZE 1\n#define AVR32_PM_PLLCOUNT 24\n#define AVR32_PM_PLLCOUNT_MASK 0x3f000000\n#define AVR32_PM_PLLCOUNT_OFFSET 24\n#define AVR32_PM_PLLCOUNT_SIZE 6\n#define AVR32_PM_PLLDIV 8\n#define AVR32_PM_PLLDIV_MASK 0x00000f00\n#define AVR32_PM_PLLDIV_OFFSET 8\n#define AVR32_PM_PLLDIV_SIZE 4\n#define AVR32_PM_PLLEN 0\n#define AVR32_PM_PLLEN_MASK 0x00000001\n#define AVR32_PM_PLLEN_OFFSET 0\n#define AVR32_PM_PLLEN_SIZE 1\n#define AVR32_PM_PLLIOTESTEN 30\n#define AVR32_PM_PLLIOTESTEN_MASK 0x40000000\n#define AVR32_PM_PLLIOTESTEN_OFFSET 30\n#define AVR32_PM_PLLIOTESTEN_SIZE 1\n#define AVR32_PM_PLLMUL 16\n#define AVR32_PM_PLLMUL_MASK 0x000f0000\n#define AVR32_PM_PLLMUL_OFFSET 16\n#define AVR32_PM_PLLMUL_SIZE 4\n#define AVR32_PM_PLLOPT 2\n#define AVR32_PM_PLLOPT_MASK 0x0000001c\n#define AVR32_PM_PLLOPT_OFFSET 2\n#define AVR32_PM_PLLOPT_SIZE 3\n#define AVR32_PM_PLLOSC 1\n#define AVR32_PM_PLLOSC_MASK 0x00000002\n#define AVR32_PM_PLLOSC_OFFSET 1\n#define AVR32_PM_PLLOSC_SIZE 1\n#define AVR32_PM_PLLSEL 1\n#define AVR32_PM_PLLSEL_MASK 0x00000002\n#define AVR32_PM_PLLSEL_OFFSET 1\n#define AVR32_PM_PLLSEL_SIZE 1\n#define AVR32_PM_PLLTEST 31\n#define AVR32_PM_PLLTEST_MASK 0x80000000\n#define AVR32_PM_PLLTEST_OFFSET 31\n#define AVR32_PM_PLLTEST_SIZE 1\n#define AVR32_PM_POR 0\n#define AVR32_PM_POR_MASK 0x00000001\n#define AVR32_PM_POR_OFFSET 0\n#define AVR32_PM_POR_SIZE 1\n#define AVR32_PM_POSCSR 0x00000054\n#define AVR32_PM_POSCSR_BODDET 16\n#define AVR32_PM_POSCSR_BODDET_MASK 0x00010000\n#define AVR32_PM_POSCSR_BODDET_OFFSET 16\n#define AVR32_PM_POSCSR_BODDET_SIZE 1\n#define AVR32_PM_POSCSR_CKRDY 5\n#define AVR32_PM_POSCSR_CKRDY_MASK 0x00000020\n#define AVR32_PM_POSCSR_CKRDY_OFFSET 5\n#define AVR32_PM_POSCSR_CKRDY_SIZE 1\n#define AVR32_PM_POSCSR_LOCK0 0\n#define AVR32_PM_POSCSR_LOCK0_MASK 0x00000001\n#define AVR32_PM_POSCSR_LOCK0_OFFSET 0\n#define AVR32_PM_POSCSR_LOCK0_SIZE 1\n#define AVR32_PM_POSCSR_LOCK1 1\n#define AVR32_PM_POSCSR_LOCK1_MASK 0x00000002\n#define AVR32_PM_POSCSR_LOCK1_OFFSET 1\n#define AVR32_PM_POSCSR_LOCK1_SIZE 1\n#define AVR32_PM_POSCSR_MSKRDY 6\n#define AVR32_PM_POSCSR_MSKRDY_MASK 0x00000040\n#define AVR32_PM_POSCSR_MSKRDY_OFFSET 6\n#define AVR32_PM_POSCSR_MSKRDY_SIZE 1\n#define AVR32_PM_POSCSR_OSC0RDY 7\n#define AVR32_PM_POSCSR_OSC0RDY_MASK 0x00000080\n#define AVR32_PM_POSCSR_OSC0RDY_OFFSET 7\n#define AVR32_PM_POSCSR_OSC0RDY_SIZE 1\n#define AVR32_PM_POSCSR_OSC1RDY 8\n#define AVR32_PM_POSCSR_OSC1RDY_MASK 0x00000100\n#define AVR32_PM_POSCSR_OSC1RDY_OFFSET 8\n#define AVR32_PM_POSCSR_OSC1RDY_SIZE 1\n#define AVR32_PM_POSCSR_OSC32RDY 9\n#define AVR32_PM_POSCSR_OSC32RDY_MASK 0x00000200\n#define AVR32_PM_POSCSR_OSC32RDY_OFFSET 9\n#define AVR32_PM_POSCSR_OSC32RDY_SIZE 1\n#define AVR32_PM_POSCSR_VMRDY 4\n#define AVR32_PM_POSCSR_VMRDY_MASK 0x00000010\n#define AVR32_PM_POSCSR_VMRDY_OFFSET 4\n#define AVR32_PM_POSCSR_VMRDY_SIZE 1\n#define AVR32_PM_POSCSR_VOK 3\n#define AVR32_PM_POSCSR_VOK_MASK 0x00000008\n#define AVR32_PM_POSCSR_VOK_OFFSET 3\n#define AVR32_PM_POSCSR_VOK_SIZE 1\n#define AVR32_PM_POSCSR_WAKE 2\n#define AVR32_PM_POSCSR_WAKE_MASK 0x00000004\n#define AVR32_PM_POSCSR_WAKE_OFFSET 2\n#define AVR32_PM_POSCSR_WAKE_SIZE 1\n#define AVR32_PM_RCAUSE 0x00000140\n#define AVR32_PM_RCAUSE_BOD 1\n#define AVR32_PM_RCAUSE_BOD_MASK 0x00000002\n#define AVR32_PM_RCAUSE_BOD_OFFSET 1\n#define AVR32_PM_RCAUSE_BOD_SIZE 1\n#define AVR32_PM_RCAUSE_CPUERR 7\n#define AVR32_PM_RCAUSE_CPUERR_MASK 0x00000080\n#define AVR32_PM_RCAUSE_CPUERR_OFFSET 7\n#define AVR32_PM_RCAUSE_CPUERR_SIZE 1\n#define AVR32_PM_RCAUSE_EXT 2\n#define AVR32_PM_RCAUSE_EXT_MASK 0x00000004\n#define AVR32_PM_RCAUSE_EXT_OFFSET 2\n#define AVR32_PM_RCAUSE_EXT_SIZE 1\n#define AVR32_PM_RCAUSE_JTAG 4\n#define AVR32_PM_RCAUSE_JTAGHARD 9\n#define AVR32_PM_RCAUSE_JTAGHARD_MASK 0x00000200\n#define AVR32_PM_RCAUSE_JTAGHARD_OFFSET 9\n#define AVR32_PM_RCAUSE_JTAGHARD_SIZE 1\n#define AVR32_PM_RCAUSE_JTAG_MASK 0x00000010\n#define AVR32_PM_RCAUSE_JTAG_OFFSET 4\n#define AVR32_PM_RCAUSE_JTAG_SIZE 1\n#define AVR32_PM_RCAUSE_OCDRST 8\n#define AVR32_PM_RCAUSE_OCDRST_MASK 0x00000100\n#define AVR32_PM_RCAUSE_OCDRST_OFFSET 8\n#define AVR32_PM_RCAUSE_OCDRST_SIZE 1\n#define AVR32_PM_RCAUSE_POR 0\n#define AVR32_PM_RCAUSE_POR_MASK 0x00000001\n#define AVR32_PM_RCAUSE_POR_OFFSET 0\n#define AVR32_PM_RCAUSE_POR_SIZE 1\n#define AVR32_PM_RCAUSE_SLEEP 6\n#define AVR32_PM_RCAUSE_SLEEP_MASK 0x00000040\n#define AVR32_PM_RCAUSE_SLEEP_OFFSET 6\n#define AVR32_PM_RCAUSE_SLEEP_SIZE 1\n#define AVR32_PM_RCAUSE_WDT 3\n#define AVR32_PM_RCAUSE_WDT_MASK 0x00000008\n#define AVR32_PM_RCAUSE_WDT_OFFSET 3\n#define AVR32_PM_RCAUSE_WDT_SIZE 1\n#define AVR32_PM_RCCR 0x000000c0\n#define AVR32_PM_RCCR_CALIB 0\n#define AVR32_PM_RCCR_CALIB_MASK 0x000003ff\n#define AVR32_PM_RCCR_CALIB_OFFSET 0\n#define AVR32_PM_RCCR_CALIB_SIZE 10\n#define AVR32_PM_RCCR_FCD 16\n#define AVR32_PM_RCCR_FCD_MASK 0x00010000\n#define AVR32_PM_RCCR_FCD_OFFSET 16\n#define AVR32_PM_RCCR_FCD_SIZE 1\n#define AVR32_PM_RCCR_KEY 24\n#define AVR32_PM_RCCR_KEY_MASK 0xff000000\n#define AVR32_PM_RCCR_KEY_OFFSET 24\n#define AVR32_PM_RCCR_KEY_SIZE 8\n#define AVR32_PM_SLEEP 6\n#define AVR32_PM_SLEEP_MASK 0x00000040\n#define AVR32_PM_SLEEP_OFFSET 6\n#define AVR32_PM_SLEEP_SIZE 1\n#define AVR32_PM_SLOW 0x00000000\n#define AVR32_PM_STARTUP_SIZE 3\n#define AVR32_PM_USB_WAKEN 0\n#define AVR32_PM_USB_WAKEN_MASK 0x00000001\n#define AVR32_PM_USB_WAKEN_OFFSET 0\n#define AVR32_PM_USB_WAKEN_SIZE 1\n#define AVR32_PM_VMRDY 4\n#define AVR32_PM_VMRDY_MASK 0x00000010\n#define AVR32_PM_VMRDY_OFFSET 4\n#define AVR32_PM_VMRDY_SIZE 1\n#define AVR32_PM_VOK 3\n#define AVR32_PM_VOK_MASK 0x00000008\n#define AVR32_PM_VOK_OFFSET 3\n#define AVR32_PM_VOK_SIZE 1\n#define AVR32_PM_VREGCR 0x000000c8\n#define AVR32_PM_VREGCR_CALIB 0\n#define AVR32_PM_VREGCR_CALIB_MASK 0x00000007\n#define AVR32_PM_VREGCR_CALIB_OFFSET 0\n#define AVR32_PM_VREGCR_CALIB_SIZE 3\n#define AVR32_PM_VREGCR_FCD 16\n#define AVR32_PM_VREGCR_FCD_MASK 0x00010000\n#define AVR32_PM_VREGCR_FCD_OFFSET 16\n#define AVR32_PM_VREGCR_FCD_SIZE 1\n#define AVR32_PM_VREGCR_KEY 24\n#define AVR32_PM_VREGCR_KEY_MASK 0xff000000\n#define AVR32_PM_VREGCR_KEY_OFFSET 24\n#define AVR32_PM_VREGCR_KEY_SIZE 8\n#define AVR32_PM_WAKE 2\n#define AVR32_PM_WAKE_MASK 0x00000004\n#define AVR32_PM_WAKE_OFFSET 2\n#define AVR32_PM_WAKE_SIZE 1\n#define AVR32_PM_WDT 3\n#define AVR32_PM_WDT_MASK 0x00000008\n#define AVR32_PM_WDT_OFFSET 3\n#define AVR32_PM_WDT_SIZE 1\n\n#define AVR32_BGCR_KEY 0x00000055\n#define AVR32_BOD_KEY 0x00000055\n#define AVR32_BOD_OFF 0x00000000\n#define AVR32_BOD_ON 0x00000001\n#define AVR32_BOD_ON_NORESET 0x00000002\n#define AVR32_GC_DIV_CLOCK 0x00000001\n#define AVR32_GC_NO_DIV_CLOCK 0x00000000\n#define AVR32_GC_USES_OSC 0x00000000\n#define AVR32_GC_USES_OSC0 0x00000000\n#define AVR32_GC_USES_OSC1 0x00000001\n#define AVR32_GC_USES_PLL 0x00000001\n#define AVR32_GC_USES_PLL0 0x00000000\n#define AVR32_GC_USES_PLL1 0x00000001\n#define AVR32_PLL_USES_OSC0 0x00000000\n#define AVR32_PLL_USES_OSC1 0x00000001\n#define AVR32_PM_SMODE_DEEPSTOP 0x00000004\n#define AVR32_PM_SMODE_FROZEN 0x00000001\n#define AVR32_PM_SMODE_IDLE 0x00000000\n#define AVR32_PM_SMODE_STANDBY 0x00000002\n#define AVR32_PM_SMODE_STATIC 0x00000005\n#define AVR32_PM_SMODE_STOP 0x00000003\n#define AVR32_RCCR_KEY 0x00000055\n#define AVR32_VREGCR_KEY 0x00000055\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_pm_mcctrl_t {\n unsigned int :28;\n unsigned int osc1en : 1;\n unsigned int osc0en : 1;\n unsigned int mcsel : 2;\n} avr32_pm_mcctrl_t;\n\n\n\ntypedef struct avr32_pm_cksel_t {\n unsigned int pbbdiv : 1;\n unsigned int : 4;\n unsigned int pbbsel : 3;\n unsigned int pbadiv : 1;\n unsigned int : 4;\n unsigned int pbasel : 3;\n unsigned int hsbdiv : 1;\n unsigned int : 4;\n unsigned int hsbsel : 3;\n unsigned int cpudiv : 1;\n unsigned int : 4;\n unsigned int cpusel : 3;\n} avr32_pm_cksel_t;\n\n\n\ntypedef struct avr32_pm_pll_t {\n unsigned int plltest : 1;\n unsigned int plliotesten : 1;\n unsigned int pllcount : 6;\n unsigned int : 4;\n unsigned int pllmul : 4;\n unsigned int : 4;\n unsigned int plldiv : 4;\n unsigned int pllbpl : 1;\n unsigned int : 2;\n unsigned int pllopt : 3;\n unsigned int pllosc : 1;\n unsigned int pllen : 1;\n} avr32_pm_pll_t;\n\n\n\ntypedef struct avr32_pm_oscctrl0_t {\n unsigned int :21;\n unsigned int startup : 3;\n unsigned int : 5;\n unsigned int mode : 3;\n} avr32_pm_oscctrl0_t;\n\n\n\ntypedef struct avr32_pm_oscctrl1_t {\n unsigned int :21;\n unsigned int startup : 3;\n unsigned int : 5;\n unsigned int mode : 3;\n} avr32_pm_oscctrl1_t;\n\n\n\ntypedef struct avr32_pm_oscctrl32_t {\n unsigned int :13;\n unsigned int startup : 3;\n unsigned int : 5;\n unsigned int mode : 3;\n unsigned int : 7;\n unsigned int osc32en : 1;\n} avr32_pm_oscctrl32_t;\n\n\n\ntypedef struct avr32_pm_ier_t {\n unsigned int :15;\n unsigned int boddet : 1;\n unsigned int : 6;\n unsigned int osc32rdy : 1;\n unsigned int osc1rdy : 1;\n unsigned int osc0rdy : 1;\n unsigned int mskrdy : 1;\n unsigned int ckrdy : 1;\n unsigned int : 3;\n unsigned int lock1 : 1;\n unsigned int lock0 : 1;\n} avr32_pm_ier_t;\n\n\n\ntypedef struct avr32_pm_idr_t {\n unsigned int :15;\n unsigned int boddet : 1;\n unsigned int : 6;\n unsigned int osc32rdy : 1;\n unsigned int osc1rdy : 1;\n unsigned int osc0rdy : 1;\n unsigned int mskrdy : 1;\n unsigned int ckrdy : 1;\n unsigned int : 3;\n unsigned int lock1 : 1;\n unsigned int lock0 : 1;\n} avr32_pm_idr_t;\n\n\n\ntypedef struct avr32_pm_imr_t {\n unsigned int :15;\n unsigned int boddet : 1;\n unsigned int : 6;\n unsigned int osc32rdy : 1;\n unsigned int osc1rdy : 1;\n unsigned int osc0rdy : 1;\n unsigned int mskrdy : 1;\n unsigned int ckrdy : 1;\n unsigned int : 3;\n unsigned int lock1 : 1;\n unsigned int lock0 : 1;\n} avr32_pm_imr_t;\n\n\n\ntypedef struct avr32_pm_isr_t {\n unsigned int :15;\n unsigned int boddet : 1;\n unsigned int : 6;\n unsigned int osc32rdy : 1;\n unsigned int osc1rdy : 1;\n unsigned int osc0rdy : 1;\n unsigned int mskrdy : 1;\n unsigned int ckrdy : 1;\n unsigned int : 3;\n unsigned int lock1 : 1;\n unsigned int lock0 : 1;\n} avr32_pm_isr_t;\n\n\n\ntypedef struct avr32_pm_icr_t {\n unsigned int :15;\n unsigned int boddet : 1;\n unsigned int : 6;\n unsigned int osc32rdy : 1;\n unsigned int osc1rdy : 1;\n unsigned int osc0rdy : 1;\n unsigned int mskrdy : 1;\n unsigned int ckrdy : 1;\n unsigned int : 3;\n unsigned int lock1 : 1;\n unsigned int lock0 : 1;\n} avr32_pm_icr_t;\n\n\n\ntypedef struct avr32_pm_poscsr_t {\n unsigned int :15;\n unsigned int boddet : 1;\n unsigned int : 6;\n unsigned int osc32rdy : 1;\n unsigned int osc1rdy : 1;\n unsigned int osc0rdy : 1;\n unsigned int mskrdy : 1;\n unsigned int ckrdy : 1;\n unsigned int vmrdy : 1;\n unsigned int vok : 1;\n unsigned int wake : 1;\n unsigned int lock1 : 1;\n unsigned int lock0 : 1;\n} avr32_pm_poscsr_t;\n\n\n\ntypedef struct avr32_pm_gcctrl_t {\n unsigned int :16;\n unsigned int div : 8;\n unsigned int : 3;\n unsigned int diven : 1;\n unsigned int : 1;\n unsigned int cen : 1;\n unsigned int pllsel : 1;\n unsigned int oscsel : 1;\n} avr32_pm_gcctrl_t;\n\n\n\ntypedef struct avr32_pm_rccr_t {\n unsigned int key : 8;\n unsigned int : 7;\n unsigned int fcd : 1;\n unsigned int : 6;\n unsigned int calib :10;\n} avr32_pm_rccr_t;\n\n\n\ntypedef struct avr32_pm_bgcr_t {\n unsigned int key : 8;\n unsigned int : 7;\n unsigned int fcd : 1;\n unsigned int :13;\n unsigned int calib : 3;\n} avr32_pm_bgcr_t;\n\n\n\ntypedef struct avr32_pm_vregcr_t {\n unsigned int key : 8;\n unsigned int : 7;\n unsigned int fcd : 1;\n unsigned int :13;\n unsigned int calib : 3;\n} avr32_pm_vregcr_t;\n\n\n\ntypedef struct avr32_pm_bod_t {\n unsigned int key : 8;\n unsigned int : 7;\n unsigned int fcd : 1;\n unsigned int : 6;\n unsigned int ctrl : 2;\n unsigned int : 1;\n unsigned int hyst : 1;\n unsigned int level : 6;\n} avr32_pm_bod_t;\n\n\n\ntypedef struct avr32_pm_rcause_t {\n unsigned int :22;\n unsigned int jtaghard : 1;\n unsigned int ocdrst : 1;\n unsigned int cpuerr : 1;\n unsigned int sleep : 1;\n unsigned int : 1;\n unsigned int jtag : 1;\n unsigned int wdt : 1;\n unsigned int ext : 1;\n unsigned int bod : 1;\n unsigned int por : 1;\n} avr32_pm_rcause_t;\n\n\n\ntypedef struct avr32_pm_awen_t {\n unsigned int :31;\n unsigned int usb_waken : 1;\n} avr32_pm_awen_t;\n\n\n\ntypedef struct avr32_pm_t {\n union {\n unsigned long mcctrl ;//0x0000\n avr32_pm_mcctrl_t MCCTRL ;\n };\n union {\n unsigned long cksel ;//0x0004\n avr32_pm_cksel_t CKSEL ;\n };\n union {\n unsigned long clkmask [4];//0x0008\n struct {\n unsigned long cpumask ;//0x0008\n unsigned long hsbmask ;//0x000c\n unsigned long pbamask ;//0x0010\n unsigned long pbbmask ;//0x0014\n };\n };\n unsigned int :32 ;//0x0018\n unsigned int :32 ;//0x001c\n union {\n unsigned long pll [2];//0x0020\n avr32_pm_pll_t PLL [2];\n };\n union {\n unsigned long oscctrl0 ;//0x0028\n avr32_pm_oscctrl0_t OSCCTRL0 ;\n };\n union {\n unsigned long oscctrl1 ;//0x002c\n avr32_pm_oscctrl1_t OSCCTRL1 ;\n };\n union {\n unsigned long oscctrl32 ;//0x0030\n avr32_pm_oscctrl32_t OSCCTRL32 ;\n };\n unsigned int :32 ;//0x0034\n unsigned int :32 ;//0x0038\n unsigned int :32 ;//0x003c\n union {\n unsigned long ier ;//0x0040\n avr32_pm_ier_t IER ;\n };\n union {\n unsigned long idr ;//0x0044\n avr32_pm_idr_t IDR ;\n };\n union {\n const unsigned long imr ;//0x0048\n const avr32_pm_imr_t IMR ;\n };\n union {\n const unsigned long isr ;//0x004c\n const avr32_pm_isr_t ISR ;\n };\n union {\n unsigned long icr ;//0x0050\n avr32_pm_icr_t ICR ;\n };\n union {\n unsigned long poscsr ;//0x0054\n avr32_pm_poscsr_t POSCSR ;\n };\n unsigned int :32 ;//0x0058\n unsigned int :32 ;//0x005c\n union {\n unsigned long gcctrl [6];//0x0060\n avr32_pm_gcctrl_t GCCTRL [6];\n };\n unsigned int :32 ;//0x0078\n unsigned int :32 ;//0x007c\n unsigned int :32 ;//0x0080\n unsigned int :32 ;//0x0084\n unsigned int :32 ;//0x0088\n unsigned int :32 ;//0x008c\n unsigned int :32 ;//0x0090\n unsigned int :32 ;//0x0094\n unsigned int :32 ;//0x0098\n unsigned int :32 ;//0x009c\n unsigned int :32 ;//0x00a0\n unsigned int :32 ;//0x00a4\n unsigned int :32 ;//0x00a8\n unsigned int :32 ;//0x00ac\n unsigned int :32 ;//0x00b0\n unsigned int :32 ;//0x00b4\n unsigned int :32 ;//0x00b8\n unsigned int :32 ;//0x00bc\n union {\n unsigned long rccr ;//0x00c0\n avr32_pm_rccr_t RCCR ;\n };\n union {\n unsigned long bgcr ;//0x00c4\n avr32_pm_bgcr_t BGCR ;\n };\n union {\n unsigned long vregcr ;//0x00c8\n avr32_pm_vregcr_t VREGCR ;\n };\n unsigned int :32 ;//0x00cc\n union {\n unsigned long bod ;//0x00d0\n avr32_pm_bod_t BOD ;\n };\n unsigned int :32 ;//0x00d4\n unsigned int :32 ;//0x00d8\n unsigned int :32 ;//0x00dc\n unsigned int :32 ;//0x00e0\n unsigned int :32 ;//0x00e4\n unsigned int :32 ;//0x00e8\n unsigned int :32 ;//0x00ec\n unsigned int :32 ;//0x00f0\n unsigned int :32 ;//0x00f4\n unsigned int :32 ;//0x00f8\n unsigned int :32 ;//0x00fc\n unsigned int :32 ;//0x0100\n unsigned int :32 ;//0x0104\n unsigned int :32 ;//0x0108\n unsigned int :32 ;//0x010c\n unsigned int :32 ;//0x0110\n unsigned int :32 ;//0x0114\n unsigned int :32 ;//0x0118\n unsigned int :32 ;//0x011c\n unsigned int :32 ;//0x0120\n unsigned int :32 ;//0x0124\n unsigned int :32 ;//0x0128\n unsigned int :32 ;//0x012c\n unsigned int :32 ;//0x0130\n unsigned int :32 ;//0x0134\n unsigned int :32 ;//0x0138\n unsigned int :32 ;//0x013c\n union {\n const unsigned long rcause ;//0x0140\n const avr32_pm_rcause_t RCAUSE ;\n };\n union {\n unsigned long awen ;//0x0144\n avr32_pm_awen_t AWEN ;\n };\n unsigned int :32 ;//0x0148\n unsigned int :32 ;//0x014c\n unsigned int :32 ;//0x0150\n unsigned int :32 ;//0x0154\n unsigned int :32 ;//0x0158\n unsigned int :32 ;//0x015c\n unsigned int :32 ;//0x0160\n unsigned int :32 ;//0x0164\n unsigned int :32 ;//0x0168\n unsigned int :32 ;//0x016c\n unsigned int :32 ;//0x0170\n unsigned int :32 ;//0x0174\n unsigned int :32 ;//0x0178\n unsigned int :32 ;//0x017c\n unsigned int :32 ;//0x0180\n unsigned int :32 ;//0x0184\n unsigned int :32 ;//0x0188\n unsigned int :32 ;//0x018c\n unsigned int :32 ;//0x0190\n unsigned int :32 ;//0x0194\n unsigned int :32 ;//0x0198\n unsigned int :32 ;//0x019c\n unsigned int :32 ;//0x01a0\n unsigned int :32 ;//0x01a4\n unsigned int :32 ;//0x01a8\n unsigned int :32 ;//0x01ac\n unsigned int :32 ;//0x01b0\n unsigned int :32 ;//0x01b4\n unsigned int :32 ;//0x01b8\n unsigned int :32 ;//0x01bc\n unsigned int :32 ;//0x01c0\n unsigned int :32 ;//0x01c4\n unsigned int :32 ;//0x01c8\n unsigned int :32 ;//0x01cc\n unsigned int :32 ;//0x01d0\n unsigned int :32 ;//0x01d4\n unsigned int :32 ;//0x01d8\n unsigned int :32 ;//0x01dc\n unsigned int :32 ;//0x01e0\n unsigned int :32 ;//0x01e4\n unsigned int :32 ;//0x01e8\n unsigned int :32 ;//0x01ec\n unsigned int :32 ;//0x01f0\n unsigned int :32 ;//0x01f4\n unsigned int :32 ;//0x01f8\n unsigned int :32 ;//0x01fc\n unsigned long gplp [2];//0x0200\n} avr32_pm_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n\n#if !defined (DEPRECATED_DISABLE)\n\n#define AVR32_PM_SMODE_DEEP_STOP 0x00000004\n#define AVR32_PM_SMODE_SHUTDOWN 0x00000004\n\n#endif\n\n\n/*#ifdef AVR32_PM_230_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/pwm_130.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3A0512\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_PWM_130_H_INCLUDED\n#define AVR32_PWM_130_H_INCLUDED\n\n#define AVR32_PWM_H_VERSION 130\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_PWM_\n - Bitfield mask: AVR32_PWM__\n - Bitfield offset: AVR32_PWM___OFFSET\n - Bitfield size: AVR32_PWM___SIZE\n - Bitfield values: AVR32_PWM___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_PWM_\n - Bitfield offset: AVR32_PWM__OFFSET\n - Bitfield size: AVR32_PWM__SIZE\n - Bitfield values: AVR32_PWM__\n - Bitfield values: AVR32_PWM_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_PWM_CALG 8\n#define AVR32_PWM_CALG_MASK 0x00000100\n#define AVR32_PWM_CALG_OFFSET 8\n#define AVR32_PWM_CALG_SIZE 1\n#define AVR32_PWM_CCNT 0x0000020c\n#define AVR32_PWM_CCNT_CNT 0\n#define AVR32_PWM_CCNT_CNT_MASK 0xffffffff\n#define AVR32_PWM_CCNT_CNT_OFFSET 0\n#define AVR32_PWM_CCNT_CNT_SIZE 32\n#define AVR32_PWM_CDTY 0x00000204\n#define AVR32_PWM_CDTY_CDTY 0\n#define AVR32_PWM_CDTY_CDTY_MASK 0xffffffff\n#define AVR32_PWM_CDTY_CDTY_OFFSET 0\n#define AVR32_PWM_CDTY_CDTY_SIZE 32\n#define AVR32_PWM_CDTY_MASK 0xffffffff\n#define AVR32_PWM_CDTY_OFFSET 0\n#define AVR32_PWM_CDTY_SIZE 32\n#define AVR32_PWM_CHID0 0\n#define AVR32_PWM_CHID0_MASK 0x00000001\n#define AVR32_PWM_CHID0_OFFSET 0\n#define AVR32_PWM_CHID0_SIZE 1\n#define AVR32_PWM_CHID1 1\n#define AVR32_PWM_CHID1_MASK 0x00000002\n#define AVR32_PWM_CHID1_OFFSET 1\n#define AVR32_PWM_CHID1_SIZE 1\n#define AVR32_PWM_CHID2 2\n#define AVR32_PWM_CHID2_MASK 0x00000004\n#define AVR32_PWM_CHID2_OFFSET 2\n#define AVR32_PWM_CHID2_SIZE 1\n#define AVR32_PWM_CHID3 3\n#define AVR32_PWM_CHID3_MASK 0x00000008\n#define AVR32_PWM_CHID3_OFFSET 3\n#define AVR32_PWM_CHID3_SIZE 1\n#define AVR32_PWM_CHID4 4\n#define AVR32_PWM_CHID4_MASK 0x00000010\n#define AVR32_PWM_CHID4_OFFSET 4\n#define AVR32_PWM_CHID4_SIZE 1\n#define AVR32_PWM_CHID5 5\n#define AVR32_PWM_CHID5_MASK 0x00000020\n#define AVR32_PWM_CHID5_OFFSET 5\n#define AVR32_PWM_CHID5_SIZE 1\n#define AVR32_PWM_CHID6 6\n#define AVR32_PWM_CHID6_MASK 0x00000040\n#define AVR32_PWM_CHID6_OFFSET 6\n#define AVR32_PWM_CHID6_SIZE 1\n#define AVR32_PWM_CLKA 0x0000000b\n#define AVR32_PWM_CLKB 0x0000000c\n#define AVR32_PWM_CLK_OFF 0x00000000\n#define AVR32_PWM_CLK_SEL_PREAB 0x00000001\n#define AVR32_PWM_CMR 0x00000200\n#define AVR32_PWM_CMR_CALG 8\n#define AVR32_PWM_CMR_CALG_MASK 0x00000100\n#define AVR32_PWM_CMR_CALG_OFFSET 8\n#define AVR32_PWM_CMR_CALG_SIZE 1\n#define AVR32_PWM_CMR_CPD 10\n#define AVR32_PWM_CMR_CPD_MASK 0x00000400\n#define AVR32_PWM_CMR_CPD_OFFSET 10\n#define AVR32_PWM_CMR_CPD_SIZE 1\n#define AVR32_PWM_CMR_CPOL 9\n#define AVR32_PWM_CMR_CPOL_MASK 0x00000200\n#define AVR32_PWM_CMR_CPOL_OFFSET 9\n#define AVR32_PWM_CMR_CPOL_SIZE 1\n#define AVR32_PWM_CMR_CPRE 0\n#define AVR32_PWM_CMR_CPRE_CLKA 0x0000000b\n#define AVR32_PWM_CMR_CPRE_CLKB 0x0000000c\n#define AVR32_PWM_CMR_CPRE_MASK 0x0000000f\n#define AVR32_PWM_CMR_CPRE_MCK 0x00000000\n#define AVR32_PWM_CMR_CPRE_MCK_DIV_1024 0x0000000a\n#define AVR32_PWM_CMR_CPRE_MCK_DIV_128 0x00000007\n#define AVR32_PWM_CMR_CPRE_MCK_DIV_16 0x00000004\n#define AVR32_PWM_CMR_CPRE_MCK_DIV_2 0x00000001\n#define AVR32_PWM_CMR_CPRE_MCK_DIV_256 0x00000008\n#define AVR32_PWM_CMR_CPRE_MCK_DIV_32 0x00000005\n#define AVR32_PWM_CMR_CPRE_MCK_DIV_4 0x00000002\n#define AVR32_PWM_CMR_CPRE_MCK_DIV_512 0x00000009\n#define AVR32_PWM_CMR_CPRE_MCK_DIV_64 0x00000006\n#define AVR32_PWM_CMR_CPRE_MCK_DIV_8 0x00000003\n#define AVR32_PWM_CMR_CPRE_OFFSET 0\n#define AVR32_PWM_CMR_CPRE_SIZE 4\n#define AVR32_PWM_CNT 0\n#define AVR32_PWM_CNT_MASK 0xffffffff\n#define AVR32_PWM_CNT_OFFSET 0\n#define AVR32_PWM_CNT_SIZE 32\n#define AVR32_PWM_CPD 10\n#define AVR32_PWM_CPD_MASK 0x00000400\n#define AVR32_PWM_CPD_OFFSET 10\n#define AVR32_PWM_CPD_SIZE 1\n#define AVR32_PWM_CPOL 9\n#define AVR32_PWM_CPOL_MASK 0x00000200\n#define AVR32_PWM_CPOL_OFFSET 9\n#define AVR32_PWM_CPOL_SIZE 1\n#define AVR32_PWM_CPRD 0x00000208\n#define AVR32_PWM_CPRD_CPRD 0\n#define AVR32_PWM_CPRD_CPRD_MASK 0xffffffff\n#define AVR32_PWM_CPRD_CPRD_OFFSET 0\n#define AVR32_PWM_CPRD_CPRD_SIZE 32\n#define AVR32_PWM_CPRD_MASK 0xffffffff\n#define AVR32_PWM_CPRD_OFFSET 0\n#define AVR32_PWM_CPRD_SIZE 32\n#define AVR32_PWM_CPRE 0\n#define AVR32_PWM_CPRE_CLKA 0x0000000b\n#define AVR32_PWM_CPRE_CLKB 0x0000000c\n#define AVR32_PWM_CPRE_MASK 0x0000000f\n#define AVR32_PWM_CPRE_MCK 0x00000000\n#define AVR32_PWM_CPRE_MCK_DIV_1024 0x0000000a\n#define AVR32_PWM_CPRE_MCK_DIV_128 0x00000007\n#define AVR32_PWM_CPRE_MCK_DIV_16 0x00000004\n#define AVR32_PWM_CPRE_MCK_DIV_2 0x00000001\n#define AVR32_PWM_CPRE_MCK_DIV_256 0x00000008\n#define AVR32_PWM_CPRE_MCK_DIV_32 0x00000005\n#define AVR32_PWM_CPRE_MCK_DIV_4 0x00000002\n#define AVR32_PWM_CPRE_MCK_DIV_512 0x00000009\n#define AVR32_PWM_CPRE_MCK_DIV_64 0x00000006\n#define AVR32_PWM_CPRE_MCK_DIV_8 0x00000003\n#define AVR32_PWM_CPRE_OFFSET 0\n#define AVR32_PWM_CPRE_SIZE 4\n#define AVR32_PWM_CUPD 0x00000210\n#define AVR32_PWM_CUPD_CUPD 0\n#define AVR32_PWM_CUPD_CUPD_MASK 0xffffffff\n#define AVR32_PWM_CUPD_CUPD_OFFSET 0\n#define AVR32_PWM_CUPD_CUPD_SIZE 32\n#define AVR32_PWM_CUPD_MASK 0xffffffff\n#define AVR32_PWM_CUPD_OFFSET 0\n#define AVR32_PWM_CUPD_SIZE 32\n#define AVR32_PWM_DIS 0x00000008\n#define AVR32_PWM_DIS_CHID0 0\n#define AVR32_PWM_DIS_CHID0_MASK 0x00000001\n#define AVR32_PWM_DIS_CHID0_OFFSET 0\n#define AVR32_PWM_DIS_CHID0_SIZE 1\n#define AVR32_PWM_DIS_CHID1 1\n#define AVR32_PWM_DIS_CHID1_MASK 0x00000002\n#define AVR32_PWM_DIS_CHID1_OFFSET 1\n#define AVR32_PWM_DIS_CHID1_SIZE 1\n#define AVR32_PWM_DIS_CHID2 2\n#define AVR32_PWM_DIS_CHID2_MASK 0x00000004\n#define AVR32_PWM_DIS_CHID2_OFFSET 2\n#define AVR32_PWM_DIS_CHID2_SIZE 1\n#define AVR32_PWM_DIS_CHID3 3\n#define AVR32_PWM_DIS_CHID3_MASK 0x00000008\n#define AVR32_PWM_DIS_CHID3_OFFSET 3\n#define AVR32_PWM_DIS_CHID3_SIZE 1\n#define AVR32_PWM_DIS_CHID4 4\n#define AVR32_PWM_DIS_CHID4_MASK 0x00000010\n#define AVR32_PWM_DIS_CHID4_OFFSET 4\n#define AVR32_PWM_DIS_CHID4_SIZE 1\n#define AVR32_PWM_DIS_CHID5 5\n#define AVR32_PWM_DIS_CHID5_MASK 0x00000020\n#define AVR32_PWM_DIS_CHID5_OFFSET 5\n#define AVR32_PWM_DIS_CHID5_SIZE 1\n#define AVR32_PWM_DIS_CHID6 6\n#define AVR32_PWM_DIS_CHID6_MASK 0x00000040\n#define AVR32_PWM_DIS_CHID6_OFFSET 6\n#define AVR32_PWM_DIS_CHID6_SIZE 1\n#define AVR32_PWM_DIVA 0\n#define AVR32_PWM_DIVA_CLK_OFF 0x00000000\n#define AVR32_PWM_DIVA_CLK_SEL_PREAB 0x00000001\n#define AVR32_PWM_DIVA_MASK 0x000000ff\n#define AVR32_PWM_DIVA_OFFSET 0\n#define AVR32_PWM_DIVA_SIZE 8\n#define AVR32_PWM_DIVB 16\n#define AVR32_PWM_DIVB_CLK_OFF 0x00000000\n#define AVR32_PWM_DIVB_CLK_SEL_PREAB 0x00000001\n#define AVR32_PWM_DIVB_MASK 0x00ff0000\n#define AVR32_PWM_DIVB_OFFSET 16\n#define AVR32_PWM_DIVB_SIZE 8\n#define AVR32_PWM_ENA 0x00000004\n#define AVR32_PWM_ENA_CHID0 0\n#define AVR32_PWM_ENA_CHID0_MASK 0x00000001\n#define AVR32_PWM_ENA_CHID0_OFFSET 0\n#define AVR32_PWM_ENA_CHID0_SIZE 1\n#define AVR32_PWM_ENA_CHID1 1\n#define AVR32_PWM_ENA_CHID1_MASK 0x00000002\n#define AVR32_PWM_ENA_CHID1_OFFSET 1\n#define AVR32_PWM_ENA_CHID1_SIZE 1\n#define AVR32_PWM_ENA_CHID2 2\n#define AVR32_PWM_ENA_CHID2_MASK 0x00000004\n#define AVR32_PWM_ENA_CHID2_OFFSET 2\n#define AVR32_PWM_ENA_CHID2_SIZE 1\n#define AVR32_PWM_ENA_CHID3 3\n#define AVR32_PWM_ENA_CHID3_MASK 0x00000008\n#define AVR32_PWM_ENA_CHID3_OFFSET 3\n#define AVR32_PWM_ENA_CHID3_SIZE 1\n#define AVR32_PWM_ENA_CHID4 4\n#define AVR32_PWM_ENA_CHID4_MASK 0x00000010\n#define AVR32_PWM_ENA_CHID4_OFFSET 4\n#define AVR32_PWM_ENA_CHID4_SIZE 1\n#define AVR32_PWM_ENA_CHID5 5\n#define AVR32_PWM_ENA_CHID5_MASK 0x00000020\n#define AVR32_PWM_ENA_CHID5_OFFSET 5\n#define AVR32_PWM_ENA_CHID5_SIZE 1\n#define AVR32_PWM_ENA_CHID6 6\n#define AVR32_PWM_ENA_CHID6_MASK 0x00000040\n#define AVR32_PWM_ENA_CHID6_OFFSET 6\n#define AVR32_PWM_ENA_CHID6_SIZE 1\n#define AVR32_PWM_IDR 0x00000014\n#define AVR32_PWM_IDR_CHID0 0\n#define AVR32_PWM_IDR_CHID0_MASK 0x00000001\n#define AVR32_PWM_IDR_CHID0_OFFSET 0\n#define AVR32_PWM_IDR_CHID0_SIZE 1\n#define AVR32_PWM_IDR_CHID1 1\n#define AVR32_PWM_IDR_CHID1_MASK 0x00000002\n#define AVR32_PWM_IDR_CHID1_OFFSET 1\n#define AVR32_PWM_IDR_CHID1_SIZE 1\n#define AVR32_PWM_IDR_CHID2 2\n#define AVR32_PWM_IDR_CHID2_MASK 0x00000004\n#define AVR32_PWM_IDR_CHID2_OFFSET 2\n#define AVR32_PWM_IDR_CHID2_SIZE 1\n#define AVR32_PWM_IDR_CHID3 3\n#define AVR32_PWM_IDR_CHID3_MASK 0x00000008\n#define AVR32_PWM_IDR_CHID3_OFFSET 3\n#define AVR32_PWM_IDR_CHID3_SIZE 1\n#define AVR32_PWM_IDR_CHID4 4\n#define AVR32_PWM_IDR_CHID4_MASK 0x00000010\n#define AVR32_PWM_IDR_CHID4_OFFSET 4\n#define AVR32_PWM_IDR_CHID4_SIZE 1\n#define AVR32_PWM_IDR_CHID5 5\n#define AVR32_PWM_IDR_CHID5_MASK 0x00000020\n#define AVR32_PWM_IDR_CHID5_OFFSET 5\n#define AVR32_PWM_IDR_CHID5_SIZE 1\n#define AVR32_PWM_IDR_CHID6 6\n#define AVR32_PWM_IDR_CHID6_MASK 0x00000040\n#define AVR32_PWM_IDR_CHID6_OFFSET 6\n#define AVR32_PWM_IDR_CHID6_SIZE 1\n#define AVR32_PWM_IER 0x00000010\n#define AVR32_PWM_IER_CHID0 0\n#define AVR32_PWM_IER_CHID0_MASK 0x00000001\n#define AVR32_PWM_IER_CHID0_OFFSET 0\n#define AVR32_PWM_IER_CHID0_SIZE 1\n#define AVR32_PWM_IER_CHID1 1\n#define AVR32_PWM_IER_CHID1_MASK 0x00000002\n#define AVR32_PWM_IER_CHID1_OFFSET 1\n#define AVR32_PWM_IER_CHID1_SIZE 1\n#define AVR32_PWM_IER_CHID2 2\n#define AVR32_PWM_IER_CHID2_MASK 0x00000004\n#define AVR32_PWM_IER_CHID2_OFFSET 2\n#define AVR32_PWM_IER_CHID2_SIZE 1\n#define AVR32_PWM_IER_CHID3 3\n#define AVR32_PWM_IER_CHID3_MASK 0x00000008\n#define AVR32_PWM_IER_CHID3_OFFSET 3\n#define AVR32_PWM_IER_CHID3_SIZE 1\n#define AVR32_PWM_IER_CHID4 4\n#define AVR32_PWM_IER_CHID4_MASK 0x00000010\n#define AVR32_PWM_IER_CHID4_OFFSET 4\n#define AVR32_PWM_IER_CHID4_SIZE 1\n#define AVR32_PWM_IER_CHID5 5\n#define AVR32_PWM_IER_CHID5_MASK 0x00000020\n#define AVR32_PWM_IER_CHID5_OFFSET 5\n#define AVR32_PWM_IER_CHID5_SIZE 1\n#define AVR32_PWM_IER_CHID6 6\n#define AVR32_PWM_IER_CHID6_MASK 0x00000040\n#define AVR32_PWM_IER_CHID6_OFFSET 6\n#define AVR32_PWM_IER_CHID6_SIZE 1\n#define AVR32_PWM_IMR 0x00000018\n#define AVR32_PWM_IMR_CHID0 0\n#define AVR32_PWM_IMR_CHID0_MASK 0x00000001\n#define AVR32_PWM_IMR_CHID0_OFFSET 0\n#define AVR32_PWM_IMR_CHID0_SIZE 1\n#define AVR32_PWM_IMR_CHID1 1\n#define AVR32_PWM_IMR_CHID1_MASK 0x00000002\n#define AVR32_PWM_IMR_CHID1_OFFSET 1\n#define AVR32_PWM_IMR_CHID1_SIZE 1\n#define AVR32_PWM_IMR_CHID2 2\n#define AVR32_PWM_IMR_CHID2_MASK 0x00000004\n#define AVR32_PWM_IMR_CHID2_OFFSET 2\n#define AVR32_PWM_IMR_CHID2_SIZE 1\n#define AVR32_PWM_IMR_CHID3 3\n#define AVR32_PWM_IMR_CHID3_MASK 0x00000008\n#define AVR32_PWM_IMR_CHID3_OFFSET 3\n#define AVR32_PWM_IMR_CHID3_SIZE 1\n#define AVR32_PWM_IMR_CHID4 4\n#define AVR32_PWM_IMR_CHID4_MASK 0x00000010\n#define AVR32_PWM_IMR_CHID4_OFFSET 4\n#define AVR32_PWM_IMR_CHID4_SIZE 1\n#define AVR32_PWM_IMR_CHID5 5\n#define AVR32_PWM_IMR_CHID5_MASK 0x00000020\n#define AVR32_PWM_IMR_CHID5_OFFSET 5\n#define AVR32_PWM_IMR_CHID5_SIZE 1\n#define AVR32_PWM_IMR_CHID6 6\n#define AVR32_PWM_IMR_CHID6_MASK 0x00000040\n#define AVR32_PWM_IMR_CHID6_OFFSET 6\n#define AVR32_PWM_IMR_CHID6_SIZE 1\n#define AVR32_PWM_ISR 0x0000001c\n#define AVR32_PWM_ISR_CHID0 0\n#define AVR32_PWM_ISR_CHID0_MASK 0x00000001\n#define AVR32_PWM_ISR_CHID0_OFFSET 0\n#define AVR32_PWM_ISR_CHID0_SIZE 1\n#define AVR32_PWM_ISR_CHID1 1\n#define AVR32_PWM_ISR_CHID1_MASK 0x00000002\n#define AVR32_PWM_ISR_CHID1_OFFSET 1\n#define AVR32_PWM_ISR_CHID1_SIZE 1\n#define AVR32_PWM_ISR_CHID2 2\n#define AVR32_PWM_ISR_CHID2_MASK 0x00000004\n#define AVR32_PWM_ISR_CHID2_OFFSET 2\n#define AVR32_PWM_ISR_CHID2_SIZE 1\n#define AVR32_PWM_ISR_CHID3 3\n#define AVR32_PWM_ISR_CHID3_MASK 0x00000008\n#define AVR32_PWM_ISR_CHID3_OFFSET 3\n#define AVR32_PWM_ISR_CHID3_SIZE 1\n#define AVR32_PWM_ISR_CHID4 4\n#define AVR32_PWM_ISR_CHID4_MASK 0x00000010\n#define AVR32_PWM_ISR_CHID4_OFFSET 4\n#define AVR32_PWM_ISR_CHID4_SIZE 1\n#define AVR32_PWM_ISR_CHID5 5\n#define AVR32_PWM_ISR_CHID5_MASK 0x00000020\n#define AVR32_PWM_ISR_CHID5_OFFSET 5\n#define AVR32_PWM_ISR_CHID5_SIZE 1\n#define AVR32_PWM_ISR_CHID6 6\n#define AVR32_PWM_ISR_CHID6_MASK 0x00000040\n#define AVR32_PWM_ISR_CHID6_OFFSET 6\n#define AVR32_PWM_ISR_CHID6_SIZE 1\n#define AVR32_PWM_MCK 0x00000000\n#define AVR32_PWM_MCK_DIV_1024 0x0000000a\n#define AVR32_PWM_MCK_DIV_128 0x00000007\n#define AVR32_PWM_MCK_DIV_16 0x00000004\n#define AVR32_PWM_MCK_DIV_2 0x00000001\n#define AVR32_PWM_MCK_DIV_256 0x00000008\n#define AVR32_PWM_MCK_DIV_32 0x00000005\n#define AVR32_PWM_MCK_DIV_4 0x00000002\n#define AVR32_PWM_MCK_DIV_512 0x00000009\n#define AVR32_PWM_MCK_DIV_64 0x00000006\n#define AVR32_PWM_MCK_DIV_8 0x00000003\n#define AVR32_PWM_MR 0x00000000\n#define AVR32_PWM_MR_DIVA 0\n#define AVR32_PWM_MR_DIVA_CLK_OFF 0x00000000\n#define AVR32_PWM_MR_DIVA_CLK_SEL_PREAB 0x00000001\n#define AVR32_PWM_MR_DIVA_MASK 0x000000ff\n#define AVR32_PWM_MR_DIVA_OFFSET 0\n#define AVR32_PWM_MR_DIVA_SIZE 8\n#define AVR32_PWM_MR_DIVB 16\n#define AVR32_PWM_MR_DIVB_CLK_OFF 0x00000000\n#define AVR32_PWM_MR_DIVB_CLK_SEL_PREAB 0x00000001\n#define AVR32_PWM_MR_DIVB_MASK 0x00ff0000\n#define AVR32_PWM_MR_DIVB_OFFSET 16\n#define AVR32_PWM_MR_DIVB_SIZE 8\n#define AVR32_PWM_MR_PREA 8\n#define AVR32_PWM_MR_PREA_MASK 0x00000f00\n#define AVR32_PWM_MR_PREA_MCK 0x00000000\n#define AVR32_PWM_MR_PREA_MCK_DIV_1024 0x0000000a\n#define AVR32_PWM_MR_PREA_MCK_DIV_128 0x00000007\n#define AVR32_PWM_MR_PREA_MCK_DIV_16 0x00000004\n#define AVR32_PWM_MR_PREA_MCK_DIV_2 0x00000001\n#define AVR32_PWM_MR_PREA_MCK_DIV_256 0x00000008\n#define AVR32_PWM_MR_PREA_MCK_DIV_32 0x00000005\n#define AVR32_PWM_MR_PREA_MCK_DIV_4 0x00000002\n#define AVR32_PWM_MR_PREA_MCK_DIV_512 0x00000009\n#define AVR32_PWM_MR_PREA_MCK_DIV_64 0x00000006\n#define AVR32_PWM_MR_PREA_MCK_DIV_8 0x00000003\n#define AVR32_PWM_MR_PREA_OFFSET 8\n#define AVR32_PWM_MR_PREA_SIZE 4\n#define AVR32_PWM_MR_PREB 24\n#define AVR32_PWM_MR_PREB_MASK 0x0f000000\n#define AVR32_PWM_MR_PREB_MCK 0x00000000\n#define AVR32_PWM_MR_PREB_MCK_DIV_1024 0x0000000a\n#define AVR32_PWM_MR_PREB_MCK_DIV_128 0x00000007\n#define AVR32_PWM_MR_PREB_MCK_DIV_16 0x00000004\n#define AVR32_PWM_MR_PREB_MCK_DIV_2 0x00000001\n#define AVR32_PWM_MR_PREB_MCK_DIV_256 0x00000008\n#define AVR32_PWM_MR_PREB_MCK_DIV_32 0x00000005\n#define AVR32_PWM_MR_PREB_MCK_DIV_4 0x00000002\n#define AVR32_PWM_MR_PREB_MCK_DIV_512 0x00000009\n#define AVR32_PWM_MR_PREB_MCK_DIV_64 0x00000006\n#define AVR32_PWM_MR_PREB_MCK_DIV_8 0x00000003\n#define AVR32_PWM_MR_PREB_OFFSET 24\n#define AVR32_PWM_MR_PREB_SIZE 4\n#define AVR32_PWM_PREA 8\n#define AVR32_PWM_PREA_MASK 0x00000f00\n#define AVR32_PWM_PREA_MCK 0x00000000\n#define AVR32_PWM_PREA_MCK_DIV_1024 0x0000000a\n#define AVR32_PWM_PREA_MCK_DIV_128 0x00000007\n#define AVR32_PWM_PREA_MCK_DIV_16 0x00000004\n#define AVR32_PWM_PREA_MCK_DIV_2 0x00000001\n#define AVR32_PWM_PREA_MCK_DIV_256 0x00000008\n#define AVR32_PWM_PREA_MCK_DIV_32 0x00000005\n#define AVR32_PWM_PREA_MCK_DIV_4 0x00000002\n#define AVR32_PWM_PREA_MCK_DIV_512 0x00000009\n#define AVR32_PWM_PREA_MCK_DIV_64 0x00000006\n#define AVR32_PWM_PREA_MCK_DIV_8 0x00000003\n#define AVR32_PWM_PREA_OFFSET 8\n#define AVR32_PWM_PREA_SIZE 4\n#define AVR32_PWM_PREB 24\n#define AVR32_PWM_PREB_MASK 0x0f000000\n#define AVR32_PWM_PREB_MCK 0x00000000\n#define AVR32_PWM_PREB_MCK_DIV_1024 0x0000000a\n#define AVR32_PWM_PREB_MCK_DIV_128 0x00000007\n#define AVR32_PWM_PREB_MCK_DIV_16 0x00000004\n#define AVR32_PWM_PREB_MCK_DIV_2 0x00000001\n#define AVR32_PWM_PREB_MCK_DIV_256 0x00000008\n#define AVR32_PWM_PREB_MCK_DIV_32 0x00000005\n#define AVR32_PWM_PREB_MCK_DIV_4 0x00000002\n#define AVR32_PWM_PREB_MCK_DIV_512 0x00000009\n#define AVR32_PWM_PREB_MCK_DIV_64 0x00000006\n#define AVR32_PWM_PREB_MCK_DIV_8 0x00000003\n#define AVR32_PWM_PREB_OFFSET 24\n#define AVR32_PWM_PREB_SIZE 4\n#define AVR32_PWM_SR 0x0000000c\n#define AVR32_PWM_SR_CHID0 0\n#define AVR32_PWM_SR_CHID0_MASK 0x00000001\n#define AVR32_PWM_SR_CHID0_OFFSET 0\n#define AVR32_PWM_SR_CHID0_SIZE 1\n#define AVR32_PWM_SR_CHID1 1\n#define AVR32_PWM_SR_CHID1_MASK 0x00000002\n#define AVR32_PWM_SR_CHID1_OFFSET 1\n#define AVR32_PWM_SR_CHID1_SIZE 1\n#define AVR32_PWM_SR_CHID2 2\n#define AVR32_PWM_SR_CHID2_MASK 0x00000004\n#define AVR32_PWM_SR_CHID2_OFFSET 2\n#define AVR32_PWM_SR_CHID2_SIZE 1\n#define AVR32_PWM_SR_CHID3 3\n#define AVR32_PWM_SR_CHID3_MASK 0x00000008\n#define AVR32_PWM_SR_CHID3_OFFSET 3\n#define AVR32_PWM_SR_CHID3_SIZE 1\n#define AVR32_PWM_SR_CHID4 4\n#define AVR32_PWM_SR_CHID4_MASK 0x00000010\n#define AVR32_PWM_SR_CHID4_OFFSET 4\n#define AVR32_PWM_SR_CHID4_SIZE 1\n#define AVR32_PWM_SR_CHID5 5\n#define AVR32_PWM_SR_CHID5_MASK 0x00000020\n#define AVR32_PWM_SR_CHID5_OFFSET 5\n#define AVR32_PWM_SR_CHID5_SIZE 1\n#define AVR32_PWM_SR_CHID6 6\n#define AVR32_PWM_SR_CHID6_MASK 0x00000040\n#define AVR32_PWM_SR_CHID6_OFFSET 6\n#define AVR32_PWM_SR_CHID6_SIZE 1\n#define AVR32_PWM_VARIANT 16\n#define AVR32_PWM_VARIANT_MASK 0x00070000\n#define AVR32_PWM_VARIANT_OFFSET 16\n#define AVR32_PWM_VARIANT_SIZE 3\n#define AVR32_PWM_VERSION 0x000000fc\n#define AVR32_PWM_VERSION_MASK 0x00000fff\n#define AVR32_PWM_VERSION_OFFSET 0\n#define AVR32_PWM_VERSION_SIZE 12\n#define AVR32_PWM_VERSION_VARIANT 16\n#define AVR32_PWM_VERSION_VARIANT_MASK 0x00070000\n#define AVR32_PWM_VERSION_VARIANT_OFFSET 16\n#define AVR32_PWM_VERSION_VARIANT_SIZE 3\n#define AVR32_PWM_VERSION_VERSION 0\n#define AVR32_PWM_VERSION_VERSION_MASK 0x00000fff\n#define AVR32_PWM_VERSION_VERSION_OFFSET 0\n#define AVR32_PWM_VERSION_VERSION_SIZE 12\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_pwm_mr_t {\n unsigned int : 4;\n unsigned int preb : 4;\n unsigned int divb : 8;\n unsigned int : 4;\n unsigned int prea : 4;\n unsigned int diva : 8;\n} avr32_pwm_mr_t;\n\n\n\ntypedef struct avr32_pwm_ena_t {\n unsigned int :25;\n unsigned int chid6 : 1;\n unsigned int chid5 : 1;\n unsigned int chid4 : 1;\n unsigned int chid3 : 1;\n unsigned int chid2 : 1;\n unsigned int chid1 : 1;\n unsigned int chid0 : 1;\n} avr32_pwm_ena_t;\n\n\n\ntypedef struct avr32_pwm_dis_t {\n unsigned int :25;\n unsigned int chid6 : 1;\n unsigned int chid5 : 1;\n unsigned int chid4 : 1;\n unsigned int chid3 : 1;\n unsigned int chid2 : 1;\n unsigned int chid1 : 1;\n unsigned int chid0 : 1;\n} avr32_pwm_dis_t;\n\n\n\ntypedef struct avr32_pwm_sr_t {\n unsigned int :25;\n unsigned int chid6 : 1;\n unsigned int chid5 : 1;\n unsigned int chid4 : 1;\n unsigned int chid3 : 1;\n unsigned int chid2 : 1;\n unsigned int chid1 : 1;\n unsigned int chid0 : 1;\n} avr32_pwm_sr_t;\n\n\n\ntypedef struct avr32_pwm_ier_t {\n unsigned int :25;\n unsigned int chid6 : 1;\n unsigned int chid5 : 1;\n unsigned int chid4 : 1;\n unsigned int chid3 : 1;\n unsigned int chid2 : 1;\n unsigned int chid1 : 1;\n unsigned int chid0 : 1;\n} avr32_pwm_ier_t;\n\n\n\ntypedef struct avr32_pwm_idr_t {\n unsigned int :25;\n unsigned int chid6 : 1;\n unsigned int chid5 : 1;\n unsigned int chid4 : 1;\n unsigned int chid3 : 1;\n unsigned int chid2 : 1;\n unsigned int chid1 : 1;\n unsigned int chid0 : 1;\n} avr32_pwm_idr_t;\n\n\n\ntypedef struct avr32_pwm_imr_t {\n unsigned int :25;\n unsigned int chid6 : 1;\n unsigned int chid5 : 1;\n unsigned int chid4 : 1;\n unsigned int chid3 : 1;\n unsigned int chid2 : 1;\n unsigned int chid1 : 1;\n unsigned int chid0 : 1;\n} avr32_pwm_imr_t;\n\n\n\ntypedef struct avr32_pwm_isr_t {\n unsigned int :25;\n unsigned int chid6 : 1;\n unsigned int chid5 : 1;\n unsigned int chid4 : 1;\n unsigned int chid3 : 1;\n unsigned int chid2 : 1;\n unsigned int chid1 : 1;\n unsigned int chid0 : 1;\n} avr32_pwm_isr_t;\n\n\n\ntypedef struct avr32_pwm_version_t {\n unsigned int :13;\n unsigned int variant : 3;\n unsigned int : 4;\n unsigned int version :12;\n} avr32_pwm_version_t;\n\n\n\ntypedef struct avr32_pwm_cmr_t {\n unsigned int :21;\n unsigned int cpd : 1;\n unsigned int cpol : 1;\n unsigned int calg : 1;\n unsigned int : 4;\n unsigned int cpre : 4;\n} avr32_pwm_cmr_t;\n\n\ntypedef struct avr32_pwm_channel_t {\n union {\n unsigned long cmr ;//0x0000\n avr32_pwm_cmr_t CMR ;\n };\n unsigned long cdty ;//0x0004\n unsigned long cprd ;//0x0008\n const unsigned long ccnt ;//0x000c\n unsigned long cupd ;//0x0010\n unsigned int :32 ;//0x0014\n unsigned int :32 ;//0x0018\n unsigned int :32 ;//0x001c\n} avr32_pwm_channel_t;\n\n\ntypedef struct avr32_pwm_t {\n union {\n unsigned long mr ;//0x0000\n avr32_pwm_mr_t MR ;\n };\n union {\n unsigned long ena ;//0x0004\n avr32_pwm_ena_t ENA ;\n };\n union {\n unsigned long dis ;//0x0008\n avr32_pwm_dis_t DIS ;\n };\n union {\n const unsigned long sr ;//0x000c\n const avr32_pwm_sr_t SR ;\n };\n union {\n unsigned long ier ;//0x0010\n avr32_pwm_ier_t IER ;\n };\n union {\n unsigned long idr ;//0x0014\n avr32_pwm_idr_t IDR ;\n };\n union {\n const unsigned long imr ;//0x0018\n const avr32_pwm_imr_t IMR ;\n };\n union {\n const unsigned long isr ;//0x001c\n const avr32_pwm_isr_t ISR ;\n };\n unsigned int :32 ;//0x0020\n unsigned int :32 ;//0x0024\n unsigned int :32 ;//0x0028\n unsigned int :32 ;//0x002c\n unsigned int :32 ;//0x0030\n unsigned int :32 ;//0x0034\n unsigned int :32 ;//0x0038\n unsigned int :32 ;//0x003c\n unsigned int :32 ;//0x0040\n unsigned int :32 ;//0x0044\n unsigned int :32 ;//0x0048\n unsigned int :32 ;//0x004c\n unsigned int :32 ;//0x0050\n unsigned int :32 ;//0x0054\n unsigned int :32 ;//0x0058\n unsigned int :32 ;//0x005c\n unsigned int :32 ;//0x0060\n unsigned int :32 ;//0x0064\n unsigned int :32 ;//0x0068\n unsigned int :32 ;//0x006c\n unsigned int :32 ;//0x0070\n unsigned int :32 ;//0x0074\n unsigned int :32 ;//0x0078\n unsigned int :32 ;//0x007c\n unsigned int :32 ;//0x0080\n unsigned int :32 ;//0x0084\n unsigned int :32 ;//0x0088\n unsigned int :32 ;//0x008c\n unsigned int :32 ;//0x0090\n unsigned int :32 ;//0x0094\n unsigned int :32 ;//0x0098\n unsigned int :32 ;//0x009c\n unsigned int :32 ;//0x00a0\n unsigned int :32 ;//0x00a4\n unsigned int :32 ;//0x00a8\n unsigned int :32 ;//0x00ac\n unsigned int :32 ;//0x00b0\n unsigned int :32 ;//0x00b4\n unsigned int :32 ;//0x00b8\n unsigned int :32 ;//0x00bc\n unsigned int :32 ;//0x00c0\n unsigned int :32 ;//0x00c4\n unsigned int :32 ;//0x00c8\n unsigned int :32 ;//0x00cc\n unsigned int :32 ;//0x00d0\n unsigned int :32 ;//0x00d4\n unsigned int :32 ;//0x00d8\n unsigned int :32 ;//0x00dc\n unsigned int :32 ;//0x00e0\n unsigned int :32 ;//0x00e4\n unsigned int :32 ;//0x00e8\n unsigned int :32 ;//0x00ec\n unsigned int :32 ;//0x00f0\n unsigned int :32 ;//0x00f4\n unsigned int :32 ;//0x00f8\n union {\n const unsigned long version ;//0x00fc\n const avr32_pwm_version_t VERSION ;\n };\n unsigned int :32 ;//0x0100\n unsigned int :32 ;//0x0104\n unsigned int :32 ;//0x0108\n unsigned int :32 ;//0x010c\n unsigned int :32 ;//0x0110\n unsigned int :32 ;//0x0114\n unsigned int :32 ;//0x0118\n unsigned int :32 ;//0x011c\n unsigned int :32 ;//0x0120\n unsigned int :32 ;//0x0124\n unsigned int :32 ;//0x0128\n unsigned int :32 ;//0x012c\n unsigned int :32 ;//0x0130\n unsigned int :32 ;//0x0134\n unsigned int :32 ;//0x0138\n unsigned int :32 ;//0x013c\n unsigned int :32 ;//0x0140\n unsigned int :32 ;//0x0144\n unsigned int :32 ;//0x0148\n unsigned int :32 ;//0x014c\n unsigned int :32 ;//0x0150\n unsigned int :32 ;//0x0154\n unsigned int :32 ;//0x0158\n unsigned int :32 ;//0x015c\n unsigned int :32 ;//0x0160\n unsigned int :32 ;//0x0164\n unsigned int :32 ;//0x0168\n unsigned int :32 ;//0x016c\n unsigned int :32 ;//0x0170\n unsigned int :32 ;//0x0174\n unsigned int :32 ;//0x0178\n unsigned int :32 ;//0x017c\n unsigned int :32 ;//0x0180\n unsigned int :32 ;//0x0184\n unsigned int :32 ;//0x0188\n unsigned int :32 ;//0x018c\n unsigned int :32 ;//0x0190\n unsigned int :32 ;//0x0194\n unsigned int :32 ;//0x0198\n unsigned int :32 ;//0x019c\n unsigned int :32 ;//0x01a0\n unsigned int :32 ;//0x01a4\n unsigned int :32 ;//0x01a8\n unsigned int :32 ;//0x01ac\n unsigned int :32 ;//0x01b0\n unsigned int :32 ;//0x01b4\n unsigned int :32 ;//0x01b8\n unsigned int :32 ;//0x01bc\n unsigned int :32 ;//0x01c0\n unsigned int :32 ;//0x01c4\n unsigned int :32 ;//0x01c8\n unsigned int :32 ;//0x01cc\n unsigned int :32 ;//0x01d0\n unsigned int :32 ;//0x01d4\n unsigned int :32 ;//0x01d8\n unsigned int :32 ;//0x01dc\n unsigned int :32 ;//0x01e0\n unsigned int :32 ;//0x01e4\n unsigned int :32 ;//0x01e8\n unsigned int :32 ;//0x01ec\n unsigned int :32 ;//0x01f0\n unsigned int :32 ;//0x01f4\n unsigned int :32 ;//0x01f8\n unsigned int :32 ;//0x01fc\n avr32_pwm_channel_t channel[AVR32_PWM_CHANNEL_LENGTH];//0x200\n} avr32_pwm_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n\n#if !defined (DEPRECATED_DISABLE)\n\n#define AVR32_PWM_CCNT0 0x0000020c\n#define AVR32_PWM_CCNT0_CNT 0\n#define AVR32_PWM_CCNT0_CNT_MASK 0xffffffff\n#define AVR32_PWM_CCNT0_CNT_OFFSET 0\n#define AVR32_PWM_CCNT0_CNT_SIZE 32\n\n#define AVR32_PWM_CDTY0 0x00000204\n#define AVR32_PWM_CDTY0_CDTY 0\n#define AVR32_PWM_CDTY0_CDTY_MASK 0xffffffff\n#define AVR32_PWM_CDTY0_CDTY_OFFSET 0\n#define AVR32_PWM_CDTY0_CDTY_SIZE 32\n\n#define AVR32_PWM_CMR0 0x00000200\n#define AVR32_PWM_CMR0_CALG 8\n#define AVR32_PWM_CMR0_CALG_MASK 0x00000100\n#define AVR32_PWM_CMR0_CALG_OFFSET 8\n#define AVR32_PWM_CMR0_CALG_SIZE 1\n#define AVR32_PWM_CMR0_CPD 10\n#define AVR32_PWM_CMR0_CPD_MASK 0x00000400\n#define AVR32_PWM_CMR0_CPD_OFFSET 10\n#define AVR32_PWM_CMR0_CPD_SIZE 1\n#define AVR32_PWM_CMR0_CPOL 9\n#define AVR32_PWM_CMR0_CPOL_MASK 0x00000200\n#define AVR32_PWM_CMR0_CPOL_OFFSET 9\n#define AVR32_PWM_CMR0_CPOL_SIZE 1\n#define AVR32_PWM_CMR0_CPRE 0\n#define AVR32_PWM_CMR0_CPRE_CLKA 0x0000000b\n#define AVR32_PWM_CMR0_CPRE_CLKB 0x0000000c\n#define AVR32_PWM_CMR0_CPRE_MASK 0x0000000f\n#define AVR32_PWM_CMR0_CPRE_MCK 0x00000000\n#define AVR32_PWM_CMR0_CPRE_MCK_DIV_1024 0x0000000a\n#define AVR32_PWM_CMR0_CPRE_MCK_DIV_128 0x00000007\n#define AVR32_PWM_CMR0_CPRE_MCK_DIV_16 0x00000004\n#define AVR32_PWM_CMR0_CPRE_MCK_DIV_2 0x00000001\n#define AVR32_PWM_CMR0_CPRE_MCK_DIV_256 0x00000008\n#define AVR32_PWM_CMR0_CPRE_MCK_DIV_32 0x00000005\n#define AVR32_PWM_CMR0_CPRE_MCK_DIV_4 0x00000002\n#define AVR32_PWM_CMR0_CPRE_MCK_DIV_512 0x00000009\n#define AVR32_PWM_CMR0_CPRE_MCK_DIV_64 0x00000006\n#define AVR32_PWM_CMR0_CPRE_MCK_DIV_8 0x00000003\n#define AVR32_PWM_CMR0_CPRE_OFFSET 0\n#define AVR32_PWM_CMR0_CPRE_SIZE 4\n\n#define AVR32_PWM_CPRD0 0x00000208\n#define AVR32_PWM_CPRD0_CPRD 0\n#define AVR32_PWM_CPRD0_CPRD_MASK 0xffffffff\n#define AVR32_PWM_CPRD0_CPRD_OFFSET 0\n#define AVR32_PWM_CPRD0_CPRD_SIZE 32\n\n#define AVR32_PWM_CUPD0 0x00000210\n#define AVR32_PWM_CUPD0_CUPD 0\n#define AVR32_PWM_CUPD0_CUPD_MASK 0xffffffff\n#define AVR32_PWM_CUPD0_CUPD_OFFSET 0\n#define AVR32_PWM_CUPD0_CUPD_SIZE 32\n\n#endif\n\n\n/*#ifdef AVR32_PWM_130_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/rtc_230.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3000\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_RTC_230_H_INCLUDED\n#define AVR32_RTC_230_H_INCLUDED\n\n#define AVR32_RTC_H_VERSION 230\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_RTC_\n - Bitfield mask: AVR32_RTC__\n - Bitfield offset: AVR32_RTC___OFFSET\n - Bitfield size: AVR32_RTC___SIZE\n - Bitfield values: AVR32_RTC___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_RTC_\n - Bitfield offset: AVR32_RTC__OFFSET\n - Bitfield size: AVR32_RTC__SIZE\n - Bitfield values: AVR32_RTC__\n - Bitfield values: AVR32_RTC_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_RTC_BUSY 4\n#define AVR32_RTC_BUSY_MASK 0x00000010\n#define AVR32_RTC_BUSY_OFFSET 4\n#define AVR32_RTC_BUSY_SIZE 1\n#define AVR32_RTC_CLK32 3\n#define AVR32_RTC_CLK32_MASK 0x00000008\n#define AVR32_RTC_CLK32_OFFSET 3\n#define AVR32_RTC_CLK32_SIZE 1\n#define AVR32_RTC_CLKEN 16\n#define AVR32_RTC_CLKEN_MASK 0x00010000\n#define AVR32_RTC_CLKEN_OFFSET 16\n#define AVR32_RTC_CLKEN_SIZE 1\n#define AVR32_RTC_CTRL 0x00000000\n#define AVR32_RTC_CTRL_BUSY 4\n#define AVR32_RTC_CTRL_BUSY_MASK 0x00000010\n#define AVR32_RTC_CTRL_BUSY_OFFSET 4\n#define AVR32_RTC_CTRL_BUSY_SIZE 1\n#define AVR32_RTC_CTRL_CLK32 3\n#define AVR32_RTC_CTRL_CLK32_MASK 0x00000008\n#define AVR32_RTC_CTRL_CLK32_OFFSET 3\n#define AVR32_RTC_CTRL_CLK32_SIZE 1\n#define AVR32_RTC_CTRL_CLKEN 16\n#define AVR32_RTC_CTRL_CLKEN_MASK 0x00010000\n#define AVR32_RTC_CTRL_CLKEN_OFFSET 16\n#define AVR32_RTC_CTRL_CLKEN_SIZE 1\n#define AVR32_RTC_CTRL_EN 0\n#define AVR32_RTC_CTRL_EN_MASK 0x00000001\n#define AVR32_RTC_CTRL_EN_OFFSET 0\n#define AVR32_RTC_CTRL_EN_SIZE 1\n#define AVR32_RTC_CTRL_PCLR 1\n#define AVR32_RTC_CTRL_PCLR_MASK 0x00000002\n#define AVR32_RTC_CTRL_PCLR_OFFSET 1\n#define AVR32_RTC_CTRL_PCLR_SIZE 1\n#define AVR32_RTC_CTRL_PSEL 8\n#define AVR32_RTC_CTRL_PSEL_MASK 0x00000f00\n#define AVR32_RTC_CTRL_PSEL_OFFSET 8\n#define AVR32_RTC_CTRL_PSEL_SIZE 4\n#define AVR32_RTC_CTRL_WAKE_EN 2\n#define AVR32_RTC_CTRL_WAKE_EN_MASK 0x00000004\n#define AVR32_RTC_CTRL_WAKE_EN_OFFSET 2\n#define AVR32_RTC_CTRL_WAKE_EN_SIZE 1\n#define AVR32_RTC_EN 0\n#define AVR32_RTC_EN_MASK 0x00000001\n#define AVR32_RTC_EN_OFFSET 0\n#define AVR32_RTC_EN_SIZE 1\n#define AVR32_RTC_ICR 0x00000020\n#define AVR32_RTC_ICR_TOPI 0\n#define AVR32_RTC_ICR_TOPI_MASK 0x00000001\n#define AVR32_RTC_ICR_TOPI_OFFSET 0\n#define AVR32_RTC_ICR_TOPI_SIZE 1\n#define AVR32_RTC_IDR 0x00000014\n#define AVR32_RTC_IDR_TOPI 0\n#define AVR32_RTC_IDR_TOPI_MASK 0x00000001\n#define AVR32_RTC_IDR_TOPI_OFFSET 0\n#define AVR32_RTC_IDR_TOPI_SIZE 1\n#define AVR32_RTC_IER 0x00000010\n#define AVR32_RTC_IER_TOPI 0\n#define AVR32_RTC_IER_TOPI_MASK 0x00000001\n#define AVR32_RTC_IER_TOPI_OFFSET 0\n#define AVR32_RTC_IER_TOPI_SIZE 1\n#define AVR32_RTC_IMR 0x00000018\n#define AVR32_RTC_IMR_TOPI 0\n#define AVR32_RTC_IMR_TOPI_MASK 0x00000001\n#define AVR32_RTC_IMR_TOPI_OFFSET 0\n#define AVR32_RTC_IMR_TOPI_SIZE 1\n#define AVR32_RTC_ISR 0x0000001c\n#define AVR32_RTC_ISR_TOPI 0\n#define AVR32_RTC_ISR_TOPI_MASK 0x00000001\n#define AVR32_RTC_ISR_TOPI_OFFSET 0\n#define AVR32_RTC_ISR_TOPI_SIZE 1\n#define AVR32_RTC_PCLR 1\n#define AVR32_RTC_PCLR_MASK 0x00000002\n#define AVR32_RTC_PCLR_OFFSET 1\n#define AVR32_RTC_PCLR_SIZE 1\n#define AVR32_RTC_PSEL 8\n#define AVR32_RTC_PSEL_MASK 0x00000f00\n#define AVR32_RTC_PSEL_OFFSET 8\n#define AVR32_RTC_PSEL_SIZE 4\n#define AVR32_RTC_TOP 0x00000008\n#define AVR32_RTC_TOPI 0\n#define AVR32_RTC_TOPI_MASK 0x00000001\n#define AVR32_RTC_TOPI_OFFSET 0\n#define AVR32_RTC_TOPI_SIZE 1\n#define AVR32_RTC_TOP_VAL 0\n#define AVR32_RTC_TOP_VAL_MASK 0xffffffff\n#define AVR32_RTC_TOP_VAL_OFFSET 0\n#define AVR32_RTC_TOP_VAL_SIZE 32\n#define AVR32_RTC_VAL 0x00000004\n#define AVR32_RTC_VAL_MASK 0xffffffff\n#define AVR32_RTC_VAL_OFFSET 0\n#define AVR32_RTC_VAL_SIZE 32\n#define AVR32_RTC_VAL_VAL 0\n#define AVR32_RTC_VAL_VAL_MASK 0xffffffff\n#define AVR32_RTC_VAL_VAL_OFFSET 0\n#define AVR32_RTC_VAL_VAL_SIZE 32\n#define AVR32_RTC_WAKE_EN 2\n#define AVR32_RTC_WAKE_EN_MASK 0x00000004\n#define AVR32_RTC_WAKE_EN_OFFSET 2\n#define AVR32_RTC_WAKE_EN_SIZE 1\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_rtc_ctrl_t {\n unsigned int :15;\n unsigned int clken : 1;\n unsigned int : 4;\n unsigned int psel : 4;\n unsigned int : 3;\n unsigned int busy : 1;\n unsigned int clk32 : 1;\n unsigned int wake_en : 1;\n unsigned int pclr : 1;\n unsigned int en : 1;\n} avr32_rtc_ctrl_t;\n\n\n\ntypedef struct avr32_rtc_ier_t {\n unsigned int :31;\n unsigned int topi : 1;\n} avr32_rtc_ier_t;\n\n\n\ntypedef struct avr32_rtc_idr_t {\n unsigned int :31;\n unsigned int topi : 1;\n} avr32_rtc_idr_t;\n\n\n\ntypedef struct avr32_rtc_imr_t {\n unsigned int :31;\n unsigned int topi : 1;\n} avr32_rtc_imr_t;\n\n\n\ntypedef struct avr32_rtc_isr_t {\n unsigned int :31;\n unsigned int topi : 1;\n} avr32_rtc_isr_t;\n\n\n\ntypedef struct avr32_rtc_icr_t {\n unsigned int :31;\n unsigned int topi : 1;\n} avr32_rtc_icr_t;\n\n\n\ntypedef struct avr32_rtc_t {\n union {\n unsigned long ctrl ;//0x0000\n avr32_rtc_ctrl_t CTRL ;\n };\n unsigned long val ;//0x0004\n unsigned long top ;//0x0008\n unsigned int :32 ;//0x000c\n union {\n unsigned long ier ;//0x0010\n avr32_rtc_ier_t IER ;\n };\n union {\n unsigned long idr ;//0x0014\n avr32_rtc_idr_t IDR ;\n };\n union {\n const unsigned long imr ;//0x0018\n const avr32_rtc_imr_t IMR ;\n };\n union {\n const unsigned long isr ;//0x001c\n const avr32_rtc_isr_t ISR ;\n };\n union {\n unsigned long icr ;//0x0020\n avr32_rtc_icr_t ICR ;\n };\n} avr32_rtc_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n/*#ifdef AVR32_RTC_230_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/spi_199.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3000\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_SPI_199_H_INCLUDED\n#define AVR32_SPI_199_H_INCLUDED\n\n#define AVR32_SPI_H_VERSION 199\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_SPI_\n - Bitfield mask: AVR32_SPI__\n - Bitfield offset: AVR32_SPI___OFFSET\n - Bitfield size: AVR32_SPI___SIZE\n - Bitfield values: AVR32_SPI___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_SPI_\n - Bitfield offset: AVR32_SPI__OFFSET\n - Bitfield size: AVR32_SPI__SIZE\n - Bitfield values: AVR32_SPI__\n - Bitfield values: AVR32_SPI_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_SPI_10_BPT 0x00000002\n#define AVR32_SPI_11_BPT 0x00000003\n#define AVR32_SPI_12_BPT 0x00000004\n#define AVR32_SPI_13_BPT 0x00000005\n#define AVR32_SPI_14_BPT 0x00000006\n#define AVR32_SPI_15_BPT 0x00000007\n#define AVR32_SPI_16_BPT 0x00000008\n#define AVR32_SPI_8_BPT 0x00000000\n#define AVR32_SPI_9_BPT 0x00000001\n#define AVR32_SPI_BITS 4\n#define AVR32_SPI_BITS_10_BPT 0x00000002\n#define AVR32_SPI_BITS_11_BPT 0x00000003\n#define AVR32_SPI_BITS_12_BPT 0x00000004\n#define AVR32_SPI_BITS_13_BPT 0x00000005\n#define AVR32_SPI_BITS_14_BPT 0x00000006\n#define AVR32_SPI_BITS_15_BPT 0x00000007\n#define AVR32_SPI_BITS_16_BPT 0x00000008\n#define AVR32_SPI_BITS_8_BPT 0x00000000\n#define AVR32_SPI_BITS_9_BPT 0x00000001\n#define AVR32_SPI_BITS_MASK 0x000000f0\n#define AVR32_SPI_BITS_OFFSET 4\n#define AVR32_SPI_BITS_SIZE 4\n#define AVR32_SPI_CPOL 0\n#define AVR32_SPI_CPOL_MASK 0x00000001\n#define AVR32_SPI_CPOL_OFFSET 0\n#define AVR32_SPI_CPOL_SIZE 1\n#define AVR32_SPI_CR 0x00000000\n#define AVR32_SPI_CR_LASTXFER 24\n#define AVR32_SPI_CR_LASTXFER_MASK 0x01000000\n#define AVR32_SPI_CR_LASTXFER_OFFSET 24\n#define AVR32_SPI_CR_LASTXFER_SIZE 1\n#define AVR32_SPI_CR_SPIDIS 1\n#define AVR32_SPI_CR_SPIDIS_MASK 0x00000002\n#define AVR32_SPI_CR_SPIDIS_OFFSET 1\n#define AVR32_SPI_CR_SPIDIS_SIZE 1\n#define AVR32_SPI_CR_SPIEN 0\n#define AVR32_SPI_CR_SPIEN_MASK 0x00000001\n#define AVR32_SPI_CR_SPIEN_OFFSET 0\n#define AVR32_SPI_CR_SPIEN_SIZE 1\n#define AVR32_SPI_CR_SWRST 7\n#define AVR32_SPI_CR_SWRST_MASK 0x00000080\n#define AVR32_SPI_CR_SWRST_OFFSET 7\n#define AVR32_SPI_CR_SWRST_SIZE 1\n#define AVR32_SPI_CSAAT 3\n#define AVR32_SPI_CSAAT_MASK 0x00000008\n#define AVR32_SPI_CSAAT_OFFSET 3\n#define AVR32_SPI_CSAAT_SIZE 1\n#define AVR32_SPI_CSNAAT 2\n#define AVR32_SPI_CSNAAT_MASK 0x00000004\n#define AVR32_SPI_CSNAAT_OFFSET 2\n#define AVR32_SPI_CSNAAT_SIZE 1\n#define AVR32_SPI_CSR0 0x00000030\n#define AVR32_SPI_CSR0_BITS 4\n#define AVR32_SPI_CSR0_BITS_10_BPT 0x00000002\n#define AVR32_SPI_CSR0_BITS_11_BPT 0x00000003\n#define AVR32_SPI_CSR0_BITS_12_BPT 0x00000004\n#define AVR32_SPI_CSR0_BITS_13_BPT 0x00000005\n#define AVR32_SPI_CSR0_BITS_14_BPT 0x00000006\n#define AVR32_SPI_CSR0_BITS_15_BPT 0x00000007\n#define AVR32_SPI_CSR0_BITS_16_BPT 0x00000008\n#define AVR32_SPI_CSR0_BITS_8_BPT 0x00000000\n#define AVR32_SPI_CSR0_BITS_9_BPT 0x00000001\n#define AVR32_SPI_CSR0_BITS_MASK 0x000000f0\n#define AVR32_SPI_CSR0_BITS_OFFSET 4\n#define AVR32_SPI_CSR0_BITS_SIZE 4\n#define AVR32_SPI_CSR0_CPOL 0\n#define AVR32_SPI_CSR0_CPOL_MASK 0x00000001\n#define AVR32_SPI_CSR0_CPOL_OFFSET 0\n#define AVR32_SPI_CSR0_CPOL_SIZE 1\n#define AVR32_SPI_CSR0_CSAAT 3\n#define AVR32_SPI_CSR0_CSAAT_MASK 0x00000008\n#define AVR32_SPI_CSR0_CSAAT_OFFSET 3\n#define AVR32_SPI_CSR0_CSAAT_SIZE 1\n#define AVR32_SPI_CSR0_CSNAAT 2\n#define AVR32_SPI_CSR0_CSNAAT_MASK 0x00000004\n#define AVR32_SPI_CSR0_CSNAAT_OFFSET 2\n#define AVR32_SPI_CSR0_CSNAAT_SIZE 1\n#define AVR32_SPI_CSR0_DLYBCT 24\n#define AVR32_SPI_CSR0_DLYBCT_MASK 0xff000000\n#define AVR32_SPI_CSR0_DLYBCT_OFFSET 24\n#define AVR32_SPI_CSR0_DLYBCT_SIZE 8\n#define AVR32_SPI_CSR0_DLYBS 16\n#define AVR32_SPI_CSR0_DLYBS_MASK 0x00ff0000\n#define AVR32_SPI_CSR0_DLYBS_OFFSET 16\n#define AVR32_SPI_CSR0_DLYBS_SIZE 8\n#define AVR32_SPI_CSR0_NCPHA 1\n#define AVR32_SPI_CSR0_NCPHA_MASK 0x00000002\n#define AVR32_SPI_CSR0_NCPHA_OFFSET 1\n#define AVR32_SPI_CSR0_NCPHA_SIZE 1\n#define AVR32_SPI_CSR0_SCBR 8\n#define AVR32_SPI_CSR0_SCBR_MASK 0x0000ff00\n#define AVR32_SPI_CSR0_SCBR_OFFSET 8\n#define AVR32_SPI_CSR0_SCBR_SIZE 8\n#define AVR32_SPI_CSR1 0x00000034\n#define AVR32_SPI_CSR1_BITS 4\n#define AVR32_SPI_CSR1_BITS_10_BPT 0x00000002\n#define AVR32_SPI_CSR1_BITS_11_BPT 0x00000003\n#define AVR32_SPI_CSR1_BITS_12_BPT 0x00000004\n#define AVR32_SPI_CSR1_BITS_13_BPT 0x00000005\n#define AVR32_SPI_CSR1_BITS_14_BPT 0x00000006\n#define AVR32_SPI_CSR1_BITS_15_BPT 0x00000007\n#define AVR32_SPI_CSR1_BITS_16_BPT 0x00000008\n#define AVR32_SPI_CSR1_BITS_8_BPT 0x00000000\n#define AVR32_SPI_CSR1_BITS_9_BPT 0x00000001\n#define AVR32_SPI_CSR1_BITS_MASK 0x000000f0\n#define AVR32_SPI_CSR1_BITS_OFFSET 4\n#define AVR32_SPI_CSR1_BITS_SIZE 4\n#define AVR32_SPI_CSR1_CPOL 0\n#define AVR32_SPI_CSR1_CPOL_MASK 0x00000001\n#define AVR32_SPI_CSR1_CPOL_OFFSET 0\n#define AVR32_SPI_CSR1_CPOL_SIZE 1\n#define AVR32_SPI_CSR1_CSAAT 3\n#define AVR32_SPI_CSR1_CSAAT_MASK 0x00000008\n#define AVR32_SPI_CSR1_CSAAT_OFFSET 3\n#define AVR32_SPI_CSR1_CSAAT_SIZE 1\n#define AVR32_SPI_CSR1_CSNAAT 2\n#define AVR32_SPI_CSR1_CSNAAT_MASK 0x00000004\n#define AVR32_SPI_CSR1_CSNAAT_OFFSET 2\n#define AVR32_SPI_CSR1_CSNAAT_SIZE 1\n#define AVR32_SPI_CSR1_DLYBCT 24\n#define AVR32_SPI_CSR1_DLYBCT_MASK 0xff000000\n#define AVR32_SPI_CSR1_DLYBCT_OFFSET 24\n#define AVR32_SPI_CSR1_DLYBCT_SIZE 8\n#define AVR32_SPI_CSR1_DLYBS 16\n#define AVR32_SPI_CSR1_DLYBS_MASK 0x00ff0000\n#define AVR32_SPI_CSR1_DLYBS_OFFSET 16\n#define AVR32_SPI_CSR1_DLYBS_SIZE 8\n#define AVR32_SPI_CSR1_NCPHA 1\n#define AVR32_SPI_CSR1_NCPHA_MASK 0x00000002\n#define AVR32_SPI_CSR1_NCPHA_OFFSET 1\n#define AVR32_SPI_CSR1_NCPHA_SIZE 1\n#define AVR32_SPI_CSR1_SCBR 8\n#define AVR32_SPI_CSR1_SCBR_MASK 0x0000ff00\n#define AVR32_SPI_CSR1_SCBR_OFFSET 8\n#define AVR32_SPI_CSR1_SCBR_SIZE 8\n#define AVR32_SPI_CSR2 0x00000038\n#define AVR32_SPI_CSR2_BITS 4\n#define AVR32_SPI_CSR2_BITS_10_BPT 0x00000002\n#define AVR32_SPI_CSR2_BITS_11_BPT 0x00000003\n#define AVR32_SPI_CSR2_BITS_12_BPT 0x00000004\n#define AVR32_SPI_CSR2_BITS_13_BPT 0x00000005\n#define AVR32_SPI_CSR2_BITS_14_BPT 0x00000006\n#define AVR32_SPI_CSR2_BITS_15_BPT 0x00000007\n#define AVR32_SPI_CSR2_BITS_16_BPT 0x00000008\n#define AVR32_SPI_CSR2_BITS_8_BPT 0x00000000\n#define AVR32_SPI_CSR2_BITS_9_BPT 0x00000001\n#define AVR32_SPI_CSR2_BITS_MASK 0x000000f0\n#define AVR32_SPI_CSR2_BITS_OFFSET 4\n#define AVR32_SPI_CSR2_BITS_SIZE 4\n#define AVR32_SPI_CSR2_CPOL 0\n#define AVR32_SPI_CSR2_CPOL_MASK 0x00000001\n#define AVR32_SPI_CSR2_CPOL_OFFSET 0\n#define AVR32_SPI_CSR2_CPOL_SIZE 1\n#define AVR32_SPI_CSR2_CSAAT 3\n#define AVR32_SPI_CSR2_CSAAT_MASK 0x00000008\n#define AVR32_SPI_CSR2_CSAAT_OFFSET 3\n#define AVR32_SPI_CSR2_CSAAT_SIZE 1\n#define AVR32_SPI_CSR2_CSNAAT 2\n#define AVR32_SPI_CSR2_CSNAAT_MASK 0x00000004\n#define AVR32_SPI_CSR2_CSNAAT_OFFSET 2\n#define AVR32_SPI_CSR2_CSNAAT_SIZE 1\n#define AVR32_SPI_CSR2_DLYBCT 24\n#define AVR32_SPI_CSR2_DLYBCT_MASK 0xff000000\n#define AVR32_SPI_CSR2_DLYBCT_OFFSET 24\n#define AVR32_SPI_CSR2_DLYBCT_SIZE 8\n#define AVR32_SPI_CSR2_DLYBS 16\n#define AVR32_SPI_CSR2_DLYBS_MASK 0x00ff0000\n#define AVR32_SPI_CSR2_DLYBS_OFFSET 16\n#define AVR32_SPI_CSR2_DLYBS_SIZE 8\n#define AVR32_SPI_CSR2_NCPHA 1\n#define AVR32_SPI_CSR2_NCPHA_MASK 0x00000002\n#define AVR32_SPI_CSR2_NCPHA_OFFSET 1\n#define AVR32_SPI_CSR2_NCPHA_SIZE 1\n#define AVR32_SPI_CSR2_SCBR 8\n#define AVR32_SPI_CSR2_SCBR_MASK 0x0000ff00\n#define AVR32_SPI_CSR2_SCBR_OFFSET 8\n#define AVR32_SPI_CSR2_SCBR_SIZE 8\n#define AVR32_SPI_CSR3 0x0000003c\n#define AVR32_SPI_CSR3_BITS 4\n#define AVR32_SPI_CSR3_BITS_10_BPT 0x00000002\n#define AVR32_SPI_CSR3_BITS_11_BPT 0x00000003\n#define AVR32_SPI_CSR3_BITS_12_BPT 0x00000004\n#define AVR32_SPI_CSR3_BITS_13_BPT 0x00000005\n#define AVR32_SPI_CSR3_BITS_14_BPT 0x00000006\n#define AVR32_SPI_CSR3_BITS_15_BPT 0x00000007\n#define AVR32_SPI_CSR3_BITS_16_BPT 0x00000008\n#define AVR32_SPI_CSR3_BITS_8_BPT 0x00000000\n#define AVR32_SPI_CSR3_BITS_9_BPT 0x00000001\n#define AVR32_SPI_CSR3_BITS_MASK 0x000000f0\n#define AVR32_SPI_CSR3_BITS_OFFSET 4\n#define AVR32_SPI_CSR3_BITS_SIZE 4\n#define AVR32_SPI_CSR3_CPOL 0\n#define AVR32_SPI_CSR3_CPOL_MASK 0x00000001\n#define AVR32_SPI_CSR3_CPOL_OFFSET 0\n#define AVR32_SPI_CSR3_CPOL_SIZE 1\n#define AVR32_SPI_CSR3_CSAAT 3\n#define AVR32_SPI_CSR3_CSAAT_MASK 0x00000008\n#define AVR32_SPI_CSR3_CSAAT_OFFSET 3\n#define AVR32_SPI_CSR3_CSAAT_SIZE 1\n#define AVR32_SPI_CSR3_CSNAAT 2\n#define AVR32_SPI_CSR3_CSNAAT_MASK 0x00000004\n#define AVR32_SPI_CSR3_CSNAAT_OFFSET 2\n#define AVR32_SPI_CSR3_CSNAAT_SIZE 1\n#define AVR32_SPI_CSR3_DLYBCT 24\n#define AVR32_SPI_CSR3_DLYBCT_MASK 0xff000000\n#define AVR32_SPI_CSR3_DLYBCT_OFFSET 24\n#define AVR32_SPI_CSR3_DLYBCT_SIZE 8\n#define AVR32_SPI_CSR3_DLYBS 16\n#define AVR32_SPI_CSR3_DLYBS_MASK 0x00ff0000\n#define AVR32_SPI_CSR3_DLYBS_OFFSET 16\n#define AVR32_SPI_CSR3_DLYBS_SIZE 8\n#define AVR32_SPI_CSR3_NCPHA 1\n#define AVR32_SPI_CSR3_NCPHA_MASK 0x00000002\n#define AVR32_SPI_CSR3_NCPHA_OFFSET 1\n#define AVR32_SPI_CSR3_NCPHA_SIZE 1\n#define AVR32_SPI_CSR3_SCBR 8\n#define AVR32_SPI_CSR3_SCBR_MASK 0x0000ff00\n#define AVR32_SPI_CSR3_SCBR_OFFSET 8\n#define AVR32_SPI_CSR3_SCBR_SIZE 8\n#define AVR32_SPI_DLYBCS 24\n#define AVR32_SPI_DLYBCS_MASK 0xff000000\n#define AVR32_SPI_DLYBCS_OFFSET 24\n#define AVR32_SPI_DLYBCS_SIZE 8\n#define AVR32_SPI_DLYBCT 24\n#define AVR32_SPI_DLYBCT_MASK 0xff000000\n#define AVR32_SPI_DLYBCT_OFFSET 24\n#define AVR32_SPI_DLYBCT_SIZE 8\n#define AVR32_SPI_DLYBS 16\n#define AVR32_SPI_DLYBS_MASK 0x00ff0000\n#define AVR32_SPI_DLYBS_OFFSET 16\n#define AVR32_SPI_DLYBS_SIZE 8\n#define AVR32_SPI_ENDRX 4\n#define AVR32_SPI_ENDRX_MASK 0x00000010\n#define AVR32_SPI_ENDRX_OFFSET 4\n#define AVR32_SPI_ENDRX_SIZE 1\n#define AVR32_SPI_ENDTX 5\n#define AVR32_SPI_ENDTX_MASK 0x00000020\n#define AVR32_SPI_ENDTX_OFFSET 5\n#define AVR32_SPI_ENDTX_SIZE 1\n#define AVR32_SPI_IDR 0x00000018\n#define AVR32_SPI_IDR_ENDRX 4\n#define AVR32_SPI_IDR_ENDRX_MASK 0x00000010\n#define AVR32_SPI_IDR_ENDRX_OFFSET 4\n#define AVR32_SPI_IDR_ENDRX_SIZE 1\n#define AVR32_SPI_IDR_ENDTX 5\n#define AVR32_SPI_IDR_ENDTX_MASK 0x00000020\n#define AVR32_SPI_IDR_ENDTX_OFFSET 5\n#define AVR32_SPI_IDR_ENDTX_SIZE 1\n#define AVR32_SPI_IDR_MODF 2\n#define AVR32_SPI_IDR_MODF_MASK 0x00000004\n#define AVR32_SPI_IDR_MODF_OFFSET 2\n#define AVR32_SPI_IDR_MODF_SIZE 1\n#define AVR32_SPI_IDR_NSSR 8\n#define AVR32_SPI_IDR_NSSR_MASK 0x00000100\n#define AVR32_SPI_IDR_NSSR_OFFSET 8\n#define AVR32_SPI_IDR_NSSR_SIZE 1\n#define AVR32_SPI_IDR_OVRES 3\n#define AVR32_SPI_IDR_OVRES_MASK 0x00000008\n#define AVR32_SPI_IDR_OVRES_OFFSET 3\n#define AVR32_SPI_IDR_OVRES_SIZE 1\n#define AVR32_SPI_IDR_RDRF 0\n#define AVR32_SPI_IDR_RDRF_MASK 0x00000001\n#define AVR32_SPI_IDR_RDRF_OFFSET 0\n#define AVR32_SPI_IDR_RDRF_SIZE 1\n#define AVR32_SPI_IDR_RXBUFF 6\n#define AVR32_SPI_IDR_RXBUFF_MASK 0x00000040\n#define AVR32_SPI_IDR_RXBUFF_OFFSET 6\n#define AVR32_SPI_IDR_RXBUFF_SIZE 1\n#define AVR32_SPI_IDR_TDRE 1\n#define AVR32_SPI_IDR_TDRE_MASK 0x00000002\n#define AVR32_SPI_IDR_TDRE_OFFSET 1\n#define AVR32_SPI_IDR_TDRE_SIZE 1\n#define AVR32_SPI_IDR_TXBUFE 7\n#define AVR32_SPI_IDR_TXBUFE_MASK 0x00000080\n#define AVR32_SPI_IDR_TXBUFE_OFFSET 7\n#define AVR32_SPI_IDR_TXBUFE_SIZE 1\n#define AVR32_SPI_IDR_TXEMPTY 9\n#define AVR32_SPI_IDR_TXEMPTY_MASK 0x00000200\n#define AVR32_SPI_IDR_TXEMPTY_OFFSET 9\n#define AVR32_SPI_IDR_TXEMPTY_SIZE 1\n#define AVR32_SPI_IER 0x00000014\n#define AVR32_SPI_IER_ENDRX 4\n#define AVR32_SPI_IER_ENDRX_MASK 0x00000010\n#define AVR32_SPI_IER_ENDRX_OFFSET 4\n#define AVR32_SPI_IER_ENDRX_SIZE 1\n#define AVR32_SPI_IER_ENDTX 5\n#define AVR32_SPI_IER_ENDTX_MASK 0x00000020\n#define AVR32_SPI_IER_ENDTX_OFFSET 5\n#define AVR32_SPI_IER_ENDTX_SIZE 1\n#define AVR32_SPI_IER_MODF 2\n#define AVR32_SPI_IER_MODF_MASK 0x00000004\n#define AVR32_SPI_IER_MODF_OFFSET 2\n#define AVR32_SPI_IER_MODF_SIZE 1\n#define AVR32_SPI_IER_NSSR 8\n#define AVR32_SPI_IER_NSSR_MASK 0x00000100\n#define AVR32_SPI_IER_NSSR_OFFSET 8\n#define AVR32_SPI_IER_NSSR_SIZE 1\n#define AVR32_SPI_IER_OVRES 3\n#define AVR32_SPI_IER_OVRES_MASK 0x00000008\n#define AVR32_SPI_IER_OVRES_OFFSET 3\n#define AVR32_SPI_IER_OVRES_SIZE 1\n#define AVR32_SPI_IER_RDRF 0\n#define AVR32_SPI_IER_RDRF_MASK 0x00000001\n#define AVR32_SPI_IER_RDRF_OFFSET 0\n#define AVR32_SPI_IER_RDRF_SIZE 1\n#define AVR32_SPI_IER_RXBUFF 6\n#define AVR32_SPI_IER_RXBUFF_MASK 0x00000040\n#define AVR32_SPI_IER_RXBUFF_OFFSET 6\n#define AVR32_SPI_IER_RXBUFF_SIZE 1\n#define AVR32_SPI_IER_TDRE 1\n#define AVR32_SPI_IER_TDRE_MASK 0x00000002\n#define AVR32_SPI_IER_TDRE_OFFSET 1\n#define AVR32_SPI_IER_TDRE_SIZE 1\n#define AVR32_SPI_IER_TXBUFE 7\n#define AVR32_SPI_IER_TXBUFE_MASK 0x00000080\n#define AVR32_SPI_IER_TXBUFE_OFFSET 7\n#define AVR32_SPI_IER_TXBUFE_SIZE 1\n#define AVR32_SPI_IER_TXEMPTY 9\n#define AVR32_SPI_IER_TXEMPTY_MASK 0x00000200\n#define AVR32_SPI_IER_TXEMPTY_OFFSET 9\n#define AVR32_SPI_IER_TXEMPTY_SIZE 1\n#define AVR32_SPI_IMR 0x0000001c\n#define AVR32_SPI_IMR_ENDRX 4\n#define AVR32_SPI_IMR_ENDRX_MASK 0x00000010\n#define AVR32_SPI_IMR_ENDRX_OFFSET 4\n#define AVR32_SPI_IMR_ENDRX_SIZE 1\n#define AVR32_SPI_IMR_ENDTX 5\n#define AVR32_SPI_IMR_ENDTX_MASK 0x00000020\n#define AVR32_SPI_IMR_ENDTX_OFFSET 5\n#define AVR32_SPI_IMR_ENDTX_SIZE 1\n#define AVR32_SPI_IMR_MODF 2\n#define AVR32_SPI_IMR_MODF_MASK 0x00000004\n#define AVR32_SPI_IMR_MODF_OFFSET 2\n#define AVR32_SPI_IMR_MODF_SIZE 1\n#define AVR32_SPI_IMR_NSSR 8\n#define AVR32_SPI_IMR_NSSR_MASK 0x00000100\n#define AVR32_SPI_IMR_NSSR_OFFSET 8\n#define AVR32_SPI_IMR_NSSR_SIZE 1\n#define AVR32_SPI_IMR_OVRES 3\n#define AVR32_SPI_IMR_OVRES_MASK 0x00000008\n#define AVR32_SPI_IMR_OVRES_OFFSET 3\n#define AVR32_SPI_IMR_OVRES_SIZE 1\n#define AVR32_SPI_IMR_RDRF 0\n#define AVR32_SPI_IMR_RDRF_MASK 0x00000001\n#define AVR32_SPI_IMR_RDRF_OFFSET 0\n#define AVR32_SPI_IMR_RDRF_SIZE 1\n#define AVR32_SPI_IMR_RXBUFF 6\n#define AVR32_SPI_IMR_RXBUFF_MASK 0x00000040\n#define AVR32_SPI_IMR_RXBUFF_OFFSET 6\n#define AVR32_SPI_IMR_RXBUFF_SIZE 1\n#define AVR32_SPI_IMR_TDRE 1\n#define AVR32_SPI_IMR_TDRE_MASK 0x00000002\n#define AVR32_SPI_IMR_TDRE_OFFSET 1\n#define AVR32_SPI_IMR_TDRE_SIZE 1\n#define AVR32_SPI_IMR_TXBUFE 7\n#define AVR32_SPI_IMR_TXBUFE_MASK 0x00000080\n#define AVR32_SPI_IMR_TXBUFE_OFFSET 7\n#define AVR32_SPI_IMR_TXBUFE_SIZE 1\n#define AVR32_SPI_IMR_TXEMPTY 9\n#define AVR32_SPI_IMR_TXEMPTY_MASK 0x00000200\n#define AVR32_SPI_IMR_TXEMPTY_OFFSET 9\n#define AVR32_SPI_IMR_TXEMPTY_SIZE 1\n#define AVR32_SPI_LASTXFER 24\n#define AVR32_SPI_LASTXFER_MASK 0x01000000\n#define AVR32_SPI_LASTXFER_OFFSET 24\n#define AVR32_SPI_LASTXFER_SIZE 1\n#define AVR32_SPI_LLB 7\n#define AVR32_SPI_LLB_MASK 0x00000080\n#define AVR32_SPI_LLB_OFFSET 7\n#define AVR32_SPI_LLB_SIZE 1\n#define AVR32_SPI_MODF 2\n#define AVR32_SPI_MODFDIS 4\n#define AVR32_SPI_MODFDIS_MASK 0x00000010\n#define AVR32_SPI_MODFDIS_OFFSET 4\n#define AVR32_SPI_MODFDIS_SIZE 1\n#define AVR32_SPI_MODF_MASK 0x00000004\n#define AVR32_SPI_MODF_OFFSET 2\n#define AVR32_SPI_MODF_SIZE 1\n#define AVR32_SPI_MR 0x00000004\n#define AVR32_SPI_MR_DLYBCS 24\n#define AVR32_SPI_MR_DLYBCS_MASK 0xff000000\n#define AVR32_SPI_MR_DLYBCS_OFFSET 24\n#define AVR32_SPI_MR_DLYBCS_SIZE 8\n#define AVR32_SPI_MR_LLB 7\n#define AVR32_SPI_MR_LLB_MASK 0x00000080\n#define AVR32_SPI_MR_LLB_OFFSET 7\n#define AVR32_SPI_MR_LLB_SIZE 1\n#define AVR32_SPI_MR_MODFDIS 4\n#define AVR32_SPI_MR_MODFDIS_MASK 0x00000010\n#define AVR32_SPI_MR_MODFDIS_OFFSET 4\n#define AVR32_SPI_MR_MODFDIS_SIZE 1\n#define AVR32_SPI_MR_MSTR 0\n#define AVR32_SPI_MR_MSTR_MASK 0x00000001\n#define AVR32_SPI_MR_MSTR_OFFSET 0\n#define AVR32_SPI_MR_MSTR_SIZE 1\n#define AVR32_SPI_MR_PCS 16\n#define AVR32_SPI_MR_PCSDEC 2\n#define AVR32_SPI_MR_PCSDEC_MASK 0x00000004\n#define AVR32_SPI_MR_PCSDEC_OFFSET 2\n#define AVR32_SPI_MR_PCSDEC_SIZE 1\n#define AVR32_SPI_MR_PCS_MASK 0x000f0000\n#define AVR32_SPI_MR_PCS_OFFSET 16\n#define AVR32_SPI_MR_PCS_SIZE 4\n#define AVR32_SPI_MR_PS 1\n#define AVR32_SPI_MR_PS_MASK 0x00000002\n#define AVR32_SPI_MR_PS_OFFSET 1\n#define AVR32_SPI_MR_PS_SIZE 1\n#define AVR32_SPI_MSTR 0\n#define AVR32_SPI_MSTR_MASK 0x00000001\n#define AVR32_SPI_MSTR_OFFSET 0\n#define AVR32_SPI_MSTR_SIZE 1\n#define AVR32_SPI_NCPHA 1\n#define AVR32_SPI_NCPHA_MASK 0x00000002\n#define AVR32_SPI_NCPHA_OFFSET 1\n#define AVR32_SPI_NCPHA_SIZE 1\n#define AVR32_SPI_NSSR 8\n#define AVR32_SPI_NSSR_MASK 0x00000100\n#define AVR32_SPI_NSSR_OFFSET 8\n#define AVR32_SPI_NSSR_SIZE 1\n#define AVR32_SPI_OVRES 3\n#define AVR32_SPI_OVRES_MASK 0x00000008\n#define AVR32_SPI_OVRES_OFFSET 3\n#define AVR32_SPI_OVRES_SIZE 1\n#define AVR32_SPI_PCS 16\n#define AVR32_SPI_PCSDEC 2\n#define AVR32_SPI_PCSDEC_MASK 0x00000004\n#define AVR32_SPI_PCSDEC_OFFSET 2\n#define AVR32_SPI_PCSDEC_SIZE 1\n#define AVR32_SPI_PCS_MASK 0x000f0000\n#define AVR32_SPI_PCS_OFFSET 16\n#define AVR32_SPI_PCS_SIZE 4\n#define AVR32_SPI_PS 1\n#define AVR32_SPI_PS_MASK 0x00000002\n#define AVR32_SPI_PS_OFFSET 1\n#define AVR32_SPI_PS_SIZE 1\n#define AVR32_SPI_RD 0\n#define AVR32_SPI_RDR 0x00000008\n#define AVR32_SPI_RDRF 0\n#define AVR32_SPI_RDRF_MASK 0x00000001\n#define AVR32_SPI_RDRF_OFFSET 0\n#define AVR32_SPI_RDRF_SIZE 1\n#define AVR32_SPI_RDR_PCS 16\n#define AVR32_SPI_RDR_PCS_MASK 0x000f0000\n#define AVR32_SPI_RDR_PCS_OFFSET 16\n#define AVR32_SPI_RDR_PCS_SIZE 4\n#define AVR32_SPI_RDR_RD 0\n#define AVR32_SPI_RDR_RD_MASK 0x0000ffff\n#define AVR32_SPI_RDR_RD_OFFSET 0\n#define AVR32_SPI_RDR_RD_SIZE 16\n#define AVR32_SPI_RD_MASK 0x0000ffff\n#define AVR32_SPI_RD_OFFSET 0\n#define AVR32_SPI_RD_SIZE 16\n#define AVR32_SPI_RXBUFF 6\n#define AVR32_SPI_RXBUFF_MASK 0x00000040\n#define AVR32_SPI_RXBUFF_OFFSET 6\n#define AVR32_SPI_RXBUFF_SIZE 1\n#define AVR32_SPI_SCBR 8\n#define AVR32_SPI_SCBR_MASK 0x0000ff00\n#define AVR32_SPI_SCBR_OFFSET 8\n#define AVR32_SPI_SCBR_SIZE 8\n#define AVR32_SPI_SPIDIS 1\n#define AVR32_SPI_SPIDIS_MASK 0x00000002\n#define AVR32_SPI_SPIDIS_OFFSET 1\n#define AVR32_SPI_SPIDIS_SIZE 1\n#define AVR32_SPI_SPIEN 0\n#define AVR32_SPI_SPIENS 16\n#define AVR32_SPI_SPIENS_MASK 0x00010000\n#define AVR32_SPI_SPIENS_OFFSET 16\n#define AVR32_SPI_SPIENS_SIZE 1\n#define AVR32_SPI_SPIEN_MASK 0x00000001\n#define AVR32_SPI_SPIEN_OFFSET 0\n#define AVR32_SPI_SPIEN_SIZE 1\n#define AVR32_SPI_SR 0x00000010\n#define AVR32_SPI_SR_ENDRX 4\n#define AVR32_SPI_SR_ENDRX_MASK 0x00000010\n#define AVR32_SPI_SR_ENDRX_OFFSET 4\n#define AVR32_SPI_SR_ENDRX_SIZE 1\n#define AVR32_SPI_SR_ENDTX 5\n#define AVR32_SPI_SR_ENDTX_MASK 0x00000020\n#define AVR32_SPI_SR_ENDTX_OFFSET 5\n#define AVR32_SPI_SR_ENDTX_SIZE 1\n#define AVR32_SPI_SR_MODF 2\n#define AVR32_SPI_SR_MODF_MASK 0x00000004\n#define AVR32_SPI_SR_MODF_OFFSET 2\n#define AVR32_SPI_SR_MODF_SIZE 1\n#define AVR32_SPI_SR_NSSR 8\n#define AVR32_SPI_SR_NSSR_MASK 0x00000100\n#define AVR32_SPI_SR_NSSR_OFFSET 8\n#define AVR32_SPI_SR_NSSR_SIZE 1\n#define AVR32_SPI_SR_OVRES 3\n#define AVR32_SPI_SR_OVRES_MASK 0x00000008\n#define AVR32_SPI_SR_OVRES_OFFSET 3\n#define AVR32_SPI_SR_OVRES_SIZE 1\n#define AVR32_SPI_SR_RDRF 0\n#define AVR32_SPI_SR_RDRF_MASK 0x00000001\n#define AVR32_SPI_SR_RDRF_OFFSET 0\n#define AVR32_SPI_SR_RDRF_SIZE 1\n#define AVR32_SPI_SR_RXBUFF 6\n#define AVR32_SPI_SR_RXBUFF_MASK 0x00000040\n#define AVR32_SPI_SR_RXBUFF_OFFSET 6\n#define AVR32_SPI_SR_RXBUFF_SIZE 1\n#define AVR32_SPI_SR_SPIENS 16\n#define AVR32_SPI_SR_SPIENS_MASK 0x00010000\n#define AVR32_SPI_SR_SPIENS_OFFSET 16\n#define AVR32_SPI_SR_SPIENS_SIZE 1\n#define AVR32_SPI_SR_TDRE 1\n#define AVR32_SPI_SR_TDRE_MASK 0x00000002\n#define AVR32_SPI_SR_TDRE_OFFSET 1\n#define AVR32_SPI_SR_TDRE_SIZE 1\n#define AVR32_SPI_SR_TXBUFE 7\n#define AVR32_SPI_SR_TXBUFE_MASK 0x00000080\n#define AVR32_SPI_SR_TXBUFE_OFFSET 7\n#define AVR32_SPI_SR_TXBUFE_SIZE 1\n#define AVR32_SPI_SR_TXEMPTY 9\n#define AVR32_SPI_SR_TXEMPTY_MASK 0x00000200\n#define AVR32_SPI_SR_TXEMPTY_OFFSET 9\n#define AVR32_SPI_SR_TXEMPTY_SIZE 1\n#define AVR32_SPI_SWRST 7\n#define AVR32_SPI_SWRST_MASK 0x00000080\n#define AVR32_SPI_SWRST_OFFSET 7\n#define AVR32_SPI_SWRST_SIZE 1\n#define AVR32_SPI_TD 0\n#define AVR32_SPI_TDR 0x0000000c\n#define AVR32_SPI_TDRE 1\n#define AVR32_SPI_TDRE_MASK 0x00000002\n#define AVR32_SPI_TDRE_OFFSET 1\n#define AVR32_SPI_TDRE_SIZE 1\n#define AVR32_SPI_TDR_LASTXFER 24\n#define AVR32_SPI_TDR_LASTXFER_MASK 0x01000000\n#define AVR32_SPI_TDR_LASTXFER_OFFSET 24\n#define AVR32_SPI_TDR_LASTXFER_SIZE 1\n#define AVR32_SPI_TDR_PCS 16\n#define AVR32_SPI_TDR_PCS_MASK 0x000f0000\n#define AVR32_SPI_TDR_PCS_OFFSET 16\n#define AVR32_SPI_TDR_PCS_SIZE 4\n#define AVR32_SPI_TDR_TD 0\n#define AVR32_SPI_TDR_TD_MASK 0x0000ffff\n#define AVR32_SPI_TDR_TD_OFFSET 0\n#define AVR32_SPI_TDR_TD_SIZE 16\n#define AVR32_SPI_TD_MASK 0x0000ffff\n#define AVR32_SPI_TD_OFFSET 0\n#define AVR32_SPI_TD_SIZE 16\n#define AVR32_SPI_TXBUFE 7\n#define AVR32_SPI_TXBUFE_MASK 0x00000080\n#define AVR32_SPI_TXBUFE_OFFSET 7\n#define AVR32_SPI_TXBUFE_SIZE 1\n#define AVR32_SPI_TXEMPTY 9\n#define AVR32_SPI_TXEMPTY_MASK 0x00000200\n#define AVR32_SPI_TXEMPTY_OFFSET 9\n#define AVR32_SPI_TXEMPTY_SIZE 1\n#define AVR32_SPI_VARIANT 16\n#define AVR32_SPI_VARIANT_MASK 0x00070000\n#define AVR32_SPI_VARIANT_OFFSET 16\n#define AVR32_SPI_VARIANT_SIZE 3\n#define AVR32_SPI_VERSION 0x000000fc\n#define AVR32_SPI_VERSION_MASK 0x00000fff\n#define AVR32_SPI_VERSION_OFFSET 0\n#define AVR32_SPI_VERSION_SIZE 12\n#define AVR32_SPI_VERSION_VARIANT 16\n#define AVR32_SPI_VERSION_VARIANT_MASK 0x00070000\n#define AVR32_SPI_VERSION_VARIANT_OFFSET 16\n#define AVR32_SPI_VERSION_VARIANT_SIZE 3\n#define AVR32_SPI_VERSION_VERSION 0\n#define AVR32_SPI_VERSION_VERSION_MASK 0x00000fff\n#define AVR32_SPI_VERSION_VERSION_OFFSET 0\n#define AVR32_SPI_VERSION_VERSION_SIZE 12\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_spi_cr_t {\n unsigned int : 7;\n unsigned int lastxfer : 1;\n unsigned int :16;\n unsigned int swrst : 1;\n unsigned int : 5;\n unsigned int spidis : 1;\n unsigned int spien : 1;\n} avr32_spi_cr_t;\n\n\n\ntypedef struct avr32_spi_mr_t {\n unsigned int dlybcs : 8;\n unsigned int : 4;\n unsigned int pcs : 4;\n unsigned int : 8;\n unsigned int llb : 1;\n unsigned int : 2;\n unsigned int modfdis : 1;\n unsigned int : 1;\n unsigned int pcsdec : 1;\n unsigned int ps : 1;\n unsigned int mstr : 1;\n} avr32_spi_mr_t;\n\n\n\ntypedef struct avr32_spi_rdr_t {\n unsigned int :12;\n unsigned int pcs : 4;\n unsigned int rd :16;\n} avr32_spi_rdr_t;\n\n\n\ntypedef struct avr32_spi_tdr_t {\n unsigned int : 7;\n unsigned int lastxfer : 1;\n unsigned int : 4;\n unsigned int pcs : 4;\n unsigned int td :16;\n} avr32_spi_tdr_t;\n\n\n\ntypedef struct avr32_spi_sr_t {\n unsigned int :15;\n unsigned int spiens : 1;\n unsigned int : 6;\n unsigned int txempty : 1;\n unsigned int nssr : 1;\n unsigned int txbufe : 1;\n unsigned int rxbuff : 1;\n unsigned int endtx : 1;\n unsigned int endrx : 1;\n unsigned int ovres : 1;\n unsigned int modf : 1;\n unsigned int tdre : 1;\n unsigned int rdrf : 1;\n} avr32_spi_sr_t;\n\n\n\ntypedef struct avr32_spi_ier_t {\n unsigned int :22;\n unsigned int txempty : 1;\n unsigned int nssr : 1;\n unsigned int txbufe : 1;\n unsigned int rxbuff : 1;\n unsigned int endtx : 1;\n unsigned int endrx : 1;\n unsigned int ovres : 1;\n unsigned int modf : 1;\n unsigned int tdre : 1;\n unsigned int rdrf : 1;\n} avr32_spi_ier_t;\n\n\n\ntypedef struct avr32_spi_idr_t {\n unsigned int :22;\n unsigned int txempty : 1;\n unsigned int nssr : 1;\n unsigned int txbufe : 1;\n unsigned int rxbuff : 1;\n unsigned int endtx : 1;\n unsigned int endrx : 1;\n unsigned int ovres : 1;\n unsigned int modf : 1;\n unsigned int tdre : 1;\n unsigned int rdrf : 1;\n} avr32_spi_idr_t;\n\n\n\ntypedef struct avr32_spi_imr_t {\n unsigned int :22;\n unsigned int txempty : 1;\n unsigned int nssr : 1;\n unsigned int txbufe : 1;\n unsigned int rxbuff : 1;\n unsigned int endtx : 1;\n unsigned int endrx : 1;\n unsigned int ovres : 1;\n unsigned int modf : 1;\n unsigned int tdre : 1;\n unsigned int rdrf : 1;\n} avr32_spi_imr_t;\n\n\n\ntypedef struct avr32_spi_csr0_t {\n unsigned int dlybct : 8;\n unsigned int dlybs : 8;\n unsigned int scbr : 8;\n unsigned int bits : 4;\n unsigned int csaat : 1;\n unsigned int csnaat : 1;\n unsigned int ncpha : 1;\n unsigned int cpol : 1;\n} avr32_spi_csr0_t;\n\n\n\ntypedef struct avr32_spi_csr1_t {\n unsigned int dlybct : 8;\n unsigned int dlybs : 8;\n unsigned int scbr : 8;\n unsigned int bits : 4;\n unsigned int csaat : 1;\n unsigned int csnaat : 1;\n unsigned int ncpha : 1;\n unsigned int cpol : 1;\n} avr32_spi_csr1_t;\n\n\n\ntypedef struct avr32_spi_csr2_t {\n unsigned int dlybct : 8;\n unsigned int dlybs : 8;\n unsigned int scbr : 8;\n unsigned int bits : 4;\n unsigned int csaat : 1;\n unsigned int csnaat : 1;\n unsigned int ncpha : 1;\n unsigned int cpol : 1;\n} avr32_spi_csr2_t;\n\n\n\ntypedef struct avr32_spi_csr3_t {\n unsigned int dlybct : 8;\n unsigned int dlybs : 8;\n unsigned int scbr : 8;\n unsigned int bits : 4;\n unsigned int csaat : 1;\n unsigned int csnaat : 1;\n unsigned int ncpha : 1;\n unsigned int cpol : 1;\n} avr32_spi_csr3_t;\n\n\n\ntypedef struct avr32_spi_version_t {\n unsigned int :13;\n unsigned int variant : 3;\n unsigned int : 4;\n unsigned int version :12;\n} avr32_spi_version_t;\n\n\n\ntypedef struct avr32_spi_t {\n union {\n unsigned long cr ;//0x0000\n avr32_spi_cr_t CR ;\n };\n union {\n unsigned long mr ;//0x0004\n avr32_spi_mr_t MR ;\n };\n union {\n const unsigned long rdr ;//0x0008\n const avr32_spi_rdr_t RDR ;\n };\n union {\n unsigned long tdr ;//0x000c\n avr32_spi_tdr_t TDR ;\n };\n union {\n const unsigned long sr ;//0x0010\n const avr32_spi_sr_t SR ;\n };\n union {\n unsigned long ier ;//0x0014\n avr32_spi_ier_t IER ;\n };\n union {\n unsigned long idr ;//0x0018\n avr32_spi_idr_t IDR ;\n };\n union {\n const unsigned long imr ;//0x001c\n const avr32_spi_imr_t IMR ;\n };\n unsigned int :32 ;//0x0020\n unsigned int :32 ;//0x0024\n unsigned int :32 ;//0x0028\n unsigned int :32 ;//0x002c\n union {\n unsigned long csr0 ;//0x0030\n avr32_spi_csr0_t CSR0 ;\n };\n union {\n unsigned long csr1 ;//0x0034\n avr32_spi_csr1_t CSR1 ;\n };\n union {\n unsigned long csr2 ;//0x0038\n avr32_spi_csr2_t CSR2 ;\n };\n union {\n unsigned long csr3 ;//0x003c\n avr32_spi_csr3_t CSR3 ;\n };\n unsigned int :32 ;//0x0040\n unsigned int :32 ;//0x0044\n unsigned int :32 ;//0x0048\n unsigned int :32 ;//0x004c\n unsigned int :32 ;//0x0050\n unsigned int :32 ;//0x0054\n unsigned int :32 ;//0x0058\n unsigned int :32 ;//0x005c\n unsigned int :32 ;//0x0060\n unsigned int :32 ;//0x0064\n unsigned int :32 ;//0x0068\n unsigned int :32 ;//0x006c\n unsigned int :32 ;//0x0070\n unsigned int :32 ;//0x0074\n unsigned int :32 ;//0x0078\n unsigned int :32 ;//0x007c\n unsigned int :32 ;//0x0080\n unsigned int :32 ;//0x0084\n unsigned int :32 ;//0x0088\n unsigned int :32 ;//0x008c\n unsigned int :32 ;//0x0090\n unsigned int :32 ;//0x0094\n unsigned int :32 ;//0x0098\n unsigned int :32 ;//0x009c\n unsigned int :32 ;//0x00a0\n unsigned int :32 ;//0x00a4\n unsigned int :32 ;//0x00a8\n unsigned int :32 ;//0x00ac\n unsigned int :32 ;//0x00b0\n unsigned int :32 ;//0x00b4\n unsigned int :32 ;//0x00b8\n unsigned int :32 ;//0x00bc\n unsigned int :32 ;//0x00c0\n unsigned int :32 ;//0x00c4\n unsigned int :32 ;//0x00c8\n unsigned int :32 ;//0x00cc\n unsigned int :32 ;//0x00d0\n unsigned int :32 ;//0x00d4\n unsigned int :32 ;//0x00d8\n unsigned int :32 ;//0x00dc\n unsigned int :32 ;//0x00e0\n unsigned int :32 ;//0x00e4\n unsigned int :32 ;//0x00e8\n unsigned int :32 ;//0x00ec\n unsigned int :32 ;//0x00f0\n unsigned int :32 ;//0x00f4\n unsigned int :32 ;//0x00f8\n union {\n const unsigned long version ;//0x00fc\n const avr32_spi_version_t VERSION ;\n };\n} avr32_spi_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n\n#if !defined (DEPRECATED_DISABLE)\n\n#define AVR32_SPI_MFN 16\n#define AVR32_SPI_MFN_MASK 0x00070000\n#define AVR32_SPI_MFN_OFFSET 16\n#define AVR32_SPI_MFN_SIZE 3\n\n#define AVR32_SPI_VERSION_MFN 16\n#define AVR32_SPI_VERSION_MFN_MASK 0x00070000\n#define AVR32_SPI_VERSION_MFN_OFFSET 16\n#define AVR32_SPI_VERSION_MFN_SIZE 3\n\n#endif\n\n\n/*#ifdef AVR32_SPI_199_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/ssc_310.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3A0512\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_SSC_310_H_INCLUDED\n#define AVR32_SSC_310_H_INCLUDED\n\n#define AVR32_SSC_H_VERSION 310\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_SSC_\n - Bitfield mask: AVR32_SSC__\n - Bitfield offset: AVR32_SSC___OFFSET\n - Bitfield size: AVR32_SSC___SIZE\n - Bitfield values: AVR32_SSC___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_SSC_\n - Bitfield offset: AVR32_SSC__OFFSET\n - Bitfield size: AVR32_SSC__SIZE\n - Bitfield values: AVR32_SSC__\n - Bitfield values: AVR32_SSC_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_SSC_CKG 6\n#define AVR32_SSC_CKG_HIGH 0x00000002\n#define AVR32_SSC_CKG_LOW 0x00000001\n#define AVR32_SSC_CKG_MASK 0x000000c0\n#define AVR32_SSC_CKG_NONE 0x00000000\n#define AVR32_SSC_CKG_OFFSET 6\n#define AVR32_SSC_CKG_SIZE 2\n#define AVR32_SSC_CKI 5\n#define AVR32_SSC_CKI_MASK 0x00000020\n#define AVR32_SSC_CKI_OFFSET 5\n#define AVR32_SSC_CKI_SIZE 1\n#define AVR32_SSC_CKO 2\n#define AVR32_SSC_CKO_CONTINOUS_CLOCK_OUTPUT 0x00000001\n#define AVR32_SSC_CKO_INPUT_ONLY 0x00000000\n#define AVR32_SSC_CKO_MASK 0x0000001c\n#define AVR32_SSC_CKO_OFFSET 2\n#define AVR32_SSC_CKO_SIZE 3\n#define AVR32_SSC_CKS 0\n#define AVR32_SSC_CKS_DIV_CLOCK 0x00000000\n#define AVR32_SSC_CKS_MASK 0x00000003\n#define AVR32_SSC_CKS_OFFSET 0\n#define AVR32_SSC_CKS_RK_CLOCK 0x00000001\n#define AVR32_SSC_CKS_RK_PIN 0x00000002\n#define AVR32_SSC_CKS_SIZE 2\n#define AVR32_SSC_CKS_TK_CLOCK 0x00000001\n#define AVR32_SSC_CKS_TK_PIN 0x00000002\n#define AVR32_SSC_CMR 0x00000004\n#define AVR32_SSC_CMR_DIV 0\n#define AVR32_SSC_CMR_DIV_MASK 0x00000fff\n#define AVR32_SSC_CMR_DIV_NOT_ACTIVE 0x00000000\n#define AVR32_SSC_CMR_DIV_OFFSET 0\n#define AVR32_SSC_CMR_DIV_SIZE 12\n#define AVR32_SSC_COMPARE_0 0x00000008\n#define AVR32_SSC_CONTINOUS 0x00000000\n#define AVR32_SSC_CONTINOUS_CLOCK_OUTPUT 0x00000001\n#define AVR32_SSC_CR 0x00000000\n#define AVR32_SSC_CR_RXDIS 1\n#define AVR32_SSC_CR_RXDIS_MASK 0x00000002\n#define AVR32_SSC_CR_RXDIS_OFFSET 1\n#define AVR32_SSC_CR_RXDIS_SIZE 1\n#define AVR32_SSC_CR_RXEN 0\n#define AVR32_SSC_CR_RXEN_MASK 0x00000001\n#define AVR32_SSC_CR_RXEN_OFFSET 0\n#define AVR32_SSC_CR_RXEN_SIZE 1\n#define AVR32_SSC_CR_SWRST 15\n#define AVR32_SSC_CR_SWRST_MASK 0x00008000\n#define AVR32_SSC_CR_SWRST_OFFSET 15\n#define AVR32_SSC_CR_SWRST_SIZE 1\n#define AVR32_SSC_CR_TXDIS 9\n#define AVR32_SSC_CR_TXDIS_MASK 0x00000200\n#define AVR32_SSC_CR_TXDIS_OFFSET 9\n#define AVR32_SSC_CR_TXDIS_SIZE 1\n#define AVR32_SSC_CR_TXEN 8\n#define AVR32_SSC_CR_TXEN_MASK 0x00000100\n#define AVR32_SSC_CR_TXEN_OFFSET 8\n#define AVR32_SSC_CR_TXEN_SIZE 1\n#define AVR32_SSC_DATDEF 5\n#define AVR32_SSC_DATDEF_MASK 0x00000020\n#define AVR32_SSC_DATDEF_OFFSET 5\n#define AVR32_SSC_DATDEF_SIZE 1\n#define AVR32_SSC_DATLEN 0\n#define AVR32_SSC_DATLEN_MASK 0x0000001f\n#define AVR32_SSC_DATLEN_OFFSET 0\n#define AVR32_SSC_DATLEN_SIZE 5\n#define AVR32_SSC_DATNB 8\n#define AVR32_SSC_DATNB_MASK 0x00000f00\n#define AVR32_SSC_DATNB_OFFSET 8\n#define AVR32_SSC_DATNB_SIZE 4\n#define AVR32_SSC_DETECT_ANY_EDGE_RF 0x00000007\n#define AVR32_SSC_DETECT_ANY_EDGE_TF 0x00000007\n#define AVR32_SSC_DETECT_FALLING_RF 0x00000004\n#define AVR32_SSC_DETECT_FALLING_TF 0x00000004\n#define AVR32_SSC_DETECT_HIGH_RF 0x00000003\n#define AVR32_SSC_DETECT_HIGH_TF 0x00000003\n#define AVR32_SSC_DETECT_LEVEL_CHANGE_RF 0x00000006\n#define AVR32_SSC_DETECT_LEVEL_CHANGE_TF 0x00000006\n#define AVR32_SSC_DETECT_LOW_RF 0x00000002\n#define AVR32_SSC_DETECT_LOW_TF 0x00000002\n#define AVR32_SSC_DETECT_RISING_RF 0x00000005\n#define AVR32_SSC_DETECT_RISING_TF 0x00000005\n#define AVR32_SSC_DIV 0\n#define AVR32_SSC_DIV_CLOCK 0x00000000\n#define AVR32_SSC_DIV_MASK 0x00000fff\n#define AVR32_SSC_DIV_NOT_ACTIVE 0x00000000\n#define AVR32_SSC_DIV_OFFSET 0\n#define AVR32_SSC_DIV_SIZE 12\n#define AVR32_SSC_ENDRX 6\n#define AVR32_SSC_ENDRX_MASK 0x00000040\n#define AVR32_SSC_ENDRX_OFFSET 6\n#define AVR32_SSC_ENDRX_SIZE 1\n#define AVR32_SSC_ENDTX 2\n#define AVR32_SSC_ENDTX_MASK 0x00000004\n#define AVR32_SSC_ENDTX_OFFSET 2\n#define AVR32_SSC_ENDTX_SIZE 1\n#define AVR32_SSC_FSDEN 23\n#define AVR32_SSC_FSDEN_MASK 0x00800000\n#define AVR32_SSC_FSDEN_OFFSET 23\n#define AVR32_SSC_FSDEN_SIZE 1\n#define AVR32_SSC_FSEDGE 24\n#define AVR32_SSC_FSEDGE_MASK 0x01000000\n#define AVR32_SSC_FSEDGE_OFFSET 24\n#define AVR32_SSC_FSEDGE_SIZE 1\n#define AVR32_SSC_FSLEN 16\n#define AVR32_SSC_FSLENHI 28\n#define AVR32_SSC_FSLENHI_MASK 0xf0000000\n#define AVR32_SSC_FSLENHI_OFFSET 28\n#define AVR32_SSC_FSLENHI_SIZE 4\n#define AVR32_SSC_FSLEN_MASK 0x000f0000\n#define AVR32_SSC_FSLEN_OFFSET 16\n#define AVR32_SSC_FSLEN_SIZE 4\n#define AVR32_SSC_FSOS 20\n#define AVR32_SSC_FSOS_HIGH_DURING_DATA 0x00000004\n#define AVR32_SSC_FSOS_INPUT_ONLY 0x00000000\n#define AVR32_SSC_FSOS_LOW_DURING_DATA 0x00000003\n#define AVR32_SSC_FSOS_MASK 0x00700000\n#define AVR32_SSC_FSOS_NEG_PULSE 0x00000001\n#define AVR32_SSC_FSOS_OFFSET 20\n#define AVR32_SSC_FSOS_POS_PULSE 0x00000002\n#define AVR32_SSC_FSOS_SIZE 3\n#define AVR32_SSC_FSOS_TOGGLE_DATA_START 0x00000005\n#define AVR32_SSC_HIGH 0x00000002\n#define AVR32_SSC_HIGH_DURING_DATA 0x00000004\n#define AVR32_SSC_IDR 0x00000048\n#define AVR32_SSC_IDR_CP0 8\n#define AVR32_SSC_IDR_CP0_MASK 0x00000100\n#define AVR32_SSC_IDR_CP0_OFFSET 8\n#define AVR32_SSC_IDR_CP0_SIZE 1\n#define AVR32_SSC_IDR_CP1 9\n#define AVR32_SSC_IDR_CP1_MASK 0x00000200\n#define AVR32_SSC_IDR_CP1_OFFSET 9\n#define AVR32_SSC_IDR_CP1_SIZE 1\n#define AVR32_SSC_IDR_ENDRX 6\n#define AVR32_SSC_IDR_ENDRX_MASK 0x00000040\n#define AVR32_SSC_IDR_ENDRX_OFFSET 6\n#define AVR32_SSC_IDR_ENDRX_SIZE 1\n#define AVR32_SSC_IDR_ENDTX 2\n#define AVR32_SSC_IDR_ENDTX_MASK 0x00000004\n#define AVR32_SSC_IDR_ENDTX_OFFSET 2\n#define AVR32_SSC_IDR_ENDTX_SIZE 1\n#define AVR32_SSC_IDR_OVRUN 5\n#define AVR32_SSC_IDR_OVRUN_MASK 0x00000020\n#define AVR32_SSC_IDR_OVRUN_OFFSET 5\n#define AVR32_SSC_IDR_OVRUN_SIZE 1\n#define AVR32_SSC_IDR_RXBUFF 7\n#define AVR32_SSC_IDR_RXBUFF_MASK 0x00000080\n#define AVR32_SSC_IDR_RXBUFF_OFFSET 7\n#define AVR32_SSC_IDR_RXBUFF_SIZE 1\n#define AVR32_SSC_IDR_RXRDY 4\n#define AVR32_SSC_IDR_RXRDY_MASK 0x00000010\n#define AVR32_SSC_IDR_RXRDY_OFFSET 4\n#define AVR32_SSC_IDR_RXRDY_SIZE 1\n#define AVR32_SSC_IDR_RXSYN 11\n#define AVR32_SSC_IDR_RXSYN_MASK 0x00000800\n#define AVR32_SSC_IDR_RXSYN_OFFSET 11\n#define AVR32_SSC_IDR_RXSYN_SIZE 1\n#define AVR32_SSC_IDR_TXBUFE 3\n#define AVR32_SSC_IDR_TXBUFE_MASK 0x00000008\n#define AVR32_SSC_IDR_TXBUFE_OFFSET 3\n#define AVR32_SSC_IDR_TXBUFE_SIZE 1\n#define AVR32_SSC_IDR_TXEMPTY 1\n#define AVR32_SSC_IDR_TXEMPTY_MASK 0x00000002\n#define AVR32_SSC_IDR_TXEMPTY_OFFSET 1\n#define AVR32_SSC_IDR_TXEMPTY_SIZE 1\n#define AVR32_SSC_IDR_TXRDY 0\n#define AVR32_SSC_IDR_TXRDY_MASK 0x00000001\n#define AVR32_SSC_IDR_TXRDY_OFFSET 0\n#define AVR32_SSC_IDR_TXRDY_SIZE 1\n#define AVR32_SSC_IDR_TXSYN 10\n#define AVR32_SSC_IDR_TXSYN_MASK 0x00000400\n#define AVR32_SSC_IDR_TXSYN_OFFSET 10\n#define AVR32_SSC_IDR_TXSYN_SIZE 1\n#define AVR32_SSC_IER 0x00000044\n#define AVR32_SSC_IER_CP0 8\n#define AVR32_SSC_IER_CP0_MASK 0x00000100\n#define AVR32_SSC_IER_CP0_OFFSET 8\n#define AVR32_SSC_IER_CP0_SIZE 1\n#define AVR32_SSC_IER_CP1 9\n#define AVR32_SSC_IER_CP1_MASK 0x00000200\n#define AVR32_SSC_IER_CP1_OFFSET 9\n#define AVR32_SSC_IER_CP1_SIZE 1\n#define AVR32_SSC_IER_ENDRX 6\n#define AVR32_SSC_IER_ENDRX_MASK 0x00000040\n#define AVR32_SSC_IER_ENDRX_OFFSET 6\n#define AVR32_SSC_IER_ENDRX_SIZE 1\n#define AVR32_SSC_IER_ENDTX 2\n#define AVR32_SSC_IER_ENDTX_MASK 0x00000004\n#define AVR32_SSC_IER_ENDTX_OFFSET 2\n#define AVR32_SSC_IER_ENDTX_SIZE 1\n#define AVR32_SSC_IER_OVRUN 5\n#define AVR32_SSC_IER_OVRUN_MASK 0x00000020\n#define AVR32_SSC_IER_OVRUN_OFFSET 5\n#define AVR32_SSC_IER_OVRUN_SIZE 1\n#define AVR32_SSC_IER_RXBUFF 7\n#define AVR32_SSC_IER_RXBUFF_MASK 0x00000080\n#define AVR32_SSC_IER_RXBUFF_OFFSET 7\n#define AVR32_SSC_IER_RXBUFF_SIZE 1\n#define AVR32_SSC_IER_RXRDY 4\n#define AVR32_SSC_IER_RXRDY_MASK 0x00000010\n#define AVR32_SSC_IER_RXRDY_OFFSET 4\n#define AVR32_SSC_IER_RXRDY_SIZE 1\n#define AVR32_SSC_IER_RXSYN 11\n#define AVR32_SSC_IER_RXSYN_MASK 0x00000800\n#define AVR32_SSC_IER_RXSYN_OFFSET 11\n#define AVR32_SSC_IER_RXSYN_SIZE 1\n#define AVR32_SSC_IER_TXBUFE 3\n#define AVR32_SSC_IER_TXBUFE_MASK 0x00000008\n#define AVR32_SSC_IER_TXBUFE_OFFSET 3\n#define AVR32_SSC_IER_TXBUFE_SIZE 1\n#define AVR32_SSC_IER_TXEMPTY 1\n#define AVR32_SSC_IER_TXEMPTY_MASK 0x00000002\n#define AVR32_SSC_IER_TXEMPTY_OFFSET 1\n#define AVR32_SSC_IER_TXEMPTY_SIZE 1\n#define AVR32_SSC_IER_TXRDY 0\n#define AVR32_SSC_IER_TXRDY_MASK 0x00000001\n#define AVR32_SSC_IER_TXRDY_OFFSET 0\n#define AVR32_SSC_IER_TXRDY_SIZE 1\n#define AVR32_SSC_IER_TXSYN 10\n#define AVR32_SSC_IER_TXSYN_MASK 0x00000400\n#define AVR32_SSC_IER_TXSYN_OFFSET 10\n#define AVR32_SSC_IER_TXSYN_SIZE 1\n#define AVR32_SSC_IMR 0x0000004c\n#define AVR32_SSC_IMR_CP0 8\n#define AVR32_SSC_IMR_CP0_MASK 0x00000100\n#define AVR32_SSC_IMR_CP0_OFFSET 8\n#define AVR32_SSC_IMR_CP0_SIZE 1\n#define AVR32_SSC_IMR_CP1 9\n#define AVR32_SSC_IMR_CP1_MASK 0x00000200\n#define AVR32_SSC_IMR_CP1_OFFSET 9\n#define AVR32_SSC_IMR_CP1_SIZE 1\n#define AVR32_SSC_IMR_ENDRX 6\n#define AVR32_SSC_IMR_ENDRX_MASK 0x00000040\n#define AVR32_SSC_IMR_ENDRX_OFFSET 6\n#define AVR32_SSC_IMR_ENDRX_SIZE 1\n#define AVR32_SSC_IMR_ENDTX 2\n#define AVR32_SSC_IMR_ENDTX_MASK 0x00000004\n#define AVR32_SSC_IMR_ENDTX_OFFSET 2\n#define AVR32_SSC_IMR_ENDTX_SIZE 1\n#define AVR32_SSC_IMR_OVRUN 5\n#define AVR32_SSC_IMR_OVRUN_MASK 0x00000020\n#define AVR32_SSC_IMR_OVRUN_OFFSET 5\n#define AVR32_SSC_IMR_OVRUN_SIZE 1\n#define AVR32_SSC_IMR_RXBUFF 7\n#define AVR32_SSC_IMR_RXBUFF_MASK 0x00000080\n#define AVR32_SSC_IMR_RXBUFF_OFFSET 7\n#define AVR32_SSC_IMR_RXBUFF_SIZE 1\n#define AVR32_SSC_IMR_RXRDY 4\n#define AVR32_SSC_IMR_RXRDY_MASK 0x00000010\n#define AVR32_SSC_IMR_RXRDY_OFFSET 4\n#define AVR32_SSC_IMR_RXRDY_SIZE 1\n#define AVR32_SSC_IMR_RXSYN 11\n#define AVR32_SSC_IMR_RXSYN_MASK 0x00000800\n#define AVR32_SSC_IMR_RXSYN_OFFSET 11\n#define AVR32_SSC_IMR_RXSYN_SIZE 1\n#define AVR32_SSC_IMR_TXBUFE 3\n#define AVR32_SSC_IMR_TXBUFE_MASK 0x00000008\n#define AVR32_SSC_IMR_TXBUFE_OFFSET 3\n#define AVR32_SSC_IMR_TXBUFE_SIZE 1\n#define AVR32_SSC_IMR_TXEMPTY 1\n#define AVR32_SSC_IMR_TXEMPTY_MASK 0x00000002\n#define AVR32_SSC_IMR_TXEMPTY_OFFSET 1\n#define AVR32_SSC_IMR_TXEMPTY_SIZE 1\n#define AVR32_SSC_IMR_TXRDY 0\n#define AVR32_SSC_IMR_TXRDY_MASK 0x00000001\n#define AVR32_SSC_IMR_TXRDY_OFFSET 0\n#define AVR32_SSC_IMR_TXRDY_SIZE 1\n#define AVR32_SSC_IMR_TXSYN 10\n#define AVR32_SSC_IMR_TXSYN_MASK 0x00000400\n#define AVR32_SSC_IMR_TXSYN_OFFSET 10\n#define AVR32_SSC_IMR_TXSYN_SIZE 1\n#define AVR32_SSC_INPUT_ONLY 0x00000000\n#define AVR32_SSC_LOOP 5\n#define AVR32_SSC_LOOP_MASK 0x00000020\n#define AVR32_SSC_LOOP_OFFSET 5\n#define AVR32_SSC_LOOP_SIZE 1\n#define AVR32_SSC_LOW 0x00000001\n#define AVR32_SSC_LOW_DURING_DATA 0x00000003\n#define AVR32_SSC_MSBF 7\n#define AVR32_SSC_MSBF_MASK 0x00000080\n#define AVR32_SSC_MSBF_OFFSET 7\n#define AVR32_SSC_MSBF_SIZE 1\n#define AVR32_SSC_NEG_PULSE 0x00000001\n#define AVR32_SSC_NONE 0x00000000\n#define AVR32_SSC_NOT_ACTIVE 0x00000000\n#define AVR32_SSC_OVRUN 5\n#define AVR32_SSC_OVRUN_MASK 0x00000020\n#define AVR32_SSC_OVRUN_OFFSET 5\n#define AVR32_SSC_OVRUN_SIZE 1\n#define AVR32_SSC_PERIOD 24\n#define AVR32_SSC_PERIOD_MASK 0xff000000\n#define AVR32_SSC_PERIOD_OFFSET 24\n#define AVR32_SSC_PERIOD_SIZE 8\n#define AVR32_SSC_POS_PULSE 0x00000002\n#define AVR32_SSC_RC0R 0x00000038\n#define AVR32_SSC_RC0R_CP0 0\n#define AVR32_SSC_RC0R_CP0_MASK 0x0000ffff\n#define AVR32_SSC_RC0R_CP0_OFFSET 0\n#define AVR32_SSC_RC0R_CP0_SIZE 16\n#define AVR32_SSC_RC1R 0x0000003c\n#define AVR32_SSC_RC1R_CP1 0\n#define AVR32_SSC_RC1R_CP1_MASK 0x0000ffff\n#define AVR32_SSC_RC1R_CP1_OFFSET 0\n#define AVR32_SSC_RC1R_CP1_SIZE 16\n#define AVR32_SSC_RCMR 0x00000010\n#define AVR32_SSC_RCMR_CKG 6\n#define AVR32_SSC_RCMR_CKG_HIGH 0x00000002\n#define AVR32_SSC_RCMR_CKG_LOW 0x00000001\n#define AVR32_SSC_RCMR_CKG_MASK 0x000000c0\n#define AVR32_SSC_RCMR_CKG_NONE 0x00000000\n#define AVR32_SSC_RCMR_CKG_OFFSET 6\n#define AVR32_SSC_RCMR_CKG_SIZE 2\n#define AVR32_SSC_RCMR_CKI 5\n#define AVR32_SSC_RCMR_CKI_MASK 0x00000020\n#define AVR32_SSC_RCMR_CKI_OFFSET 5\n#define AVR32_SSC_RCMR_CKI_SIZE 1\n#define AVR32_SSC_RCMR_CKO 2\n#define AVR32_SSC_RCMR_CKO_CONTINOUS_CLOCK_OUTPUT 0x00000001\n#define AVR32_SSC_RCMR_CKO_INPUT_ONLY 0x00000000\n#define AVR32_SSC_RCMR_CKO_MASK 0x0000001c\n#define AVR32_SSC_RCMR_CKO_OFFSET 2\n#define AVR32_SSC_RCMR_CKO_SIZE 3\n#define AVR32_SSC_RCMR_CKS 0\n#define AVR32_SSC_RCMR_CKS_DIV_CLOCK 0x00000000\n#define AVR32_SSC_RCMR_CKS_MASK 0x00000003\n#define AVR32_SSC_RCMR_CKS_OFFSET 0\n#define AVR32_SSC_RCMR_CKS_RK_PIN 0x00000002\n#define AVR32_SSC_RCMR_CKS_SIZE 2\n#define AVR32_SSC_RCMR_CKS_TK_CLOCK 0x00000001\n#define AVR32_SSC_RCMR_PERIOD 24\n#define AVR32_SSC_RCMR_PERIOD_MASK 0xff000000\n#define AVR32_SSC_RCMR_PERIOD_OFFSET 24\n#define AVR32_SSC_RCMR_PERIOD_SIZE 8\n#define AVR32_SSC_RCMR_START 8\n#define AVR32_SSC_RCMR_START_COMPARE_0 0x00000008\n#define AVR32_SSC_RCMR_START_CONTINOUS 0x00000000\n#define AVR32_SSC_RCMR_START_DETECT_ANY_EDGE_RF 0x00000007\n#define AVR32_SSC_RCMR_START_DETECT_FALLING_RF 0x00000004\n#define AVR32_SSC_RCMR_START_DETECT_HIGH_RF 0x00000003\n#define AVR32_SSC_RCMR_START_DETECT_LEVEL_CHANGE_RF 0x00000006\n#define AVR32_SSC_RCMR_START_DETECT_LOW_RF 0x00000002\n#define AVR32_SSC_RCMR_START_DETECT_RISING_RF 0x00000005\n#define AVR32_SSC_RCMR_START_MASK 0x00000f00\n#define AVR32_SSC_RCMR_START_OFFSET 8\n#define AVR32_SSC_RCMR_START_SIZE 4\n#define AVR32_SSC_RCMR_START_TRANSMIT_START 0x00000001\n#define AVR32_SSC_RCMR_STOP 12\n#define AVR32_SSC_RCMR_STOP_MASK 0x00001000\n#define AVR32_SSC_RCMR_STOP_OFFSET 12\n#define AVR32_SSC_RCMR_STOP_SIZE 1\n#define AVR32_SSC_RCMR_STTDLY 16\n#define AVR32_SSC_RCMR_STTDLY_MASK 0x00ff0000\n#define AVR32_SSC_RCMR_STTDLY_OFFSET 16\n#define AVR32_SSC_RCMR_STTDLY_SIZE 8\n#define AVR32_SSC_RDAT 0\n#define AVR32_SSC_RDAT_MASK 0xffffffff\n#define AVR32_SSC_RDAT_OFFSET 0\n#define AVR32_SSC_RDAT_SIZE 32\n#define AVR32_SSC_RECEIVE_START 0x00000001\n#define AVR32_SSC_RFMR 0x00000014\n#define AVR32_SSC_RFMR_DATLEN 0\n#define AVR32_SSC_RFMR_DATLEN_MASK 0x0000001f\n#define AVR32_SSC_RFMR_DATLEN_OFFSET 0\n#define AVR32_SSC_RFMR_DATLEN_SIZE 5\n#define AVR32_SSC_RFMR_DATNB 8\n#define AVR32_SSC_RFMR_DATNB_MASK 0x00000f00\n#define AVR32_SSC_RFMR_DATNB_OFFSET 8\n#define AVR32_SSC_RFMR_DATNB_SIZE 4\n#define AVR32_SSC_RFMR_FSEDGE 24\n#define AVR32_SSC_RFMR_FSEDGE_MASK 0x01000000\n#define AVR32_SSC_RFMR_FSEDGE_OFFSET 24\n#define AVR32_SSC_RFMR_FSEDGE_SIZE 1\n#define AVR32_SSC_RFMR_FSLEN 16\n#define AVR32_SSC_RFMR_FSLENHI 28\n#define AVR32_SSC_RFMR_FSLENHI_MASK 0xf0000000\n#define AVR32_SSC_RFMR_FSLENHI_OFFSET 28\n#define AVR32_SSC_RFMR_FSLENHI_SIZE 4\n#define AVR32_SSC_RFMR_FSLEN_MASK 0x000f0000\n#define AVR32_SSC_RFMR_FSLEN_OFFSET 16\n#define AVR32_SSC_RFMR_FSLEN_SIZE 4\n#define AVR32_SSC_RFMR_FSOS 20\n#define AVR32_SSC_RFMR_FSOS_HIGH_DURING_DATA 0x00000004\n#define AVR32_SSC_RFMR_FSOS_INPUT_ONLY 0x00000000\n#define AVR32_SSC_RFMR_FSOS_LOW_DURING_DATA 0x00000003\n#define AVR32_SSC_RFMR_FSOS_MASK 0x00700000\n#define AVR32_SSC_RFMR_FSOS_NEG_PULSE 0x00000001\n#define AVR32_SSC_RFMR_FSOS_OFFSET 20\n#define AVR32_SSC_RFMR_FSOS_POS_PULSE 0x00000002\n#define AVR32_SSC_RFMR_FSOS_SIZE 3\n#define AVR32_SSC_RFMR_FSOS_TOGGLE_DATA_START 0x00000005\n#define AVR32_SSC_RFMR_LOOP 5\n#define AVR32_SSC_RFMR_LOOP_MASK 0x00000020\n#define AVR32_SSC_RFMR_LOOP_OFFSET 5\n#define AVR32_SSC_RFMR_LOOP_SIZE 1\n#define AVR32_SSC_RFMR_MSBF 7\n#define AVR32_SSC_RFMR_MSBF_MASK 0x00000080\n#define AVR32_SSC_RFMR_MSBF_OFFSET 7\n#define AVR32_SSC_RFMR_MSBF_SIZE 1\n#define AVR32_SSC_RHR 0x00000020\n#define AVR32_SSC_RHR_RDAT 0\n#define AVR32_SSC_RHR_RDAT_MASK 0xffffffff\n#define AVR32_SSC_RHR_RDAT_OFFSET 0\n#define AVR32_SSC_RHR_RDAT_SIZE 32\n#define AVR32_SSC_RK_CLOCK 0x00000001\n#define AVR32_SSC_RK_PIN 0x00000002\n#define AVR32_SSC_RSDAT 0\n#define AVR32_SSC_RSDAT_MASK 0x0000ffff\n#define AVR32_SSC_RSDAT_OFFSET 0\n#define AVR32_SSC_RSDAT_SIZE 16\n#define AVR32_SSC_RSHR 0x00000030\n#define AVR32_SSC_RSHR_RSDAT 0\n#define AVR32_SSC_RSHR_RSDAT_MASK 0x0000ffff\n#define AVR32_SSC_RSHR_RSDAT_OFFSET 0\n#define AVR32_SSC_RSHR_RSDAT_SIZE 16\n#define AVR32_SSC_RXBUFF 7\n#define AVR32_SSC_RXBUFF_MASK 0x00000080\n#define AVR32_SSC_RXBUFF_OFFSET 7\n#define AVR32_SSC_RXBUFF_SIZE 1\n#define AVR32_SSC_RXDIS 1\n#define AVR32_SSC_RXDIS_MASK 0x00000002\n#define AVR32_SSC_RXDIS_OFFSET 1\n#define AVR32_SSC_RXDIS_SIZE 1\n#define AVR32_SSC_RXEN_SIZE 1\n#define AVR32_SSC_RXRDY 4\n#define AVR32_SSC_RXRDY_MASK 0x00000010\n#define AVR32_SSC_RXRDY_OFFSET 4\n#define AVR32_SSC_RXRDY_SIZE 1\n#define AVR32_SSC_RXSYN 11\n#define AVR32_SSC_RXSYN_MASK 0x00000800\n#define AVR32_SSC_RXSYN_OFFSET 11\n#define AVR32_SSC_RXSYN_SIZE 1\n#define AVR32_SSC_SR 0x00000040\n#define AVR32_SSC_SR_CP0 8\n#define AVR32_SSC_SR_CP0_MASK 0x00000100\n#define AVR32_SSC_SR_CP0_OFFSET 8\n#define AVR32_SSC_SR_CP0_SIZE 1\n#define AVR32_SSC_SR_CP1 9\n#define AVR32_SSC_SR_CP1_MASK 0x00000200\n#define AVR32_SSC_SR_CP1_OFFSET 9\n#define AVR32_SSC_SR_CP1_SIZE 1\n#define AVR32_SSC_SR_ENDRX 6\n#define AVR32_SSC_SR_ENDRX_MASK 0x00000040\n#define AVR32_SSC_SR_ENDRX_OFFSET 6\n#define AVR32_SSC_SR_ENDRX_SIZE 1\n#define AVR32_SSC_SR_ENDTX 2\n#define AVR32_SSC_SR_ENDTX_MASK 0x00000004\n#define AVR32_SSC_SR_ENDTX_OFFSET 2\n#define AVR32_SSC_SR_ENDTX_SIZE 1\n#define AVR32_SSC_SR_OVRUN 5\n#define AVR32_SSC_SR_OVRUN_MASK 0x00000020\n#define AVR32_SSC_SR_OVRUN_OFFSET 5\n#define AVR32_SSC_SR_OVRUN_SIZE 1\n#define AVR32_SSC_SR_RXBUFF 7\n#define AVR32_SSC_SR_RXBUFF_MASK 0x00000080\n#define AVR32_SSC_SR_RXBUFF_OFFSET 7\n#define AVR32_SSC_SR_RXBUFF_SIZE 1\n#define AVR32_SSC_SR_RXEN 17\n#define AVR32_SSC_SR_RXEN_MASK 0x00020000\n#define AVR32_SSC_SR_RXEN_OFFSET 17\n#define AVR32_SSC_SR_RXEN_SIZE 1\n#define AVR32_SSC_SR_RXRDY 4\n#define AVR32_SSC_SR_RXRDY_MASK 0x00000010\n#define AVR32_SSC_SR_RXRDY_OFFSET 4\n#define AVR32_SSC_SR_RXRDY_SIZE 1\n#define AVR32_SSC_SR_RXSYN 11\n#define AVR32_SSC_SR_RXSYN_MASK 0x00000800\n#define AVR32_SSC_SR_RXSYN_OFFSET 11\n#define AVR32_SSC_SR_RXSYN_SIZE 1\n#define AVR32_SSC_SR_TXBUFE 3\n#define AVR32_SSC_SR_TXBUFE_MASK 0x00000008\n#define AVR32_SSC_SR_TXBUFE_OFFSET 3\n#define AVR32_SSC_SR_TXBUFE_SIZE 1\n#define AVR32_SSC_SR_TXEMPTY 1\n#define AVR32_SSC_SR_TXEMPTY_MASK 0x00000002\n#define AVR32_SSC_SR_TXEMPTY_OFFSET 1\n#define AVR32_SSC_SR_TXEMPTY_SIZE 1\n#define AVR32_SSC_SR_TXEN 16\n#define AVR32_SSC_SR_TXEN_MASK 0x00010000\n#define AVR32_SSC_SR_TXEN_OFFSET 16\n#define AVR32_SSC_SR_TXEN_SIZE 1\n#define AVR32_SSC_SR_TXRDY 0\n#define AVR32_SSC_SR_TXRDY_MASK 0x00000001\n#define AVR32_SSC_SR_TXRDY_OFFSET 0\n#define AVR32_SSC_SR_TXRDY_SIZE 1\n#define AVR32_SSC_SR_TXSYN 10\n#define AVR32_SSC_SR_TXSYN_MASK 0x00000400\n#define AVR32_SSC_SR_TXSYN_OFFSET 10\n#define AVR32_SSC_SR_TXSYN_SIZE 1\n#define AVR32_SSC_START 8\n#define AVR32_SSC_START_COMPARE_0 0x00000008\n#define AVR32_SSC_START_CONTINOUS 0x00000000\n#define AVR32_SSC_START_DETECT_ANY_EDGE_RF 0x00000007\n#define AVR32_SSC_START_DETECT_ANY_EDGE_TF 0x00000007\n#define AVR32_SSC_START_DETECT_FALLING_RF 0x00000004\n#define AVR32_SSC_START_DETECT_FALLING_TF 0x00000004\n#define AVR32_SSC_START_DETECT_HIGH_RF 0x00000003\n#define AVR32_SSC_START_DETECT_HIGH_TF 0x00000003\n#define AVR32_SSC_START_DETECT_LEVEL_CHANGE_RF 0x00000006\n#define AVR32_SSC_START_DETECT_LEVEL_CHANGE_TF 0x00000006\n#define AVR32_SSC_START_DETECT_LOW_RF 0x00000002\n#define AVR32_SSC_START_DETECT_LOW_TF 0x00000002\n#define AVR32_SSC_START_DETECT_RISING_RF 0x00000005\n#define AVR32_SSC_START_DETECT_RISING_TF 0x00000005\n#define AVR32_SSC_START_MASK 0x00000f00\n#define AVR32_SSC_START_OFFSET 8\n#define AVR32_SSC_START_RECEIVE_START 0x00000001\n#define AVR32_SSC_START_SIZE 4\n#define AVR32_SSC_START_TRANSMIT_START 0x00000001\n#define AVR32_SSC_STOP 12\n#define AVR32_SSC_STOP_MASK 0x00001000\n#define AVR32_SSC_STOP_OFFSET 12\n#define AVR32_SSC_STOP_SIZE 1\n#define AVR32_SSC_STTDLY 16\n#define AVR32_SSC_STTDLY_MASK 0x00ff0000\n#define AVR32_SSC_STTDLY_OFFSET 16\n#define AVR32_SSC_STTDLY_SIZE 8\n#define AVR32_SSC_SWRST 15\n#define AVR32_SSC_SWRST_MASK 0x00008000\n#define AVR32_SSC_SWRST_OFFSET 15\n#define AVR32_SSC_SWRST_SIZE 1\n#define AVR32_SSC_TCMR 0x00000018\n#define AVR32_SSC_TCMR_CKG 6\n#define AVR32_SSC_TCMR_CKG_HIGH 0x00000002\n#define AVR32_SSC_TCMR_CKG_LOW 0x00000001\n#define AVR32_SSC_TCMR_CKG_MASK 0x000000c0\n#define AVR32_SSC_TCMR_CKG_NONE 0x00000000\n#define AVR32_SSC_TCMR_CKG_OFFSET 6\n#define AVR32_SSC_TCMR_CKG_SIZE 2\n#define AVR32_SSC_TCMR_CKI 5\n#define AVR32_SSC_TCMR_CKI_MASK 0x00000020\n#define AVR32_SSC_TCMR_CKI_OFFSET 5\n#define AVR32_SSC_TCMR_CKI_SIZE 1\n#define AVR32_SSC_TCMR_CKO 2\n#define AVR32_SSC_TCMR_CKO_CONTINOUS_CLOCK_OUTPUT 0x00000001\n#define AVR32_SSC_TCMR_CKO_INPUT_ONLY 0x00000000\n#define AVR32_SSC_TCMR_CKO_MASK 0x0000001c\n#define AVR32_SSC_TCMR_CKO_OFFSET 2\n#define AVR32_SSC_TCMR_CKO_SIZE 3\n#define AVR32_SSC_TCMR_CKS 0\n#define AVR32_SSC_TCMR_CKS_DIV_CLOCK 0x00000000\n#define AVR32_SSC_TCMR_CKS_MASK 0x00000003\n#define AVR32_SSC_TCMR_CKS_OFFSET 0\n#define AVR32_SSC_TCMR_CKS_RK_CLOCK 0x00000001\n#define AVR32_SSC_TCMR_CKS_SIZE 2\n#define AVR32_SSC_TCMR_CKS_TK_PIN 0x00000002\n#define AVR32_SSC_TCMR_PERIOD 24\n#define AVR32_SSC_TCMR_PERIOD_MASK 0xff000000\n#define AVR32_SSC_TCMR_PERIOD_OFFSET 24\n#define AVR32_SSC_TCMR_PERIOD_SIZE 8\n#define AVR32_SSC_TCMR_START 8\n#define AVR32_SSC_TCMR_START_CONTINOUS 0x00000000\n#define AVR32_SSC_TCMR_START_DETECT_ANY_EDGE_TF 0x00000007\n#define AVR32_SSC_TCMR_START_DETECT_FALLING_TF 0x00000004\n#define AVR32_SSC_TCMR_START_DETECT_HIGH_TF 0x00000003\n#define AVR32_SSC_TCMR_START_DETECT_LEVEL_CHANGE_TF 0x00000006\n#define AVR32_SSC_TCMR_START_DETECT_LOW_TF 0x00000002\n#define AVR32_SSC_TCMR_START_DETECT_RISING_TF 0x00000005\n#define AVR32_SSC_TCMR_START_MASK 0x00000f00\n#define AVR32_SSC_TCMR_START_OFFSET 8\n#define AVR32_SSC_TCMR_START_RECEIVE_START 0x00000001\n#define AVR32_SSC_TCMR_START_SIZE 4\n#define AVR32_SSC_TCMR_STTDLY 16\n#define AVR32_SSC_TCMR_STTDLY_MASK 0x00ff0000\n#define AVR32_SSC_TCMR_STTDLY_OFFSET 16\n#define AVR32_SSC_TCMR_STTDLY_SIZE 8\n#define AVR32_SSC_TDAT 0\n#define AVR32_SSC_TDAT_MASK 0xffffffff\n#define AVR32_SSC_TDAT_OFFSET 0\n#define AVR32_SSC_TDAT_SIZE 32\n#define AVR32_SSC_TFMR 0x0000001c\n#define AVR32_SSC_TFMR_DATDEF 5\n#define AVR32_SSC_TFMR_DATDEF_MASK 0x00000020\n#define AVR32_SSC_TFMR_DATDEF_OFFSET 5\n#define AVR32_SSC_TFMR_DATDEF_SIZE 1\n#define AVR32_SSC_TFMR_DATLEN 0\n#define AVR32_SSC_TFMR_DATLEN_MASK 0x0000001f\n#define AVR32_SSC_TFMR_DATLEN_OFFSET 0\n#define AVR32_SSC_TFMR_DATLEN_SIZE 5\n#define AVR32_SSC_TFMR_DATNB 8\n#define AVR32_SSC_TFMR_DATNB_MASK 0x00000f00\n#define AVR32_SSC_TFMR_DATNB_OFFSET 8\n#define AVR32_SSC_TFMR_DATNB_SIZE 4\n#define AVR32_SSC_TFMR_FSDEN 23\n#define AVR32_SSC_TFMR_FSDEN_MASK 0x00800000\n#define AVR32_SSC_TFMR_FSDEN_OFFSET 23\n#define AVR32_SSC_TFMR_FSDEN_SIZE 1\n#define AVR32_SSC_TFMR_FSEDGE 24\n#define AVR32_SSC_TFMR_FSEDGE_MASK 0x01000000\n#define AVR32_SSC_TFMR_FSEDGE_OFFSET 24\n#define AVR32_SSC_TFMR_FSEDGE_SIZE 1\n#define AVR32_SSC_TFMR_FSLEN 16\n#define AVR32_SSC_TFMR_FSLENHI 28\n#define AVR32_SSC_TFMR_FSLENHI_MASK 0xf0000000\n#define AVR32_SSC_TFMR_FSLENHI_OFFSET 28\n#define AVR32_SSC_TFMR_FSLENHI_SIZE 4\n#define AVR32_SSC_TFMR_FSLEN_MASK 0x000f0000\n#define AVR32_SSC_TFMR_FSLEN_OFFSET 16\n#define AVR32_SSC_TFMR_FSLEN_SIZE 4\n#define AVR32_SSC_TFMR_FSOS 20\n#define AVR32_SSC_TFMR_FSOS_HIGH_DURING_DATA 0x00000004\n#define AVR32_SSC_TFMR_FSOS_INPUT_ONLY 0x00000000\n#define AVR32_SSC_TFMR_FSOS_LOW_DURING_DATA 0x00000003\n#define AVR32_SSC_TFMR_FSOS_MASK 0x00700000\n#define AVR32_SSC_TFMR_FSOS_NEG_PULSE 0x00000001\n#define AVR32_SSC_TFMR_FSOS_OFFSET 20\n#define AVR32_SSC_TFMR_FSOS_POS_PULSE 0x00000002\n#define AVR32_SSC_TFMR_FSOS_SIZE 3\n#define AVR32_SSC_TFMR_FSOS_TOGGLE_DATA_START 0x00000005\n#define AVR32_SSC_TFMR_MSBF 7\n#define AVR32_SSC_TFMR_MSBF_MASK 0x00000080\n#define AVR32_SSC_TFMR_MSBF_OFFSET 7\n#define AVR32_SSC_TFMR_MSBF_SIZE 1\n#define AVR32_SSC_THR 0x00000024\n#define AVR32_SSC_THR_TDAT 0\n#define AVR32_SSC_THR_TDAT_MASK 0xffffffff\n#define AVR32_SSC_THR_TDAT_OFFSET 0\n#define AVR32_SSC_THR_TDAT_SIZE 32\n#define AVR32_SSC_TK_CLOCK 0x00000001\n#define AVR32_SSC_TK_PIN 0x00000002\n#define AVR32_SSC_TOGGLE_DATA_START 0x00000005\n#define AVR32_SSC_TRANSMIT_START 0x00000001\n#define AVR32_SSC_TSDAT 0\n#define AVR32_SSC_TSDAT_MASK 0x0000ffff\n#define AVR32_SSC_TSDAT_OFFSET 0\n#define AVR32_SSC_TSDAT_SIZE 16\n#define AVR32_SSC_TSHR 0x00000034\n#define AVR32_SSC_TSHR_TSDAT 0\n#define AVR32_SSC_TSHR_TSDAT_MASK 0x0000ffff\n#define AVR32_SSC_TSHR_TSDAT_OFFSET 0\n#define AVR32_SSC_TSHR_TSDAT_SIZE 16\n#define AVR32_SSC_TXBUFE 3\n#define AVR32_SSC_TXBUFE_MASK 0x00000008\n#define AVR32_SSC_TXBUFE_OFFSET 3\n#define AVR32_SSC_TXBUFE_SIZE 1\n#define AVR32_SSC_TXDIS 9\n#define AVR32_SSC_TXDIS_MASK 0x00000200\n#define AVR32_SSC_TXDIS_OFFSET 9\n#define AVR32_SSC_TXDIS_SIZE 1\n#define AVR32_SSC_TXEMPTY 1\n#define AVR32_SSC_TXEMPTY_MASK 0x00000002\n#define AVR32_SSC_TXEMPTY_OFFSET 1\n#define AVR32_SSC_TXEMPTY_SIZE 1\n#define AVR32_SSC_TXEN_SIZE 1\n#define AVR32_SSC_TXRDY 0\n#define AVR32_SSC_TXRDY_MASK 0x00000001\n#define AVR32_SSC_TXRDY_OFFSET 0\n#define AVR32_SSC_TXRDY_SIZE 1\n#define AVR32_SSC_TXSYN 10\n#define AVR32_SSC_TXSYN_MASK 0x00000400\n#define AVR32_SSC_TXSYN_OFFSET 10\n#define AVR32_SSC_TXSYN_SIZE 1\n#define AVR32_SSC_VARIANT 16\n#define AVR32_SSC_VARIANT_MASK 0x00070000\n#define AVR32_SSC_VARIANT_OFFSET 16\n#define AVR32_SSC_VARIANT_SIZE 3\n#define AVR32_SSC_VERSION 0x000000fc\n#define AVR32_SSC_VERSION_MASK 0x00000fff\n#define AVR32_SSC_VERSION_OFFSET 0\n#define AVR32_SSC_VERSION_SIZE 12\n#define AVR32_SSC_VERSION_VARIANT 16\n#define AVR32_SSC_VERSION_VARIANT_MASK 0x00070000\n#define AVR32_SSC_VERSION_VARIANT_OFFSET 16\n#define AVR32_SSC_VERSION_VARIANT_SIZE 3\n#define AVR32_SSC_VERSION_VERSION 0\n#define AVR32_SSC_VERSION_VERSION_MASK 0x00000fff\n#define AVR32_SSC_VERSION_VERSION_OFFSET 0\n#define AVR32_SSC_VERSION_VERSION_SIZE 12\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_ssc_cr_t {\n unsigned int :16;\n unsigned int swrst : 1;\n unsigned int : 5;\n unsigned int txdis : 1;\n unsigned int txen : 1;\n unsigned int : 6;\n unsigned int rxdis : 1;\n unsigned int rxen : 1;\n} avr32_ssc_cr_t;\n\n\n\ntypedef struct avr32_ssc_cmr_t {\n unsigned int :20;\n unsigned int div :12;\n} avr32_ssc_cmr_t;\n\n\n\ntypedef struct avr32_ssc_rcmr_t {\n unsigned int period : 8;\n unsigned int sttdly : 8;\n unsigned int : 3;\n unsigned int stop : 1;\n unsigned int start : 4;\n unsigned int ckg : 2;\n unsigned int cki : 1;\n unsigned int cko : 3;\n unsigned int cks : 2;\n} avr32_ssc_rcmr_t;\n\n\n\ntypedef struct avr32_ssc_rfmr_t {\n unsigned int fslenhi : 4;\n unsigned int : 3;\n unsigned int fsedge : 1;\n unsigned int : 1;\n unsigned int fsos : 3;\n unsigned int fslen : 4;\n unsigned int : 4;\n unsigned int datnb : 4;\n unsigned int msbf : 1;\n unsigned int : 1;\n unsigned int loop : 1;\n unsigned int datlen : 5;\n} avr32_ssc_rfmr_t;\n\n\n\ntypedef struct avr32_ssc_tcmr_t {\n unsigned int period : 8;\n unsigned int sttdly : 8;\n unsigned int : 4;\n unsigned int start : 4;\n unsigned int ckg : 2;\n unsigned int cki : 1;\n unsigned int cko : 3;\n unsigned int cks : 2;\n} avr32_ssc_tcmr_t;\n\n\n\ntypedef struct avr32_ssc_tfmr_t {\n unsigned int fslenhi : 4;\n unsigned int : 3;\n unsigned int fsedge : 1;\n unsigned int fsden : 1;\n unsigned int fsos : 3;\n unsigned int fslen : 4;\n unsigned int : 4;\n unsigned int datnb : 4;\n unsigned int msbf : 1;\n unsigned int : 1;\n unsigned int datdef : 1;\n unsigned int datlen : 5;\n} avr32_ssc_tfmr_t;\n\n\n\ntypedef struct avr32_ssc_rshr_t {\n unsigned int :16;\n unsigned int rsdat :16;\n} avr32_ssc_rshr_t;\n\n\n\ntypedef struct avr32_ssc_tshr_t {\n unsigned int :16;\n unsigned int tsdat :16;\n} avr32_ssc_tshr_t;\n\n\n\ntypedef struct avr32_ssc_rc0r_t {\n unsigned int :16;\n unsigned int cp0 :16;\n} avr32_ssc_rc0r_t;\n\n\n\ntypedef struct avr32_ssc_rc1r_t {\n unsigned int :16;\n unsigned int cp1 :16;\n} avr32_ssc_rc1r_t;\n\n\n\ntypedef struct avr32_ssc_sr_t {\n unsigned int :14;\n unsigned int rxen : 1;\n unsigned int txen : 1;\n unsigned int : 4;\n unsigned int rxsyn : 1;\n unsigned int txsyn : 1;\n unsigned int cp1 : 1;\n unsigned int cp0 : 1;\n unsigned int rxbuff : 1;\n unsigned int endrx : 1;\n unsigned int ovrun : 1;\n unsigned int rxrdy : 1;\n unsigned int txbufe : 1;\n unsigned int endtx : 1;\n unsigned int txempty : 1;\n unsigned int txrdy : 1;\n} avr32_ssc_sr_t;\n\n\n\ntypedef struct avr32_ssc_ier_t {\n unsigned int :20;\n unsigned int rxsyn : 1;\n unsigned int txsyn : 1;\n unsigned int cp1 : 1;\n unsigned int cp0 : 1;\n unsigned int rxbuff : 1;\n unsigned int endrx : 1;\n unsigned int ovrun : 1;\n unsigned int rxrdy : 1;\n unsigned int txbufe : 1;\n unsigned int endtx : 1;\n unsigned int txempty : 1;\n unsigned int txrdy : 1;\n} avr32_ssc_ier_t;\n\n\n\ntypedef struct avr32_ssc_idr_t {\n unsigned int :20;\n unsigned int rxsyn : 1;\n unsigned int txsyn : 1;\n unsigned int cp1 : 1;\n unsigned int cp0 : 1;\n unsigned int rxbuff : 1;\n unsigned int endrx : 1;\n unsigned int ovrun : 1;\n unsigned int rxrdy : 1;\n unsigned int txbufe : 1;\n unsigned int endtx : 1;\n unsigned int txempty : 1;\n unsigned int txrdy : 1;\n} avr32_ssc_idr_t;\n\n\n\ntypedef struct avr32_ssc_imr_t {\n unsigned int :20;\n unsigned int rxsyn : 1;\n unsigned int txsyn : 1;\n unsigned int cp1 : 1;\n unsigned int cp0 : 1;\n unsigned int rxbuff : 1;\n unsigned int endrx : 1;\n unsigned int ovrun : 1;\n unsigned int rxrdy : 1;\n unsigned int txbufe : 1;\n unsigned int endtx : 1;\n unsigned int txempty : 1;\n unsigned int txrdy : 1;\n} avr32_ssc_imr_t;\n\n\n\ntypedef struct avr32_ssc_version_t {\n unsigned int :13;\n unsigned int variant : 3;\n unsigned int : 4;\n unsigned int version :12;\n} avr32_ssc_version_t;\n\n\n\ntypedef struct avr32_ssc_t {\n union {\n unsigned long cr ;//0x0000\n avr32_ssc_cr_t CR ;\n };\n union {\n unsigned long cmr ;//0x0004\n avr32_ssc_cmr_t CMR ;\n };\n unsigned int :32 ;//0x0008\n unsigned int :32 ;//0x000c\n union {\n unsigned long rcmr ;//0x0010\n avr32_ssc_rcmr_t RCMR ;\n };\n union {\n unsigned long rfmr ;//0x0014\n avr32_ssc_rfmr_t RFMR ;\n };\n union {\n unsigned long tcmr ;//0x0018\n avr32_ssc_tcmr_t TCMR ;\n };\n union {\n unsigned long tfmr ;//0x001c\n avr32_ssc_tfmr_t TFMR ;\n };\n const unsigned long rhr ;//0x0020\n unsigned long thr ;//0x0024\n unsigned int :32 ;//0x0028\n unsigned int :32 ;//0x002c\n union {\n const unsigned long rshr ;//0x0030\n const avr32_ssc_rshr_t RSHR ;\n };\n union {\n unsigned long tshr ;//0x0034\n avr32_ssc_tshr_t TSHR ;\n };\n union {\n unsigned long rc0r ;//0x0038\n avr32_ssc_rc0r_t RC0R ;\n };\n union {\n unsigned long rc1r ;//0x003c\n avr32_ssc_rc1r_t RC1R ;\n };\n union {\n const unsigned long sr ;//0x0040\n const avr32_ssc_sr_t SR ;\n };\n union {\n unsigned long ier ;//0x0044\n avr32_ssc_ier_t IER ;\n };\n union {\n unsigned long idr ;//0x0048\n avr32_ssc_idr_t IDR ;\n };\n union {\n const unsigned long imr ;//0x004c\n const avr32_ssc_imr_t IMR ;\n };\n unsigned int :32 ;//0x0050\n unsigned int :32 ;//0x0054\n unsigned int :32 ;//0x0058\n unsigned int :32 ;//0x005c\n unsigned int :32 ;//0x0060\n unsigned int :32 ;//0x0064\n unsigned int :32 ;//0x0068\n unsigned int :32 ;//0x006c\n unsigned int :32 ;//0x0070\n unsigned int :32 ;//0x0074\n unsigned int :32 ;//0x0078\n unsigned int :32 ;//0x007c\n unsigned int :32 ;//0x0080\n unsigned int :32 ;//0x0084\n unsigned int :32 ;//0x0088\n unsigned int :32 ;//0x008c\n unsigned int :32 ;//0x0090\n unsigned int :32 ;//0x0094\n unsigned int :32 ;//0x0098\n unsigned int :32 ;//0x009c\n unsigned int :32 ;//0x00a0\n unsigned int :32 ;//0x00a4\n unsigned int :32 ;//0x00a8\n unsigned int :32 ;//0x00ac\n unsigned int :32 ;//0x00b0\n unsigned int :32 ;//0x00b4\n unsigned int :32 ;//0x00b8\n unsigned int :32 ;//0x00bc\n unsigned int :32 ;//0x00c0\n unsigned int :32 ;//0x00c4\n unsigned int :32 ;//0x00c8\n unsigned int :32 ;//0x00cc\n unsigned int :32 ;//0x00d0\n unsigned int :32 ;//0x00d4\n unsigned int :32 ;//0x00d8\n unsigned int :32 ;//0x00dc\n unsigned int :32 ;//0x00e0\n unsigned int :32 ;//0x00e4\n unsigned int :32 ;//0x00e8\n unsigned int :32 ;//0x00ec\n unsigned int :32 ;//0x00f0\n unsigned int :32 ;//0x00f4\n unsigned int :32 ;//0x00f8\n union {\n const unsigned long version ;//0x00fc\n const avr32_ssc_version_t VERSION ;\n };\n} avr32_ssc_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n\n#if !defined (DEPRECATED_DISABLE)\n\n#define AVR32_SSC_DETECT_ANY_EGDE_RF 0x00000007\n\n#define AVR32_SSC_RCMR_START_DETECT_ANY_EGDE_RF 0x00000007\n\n#define AVR32_SSC_START_DETECT_ANY_EGDE_RF 0x00000007\n\n#define AVR32_SSC_TCMR_START_DETECT_ANY_EGDE_RF 0x00000007\n#define AVR32_SSC_TCMR_START_DETECT_FALLING_RF 0x00000004\n#define AVR32_SSC_TCMR_START_DETECT_HIGH_RF 0x00000003\n#define AVR32_SSC_TCMR_START_DETECT_LEVEL_CHANGE_RF 0x00000006\n#define AVR32_SSC_TCMR_START_DETECT_LOW_RF 0x00000002\n#define AVR32_SSC_TCMR_START_DETECT_RISING_RF 0x00000005\n\n#endif\n\n\n/*#ifdef AVR32_SSC_310_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/tc_222.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : AP7200\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_TC_222_H_INCLUDED\n#define AVR32_TC_222_H_INCLUDED\n\n#define AVR32_TC_H_VERSION 222\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_TC_\n - Bitfield mask: AVR32_TC__\n - Bitfield offset: AVR32_TC___OFFSET\n - Bitfield size: AVR32_TC___SIZE\n - Bitfield values: AVR32_TC___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_TC_\n - Bitfield offset: AVR32_TC__OFFSET\n - Bitfield size: AVR32_TC__SIZE\n - Bitfield values: AVR32_TC__\n - Bitfield values: AVR32_TC_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_TC_ABETRG 10\n#define AVR32_TC_ABETRG_MASK 0x00000400\n#define AVR32_TC_ABETRG_OFFSET 10\n#define AVR32_TC_ABETRG_SIZE 1\n#define AVR32_TC_ACPA 16\n#define AVR32_TC_ACPA_CLEAR 0x00000002\n#define AVR32_TC_ACPA_MASK 0x00030000\n#define AVR32_TC_ACPA_NONE 0x00000000\n#define AVR32_TC_ACPA_OFFSET 16\n#define AVR32_TC_ACPA_SET 0x00000001\n#define AVR32_TC_ACPA_SIZE 2\n#define AVR32_TC_ACPA_TOGGLE 0x00000003\n#define AVR32_TC_ACPC 18\n#define AVR32_TC_ACPC_CLEAR 0x00000002\n#define AVR32_TC_ACPC_MASK 0x000c0000\n#define AVR32_TC_ACPC_NONE 0x00000000\n#define AVR32_TC_ACPC_OFFSET 18\n#define AVR32_TC_ACPC_SET 0x00000001\n#define AVR32_TC_ACPC_SIZE 2\n#define AVR32_TC_ACPC_TOGGLE 0x00000003\n#define AVR32_TC_AEEVT 20\n#define AVR32_TC_AEEVT_CLEAR 0x00000002\n#define AVR32_TC_AEEVT_MASK 0x00300000\n#define AVR32_TC_AEEVT_NONE 0x00000000\n#define AVR32_TC_AEEVT_OFFSET 20\n#define AVR32_TC_AEEVT_SET 0x00000001\n#define AVR32_TC_AEEVT_SIZE 2\n#define AVR32_TC_AEEVT_TOGGLE 0x00000003\n#define AVR32_TC_ASWTRG 22\n#define AVR32_TC_ASWTRG_CLEAR 0x00000002\n#define AVR32_TC_ASWTRG_MASK 0x00c00000\n#define AVR32_TC_ASWTRG_NONE 0x00000000\n#define AVR32_TC_ASWTRG_OFFSET 22\n#define AVR32_TC_ASWTRG_SET 0x00000001\n#define AVR32_TC_ASWTRG_SIZE 2\n#define AVR32_TC_ASWTRG_TOGGLE 0x00000003\n#define AVR32_TC_BCPB 24\n#define AVR32_TC_BCPB_CLEAR 0x00000002\n#define AVR32_TC_BCPB_MASK 0x03000000\n#define AVR32_TC_BCPB_NONE 0x00000000\n#define AVR32_TC_BCPB_OFFSET 24\n#define AVR32_TC_BCPB_SET 0x00000001\n#define AVR32_TC_BCPB_SIZE 2\n#define AVR32_TC_BCPB_TOGGLE 0x00000003\n#define AVR32_TC_BCPC 26\n#define AVR32_TC_BCPC_CLEAR 0x00000002\n#define AVR32_TC_BCPC_MASK 0x0c000000\n#define AVR32_TC_BCPC_NONE 0x00000000\n#define AVR32_TC_BCPC_OFFSET 26\n#define AVR32_TC_BCPC_SET 0x00000001\n#define AVR32_TC_BCPC_SIZE 2\n#define AVR32_TC_BCPC_TOGGLE 0x00000003\n#define AVR32_TC_BCR 0x000000c0\n#define AVR32_TC_BCR_SYNC 0\n#define AVR32_TC_BCR_SYNC_MASK 0x00000001\n#define AVR32_TC_BCR_SYNC_OFFSET 0\n#define AVR32_TC_BCR_SYNC_SIZE 1\n#define AVR32_TC_BEEVT 28\n#define AVR32_TC_BEEVT_CLEAR 0x00000002\n#define AVR32_TC_BEEVT_MASK 0x30000000\n#define AVR32_TC_BEEVT_NONE 0x00000000\n#define AVR32_TC_BEEVT_OFFSET 28\n#define AVR32_TC_BEEVT_SET 0x00000001\n#define AVR32_TC_BEEVT_SIZE 2\n#define AVR32_TC_BEEVT_TOGGLE 0x00000003\n#define AVR32_TC_BIOTH_EDGES_TIOA 0x00000003\n#define AVR32_TC_BMR 0x000000c4\n#define AVR32_TC_BMR_TC0XC0S 0\n#define AVR32_TC_BMR_TC0XC0S_MASK 0x00000003\n#define AVR32_TC_BMR_TC0XC0S_NO_CLK 0x00000001\n#define AVR32_TC_BMR_TC0XC0S_OFFSET 0\n#define AVR32_TC_BMR_TC0XC0S_SIZE 2\n#define AVR32_TC_BMR_TC0XC0S_TCLK0 0x00000000\n#define AVR32_TC_BMR_TC0XC0S_TIOA1 0x00000002\n#define AVR32_TC_BMR_TC0XC0S_TIOA2 0x00000003\n#define AVR32_TC_BMR_TC1XC1S 2\n#define AVR32_TC_BMR_TC1XC1S_MASK 0x0000000c\n#define AVR32_TC_BMR_TC1XC1S_NO_CLK 0x00000001\n#define AVR32_TC_BMR_TC1XC1S_OFFSET 2\n#define AVR32_TC_BMR_TC1XC1S_SIZE 2\n#define AVR32_TC_BMR_TC1XC1S_TCLK1 0x00000000\n#define AVR32_TC_BMR_TC1XC1S_TIOA0 0x00000002\n#define AVR32_TC_BMR_TC1XC1S_TIOA2 0x00000003\n#define AVR32_TC_BMR_TC2XC2S 4\n#define AVR32_TC_BMR_TC2XC2S_MASK 0x00000030\n#define AVR32_TC_BMR_TC2XC2S_NO_CLK 0x00000001\n#define AVR32_TC_BMR_TC2XC2S_OFFSET 4\n#define AVR32_TC_BMR_TC2XC2S_SIZE 2\n#define AVR32_TC_BMR_TC2XC2S_TCLK2 0x00000000\n#define AVR32_TC_BMR_TC2XC2S_TIOA0 0x00000002\n#define AVR32_TC_BMR_TC2XC2S_TIOA1 0x00000003\n#define AVR32_TC_BOTH_EDGES 0x00000003\n#define AVR32_TC_BSWTRG 30\n#define AVR32_TC_BSWTRG_CLEAR 0x00000002\n#define AVR32_TC_BSWTRG_MASK 0xc0000000\n#define AVR32_TC_BSWTRG_NONE 0x00000000\n#define AVR32_TC_BSWTRG_OFFSET 30\n#define AVR32_TC_BSWTRG_SET 0x00000001\n#define AVR32_TC_BSWTRG_SIZE 2\n#define AVR32_TC_BSWTRG_TOGGLE 0x00000003\n#define AVR32_TC_BURST 4\n#define AVR32_TC_BURST_CLK_AND_XC0 0x00000001\n#define AVR32_TC_BURST_CLK_AND_XC1 0x00000002\n#define AVR32_TC_BURST_CLK_AND_XC2 0x00000003\n#define AVR32_TC_BURST_MASK 0x00000030\n#define AVR32_TC_BURST_NOT_GATED 0x00000000\n#define AVR32_TC_BURST_OFFSET 4\n#define AVR32_TC_BURST_SIZE 2\n#define AVR32_TC_CCR0 0x00000000\n#define AVR32_TC_CCR0_CLKDIS 1\n#define AVR32_TC_CCR0_CLKDIS_MASK 0x00000002\n#define AVR32_TC_CCR0_CLKDIS_OFFSET 1\n#define AVR32_TC_CCR0_CLKDIS_SIZE 1\n#define AVR32_TC_CCR0_CLKEN 0\n#define AVR32_TC_CCR0_CLKEN_MASK 0x00000001\n#define AVR32_TC_CCR0_CLKEN_OFFSET 0\n#define AVR32_TC_CCR0_CLKEN_SIZE 1\n#define AVR32_TC_CCR0_SWTRG 2\n#define AVR32_TC_CCR0_SWTRG_MASK 0x00000004\n#define AVR32_TC_CCR0_SWTRG_OFFSET 2\n#define AVR32_TC_CCR0_SWTRG_SIZE 1\n#define AVR32_TC_CCR1 0x00000040\n#define AVR32_TC_CCR1_CLKDIS 1\n#define AVR32_TC_CCR1_CLKDIS_MASK 0x00000002\n#define AVR32_TC_CCR1_CLKDIS_OFFSET 1\n#define AVR32_TC_CCR1_CLKDIS_SIZE 1\n#define AVR32_TC_CCR1_CLKEN 0\n#define AVR32_TC_CCR1_CLKEN_MASK 0x00000001\n#define AVR32_TC_CCR1_CLKEN_OFFSET 0\n#define AVR32_TC_CCR1_CLKEN_SIZE 1\n#define AVR32_TC_CCR1_SWTRG 2\n#define AVR32_TC_CCR1_SWTRG_MASK 0x00000004\n#define AVR32_TC_CCR1_SWTRG_OFFSET 2\n#define AVR32_TC_CCR1_SWTRG_SIZE 1\n#define AVR32_TC_CCR2 0x00000080\n#define AVR32_TC_CCR2_CLKDIS 1\n#define AVR32_TC_CCR2_CLKDIS_MASK 0x00000002\n#define AVR32_TC_CCR2_CLKDIS_OFFSET 1\n#define AVR32_TC_CCR2_CLKDIS_SIZE 1\n#define AVR32_TC_CCR2_CLKEN 0\n#define AVR32_TC_CCR2_CLKEN_MASK 0x00000001\n#define AVR32_TC_CCR2_CLKEN_OFFSET 0\n#define AVR32_TC_CCR2_CLKEN_SIZE 1\n#define AVR32_TC_CCR2_SWTRG 2\n#define AVR32_TC_CCR2_SWTRG_MASK 0x00000004\n#define AVR32_TC_CCR2_SWTRG_OFFSET 2\n#define AVR32_TC_CCR2_SWTRG_SIZE 1\n#define AVR32_TC_CLEAR 0x00000002\n#define AVR32_TC_CLKDIS 1\n#define AVR32_TC_CLKDIS_MASK 0x00000002\n#define AVR32_TC_CLKDIS_OFFSET 1\n#define AVR32_TC_CLKDIS_SIZE 1\n#define AVR32_TC_CLKEN 0\n#define AVR32_TC_CLKEN_MASK 0x00000001\n#define AVR32_TC_CLKEN_OFFSET 0\n#define AVR32_TC_CLKEN_SIZE 1\n#define AVR32_TC_CLKI 3\n#define AVR32_TC_CLKI_MASK 0x00000008\n#define AVR32_TC_CLKI_OFFSET 3\n#define AVR32_TC_CLKI_SIZE 1\n#define AVR32_TC_CLKSTA 16\n#define AVR32_TC_CLKSTA_MASK 0x00010000\n#define AVR32_TC_CLKSTA_OFFSET 16\n#define AVR32_TC_CLKSTA_SIZE 1\n#define AVR32_TC_CLK_AND_XC0 0x00000001\n#define AVR32_TC_CLK_AND_XC1 0x00000002\n#define AVR32_TC_CLK_AND_XC2 0x00000003\n#define AVR32_TC_CMR0 0x00000004\n#define AVR32_TC_CMR0_ABETRG 10\n#define AVR32_TC_CMR0_ABETRG_MASK 0x00000400\n#define AVR32_TC_CMR0_ABETRG_OFFSET 10\n#define AVR32_TC_CMR0_ABETRG_SIZE 1\n#define AVR32_TC_CMR0_ACPA 16\n#define AVR32_TC_CMR0_ACPA_CLEAR 0x00000002\n#define AVR32_TC_CMR0_ACPA_MASK 0x00030000\n#define AVR32_TC_CMR0_ACPA_NONE 0x00000000\n#define AVR32_TC_CMR0_ACPA_OFFSET 16\n#define AVR32_TC_CMR0_ACPA_SET 0x00000001\n#define AVR32_TC_CMR0_ACPA_SIZE 2\n#define AVR32_TC_CMR0_ACPA_TOGGLE 0x00000003\n#define AVR32_TC_CMR0_ACPC 18\n#define AVR32_TC_CMR0_ACPC_CLEAR 0x00000002\n#define AVR32_TC_CMR0_ACPC_MASK 0x000c0000\n#define AVR32_TC_CMR0_ACPC_NONE 0x00000000\n#define AVR32_TC_CMR0_ACPC_OFFSET 18\n#define AVR32_TC_CMR0_ACPC_SET 0x00000001\n#define AVR32_TC_CMR0_ACPC_SIZE 2\n#define AVR32_TC_CMR0_ACPC_TOGGLE 0x00000003\n#define AVR32_TC_CMR0_AEEVT 20\n#define AVR32_TC_CMR0_AEEVT_CLEAR 0x00000002\n#define AVR32_TC_CMR0_AEEVT_MASK 0x00300000\n#define AVR32_TC_CMR0_AEEVT_NONE 0x00000000\n#define AVR32_TC_CMR0_AEEVT_OFFSET 20\n#define AVR32_TC_CMR0_AEEVT_SET 0x00000001\n#define AVR32_TC_CMR0_AEEVT_SIZE 2\n#define AVR32_TC_CMR0_AEEVT_TOGGLE 0x00000003\n#define AVR32_TC_CMR0_ASWTRG 22\n#define AVR32_TC_CMR0_ASWTRG_CLEAR 0x00000002\n#define AVR32_TC_CMR0_ASWTRG_MASK 0x00c00000\n#define AVR32_TC_CMR0_ASWTRG_NONE 0x00000000\n#define AVR32_TC_CMR0_ASWTRG_OFFSET 22\n#define AVR32_TC_CMR0_ASWTRG_SET 0x00000001\n#define AVR32_TC_CMR0_ASWTRG_SIZE 2\n#define AVR32_TC_CMR0_ASWTRG_TOGGLE 0x00000003\n#define AVR32_TC_CMR0_BCPB 24\n#define AVR32_TC_CMR0_BCPB_CLEAR 0x00000002\n#define AVR32_TC_CMR0_BCPB_MASK 0x03000000\n#define AVR32_TC_CMR0_BCPB_NONE 0x00000000\n#define AVR32_TC_CMR0_BCPB_OFFSET 24\n#define AVR32_TC_CMR0_BCPB_SET 0x00000001\n#define AVR32_TC_CMR0_BCPB_SIZE 2\n#define AVR32_TC_CMR0_BCPB_TOGGLE 0x00000003\n#define AVR32_TC_CMR0_BCPC 26\n#define AVR32_TC_CMR0_BCPC_CLEAR 0x00000002\n#define AVR32_TC_CMR0_BCPC_MASK 0x0c000000\n#define AVR32_TC_CMR0_BCPC_NONE 0x00000000\n#define AVR32_TC_CMR0_BCPC_OFFSET 26\n#define AVR32_TC_CMR0_BCPC_SET 0x00000001\n#define AVR32_TC_CMR0_BCPC_SIZE 2\n#define AVR32_TC_CMR0_BCPC_TOGGLE 0x00000003\n#define AVR32_TC_CMR0_BEEVT 28\n#define AVR32_TC_CMR0_BEEVT_CLEAR 0x00000002\n#define AVR32_TC_CMR0_BEEVT_MASK 0x30000000\n#define AVR32_TC_CMR0_BEEVT_NONE 0x00000000\n#define AVR32_TC_CMR0_BEEVT_OFFSET 28\n#define AVR32_TC_CMR0_BEEVT_SET 0x00000001\n#define AVR32_TC_CMR0_BEEVT_SIZE 2\n#define AVR32_TC_CMR0_BEEVT_TOGGLE 0x00000003\n#define AVR32_TC_CMR0_BSWTRG 30\n#define AVR32_TC_CMR0_BSWTRG_CLEAR 0x00000002\n#define AVR32_TC_CMR0_BSWTRG_MASK 0xc0000000\n#define AVR32_TC_CMR0_BSWTRG_NONE 0x00000000\n#define AVR32_TC_CMR0_BSWTRG_OFFSET 30\n#define AVR32_TC_CMR0_BSWTRG_SET 0x00000001\n#define AVR32_TC_CMR0_BSWTRG_SIZE 2\n#define AVR32_TC_CMR0_BSWTRG_TOGGLE 0x00000003\n#define AVR32_TC_CMR0_BURST 4\n#define AVR32_TC_CMR0_BURST_CLK_AND_XC0 0x00000001\n#define AVR32_TC_CMR0_BURST_CLK_AND_XC1 0x00000002\n#define AVR32_TC_CMR0_BURST_CLK_AND_XC2 0x00000003\n#define AVR32_TC_CMR0_BURST_MASK 0x00000030\n#define AVR32_TC_CMR0_BURST_NOT_GATED 0x00000000\n#define AVR32_TC_CMR0_BURST_OFFSET 4\n#define AVR32_TC_CMR0_BURST_SIZE 2\n#define AVR32_TC_CMR0_CLKI 3\n#define AVR32_TC_CMR0_CLKI_MASK 0x00000008\n#define AVR32_TC_CMR0_CLKI_OFFSET 3\n#define AVR32_TC_CMR0_CLKI_SIZE 1\n#define AVR32_TC_CMR0_CPCDIS 7\n#define AVR32_TC_CMR0_CPCDIS_MASK 0x00000080\n#define AVR32_TC_CMR0_CPCDIS_OFFSET 7\n#define AVR32_TC_CMR0_CPCDIS_SIZE 1\n#define AVR32_TC_CMR0_CPCSTOP 6\n#define AVR32_TC_CMR0_CPCSTOP_MASK 0x00000040\n#define AVR32_TC_CMR0_CPCSTOP_OFFSET 6\n#define AVR32_TC_CMR0_CPCSTOP_SIZE 1\n#define AVR32_TC_CMR0_CPCTRG 14\n#define AVR32_TC_CMR0_CPCTRG_MASK 0x00004000\n#define AVR32_TC_CMR0_CPCTRG_OFFSET 14\n#define AVR32_TC_CMR0_CPCTRG_SIZE 1\n#define AVR32_TC_CMR0_EEVT 10\n#define AVR32_TC_CMR0_EEVTEDG 8\n#define AVR32_TC_CMR0_EEVTEDG_BOTH_EDGES 0x00000003\n#define AVR32_TC_CMR0_EEVTEDG_MASK 0x00000300\n#define AVR32_TC_CMR0_EEVTEDG_NEG_EDGE 0x00000002\n#define AVR32_TC_CMR0_EEVTEDG_NO_EDGE 0x00000000\n#define AVR32_TC_CMR0_EEVTEDG_OFFSET 8\n#define AVR32_TC_CMR0_EEVTEDG_POS_EDGE 0x00000001\n#define AVR32_TC_CMR0_EEVTEDG_SIZE 2\n#define AVR32_TC_CMR0_EEVT_MASK 0x00000c00\n#define AVR32_TC_CMR0_EEVT_OFFSET 10\n#define AVR32_TC_CMR0_EEVT_SIZE 2\n#define AVR32_TC_CMR0_EEVT_TIOB_INPUT 0x00000000\n#define AVR32_TC_CMR0_EEVT_XC0_OUTPUT 0x00000001\n#define AVR32_TC_CMR0_EEVT_XC1_OUTPUT 0x00000002\n#define AVR32_TC_CMR0_EEVT_XC2_OUTPUT 0x00000003\n#define AVR32_TC_CMR0_ENETRG 12\n#define AVR32_TC_CMR0_ENETRG_MASK 0x00001000\n#define AVR32_TC_CMR0_ENETRG_OFFSET 12\n#define AVR32_TC_CMR0_ENETRG_SIZE 1\n#define AVR32_TC_CMR0_ETRGEDG 8\n#define AVR32_TC_CMR0_ETRGEDG_BOTH_EDGES 0x00000003\n#define AVR32_TC_CMR0_ETRGEDG_MASK 0x00000300\n#define AVR32_TC_CMR0_ETRGEDG_NEG_EDGE 0x00000002\n#define AVR32_TC_CMR0_ETRGEDG_NO_EDGE 0x00000000\n#define AVR32_TC_CMR0_ETRGEDG_OFFSET 8\n#define AVR32_TC_CMR0_ETRGEDG_POS_EDGE 0x00000001\n#define AVR32_TC_CMR0_ETRGEDG_SIZE 2\n#define AVR32_TC_CMR0_LDBDIS 7\n#define AVR32_TC_CMR0_LDBDIS_MASK 0x00000080\n#define AVR32_TC_CMR0_LDBDIS_OFFSET 7\n#define AVR32_TC_CMR0_LDBDIS_SIZE 1\n#define AVR32_TC_CMR0_LDBSTOP 6\n#define AVR32_TC_CMR0_LDBSTOP_MASK 0x00000040\n#define AVR32_TC_CMR0_LDBSTOP_OFFSET 6\n#define AVR32_TC_CMR0_LDBSTOP_SIZE 1\n#define AVR32_TC_CMR0_LDRA 16\n#define AVR32_TC_CMR0_LDRA_BIOTH_EDGES_TIOA 0x00000003\n#define AVR32_TC_CMR0_LDRA_MASK 0x00030000\n#define AVR32_TC_CMR0_LDRA_NEG_EDGE_TIOA 0x00000002\n#define AVR32_TC_CMR0_LDRA_NO_EDGE 0x00000000\n#define AVR32_TC_CMR0_LDRA_OFFSET 16\n#define AVR32_TC_CMR0_LDRA_POS_EDGE_TIOA 0x00000001\n#define AVR32_TC_CMR0_LDRA_SIZE 2\n#define AVR32_TC_CMR0_LDRB 18\n#define AVR32_TC_CMR0_LDRB_BIOTH_EDGES_TIOA 0x00000003\n#define AVR32_TC_CMR0_LDRB_MASK 0x000c0000\n#define AVR32_TC_CMR0_LDRB_NEG_EDGE_TIOA 0x00000002\n#define AVR32_TC_CMR0_LDRB_NO_EDGE 0x00000000\n#define AVR32_TC_CMR0_LDRB_OFFSET 18\n#define AVR32_TC_CMR0_LDRB_POS_EDGE_TIOA 0x00000001\n#define AVR32_TC_CMR0_LDRB_SIZE 2\n#define AVR32_TC_CMR0_TCCLKS 0\n#define AVR32_TC_CMR0_TCCLKS_MASK 0x00000007\n#define AVR32_TC_CMR0_TCCLKS_OFFSET 0\n#define AVR32_TC_CMR0_TCCLKS_SIZE 3\n#define AVR32_TC_CMR0_TCCLKS_TIMER_CLOCK1 0x00000000\n#define AVR32_TC_CMR0_TCCLKS_TIMER_CLOCK2 0x00000001\n#define AVR32_TC_CMR0_TCCLKS_TIMER_CLOCK3 0x00000002\n#define AVR32_TC_CMR0_TCCLKS_TIMER_CLOCK4 0x00000003\n#define AVR32_TC_CMR0_TCCLKS_TIMER_CLOCK5 0x00000004\n#define AVR32_TC_CMR0_TCCLKS_XC0 0x00000005\n#define AVR32_TC_CMR0_TCCLKS_XC1 0x00000006\n#define AVR32_TC_CMR0_TCCLKS_XC2 0x00000007\n#define AVR32_TC_CMR0_WAVE 15\n#define AVR32_TC_CMR0_WAVE_MASK 0x00008000\n#define AVR32_TC_CMR0_WAVE_OFFSET 15\n#define AVR32_TC_CMR0_WAVE_SIZE 1\n#define AVR32_TC_CMR0_WAVSEL 13\n#define AVR32_TC_CMR0_WAVSEL_MASK 0x00006000\n#define AVR32_TC_CMR0_WAVSEL_OFFSET 13\n#define AVR32_TC_CMR0_WAVSEL_SIZE 2\n#define AVR32_TC_CMR0_WAVSEL_UPDOWN_AUTO 0x00000003\n#define AVR32_TC_CMR0_WAVSEL_UPDOWN_NO_AUTO 0x00000001\n#define AVR32_TC_CMR0_WAVSEL_UP_AUTO 0x00000002\n#define AVR32_TC_CMR0_WAVSEL_UP_NO_AUTO 0x00000000\n#define AVR32_TC_CMR1 0x00000044\n#define AVR32_TC_CMR1_ABETRG 10\n#define AVR32_TC_CMR1_ABETRG_MASK 0x00000400\n#define AVR32_TC_CMR1_ABETRG_OFFSET 10\n#define AVR32_TC_CMR1_ABETRG_SIZE 1\n#define AVR32_TC_CMR1_ACPA 16\n#define AVR32_TC_CMR1_ACPA_CLEAR 0x00000002\n#define AVR32_TC_CMR1_ACPA_MASK 0x00030000\n#define AVR32_TC_CMR1_ACPA_NONE 0x00000000\n#define AVR32_TC_CMR1_ACPA_OFFSET 16\n#define AVR32_TC_CMR1_ACPA_SET 0x00000001\n#define AVR32_TC_CMR1_ACPA_SIZE 2\n#define AVR32_TC_CMR1_ACPA_TOGGLE 0x00000003\n#define AVR32_TC_CMR1_ACPC 18\n#define AVR32_TC_CMR1_ACPC_CLEAR 0x00000002\n#define AVR32_TC_CMR1_ACPC_MASK 0x000c0000\n#define AVR32_TC_CMR1_ACPC_NONE 0x00000000\n#define AVR32_TC_CMR1_ACPC_OFFSET 18\n#define AVR32_TC_CMR1_ACPC_SET 0x00000001\n#define AVR32_TC_CMR1_ACPC_SIZE 2\n#define AVR32_TC_CMR1_ACPC_TOGGLE 0x00000003\n#define AVR32_TC_CMR1_AEEVT 20\n#define AVR32_TC_CMR1_AEEVT_CLEAR 0x00000002\n#define AVR32_TC_CMR1_AEEVT_MASK 0x00300000\n#define AVR32_TC_CMR1_AEEVT_NONE 0x00000000\n#define AVR32_TC_CMR1_AEEVT_OFFSET 20\n#define AVR32_TC_CMR1_AEEVT_SET 0x00000001\n#define AVR32_TC_CMR1_AEEVT_SIZE 2\n#define AVR32_TC_CMR1_AEEVT_TOGGLE 0x00000003\n#define AVR32_TC_CMR1_ASWTRG 22\n#define AVR32_TC_CMR1_ASWTRG_CLEAR 0x00000002\n#define AVR32_TC_CMR1_ASWTRG_MASK 0x00c00000\n#define AVR32_TC_CMR1_ASWTRG_NONE 0x00000000\n#define AVR32_TC_CMR1_ASWTRG_OFFSET 22\n#define AVR32_TC_CMR1_ASWTRG_SET 0x00000001\n#define AVR32_TC_CMR1_ASWTRG_SIZE 2\n#define AVR32_TC_CMR1_ASWTRG_TOGGLE 0x00000003\n#define AVR32_TC_CMR1_BCPB 24\n#define AVR32_TC_CMR1_BCPB_CLEAR 0x00000002\n#define AVR32_TC_CMR1_BCPB_MASK 0x03000000\n#define AVR32_TC_CMR1_BCPB_NONE 0x00000000\n#define AVR32_TC_CMR1_BCPB_OFFSET 24\n#define AVR32_TC_CMR1_BCPB_SET 0x00000001\n#define AVR32_TC_CMR1_BCPB_SIZE 2\n#define AVR32_TC_CMR1_BCPB_TOGGLE 0x00000003\n#define AVR32_TC_CMR1_BCPC 26\n#define AVR32_TC_CMR1_BCPC_CLEAR 0x00000002\n#define AVR32_TC_CMR1_BCPC_MASK 0x0c000000\n#define AVR32_TC_CMR1_BCPC_NONE 0x00000000\n#define AVR32_TC_CMR1_BCPC_OFFSET 26\n#define AVR32_TC_CMR1_BCPC_SET 0x00000001\n#define AVR32_TC_CMR1_BCPC_SIZE 2\n#define AVR32_TC_CMR1_BCPC_TOGGLE 0x00000003\n#define AVR32_TC_CMR1_BEEVT 28\n#define AVR32_TC_CMR1_BEEVT_CLEAR 0x00000002\n#define AVR32_TC_CMR1_BEEVT_MASK 0x30000000\n#define AVR32_TC_CMR1_BEEVT_NONE 0x00000000\n#define AVR32_TC_CMR1_BEEVT_OFFSET 28\n#define AVR32_TC_CMR1_BEEVT_SET 0x00000001\n#define AVR32_TC_CMR1_BEEVT_SIZE 2\n#define AVR32_TC_CMR1_BEEVT_TOGGLE 0x00000003\n#define AVR32_TC_CMR1_BSWTRG 30\n#define AVR32_TC_CMR1_BSWTRG_CLEAR 0x00000002\n#define AVR32_TC_CMR1_BSWTRG_MASK 0xc0000000\n#define AVR32_TC_CMR1_BSWTRG_NONE 0x00000000\n#define AVR32_TC_CMR1_BSWTRG_OFFSET 30\n#define AVR32_TC_CMR1_BSWTRG_SET 0x00000001\n#define AVR32_TC_CMR1_BSWTRG_SIZE 2\n#define AVR32_TC_CMR1_BSWTRG_TOGGLE 0x00000003\n#define AVR32_TC_CMR1_BURST 4\n#define AVR32_TC_CMR1_BURST_CLK_AND_XC0 0x00000001\n#define AVR32_TC_CMR1_BURST_CLK_AND_XC1 0x00000002\n#define AVR32_TC_CMR1_BURST_CLK_AND_XC2 0x00000003\n#define AVR32_TC_CMR1_BURST_MASK 0x00000030\n#define AVR32_TC_CMR1_BURST_NOT_GATED 0x00000000\n#define AVR32_TC_CMR1_BURST_OFFSET 4\n#define AVR32_TC_CMR1_BURST_SIZE 2\n#define AVR32_TC_CMR1_CLKI 3\n#define AVR32_TC_CMR1_CLKI_MASK 0x00000008\n#define AVR32_TC_CMR1_CLKI_OFFSET 3\n#define AVR32_TC_CMR1_CLKI_SIZE 1\n#define AVR32_TC_CMR1_CPCDIS 7\n#define AVR32_TC_CMR1_CPCDIS_MASK 0x00000080\n#define AVR32_TC_CMR1_CPCDIS_OFFSET 7\n#define AVR32_TC_CMR1_CPCDIS_SIZE 1\n#define AVR32_TC_CMR1_CPCSTOP 6\n#define AVR32_TC_CMR1_CPCSTOP_MASK 0x00000040\n#define AVR32_TC_CMR1_CPCSTOP_OFFSET 6\n#define AVR32_TC_CMR1_CPCSTOP_SIZE 1\n#define AVR32_TC_CMR1_CPCTRG 14\n#define AVR32_TC_CMR1_CPCTRG_MASK 0x00004000\n#define AVR32_TC_CMR1_CPCTRG_OFFSET 14\n#define AVR32_TC_CMR1_CPCTRG_SIZE 1\n#define AVR32_TC_CMR1_EEVT 10\n#define AVR32_TC_CMR1_EEVTEDG 8\n#define AVR32_TC_CMR1_EEVTEDG_BOTH_EDGES 0x00000003\n#define AVR32_TC_CMR1_EEVTEDG_MASK 0x00000300\n#define AVR32_TC_CMR1_EEVTEDG_NEG_EDGE 0x00000002\n#define AVR32_TC_CMR1_EEVTEDG_NO_EDGE 0x00000000\n#define AVR32_TC_CMR1_EEVTEDG_OFFSET 8\n#define AVR32_TC_CMR1_EEVTEDG_POS_EDGE 0x00000001\n#define AVR32_TC_CMR1_EEVTEDG_SIZE 2\n#define AVR32_TC_CMR1_EEVT_MASK 0x00000c00\n#define AVR32_TC_CMR1_EEVT_OFFSET 10\n#define AVR32_TC_CMR1_EEVT_SIZE 2\n#define AVR32_TC_CMR1_EEVT_TIOB_INPUT 0x00000000\n#define AVR32_TC_CMR1_EEVT_XC0_OUTPUT 0x00000001\n#define AVR32_TC_CMR1_EEVT_XC1_OUTPUT 0x00000002\n#define AVR32_TC_CMR1_EEVT_XC2_OUTPUT 0x00000003\n#define AVR32_TC_CMR1_ENETRG 12\n#define AVR32_TC_CMR1_ENETRG_MASK 0x00001000\n#define AVR32_TC_CMR1_ENETRG_OFFSET 12\n#define AVR32_TC_CMR1_ENETRG_SIZE 1\n#define AVR32_TC_CMR1_ETRGEDG 8\n#define AVR32_TC_CMR1_ETRGEDG_BOTH_EDGES 0x00000003\n#define AVR32_TC_CMR1_ETRGEDG_MASK 0x00000300\n#define AVR32_TC_CMR1_ETRGEDG_NEG_EDGE 0x00000002\n#define AVR32_TC_CMR1_ETRGEDG_NO_EDGE 0x00000000\n#define AVR32_TC_CMR1_ETRGEDG_OFFSET 8\n#define AVR32_TC_CMR1_ETRGEDG_POS_EDGE 0x00000001\n#define AVR32_TC_CMR1_ETRGEDG_SIZE 2\n#define AVR32_TC_CMR1_LDBDIS 7\n#define AVR32_TC_CMR1_LDBDIS_MASK 0x00000080\n#define AVR32_TC_CMR1_LDBDIS_OFFSET 7\n#define AVR32_TC_CMR1_LDBDIS_SIZE 1\n#define AVR32_TC_CMR1_LDBSTOP 6\n#define AVR32_TC_CMR1_LDBSTOP_MASK 0x00000040\n#define AVR32_TC_CMR1_LDBSTOP_OFFSET 6\n#define AVR32_TC_CMR1_LDBSTOP_SIZE 1\n#define AVR32_TC_CMR1_LDRA 16\n#define AVR32_TC_CMR1_LDRA_BIOTH_EDGES_TIOA 0x00000003\n#define AVR32_TC_CMR1_LDRA_MASK 0x00030000\n#define AVR32_TC_CMR1_LDRA_NEG_EDGE_TIOA 0x00000002\n#define AVR32_TC_CMR1_LDRA_NO_EDGE 0x00000000\n#define AVR32_TC_CMR1_LDRA_OFFSET 16\n#define AVR32_TC_CMR1_LDRA_POS_EDGE_TIOA 0x00000001\n#define AVR32_TC_CMR1_LDRA_SIZE 2\n#define AVR32_TC_CMR1_LDRB 18\n#define AVR32_TC_CMR1_LDRB_BIOTH_EDGES_TIOA 0x00000003\n#define AVR32_TC_CMR1_LDRB_MASK 0x000c0000\n#define AVR32_TC_CMR1_LDRB_NEG_EDGE_TIOA 0x00000002\n#define AVR32_TC_CMR1_LDRB_NO_EDGE 0x00000000\n#define AVR32_TC_CMR1_LDRB_OFFSET 18\n#define AVR32_TC_CMR1_LDRB_POS_EDGE_TIOA 0x00000001\n#define AVR32_TC_CMR1_LDRB_SIZE 2\n#define AVR32_TC_CMR1_TCCLKS 0\n#define AVR32_TC_CMR1_TCCLKS_MASK 0x00000007\n#define AVR32_TC_CMR1_TCCLKS_OFFSET 0\n#define AVR32_TC_CMR1_TCCLKS_SIZE 3\n#define AVR32_TC_CMR1_TCCLKS_TIMER_CLOCK1 0x00000000\n#define AVR32_TC_CMR1_TCCLKS_TIMER_CLOCK2 0x00000001\n#define AVR32_TC_CMR1_TCCLKS_TIMER_CLOCK3 0x00000002\n#define AVR32_TC_CMR1_TCCLKS_TIMER_CLOCK4 0x00000003\n#define AVR32_TC_CMR1_TCCLKS_TIMER_CLOCK5 0x00000004\n#define AVR32_TC_CMR1_TCCLKS_XC0 0x00000005\n#define AVR32_TC_CMR1_TCCLKS_XC1 0x00000006\n#define AVR32_TC_CMR1_TCCLKS_XC2 0x00000007\n#define AVR32_TC_CMR1_WAVE 15\n#define AVR32_TC_CMR1_WAVE_MASK 0x00008000\n#define AVR32_TC_CMR1_WAVE_OFFSET 15\n#define AVR32_TC_CMR1_WAVE_SIZE 1\n#define AVR32_TC_CMR1_WAVSEL 13\n#define AVR32_TC_CMR1_WAVSEL_MASK 0x00006000\n#define AVR32_TC_CMR1_WAVSEL_OFFSET 13\n#define AVR32_TC_CMR1_WAVSEL_SIZE 2\n#define AVR32_TC_CMR1_WAVSEL_UPDOWN_AUTO 0x00000003\n#define AVR32_TC_CMR1_WAVSEL_UPDOWN_NO_AUTO 0x00000001\n#define AVR32_TC_CMR1_WAVSEL_UP_AUTO 0x00000002\n#define AVR32_TC_CMR1_WAVSEL_UP_NO_AUTO 0x00000000\n#define AVR32_TC_CMR2 0x00000084\n#define AVR32_TC_CMR2_ABETRG 10\n#define AVR32_TC_CMR2_ABETRG_MASK 0x00000400\n#define AVR32_TC_CMR2_ABETRG_OFFSET 10\n#define AVR32_TC_CMR2_ABETRG_SIZE 1\n#define AVR32_TC_CMR2_ACPA 16\n#define AVR32_TC_CMR2_ACPA_CLEAR 0x00000002\n#define AVR32_TC_CMR2_ACPA_MASK 0x00030000\n#define AVR32_TC_CMR2_ACPA_NONE 0x00000000\n#define AVR32_TC_CMR2_ACPA_OFFSET 16\n#define AVR32_TC_CMR2_ACPA_SET 0x00000001\n#define AVR32_TC_CMR2_ACPA_SIZE 2\n#define AVR32_TC_CMR2_ACPA_TOGGLE 0x00000003\n#define AVR32_TC_CMR2_ACPC 18\n#define AVR32_TC_CMR2_ACPC_CLEAR 0x00000002\n#define AVR32_TC_CMR2_ACPC_MASK 0x000c0000\n#define AVR32_TC_CMR2_ACPC_NONE 0x00000000\n#define AVR32_TC_CMR2_ACPC_OFFSET 18\n#define AVR32_TC_CMR2_ACPC_SET 0x00000001\n#define AVR32_TC_CMR2_ACPC_SIZE 2\n#define AVR32_TC_CMR2_ACPC_TOGGLE 0x00000003\n#define AVR32_TC_CMR2_AEEVT 20\n#define AVR32_TC_CMR2_AEEVT_CLEAR 0x00000002\n#define AVR32_TC_CMR2_AEEVT_MASK 0x00300000\n#define AVR32_TC_CMR2_AEEVT_NONE 0x00000000\n#define AVR32_TC_CMR2_AEEVT_OFFSET 20\n#define AVR32_TC_CMR2_AEEVT_SET 0x00000001\n#define AVR32_TC_CMR2_AEEVT_SIZE 2\n#define AVR32_TC_CMR2_AEEVT_TOGGLE 0x00000003\n#define AVR32_TC_CMR2_ASWTRG 22\n#define AVR32_TC_CMR2_ASWTRG_CLEAR 0x00000002\n#define AVR32_TC_CMR2_ASWTRG_MASK 0x00c00000\n#define AVR32_TC_CMR2_ASWTRG_NONE 0x00000000\n#define AVR32_TC_CMR2_ASWTRG_OFFSET 22\n#define AVR32_TC_CMR2_ASWTRG_SET 0x00000001\n#define AVR32_TC_CMR2_ASWTRG_SIZE 2\n#define AVR32_TC_CMR2_ASWTRG_TOGGLE 0x00000003\n#define AVR32_TC_CMR2_BCPB 24\n#define AVR32_TC_CMR2_BCPB_CLEAR 0x00000002\n#define AVR32_TC_CMR2_BCPB_MASK 0x03000000\n#define AVR32_TC_CMR2_BCPB_NONE 0x00000000\n#define AVR32_TC_CMR2_BCPB_OFFSET 24\n#define AVR32_TC_CMR2_BCPB_SET 0x00000001\n#define AVR32_TC_CMR2_BCPB_SIZE 2\n#define AVR32_TC_CMR2_BCPB_TOGGLE 0x00000003\n#define AVR32_TC_CMR2_BCPC 26\n#define AVR32_TC_CMR2_BCPC_CLEAR 0x00000002\n#define AVR32_TC_CMR2_BCPC_MASK 0x0c000000\n#define AVR32_TC_CMR2_BCPC_NONE 0x00000000\n#define AVR32_TC_CMR2_BCPC_OFFSET 26\n#define AVR32_TC_CMR2_BCPC_SET 0x00000001\n#define AVR32_TC_CMR2_BCPC_SIZE 2\n#define AVR32_TC_CMR2_BCPC_TOGGLE 0x00000003\n#define AVR32_TC_CMR2_BEEVT 28\n#define AVR32_TC_CMR2_BEEVT_CLEAR 0x00000002\n#define AVR32_TC_CMR2_BEEVT_MASK 0x30000000\n#define AVR32_TC_CMR2_BEEVT_NONE 0x00000000\n#define AVR32_TC_CMR2_BEEVT_OFFSET 28\n#define AVR32_TC_CMR2_BEEVT_SET 0x00000001\n#define AVR32_TC_CMR2_BEEVT_SIZE 2\n#define AVR32_TC_CMR2_BEEVT_TOGGLE 0x00000003\n#define AVR32_TC_CMR2_BSWTRG 30\n#define AVR32_TC_CMR2_BSWTRG_CLEAR 0x00000002\n#define AVR32_TC_CMR2_BSWTRG_MASK 0xc0000000\n#define AVR32_TC_CMR2_BSWTRG_NONE 0x00000000\n#define AVR32_TC_CMR2_BSWTRG_OFFSET 30\n#define AVR32_TC_CMR2_BSWTRG_SET 0x00000001\n#define AVR32_TC_CMR2_BSWTRG_SIZE 2\n#define AVR32_TC_CMR2_BSWTRG_TOGGLE 0x00000003\n#define AVR32_TC_CMR2_BURST 4\n#define AVR32_TC_CMR2_BURST_CLK_AND_XC0 0x00000001\n#define AVR32_TC_CMR2_BURST_CLK_AND_XC1 0x00000002\n#define AVR32_TC_CMR2_BURST_CLK_AND_XC2 0x00000003\n#define AVR32_TC_CMR2_BURST_MASK 0x00000030\n#define AVR32_TC_CMR2_BURST_NOT_GATED 0x00000000\n#define AVR32_TC_CMR2_BURST_OFFSET 4\n#define AVR32_TC_CMR2_BURST_SIZE 2\n#define AVR32_TC_CMR2_CLKI 3\n#define AVR32_TC_CMR2_CLKI_MASK 0x00000008\n#define AVR32_TC_CMR2_CLKI_OFFSET 3\n#define AVR32_TC_CMR2_CLKI_SIZE 1\n#define AVR32_TC_CMR2_CPCDIS 7\n#define AVR32_TC_CMR2_CPCDIS_MASK 0x00000080\n#define AVR32_TC_CMR2_CPCDIS_OFFSET 7\n#define AVR32_TC_CMR2_CPCDIS_SIZE 1\n#define AVR32_TC_CMR2_CPCSTOP 6\n#define AVR32_TC_CMR2_CPCSTOP_MASK 0x00000040\n#define AVR32_TC_CMR2_CPCSTOP_OFFSET 6\n#define AVR32_TC_CMR2_CPCSTOP_SIZE 1\n#define AVR32_TC_CMR2_CPCTRG 14\n#define AVR32_TC_CMR2_CPCTRG_MASK 0x00004000\n#define AVR32_TC_CMR2_CPCTRG_OFFSET 14\n#define AVR32_TC_CMR2_CPCTRG_SIZE 1\n#define AVR32_TC_CMR2_EEVT 10\n#define AVR32_TC_CMR2_EEVTEDG 8\n#define AVR32_TC_CMR2_EEVTEDG_BOTH_EDGES 0x00000003\n#define AVR32_TC_CMR2_EEVTEDG_MASK 0x00000300\n#define AVR32_TC_CMR2_EEVTEDG_NEG_EDGE 0x00000002\n#define AVR32_TC_CMR2_EEVTEDG_NO_EDGE 0x00000000\n#define AVR32_TC_CMR2_EEVTEDG_OFFSET 8\n#define AVR32_TC_CMR2_EEVTEDG_POS_EDGE 0x00000001\n#define AVR32_TC_CMR2_EEVTEDG_SIZE 2\n#define AVR32_TC_CMR2_EEVT_MASK 0x00000c00\n#define AVR32_TC_CMR2_EEVT_OFFSET 10\n#define AVR32_TC_CMR2_EEVT_SIZE 2\n#define AVR32_TC_CMR2_EEVT_TIOB_INPUT 0x00000000\n#define AVR32_TC_CMR2_EEVT_XC0_OUTPUT 0x00000001\n#define AVR32_TC_CMR2_EEVT_XC1_OUTPUT 0x00000002\n#define AVR32_TC_CMR2_EEVT_XC2_OUTPUT 0x00000003\n#define AVR32_TC_CMR2_ENETRG 12\n#define AVR32_TC_CMR2_ENETRG_MASK 0x00001000\n#define AVR32_TC_CMR2_ENETRG_OFFSET 12\n#define AVR32_TC_CMR2_ENETRG_SIZE 1\n#define AVR32_TC_CMR2_ETRGEDG 8\n#define AVR32_TC_CMR2_ETRGEDG_BOTH_EDGES 0x00000003\n#define AVR32_TC_CMR2_ETRGEDG_MASK 0x00000300\n#define AVR32_TC_CMR2_ETRGEDG_NEG_EDGE 0x00000002\n#define AVR32_TC_CMR2_ETRGEDG_NO_EDGE 0x00000000\n#define AVR32_TC_CMR2_ETRGEDG_OFFSET 8\n#define AVR32_TC_CMR2_ETRGEDG_POS_EDGE 0x00000001\n#define AVR32_TC_CMR2_ETRGEDG_SIZE 2\n#define AVR32_TC_CMR2_LDBDIS 7\n#define AVR32_TC_CMR2_LDBDIS_MASK 0x00000080\n#define AVR32_TC_CMR2_LDBDIS_OFFSET 7\n#define AVR32_TC_CMR2_LDBDIS_SIZE 1\n#define AVR32_TC_CMR2_LDBSTOP 6\n#define AVR32_TC_CMR2_LDBSTOP_MASK 0x00000040\n#define AVR32_TC_CMR2_LDBSTOP_OFFSET 6\n#define AVR32_TC_CMR2_LDBSTOP_SIZE 1\n#define AVR32_TC_CMR2_LDRA 16\n#define AVR32_TC_CMR2_LDRA_BIOTH_EDGES_TIOA 0x00000003\n#define AVR32_TC_CMR2_LDRA_MASK 0x00030000\n#define AVR32_TC_CMR2_LDRA_NEG_EDGE_TIOA 0x00000002\n#define AVR32_TC_CMR2_LDRA_NO_EDGE 0x00000000\n#define AVR32_TC_CMR2_LDRA_OFFSET 16\n#define AVR32_TC_CMR2_LDRA_POS_EDGE_TIOA 0x00000001\n#define AVR32_TC_CMR2_LDRA_SIZE 2\n#define AVR32_TC_CMR2_LDRB 18\n#define AVR32_TC_CMR2_LDRB_BIOTH_EDGES_TIOA 0x00000003\n#define AVR32_TC_CMR2_LDRB_MASK 0x000c0000\n#define AVR32_TC_CMR2_LDRB_NEG_EDGE_TIOA 0x00000002\n#define AVR32_TC_CMR2_LDRB_NO_EDGE 0x00000000\n#define AVR32_TC_CMR2_LDRB_OFFSET 18\n#define AVR32_TC_CMR2_LDRB_POS_EDGE_TIOA 0x00000001\n#define AVR32_TC_CMR2_LDRB_SIZE 2\n#define AVR32_TC_CMR2_TCCLKS 0\n#define AVR32_TC_CMR2_TCCLKS_MASK 0x00000007\n#define AVR32_TC_CMR2_TCCLKS_OFFSET 0\n#define AVR32_TC_CMR2_TCCLKS_SIZE 3\n#define AVR32_TC_CMR2_TCCLKS_TIMER_CLOCK1 0x00000000\n#define AVR32_TC_CMR2_TCCLKS_TIMER_CLOCK2 0x00000001\n#define AVR32_TC_CMR2_TCCLKS_TIMER_CLOCK3 0x00000002\n#define AVR32_TC_CMR2_TCCLKS_TIMER_CLOCK4 0x00000003\n#define AVR32_TC_CMR2_TCCLKS_TIMER_CLOCK5 0x00000004\n#define AVR32_TC_CMR2_TCCLKS_XC0 0x00000005\n#define AVR32_TC_CMR2_TCCLKS_XC1 0x00000006\n#define AVR32_TC_CMR2_TCCLKS_XC2 0x00000007\n#define AVR32_TC_CMR2_WAVE 15\n#define AVR32_TC_CMR2_WAVE_MASK 0x00008000\n#define AVR32_TC_CMR2_WAVE_OFFSET 15\n#define AVR32_TC_CMR2_WAVE_SIZE 1\n#define AVR32_TC_CMR2_WAVSEL 13\n#define AVR32_TC_CMR2_WAVSEL_MASK 0x00006000\n#define AVR32_TC_CMR2_WAVSEL_OFFSET 13\n#define AVR32_TC_CMR2_WAVSEL_SIZE 2\n#define AVR32_TC_CMR2_WAVSEL_UPDOWN_AUTO 0x00000003\n#define AVR32_TC_CMR2_WAVSEL_UPDOWN_NO_AUTO 0x00000001\n#define AVR32_TC_CMR2_WAVSEL_UP_AUTO 0x00000002\n#define AVR32_TC_CMR2_WAVSEL_UP_NO_AUTO 0x00000000\n#define AVR32_TC_COVFS 0\n#define AVR32_TC_COVFS_MASK 0x00000001\n#define AVR32_TC_COVFS_OFFSET 0\n#define AVR32_TC_COVFS_SIZE 1\n#define AVR32_TC_CPAS 2\n#define AVR32_TC_CPAS_MASK 0x00000004\n#define AVR32_TC_CPAS_OFFSET 2\n#define AVR32_TC_CPAS_SIZE 1\n#define AVR32_TC_CPBS 3\n#define AVR32_TC_CPBS_MASK 0x00000008\n#define AVR32_TC_CPBS_OFFSET 3\n#define AVR32_TC_CPBS_SIZE 1\n#define AVR32_TC_CPCDIS 7\n#define AVR32_TC_CPCDIS_MASK 0x00000080\n#define AVR32_TC_CPCDIS_OFFSET 7\n#define AVR32_TC_CPCDIS_SIZE 1\n#define AVR32_TC_CPCS 4\n#define AVR32_TC_CPCSTOP 6\n#define AVR32_TC_CPCSTOP_MASK 0x00000040\n#define AVR32_TC_CPCSTOP_OFFSET 6\n#define AVR32_TC_CPCSTOP_SIZE 1\n#define AVR32_TC_CPCS_MASK 0x00000010\n#define AVR32_TC_CPCS_OFFSET 4\n#define AVR32_TC_CPCS_SIZE 1\n#define AVR32_TC_CPCTRG 14\n#define AVR32_TC_CPCTRG_MASK 0x00004000\n#define AVR32_TC_CPCTRG_OFFSET 14\n#define AVR32_TC_CPCTRG_SIZE 1\n#define AVR32_TC_CV 0\n#define AVR32_TC_CV0 0x00000010\n#define AVR32_TC_CV0_CV 0\n#define AVR32_TC_CV0_CV_MASK 0x0000ffff\n#define AVR32_TC_CV0_CV_OFFSET 0\n#define AVR32_TC_CV0_CV_SIZE 16\n#define AVR32_TC_CV1 0x00000050\n#define AVR32_TC_CV1_CV 0\n#define AVR32_TC_CV1_CV_MASK 0x0000ffff\n#define AVR32_TC_CV1_CV_OFFSET 0\n#define AVR32_TC_CV1_CV_SIZE 16\n#define AVR32_TC_CV2 0x00000090\n#define AVR32_TC_CV2_CV 0\n#define AVR32_TC_CV2_CV_MASK 0x0000ffff\n#define AVR32_TC_CV2_CV_OFFSET 0\n#define AVR32_TC_CV2_CV_SIZE 16\n#define AVR32_TC_CV_MASK 0x0000ffff\n#define AVR32_TC_CV_OFFSET 0\n#define AVR32_TC_CV_SIZE 16\n#define AVR32_TC_EEVT 10\n#define AVR32_TC_EEVTEDG 8\n#define AVR32_TC_EEVTEDG_BOTH_EDGES 0x00000003\n#define AVR32_TC_EEVTEDG_MASK 0x00000300\n#define AVR32_TC_EEVTEDG_NEG_EDGE 0x00000002\n#define AVR32_TC_EEVTEDG_NO_EDGE 0x00000000\n#define AVR32_TC_EEVTEDG_OFFSET 8\n#define AVR32_TC_EEVTEDG_POS_EDGE 0x00000001\n#define AVR32_TC_EEVTEDG_SIZE 2\n#define AVR32_TC_EEVT_MASK 0x00000c00\n#define AVR32_TC_EEVT_OFFSET 10\n#define AVR32_TC_EEVT_SIZE 2\n#define AVR32_TC_EEVT_TIOB_INPUT 0x00000000\n#define AVR32_TC_EEVT_XC0_OUTPUT 0x00000001\n#define AVR32_TC_EEVT_XC1_OUTPUT 0x00000002\n#define AVR32_TC_EEVT_XC2_OUTPUT 0x00000003\n#define AVR32_TC_ENETRG 12\n#define AVR32_TC_ENETRG_MASK 0x00001000\n#define AVR32_TC_ENETRG_OFFSET 12\n#define AVR32_TC_ENETRG_SIZE 1\n#define AVR32_TC_ETRGEDG 8\n#define AVR32_TC_ETRGEDG_BOTH_EDGES 0x00000003\n#define AVR32_TC_ETRGEDG_MASK 0x00000300\n#define AVR32_TC_ETRGEDG_NEG_EDGE 0x00000002\n#define AVR32_TC_ETRGEDG_NO_EDGE 0x00000000\n#define AVR32_TC_ETRGEDG_OFFSET 8\n#define AVR32_TC_ETRGEDG_POS_EDGE 0x00000001\n#define AVR32_TC_ETRGEDG_SIZE 2\n#define AVR32_TC_ETRGS 7\n#define AVR32_TC_ETRGS_MASK 0x00000080\n#define AVR32_TC_ETRGS_OFFSET 7\n#define AVR32_TC_ETRGS_SIZE 1\n#define AVR32_TC_IDR0 0x00000028\n#define AVR32_TC_IDR0_COVFS 0\n#define AVR32_TC_IDR0_COVFS_MASK 0x00000001\n#define AVR32_TC_IDR0_COVFS_OFFSET 0\n#define AVR32_TC_IDR0_COVFS_SIZE 1\n#define AVR32_TC_IDR0_CPAS 2\n#define AVR32_TC_IDR0_CPAS_MASK 0x00000004\n#define AVR32_TC_IDR0_CPAS_OFFSET 2\n#define AVR32_TC_IDR0_CPAS_SIZE 1\n#define AVR32_TC_IDR0_CPBS 3\n#define AVR32_TC_IDR0_CPBS_MASK 0x00000008\n#define AVR32_TC_IDR0_CPBS_OFFSET 3\n#define AVR32_TC_IDR0_CPBS_SIZE 1\n#define AVR32_TC_IDR0_CPCS 4\n#define AVR32_TC_IDR0_CPCS_MASK 0x00000010\n#define AVR32_TC_IDR0_CPCS_OFFSET 4\n#define AVR32_TC_IDR0_CPCS_SIZE 1\n#define AVR32_TC_IDR0_ETRGS 7\n#define AVR32_TC_IDR0_ETRGS_MASK 0x00000080\n#define AVR32_TC_IDR0_ETRGS_OFFSET 7\n#define AVR32_TC_IDR0_ETRGS_SIZE 1\n#define AVR32_TC_IDR0_LDRAS 5\n#define AVR32_TC_IDR0_LDRAS_MASK 0x00000020\n#define AVR32_TC_IDR0_LDRAS_OFFSET 5\n#define AVR32_TC_IDR0_LDRAS_SIZE 1\n#define AVR32_TC_IDR0_LDRBS 6\n#define AVR32_TC_IDR0_LDRBS_MASK 0x00000040\n#define AVR32_TC_IDR0_LDRBS_OFFSET 6\n#define AVR32_TC_IDR0_LDRBS_SIZE 1\n#define AVR32_TC_IDR0_LOVRS 1\n#define AVR32_TC_IDR0_LOVRS_MASK 0x00000002\n#define AVR32_TC_IDR0_LOVRS_OFFSET 1\n#define AVR32_TC_IDR0_LOVRS_SIZE 1\n#define AVR32_TC_IDR1 0x00000068\n#define AVR32_TC_IDR1_COVFS 0\n#define AVR32_TC_IDR1_COVFS_MASK 0x00000001\n#define AVR32_TC_IDR1_COVFS_OFFSET 0\n#define AVR32_TC_IDR1_COVFS_SIZE 1\n#define AVR32_TC_IDR1_CPAS 2\n#define AVR32_TC_IDR1_CPAS_MASK 0x00000004\n#define AVR32_TC_IDR1_CPAS_OFFSET 2\n#define AVR32_TC_IDR1_CPAS_SIZE 1\n#define AVR32_TC_IDR1_CPBS 3\n#define AVR32_TC_IDR1_CPBS_MASK 0x00000008\n#define AVR32_TC_IDR1_CPBS_OFFSET 3\n#define AVR32_TC_IDR1_CPBS_SIZE 1\n#define AVR32_TC_IDR1_CPCS 4\n#define AVR32_TC_IDR1_CPCS_MASK 0x00000010\n#define AVR32_TC_IDR1_CPCS_OFFSET 4\n#define AVR32_TC_IDR1_CPCS_SIZE 1\n#define AVR32_TC_IDR1_ETRGS 7\n#define AVR32_TC_IDR1_ETRGS_MASK 0x00000080\n#define AVR32_TC_IDR1_ETRGS_OFFSET 7\n#define AVR32_TC_IDR1_ETRGS_SIZE 1\n#define AVR32_TC_IDR1_LDRAS 5\n#define AVR32_TC_IDR1_LDRAS_MASK 0x00000020\n#define AVR32_TC_IDR1_LDRAS_OFFSET 5\n#define AVR32_TC_IDR1_LDRAS_SIZE 1\n#define AVR32_TC_IDR1_LDRBS 6\n#define AVR32_TC_IDR1_LDRBS_MASK 0x00000040\n#define AVR32_TC_IDR1_LDRBS_OFFSET 6\n#define AVR32_TC_IDR1_LDRBS_SIZE 1\n#define AVR32_TC_IDR1_LOVRS 1\n#define AVR32_TC_IDR1_LOVRS_MASK 0x00000002\n#define AVR32_TC_IDR1_LOVRS_OFFSET 1\n#define AVR32_TC_IDR1_LOVRS_SIZE 1\n#define AVR32_TC_IDR2 0x000000a8\n#define AVR32_TC_IDR2_COVFS 0\n#define AVR32_TC_IDR2_COVFS_MASK 0x00000001\n#define AVR32_TC_IDR2_COVFS_OFFSET 0\n#define AVR32_TC_IDR2_COVFS_SIZE 1\n#define AVR32_TC_IDR2_CPAS 2\n#define AVR32_TC_IDR2_CPAS_MASK 0x00000004\n#define AVR32_TC_IDR2_CPAS_OFFSET 2\n#define AVR32_TC_IDR2_CPAS_SIZE 1\n#define AVR32_TC_IDR2_CPBS 3\n#define AVR32_TC_IDR2_CPBS_MASK 0x00000008\n#define AVR32_TC_IDR2_CPBS_OFFSET 3\n#define AVR32_TC_IDR2_CPBS_SIZE 1\n#define AVR32_TC_IDR2_CPCS 4\n#define AVR32_TC_IDR2_CPCS_MASK 0x00000010\n#define AVR32_TC_IDR2_CPCS_OFFSET 4\n#define AVR32_TC_IDR2_CPCS_SIZE 1\n#define AVR32_TC_IDR2_ETRGS 7\n#define AVR32_TC_IDR2_ETRGS_MASK 0x00000080\n#define AVR32_TC_IDR2_ETRGS_OFFSET 7\n#define AVR32_TC_IDR2_ETRGS_SIZE 1\n#define AVR32_TC_IDR2_LDRAS 5\n#define AVR32_TC_IDR2_LDRAS_MASK 0x00000020\n#define AVR32_TC_IDR2_LDRAS_OFFSET 5\n#define AVR32_TC_IDR2_LDRAS_SIZE 1\n#define AVR32_TC_IDR2_LDRBS 6\n#define AVR32_TC_IDR2_LDRBS_MASK 0x00000040\n#define AVR32_TC_IDR2_LDRBS_OFFSET 6\n#define AVR32_TC_IDR2_LDRBS_SIZE 1\n#define AVR32_TC_IDR2_LOVRS 1\n#define AVR32_TC_IDR2_LOVRS_MASK 0x00000002\n#define AVR32_TC_IDR2_LOVRS_OFFSET 1\n#define AVR32_TC_IDR2_LOVRS_SIZE 1\n#define AVR32_TC_IER0 0x00000024\n#define AVR32_TC_IER0_COVFS 0\n#define AVR32_TC_IER0_COVFS_MASK 0x00000001\n#define AVR32_TC_IER0_COVFS_OFFSET 0\n#define AVR32_TC_IER0_COVFS_SIZE 1\n#define AVR32_TC_IER0_CPAS 2\n#define AVR32_TC_IER0_CPAS_MASK 0x00000004\n#define AVR32_TC_IER0_CPAS_OFFSET 2\n#define AVR32_TC_IER0_CPAS_SIZE 1\n#define AVR32_TC_IER0_CPBS 3\n#define AVR32_TC_IER0_CPBS_MASK 0x00000008\n#define AVR32_TC_IER0_CPBS_OFFSET 3\n#define AVR32_TC_IER0_CPBS_SIZE 1\n#define AVR32_TC_IER0_CPCS 4\n#define AVR32_TC_IER0_CPCS_MASK 0x00000010\n#define AVR32_TC_IER0_CPCS_OFFSET 4\n#define AVR32_TC_IER0_CPCS_SIZE 1\n#define AVR32_TC_IER0_ETRGS 7\n#define AVR32_TC_IER0_ETRGS_MASK 0x00000080\n#define AVR32_TC_IER0_ETRGS_OFFSET 7\n#define AVR32_TC_IER0_ETRGS_SIZE 1\n#define AVR32_TC_IER0_LDRAS 5\n#define AVR32_TC_IER0_LDRAS_MASK 0x00000020\n#define AVR32_TC_IER0_LDRAS_OFFSET 5\n#define AVR32_TC_IER0_LDRAS_SIZE 1\n#define AVR32_TC_IER0_LDRBS 6\n#define AVR32_TC_IER0_LDRBS_MASK 0x00000040\n#define AVR32_TC_IER0_LDRBS_OFFSET 6\n#define AVR32_TC_IER0_LDRBS_SIZE 1\n#define AVR32_TC_IER0_LOVRS 1\n#define AVR32_TC_IER0_LOVRS_MASK 0x00000002\n#define AVR32_TC_IER0_LOVRS_OFFSET 1\n#define AVR32_TC_IER0_LOVRS_SIZE 1\n#define AVR32_TC_IER1 0x00000064\n#define AVR32_TC_IER1_COVFS 0\n#define AVR32_TC_IER1_COVFS_MASK 0x00000001\n#define AVR32_TC_IER1_COVFS_OFFSET 0\n#define AVR32_TC_IER1_COVFS_SIZE 1\n#define AVR32_TC_IER1_CPAS 2\n#define AVR32_TC_IER1_CPAS_MASK 0x00000004\n#define AVR32_TC_IER1_CPAS_OFFSET 2\n#define AVR32_TC_IER1_CPAS_SIZE 1\n#define AVR32_TC_IER1_CPBS 3\n#define AVR32_TC_IER1_CPBS_MASK 0x00000008\n#define AVR32_TC_IER1_CPBS_OFFSET 3\n#define AVR32_TC_IER1_CPBS_SIZE 1\n#define AVR32_TC_IER1_CPCS 4\n#define AVR32_TC_IER1_CPCS_MASK 0x00000010\n#define AVR32_TC_IER1_CPCS_OFFSET 4\n#define AVR32_TC_IER1_CPCS_SIZE 1\n#define AVR32_TC_IER1_ETRGS 7\n#define AVR32_TC_IER1_ETRGS_MASK 0x00000080\n#define AVR32_TC_IER1_ETRGS_OFFSET 7\n#define AVR32_TC_IER1_ETRGS_SIZE 1\n#define AVR32_TC_IER1_LDRAS 5\n#define AVR32_TC_IER1_LDRAS_MASK 0x00000020\n#define AVR32_TC_IER1_LDRAS_OFFSET 5\n#define AVR32_TC_IER1_LDRAS_SIZE 1\n#define AVR32_TC_IER1_LDRBS 6\n#define AVR32_TC_IER1_LDRBS_MASK 0x00000040\n#define AVR32_TC_IER1_LDRBS_OFFSET 6\n#define AVR32_TC_IER1_LDRBS_SIZE 1\n#define AVR32_TC_IER1_LOVRS 1\n#define AVR32_TC_IER1_LOVRS_MASK 0x00000002\n#define AVR32_TC_IER1_LOVRS_OFFSET 1\n#define AVR32_TC_IER1_LOVRS_SIZE 1\n#define AVR32_TC_IER2 0x000000a4\n#define AVR32_TC_IER2_COVFS 0\n#define AVR32_TC_IER2_COVFS_MASK 0x00000001\n#define AVR32_TC_IER2_COVFS_OFFSET 0\n#define AVR32_TC_IER2_COVFS_SIZE 1\n#define AVR32_TC_IER2_CPAS 2\n#define AVR32_TC_IER2_CPAS_MASK 0x00000004\n#define AVR32_TC_IER2_CPAS_OFFSET 2\n#define AVR32_TC_IER2_CPAS_SIZE 1\n#define AVR32_TC_IER2_CPBS 3\n#define AVR32_TC_IER2_CPBS_MASK 0x00000008\n#define AVR32_TC_IER2_CPBS_OFFSET 3\n#define AVR32_TC_IER2_CPBS_SIZE 1\n#define AVR32_TC_IER2_CPCS 4\n#define AVR32_TC_IER2_CPCS_MASK 0x00000010\n#define AVR32_TC_IER2_CPCS_OFFSET 4\n#define AVR32_TC_IER2_CPCS_SIZE 1\n#define AVR32_TC_IER2_ETRGS 7\n#define AVR32_TC_IER2_ETRGS_MASK 0x00000080\n#define AVR32_TC_IER2_ETRGS_OFFSET 7\n#define AVR32_TC_IER2_ETRGS_SIZE 1\n#define AVR32_TC_IER2_LDRAS 5\n#define AVR32_TC_IER2_LDRAS_MASK 0x00000020\n#define AVR32_TC_IER2_LDRAS_OFFSET 5\n#define AVR32_TC_IER2_LDRAS_SIZE 1\n#define AVR32_TC_IER2_LDRBS 6\n#define AVR32_TC_IER2_LDRBS_MASK 0x00000040\n#define AVR32_TC_IER2_LDRBS_OFFSET 6\n#define AVR32_TC_IER2_LDRBS_SIZE 1\n#define AVR32_TC_IER2_LOVRS 1\n#define AVR32_TC_IER2_LOVRS_MASK 0x00000002\n#define AVR32_TC_IER2_LOVRS_OFFSET 1\n#define AVR32_TC_IER2_LOVRS_SIZE 1\n#define AVR32_TC_IMR0 0x0000002c\n#define AVR32_TC_IMR0_COVFS 0\n#define AVR32_TC_IMR0_COVFS_MASK 0x00000001\n#define AVR32_TC_IMR0_COVFS_OFFSET 0\n#define AVR32_TC_IMR0_COVFS_SIZE 1\n#define AVR32_TC_IMR0_CPAS 2\n#define AVR32_TC_IMR0_CPAS_MASK 0x00000004\n#define AVR32_TC_IMR0_CPAS_OFFSET 2\n#define AVR32_TC_IMR0_CPAS_SIZE 1\n#define AVR32_TC_IMR0_CPBS 3\n#define AVR32_TC_IMR0_CPBS_MASK 0x00000008\n#define AVR32_TC_IMR0_CPBS_OFFSET 3\n#define AVR32_TC_IMR0_CPBS_SIZE 1\n#define AVR32_TC_IMR0_CPCS 4\n#define AVR32_TC_IMR0_CPCS_MASK 0x00000010\n#define AVR32_TC_IMR0_CPCS_OFFSET 4\n#define AVR32_TC_IMR0_CPCS_SIZE 1\n#define AVR32_TC_IMR0_ETRGS 7\n#define AVR32_TC_IMR0_ETRGS_MASK 0x00000080\n#define AVR32_TC_IMR0_ETRGS_OFFSET 7\n#define AVR32_TC_IMR0_ETRGS_SIZE 1\n#define AVR32_TC_IMR0_LDRAS 5\n#define AVR32_TC_IMR0_LDRAS_MASK 0x00000020\n#define AVR32_TC_IMR0_LDRAS_OFFSET 5\n#define AVR32_TC_IMR0_LDRAS_SIZE 1\n#define AVR32_TC_IMR0_LDRBS 6\n#define AVR32_TC_IMR0_LDRBS_MASK 0x00000040\n#define AVR32_TC_IMR0_LDRBS_OFFSET 6\n#define AVR32_TC_IMR0_LDRBS_SIZE 1\n#define AVR32_TC_IMR0_LOVRS 1\n#define AVR32_TC_IMR0_LOVRS_MASK 0x00000002\n#define AVR32_TC_IMR0_LOVRS_OFFSET 1\n#define AVR32_TC_IMR0_LOVRS_SIZE 1\n#define AVR32_TC_IMR1 0x0000006c\n#define AVR32_TC_IMR1_COVFS 0\n#define AVR32_TC_IMR1_COVFS_MASK 0x00000001\n#define AVR32_TC_IMR1_COVFS_OFFSET 0\n#define AVR32_TC_IMR1_COVFS_SIZE 1\n#define AVR32_TC_IMR1_CPAS 2\n#define AVR32_TC_IMR1_CPAS_MASK 0x00000004\n#define AVR32_TC_IMR1_CPAS_OFFSET 2\n#define AVR32_TC_IMR1_CPAS_SIZE 1\n#define AVR32_TC_IMR1_CPBS 3\n#define AVR32_TC_IMR1_CPBS_MASK 0x00000008\n#define AVR32_TC_IMR1_CPBS_OFFSET 3\n#define AVR32_TC_IMR1_CPBS_SIZE 1\n#define AVR32_TC_IMR1_CPCS 4\n#define AVR32_TC_IMR1_CPCS_MASK 0x00000010\n#define AVR32_TC_IMR1_CPCS_OFFSET 4\n#define AVR32_TC_IMR1_CPCS_SIZE 1\n#define AVR32_TC_IMR1_ETRGS 7\n#define AVR32_TC_IMR1_ETRGS_MASK 0x00000080\n#define AVR32_TC_IMR1_ETRGS_OFFSET 7\n#define AVR32_TC_IMR1_ETRGS_SIZE 1\n#define AVR32_TC_IMR1_LDRAS 5\n#define AVR32_TC_IMR1_LDRAS_MASK 0x00000020\n#define AVR32_TC_IMR1_LDRAS_OFFSET 5\n#define AVR32_TC_IMR1_LDRAS_SIZE 1\n#define AVR32_TC_IMR1_LDRBS 6\n#define AVR32_TC_IMR1_LDRBS_MASK 0x00000040\n#define AVR32_TC_IMR1_LDRBS_OFFSET 6\n#define AVR32_TC_IMR1_LDRBS_SIZE 1\n#define AVR32_TC_IMR1_LOVRS 1\n#define AVR32_TC_IMR1_LOVRS_MASK 0x00000002\n#define AVR32_TC_IMR1_LOVRS_OFFSET 1\n#define AVR32_TC_IMR1_LOVRS_SIZE 1\n#define AVR32_TC_IMR2 0x000000ac\n#define AVR32_TC_IMR2_COVFS 0\n#define AVR32_TC_IMR2_COVFS_MASK 0x00000001\n#define AVR32_TC_IMR2_COVFS_OFFSET 0\n#define AVR32_TC_IMR2_COVFS_SIZE 1\n#define AVR32_TC_IMR2_CPAS 2\n#define AVR32_TC_IMR2_CPAS_MASK 0x00000004\n#define AVR32_TC_IMR2_CPAS_OFFSET 2\n#define AVR32_TC_IMR2_CPAS_SIZE 1\n#define AVR32_TC_IMR2_CPBS 3\n#define AVR32_TC_IMR2_CPBS_MASK 0x00000008\n#define AVR32_TC_IMR2_CPBS_OFFSET 3\n#define AVR32_TC_IMR2_CPBS_SIZE 1\n#define AVR32_TC_IMR2_CPCS 4\n#define AVR32_TC_IMR2_CPCS_MASK 0x00000010\n#define AVR32_TC_IMR2_CPCS_OFFSET 4\n#define AVR32_TC_IMR2_CPCS_SIZE 1\n#define AVR32_TC_IMR2_ETRGS 7\n#define AVR32_TC_IMR2_ETRGS_MASK 0x00000080\n#define AVR32_TC_IMR2_ETRGS_OFFSET 7\n#define AVR32_TC_IMR2_ETRGS_SIZE 1\n#define AVR32_TC_IMR2_LDRAS 5\n#define AVR32_TC_IMR2_LDRAS_MASK 0x00000020\n#define AVR32_TC_IMR2_LDRAS_OFFSET 5\n#define AVR32_TC_IMR2_LDRAS_SIZE 1\n#define AVR32_TC_IMR2_LDRBS 6\n#define AVR32_TC_IMR2_LDRBS_MASK 0x00000040\n#define AVR32_TC_IMR2_LDRBS_OFFSET 6\n#define AVR32_TC_IMR2_LDRBS_SIZE 1\n#define AVR32_TC_IMR2_LOVRS 1\n#define AVR32_TC_IMR2_LOVRS_MASK 0x00000002\n#define AVR32_TC_IMR2_LOVRS_OFFSET 1\n#define AVR32_TC_IMR2_LOVRS_SIZE 1\n#define AVR32_TC_LDBDIS 7\n#define AVR32_TC_LDBDIS_MASK 0x00000080\n#define AVR32_TC_LDBDIS_OFFSET 7\n#define AVR32_TC_LDBDIS_SIZE 1\n#define AVR32_TC_LDBSTOP 6\n#define AVR32_TC_LDBSTOP_MASK 0x00000040\n#define AVR32_TC_LDBSTOP_OFFSET 6\n#define AVR32_TC_LDBSTOP_SIZE 1\n#define AVR32_TC_LDRA 16\n#define AVR32_TC_LDRAS 5\n#define AVR32_TC_LDRAS_MASK 0x00000020\n#define AVR32_TC_LDRAS_OFFSET 5\n#define AVR32_TC_LDRAS_SIZE 1\n#define AVR32_TC_LDRA_BIOTH_EDGES_TIOA 0x00000003\n#define AVR32_TC_LDRA_MASK 0x00030000\n#define AVR32_TC_LDRA_NEG_EDGE_TIOA 0x00000002\n#define AVR32_TC_LDRA_NO_EDGE 0x00000000\n#define AVR32_TC_LDRA_OFFSET 16\n#define AVR32_TC_LDRA_POS_EDGE_TIOA 0x00000001\n#define AVR32_TC_LDRA_SIZE 2\n#define AVR32_TC_LDRB 18\n#define AVR32_TC_LDRBS 6\n#define AVR32_TC_LDRBS_MASK 0x00000040\n#define AVR32_TC_LDRBS_OFFSET 6\n#define AVR32_TC_LDRBS_SIZE 1\n#define AVR32_TC_LDRB_BIOTH_EDGES_TIOA 0x00000003\n#define AVR32_TC_LDRB_MASK 0x000c0000\n#define AVR32_TC_LDRB_NEG_EDGE_TIOA 0x00000002\n#define AVR32_TC_LDRB_NO_EDGE 0x00000000\n#define AVR32_TC_LDRB_OFFSET 18\n#define AVR32_TC_LDRB_POS_EDGE_TIOA 0x00000001\n#define AVR32_TC_LDRB_SIZE 2\n#define AVR32_TC_LOVRS 1\n#define AVR32_TC_LOVRS_MASK 0x00000002\n#define AVR32_TC_LOVRS_OFFSET 1\n#define AVR32_TC_LOVRS_SIZE 1\n#define AVR32_TC_MTIOA 17\n#define AVR32_TC_MTIOA_MASK 0x00020000\n#define AVR32_TC_MTIOA_OFFSET 17\n#define AVR32_TC_MTIOA_SIZE 1\n#define AVR32_TC_MTIOB 18\n#define AVR32_TC_MTIOB_MASK 0x00040000\n#define AVR32_TC_MTIOB_OFFSET 18\n#define AVR32_TC_MTIOB_SIZE 1\n#define AVR32_TC_NEG_EDGE 0x00000002\n#define AVR32_TC_NEG_EDGE_TIOA 0x00000002\n#define AVR32_TC_NONE 0x00000000\n#define AVR32_TC_NOT_GATED 0x00000000\n#define AVR32_TC_NO_CLK 0x00000001\n#define AVR32_TC_NO_EDGE 0x00000000\n#define AVR32_TC_POS_EDGE 0x00000001\n#define AVR32_TC_POS_EDGE_TIOA 0x00000001\n#define AVR32_TC_RA 0\n#define AVR32_TC_RA0 0x00000014\n#define AVR32_TC_RA0_RA 0\n#define AVR32_TC_RA0_RA_MASK 0x0000ffff\n#define AVR32_TC_RA0_RA_OFFSET 0\n#define AVR32_TC_RA0_RA_SIZE 16\n#define AVR32_TC_RA1 0x00000054\n#define AVR32_TC_RA1_RA 0\n#define AVR32_TC_RA1_RA_MASK 0x0000ffff\n#define AVR32_TC_RA1_RA_OFFSET 0\n#define AVR32_TC_RA1_RA_SIZE 16\n#define AVR32_TC_RA2 0x00000094\n#define AVR32_TC_RA2_RA 0\n#define AVR32_TC_RA2_RA_MASK 0x0000ffff\n#define AVR32_TC_RA2_RA_OFFSET 0\n#define AVR32_TC_RA2_RA_SIZE 16\n#define AVR32_TC_RA_MASK 0x0000ffff\n#define AVR32_TC_RA_OFFSET 0\n#define AVR32_TC_RA_SIZE 16\n#define AVR32_TC_RB 0\n#define AVR32_TC_RB0 0x00000018\n#define AVR32_TC_RB0_RB 0\n#define AVR32_TC_RB0_RB_MASK 0x0000ffff\n#define AVR32_TC_RB0_RB_OFFSET 0\n#define AVR32_TC_RB0_RB_SIZE 16\n#define AVR32_TC_RB1 0x00000058\n#define AVR32_TC_RB1_RB 0\n#define AVR32_TC_RB1_RB_MASK 0x0000ffff\n#define AVR32_TC_RB1_RB_OFFSET 0\n#define AVR32_TC_RB1_RB_SIZE 16\n#define AVR32_TC_RB2 0x00000098\n#define AVR32_TC_RB2_RB 0\n#define AVR32_TC_RB2_RB_MASK 0x0000ffff\n#define AVR32_TC_RB2_RB_OFFSET 0\n#define AVR32_TC_RB2_RB_SIZE 16\n#define AVR32_TC_RB_MASK 0x0000ffff\n#define AVR32_TC_RB_OFFSET 0\n#define AVR32_TC_RB_SIZE 16\n#define AVR32_TC_RC 0\n#define AVR32_TC_RC0 0x0000001c\n#define AVR32_TC_RC0_RC 0\n#define AVR32_TC_RC0_RC_MASK 0x0000ffff\n#define AVR32_TC_RC0_RC_OFFSET 0\n#define AVR32_TC_RC0_RC_SIZE 16\n#define AVR32_TC_RC1 0x0000005c\n#define AVR32_TC_RC1_RC 0\n#define AVR32_TC_RC1_RC_MASK 0x0000ffff\n#define AVR32_TC_RC1_RC_OFFSET 0\n#define AVR32_TC_RC1_RC_SIZE 16\n#define AVR32_TC_RC2 0x0000009c\n#define AVR32_TC_RC2_RC 0\n#define AVR32_TC_RC2_RC_MASK 0x0000ffff\n#define AVR32_TC_RC2_RC_OFFSET 0\n#define AVR32_TC_RC2_RC_SIZE 16\n#define AVR32_TC_RC_MASK 0x0000ffff\n#define AVR32_TC_RC_OFFSET 0\n#define AVR32_TC_RC_SIZE 16\n#define AVR32_TC_SET 0x00000001\n#define AVR32_TC_SR0 0x00000020\n#define AVR32_TC_SR0_CLKSTA 16\n#define AVR32_TC_SR0_CLKSTA_MASK 0x00010000\n#define AVR32_TC_SR0_CLKSTA_OFFSET 16\n#define AVR32_TC_SR0_CLKSTA_SIZE 1\n#define AVR32_TC_SR0_COVFS 0\n#define AVR32_TC_SR0_COVFS_MASK 0x00000001\n#define AVR32_TC_SR0_COVFS_OFFSET 0\n#define AVR32_TC_SR0_COVFS_SIZE 1\n#define AVR32_TC_SR0_CPAS 2\n#define AVR32_TC_SR0_CPAS_MASK 0x00000004\n#define AVR32_TC_SR0_CPAS_OFFSET 2\n#define AVR32_TC_SR0_CPAS_SIZE 1\n#define AVR32_TC_SR0_CPBS 3\n#define AVR32_TC_SR0_CPBS_MASK 0x00000008\n#define AVR32_TC_SR0_CPBS_OFFSET 3\n#define AVR32_TC_SR0_CPBS_SIZE 1\n#define AVR32_TC_SR0_CPCS 4\n#define AVR32_TC_SR0_CPCS_MASK 0x00000010\n#define AVR32_TC_SR0_CPCS_OFFSET 4\n#define AVR32_TC_SR0_CPCS_SIZE 1\n#define AVR32_TC_SR0_ETRGS 7\n#define AVR32_TC_SR0_ETRGS_MASK 0x00000080\n#define AVR32_TC_SR0_ETRGS_OFFSET 7\n#define AVR32_TC_SR0_ETRGS_SIZE 1\n#define AVR32_TC_SR0_LDRAS 5\n#define AVR32_TC_SR0_LDRAS_MASK 0x00000020\n#define AVR32_TC_SR0_LDRAS_OFFSET 5\n#define AVR32_TC_SR0_LDRAS_SIZE 1\n#define AVR32_TC_SR0_LDRBS 6\n#define AVR32_TC_SR0_LDRBS_MASK 0x00000040\n#define AVR32_TC_SR0_LDRBS_OFFSET 6\n#define AVR32_TC_SR0_LDRBS_SIZE 1\n#define AVR32_TC_SR0_LOVRS 1\n#define AVR32_TC_SR0_LOVRS_MASK 0x00000002\n#define AVR32_TC_SR0_LOVRS_OFFSET 1\n#define AVR32_TC_SR0_LOVRS_SIZE 1\n#define AVR32_TC_SR0_MTIOA 17\n#define AVR32_TC_SR0_MTIOA_MASK 0x00020000\n#define AVR32_TC_SR0_MTIOA_OFFSET 17\n#define AVR32_TC_SR0_MTIOA_SIZE 1\n#define AVR32_TC_SR0_MTIOB 18\n#define AVR32_TC_SR0_MTIOB_MASK 0x00040000\n#define AVR32_TC_SR0_MTIOB_OFFSET 18\n#define AVR32_TC_SR0_MTIOB_SIZE 1\n#define AVR32_TC_SR1 0x00000060\n#define AVR32_TC_SR1_CLKSTA 16\n#define AVR32_TC_SR1_CLKSTA_MASK 0x00010000\n#define AVR32_TC_SR1_CLKSTA_OFFSET 16\n#define AVR32_TC_SR1_CLKSTA_SIZE 1\n#define AVR32_TC_SR1_COVFS 0\n#define AVR32_TC_SR1_COVFS_MASK 0x00000001\n#define AVR32_TC_SR1_COVFS_OFFSET 0\n#define AVR32_TC_SR1_COVFS_SIZE 1\n#define AVR32_TC_SR1_CPAS 2\n#define AVR32_TC_SR1_CPAS_MASK 0x00000004\n#define AVR32_TC_SR1_CPAS_OFFSET 2\n#define AVR32_TC_SR1_CPAS_SIZE 1\n#define AVR32_TC_SR1_CPBS 3\n#define AVR32_TC_SR1_CPBS_MASK 0x00000008\n#define AVR32_TC_SR1_CPBS_OFFSET 3\n#define AVR32_TC_SR1_CPBS_SIZE 1\n#define AVR32_TC_SR1_CPCS 4\n#define AVR32_TC_SR1_CPCS_MASK 0x00000010\n#define AVR32_TC_SR1_CPCS_OFFSET 4\n#define AVR32_TC_SR1_CPCS_SIZE 1\n#define AVR32_TC_SR1_ETRGS 7\n#define AVR32_TC_SR1_ETRGS_MASK 0x00000080\n#define AVR32_TC_SR1_ETRGS_OFFSET 7\n#define AVR32_TC_SR1_ETRGS_SIZE 1\n#define AVR32_TC_SR1_LDRAS 5\n#define AVR32_TC_SR1_LDRAS_MASK 0x00000020\n#define AVR32_TC_SR1_LDRAS_OFFSET 5\n#define AVR32_TC_SR1_LDRAS_SIZE 1\n#define AVR32_TC_SR1_LDRBS 6\n#define AVR32_TC_SR1_LDRBS_MASK 0x00000040\n#define AVR32_TC_SR1_LDRBS_OFFSET 6\n#define AVR32_TC_SR1_LDRBS_SIZE 1\n#define AVR32_TC_SR1_LOVRS 1\n#define AVR32_TC_SR1_LOVRS_MASK 0x00000002\n#define AVR32_TC_SR1_LOVRS_OFFSET 1\n#define AVR32_TC_SR1_LOVRS_SIZE 1\n#define AVR32_TC_SR1_MTIOA 17\n#define AVR32_TC_SR1_MTIOA_MASK 0x00020000\n#define AVR32_TC_SR1_MTIOA_OFFSET 17\n#define AVR32_TC_SR1_MTIOA_SIZE 1\n#define AVR32_TC_SR1_MTIOB 18\n#define AVR32_TC_SR1_MTIOB_MASK 0x00040000\n#define AVR32_TC_SR1_MTIOB_OFFSET 18\n#define AVR32_TC_SR1_MTIOB_SIZE 1\n#define AVR32_TC_SR2 0x000000a0\n#define AVR32_TC_SR2_CLKSTA 16\n#define AVR32_TC_SR2_CLKSTA_MASK 0x00010000\n#define AVR32_TC_SR2_CLKSTA_OFFSET 16\n#define AVR32_TC_SR2_CLKSTA_SIZE 1\n#define AVR32_TC_SR2_COVFS 0\n#define AVR32_TC_SR2_COVFS_MASK 0x00000001\n#define AVR32_TC_SR2_COVFS_OFFSET 0\n#define AVR32_TC_SR2_COVFS_SIZE 1\n#define AVR32_TC_SR2_CPAS 2\n#define AVR32_TC_SR2_CPAS_MASK 0x00000004\n#define AVR32_TC_SR2_CPAS_OFFSET 2\n#define AVR32_TC_SR2_CPAS_SIZE 1\n#define AVR32_TC_SR2_CPBS 3\n#define AVR32_TC_SR2_CPBS_MASK 0x00000008\n#define AVR32_TC_SR2_CPBS_OFFSET 3\n#define AVR32_TC_SR2_CPBS_SIZE 1\n#define AVR32_TC_SR2_CPCS 4\n#define AVR32_TC_SR2_CPCS_MASK 0x00000010\n#define AVR32_TC_SR2_CPCS_OFFSET 4\n#define AVR32_TC_SR2_CPCS_SIZE 1\n#define AVR32_TC_SR2_ETRGS 7\n#define AVR32_TC_SR2_ETRGS_MASK 0x00000080\n#define AVR32_TC_SR2_ETRGS_OFFSET 7\n#define AVR32_TC_SR2_ETRGS_SIZE 1\n#define AVR32_TC_SR2_LDRAS 5\n#define AVR32_TC_SR2_LDRAS_MASK 0x00000020\n#define AVR32_TC_SR2_LDRAS_OFFSET 5\n#define AVR32_TC_SR2_LDRAS_SIZE 1\n#define AVR32_TC_SR2_LDRBS 6\n#define AVR32_TC_SR2_LDRBS_MASK 0x00000040\n#define AVR32_TC_SR2_LDRBS_OFFSET 6\n#define AVR32_TC_SR2_LDRBS_SIZE 1\n#define AVR32_TC_SR2_LOVRS 1\n#define AVR32_TC_SR2_LOVRS_MASK 0x00000002\n#define AVR32_TC_SR2_LOVRS_OFFSET 1\n#define AVR32_TC_SR2_LOVRS_SIZE 1\n#define AVR32_TC_SR2_MTIOA 17\n#define AVR32_TC_SR2_MTIOA_MASK 0x00020000\n#define AVR32_TC_SR2_MTIOA_OFFSET 17\n#define AVR32_TC_SR2_MTIOA_SIZE 1\n#define AVR32_TC_SR2_MTIOB 18\n#define AVR32_TC_SR2_MTIOB_MASK 0x00040000\n#define AVR32_TC_SR2_MTIOB_OFFSET 18\n#define AVR32_TC_SR2_MTIOB_SIZE 1\n#define AVR32_TC_SWTRG 2\n#define AVR32_TC_SWTRG_MASK 0x00000004\n#define AVR32_TC_SWTRG_OFFSET 2\n#define AVR32_TC_SWTRG_SIZE 1\n#define AVR32_TC_SYNC 0\n#define AVR32_TC_SYNC_MASK 0x00000001\n#define AVR32_TC_SYNC_OFFSET 0\n#define AVR32_TC_SYNC_SIZE 1\n#define AVR32_TC_TC0XC0S 0\n#define AVR32_TC_TC0XC0S_MASK 0x00000003\n#define AVR32_TC_TC0XC0S_NO_CLK 0x00000001\n#define AVR32_TC_TC0XC0S_OFFSET 0\n#define AVR32_TC_TC0XC0S_SIZE 2\n#define AVR32_TC_TC0XC0S_TCLK0 0x00000000\n#define AVR32_TC_TC0XC0S_TIOA1 0x00000002\n#define AVR32_TC_TC0XC0S_TIOA2 0x00000003\n#define AVR32_TC_TC1XC1S 2\n#define AVR32_TC_TC1XC1S_MASK 0x0000000c\n#define AVR32_TC_TC1XC1S_NO_CLK 0x00000001\n#define AVR32_TC_TC1XC1S_OFFSET 2\n#define AVR32_TC_TC1XC1S_SIZE 2\n#define AVR32_TC_TC1XC1S_TCLK1 0x00000000\n#define AVR32_TC_TC1XC1S_TIOA0 0x00000002\n#define AVR32_TC_TC1XC1S_TIOA2 0x00000003\n#define AVR32_TC_TC2XC2S 4\n#define AVR32_TC_TC2XC2S_MASK 0x00000030\n#define AVR32_TC_TC2XC2S_NO_CLK 0x00000001\n#define AVR32_TC_TC2XC2S_OFFSET 4\n#define AVR32_TC_TC2XC2S_SIZE 2\n#define AVR32_TC_TC2XC2S_TCLK2 0x00000000\n#define AVR32_TC_TC2XC2S_TIOA0 0x00000002\n#define AVR32_TC_TC2XC2S_TIOA1 0x00000003\n#define AVR32_TC_TCCLKS 0\n#define AVR32_TC_TCCLKS_MASK 0x00000007\n#define AVR32_TC_TCCLKS_OFFSET 0\n#define AVR32_TC_TCCLKS_SIZE 3\n#define AVR32_TC_TCCLKS_TIMER_CLOCK1 0x00000000\n#define AVR32_TC_TCCLKS_TIMER_CLOCK2 0x00000001\n#define AVR32_TC_TCCLKS_TIMER_CLOCK3 0x00000002\n#define AVR32_TC_TCCLKS_TIMER_CLOCK4 0x00000003\n#define AVR32_TC_TCCLKS_TIMER_CLOCK5 0x00000004\n#define AVR32_TC_TCCLKS_XC0 0x00000005\n#define AVR32_TC_TCCLKS_XC1 0x00000006\n#define AVR32_TC_TCCLKS_XC2 0x00000007\n#define AVR32_TC_TCLK0 0x00000000\n#define AVR32_TC_TCLK1 0x00000000\n#define AVR32_TC_TCLK2 0x00000000\n#define AVR32_TC_TIMER_CLOCK1 0x00000000\n#define AVR32_TC_TIMER_CLOCK2 0x00000001\n#define AVR32_TC_TIMER_CLOCK3 0x00000002\n#define AVR32_TC_TIMER_CLOCK4 0x00000003\n#define AVR32_TC_TIMER_CLOCK5 0x00000004\n#define AVR32_TC_TIOA0 0x00000002\n#define AVR32_TC_TIOA2 0x00000003\n#define AVR32_TC_TIOB_INPUT 0x00000000\n#define AVR32_TC_TOGGLE 0x00000003\n#define AVR32_TC_UPDOWN_AUTO 0x00000003\n#define AVR32_TC_UPDOWN_NO_AUTO 0x00000001\n#define AVR32_TC_UP_AUTO 0x00000002\n#define AVR32_TC_UP_NO_AUTO 0x00000000\n#define AVR32_TC_WAVE 15\n#define AVR32_TC_WAVE_MASK 0x00008000\n#define AVR32_TC_WAVE_OFFSET 15\n#define AVR32_TC_WAVE_SIZE 1\n#define AVR32_TC_WAVSEL 13\n#define AVR32_TC_WAVSEL_MASK 0x00006000\n#define AVR32_TC_WAVSEL_OFFSET 13\n#define AVR32_TC_WAVSEL_SIZE 2\n#define AVR32_TC_WAVSEL_UPDOWN_AUTO 0x00000003\n#define AVR32_TC_WAVSEL_UPDOWN_NO_AUTO 0x00000001\n#define AVR32_TC_WAVSEL_UP_AUTO 0x00000002\n#define AVR32_TC_WAVSEL_UP_NO_AUTO 0x00000000\n#define AVR32_TC_XC0 0x00000005\n#define AVR32_TC_XC0_OUTPUT 0x00000001\n#define AVR32_TC_XC1 0x00000006\n#define AVR32_TC_XC1_OUTPUT 0x00000002\n#define AVR32_TC_XC2 0x00000007\n#define AVR32_TC_XC2_OUTPUT 0x00000003\n#define AVR32_TC_VARIANT 16\n#define AVR32_TC_VARIANT_MASK 0x00070000\n#define AVR32_TC_VARIANT_OFFSET 16\n#define AVR32_TC_VARIANT_SIZE 3\n#define AVR32_TC_VERSION 0x000000fc\n#define AVR32_TC_VERSION_MASK 0x00000fff\n#define AVR32_TC_VERSION_OFFSET 0\n#define AVR32_TC_VERSION_SIZE 12\n#define AVR32_TC_VERSION_VARIANT 16\n#define AVR32_TC_VERSION_VARIANT_MASK 0x00070000\n#define AVR32_TC_VERSION_VARIANT_OFFSET 16\n#define AVR32_TC_VERSION_VARIANT_SIZE 3\n#define AVR32_TC_VERSION_VERSION 0\n#define AVR32_TC_VERSION_VERSION_MASK 0x00000fff\n#define AVR32_TC_VERSION_VERSION_OFFSET 0\n#define AVR32_TC_VERSION_VERSION_SIZE 12\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_tc_ccr_t {\n unsigned int :29;\n unsigned int swtrg : 1;\n unsigned int clkdis : 1;\n unsigned int clken : 1;\n} avr32_tc_ccr_t;\n\n\n\ntypedef union avr32_tc_cmr_t {\n struct {\n unsigned int :12;\n unsigned int ldrb : 2;\n unsigned int ldra : 2;\n unsigned int wave : 1;\n unsigned int cpctrg : 1;\n unsigned int : 3;\n unsigned int abetrg : 1;\n unsigned int etrgedg : 2;\n unsigned int ldbdis : 1;\n unsigned int ldbstop : 1;\n unsigned int burst : 2;\n unsigned int clki : 1;\n unsigned int tcclks : 3;\n } capture;\n struct {\n unsigned int bswtrg : 2;\n unsigned int beevt : 2;\n unsigned int bcpc : 2;\n unsigned int bcpb : 2;\n unsigned int aswtrg : 2;\n unsigned int aeevt : 2;\n unsigned int acpc : 2;\n unsigned int acpa : 2;\n unsigned int wave : 1;\n unsigned int wavsel : 2;\n unsigned int enetrg : 1;\n unsigned int eevt : 2;\n unsigned int eevtedg : 2;\n unsigned int cpcdis : 1;\n unsigned int cpcstop : 1;\n unsigned int burst : 2;\n unsigned int clki : 1;\n unsigned int tcclks : 3;\n } waveform;\n} avr32_tc_cmr_t;\n\n\n\ntypedef struct avr32_tc_cv_t {\n unsigned int :16;\n unsigned int cv :16;\n} avr32_tc_cv_t;\n\n\n\ntypedef struct avr32_tc_ra_t {\n unsigned int :16;\n unsigned int ra :16;\n} avr32_tc_ra_t;\n\n\n\ntypedef struct avr32_tc_rb_t {\n unsigned int :16;\n unsigned int rb :16;\n} avr32_tc_rb_t;\n\n\n\ntypedef struct avr32_tc_rc_t {\n unsigned int :16;\n unsigned int rc :16;\n} avr32_tc_rc_t;\n\n\n\ntypedef struct avr32_tc_sr_t {\n unsigned int :13;\n unsigned int mtiob : 1;\n unsigned int mtioa : 1;\n unsigned int clksta : 1;\n unsigned int : 8;\n unsigned int etrgs : 1;\n unsigned int ldrbs : 1;\n unsigned int ldras : 1;\n unsigned int cpcs : 1;\n unsigned int cpbs : 1;\n unsigned int cpas : 1;\n unsigned int lovrs : 1;\n unsigned int covfs : 1;\n} avr32_tc_sr_t;\n\n\n\ntypedef struct avr32_tc_ier_t {\n unsigned int :24;\n unsigned int etrgs : 1;\n unsigned int ldrbs : 1;\n unsigned int ldras : 1;\n unsigned int cpcs : 1;\n unsigned int cpbs : 1;\n unsigned int cpas : 1;\n unsigned int lovrs : 1;\n unsigned int covfs : 1;\n} avr32_tc_ier_t;\n\n\n\ntypedef struct avr32_tc_idr_t {\n unsigned int :24;\n unsigned int etrgs : 1;\n unsigned int ldrbs : 1;\n unsigned int ldras : 1;\n unsigned int cpcs : 1;\n unsigned int cpbs : 1;\n unsigned int cpas : 1;\n unsigned int lovrs : 1;\n unsigned int covfs : 1;\n} avr32_tc_idr_t;\n\n\n\ntypedef struct avr32_tc_imr_t {\n unsigned int :24;\n unsigned int etrgs : 1;\n unsigned int ldrbs : 1;\n unsigned int ldras : 1;\n unsigned int cpcs : 1;\n unsigned int cpbs : 1;\n unsigned int cpas : 1;\n unsigned int lovrs : 1;\n unsigned int covfs : 1;\n} avr32_tc_imr_t;\n\n\n\ntypedef struct avr32_tc_bcr_t {\n unsigned int :31;\n unsigned int sync : 1;\n} avr32_tc_bcr_t;\n\n\n\ntypedef struct avr32_tc_bmr_t {\n unsigned int :26;\n unsigned int tc2xc2s : 2;\n unsigned int tc1xc1s : 2;\n unsigned int tc0xc0s : 2;\n} avr32_tc_bmr_t;\n\n\n\ntypedef struct avr32_tc_version_t {\n unsigned int :13;\n unsigned int variant : 3;\n unsigned int : 4;\n unsigned int version :12;\n} avr32_tc_version_t;\n\n\ntypedef struct avr32_tc_channel_t {\n union {\n unsigned long ccr ;//0x0000\n avr32_tc_ccr_t CCR ;\n };\n union {\n unsigned long cmr ;//0x0004\n avr32_tc_cmr_t CMR ;\n };\n unsigned int :32 ;//0x0008\n unsigned int :32 ;//0x000c\n union {\n const unsigned long cv ;//0x0010\n const avr32_tc_cv_t CV ;\n };\n union {\n unsigned long ra ;//0x0014\n avr32_tc_ra_t RA ;\n };\n union {\n unsigned long rb ;//0x0018\n avr32_tc_rb_t RB ;\n };\n union {\n unsigned long rc ;//0x001c\n avr32_tc_rc_t RC ;\n };\n union {\n const unsigned long sr ;//0x0020\n const avr32_tc_sr_t SR ;\n };\n union {\n unsigned long ier ;//0x0024\n avr32_tc_ier_t IER ;\n };\n union {\n unsigned long idr ;//0x0028\n avr32_tc_idr_t IDR ;\n };\n union {\n const unsigned long imr ;//0x002c\n const avr32_tc_imr_t IMR ;\n };\n unsigned int :32 ;//0x0030\n unsigned int :32 ;//0x0034\n unsigned int :32 ;//0x0038\n unsigned int :32 ;//0x003c\n} avr32_tc_channel_t;\n\n\ntypedef struct avr32_tc_t {\n avr32_tc_channel_t channel[3];//0x0\n union {\n unsigned long bcr ;//0x00c0\n avr32_tc_bcr_t BCR ;\n };\n union {\n unsigned long bmr ;//0x00c4\n avr32_tc_bmr_t BMR ;\n };\n unsigned int :32 ;//0x00c8\n unsigned int :32 ;//0x00cc\n unsigned int :32 ;//0x00d0\n unsigned int :32 ;//0x00d4\n unsigned int :32 ;//0x00d8\n unsigned int :32 ;//0x00dc\n unsigned int :32 ;//0x00e0\n unsigned int :32 ;//0x00e4\n unsigned int :32 ;//0x00e8\n unsigned int :32 ;//0x00ec\n unsigned int :32 ;//0x00f0\n unsigned int :32 ;//0x00f4\n unsigned int :32 ;//0x00f8\n union {\n const unsigned long version ;//0x00fc\n const avr32_tc_version_t VERSION ;\n };\n} avr32_tc_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n\n#if !defined (DEPRECATED_DISABLE)\n\n#define AVR32_TC_CMR0_TCCLKS_TIMER_DIV1_CLOCK 0x00000000\n#define AVR32_TC_CMR0_TCCLKS_TIMER_DIV2_CLOCK 0x00000001\n#define AVR32_TC_CMR0_TCCLKS_TIMER_DIV3_CLOCK 0x00000002\n#define AVR32_TC_CMR0_TCCLKS_TIMER_DIV4_CLOCK 0x00000003\n#define AVR32_TC_CMR0_TCCLKS_TIMER_DIV5_CLOCK 0x00000004\n\n#define AVR32_TC_CMR1_TCCLKS_TIMER_DIV1_CLOCK 0x00000000\n#define AVR32_TC_CMR1_TCCLKS_TIMER_DIV2_CLOCK 0x00000001\n#define AVR32_TC_CMR1_TCCLKS_TIMER_DIV3_CLOCK 0x00000002\n#define AVR32_TC_CMR1_TCCLKS_TIMER_DIV4_CLOCK 0x00000003\n#define AVR32_TC_CMR1_TCCLKS_TIMER_DIV5_CLOCK 0x00000004\n\n#define AVR32_TC_CMR2_TCCLKS_TIMER_DIV1_CLOCK 0x00000000\n#define AVR32_TC_CMR2_TCCLKS_TIMER_DIV2_CLOCK 0x00000001\n#define AVR32_TC_CMR2_TCCLKS_TIMER_DIV3_CLOCK 0x00000002\n#define AVR32_TC_CMR2_TCCLKS_TIMER_DIV4_CLOCK 0x00000003\n#define AVR32_TC_CMR2_TCCLKS_TIMER_DIV5_CLOCK 0x00000004\n\n#define AVR32_TC_TCCLKS_TIMER_DIV1_CLOCK 0x00000000\n#define AVR32_TC_TCCLKS_TIMER_DIV2_CLOCK 0x00000001\n#define AVR32_TC_TCCLKS_TIMER_DIV3_CLOCK 0x00000002\n#define AVR32_TC_TCCLKS_TIMER_DIV4_CLOCK 0x00000003\n#define AVR32_TC_TCCLKS_TIMER_DIV5_CLOCK 0x00000004\n\n#define AVR32_TC_TIMER_DIV1_CLOCK 0x00000000\n#define AVR32_TC_TIMER_DIV2_CLOCK 0x00000001\n#define AVR32_TC_TIMER_DIV3_CLOCK 0x00000002\n#define AVR32_TC_TIMER_DIV4_CLOCK 0x00000003\n#define AVR32_TC_TIMER_DIV5_CLOCK 0x00000004\n\n#endif\n\n\n/*#ifdef AVR32_TC_222_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/twi_211.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3A0512\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_TWI_211_H_INCLUDED\n#define AVR32_TWI_211_H_INCLUDED\n\n#define AVR32_TWI_H_VERSION 211\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_TWI_\n - Bitfield mask: AVR32_TWI__\n - Bitfield offset: AVR32_TWI___OFFSET\n - Bitfield size: AVR32_TWI___SIZE\n - Bitfield values: AVR32_TWI___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_TWI_\n - Bitfield offset: AVR32_TWI__OFFSET\n - Bitfield size: AVR32_TWI__SIZE\n - Bitfield values: AVR32_TWI__\n - Bitfield values: AVR32_TWI_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_TWI_ARBLST 9\n#define AVR32_TWI_ARBLST_MASK 0x00000200\n#define AVR32_TWI_ARBLST_OFFSET 9\n#define AVR32_TWI_ARBLST_SIZE 1\n#define AVR32_TWI_CHDIV 8\n#define AVR32_TWI_CHDIV_MASK 0x0000ff00\n#define AVR32_TWI_CHDIV_OFFSET 8\n#define AVR32_TWI_CHDIV_SIZE 8\n#define AVR32_TWI_CKDIV 16\n#define AVR32_TWI_CKDIV_MASK 0x00070000\n#define AVR32_TWI_CKDIV_OFFSET 16\n#define AVR32_TWI_CKDIV_SIZE 3\n#define AVR32_TWI_CLDIV 0\n#define AVR32_TWI_CLDIV_MASK 0x000000ff\n#define AVR32_TWI_CLDIV_OFFSET 0\n#define AVR32_TWI_CLDIV_SIZE 8\n#define AVR32_TWI_CR 0x00000000\n#define AVR32_TWI_CR_MSDIS 3\n#define AVR32_TWI_CR_MSDIS_MASK 0x00000008\n#define AVR32_TWI_CR_MSDIS_OFFSET 3\n#define AVR32_TWI_CR_MSDIS_SIZE 1\n#define AVR32_TWI_CR_MSEN 2\n#define AVR32_TWI_CR_MSEN_MASK 0x00000004\n#define AVR32_TWI_CR_MSEN_OFFSET 2\n#define AVR32_TWI_CR_MSEN_SIZE 1\n#define AVR32_TWI_CR_START 0\n#define AVR32_TWI_CR_START_MASK 0x00000001\n#define AVR32_TWI_CR_START_OFFSET 0\n#define AVR32_TWI_CR_START_SIZE 1\n#define AVR32_TWI_CR_STOP 1\n#define AVR32_TWI_CR_STOP_MASK 0x00000002\n#define AVR32_TWI_CR_STOP_OFFSET 1\n#define AVR32_TWI_CR_STOP_SIZE 1\n#define AVR32_TWI_CR_SVDIS 5\n#define AVR32_TWI_CR_SVDIS_MASK 0x00000020\n#define AVR32_TWI_CR_SVDIS_OFFSET 5\n#define AVR32_TWI_CR_SVDIS_SIZE 1\n#define AVR32_TWI_CR_SVEN 4\n#define AVR32_TWI_CR_SVEN_MASK 0x00000010\n#define AVR32_TWI_CR_SVEN_OFFSET 4\n#define AVR32_TWI_CR_SVEN_SIZE 1\n#define AVR32_TWI_CR_SWRST 7\n#define AVR32_TWI_CR_SWRST_MASK 0x00000080\n#define AVR32_TWI_CR_SWRST_OFFSET 7\n#define AVR32_TWI_CR_SWRST_SIZE 1\n#define AVR32_TWI_CWGR 0x00000010\n#define AVR32_TWI_CWGR_CHDIV 8\n#define AVR32_TWI_CWGR_CHDIV_MASK 0x0000ff00\n#define AVR32_TWI_CWGR_CHDIV_OFFSET 8\n#define AVR32_TWI_CWGR_CHDIV_SIZE 8\n#define AVR32_TWI_CWGR_CKDIV 16\n#define AVR32_TWI_CWGR_CKDIV_MASK 0x00070000\n#define AVR32_TWI_CWGR_CKDIV_OFFSET 16\n#define AVR32_TWI_CWGR_CKDIV_SIZE 3\n#define AVR32_TWI_CWGR_CLDIV 0\n#define AVR32_TWI_CWGR_CLDIV_MASK 0x000000ff\n#define AVR32_TWI_CWGR_CLDIV_OFFSET 0\n#define AVR32_TWI_CWGR_CLDIV_SIZE 8\n#define AVR32_TWI_DADR 16\n#define AVR32_TWI_DADR_MASK 0x007f0000\n#define AVR32_TWI_DADR_OFFSET 16\n#define AVR32_TWI_DADR_SIZE 7\n#define AVR32_TWI_ENDRX 12\n#define AVR32_TWI_ENDRX_MASK 0x00001000\n#define AVR32_TWI_ENDRX_OFFSET 12\n#define AVR32_TWI_ENDRX_SIZE 1\n#define AVR32_TWI_ENDTX 13\n#define AVR32_TWI_ENDTX_MASK 0x00002000\n#define AVR32_TWI_ENDTX_OFFSET 13\n#define AVR32_TWI_ENDTX_SIZE 1\n#define AVR32_TWI_EOSACC 11\n#define AVR32_TWI_EOSACC_MASK 0x00000800\n#define AVR32_TWI_EOSACC_OFFSET 11\n#define AVR32_TWI_EOSACC_SIZE 1\n#define AVR32_TWI_GACC 5\n#define AVR32_TWI_GACC_MASK 0x00000020\n#define AVR32_TWI_GACC_OFFSET 5\n#define AVR32_TWI_GACC_SIZE 1\n#define AVR32_TWI_IADR 0x0000000c\n#define AVR32_TWI_IADRSZ 8\n#define AVR32_TWI_IADRSZ_MASK 0x00000300\n#define AVR32_TWI_IADRSZ_NO_ADDR 0x00000000\n#define AVR32_TWI_IADRSZ_OFFSET 8\n#define AVR32_TWI_IADRSZ_ONE_BYTE 0x00000001\n#define AVR32_TWI_IADRSZ_SIZE 2\n#define AVR32_TWI_IADRSZ_THREE_BYTES 0x00000003\n#define AVR32_TWI_IADRSZ_TWO_BYTES 0x00000002\n#define AVR32_TWI_IADR_IADR 0\n#define AVR32_TWI_IADR_IADR_MASK 0x00ffffff\n#define AVR32_TWI_IADR_IADR_OFFSET 0\n#define AVR32_TWI_IADR_IADR_SIZE 24\n#define AVR32_TWI_IADR_MASK 0x00ffffff\n#define AVR32_TWI_IADR_OFFSET 0\n#define AVR32_TWI_IADR_SIZE 24\n#define AVR32_TWI_IDR 0x00000028\n#define AVR32_TWI_IDR_ARBLST 9\n#define AVR32_TWI_IDR_ARBLST_MASK 0x00000200\n#define AVR32_TWI_IDR_ARBLST_OFFSET 9\n#define AVR32_TWI_IDR_ARBLST_SIZE 1\n#define AVR32_TWI_IDR_ENDRX 12\n#define AVR32_TWI_IDR_ENDRX_MASK 0x00001000\n#define AVR32_TWI_IDR_ENDRX_OFFSET 12\n#define AVR32_TWI_IDR_ENDRX_SIZE 1\n#define AVR32_TWI_IDR_ENDTX 13\n#define AVR32_TWI_IDR_ENDTX_MASK 0x00002000\n#define AVR32_TWI_IDR_ENDTX_OFFSET 13\n#define AVR32_TWI_IDR_ENDTX_SIZE 1\n#define AVR32_TWI_IDR_EOSACC 11\n#define AVR32_TWI_IDR_EOSACC_MASK 0x00000800\n#define AVR32_TWI_IDR_EOSACC_OFFSET 11\n#define AVR32_TWI_IDR_EOSACC_SIZE 1\n#define AVR32_TWI_IDR_GACC 5\n#define AVR32_TWI_IDR_GACC_MASK 0x00000020\n#define AVR32_TWI_IDR_GACC_OFFSET 5\n#define AVR32_TWI_IDR_GACC_SIZE 1\n#define AVR32_TWI_IDR_NACK 8\n#define AVR32_TWI_IDR_NACK_MASK 0x00000100\n#define AVR32_TWI_IDR_NACK_OFFSET 8\n#define AVR32_TWI_IDR_NACK_SIZE 1\n#define AVR32_TWI_IDR_OVRE 6\n#define AVR32_TWI_IDR_OVRE_MASK 0x00000040\n#define AVR32_TWI_IDR_OVRE_OFFSET 6\n#define AVR32_TWI_IDR_OVRE_SIZE 1\n#define AVR32_TWI_IDR_RXBUFF 14\n#define AVR32_TWI_IDR_RXBUFF_MASK 0x00004000\n#define AVR32_TWI_IDR_RXBUFF_OFFSET 14\n#define AVR32_TWI_IDR_RXBUFF_SIZE 1\n#define AVR32_TWI_IDR_RXRDY 1\n#define AVR32_TWI_IDR_RXRDY_MASK 0x00000002\n#define AVR32_TWI_IDR_RXRDY_OFFSET 1\n#define AVR32_TWI_IDR_RXRDY_SIZE 1\n#define AVR32_TWI_IDR_SCLWS 10\n#define AVR32_TWI_IDR_SCLWS_MASK 0x00000400\n#define AVR32_TWI_IDR_SCLWS_OFFSET 10\n#define AVR32_TWI_IDR_SCLWS_SIZE 1\n#define AVR32_TWI_IDR_SVACC 4\n#define AVR32_TWI_IDR_SVACC_MASK 0x00000010\n#define AVR32_TWI_IDR_SVACC_OFFSET 4\n#define AVR32_TWI_IDR_SVACC_SIZE 1\n#define AVR32_TWI_IDR_TXBUFE 15\n#define AVR32_TWI_IDR_TXBUFE_MASK 0x00008000\n#define AVR32_TWI_IDR_TXBUFE_OFFSET 15\n#define AVR32_TWI_IDR_TXBUFE_SIZE 1\n#define AVR32_TWI_IDR_TXCOMP 0\n#define AVR32_TWI_IDR_TXCOMP_MASK 0x00000001\n#define AVR32_TWI_IDR_TXCOMP_OFFSET 0\n#define AVR32_TWI_IDR_TXCOMP_SIZE 1\n#define AVR32_TWI_IDR_TXRDY 2\n#define AVR32_TWI_IDR_TXRDY_MASK 0x00000004\n#define AVR32_TWI_IDR_TXRDY_OFFSET 2\n#define AVR32_TWI_IDR_TXRDY_SIZE 1\n#define AVR32_TWI_IER 0x00000024\n#define AVR32_TWI_IER_ARBLST 9\n#define AVR32_TWI_IER_ARBLST_MASK 0x00000200\n#define AVR32_TWI_IER_ARBLST_OFFSET 9\n#define AVR32_TWI_IER_ARBLST_SIZE 1\n#define AVR32_TWI_IER_ENDRX 12\n#define AVR32_TWI_IER_ENDRX_MASK 0x00001000\n#define AVR32_TWI_IER_ENDRX_OFFSET 12\n#define AVR32_TWI_IER_ENDRX_SIZE 1\n#define AVR32_TWI_IER_ENDTX 13\n#define AVR32_TWI_IER_ENDTX_MASK 0x00002000\n#define AVR32_TWI_IER_ENDTX_OFFSET 13\n#define AVR32_TWI_IER_ENDTX_SIZE 1\n#define AVR32_TWI_IER_EOSACC 11\n#define AVR32_TWI_IER_EOSACC_MASK 0x00000800\n#define AVR32_TWI_IER_EOSACC_OFFSET 11\n#define AVR32_TWI_IER_EOSACC_SIZE 1\n#define AVR32_TWI_IER_GACC 5\n#define AVR32_TWI_IER_GACC_MASK 0x00000020\n#define AVR32_TWI_IER_GACC_OFFSET 5\n#define AVR32_TWI_IER_GACC_SIZE 1\n#define AVR32_TWI_IER_NACK 8\n#define AVR32_TWI_IER_NACK_MASK 0x00000100\n#define AVR32_TWI_IER_NACK_OFFSET 8\n#define AVR32_TWI_IER_NACK_SIZE 1\n#define AVR32_TWI_IER_OVRE 6\n#define AVR32_TWI_IER_OVRE_MASK 0x00000040\n#define AVR32_TWI_IER_OVRE_OFFSET 6\n#define AVR32_TWI_IER_OVRE_SIZE 1\n#define AVR32_TWI_IER_RXBUFF 14\n#define AVR32_TWI_IER_RXBUFF_MASK 0x00004000\n#define AVR32_TWI_IER_RXBUFF_OFFSET 14\n#define AVR32_TWI_IER_RXBUFF_SIZE 1\n#define AVR32_TWI_IER_RXRDY 1\n#define AVR32_TWI_IER_RXRDY_MASK 0x00000002\n#define AVR32_TWI_IER_RXRDY_OFFSET 1\n#define AVR32_TWI_IER_RXRDY_SIZE 1\n#define AVR32_TWI_IER_SCLWS 10\n#define AVR32_TWI_IER_SCLWS_MASK 0x00000400\n#define AVR32_TWI_IER_SCLWS_OFFSET 10\n#define AVR32_TWI_IER_SCLWS_SIZE 1\n#define AVR32_TWI_IER_SVACC 4\n#define AVR32_TWI_IER_SVACC_MASK 0x00000010\n#define AVR32_TWI_IER_SVACC_OFFSET 4\n#define AVR32_TWI_IER_SVACC_SIZE 1\n#define AVR32_TWI_IER_TXBUFE 15\n#define AVR32_TWI_IER_TXBUFE_MASK 0x00008000\n#define AVR32_TWI_IER_TXBUFE_OFFSET 15\n#define AVR32_TWI_IER_TXBUFE_SIZE 1\n#define AVR32_TWI_IER_TXCOMP 0\n#define AVR32_TWI_IER_TXCOMP_MASK 0x00000001\n#define AVR32_TWI_IER_TXCOMP_OFFSET 0\n#define AVR32_TWI_IER_TXCOMP_SIZE 1\n#define AVR32_TWI_IER_TXRDY 2\n#define AVR32_TWI_IER_TXRDY_MASK 0x00000004\n#define AVR32_TWI_IER_TXRDY_OFFSET 2\n#define AVR32_TWI_IER_TXRDY_SIZE 1\n#define AVR32_TWI_IMR 0x0000002c\n#define AVR32_TWI_IMR_ARBLST 9\n#define AVR32_TWI_IMR_ARBLST_MASK 0x00000200\n#define AVR32_TWI_IMR_ARBLST_OFFSET 9\n#define AVR32_TWI_IMR_ARBLST_SIZE 1\n#define AVR32_TWI_IMR_ENDRX 12\n#define AVR32_TWI_IMR_ENDRX_MASK 0x00001000\n#define AVR32_TWI_IMR_ENDRX_OFFSET 12\n#define AVR32_TWI_IMR_ENDRX_SIZE 1\n#define AVR32_TWI_IMR_ENDTX 13\n#define AVR32_TWI_IMR_ENDTX_MASK 0x00002000\n#define AVR32_TWI_IMR_ENDTX_OFFSET 13\n#define AVR32_TWI_IMR_ENDTX_SIZE 1\n#define AVR32_TWI_IMR_EOSACC 11\n#define AVR32_TWI_IMR_EOSACC_MASK 0x00000800\n#define AVR32_TWI_IMR_EOSACC_OFFSET 11\n#define AVR32_TWI_IMR_EOSACC_SIZE 1\n#define AVR32_TWI_IMR_GACC 5\n#define AVR32_TWI_IMR_GACC_MASK 0x00000020\n#define AVR32_TWI_IMR_GACC_OFFSET 5\n#define AVR32_TWI_IMR_GACC_SIZE 1\n#define AVR32_TWI_IMR_NACK 8\n#define AVR32_TWI_IMR_NACK_MASK 0x00000100\n#define AVR32_TWI_IMR_NACK_OFFSET 8\n#define AVR32_TWI_IMR_NACK_SIZE 1\n#define AVR32_TWI_IMR_OVRE 6\n#define AVR32_TWI_IMR_OVRE_MASK 0x00000040\n#define AVR32_TWI_IMR_OVRE_OFFSET 6\n#define AVR32_TWI_IMR_OVRE_SIZE 1\n#define AVR32_TWI_IMR_RXBUFF 14\n#define AVR32_TWI_IMR_RXBUFF_MASK 0x00004000\n#define AVR32_TWI_IMR_RXBUFF_OFFSET 14\n#define AVR32_TWI_IMR_RXBUFF_SIZE 1\n#define AVR32_TWI_IMR_RXRDY 1\n#define AVR32_TWI_IMR_RXRDY_MASK 0x00000002\n#define AVR32_TWI_IMR_RXRDY_OFFSET 1\n#define AVR32_TWI_IMR_RXRDY_SIZE 1\n#define AVR32_TWI_IMR_SCLWS 10\n#define AVR32_TWI_IMR_SCLWS_MASK 0x00000400\n#define AVR32_TWI_IMR_SCLWS_OFFSET 10\n#define AVR32_TWI_IMR_SCLWS_SIZE 1\n#define AVR32_TWI_IMR_SVACC 4\n#define AVR32_TWI_IMR_SVACC_MASK 0x00000010\n#define AVR32_TWI_IMR_SVACC_OFFSET 4\n#define AVR32_TWI_IMR_SVACC_SIZE 1\n#define AVR32_TWI_IMR_TXBUFE 15\n#define AVR32_TWI_IMR_TXBUFE_MASK 0x00008000\n#define AVR32_TWI_IMR_TXBUFE_OFFSET 15\n#define AVR32_TWI_IMR_TXBUFE_SIZE 1\n#define AVR32_TWI_IMR_TXCOMP 0\n#define AVR32_TWI_IMR_TXCOMP_MASK 0x00000001\n#define AVR32_TWI_IMR_TXCOMP_OFFSET 0\n#define AVR32_TWI_IMR_TXCOMP_SIZE 1\n#define AVR32_TWI_IMR_TXRDY 2\n#define AVR32_TWI_IMR_TXRDY_MASK 0x00000004\n#define AVR32_TWI_IMR_TXRDY_OFFSET 2\n#define AVR32_TWI_IMR_TXRDY_SIZE 1\n#define AVR32_TWI_MMR 0x00000004\n#define AVR32_TWI_MMR_DADR 16\n#define AVR32_TWI_MMR_DADR_MASK 0x007f0000\n#define AVR32_TWI_MMR_DADR_OFFSET 16\n#define AVR32_TWI_MMR_DADR_SIZE 7\n#define AVR32_TWI_MMR_IADRSZ 8\n#define AVR32_TWI_MMR_IADRSZ_MASK 0x00000300\n#define AVR32_TWI_MMR_IADRSZ_NO_ADDR 0x00000000\n#define AVR32_TWI_MMR_IADRSZ_OFFSET 8\n#define AVR32_TWI_MMR_IADRSZ_ONE_BYTE 0x00000001\n#define AVR32_TWI_MMR_IADRSZ_SIZE 2\n#define AVR32_TWI_MMR_IADRSZ_THREE_BYTES 0x00000003\n#define AVR32_TWI_MMR_IADRSZ_TWO_BYTES 0x00000002\n#define AVR32_TWI_MMR_MREAD 12\n#define AVR32_TWI_MMR_MREAD_MASK 0x00001000\n#define AVR32_TWI_MMR_MREAD_OFFSET 12\n#define AVR32_TWI_MMR_MREAD_SIZE 1\n#define AVR32_TWI_MREAD 12\n#define AVR32_TWI_MREAD_MASK 0x00001000\n#define AVR32_TWI_MREAD_OFFSET 12\n#define AVR32_TWI_MREAD_SIZE 1\n#define AVR32_TWI_MSDIS 3\n#define AVR32_TWI_MSDIS_MASK 0x00000008\n#define AVR32_TWI_MSDIS_OFFSET 3\n#define AVR32_TWI_MSDIS_SIZE 1\n#define AVR32_TWI_MSEN 2\n#define AVR32_TWI_MSEN_MASK 0x00000004\n#define AVR32_TWI_MSEN_OFFSET 2\n#define AVR32_TWI_MSEN_SIZE 1\n#define AVR32_TWI_NACK 8\n#define AVR32_TWI_NACK_MASK 0x00000100\n#define AVR32_TWI_NACK_OFFSET 8\n#define AVR32_TWI_NACK_SIZE 1\n#define AVR32_TWI_NO_ADDR 0x00000000\n#define AVR32_TWI_ONE_BYTE 0x00000001\n#define AVR32_TWI_OVRE 6\n#define AVR32_TWI_OVRE_MASK 0x00000040\n#define AVR32_TWI_OVRE_OFFSET 6\n#define AVR32_TWI_OVRE_SIZE 1\n#define AVR32_TWI_RHR 0x00000030\n#define AVR32_TWI_RHR_RXDATA 0\n#define AVR32_TWI_RHR_RXDATA_MASK 0x000000ff\n#define AVR32_TWI_RHR_RXDATA_OFFSET 0\n#define AVR32_TWI_RHR_RXDATA_SIZE 8\n#define AVR32_TWI_RXBUFF 14\n#define AVR32_TWI_RXBUFF_MASK 0x00004000\n#define AVR32_TWI_RXBUFF_OFFSET 14\n#define AVR32_TWI_RXBUFF_SIZE 1\n#define AVR32_TWI_RXDATA 0\n#define AVR32_TWI_RXDATA_MASK 0x000000ff\n#define AVR32_TWI_RXDATA_OFFSET 0\n#define AVR32_TWI_RXDATA_SIZE 8\n#define AVR32_TWI_RXRDY 1\n#define AVR32_TWI_RXRDY_MASK 0x00000002\n#define AVR32_TWI_RXRDY_OFFSET 1\n#define AVR32_TWI_RXRDY_SIZE 1\n#define AVR32_TWI_SADR 16\n#define AVR32_TWI_SADR_MASK 0x007f0000\n#define AVR32_TWI_SADR_OFFSET 16\n#define AVR32_TWI_SADR_SIZE 7\n#define AVR32_TWI_SCLWS 10\n#define AVR32_TWI_SCLWS_MASK 0x00000400\n#define AVR32_TWI_SCLWS_OFFSET 10\n#define AVR32_TWI_SCLWS_SIZE 1\n#define AVR32_TWI_SMR 0x00000008\n#define AVR32_TWI_SMR_SADR 16\n#define AVR32_TWI_SMR_SADR_MASK 0x007f0000\n#define AVR32_TWI_SMR_SADR_OFFSET 16\n#define AVR32_TWI_SMR_SADR_SIZE 7\n#define AVR32_TWI_SR 0x00000020\n#define AVR32_TWI_SR_ARBLST 9\n#define AVR32_TWI_SR_ARBLST_MASK 0x00000200\n#define AVR32_TWI_SR_ARBLST_OFFSET 9\n#define AVR32_TWI_SR_ARBLST_SIZE 1\n#define AVR32_TWI_SR_ENDRX 12\n#define AVR32_TWI_SR_ENDRX_MASK 0x00001000\n#define AVR32_TWI_SR_ENDRX_OFFSET 12\n#define AVR32_TWI_SR_ENDRX_SIZE 1\n#define AVR32_TWI_SR_ENDTX 13\n#define AVR32_TWI_SR_ENDTX_MASK 0x00002000\n#define AVR32_TWI_SR_ENDTX_OFFSET 13\n#define AVR32_TWI_SR_ENDTX_SIZE 1\n#define AVR32_TWI_SR_EOSACC 11\n#define AVR32_TWI_SR_EOSACC_MASK 0x00000800\n#define AVR32_TWI_SR_EOSACC_OFFSET 11\n#define AVR32_TWI_SR_EOSACC_SIZE 1\n#define AVR32_TWI_SR_GACC 5\n#define AVR32_TWI_SR_GACC_MASK 0x00000020\n#define AVR32_TWI_SR_GACC_OFFSET 5\n#define AVR32_TWI_SR_GACC_SIZE 1\n#define AVR32_TWI_SR_NACK 8\n#define AVR32_TWI_SR_NACK_MASK 0x00000100\n#define AVR32_TWI_SR_NACK_OFFSET 8\n#define AVR32_TWI_SR_NACK_SIZE 1\n#define AVR32_TWI_SR_OVRE 6\n#define AVR32_TWI_SR_OVRE_MASK 0x00000040\n#define AVR32_TWI_SR_OVRE_OFFSET 6\n#define AVR32_TWI_SR_OVRE_SIZE 1\n#define AVR32_TWI_SR_RXBUFF 14\n#define AVR32_TWI_SR_RXBUFF_MASK 0x00004000\n#define AVR32_TWI_SR_RXBUFF_OFFSET 14\n#define AVR32_TWI_SR_RXBUFF_SIZE 1\n#define AVR32_TWI_SR_RXRDY 1\n#define AVR32_TWI_SR_RXRDY_MASK 0x00000002\n#define AVR32_TWI_SR_RXRDY_OFFSET 1\n#define AVR32_TWI_SR_RXRDY_SIZE 1\n#define AVR32_TWI_SR_SCLWS 10\n#define AVR32_TWI_SR_SCLWS_MASK 0x00000400\n#define AVR32_TWI_SR_SCLWS_OFFSET 10\n#define AVR32_TWI_SR_SCLWS_SIZE 1\n#define AVR32_TWI_SR_SVACC 4\n#define AVR32_TWI_SR_SVACC_MASK 0x00000010\n#define AVR32_TWI_SR_SVACC_OFFSET 4\n#define AVR32_TWI_SR_SVACC_SIZE 1\n#define AVR32_TWI_SR_SVREAD 3\n#define AVR32_TWI_SR_SVREAD_MASK 0x00000008\n#define AVR32_TWI_SR_SVREAD_OFFSET 3\n#define AVR32_TWI_SR_SVREAD_SIZE 1\n#define AVR32_TWI_SR_TXBUFE 15\n#define AVR32_TWI_SR_TXBUFE_MASK 0x00008000\n#define AVR32_TWI_SR_TXBUFE_OFFSET 15\n#define AVR32_TWI_SR_TXBUFE_SIZE 1\n#define AVR32_TWI_SR_TXCOMP 0\n#define AVR32_TWI_SR_TXCOMP_MASK 0x00000001\n#define AVR32_TWI_SR_TXCOMP_OFFSET 0\n#define AVR32_TWI_SR_TXCOMP_SIZE 1\n#define AVR32_TWI_SR_TXRDY 2\n#define AVR32_TWI_SR_TXRDY_MASK 0x00000004\n#define AVR32_TWI_SR_TXRDY_OFFSET 2\n#define AVR32_TWI_SR_TXRDY_SIZE 1\n#define AVR32_TWI_START 0\n#define AVR32_TWI_START_MASK 0x00000001\n#define AVR32_TWI_START_OFFSET 0\n#define AVR32_TWI_START_SIZE 1\n#define AVR32_TWI_STOP 1\n#define AVR32_TWI_STOP_MASK 0x00000002\n#define AVR32_TWI_STOP_OFFSET 1\n#define AVR32_TWI_STOP_SIZE 1\n#define AVR32_TWI_SVACC 4\n#define AVR32_TWI_SVACC_MASK 0x00000010\n#define AVR32_TWI_SVACC_OFFSET 4\n#define AVR32_TWI_SVACC_SIZE 1\n#define AVR32_TWI_SVDIS 5\n#define AVR32_TWI_SVDIS_MASK 0x00000020\n#define AVR32_TWI_SVDIS_OFFSET 5\n#define AVR32_TWI_SVDIS_SIZE 1\n#define AVR32_TWI_SVEN 4\n#define AVR32_TWI_SVEN_MASK 0x00000010\n#define AVR32_TWI_SVEN_OFFSET 4\n#define AVR32_TWI_SVEN_SIZE 1\n#define AVR32_TWI_SVREAD 3\n#define AVR32_TWI_SVREAD_MASK 0x00000008\n#define AVR32_TWI_SVREAD_OFFSET 3\n#define AVR32_TWI_SVREAD_SIZE 1\n#define AVR32_TWI_SWRST 7\n#define AVR32_TWI_SWRST_MASK 0x00000080\n#define AVR32_TWI_SWRST_OFFSET 7\n#define AVR32_TWI_SWRST_SIZE 1\n#define AVR32_TWI_THR 0x00000034\n#define AVR32_TWI_THREE_BYTES 0x00000003\n#define AVR32_TWI_THR_TXDATA 0\n#define AVR32_TWI_THR_TXDATA_MASK 0x000000ff\n#define AVR32_TWI_THR_TXDATA_OFFSET 0\n#define AVR32_TWI_THR_TXDATA_SIZE 8\n#define AVR32_TWI_TWO_BYTES 0x00000002\n#define AVR32_TWI_TXBUFE 15\n#define AVR32_TWI_TXBUFE_MASK 0x00008000\n#define AVR32_TWI_TXBUFE_OFFSET 15\n#define AVR32_TWI_TXBUFE_SIZE 1\n#define AVR32_TWI_TXCOMP 0\n#define AVR32_TWI_TXCOMP_MASK 0x00000001\n#define AVR32_TWI_TXCOMP_OFFSET 0\n#define AVR32_TWI_TXCOMP_SIZE 1\n#define AVR32_TWI_TXDATA 0\n#define AVR32_TWI_TXDATA_MASK 0x000000ff\n#define AVR32_TWI_TXDATA_OFFSET 0\n#define AVR32_TWI_TXDATA_SIZE 8\n#define AVR32_TWI_TXRDY 2\n#define AVR32_TWI_TXRDY_MASK 0x00000004\n#define AVR32_TWI_TXRDY_OFFSET 2\n#define AVR32_TWI_TXRDY_SIZE 1\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_twi_cr_t {\n unsigned int :24;\n unsigned int swrst : 1;\n unsigned int : 1;\n unsigned int svdis : 1;\n unsigned int sven : 1;\n unsigned int msdis : 1;\n unsigned int msen : 1;\n unsigned int stop : 1;\n unsigned int start : 1;\n} avr32_twi_cr_t;\n\n\n\ntypedef struct avr32_twi_mmr_t {\n unsigned int : 9;\n unsigned int dadr : 7;\n unsigned int : 3;\n unsigned int mread : 1;\n unsigned int : 2;\n unsigned int iadrsz : 2;\n unsigned int : 8;\n} avr32_twi_mmr_t;\n\n\n\ntypedef struct avr32_twi_smr_t {\n unsigned int : 9;\n unsigned int sadr : 7;\n unsigned int :16;\n} avr32_twi_smr_t;\n\n\n\ntypedef struct avr32_twi_iadr_t {\n unsigned int : 8;\n unsigned int iadr :24;\n} avr32_twi_iadr_t;\n\n\n\ntypedef struct avr32_twi_cwgr_t {\n unsigned int :13;\n unsigned int ckdiv : 3;\n unsigned int chdiv : 8;\n unsigned int cldiv : 8;\n} avr32_twi_cwgr_t;\n\n\n\ntypedef struct avr32_twi_sr_t {\n unsigned int :16;\n unsigned int txbufe : 1;\n unsigned int rxbuff : 1;\n unsigned int endtx : 1;\n unsigned int endrx : 1;\n unsigned int eosacc : 1;\n unsigned int sclws : 1;\n unsigned int arblst : 1;\n unsigned int nack : 1;\n unsigned int : 1;\n unsigned int ovre : 1;\n unsigned int gacc : 1;\n unsigned int svacc : 1;\n unsigned int svread : 1;\n unsigned int txrdy : 1;\n unsigned int rxrdy : 1;\n unsigned int txcomp : 1;\n} avr32_twi_sr_t;\n\n\n\ntypedef struct avr32_twi_ier_t {\n unsigned int :16;\n unsigned int txbufe : 1;\n unsigned int rxbuff : 1;\n unsigned int endtx : 1;\n unsigned int endrx : 1;\n unsigned int eosacc : 1;\n unsigned int sclws : 1;\n unsigned int arblst : 1;\n unsigned int nack : 1;\n unsigned int : 1;\n unsigned int ovre : 1;\n unsigned int gacc : 1;\n unsigned int svacc : 1;\n unsigned int : 1;\n unsigned int txrdy : 1;\n unsigned int rxrdy : 1;\n unsigned int txcomp : 1;\n} avr32_twi_ier_t;\n\n\n\ntypedef struct avr32_twi_idr_t {\n unsigned int :16;\n unsigned int txbufe : 1;\n unsigned int rxbuff : 1;\n unsigned int endtx : 1;\n unsigned int endrx : 1;\n unsigned int eosacc : 1;\n unsigned int sclws : 1;\n unsigned int arblst : 1;\n unsigned int nack : 1;\n unsigned int : 1;\n unsigned int ovre : 1;\n unsigned int gacc : 1;\n unsigned int svacc : 1;\n unsigned int : 1;\n unsigned int txrdy : 1;\n unsigned int rxrdy : 1;\n unsigned int txcomp : 1;\n} avr32_twi_idr_t;\n\n\n\ntypedef struct avr32_twi_imr_t {\n unsigned int :16;\n unsigned int txbufe : 1;\n unsigned int rxbuff : 1;\n unsigned int endtx : 1;\n unsigned int endrx : 1;\n unsigned int eosacc : 1;\n unsigned int sclws : 1;\n unsigned int arblst : 1;\n unsigned int nack : 1;\n unsigned int : 1;\n unsigned int ovre : 1;\n unsigned int gacc : 1;\n unsigned int svacc : 1;\n unsigned int : 1;\n unsigned int txrdy : 1;\n unsigned int rxrdy : 1;\n unsigned int txcomp : 1;\n} avr32_twi_imr_t;\n\n\n\ntypedef struct avr32_twi_rhr_t {\n unsigned int :24;\n unsigned int rxdata : 8;\n} avr32_twi_rhr_t;\n\n\n\ntypedef struct avr32_twi_thr_t {\n unsigned int :24;\n unsigned int txdata : 8;\n} avr32_twi_thr_t;\n\n\n\ntypedef struct avr32_twi_t {\n union {\n unsigned long cr ;//0x0000\n avr32_twi_cr_t CR ;\n };\n union {\n unsigned long mmr ;//0x0004\n avr32_twi_mmr_t MMR ;\n };\n union {\n unsigned long smr ;//0x0008\n avr32_twi_smr_t SMR ;\n };\n union {\n unsigned long iadr ;//0x000c\n avr32_twi_iadr_t IADR ;\n };\n union {\n unsigned long cwgr ;//0x0010\n avr32_twi_cwgr_t CWGR ;\n };\n unsigned int :32 ;//0x0014\n unsigned int :32 ;//0x0018\n unsigned int :32 ;//0x001c\n union {\n const unsigned long sr ;//0x0020\n const avr32_twi_sr_t SR ;\n };\n union {\n unsigned long ier ;//0x0024\n avr32_twi_ier_t IER ;\n };\n union {\n unsigned long idr ;//0x0028\n avr32_twi_idr_t IDR ;\n };\n union {\n const unsigned long imr ;//0x002c\n const avr32_twi_imr_t IMR ;\n };\n union {\n const unsigned long rhr ;//0x0030\n const avr32_twi_rhr_t RHR ;\n };\n union {\n unsigned long thr ;//0x0034\n avr32_twi_thr_t THR ;\n };\n} avr32_twi_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n/*#ifdef AVR32_TWI_211_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/uc3b0256.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2006-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n * Model : UC3B0256\n * Revision : $Revision: 74373 $\n * Checkin Date : $Date: 2010-05-06 07:18:58 +0200 (Thu, 06 May 2010) $\n *\n ****************************************************************************/\n#ifndef AVR32_UC3B0256_H_INCLUDED\n#define AVR32_UC3B0256_H_INCLUDED\n\n\n/* Core */\n//#include \"avr32/core_sc0_130.h\"\n/* OCD */\n//#include \"avr32/ocd_s0_130.h\"\n\n/* CORE */ \n#define AVR32_CORE_CLK_CPU_COUNT 16\n#define AVR32_CORE_COMPARE_IRQ 0\n#define AVR32_CORE_SCAN_CHAIN_MSB 9\n#define AVR32_CORE_SCAN_CLOCK_MSB 1\n\n\n/* OCD */ \n#define AVR32_OCD_CLK_CPU 1\n\n/* Memories */\n#define AVR32_FLASH_ADDRESS 0x80000000\n#define AVR32_FLASH_SIZE 0x00040000\n#define AVR32_FLASH ((unsigned char *)AVR32_FLASH_ADDRESS)\n#define AVR32_SRAM_ADDRESS 0x00000000\n#define AVR32_SRAM_SIZE 0x00008000\n#define AVR32_SRAM ((unsigned char *)AVR32_SRAM_ADDRESS)\n#define AVR32_USBB_SLAVE_ADDRESS 0xD0000000\n#define AVR32_USBB_SLAVE_SIZE 0x00800000\n#define AVR32_USBB_SLAVE ((unsigned char *)AVR32_USBB_SLAVE_ADDRESS)\n\n/* Interrupt Controller */\n#define AVR32_INTC_NUM 1\n#define AVR32_INTC_ADDRESS 0xFFFF0800\n#define AVR32_INTC (*((volatile avr32_intc_t*)AVR32_INTC_ADDRESS))\n#define AVR32_INTC_CLK_PBA 64\n#define AVR32_INTC_NUM_INT_GRPS 18\n#define AVR32_INTC_NUM_IRQS_PER_GRP0 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP1 11\n#define AVR32_INTC_NUM_IRQS_PER_GRP10 0\n#define AVR32_INTC_NUM_IRQS_PER_GRP11 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP12 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP13 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP14 3\n#define AVR32_INTC_NUM_IRQS_PER_GRP15 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP16 0\n#define AVR32_INTC_NUM_IRQS_PER_GRP17 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP2 6\n#define AVR32_INTC_NUM_IRQS_PER_GRP3 7\n#define AVR32_INTC_NUM_IRQS_PER_GRP4 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP5 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP6 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP7 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP8 0\n#define AVR32_INTC_NUM_IRQS_PER_GRP9 1\n#define AVR32_INTC_NUM_NMI 1\n\n//#include \"avr32/intc_101.h\"\n\n\n/* ADC */\n#define AVR32_ADC_NUM 1\n\n/* ADC */ \n#define AVR32_ADC_ADDRESS 0xFFFF3C00\n#define AVR32_ADC (*((volatile avr32_adc_t*)AVR32_ADC_ADDRESS))\n#define AVR32_ADC_CLK_PBA 68\n#define AVR32_ADC_IRQ 480\n#define AVR32_ADC_CHANNELS_MSB 7\n#define AVR32_ADC_DATA_MSB 9\n#define AVR32_ADC_AD_0_PIN 3\n#define AVR32_ADC_AD_0_FUNCTION 0\n#define AVR32_ADC_AD_1_PIN 4\n#define AVR32_ADC_AD_1_FUNCTION 0\n#define AVR32_ADC_AD_6_PIN 30\n#define AVR32_ADC_AD_6_FUNCTION 0\n#define AVR32_ADC_AD_7_PIN 31\n#define AVR32_ADC_AD_7_FUNCTION 0\n#define AVR32_ADC_AD_2_PIN 5\n#define AVR32_ADC_AD_2_FUNCTION 1\n#define AVR32_ADC_AD_3_PIN 6\n#define AVR32_ADC_AD_3_FUNCTION 1\n#define AVR32_ADC_AD_4_PIN 7\n#define AVR32_ADC_AD_4_FUNCTION 1\n#define AVR32_ADC_AD_5_PIN 8\n#define AVR32_ADC_AD_5_FUNCTION 1\n#define AVR32_ADC_TEST_CLK_0_PIN 13\n#define AVR32_ADC_TEST_DATA_0_PIN 17\n#define AVR32_ADC_TEST_DATA_1_PIN 19\n#define AVR32_ADC_TEST_DATA_2_PIN 20\n#define AVR32_ADC_TEST_DATA_3_PIN 21\n#define AVR32_ADC_TEST_DATA_4_PIN 22\n#define AVR32_ADC_TEST_DATA_5_PIN 23\n#define AVR32_ADC_TEST_DATA_6_PIN 24\n#define AVR32_ADC_TEST_DATA_7_PIN 25\n#define AVR32_ADC_TEST_DATA_8_PIN 26\n#define AVR32_ADC_TEST_DATA_9_PIN 27\n#define AVR32_ADC_TEST_EOC_0_PIN 12\n#define AVR32_ADC_TEST_ONAD_0_PIN 11\n#define AVR32_ADC_TEST_ONSAR_0_PIN 10\n#define AVR32_ADC_TEST_SEL_0_PIN 14\n#define AVR32_ADC_TEST_SEL_1_PIN 15\n#define AVR32_ADC_TEST_SEL_2_PIN 16\n#define AVR32_ADC_TEST_START_0_PIN 9\n#define AVR32_ADC_TRIGGER_0_PIN 22\n#define AVR32_ADC_TRIGGER_0_FUNCTION 2\n\n#include \"avr32/adc_200.h\"\n\n\n/* EIC */\n#define AVR32_EIC_NUM 1\n\n/* EIC */ \n#define AVR32_EIC_ADDRESS 0xFFFF0D80\n#define AVR32_EIC (*((volatile avr32_eic_t*)AVR32_EIC_ADDRESS))\n#define AVR32_EIC_CLK_PBA 67\n#define AVR32_EIC_IRQ_0 32\n#define AVR32_EIC_IRQ_1 33\n#define AVR32_EIC_IRQ_2 34\n#define AVR32_EIC_IRQ_3 35\n#define AVR32_EIC_IRQ_4 36\n#define AVR32_EIC_IRQ_5 37\n#define AVR32_EIC_IRQ_6 38\n#define AVR32_EIC_IRQ_7 39\n#define AVR32_EIC_INT_MSB 8\n#define AVR32_EIC_SCAN_MSB 7\n#define AVR32_EIC_STD_NUM 8\n#define AVR32_EIC_EXTINT_0_PIN 5\n#define AVR32_EIC_EXTINT_0_FUNCTION 0\n#define AVR32_EIC_EXTINT_1_PIN 6\n#define AVR32_EIC_EXTINT_1_FUNCTION 0\n#define AVR32_EIC_EXTINT_8_PIN 13\n#define AVR32_EIC_EXTINT_8_FUNCTION 0\n#define AVR32_EIC_EXTINT_6_PIN 34\n#define AVR32_EIC_EXTINT_6_FUNCTION 0\n#define AVR32_EIC_EXTINT_7_PIN 35\n#define AVR32_EIC_EXTINT_7_FUNCTION 0\n#define AVR32_EIC_EXTINT_2_PIN 14\n#define AVR32_EIC_EXTINT_2_FUNCTION 2\n#define AVR32_EIC_EXTINT_3_PIN 23\n#define AVR32_EIC_EXTINT_3_FUNCTION 2\n#define AVR32_EIC_EXTINT_4_PIN 24\n#define AVR32_EIC_EXTINT_4_FUNCTION 2\n#define AVR32_EIC_EXTINT_5_PIN 25\n#define AVR32_EIC_EXTINT_5_FUNCTION 2\n#define AVR32_EIC_SCAN_0_PIN 30\n#define AVR32_EIC_SCAN_0_FUNCTION 1\n#define AVR32_EIC_SCAN_1_PIN 31\n#define AVR32_EIC_SCAN_1_FUNCTION 1\n#define AVR32_EIC_SCAN_2_PIN 32\n#define AVR32_EIC_SCAN_2_FUNCTION 1\n#define AVR32_EIC_SCAN_3_PIN 33\n#define AVR32_EIC_SCAN_3_FUNCTION 1\n#define AVR32_EIC_SCAN_4_PIN 38\n#define AVR32_EIC_SCAN_4_FUNCTION 2\n#define AVR32_EIC_SCAN_5_PIN 39\n#define AVR32_EIC_SCAN_5_FUNCTION 2\n#define AVR32_EIC_SCAN_6_PIN 40\n#define AVR32_EIC_SCAN_6_FUNCTION 2\n#define AVR32_EIC_SCAN_7_PIN 41\n#define AVR32_EIC_SCAN_7_FUNCTION 2\n\n//#include \"avr32/eic_230.h\"\n\n\n/* FLASHC */\n#define AVR32_FLASHC_NUM 1\n\n/* FLASHC */ \n#define AVR32_FLASHC_ADDRESS 0xFFFE1400\n#define AVR32_FLASHC (*((volatile avr32_flashc_t*)AVR32_FLASHC_ADDRESS))\n#define AVR32_FLASHC_CLK_HSB 32\n#define AVR32_FLASHC_CLK_PBB 98\n#define AVR32_FLASHC_IRQ 128\n#define AVR32_FLASHC_FLASH_SIZE 262144\n#define AVR32_FLASHC_FWS_0_MAX_FREQ 33000000\n#define AVR32_FLASHC_FWS_1_MAX_FREQ 60000000\n#define AVR32_FLASHC_GPF_NUM 32\n#define AVR32_FLASHC_PAGES_PR_REGION 32\n#define AVR32_FLASHC_PAGE_SIZE 512\n#define AVR32_FLASHC_USER_PAGE ((volatile unsigned char *)AVR32_FLASHC_USER_PAGE_ADDRESS)\n#define AVR32_FLASHC_USER_PAGE_ADDRESS 0x80800000\n#define AVR32_FLASHC_USER_PAGE_SIZE 512\n#define AVR32_FLASHC_BODEN 27\n#define AVR32_FLASHC_BODEN_MASK 0x18000000\n#define AVR32_FLASHC_BODEN_OFFSET 27\n#define AVR32_FLASHC_BODEN_SIZE 2\n#define AVR32_FLASHC_BODHYST 26\n#define AVR32_FLASHC_BODHYST_MASK 0x04000000\n#define AVR32_FLASHC_BODHYST_OFFSET 26\n#define AVR32_FLASHC_BODHYST_SIZE 1\n#define AVR32_FLASHC_BODLEVEL 20\n#define AVR32_FLASHC_BODLEVEL_MASK 0x03F00000\n#define AVR32_FLASHC_BODLEVEL_OFFSET 20\n#define AVR32_FLASHC_BODLEVEL_SIZE 6\n#define AVR32_FLASHC_FGPFRLO_BODEN 27\n#define AVR32_FLASHC_FGPFRLO_BODEN_MASK 0x18000000\n#define AVR32_FLASHC_FGPFRLO_BODEN_OFFSET 27\n#define AVR32_FLASHC_FGPFRLO_BODEN_SIZE 2\n#define AVR32_FLASHC_FGPFRLO_BODHYST 26\n#define AVR32_FLASHC_FGPFRLO_BODHYST_MASK 0x04000000\n#define AVR32_FLASHC_FGPFRLO_BODHYST_OFFSET 26\n#define AVR32_FLASHC_FGPFRLO_BODHYST_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_BODLEVEL 20\n#define AVR32_FLASHC_FGPFRLO_BODLEVEL_MASK 0x03F00000\n#define AVR32_FLASHC_FGPFRLO_BODLEVEL_OFFSET 20\n#define AVR32_FLASHC_FGPFRLO_BODLEVEL_SIZE 6\n#define AVR32_FLASHC_EXTCLK_0_PIN 3\n#define AVR32_FLASHC_FLASH_OBS_0_PIN 3\n#define AVR32_FLASHC_FLASH_OBS_1_PIN 4\n#define AVR32_FLASHC_FLASH_OBS_2_PIN 5\n#define AVR32_FLASHC_FLASH_OBS_3_PIN 6\n#define AVR32_FLASHC_FLASH_OBS_4_PIN 9\n#define AVR32_FLASHC_FLASH_OBS_5_PIN 10\n#define AVR32_FLASHC_FLASH_OBS_6_PIN 11\n#define AVR32_FLASHC_FLASH_OBS_7_PIN 12\n#define AVR32_FLASHC_FLASH_OBS_8_PIN 13\n#define AVR32_FLASHC_FLASH_OBS_9_PIN 14\n#define AVR32_FLASHC_FLASH_OBS_10_PIN 15\n#define AVR32_FLASHC_FLASH_OBS_11_PIN 16\n#define AVR32_FLASHC_FLASH_OBS_12_PIN 17\n#define AVR32_FLASHC_FLASH_OBS_13_PIN 20\n#define AVR32_FLASHC_FLASH_OBS_14_PIN 21\n#define AVR32_FLASHC_FLASH_OBS_15_PIN 22\n#define AVR32_FLASHC_FLASH_OBS_16_PIN 23\n#define AVR32_FLASHC_FLASH_OBS_17_PIN 24\n#define AVR32_FLASHC_FLASH_OBS_18_PIN 25\n#define AVR32_FLASHC_FLASH_OBS_19_PIN 26\n#define AVR32_FLASHC_FLASH_OBS_20_PIN 27\n#define AVR32_FLASHC_LATDEL_0_PIN 7\n#define AVR32_FLASHC_LATDELCLK_0_PIN 8\n\n//#include \"avr32/flashc_200.h\"\n\n\n/* FREQM */\n#define AVR32_FREQM_NUM 1\n\n/* FREQM */ \n#define AVR32_FREQM_ADDRESS 0xFFFF0D50\n#define AVR32_FREQM (*((volatile avr32_freqm_t*)AVR32_FREQM_ADDRESS))\n#define AVR32_FREQM_IRQ 42\n#define AVR32_FREQM_REFSEL_BITS 1\n\n//#include \"avr32/freqm_230.h\"\n\n\n/* GPIO */\n#define AVR32_GPIO_NUM 1\n\n/* GPIO */ \n#define AVR32_GPIO_ADDRESS 0xFFFF1000\n#define AVR32_GPIO (*((volatile avr32_gpio_t*)AVR32_GPIO_ADDRESS))\n#define AVR32_GPIO_LOCAL_ADDRESS 0x40000000\n#define AVR32_GPIO_LOCAL (*((volatile avr32_gpio_local_t*)AVR32_GPIO_LOCAL_ADDRESS))\n#define AVR32_GPIO_CLK_PBA 65\n#define AVR32_GPIO_IRQ_0 64\n#define AVR32_GPIO_IRQ_1 65\n#define AVR32_GPIO_IRQ_2 66\n#define AVR32_GPIO_IRQ_3 67\n#define AVR32_GPIO_IRQ_4 68\n#define AVR32_GPIO_IRQ_5 69\n#define AVR32_GPIO_GFER_DEFAULT_VAL \"44'b11111111111111111111111111111111111111111111\"\n#define AVR32_GPIO_GFER_IMPLEMENTED \"44'b11111111111111111111111111111111111111111111\"\n#define AVR32_GPIO_GFILTER_IMPLEMENTED \"44'b11111111111111111111111111111111111111111111\"\n#define AVR32_GPIO_GPER_DEFAULT_VAL \"44'b11111111111111111111111111111111111111111111\"\n#define AVR32_GPIO_GPER_IMPLEMENTED \"44'b11111111111111111111111111111111111111111000\"\n#define AVR32_GPIO_IRQ_MSB 5\n#define AVR32_GPIO_PADDR_BITS 9\n#define AVR32_GPIO_PINS_MSB 43\n#define AVR32_GPIO_IER_DEFAULT_VAL \"44'b00000000000000000000000000000000000000000000\"\n#define AVR32_GPIO_IER_IMPLEMENTED \"44'b11111111111111111111111111111111111111111111\"\n#define AVR32_GPIO_IFR_IMPLEMENTED \"44'b11111111111111111111111111111111111111111111\"\n#define AVR32_GPIO_IMR0_DEFAULT_VAL \"44'b00000000000000000000000000000000000000000000\"\n#define AVR32_GPIO_IMR0_IMPLEMENTED \"44'b11111111111111111111111111111111111111111111\"\n#define AVR32_GPIO_IMR1_DEFAULT_VAL \"44'b00000000000000000000000000000000000000000000\"\n#define AVR32_GPIO_IMR1_IMPLEMENTED \"44'b11111111111111111111111111111111111111111111\"\n#define AVR32_GPIO_INPUT_SYNC_IMPLEMENTED \"44'b11111111111111111111111111111111111111111111\"\n#define AVR32_GPIO_IRQS_PER_GROUP 8\n#define AVR32_GPIO_NUMBER_OF_PINS 44\n#define AVR32_GPIO_ODER_DEFAULT_VAL \"44'b00000000000000000000000000000000000000000000\"\n#define AVR32_GPIO_ODER_IMPLEMENTED \"44'b11111111111111111111111111111111111111111111\"\n#define AVR32_GPIO_ODMER_DEFAULT_VAL \"44'b00000000000000000000000000000000000000000000\"\n#define AVR32_GPIO_ODMER_IMPLEMENTED \"44'b00000000000000000000000000000000000000000000\"\n#define AVR32_GPIO_OVR_DEFAULT_VAL \"44'b00000000000000000000000000000000000000000000\"\n#define AVR32_GPIO_OVR_IMPLEMENTED \"44'b11111111111111111111111111111111111111111111\"\n#define AVR32_GPIO_PADDR_MSB 8\n#define AVR32_GPIO_PDATA_MSB 31\n#define AVR32_GPIO_PMR0_DEFAULT_VAL \"44'b00000000000000000000000000000000000000000000\"\n#define AVR32_GPIO_PMR0_IMPLEMENTED \"44'b11111111111111111111111111111111111111111000\"\n#define AVR32_GPIO_PMR1_DEFAULT_VAL \"44'b00000000000000000000000000000000000000000000\"\n#define AVR32_GPIO_PMR1_IMPLEMENTED \"44'b11111111111111111111111111111111111111111000\"\n#define AVR32_GPIO_PORT_LENGTH 2\n#define AVR32_GPIO_PUER_DEFAULT_VAL \"44'b00000000000000000000000000000000000000000000\"\n#define AVR32_GPIO_PUER_IMPLEMENTED \"44'b11111111111111111111111111111111111111111111\"\n\n#include \"avr32/gpio_110.h\"\n\n\n/* HMATRIX */\n#define AVR32_HMATRIX_NUM 1\n\n/* HMATRIX */ \n#define AVR32_HMATRIX_ADDRESS 0xFFFE1000\n#define AVR32_HMATRIX (*((volatile avr32_hmatrix_t*)AVR32_HMATRIX_ADDRESS))\n#define AVR32_HMATRIX_CLK_HSB_PBA_BRIDGE 33\n#define AVR32_HMATRIX_CLK_HSB_PBB_BRIDGE 34\n#define AVR32_HMATRIX_CLK_PBB 96\n#define AVR32_HMATRIX_MASTER_CPU_DATA 0\n#define AVR32_HMATRIX_MASTER_CPU_INSN 1\n#define AVR32_HMATRIX_MASTER_CPU_SAB 2\n#define AVR32_HMATRIX_MASTER_NUM 5\n#define AVR32_HMATRIX_MASTER_PDCA 3\n#define AVR32_HMATRIX_MASTER_USBB_DMA 4\n#define AVR32_HMATRIX_SLAVE_FLASH 0\n#define AVR32_HMATRIX_SLAVE_NUM 5\n#define AVR32_HMATRIX_SLAVE_PBA 1\n#define AVR32_HMATRIX_SLAVE_PBB 2\n#define AVR32_HMATRIX_SLAVE_SRAM 3\n#define AVR32_HMATRIX_SLAVE_USBB_DPRAM 4\n\n//#include \"avr32/hmatrix_230.h\"\n\n\n/* JTAG */\n\n/* JTAG */ \n#define AVR32_JTAG_TDI_0_PIN 0\n#define AVR32_JTAG_TDO_0_PIN 1\n#define AVR32_JTAG_TMS_0_PIN 2\n\n\n\n/* PDCA */\n#define AVR32_PDCA_NUM 1\n\n/* PDCA */ \n#define AVR32_PDCA_ADDRESS 0xFFFF0000\n#define AVR32_PDCA (*((volatile avr32_pdca_t*)AVR32_PDCA_ADDRESS))\n#define AVR32_PDCA_CLK_HSB 36\n#define AVR32_PDCA_CLK_PBA 66\n#define AVR32_PDCA_IRQ_0 96\n#define AVR32_PDCA_IRQ_1 97\n#define AVR32_PDCA_IRQ_2 98\n#define AVR32_PDCA_IRQ_3 99\n#define AVR32_PDCA_IRQ_4 100\n#define AVR32_PDCA_IRQ_5 101\n#define AVR32_PDCA_IRQ_6 102\n#define AVR32_PDCA_CHANNEL_LENGTH 7\n#define AVR32_PDCA_PID_ADC_RX 0\n#define AVR32_PDCA_PID_SPI_RX 6\n#define AVR32_PDCA_PID_SPI_TX 12\n#define AVR32_PDCA_PID_SSC_RX 1\n#define AVR32_PDCA_PID_SSC_TX 7\n#define AVR32_PDCA_PID_TWI_RX 5\n#define AVR32_PDCA_PID_TWI_TX 11\n#define AVR32_PDCA_PID_USART0_RX 2\n#define AVR32_PDCA_PID_USART0_TX 8\n#define AVR32_PDCA_PID_USART1_RX 3\n#define AVR32_PDCA_PID_USART1_TX 9\n#define AVR32_PDCA_PID_USART2_RX 4\n#define AVR32_PDCA_PID_USART2_TX 10\n\n//#include \"avr32/pdca_102.h\"\n\n\n/* PLL */\n\n/* PLL0 */ \n#define AVR32_PLL0_DN_0_0_PIN 13\n#define AVR32_PLL0_DN_0_1_PIN 14\n#define AVR32_PLL0_FDIV_0_0_PIN 15\n#define AVR32_PLL0_FDIV_0_1_PIN 16\n#define AVR32_PLL0_FDIV_TEST_0_PIN 16\n#define AVR32_PLL0_LOCK_0_PIN 10\n#define AVR32_PLL0_PLLCLK_0_PIN 9\n#define AVR32_PLL0_UP_0_PIN 14\n\n\n/* PLL1 */ \n#define AVR32_PLL1_DN_0_PIN 5\n#define AVR32_PLL1_FDIV_0_PIN 7\n#define AVR32_PLL1_FDIV_TEST_0_PIN 8\n#define AVR32_PLL1_LOCK_0_PIN 4\n#define AVR32_PLL1_PLLCLK_0_PIN 3\n#define AVR32_PLL1_UP_0_PIN 6\n\n\n\n/* PM */\n#define AVR32_PM_NUM 1\n\n/* PM */ \n#define AVR32_PM_ADDRESS 0xFFFF0C00\n#define AVR32_PM (*((volatile avr32_pm_t*)AVR32_PM_ADDRESS))\n#define AVR32_PM_CLK_PBA 67\n#define AVR32_PM_IRQ 41\n#define AVR32_PM_GCLK_MSB 2\n#define AVR32_PM_GCLK_NUM 4\n#define AVR32_PM_GCLK_USBB 3\n#define AVR32_PM_GPLP_NUM 2\n#define AVR32_PM_CPU_MAX_FREQ 60000000\n#define AVR32_PM_HSB_MAX_FREQ 60000000\n#define AVR32_PM_PBA_MAX_FREQ 60000000\n#define AVR32_PM_PBB_MAX_FREQ 60000000\n#define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000\n#define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000\n#define AVR32_PM_PLL_VCO_RANGE1_MAX_FREQ 180000000\n#define AVR32_PM_PLL_VCO_RANGE1_MIN_FREQ 80000000\n#define AVR32_PM_RCOSC_CALIBRATION_BITS 10\n#define AVR32_PM_RCOSC_FREQUENCY 115200\n#define AVR32_PM_GCLK_GCLK0 0\n#define AVR32_PM_GCLK_GCLK1 1\n#define AVR32_PM_GCLK_GCLK2 2\n#define AVR32_PM_GCLK_0_PIN 3\n#define AVR32_PM_GCLK_0_FUNCTION 1\n#define AVR32_PM_GCLK_1_PIN 4\n#define AVR32_PM_GCLK_1_FUNCTION 1\n#define AVR32_PM_GCLK_2_PIN 30\n#define AVR32_PM_GCLK_2_FUNCTION 2\n#define AVR32_PM_RSTM_N_0_PIN 27\n#define AVR32_PM_XIN0_0_PIN 18\n#define AVR32_PM_XIN1_0_PIN 28\n#define AVR32_PM_XIN32_0_PIN 11\n#define AVR32_PM_XOUT0_0_PIN 19\n#define AVR32_PM_XOUT1_0_PIN 29\n#define AVR32_PM_XOUT32_0_PIN 12\n#define AVR32_PM_CLK_GRP_CPU 0\n#define AVR32_PM_CLK_GRP_HSB 1\n#define AVR32_PM_CLK_GRP_PBA 2\n#define AVR32_PM_CLK_GRP_PBB 3\n#define AVR32_PM_NUM_CLK_GRPS 4\n#define AVR32_PM_NUM_CLKS_PER_GRP0 17\n#define AVR32_PM_NUM_CLKS_PER_GRP1 5\n#define AVR32_PM_NUM_CLKS_PER_GRP2 13\n#define AVR32_PM_NUM_CLKS_PER_GRP3 3\n\n//#include \"avr32/pm_230.h\"\n\n\n/* PULLUP */\n\n/* PULLUP */ \n#define AVR32_PULLUP_LPC_PULLUP_0_0_PIN 28\n#define AVR32_PULLUP_LPC_PULLUP_0_1_PIN 29\n#define AVR32_PULLUP_LPC_PULLUP_0_2_PIN 30\n#define AVR32_PULLUP_LPC_PULLUP_0_3_PIN 31\n#define AVR32_PULLUP_LPC_PULLUP_0_4_PIN 32\n#define AVR32_PULLUP_LPC_PULLUP_0_5_PIN 33\n#define AVR32_PULLUP_LPC_PULLUP_0_6_PIN 34\n#define AVR32_PULLUP_LPC_PULLUP_0_7_PIN 35\n#define AVR32_PULLUP_LPC_PULLUP_0_8_PIN 36\n#define AVR32_PULLUP_LPC_PULLUP_0_9_PIN 37\n#define AVR32_PULLUP_LPC_PULLUP_0_10_PIN 38\n#define AVR32_PULLUP_LPC_PULLUP_0_11_PIN 39\n#define AVR32_PULLUP_LPC_PULLUP_0_12_PIN 40\n#define AVR32_PULLUP_LPC_PULLUP_0_13_PIN 41\n#define AVR32_PULLUP_LPC_PULLUP_0_14_PIN 42\n#define AVR32_PULLUP_LPC_PULLUP_0_15_PIN 43\n\n\n\n/* PWM */\n#define AVR32_PWM_NUM 1\n\n/* PWM */ \n#define AVR32_PWM_ADDRESS 0xFFFF3000\n#define AVR32_PWM (*((volatile avr32_pwm_t*)AVR32_PWM_ADDRESS))\n#define AVR32_PWM_CLK_PBA 74\n#define AVR32_PWM_IRQ 384\n#define AVR32_PWM_CHANNEL_LENGTH 0x7\n#define AVR32_PWM_LINES_MSB 6\n#define AVR32_PWM_0_0_PIN 7\n#define AVR32_PWM_0_0_FUNCTION 0\n#define AVR32_PWM_1_0_PIN 8\n#define AVR32_PWM_1_0_FUNCTION 0\n#define AVR32_PWM_2_0_PIN 21\n#define AVR32_PWM_2_0_FUNCTION 0\n#define AVR32_PWM_6_0_PIN 22\n#define AVR32_PWM_6_0_FUNCTION 0\n#define AVR32_PWM_2_1_PIN 13\n#define AVR32_PWM_2_1_FUNCTION 1\n#define AVR32_PWM_3_0_PIN 14\n#define AVR32_PWM_3_0_FUNCTION 1\n#define AVR32_PWM_4_0_PIN 15\n#define AVR32_PWM_4_0_FUNCTION 1\n#define AVR32_PWM_5_0_PIN 18\n#define AVR32_PWM_5_0_FUNCTION 1\n#define AVR32_PWM_6_1_PIN 19\n#define AVR32_PWM_6_1_FUNCTION 1\n#define AVR32_PWM_3_1_PIN 25\n#define AVR32_PWM_3_1_FUNCTION 1\n#define AVR32_PWM_4_1_PIN 28\n#define AVR32_PWM_4_1_FUNCTION 1\n#define AVR32_PWM_0_1_PIN 11\n#define AVR32_PWM_0_1_FUNCTION 2\n#define AVR32_PWM_1_1_PIN 12\n#define AVR32_PWM_1_1_FUNCTION 2\n#define AVR32_PWM_4_2_PIN 16\n#define AVR32_PWM_4_2_FUNCTION 2\n#define AVR32_PWM_6_2_PIN 31\n#define AVR32_PWM_6_2_FUNCTION 2\n#define AVR32_PWM_5_1_PIN 37\n#define AVR32_PWM_5_1_FUNCTION 2\n\n#include \"avr32/pwm_130.h\"\n\n\n/* RTC */\n#define AVR32_RTC_NUM 1\n\n/* RTC */ \n#define AVR32_RTC_ADDRESS 0xFFFF0D00\n#define AVR32_RTC (*((volatile avr32_rtc_t*)AVR32_RTC_ADDRESS))\n#define AVR32_RTC_CLK_PBA 67\n#define AVR32_RTC_IRQ 40\n\n//#include \"avr32/rtc_230.h\"\n\n\n/* SPI */\n#define AVR32_SPI_NUM 1\n\n/* SPI */ \n#define AVR32_SPI_ADDRESS 0xFFFF2400\n#define AVR32_SPI (*((volatile avr32_spi_t*)AVR32_SPI_ADDRESS))\n#define AVR32_SPI_CLK_PBA 69\n#define AVR32_SPI_IRQ 288\n#define AVR32_SPI_SPI_CS_MSB 3\n#define AVR32_SPI_MISO_0_0_PIN 25\n#define AVR32_SPI_MISO_0_0_FUNCTION 0\n#define AVR32_SPI_MISO_0_1_PIN 18\n#define AVR32_SPI_MISO_0_1_FUNCTION 2\n#define AVR32_SPI_MISO_0_2_PIN 28\n#define AVR32_SPI_MISO_0_2_FUNCTION 2\n#define AVR32_SPI_MOSI_0_0_PIN 14\n#define AVR32_SPI_MOSI_0_0_FUNCTION 0\n#define AVR32_SPI_MOSI_0_1_PIN 19\n#define AVR32_SPI_MOSI_0_1_FUNCTION 2\n#define AVR32_SPI_MOSI_0_2_PIN 29\n#define AVR32_SPI_MOSI_0_2_FUNCTION 2\n#define AVR32_SPI_NPCS_0_0_PIN 16\n#define AVR32_SPI_NPCS_0_0_FUNCTION 0\n#define AVR32_SPI_NPCS_1_0_PIN 17\n#define AVR32_SPI_NPCS_1_0_FUNCTION 0\n#define AVR32_SPI_NPCS_2_0_PIN 9\n#define AVR32_SPI_NPCS_2_0_FUNCTION 1\n#define AVR32_SPI_NPCS_3_0_PIN 10\n#define AVR32_SPI_NPCS_3_0_FUNCTION 1\n#define AVR32_SPI_NPCS_1_1_PIN 23\n#define AVR32_SPI_NPCS_1_1_FUNCTION 1\n#define AVR32_SPI_NPCS_0_1_PIN 24\n#define AVR32_SPI_NPCS_0_1_FUNCTION 1\n#define AVR32_SPI_NPCS_3_1_PIN 36\n#define AVR32_SPI_NPCS_3_1_FUNCTION 1\n#define AVR32_SPI_NPCS_2_1_PIN 37\n#define AVR32_SPI_NPCS_2_1_FUNCTION 1\n#define AVR32_SPI_SCK_0_0_PIN 15\n#define AVR32_SPI_SCK_0_0_FUNCTION 0\n#define AVR32_SPI_SCK_0_1_PIN 17\n#define AVR32_SPI_SCK_0_1_FUNCTION 2\n\n#include \"avr32/spi_199.h\"\n\n\n/* SSC */\n#define AVR32_SSC_NUM 1\n\n/* SSC */ \n#define AVR32_SSC_ADDRESS 0xFFFF3400\n#define AVR32_SSC (*((volatile avr32_ssc_t*)AVR32_SSC_ADDRESS))\n#define AVR32_SSC_CLK_PBA 75\n#define AVR32_SSC_IRQ 416\n#define AVR32_SSC_RX_CLOCK_0_PIN 38\n#define AVR32_SSC_RX_CLOCK_0_FUNCTION 0\n#define AVR32_SSC_RX_DATA_0_PIN 39\n#define AVR32_SSC_RX_DATA_0_FUNCTION 0\n#define AVR32_SSC_RX_FRAME_SYNC_0_PIN 40\n#define AVR32_SSC_RX_FRAME_SYNC_0_FUNCTION 0\n#define AVR32_SSC_TX_CLOCK_0_PIN 41\n#define AVR32_SSC_TX_CLOCK_0_FUNCTION 0\n#define AVR32_SSC_TX_DATA_0_PIN 42\n#define AVR32_SSC_TX_DATA_0_FUNCTION 0\n#define AVR32_SSC_TX_FRAME_SYNC_0_PIN 43\n#define AVR32_SSC_TX_FRAME_SYNC_0_FUNCTION 0\n\n//#include \"avr32/ssc_310.h\"\n\n\n/* TC */\n#define AVR32_TC_NUM 1\n\n/* TC */ \n#define AVR32_TC_ADDRESS 0xFFFF3800\n#define AVR32_TC (*((volatile avr32_tc_t*)AVR32_TC_ADDRESS))\n#define AVR32_TC_CLK_PBA 76\n#define AVR32_TC_IRQ0 448\n#define AVR32_TC_IRQ1 449\n#define AVR32_TC_IRQ2 450\n#define AVR32_TC_A0_0_0_PIN 32\n#define AVR32_TC_A0_0_0_FUNCTION 0\n#define AVR32_TC_A0_0_1_PIN 26\n#define AVR32_TC_A0_0_1_FUNCTION 2\n#define AVR32_TC_A1_0_0_PIN 21\n#define AVR32_TC_A1_0_0_FUNCTION 1\n#define AVR32_TC_A1_0_1_PIN 34\n#define AVR32_TC_A1_0_1_FUNCTION 1\n#define AVR32_TC_A2_0_0_PIN 11\n#define AVR32_TC_A2_0_0_FUNCTION 1\n#define AVR32_TC_A2_0_1_PIN 42\n#define AVR32_TC_A2_0_1_FUNCTION 1\n#define AVR32_TC_B0_0_0_PIN 33\n#define AVR32_TC_B0_0_0_FUNCTION 0\n#define AVR32_TC_B0_0_1_PIN 27\n#define AVR32_TC_B0_0_1_FUNCTION 2\n#define AVR32_TC_B1_0_0_PIN 22\n#define AVR32_TC_B1_0_0_FUNCTION 1\n#define AVR32_TC_B1_0_1_PIN 35\n#define AVR32_TC_B1_0_1_FUNCTION 1\n#define AVR32_TC_B2_0_0_PIN 12\n#define AVR32_TC_B2_0_0_FUNCTION 1\n#define AVR32_TC_B2_0_1_PIN 43\n#define AVR32_TC_B2_0_1_FUNCTION 1\n#define AVR32_TC_CLK0_0_0_PIN 29\n#define AVR32_TC_CLK0_0_0_FUNCTION 0\n#define AVR32_TC_CLK0_0_1_PIN 20\n#define AVR32_TC_CLK0_0_1_FUNCTION 1\n#define AVR32_TC_CLK1_0_0_PIN 16\n#define AVR32_TC_CLK1_0_0_FUNCTION 1\n#define AVR32_TC_CLK1_0_1_PIN 29\n#define AVR32_TC_CLK1_0_1_FUNCTION 1\n#define AVR32_TC_CLK2_0_0_PIN 17\n#define AVR32_TC_CLK2_0_0_FUNCTION 1\n#define AVR32_TC_CLK2_0_1_PIN 36\n#define AVR32_TC_CLK2_0_1_FUNCTION 2\n\n//#include \"avr32/tc_222.h\"\n\n\n/* TWI */\n#define AVR32_TWI_NUM 1\n\n/* TWI */ \n#define AVR32_TWI_ADDRESS 0xFFFF2C00\n#define AVR32_TWI (*((volatile avr32_twi_t*)AVR32_TWI_ADDRESS))\n#define AVR32_TWI_CLK_PBA 70\n#define AVR32_TWI_IRQ 352\n#define AVR32_TWI_SCL_0_0_PIN 9\n#define AVR32_TWI_SCL_0_0_FUNCTION 0\n#define AVR32_TWI_SCL_0_1_PIN 9\n#define AVR32_TWI_SCL_INPUT_TEST_0_PIN 5\n#define AVR32_TWI_SCL_OUTPUT_TEST_0_PIN 6\n#define AVR32_TWI_SDA_0_0_PIN 10\n#define AVR32_TWI_SDA_0_0_FUNCTION 0\n#define AVR32_TWI_SDA_0_1_PIN 10\n#define AVR32_TWI_SDA_INPUT_TEST_0_PIN 3\n#define AVR32_TWI_SDA_OUTPUT_TEST_0_PIN 4\n\n//#include \"avr32/twi_211.h\"\n\n\n/* USART */\n#define AVR32_USART_NUM 3\n\n/* USART0 */ \n#define AVR32_USART0_ADDRESS 0xFFFF1400\n#define AVR32_USART0 (*((volatile avr32_usart_t*)AVR32_USART0_ADDRESS))\n#define AVR32_USART0_CLK_PBA 71\n#define AVR32_USART0_IRQ 160\n#define AVR32_USART0_CLK_0_0_PIN 28\n#define AVR32_USART0_CLK_0_0_FUNCTION 0\n#define AVR32_USART0_CLK_0_1_PIN 13\n#define AVR32_USART0_CLK_0_1_FUNCTION 2\n#define AVR32_USART0_CTS_0_PIN 12\n#define AVR32_USART0_CTS_0_FUNCTION 0\n#define AVR32_USART0_RTS_0_PIN 11\n#define AVR32_USART0_RTS_0_FUNCTION 0\n#define AVR32_USART0_RXD_0_0_PIN 18\n#define AVR32_USART0_RXD_0_0_FUNCTION 0\n#define AVR32_USART0_RXD_0_1_PIN 42\n#define AVR32_USART0_RXD_0_1_FUNCTION 2\n#define AVR32_USART0_TXD_0_0_PIN 19\n#define AVR32_USART0_TXD_0_0_FUNCTION 0\n#define AVR32_USART0_TXD_0_1_PIN 43\n#define AVR32_USART0_TXD_0_1_FUNCTION 2\n\n\n/* USART1 */ \n#define AVR32_USART1_ADDRESS 0xFFFF1800\n#define AVR32_USART1 (*((volatile avr32_usart_t*)AVR32_USART1_ADDRESS))\n#define AVR32_USART1_CLK_PBA 72\n#define AVR32_USART1_IRQ 192\n#define AVR32_USART1_CLK_0_PIN 20\n#define AVR32_USART1_CLK_0_FUNCTION 0\n#define AVR32_USART1_CTS_0_0_PIN 36\n#define AVR32_USART1_CTS_0_0_FUNCTION 0\n#define AVR32_USART1_CTS_0_1_PIN 9\n#define AVR32_USART1_CTS_0_1_FUNCTION 2\n#define AVR32_USART1_DCD_0_0_PIN 38\n#define AVR32_USART1_DCD_0_0_FUNCTION 1\n#define AVR32_USART1_DCD_0_1_PIN 5\n#define AVR32_USART1_DCD_0_1_FUNCTION 2\n#define AVR32_USART1_DSR_0_0_PIN 39\n#define AVR32_USART1_DSR_0_0_FUNCTION 1\n#define AVR32_USART1_DSR_0_1_PIN 6\n#define AVR32_USART1_DSR_0_1_FUNCTION 2\n#define AVR32_USART1_DTR_0_0_PIN 40\n#define AVR32_USART1_DTR_0_0_FUNCTION 1\n#define AVR32_USART1_DTR_0_1_PIN 7\n#define AVR32_USART1_DTR_0_1_FUNCTION 2\n#define AVR32_USART1_RI_0_0_PIN 41\n#define AVR32_USART1_RI_0_0_FUNCTION 1\n#define AVR32_USART1_RI_0_1_PIN 8\n#define AVR32_USART1_RI_0_1_FUNCTION 2\n#define AVR32_USART1_RTS_0_0_PIN 37\n#define AVR32_USART1_RTS_0_0_FUNCTION 0\n#define AVR32_USART1_RTS_0_1_PIN 10\n#define AVR32_USART1_RTS_0_1_FUNCTION 2\n#define AVR32_USART1_RXD_0_0_PIN 24\n#define AVR32_USART1_RXD_0_0_FUNCTION 0\n#define AVR32_USART1_RXD_0_1_PIN 35\n#define AVR32_USART1_RXD_0_1_FUNCTION 2\n#define AVR32_USART1_TXD_0_0_PIN 23\n#define AVR32_USART1_TXD_0_0_FUNCTION 0\n#define AVR32_USART1_TXD_0_1_PIN 34\n#define AVR32_USART1_TXD_0_1_FUNCTION 2\n\n\n/* USART2 */ \n#define AVR32_USART2_ADDRESS 0xFFFF1C00\n#define AVR32_USART2 (*((volatile avr32_usart_t*)AVR32_USART2_ADDRESS))\n#define AVR32_USART2_CLK_PBA 73\n#define AVR32_USART2_IRQ 224\n#define AVR32_USART2_CLK_0_PIN 15\n#define AVR32_USART2_CLK_0_FUNCTION 2\n#define AVR32_USART2_CTS_0_PIN 32\n#define AVR32_USART2_CTS_0_FUNCTION 2\n#define AVR32_USART2_RTS_0_PIN 33\n#define AVR32_USART2_RTS_0_FUNCTION 2\n#define AVR32_USART2_RXD_0_0_PIN 27\n#define AVR32_USART2_RXD_0_0_FUNCTION 1\n#define AVR32_USART2_RXD_0_1_PIN 20\n#define AVR32_USART2_RXD_0_1_FUNCTION 2\n#define AVR32_USART2_TXD_0_0_PIN 26\n#define AVR32_USART2_TXD_0_0_FUNCTION 1\n#define AVR32_USART2_TXD_0_1_PIN 21\n#define AVR32_USART2_TXD_0_1_FUNCTION 2\n\n//#include \"avr32/usart_400.h\"\n\n\n/* USBB */\n#define AVR32_USBB_NUM 1\n\n/* USBB */ \n#define AVR32_USBB_ADDRESS 0xFFFE0000\n#define AVR32_USBB (*((volatile avr32_usbb_t*)AVR32_USBB_ADDRESS))\n#define AVR32_USBB_CLK_HSB 35\n#define AVR32_USBB_CLK_PBB 97\n#define AVR32_USBB_IRQ 544\n#define AVR32_USBB_EPT_NUM 7\n#define AVR32_USBB_ENABLE_TEST_0_PIN 22\n#define AVR32_USBB_EOPN_TEST_0_PIN 23\n#define AVR32_USBB_FS_TEST_0_PIN 5\n#define AVR32_USBB_OEN_TEST_0_PIN 6\n#define AVR32_USBB_ONN_TEST_0_PIN 7\n#define AVR32_USBB_PDONDM_TEST_0_PIN 8\n#define AVR32_USBB_PDONDP_TEST_0_PIN 9\n#define AVR32_USBB_PUIDLE_TEST_0_PIN 10\n#define AVR32_USBB_PUON_TEST_0_PIN 13\n#define AVR32_USBB_RXDM_TEST_0_PIN 14\n#define AVR32_USBB_RXDP_TEST_0_PIN 15\n#define AVR32_USBB_RXD_TEST_0_PIN 16\n#define AVR32_USBB_SESSVLD_TEST_0_PIN 17\n#define AVR32_USBB_TXD_TEST_0_PIN 24\n#define AVR32_USBB_USB_ID_0_0_PIN 26\n#define AVR32_USBB_USB_ID_0_0_FUNCTION 0\n#define AVR32_USBB_USB_ID_0_1_PIN 3\n#define AVR32_USBB_USB_ID_0_1_FUNCTION 2\n#define AVR32_USBB_USB_VBOF_0_0_PIN 27\n#define AVR32_USBB_USB_VBOF_0_0_FUNCTION 0\n#define AVR32_USBB_USB_VBOF_0_1_PIN 4\n#define AVR32_USBB_USB_VBOF_0_1_FUNCTION 2\n#define AVR32_USBB_VAVBUSVLD_TEST_0_PIN 19\n#define AVR32_USBB_VBUSDISCHARGE_TEST_0_PIN 20\n#define AVR32_USBB_VBUSPULSING_TEST_0_PIN 21\n\n//#include \"avr32/usbb_310.h\"\n\n\n/* WDT */\n#define AVR32_WDT_NUM 1\n\n/* WDT */ \n#define AVR32_WDT_ADDRESS 0xFFFF0D30\n#define AVR32_WDT (*((volatile avr32_wdt_t*)AVR32_WDT_ADDRESS))\n#define AVR32_WDT_WDTEXTRST_MSB 1\n\n//#include \"avr32/wdt_230.h\"\n\n\n/* PAD->GPIO bits mapping */\n#define AVR32_PIN_PA03 3\n#define AVR32_PIN_PA04 4\n#define AVR32_PIN_PA05 5\n#define AVR32_PIN_PA06 6\n#define AVR32_PIN_PA07 7\n#define AVR32_PIN_PA08 8\n#define AVR32_PIN_PA09 9\n#define AVR32_PIN_PA10 10\n#define AVR32_PIN_PA11 11\n#define AVR32_PIN_PA12 12\n#define AVR32_PIN_PA13 13\n#define AVR32_PIN_PA14 14\n#define AVR32_PIN_PA15 15\n#define AVR32_PIN_PA16 16\n#define AVR32_PIN_PA17 17\n#define AVR32_PIN_PA18 18\n#define AVR32_PIN_PA19 19\n#define AVR32_PIN_PA20 20\n#define AVR32_PIN_PA21 21\n#define AVR32_PIN_PA22 22\n#define AVR32_PIN_PA23 23\n#define AVR32_PIN_PA24 24\n#define AVR32_PIN_PA25 25\n#define AVR32_PIN_PA26 26\n#define AVR32_PIN_PA27 27\n#define AVR32_PIN_PA28 28\n#define AVR32_PIN_PA29 29\n#define AVR32_PIN_PA30 30\n#define AVR32_PIN_PA31 31\n#define AVR32_PIN_PB00 32\n#define AVR32_PIN_PB01 33\n#define AVR32_PIN_PB02 34\n#define AVR32_PIN_PB03 35\n#define AVR32_PIN_PB04 36\n#define AVR32_PIN_PB05 37\n#define AVR32_PIN_PB06 38\n#define AVR32_PIN_PB07 39\n#define AVR32_PIN_PB08 40\n#define AVR32_PIN_PB09 41\n#define AVR32_PIN_PB10 42\n#define AVR32_PIN_PB11 43\n#define AVR32_PIN_TDI 0\n#define AVR32_PIN_TDO 1\n#define AVR32_PIN_TMS 2\n\n\n#if !defined (DEPRECATED_DISABLE)\n\n#define AVR32_ADC_ADC_CHANNELS_MSB 7\n#define AVR32_ADC_ADC_DATA_MSB 9\n\n#define AVR32_FREQM_FREQM_IRQ 42\n#define AVR32_FREQM_FREQM_REFSEL_BITS 1\n\n#define AVR32_GPIO_GPIO_IRQ_MSB 5\n#define AVR32_GPIO_GPIO_PADDR_BITS 9\n#define AVR32_GPIO_GPIO_PINS_MSB 43\n\n#endif\n\n\n/* #ifndef AVR32_UC3B0256_H_INCLUDED */\n#endif\n" }, { "path": "firmware/mock_hardware/include/avr32/uc3b0512.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2006-2010 Atmel Corporation\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n * Model : UC3B0512\n * Revision : $Revision: 115080 $\n * Checkin Date : $Date: 2012-05-04 12:40:09 +0200 (Fri, 04 May 2012) $\n *\n ****************************************************************************/\n#ifndef AVR32_UC3B0512_H_INCLUDED\n#define AVR32_UC3B0512_H_INCLUDED\n\n/* Instance count */\n#define AVR32_ABDAC_NUM 1\n#define AVR32_ADC_NUM 1\n#define AVR32_EIC_NUM 1\n#define AVR32_FLASHC_NUM 1\n#define AVR32_FREQM_NUM 1\n#define AVR32_GPIO_NUM 1\n#define AVR32_HMATRIX_NUM 1\n#define AVR32_JTAG_NUM 1\n#define AVR32_PDCA_NUM 1\n#define AVR32_PLL_NUM 2\n#define AVR32_PM_NUM 1\n#define AVR32_PULLUP_NUM 1\n#define AVR32_PWM_NUM 1\n#define AVR32_RTC_NUM 1\n#define AVR32_SPI_NUM 1\n#define AVR32_SSC_NUM 1\n#define AVR32_TC_NUM 1\n#define AVR32_TWI_NUM 1\n#define AVR32_USART_NUM 3\n#define AVR32_USBB_NUM 1\n#define AVR32_WDT_NUM 1\n\n/* Maskable module clocks */\n#define AVR32_PM_CLK_GRP_CPU 0\n#define AVR32_PM_CLK_GRP_HSB 1\n#define AVR32_PM_CLK_GRP_PBA 2\n#define AVR32_PM_CLK_GRP_PBB 3\n#define AVR32_PM_NUM_CLK_GRPS 4\n#define AVR32_PM_NUM_CLKS_PER_GRP0 17\n#define AVR32_PM_NUM_CLKS_PER_GRP1 5\n#define AVR32_PM_NUM_CLKS_PER_GRP2 13\n#define AVR32_PM_NUM_CLKS_PER_GRP3 3\n\n/* CPU clocks */\n#define AVR32_OCD_CLK_CPU 1\n#define AVR32_CORE_CLK_CPU_COUNT 16\n\n/* HSB clocks */\n#define AVR32_FLASHC_CLK_HSB 32\n#define AVR32_HMATRIX_CLK_HSB_PBA_BRIDGE 33\n#define AVR32_HMATRIX_CLK_HSB_PBB_BRIDGE 34\n#define AVR32_USBB_CLK_HSB 35\n#define AVR32_PDCA_CLK_HSB 36\n\n/* PBA clocks */\n#define AVR32_INTC_CLK_PBA 64\n#define AVR32_GPIO_CLK_PBA 65\n#define AVR32_PDCA_CLK_PBA 66\n#define AVR32_PM_CLK_PBA 67\n#define AVR32_RTC_CLK_PBA 67\n#define AVR32_EIC_CLK_PBA 67\n#define AVR32_ADC_CLK_PBA 68\n#define AVR32_SPI_CLK_PBA 69\n#define AVR32_TWI_CLK_PBA 70\n#define AVR32_USART0_CLK_PBA 71\n#define AVR32_USART1_CLK_PBA 72\n#define AVR32_USART2_CLK_PBA 73\n#define AVR32_PWM_CLK_PBA 74\n#define AVR32_SSC_CLK_PBA 75\n#define AVR32_TC_CLK_PBA 76\n#define AVR32_ABDAC_CLK_PBA 77\n\n/* PBB clocks */\n#define AVR32_HMATRIX_CLK_PBB 96\n#define AVR32_USBB_CLK_PBB 97\n#define AVR32_FLASHC_CLK_PBB 98\n\n/* Generic clocks */\n#define AVR32_PM_GCLK_GCLK0 0\n#define AVR32_PM_GCLK_GCLK1 1\n#define AVR32_PM_GCLK_GCLK2 2\n#define AVR32_PM_GCLK_USBB 3\n\n/* Core */\n//#include \"avr32/core_sc0_143.h\"\n/* OCD */\n//#include \"avr32/ocd_s0_143.h\"\n\n/* CORE */\n#define AVR32_CORE_COMPARE_IRQ 0\n#define AVR32_CORE_SCAN_CHAIN_MSB 9\n#define AVR32_CORE_SCAN_CLOCK_MSB 1\n\n/* OCD */\n\n/* Memories */\n#define AVR32_FLASH_ADDRESS 0x80000000\n#define AVR32_FLASH_SIZE 0x00080000\n#define AVR32_FLASH ((unsigned char*)AVR32_FLASH_ADDRESS)\n#define AVR32_SRAM_ADDRESS 0x00000000\n#define AVR32_SRAM_SIZE 0x00018000\n#define AVR32_SRAM ((unsigned char*)AVR32_SRAM_ADDRESS)\n#define AVR32_USBB_SLAVE_ADDRESS 0xD0000000\n#define AVR32_USBB_SLAVE_SIZE 0x00800000\n#define AVR32_USBB_SLAVE ((unsigned char*)AVR32_USBB_SLAVE_ADDRESS)\n\n/* Interrupt Controller */\n#define AVR32_INTC_ADDRESS 0xFFFF0800\n#define AVR32_INTC (*((volatile avr32_intc_t*)AVR32_INTC_ADDRESS))\n#define AVR32_INTC_NUM_INT_GRPS 19\n#define AVR32_INTC_NUM_IRQS_PER_GRP0 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP1 11\n#define AVR32_INTC_NUM_IRQS_PER_GRP10 0\n#define AVR32_INTC_NUM_IRQS_PER_GRP11 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP12 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP13 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP14 3\n#define AVR32_INTC_NUM_IRQS_PER_GRP15 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP16 0\n#define AVR32_INTC_NUM_IRQS_PER_GRP17 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP18 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP2 6\n#define AVR32_INTC_NUM_IRQS_PER_GRP3 7\n#define AVR32_INTC_NUM_IRQS_PER_GRP4 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP5 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP6 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP7 1\n#define AVR32_INTC_NUM_IRQS_PER_GRP8 0\n#define AVR32_INTC_NUM_IRQS_PER_GRP9 1\n#define AVR32_INTC_NUM_NMI 1\n\n//#include \"avr32/intc_101.h\"\n\n/* ABDAC */\n\n/* ABDAC */\n#define AVR32_ABDAC_ADDRESS 0xFFFF4000\n#define AVR32_ABDAC (*((volatile avr32_abdac_t*)AVR32_ABDAC_ADDRESS))\n#define AVR32_ABDAC_IRQ 576\n#define AVR32_ABDAC_DATA_0_0_PIN 3\n#define AVR32_ABDAC_DATA_0_0_FUNCTION 3\n#define AVR32_ABDAC_DATA_1_0_PIN 5\n#define AVR32_ABDAC_DATA_1_0_FUNCTION 3\n#define AVR32_ABDAC_DATA_0_1_PIN 22\n#define AVR32_ABDAC_DATA_0_1_FUNCTION 3\n#define AVR32_ABDAC_DATA_1_1_PIN 26\n#define AVR32_ABDAC_DATA_1_1_FUNCTION 3\n#define AVR32_ABDAC_DATA_0_2_PIN 38\n#define AVR32_ABDAC_DATA_0_2_FUNCTION 3\n#define AVR32_ABDAC_DATA_1_2_PIN 40\n#define AVR32_ABDAC_DATA_1_2_FUNCTION 3\n#define AVR32_ABDAC_DATAN_0_0_PIN 4\n#define AVR32_ABDAC_DATAN_0_0_FUNCTION 3\n#define AVR32_ABDAC_DATAN_1_0_PIN 6\n#define AVR32_ABDAC_DATAN_1_0_FUNCTION 3\n#define AVR32_ABDAC_DATAN_1_1_PIN 27\n#define AVR32_ABDAC_DATAN_1_1_FUNCTION 3\n#define AVR32_ABDAC_DATAN_0_1_PIN 28\n#define AVR32_ABDAC_DATAN_0_1_FUNCTION 3\n#define AVR32_ABDAC_DATAN_0_2_PIN 39\n#define AVR32_ABDAC_DATAN_0_2_FUNCTION 3\n#define AVR32_ABDAC_DATAN_1_2_PIN 41\n#define AVR32_ABDAC_DATAN_1_2_FUNCTION 3\n\n//#include \"avr32/abdac_101.h\"\n\n/* ADC */\n\n/* ADC */\n#define AVR32_ADC_ADDRESS 0xFFFF3C00\n#define AVR32_ADC (*((volatile avr32_adc_t*)AVR32_ADC_ADDRESS))\n#define AVR32_ADC_IRQ 480\n#define AVR32_ADC_CHANNELS_MSB 7\n#define AVR32_ADC_DATA_MSB 9\n#define AVR32_ADC_AD_0_PIN 3\n#define AVR32_ADC_AD_0_FUNCTION 0\n#define AVR32_ADC_AD_1_PIN 4\n#define AVR32_ADC_AD_1_FUNCTION 0\n#define AVR32_ADC_AD_6_PIN 30\n#define AVR32_ADC_AD_6_FUNCTION 0\n#define AVR32_ADC_AD_7_PIN 31\n#define AVR32_ADC_AD_7_FUNCTION 0\n#define AVR32_ADC_AD_2_PIN 5\n#define AVR32_ADC_AD_2_FUNCTION 1\n#define AVR32_ADC_AD_3_PIN 6\n#define AVR32_ADC_AD_3_FUNCTION 1\n#define AVR32_ADC_AD_4_PIN 7\n#define AVR32_ADC_AD_4_FUNCTION 1\n#define AVR32_ADC_AD_5_PIN 8\n#define AVR32_ADC_AD_5_FUNCTION 1\n#define AVR32_ADC_TEST_CLK_0_PIN 13\n#define AVR32_ADC_TEST_DATA_0_PIN 17\n#define AVR32_ADC_TEST_DATA_1_PIN 19\n#define AVR32_ADC_TEST_DATA_2_PIN 20\n#define AVR32_ADC_TEST_DATA_3_PIN 21\n#define AVR32_ADC_TEST_DATA_4_PIN 22\n#define AVR32_ADC_TEST_DATA_5_PIN 23\n#define AVR32_ADC_TEST_DATA_6_PIN 24\n#define AVR32_ADC_TEST_DATA_7_PIN 25\n#define AVR32_ADC_TEST_DATA_8_PIN 26\n#define AVR32_ADC_TEST_DATA_9_PIN 27\n#define AVR32_ADC_TEST_EOC_0_PIN 12\n#define AVR32_ADC_TEST_ONAD_0_PIN 11\n#define AVR32_ADC_TEST_ONSAR_0_PIN 10\n#define AVR32_ADC_TEST_SEL_0_PIN 14\n#define AVR32_ADC_TEST_SEL_1_PIN 15\n#define AVR32_ADC_TEST_SEL_2_PIN 16\n#define AVR32_ADC_TEST_START_0_PIN 9\n#define AVR32_ADC_TRIGGER_0_PIN 22\n#define AVR32_ADC_TRIGGER_0_FUNCTION 2\n\n#include \"avr32/adc_200.h\"\n\n/* EIC */\n\n/* EIC */\n#define AVR32_EIC_ADDRESS 0xFFFF0D80\n#define AVR32_EIC (*((volatile avr32_eic_t*)AVR32_EIC_ADDRESS))\n#define AVR32_EIC_IRQ_0 32\n#define AVR32_EIC_IRQ_1 33\n#define AVR32_EIC_IRQ_2 34\n#define AVR32_EIC_IRQ_3 35\n#define AVR32_EIC_IRQ_4 36\n#define AVR32_EIC_IRQ_5 37\n#define AVR32_EIC_IRQ_6 38\n#define AVR32_EIC_IRQ_7 39\n#define AVR32_EIC_INT_MSB 8\n#define AVR32_EIC_SCAN_MSB 7\n#define AVR32_EIC_STD_NUM 8\n#define AVR32_EIC_EXTINT_0_PIN 5\n#define AVR32_EIC_EXTINT_0_FUNCTION 0\n#define AVR32_EIC_EXTINT_1_PIN 6\n#define AVR32_EIC_EXTINT_1_FUNCTION 0\n#define AVR32_EIC_EXTINT_8_PIN 13\n#define AVR32_EIC_EXTINT_8_FUNCTION 0\n#define AVR32_EIC_EXTINT_6_PIN 34\n#define AVR32_EIC_EXTINT_6_FUNCTION 0\n#define AVR32_EIC_EXTINT_7_PIN 35\n#define AVR32_EIC_EXTINT_7_FUNCTION 0\n#define AVR32_EIC_EXTINT_2_PIN 14\n#define AVR32_EIC_EXTINT_2_FUNCTION 2\n#define AVR32_EIC_EXTINT_3_PIN 23\n#define AVR32_EIC_EXTINT_3_FUNCTION 2\n#define AVR32_EIC_EXTINT_4_PIN 24\n#define AVR32_EIC_EXTINT_4_FUNCTION 2\n#define AVR32_EIC_EXTINT_5_PIN 25\n#define AVR32_EIC_EXTINT_5_FUNCTION 2\n#define AVR32_EIC_SCAN_0_PIN 30\n#define AVR32_EIC_SCAN_0_FUNCTION 1\n#define AVR32_EIC_SCAN_1_PIN 31\n#define AVR32_EIC_SCAN_1_FUNCTION 1\n#define AVR32_EIC_SCAN_2_PIN 32\n#define AVR32_EIC_SCAN_2_FUNCTION 1\n#define AVR32_EIC_SCAN_3_PIN 33\n#define AVR32_EIC_SCAN_3_FUNCTION 1\n#define AVR32_EIC_SCAN_4_PIN 38\n#define AVR32_EIC_SCAN_4_FUNCTION 2\n#define AVR32_EIC_SCAN_5_PIN 39\n#define AVR32_EIC_SCAN_5_FUNCTION 2\n#define AVR32_EIC_SCAN_6_PIN 40\n#define AVR32_EIC_SCAN_6_FUNCTION 2\n#define AVR32_EIC_SCAN_7_PIN 41\n#define AVR32_EIC_SCAN_7_FUNCTION 2\n\n//#include \"avr32/eic_2311.h\"\n\n/* FLASHC */\n\n/* FLASHC */\n#define AVR32_FLASHC_ADDRESS 0xFFFE1400\n#define AVR32_FLASHC (*((volatile avr32_flashc_t*)AVR32_FLASHC_ADDRESS))\n#define AVR32_FLASHC_IRQ 128\n#define AVR32_FLASHC_FLASH_SIZE 524288\n#define AVR32_FLASHC_FWS_0_MAX_FREQ 33000000\n#define AVR32_FLASHC_FWS_1_MAX_FREQ 60000000\n#define AVR32_FLASHC_PAGES_PR_REGION 64\n#define AVR32_FLASHC_PAGE_SIZE 512\n#define AVR32_FLASHC_USER_PAGE ((volatile unsigned char*)AVR32_FLASHC_USER_PAGE_ADDRESS)\n#define AVR32_FLASHC_USER_PAGE_ADDRESS 0x80800000\n#define AVR32_FLASHC_USER_PAGE_SIZE 512\n#define AVR32_FLASHC_BODEN 27\n#define AVR32_FLASHC_BODEN_MASK 0x18000000\n#define AVR32_FLASHC_BODEN_OFFSET 27\n#define AVR32_FLASHC_BODEN_SIZE 2\n#define AVR32_FLASHC_BODHYST 26\n#define AVR32_FLASHC_BODHYST_MASK 0x04000000\n#define AVR32_FLASHC_BODHYST_OFFSET 26\n#define AVR32_FLASHC_BODHYST_SIZE 1\n#define AVR32_FLASHC_BODLEVEL 20\n#define AVR32_FLASHC_BODLEVEL_MASK 0x03F00000\n#define AVR32_FLASHC_BODLEVEL_OFFSET 20\n#define AVR32_FLASHC_BODLEVEL_SIZE 6\n#define AVR32_FLASHC_FGPFRLO_BODEN 27\n#define AVR32_FLASHC_FGPFRLO_BODEN_MASK 0x18000000\n#define AVR32_FLASHC_FGPFRLO_BODEN_OFFSET 27\n#define AVR32_FLASHC_FGPFRLO_BODEN_SIZE 2\n#define AVR32_FLASHC_FGPFRLO_BODHYST 26\n#define AVR32_FLASHC_FGPFRLO_BODHYST_MASK 0x04000000\n#define AVR32_FLASHC_FGPFRLO_BODHYST_OFFSET 26\n#define AVR32_FLASHC_FGPFRLO_BODHYST_SIZE 1\n#define AVR32_FLASHC_FGPFRLO_BODLEVEL 20\n#define AVR32_FLASHC_FGPFRLO_BODLEVEL_MASK 0x03F00000\n#define AVR32_FLASHC_FGPFRLO_BODLEVEL_OFFSET 20\n#define AVR32_FLASHC_FGPFRLO_BODLEVEL_SIZE 6\n#define AVR32_FLASHC_EXTCLK_0_PIN 3\n#define AVR32_FLASHC_FLASH_OBS_0_PIN 3\n#define AVR32_FLASHC_FLASH_OBS_1_PIN 4\n#define AVR32_FLASHC_FLASH_OBS_2_PIN 5\n#define AVR32_FLASHC_FLASH_OBS_3_PIN 6\n#define AVR32_FLASHC_FLASH_OBS_4_PIN 9\n#define AVR32_FLASHC_FLASH_OBS_5_PIN 10\n#define AVR32_FLASHC_FLASH_OBS_6_PIN 11\n#define AVR32_FLASHC_FLASH_OBS_7_PIN 12\n#define AVR32_FLASHC_FLASH_OBS_8_PIN 13\n#define AVR32_FLASHC_FLASH_OBS_9_PIN 14\n#define AVR32_FLASHC_FLASH_OBS_10_PIN 15\n#define AVR32_FLASHC_FLASH_OBS_11_PIN 16\n#define AVR32_FLASHC_FLASH_OBS_12_PIN 17\n#define AVR32_FLASHC_FLASH_OBS_13_PIN 20\n#define AVR32_FLASHC_FLASH_OBS_14_PIN 21\n#define AVR32_FLASHC_FLASH_OBS_15_PIN 22\n#define AVR32_FLASHC_FLASH_OBS_16_PIN 23\n#define AVR32_FLASHC_FLASH_OBS_17_PIN 24\n#define AVR32_FLASHC_FLASH_OBS_18_PIN 25\n#define AVR32_FLASHC_FLASH_OBS_19_PIN 26\n#define AVR32_FLASHC_FLASH_OBS_20_PIN 27\n#define AVR32_FLASHC_LATDEL_0_PIN 7\n#define AVR32_FLASHC_LATDELCLK_0_PIN 8\n#define AVR32_FLASHC_LATDELMATCH_0_PIN 4\n\n//#include \"avr32/flashc_212.h\"\n\n/* FREQM */\n\n/* FREQM */\n#define AVR32_FREQM_ADDRESS 0xFFFF0D50\n#define AVR32_FREQM (*((volatile avr32_freqm_t*)AVR32_FREQM_ADDRESS))\n#define AVR32_FREQM_IRQ 42\n#define AVR32_FREQM_REFSEL_BITS 1\n\n//#include \"avr32/freqm_2311.h\"\n\n/* GPIO */\n\n/* GPIO */\n#define AVR32_GPIO_ADDRESS 0xFFFF1000\n#define AVR32_GPIO (*((volatile avr32_gpio_t*)AVR32_GPIO_ADDRESS))\n#define AVR32_GPIO_IRQ_0 64\n#define AVR32_GPIO_IRQ_1 65\n#define AVR32_GPIO_IRQ_2 66\n#define AVR32_GPIO_IRQ_3 67\n#define AVR32_GPIO_IRQ_4 68\n#define AVR32_GPIO_IRQ_5 69\n#define AVR32_GPIO_IRQ_MSB 5\n#define AVR32_GPIO_MAX_IRQ_MSB 5\n#define AVR32_GPIO_PADDR_BITS 9\n#define AVR32_GPIO_PINS_MSB 44\n#define AVR32_GPIO_IRQS_PER_GROUP 8\n#define AVR32_GPIO_NUMBER_OF_PINS 45\n#define AVR32_GPIO_PADDR_MSB 8\n#define AVR32_GPIO_PDATA_MSB 31\n#define AVR32_GPIO_PORT_LENGTH 2\n\n/* GPIO_LOCAL */\n#define AVR32_GPIO_LOCAL_ADDRESS 0x40000000\n#define AVR32_GPIO_LOCAL (*((volatile avr32_gpio_local_t*)AVR32_GPIO_LOCAL_ADDRESS))\n\n#include \"avr32/gpio_110.h\"\n\n/* HMATRIX */\n\n/* HMATRIX */\n#define AVR32_HMATRIX_ADDRESS 0xFFFE1000\n#define AVR32_HMATRIX (*((volatile avr32_hmatrix_t*)AVR32_HMATRIX_ADDRESS))\n#define AVR32_HMATRIX_MASTER_CPU_DATA 0\n#define AVR32_HMATRIX_MASTER_CPU_INSTRUCTION 1\n#define AVR32_HMATRIX_MASTER_CPU_SAB 2\n#define AVR32_HMATRIX_MASTER_MACB_DMA 4\n#define AVR32_HMATRIX_MASTER_NUM 5\n#define AVR32_HMATRIX_MASTER_PDCA 3\n#define AVR32_HMATRIX_MASTER_USBB_DMA 5\n#define AVR32_HMATRIX_SLAVE_EBI 5\n#define AVR32_HMATRIX_SLAVE_FLASH 0\n#define AVR32_HMATRIX_SLAVE_NUM 5\n#define AVR32_HMATRIX_SLAVE_PBA 1\n#define AVR32_HMATRIX_SLAVE_PBB 2\n#define AVR32_HMATRIX_SLAVE_SRAM 3\n#define AVR32_HMATRIX_SLAVE_USBB_DPRAM 4\n\n//#include \"avr32/hmatrix_230.h\"\n\n/* JTAG */\n\n/* JTAG */\n#define AVR32_JTAG_TDI_0_PIN 0\n#define AVR32_JTAG_TDO_0_PIN 1\n#define AVR32_JTAG_TMS_0_PIN 2\n\n/* PDCA */\n\n/* PDCA */\n#define AVR32_PDCA_ADDRESS 0xFFFF0000\n#define AVR32_PDCA (*((volatile avr32_pdca_t*)AVR32_PDCA_ADDRESS))\n#define AVR32_PDCA_IRQ_0 96\n#define AVR32_PDCA_IRQ_1 97\n#define AVR32_PDCA_IRQ_2 98\n#define AVR32_PDCA_IRQ_3 99\n#define AVR32_PDCA_IRQ_4 100\n#define AVR32_PDCA_IRQ_5 101\n#define AVR32_PDCA_IRQ_6 102\n#define AVR32_PDCA_CHANNEL_LENGTH 0x7\n#define AVR32_PDCA_PID_ADC_RX 0\n#define AVR32_PDCA_PID_SPI_RX 6\n#define AVR32_PDCA_PID_SPI_TX 12\n#define AVR32_PDCA_PID_SSC_RX 1\n#define AVR32_PDCA_PID_SSC_TX 7\n#define AVR32_PDCA_PID_TWI_RX 5\n#define AVR32_PDCA_PID_TWI_TX 11\n#define AVR32_PDCA_PID_USART0_RX 2\n#define AVR32_PDCA_PID_USART0_TX 8\n#define AVR32_PDCA_PID_USART1_RX 3\n#define AVR32_PDCA_PID_USART1_TX 9\n#define AVR32_PDCA_PID_USART2_RX 4\n#define AVR32_PDCA_PID_USART2_TX 10\n\n//#include \"avr32/pdca_102.h\"\n\n/* PLL */\n\n/* PLL0 */\n#define AVR32_PLL0_DN_0_PIN 13\n#define AVR32_PLL0_FDIV_0_PIN 15\n#define AVR32_PLL0_FDIV_TEST_0_PIN 16\n#define AVR32_PLL0_LOCK_0_PIN 10\n#define AVR32_PLL0_PLLCLK_0_PIN 9\n#define AVR32_PLL0_UP_0_PIN 14\n\n/* PLL1 */\n#define AVR32_PLL1_DN_0_PIN 5\n#define AVR32_PLL1_FDIV_0_PIN 7\n#define AVR32_PLL1_FDIV_TEST_0_PIN 8\n#define AVR32_PLL1_LOCK_0_PIN 4\n#define AVR32_PLL1_PLLCLK_0_PIN 3\n#define AVR32_PLL1_UP_0_PIN 6\n\n/* PM */\n\n/* PM */\n#define AVR32_PM_ADDRESS 0xFFFF0C00\n#define AVR32_PM (*((volatile avr32_pm_t*)AVR32_PM_ADDRESS))\n#define AVR32_PM_IRQ 41\n#define AVR32_PM_CPU_MAX_FREQ 60000000\n#define AVR32_PM_GCLK_ABDAC 4\n#define AVR32_PM_GCLK_MSB 3\n#define AVR32_PM_GCLK_NUM 5\n#define AVR32_PM_GCLK_USBB 3\n#define AVR32_PM_GPLP_NUM 2\n#define AVR32_PM_HSB_MAX_FREQ 60000000\n#define AVR32_PM_PBA_MAX_FREQ 60000000\n#define AVR32_PM_PBB_MAX_FREQ 60000000\n#define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000\n#define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000\n#define AVR32_PM_PLL_VCO_RANGE1_MAX_FREQ 180000000\n#define AVR32_PM_PLL_VCO_RANGE1_MIN_FREQ 80000000\n#define AVR32_PM_RCOSC_CALIBRATION_BITS 10\n#define AVR32_PM_RCOSC_FREQUENCY 115200\n#define AVR32_PM_GCLK_0_PIN 3\n#define AVR32_PM_GCLK_0_FUNCTION 1\n#define AVR32_PM_GCLK_1_PIN 4\n#define AVR32_PM_GCLK_1_FUNCTION 1\n#define AVR32_PM_GCLK_2_0_PIN 30\n#define AVR32_PM_GCLK_2_0_FUNCTION 2\n#define AVR32_PM_GCLK_2_1_PIN 14\n#define AVR32_PM_GCLK_2_1_FUNCTION 3\n#define AVR32_PM_RSTM_N_0_PIN 27\n#define AVR32_PM_XIN0_0_PIN 18\n#define AVR32_PM_XIN1_0_PIN 28\n#define AVR32_PM_XIN32_0_PIN 11\n#define AVR32_PM_XOUT0_0_PIN 19\n#define AVR32_PM_XOUT1_0_PIN 29\n#define AVR32_PM_XOUT32_0_PIN 12\n\n//#include \"avr32/pm_231.h\"\n\n/* PULLUP */\n\n/* PULLUP */\n#define AVR32_PULLUP_LPC_PULLUP_0_0_PIN 28\n#define AVR32_PULLUP_LPC_PULLUP_0_1_PIN 29\n#define AVR32_PULLUP_LPC_PULLUP_0_2_PIN 30\n#define AVR32_PULLUP_LPC_PULLUP_0_3_PIN 31\n#define AVR32_PULLUP_LPC_PULLUP_0_4_PIN 32\n#define AVR32_PULLUP_LPC_PULLUP_0_5_PIN 33\n#define AVR32_PULLUP_LPC_PULLUP_0_6_PIN 34\n#define AVR32_PULLUP_LPC_PULLUP_0_7_PIN 35\n#define AVR32_PULLUP_LPC_PULLUP_0_8_PIN 36\n#define AVR32_PULLUP_LPC_PULLUP_0_9_PIN 37\n#define AVR32_PULLUP_LPC_PULLUP_0_10_PIN 38\n#define AVR32_PULLUP_LPC_PULLUP_0_11_PIN 39\n#define AVR32_PULLUP_LPC_PULLUP_0_12_PIN 40\n#define AVR32_PULLUP_LPC_PULLUP_0_13_PIN 41\n#define AVR32_PULLUP_LPC_PULLUP_0_14_PIN 42\n#define AVR32_PULLUP_LPC_PULLUP_0_15_PIN 43\n\n/* PWM */\n\n/* PWM */\n#define AVR32_PWM_ADDRESS 0xFFFF3000\n#define AVR32_PWM (*((volatile avr32_pwm_t*)AVR32_PWM_ADDRESS))\n#define AVR32_PWM_IRQ 384\n#define AVR32_PWM_CHANNEL_LENGTH 0x7\n#define AVR32_PWM_LINES_MSB 6\n#define AVR32_PWM_0_0_PIN 7\n#define AVR32_PWM_0_0_FUNCTION 0\n#define AVR32_PWM_1_0_PIN 8\n#define AVR32_PWM_1_0_FUNCTION 0\n#define AVR32_PWM_2_0_PIN 21\n#define AVR32_PWM_2_0_FUNCTION 0\n#define AVR32_PWM_6_0_PIN 22\n#define AVR32_PWM_6_0_FUNCTION 0\n#define AVR32_PWM_2_1_PIN 13\n#define AVR32_PWM_2_1_FUNCTION 1\n#define AVR32_PWM_3_0_PIN 14\n#define AVR32_PWM_3_0_FUNCTION 1\n#define AVR32_PWM_4_0_PIN 15\n#define AVR32_PWM_4_0_FUNCTION 1\n#define AVR32_PWM_5_0_PIN 18\n#define AVR32_PWM_5_0_FUNCTION 1\n#define AVR32_PWM_6_1_PIN 19\n#define AVR32_PWM_6_1_FUNCTION 1\n#define AVR32_PWM_3_1_PIN 25\n#define AVR32_PWM_3_1_FUNCTION 1\n#define AVR32_PWM_4_1_PIN 28\n#define AVR32_PWM_4_1_FUNCTION 1\n#define AVR32_PWM_0_1_PIN 11\n#define AVR32_PWM_0_1_FUNCTION 2\n#define AVR32_PWM_1_1_PIN 12\n#define AVR32_PWM_1_1_FUNCTION 2\n#define AVR32_PWM_4_2_PIN 16\n#define AVR32_PWM_4_2_FUNCTION 2\n#define AVR32_PWM_6_2_PIN 31\n#define AVR32_PWM_6_2_FUNCTION 2\n#define AVR32_PWM_5_1_PIN 37\n#define AVR32_PWM_5_1_FUNCTION 2\n#define AVR32_PWM_0_2_PIN 23\n#define AVR32_PWM_0_2_FUNCTION 3\n#define AVR32_PWM_1_2_PIN 24\n#define AVR32_PWM_1_2_FUNCTION 3\n\n#include \"avr32/pwm_130.h\"\n\n/* RTC */\n\n/* RTC */\n#define AVR32_RTC_ADDRESS 0xFFFF0D00\n#define AVR32_RTC (*((volatile avr32_rtc_t*)AVR32_RTC_ADDRESS))\n#define AVR32_RTC_IRQ 40\n\n//#include \"avr32/rtc_2311.h\"\n\n/* SPI */\n\n/* SPI */\n#define AVR32_SPI_ADDRESS 0xFFFF2400\n#define AVR32_SPI (*((volatile avr32_spi_t*)AVR32_SPI_ADDRESS))\n#define AVR32_SPI_IRQ 288\n#define AVR32_SPI_CS_MSB 3\n#define AVR32_SPI_MISO_0_0_PIN 25\n#define AVR32_SPI_MISO_0_0_FUNCTION 0\n#define AVR32_SPI_MISO_0_1_PIN 18\n#define AVR32_SPI_MISO_0_1_FUNCTION 2\n#define AVR32_SPI_MISO_0_2_PIN 28\n#define AVR32_SPI_MISO_0_2_FUNCTION 2\n#define AVR32_SPI_MOSI_0_0_PIN 14\n#define AVR32_SPI_MOSI_0_0_FUNCTION 0\n#define AVR32_SPI_MOSI_0_1_PIN 19\n#define AVR32_SPI_MOSI_0_1_FUNCTION 2\n#define AVR32_SPI_MOSI_0_2_PIN 29\n#define AVR32_SPI_MOSI_0_2_FUNCTION 2\n#define AVR32_SPI_NPCS_0_0_PIN 16\n#define AVR32_SPI_NPCS_0_0_FUNCTION 0\n#define AVR32_SPI_NPCS_1_0_PIN 17\n#define AVR32_SPI_NPCS_1_0_FUNCTION 0\n#define AVR32_SPI_NPCS_2_0_PIN 9\n#define AVR32_SPI_NPCS_2_0_FUNCTION 1\n#define AVR32_SPI_NPCS_3_0_PIN 10\n#define AVR32_SPI_NPCS_3_0_FUNCTION 1\n#define AVR32_SPI_NPCS_1_1_PIN 23\n#define AVR32_SPI_NPCS_1_1_FUNCTION 1\n#define AVR32_SPI_NPCS_0_1_PIN 24\n#define AVR32_SPI_NPCS_0_1_FUNCTION 1\n#define AVR32_SPI_NPCS_3_1_PIN 36\n#define AVR32_SPI_NPCS_3_1_FUNCTION 1\n#define AVR32_SPI_NPCS_2_1_PIN 37\n#define AVR32_SPI_NPCS_2_1_FUNCTION 1\n#define AVR32_SPI_SCK_0_0_PIN 15\n#define AVR32_SPI_SCK_0_0_FUNCTION 0\n#define AVR32_SPI_SCK_0_1_PIN 17\n#define AVR32_SPI_SCK_0_1_FUNCTION 2\n\n#include \"avr32/spi_199.h\"\n\n/* SSC */\n\n/* SSC */\n#define AVR32_SSC_ADDRESS 0xFFFF3400\n#define AVR32_SSC (*((volatile avr32_ssc_t*)AVR32_SSC_ADDRESS))\n#define AVR32_SSC_IRQ 416\n#define AVR32_SSC_RX_CLOCK_0_0_PIN 38\n#define AVR32_SSC_RX_CLOCK_0_0_FUNCTION 0\n#define AVR32_SSC_RX_CLOCK_0_1_PIN 8\n#define AVR32_SSC_RX_CLOCK_0_1_FUNCTION 3\n#define AVR32_SSC_RX_CLOCK_0_2_PIN 13\n#define AVR32_SSC_RX_CLOCK_0_2_FUNCTION 3\n#define AVR32_SSC_RX_DATA_0_0_PIN 39\n#define AVR32_SSC_RX_DATA_0_0_FUNCTION 0\n#define AVR32_SSC_RX_DATA_0_1_PIN 11\n#define AVR32_SSC_RX_DATA_0_1_FUNCTION 3\n#define AVR32_SSC_RX_FRAME_SYNC_0_0_PIN 40\n#define AVR32_SSC_RX_FRAME_SYNC_0_0_FUNCTION 0\n#define AVR32_SSC_RX_FRAME_SYNC_0_1_PIN 7\n#define AVR32_SSC_RX_FRAME_SYNC_0_1_FUNCTION 3\n#define AVR32_SSC_RX_FRAME_SYNC_0_2_PIN 18\n#define AVR32_SSC_RX_FRAME_SYNC_0_2_FUNCTION 3\n#define AVR32_SSC_TX_CLOCK_0_0_PIN 41\n#define AVR32_SSC_TX_CLOCK_0_0_FUNCTION 0\n#define AVR32_SSC_TX_CLOCK_0_1_PIN 19\n#define AVR32_SSC_TX_CLOCK_0_1_FUNCTION 3\n#define AVR32_SSC_TX_DATA_0_0_PIN 42\n#define AVR32_SSC_TX_DATA_0_0_FUNCTION 0\n#define AVR32_SSC_TX_DATA_0_1_PIN 20\n#define AVR32_SSC_TX_DATA_0_1_FUNCTION 3\n#define AVR32_SSC_TX_FRAME_SYNC_0_0_PIN 43\n#define AVR32_SSC_TX_FRAME_SYNC_0_0_FUNCTION 0\n#define AVR32_SSC_TX_FRAME_SYNC_0_1_PIN 21\n#define AVR32_SSC_TX_FRAME_SYNC_0_1_FUNCTION 3\n\n//#include \"avr32/ssc_310.h\"\n\n/* TC */\n\n/* TC */\n#define AVR32_TC_ADDRESS 0xFFFF3800\n#define AVR32_TC (*((volatile avr32_tc_t*)AVR32_TC_ADDRESS))\n#define AVR32_TC_IRQ0 448\n#define AVR32_TC_IRQ1 449\n#define AVR32_TC_IRQ2 450\n#define AVR32_TC_A0_0_0_PIN 32\n#define AVR32_TC_A0_0_0_FUNCTION 0\n#define AVR32_TC_A0_0_1_PIN 26\n#define AVR32_TC_A0_0_1_FUNCTION 2\n#define AVR32_TC_A1_0_0_PIN 21\n#define AVR32_TC_A1_0_0_FUNCTION 1\n#define AVR32_TC_A1_0_1_PIN 34\n#define AVR32_TC_A1_0_1_FUNCTION 1\n#define AVR32_TC_A2_0_0_PIN 11\n#define AVR32_TC_A2_0_0_FUNCTION 1\n#define AVR32_TC_A2_0_1_PIN 42\n#define AVR32_TC_A2_0_1_FUNCTION 1\n#define AVR32_TC_B0_0_0_PIN 33\n#define AVR32_TC_B0_0_0_FUNCTION 0\n#define AVR32_TC_B0_0_1_PIN 27\n#define AVR32_TC_B0_0_1_FUNCTION 2\n#define AVR32_TC_B1_0_0_PIN 22\n#define AVR32_TC_B1_0_0_FUNCTION 1\n#define AVR32_TC_B1_0_1_PIN 35\n#define AVR32_TC_B1_0_1_FUNCTION 1\n#define AVR32_TC_B2_0_0_PIN 12\n#define AVR32_TC_B2_0_0_FUNCTION 1\n#define AVR32_TC_B2_0_1_PIN 43\n#define AVR32_TC_B2_0_1_FUNCTION 1\n#define AVR32_TC_CLK0_0_0_PIN 29\n#define AVR32_TC_CLK0_0_0_FUNCTION 0\n#define AVR32_TC_CLK0_0_1_PIN 20\n#define AVR32_TC_CLK0_0_1_FUNCTION 1\n#define AVR32_TC_CLK1_0_0_PIN 16\n#define AVR32_TC_CLK1_0_0_FUNCTION 1\n#define AVR32_TC_CLK1_0_1_PIN 29\n#define AVR32_TC_CLK1_0_1_FUNCTION 1\n#define AVR32_TC_CLK2_0_0_PIN 17\n#define AVR32_TC_CLK2_0_0_FUNCTION 1\n#define AVR32_TC_CLK2_0_1_PIN 36\n#define AVR32_TC_CLK2_0_1_FUNCTION 2\n\n//#include \"avr32/tc_222.h\"\n\n/* TWI */\n\n/* TWI */\n#define AVR32_TWI_ADDRESS 0xFFFF2C00\n#define AVR32_TWI (*((volatile avr32_twi_t*)AVR32_TWI_ADDRESS))\n#define AVR32_TWI_IRQ 352\n#define AVR32_TWI_SCL_0_0_PIN 9\n#define AVR32_TWI_SCL_0_0_FUNCTION 0\n#define AVR32_TWI_SCL_0_1_PIN 9\n#define AVR32_TWI_SCL_INPUT_TEST_0_PIN 5\n#define AVR32_TWI_SCL_OUTPUT_TEST_0_PIN 6\n#define AVR32_TWI_SDA_0_0_PIN 10\n#define AVR32_TWI_SDA_0_0_FUNCTION 0\n#define AVR32_TWI_SDA_0_1_PIN 10\n#define AVR32_TWI_SDA_INPUT_TEST_0_PIN 3\n#define AVR32_TWI_SDA_OUTPUT_TEST_0_PIN 4\n\n//#include \"avr32/twi_211.h\"\n\n/* USART */\n\n/* USART0 */\n#define AVR32_USART0_ADDRESS 0xFFFF1400\n#define AVR32_USART0 (*((volatile avr32_usart_t*)AVR32_USART0_ADDRESS))\n#define AVR32_USART0_IRQ 160\n#define AVR32_USART0_CLK_0_0_PIN 28\n#define AVR32_USART0_CLK_0_0_FUNCTION 0\n#define AVR32_USART0_CLK_0_1_PIN 13\n#define AVR32_USART0_CLK_0_1_FUNCTION 2\n#define AVR32_USART0_CTS_0_PIN 12\n#define AVR32_USART0_CTS_0_FUNCTION 0\n#define AVR32_USART0_RTS_0_PIN 11\n#define AVR32_USART0_RTS_0_FUNCTION 0\n#define AVR32_USART0_RXD_0_0_PIN 18\n#define AVR32_USART0_RXD_0_0_FUNCTION 0\n#define AVR32_USART0_RXD_0_1_PIN 42\n#define AVR32_USART0_RXD_0_1_FUNCTION 2\n#define AVR32_USART0_TXD_0_0_PIN 19\n#define AVR32_USART0_TXD_0_0_FUNCTION 0\n#define AVR32_USART0_TXD_0_1_PIN 43\n#define AVR32_USART0_TXD_0_1_FUNCTION 2\n\n/* USART1 */\n#define AVR32_USART1_ADDRESS 0xFFFF1800\n#define AVR32_USART1 (*((volatile avr32_usart_t*)AVR32_USART1_ADDRESS))\n#define AVR32_USART1_IRQ 192\n#define AVR32_USART1_CLK_0_PIN 20\n#define AVR32_USART1_CLK_0_FUNCTION 0\n#define AVR32_USART1_CTS_0_0_PIN 36\n#define AVR32_USART1_CTS_0_0_FUNCTION 0\n#define AVR32_USART1_CTS_0_1_PIN 9\n#define AVR32_USART1_CTS_0_1_FUNCTION 2\n#define AVR32_USART1_DCD_0_0_PIN 38\n#define AVR32_USART1_DCD_0_0_FUNCTION 1\n#define AVR32_USART1_DCD_0_1_PIN 5\n#define AVR32_USART1_DCD_0_1_FUNCTION 2\n#define AVR32_USART1_DSR_0_0_PIN 39\n#define AVR32_USART1_DSR_0_0_FUNCTION 1\n#define AVR32_USART1_DSR_0_1_PIN 6\n#define AVR32_USART1_DSR_0_1_FUNCTION 2\n#define AVR32_USART1_DTR_0_0_PIN 40\n#define AVR32_USART1_DTR_0_0_FUNCTION 1\n#define AVR32_USART1_DTR_0_1_PIN 7\n#define AVR32_USART1_DTR_0_1_FUNCTION 2\n#define AVR32_USART1_RI_0_0_PIN 41\n#define AVR32_USART1_RI_0_0_FUNCTION 1\n#define AVR32_USART1_RI_0_1_PIN 8\n#define AVR32_USART1_RI_0_1_FUNCTION 2\n#define AVR32_USART1_RTS_0_0_PIN 37\n#define AVR32_USART1_RTS_0_0_FUNCTION 0\n#define AVR32_USART1_RTS_0_1_PIN 10\n#define AVR32_USART1_RTS_0_1_FUNCTION 2\n#define AVR32_USART1_RXD_0_0_PIN 24\n#define AVR32_USART1_RXD_0_0_FUNCTION 0\n#define AVR32_USART1_RXD_0_1_PIN 35\n#define AVR32_USART1_RXD_0_1_FUNCTION 2\n#define AVR32_USART1_RXD_0_2_PIN 17\n#define AVR32_USART1_RXD_0_2_FUNCTION 3\n#define AVR32_USART1_TXD_0_0_PIN 23\n#define AVR32_USART1_TXD_0_0_FUNCTION 0\n#define AVR32_USART1_TXD_0_1_PIN 34\n#define AVR32_USART1_TXD_0_1_FUNCTION 2\n#define AVR32_USART1_TXD_0_2_PIN 12\n#define AVR32_USART1_TXD_0_2_FUNCTION 3\n\n/* USART2 */\n#define AVR32_USART2_ADDRESS 0xFFFF1C00\n#define AVR32_USART2 (*((volatile avr32_usart_t*)AVR32_USART2_ADDRESS))\n#define AVR32_USART2_IRQ 224\n#define AVR32_USART2_CLK_0_PIN 15\n#define AVR32_USART2_CLK_0_FUNCTION 2\n#define AVR32_USART2_CTS_0_PIN 32\n#define AVR32_USART2_CTS_0_FUNCTION 2\n#define AVR32_USART2_RTS_0_PIN 33\n#define AVR32_USART2_RTS_0_FUNCTION 2\n#define AVR32_USART2_RXD_0_0_PIN 27\n#define AVR32_USART2_RXD_0_0_FUNCTION 1\n#define AVR32_USART2_RXD_0_1_PIN 20\n#define AVR32_USART2_RXD_0_1_FUNCTION 2\n#define AVR32_USART2_TXD_0_0_PIN 26\n#define AVR32_USART2_TXD_0_0_FUNCTION 1\n#define AVR32_USART2_TXD_0_1_PIN 21\n#define AVR32_USART2_TXD_0_1_FUNCTION 2\n\n//#include \"avr32/usart_400.h\"\n\n/* USBB */\n\n/* USBB */\n#define AVR32_USBB_ADDRESS 0xFFFE0000\n#define AVR32_USBB (*((volatile avr32_usbb_t*)AVR32_USBB_ADDRESS))\n#define AVR32_USBB_IRQ 544\n#define AVR32_USBB_EPT_NUM 7\n#define AVR32_USBB_ENABLE_TEST_0_PIN 22\n#define AVR32_USBB_EOPN_TEST_0_PIN 23\n#define AVR32_USBB_FS_TEST_0_PIN 5\n#define AVR32_USBB_OEN_TEST_0_PIN 6\n#define AVR32_USBB_ONN_TEST_0_PIN 7\n#define AVR32_USBB_PDONDM_TEST_0_PIN 8\n#define AVR32_USBB_PDONDP_TEST_0_PIN 9\n#define AVR32_USBB_PUIDLE_TEST_0_PIN 10\n#define AVR32_USBB_PUON_TEST_0_PIN 13\n#define AVR32_USBB_RXDM_TEST_0_PIN 14\n#define AVR32_USBB_RXDP_TEST_0_PIN 15\n#define AVR32_USBB_RXD_TEST_0_PIN 16\n#define AVR32_USBB_SESSVLD_TEST_0_PIN 17\n#define AVR32_USBB_TXD_TEST_0_PIN 24\n#define AVR32_USBB_USB_ID_0_0_PIN 26\n#define AVR32_USBB_USB_ID_0_0_FUNCTION 0\n#define AVR32_USBB_USB_ID_0_1_PIN 3\n#define AVR32_USBB_USB_ID_0_1_FUNCTION 2\n#define AVR32_USBB_USB_VBOF_0_0_PIN 27\n#define AVR32_USBB_USB_VBOF_0_0_FUNCTION 0\n#define AVR32_USBB_USB_VBOF_0_1_PIN 4\n#define AVR32_USBB_USB_VBOF_0_1_FUNCTION 2\n#define AVR32_USBB_VAVBUSVLD_TEST_0_PIN 19\n#define AVR32_USBB_VBUSDISCHARGE_TEST_0_PIN 20\n#define AVR32_USBB_VBUSPULSING_TEST_0_PIN 21\n\n//#include \"avr32/usbb_3101.h\"\n\n/* WDT */\n\n/* WDT */\n#define AVR32_WDT_ADDRESS 0xFFFF0D30\n#define AVR32_WDT (*((volatile avr32_wdt_t*)AVR32_WDT_ADDRESS))\n#define AVR32_WDT_WDTEXTRST_MSB 1\n\n//#include \"avr32/wdt_2311.h\"\n\n/* PAD->GPIO bits mapping */\n#define AVR32_PIN_PA03 3\n#define AVR32_PIN_PA04 4\n#define AVR32_PIN_PA05 5\n#define AVR32_PIN_PA06 6\n#define AVR32_PIN_PA07 7\n#define AVR32_PIN_PA08 8\n#define AVR32_PIN_PA09 9\n#define AVR32_PIN_PA10 10\n#define AVR32_PIN_PA11 11\n#define AVR32_PIN_PA12 12\n#define AVR32_PIN_PA13 13\n#define AVR32_PIN_PA14 14\n#define AVR32_PIN_PA15 15\n#define AVR32_PIN_PA16 16\n#define AVR32_PIN_PA17 17\n#define AVR32_PIN_PA18 18\n#define AVR32_PIN_PA19 19\n#define AVR32_PIN_PA20 20\n#define AVR32_PIN_PA21 21\n#define AVR32_PIN_PA22 22\n#define AVR32_PIN_PA23 23\n#define AVR32_PIN_PA24 24\n#define AVR32_PIN_PA25 25\n#define AVR32_PIN_PA26 26\n#define AVR32_PIN_PA27 27\n#define AVR32_PIN_PA28 28\n#define AVR32_PIN_PA29 29\n#define AVR32_PIN_PA30 30\n#define AVR32_PIN_PA31 31\n#define AVR32_PIN_PB00 32\n#define AVR32_PIN_PB01 33\n#define AVR32_PIN_PB02 34\n#define AVR32_PIN_PB03 35\n#define AVR32_PIN_PB04 36\n#define AVR32_PIN_PB05 37\n#define AVR32_PIN_PB06 38\n#define AVR32_PIN_PB07 39\n#define AVR32_PIN_PB08 40\n#define AVR32_PIN_PB09 41\n#define AVR32_PIN_PB10 42\n#define AVR32_PIN_PB11 43\n#define AVR32_PIN_TDI 0\n#define AVR32_PIN_TDO 1\n#define AVR32_PIN_TMS 2\n\n/* #ifndef AVR32_UC3B0512_H_INCLUDED */\n#endif\n" }, { "path": "firmware/mock_hardware/include/avr32/usart_400.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3A0512\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_USART_400_H_INCLUDED\n#define AVR32_USART_400_H_INCLUDED\n\n#define AVR32_USART_H_VERSION 400\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_USART_\n - Bitfield mask: AVR32_USART__\n - Bitfield offset: AVR32_USART___OFFSET\n - Bitfield size: AVR32_USART___SIZE\n - Bitfield values: AVR32_USART___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_USART_\n - Bitfield offset: AVR32_USART__OFFSET\n - Bitfield size: AVR32_USART__SIZE\n - Bitfield values: AVR32_USART__\n - Bitfield values: AVR32_USART_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_USART_1 0x00000000\n#define AVR32_USART_1_5 0x00000001\n#define AVR32_USART_2 0x00000002\n#define AVR32_USART_5 0x00000000\n#define AVR32_USART_6 0x00000001\n#define AVR32_USART_7 0x00000002\n#define AVR32_USART_8 0x00000003\n#define AVR32_USART_BRGR 0x00000020\n#define AVR32_USART_BRGR_CD 0\n#define AVR32_USART_BRGR_CD_BYPASS 0x00000001\n#define AVR32_USART_BRGR_CD_DISABLE 0x00000000\n#define AVR32_USART_BRGR_CD_MASK 0x0000ffff\n#define AVR32_USART_BRGR_CD_OFFSET 0\n#define AVR32_USART_BRGR_CD_SIZE 16\n#define AVR32_USART_BRGR_FP 16\n#define AVR32_USART_BRGR_FP_MASK 0x00070000\n#define AVR32_USART_BRGR_FP_OFFSET 16\n#define AVR32_USART_BRGR_FP_SIZE 3\n#define AVR32_USART_BYPASS 0x00000001\n#define AVR32_USART_CD 0\n#define AVR32_USART_CD_BYPASS 0x00000001\n#define AVR32_USART_CD_DISABLE 0x00000000\n#define AVR32_USART_CD_MASK 0x0000ffff\n#define AVR32_USART_CD_OFFSET 0\n#define AVR32_USART_CD_SIZE 16\n#define AVR32_USART_CHKDIS 3\n#define AVR32_USART_CHKDIS_MASK 0x00000008\n#define AVR32_USART_CHKDIS_OFFSET 3\n#define AVR32_USART_CHKDIS_SIZE 1\n#define AVR32_USART_CHKTYP 4\n#define AVR32_USART_CHKTYP_MASK 0x00000010\n#define AVR32_USART_CHKTYP_OFFSET 4\n#define AVR32_USART_CHKTYP_SIZE 1\n#define AVR32_USART_CHMODE 14\n#define AVR32_USART_CHMODE_ECHO 0x00000001\n#define AVR32_USART_CHMODE_LOCAL_LOOP 0x00000002\n#define AVR32_USART_CHMODE_MASK 0x0000c000\n#define AVR32_USART_CHMODE_NORMAL 0x00000000\n#define AVR32_USART_CHMODE_OFFSET 14\n#define AVR32_USART_CHMODE_REMOTE_LOOP 0x00000003\n#define AVR32_USART_CHMODE_SIZE 2\n#define AVR32_USART_CHRL 6\n#define AVR32_USART_CHRL_5 0x00000000\n#define AVR32_USART_CHRL_6 0x00000001\n#define AVR32_USART_CHRL_7 0x00000002\n#define AVR32_USART_CHRL_8 0x00000003\n#define AVR32_USART_CHRL_MASK 0x000000c0\n#define AVR32_USART_CHRL_OFFSET 6\n#define AVR32_USART_CHRL_SIZE 2\n#define AVR32_USART_CLKO 18\n#define AVR32_USART_CLKO_MASK 0x00040000\n#define AVR32_USART_CLKO_OFFSET 18\n#define AVR32_USART_CLKO_SIZE 1\n#define AVR32_USART_COMM_RX 31\n#define AVR32_USART_COMM_RX_MASK 0x80000000\n#define AVR32_USART_COMM_RX_OFFSET 31\n#define AVR32_USART_COMM_RX_SIZE 1\n#define AVR32_USART_COMM_TX 30\n#define AVR32_USART_COMM_TX_MASK 0x40000000\n#define AVR32_USART_COMM_TX_OFFSET 30\n#define AVR32_USART_COMM_TX_SIZE 1\n#define AVR32_USART_CR 0x00000000\n#define AVR32_USART_CR_COMM_RX 31\n#define AVR32_USART_CR_COMM_RX_MASK 0x80000000\n#define AVR32_USART_CR_COMM_RX_OFFSET 31\n#define AVR32_USART_CR_COMM_RX_SIZE 1\n#define AVR32_USART_CR_COMM_TX 30\n#define AVR32_USART_CR_COMM_TX_MASK 0x40000000\n#define AVR32_USART_CR_COMM_TX_OFFSET 30\n#define AVR32_USART_CR_COMM_TX_SIZE 1\n#define AVR32_USART_CR_DTRDIS 17\n#define AVR32_USART_CR_DTRDIS_MASK 0x00020000\n#define AVR32_USART_CR_DTRDIS_OFFSET 17\n#define AVR32_USART_CR_DTRDIS_SIZE 1\n#define AVR32_USART_CR_DTREN 16\n#define AVR32_USART_CR_DTREN_MASK 0x00010000\n#define AVR32_USART_CR_DTREN_OFFSET 16\n#define AVR32_USART_CR_DTREN_SIZE 1\n#define AVR32_USART_CR_LINABT 20\n#define AVR32_USART_CR_LINABT_MASK 0x00100000\n#define AVR32_USART_CR_LINABT_OFFSET 20\n#define AVR32_USART_CR_LINABT_SIZE 1\n#define AVR32_USART_CR_LINWKUP 21\n#define AVR32_USART_CR_LINWKUP_MASK 0x00200000\n#define AVR32_USART_CR_LINWKUP_OFFSET 21\n#define AVR32_USART_CR_LINWKUP_SIZE 1\n#define AVR32_USART_CR_RETTO 15\n#define AVR32_USART_CR_RETTO_MASK 0x00008000\n#define AVR32_USART_CR_RETTO_OFFSET 15\n#define AVR32_USART_CR_RETTO_SIZE 1\n#define AVR32_USART_CR_RSTIT 13\n#define AVR32_USART_CR_RSTIT_MASK 0x00002000\n#define AVR32_USART_CR_RSTIT_OFFSET 13\n#define AVR32_USART_CR_RSTIT_SIZE 1\n#define AVR32_USART_CR_RSTNACK 14\n#define AVR32_USART_CR_RSTNACK_MASK 0x00004000\n#define AVR32_USART_CR_RSTNACK_OFFSET 14\n#define AVR32_USART_CR_RSTNACK_SIZE 1\n#define AVR32_USART_CR_RSTRX 2\n#define AVR32_USART_CR_RSTRX_MASK 0x00000004\n#define AVR32_USART_CR_RSTRX_OFFSET 2\n#define AVR32_USART_CR_RSTRX_SIZE 1\n#define AVR32_USART_CR_RSTSTA 8\n#define AVR32_USART_CR_RSTSTA_MASK 0x00000100\n#define AVR32_USART_CR_RSTSTA_OFFSET 8\n#define AVR32_USART_CR_RSTSTA_SIZE 1\n#define AVR32_USART_CR_RSTTX 3\n#define AVR32_USART_CR_RSTTX_MASK 0x00000008\n#define AVR32_USART_CR_RSTTX_OFFSET 3\n#define AVR32_USART_CR_RSTTX_SIZE 1\n#define AVR32_USART_CR_RTSDIS 19\n#define AVR32_USART_CR_RTSDIS_MASK 0x00080000\n#define AVR32_USART_CR_RTSDIS_OFFSET 19\n#define AVR32_USART_CR_RTSDIS_SIZE 1\n#define AVR32_USART_CR_RTSEN 18\n#define AVR32_USART_CR_RTSEN_MASK 0x00040000\n#define AVR32_USART_CR_RTSEN_OFFSET 18\n#define AVR32_USART_CR_RTSEN_SIZE 1\n#define AVR32_USART_CR_RXDIS 5\n#define AVR32_USART_CR_RXDIS_MASK 0x00000020\n#define AVR32_USART_CR_RXDIS_OFFSET 5\n#define AVR32_USART_CR_RXDIS_SIZE 1\n#define AVR32_USART_CR_RXEN 4\n#define AVR32_USART_CR_RXEN_MASK 0x00000010\n#define AVR32_USART_CR_RXEN_OFFSET 4\n#define AVR32_USART_CR_RXEN_SIZE 1\n#define AVR32_USART_CR_SENDA 12\n#define AVR32_USART_CR_SENDA_MASK 0x00001000\n#define AVR32_USART_CR_SENDA_OFFSET 12\n#define AVR32_USART_CR_SENDA_SIZE 1\n#define AVR32_USART_CR_STPBRK 10\n#define AVR32_USART_CR_STPBRK_MASK 0x00000400\n#define AVR32_USART_CR_STPBRK_OFFSET 10\n#define AVR32_USART_CR_STPBRK_SIZE 1\n#define AVR32_USART_CR_STTBRK 9\n#define AVR32_USART_CR_STTBRK_MASK 0x00000200\n#define AVR32_USART_CR_STTBRK_OFFSET 9\n#define AVR32_USART_CR_STTBRK_SIZE 1\n#define AVR32_USART_CR_STTTO 11\n#define AVR32_USART_CR_STTTO_MASK 0x00000800\n#define AVR32_USART_CR_STTTO_OFFSET 11\n#define AVR32_USART_CR_STTTO_SIZE 1\n#define AVR32_USART_CR_TXDIS 7\n#define AVR32_USART_CR_TXDIS_MASK 0x00000080\n#define AVR32_USART_CR_TXDIS_OFFSET 7\n#define AVR32_USART_CR_TXDIS_SIZE 1\n#define AVR32_USART_CR_TXEN 6\n#define AVR32_USART_CR_TXEN_MASK 0x00000040\n#define AVR32_USART_CR_TXEN_OFFSET 6\n#define AVR32_USART_CR_TXEN_SIZE 1\n#define AVR32_USART_CSR 0x00000014\n#define AVR32_USART_CSR_COMM_RX 31\n#define AVR32_USART_CSR_COMM_RX_MASK 0x80000000\n#define AVR32_USART_CSR_COMM_RX_OFFSET 31\n#define AVR32_USART_CSR_COMM_RX_SIZE 1\n#define AVR32_USART_CSR_COMM_TX 30\n#define AVR32_USART_CSR_COMM_TX_MASK 0x40000000\n#define AVR32_USART_CSR_COMM_TX_OFFSET 30\n#define AVR32_USART_CSR_COMM_TX_SIZE 1\n#define AVR32_USART_CSR_CTS 23\n#define AVR32_USART_CSR_CTSIC 19\n#define AVR32_USART_CSR_CTSIC_MASK 0x00080000\n#define AVR32_USART_CSR_CTSIC_OFFSET 19\n#define AVR32_USART_CSR_CTSIC_SIZE 1\n#define AVR32_USART_CSR_CTS_MASK 0x00800000\n#define AVR32_USART_CSR_CTS_OFFSET 23\n#define AVR32_USART_CSR_CTS_SIZE 1\n#define AVR32_USART_CSR_DCD 22\n#define AVR32_USART_CSR_DCDIC 18\n#define AVR32_USART_CSR_DCDIC_MASK 0x00040000\n#define AVR32_USART_CSR_DCDIC_OFFSET 18\n#define AVR32_USART_CSR_DCDIC_SIZE 1\n#define AVR32_USART_CSR_DCD_MASK 0x00400000\n#define AVR32_USART_CSR_DCD_OFFSET 22\n#define AVR32_USART_CSR_DCD_SIZE 1\n#define AVR32_USART_CSR_DSR 21\n#define AVR32_USART_CSR_DSRIC 17\n#define AVR32_USART_CSR_DSRIC_MASK 0x00020000\n#define AVR32_USART_CSR_DSRIC_OFFSET 17\n#define AVR32_USART_CSR_DSRIC_SIZE 1\n#define AVR32_USART_CSR_DSR_MASK 0x00200000\n#define AVR32_USART_CSR_DSR_OFFSET 21\n#define AVR32_USART_CSR_DSR_SIZE 1\n#define AVR32_USART_CSR_ENDRX 3\n#define AVR32_USART_CSR_ENDRX_MASK 0x00000008\n#define AVR32_USART_CSR_ENDRX_OFFSET 3\n#define AVR32_USART_CSR_ENDRX_SIZE 1\n#define AVR32_USART_CSR_ENDTX 4\n#define AVR32_USART_CSR_ENDTX_MASK 0x00000010\n#define AVR32_USART_CSR_ENDTX_OFFSET 4\n#define AVR32_USART_CSR_ENDTX_SIZE 1\n#define AVR32_USART_CSR_FRAME 6\n#define AVR32_USART_CSR_FRAME_MASK 0x00000040\n#define AVR32_USART_CSR_FRAME_OFFSET 6\n#define AVR32_USART_CSR_FRAME_SIZE 1\n#define AVR32_USART_CSR_ITERATION 10\n#define AVR32_USART_CSR_ITERATION_MASK 0x00000400\n#define AVR32_USART_CSR_ITERATION_OFFSET 10\n#define AVR32_USART_CSR_ITERATION_SIZE 1\n#define AVR32_USART_CSR_LINBE 25\n#define AVR32_USART_CSR_LINBE_MASK 0x02000000\n#define AVR32_USART_CSR_LINBE_OFFSET 25\n#define AVR32_USART_CSR_LINBE_SIZE 1\n#define AVR32_USART_CSR_LINCE 28\n#define AVR32_USART_CSR_LINCE_MASK 0x10000000\n#define AVR32_USART_CSR_LINCE_OFFSET 28\n#define AVR32_USART_CSR_LINCE_SIZE 1\n#define AVR32_USART_CSR_LINIPE 27\n#define AVR32_USART_CSR_LINIPE_MASK 0x08000000\n#define AVR32_USART_CSR_LINIPE_OFFSET 27\n#define AVR32_USART_CSR_LINIPE_SIZE 1\n#define AVR32_USART_CSR_LINIR 14\n#define AVR32_USART_CSR_LINIR_MASK 0x00004000\n#define AVR32_USART_CSR_LINIR_OFFSET 14\n#define AVR32_USART_CSR_LINIR_SIZE 1\n#define AVR32_USART_CSR_LINISFE 26\n#define AVR32_USART_CSR_LINISFE_MASK 0x04000000\n#define AVR32_USART_CSR_LINISFE_OFFSET 26\n#define AVR32_USART_CSR_LINISFE_SIZE 1\n#define AVR32_USART_CSR_LINSNRE 29\n#define AVR32_USART_CSR_LINSNRE_MASK 0x20000000\n#define AVR32_USART_CSR_LINSNRE_OFFSET 29\n#define AVR32_USART_CSR_LINSNRE_SIZE 1\n#define AVR32_USART_CSR_LINTC 15\n#define AVR32_USART_CSR_LINTC_MASK 0x00008000\n#define AVR32_USART_CSR_LINTC_OFFSET 15\n#define AVR32_USART_CSR_LINTC_SIZE 1\n#define AVR32_USART_CSR_MANERR 24\n#define AVR32_USART_CSR_MANERR_MASK 0x01000000\n#define AVR32_USART_CSR_MANERR_OFFSET 24\n#define AVR32_USART_CSR_MANERR_SIZE 1\n#define AVR32_USART_CSR_NACK 13\n#define AVR32_USART_CSR_NACK_MASK 0x00002000\n#define AVR32_USART_CSR_NACK_OFFSET 13\n#define AVR32_USART_CSR_NACK_SIZE 1\n#define AVR32_USART_CSR_OVRE 5\n#define AVR32_USART_CSR_OVRE_MASK 0x00000020\n#define AVR32_USART_CSR_OVRE_OFFSET 5\n#define AVR32_USART_CSR_OVRE_SIZE 1\n#define AVR32_USART_CSR_PARE 7\n#define AVR32_USART_CSR_PARE_MASK 0x00000080\n#define AVR32_USART_CSR_PARE_OFFSET 7\n#define AVR32_USART_CSR_PARE_SIZE 1\n#define AVR32_USART_CSR_RI 20\n#define AVR32_USART_CSR_RIIC 16\n#define AVR32_USART_CSR_RIIC_MASK 0x00010000\n#define AVR32_USART_CSR_RIIC_OFFSET 16\n#define AVR32_USART_CSR_RIIC_SIZE 1\n#define AVR32_USART_CSR_RI_MASK 0x00100000\n#define AVR32_USART_CSR_RI_OFFSET 20\n#define AVR32_USART_CSR_RI_SIZE 1\n#define AVR32_USART_CSR_RXBRK 2\n#define AVR32_USART_CSR_RXBRK_MASK 0x00000004\n#define AVR32_USART_CSR_RXBRK_OFFSET 2\n#define AVR32_USART_CSR_RXBRK_SIZE 1\n#define AVR32_USART_CSR_RXBUFF 12\n#define AVR32_USART_CSR_RXBUFF_MASK 0x00001000\n#define AVR32_USART_CSR_RXBUFF_OFFSET 12\n#define AVR32_USART_CSR_RXBUFF_SIZE 1\n#define AVR32_USART_CSR_RXRDY 0\n#define AVR32_USART_CSR_RXRDY_MASK 0x00000001\n#define AVR32_USART_CSR_RXRDY_OFFSET 0\n#define AVR32_USART_CSR_RXRDY_SIZE 1\n#define AVR32_USART_CSR_TIMEOUT 8\n#define AVR32_USART_CSR_TIMEOUT_MASK 0x00000100\n#define AVR32_USART_CSR_TIMEOUT_OFFSET 8\n#define AVR32_USART_CSR_TIMEOUT_SIZE 1\n#define AVR32_USART_CSR_TXBUFE 11\n#define AVR32_USART_CSR_TXBUFE_MASK 0x00000800\n#define AVR32_USART_CSR_TXBUFE_OFFSET 11\n#define AVR32_USART_CSR_TXBUFE_SIZE 1\n#define AVR32_USART_CSR_TXEMPTY 9\n#define AVR32_USART_CSR_TXEMPTY_MASK 0x00000200\n#define AVR32_USART_CSR_TXEMPTY_OFFSET 9\n#define AVR32_USART_CSR_TXEMPTY_SIZE 1\n#define AVR32_USART_CSR_TXRDY 1\n#define AVR32_USART_CSR_TXRDY_MASK 0x00000002\n#define AVR32_USART_CSR_TXRDY_OFFSET 1\n#define AVR32_USART_CSR_TXRDY_SIZE 1\n#define AVR32_USART_CTS 23\n#define AVR32_USART_CTSIC 19\n#define AVR32_USART_CTSIC_MASK 0x00080000\n#define AVR32_USART_CTSIC_OFFSET 19\n#define AVR32_USART_CTSIC_SIZE 1\n#define AVR32_USART_CTS_MASK 0x00800000\n#define AVR32_USART_CTS_OFFSET 23\n#define AVR32_USART_CTS_SIZE 1\n#define AVR32_USART_DCD 22\n#define AVR32_USART_DCDIC 18\n#define AVR32_USART_DCDIC_MASK 0x00040000\n#define AVR32_USART_DCDIC_OFFSET 18\n#define AVR32_USART_DCDIC_SIZE 1\n#define AVR32_USART_DCD_MASK 0x00400000\n#define AVR32_USART_DCD_OFFSET 22\n#define AVR32_USART_DCD_SIZE 1\n#define AVR32_USART_DISABLE 0x00000000\n#define AVR32_USART_DLC 8\n#define AVR32_USART_DLC_MASK 0x0000ff00\n#define AVR32_USART_DLC_OFFSET 8\n#define AVR32_USART_DLC_SIZE 8\n#define AVR32_USART_DLM 5\n#define AVR32_USART_DLM_MASK 0x00000020\n#define AVR32_USART_DLM_OFFSET 5\n#define AVR32_USART_DLM_SIZE 1\n#define AVR32_USART_DRIFT 30\n#define AVR32_USART_DRIFT_MASK 0x40000000\n#define AVR32_USART_DRIFT_OFFSET 30\n#define AVR32_USART_DRIFT_SIZE 1\n#define AVR32_USART_DSNACK 21\n#define AVR32_USART_DSNACK_MASK 0x00200000\n#define AVR32_USART_DSNACK_OFFSET 21\n#define AVR32_USART_DSNACK_SIZE 1\n#define AVR32_USART_DSR 21\n#define AVR32_USART_DSRIC 17\n#define AVR32_USART_DSRIC_MASK 0x00020000\n#define AVR32_USART_DSRIC_OFFSET 17\n#define AVR32_USART_DSRIC_SIZE 1\n#define AVR32_USART_DSR_MASK 0x00200000\n#define AVR32_USART_DSR_OFFSET 21\n#define AVR32_USART_DSR_SIZE 1\n#define AVR32_USART_DTRDIS 17\n#define AVR32_USART_DTRDIS_MASK 0x00020000\n#define AVR32_USART_DTRDIS_OFFSET 17\n#define AVR32_USART_DTRDIS_SIZE 1\n#define AVR32_USART_DTREN 16\n#define AVR32_USART_DTREN_MASK 0x00010000\n#define AVR32_USART_DTREN_OFFSET 16\n#define AVR32_USART_DTREN_SIZE 1\n#define AVR32_USART_ECHO 0x00000001\n#define AVR32_USART_ENDRX 3\n#define AVR32_USART_ENDRX_MASK 0x00000008\n#define AVR32_USART_ENDRX_OFFSET 3\n#define AVR32_USART_ENDRX_SIZE 1\n#define AVR32_USART_ENDTX 4\n#define AVR32_USART_ENDTX_MASK 0x00000010\n#define AVR32_USART_ENDTX_OFFSET 4\n#define AVR32_USART_ENDTX_SIZE 1\n#define AVR32_USART_EVEN 0x00000000\n#define AVR32_USART_FIDI 0x00000040\n#define AVR32_USART_FIDI_FI_DI_RATIO 0\n#define AVR32_USART_FIDI_FI_DI_RATIO_DISABLE 0x00000000\n#define AVR32_USART_FIDI_FI_DI_RATIO_MASK 0x000007ff\n#define AVR32_USART_FIDI_FI_DI_RATIO_OFFSET 0\n#define AVR32_USART_FIDI_FI_DI_RATIO_SIZE 11\n#define AVR32_USART_FILTER 28\n#define AVR32_USART_FILTER_MASK 0x10000000\n#define AVR32_USART_FILTER_OFFSET 28\n#define AVR32_USART_FILTER_SIZE 1\n#define AVR32_USART_FI_DI_RATIO 0\n#define AVR32_USART_FI_DI_RATIO_DISABLE 0x00000000\n#define AVR32_USART_FI_DI_RATIO_MASK 0x000007ff\n#define AVR32_USART_FI_DI_RATIO_OFFSET 0\n#define AVR32_USART_FI_DI_RATIO_SIZE 11\n#define AVR32_USART_FP 16\n#define AVR32_USART_FP_MASK 0x00070000\n#define AVR32_USART_FP_OFFSET 16\n#define AVR32_USART_FP_SIZE 3\n#define AVR32_USART_FRAME 6\n#define AVR32_USART_FRAME_MASK 0x00000040\n#define AVR32_USART_FRAME_OFFSET 6\n#define AVR32_USART_FRAME_SIZE 1\n#define AVR32_USART_FSDIS 6\n#define AVR32_USART_FSDIS_MASK 0x00000040\n#define AVR32_USART_FSDIS_OFFSET 6\n#define AVR32_USART_FSDIS_SIZE 1\n#define AVR32_USART_HARDWARE 0x00000002\n#define AVR32_USART_IDCHR 0\n#define AVR32_USART_IDCHR_MASK 0x000000ff\n#define AVR32_USART_IDCHR_OFFSET 0\n#define AVR32_USART_IDCHR_SIZE 8\n#define AVR32_USART_IDR 0x0000000c\n#define AVR32_USART_IDR_COMM_RX 31\n#define AVR32_USART_IDR_COMM_RX_MASK 0x80000000\n#define AVR32_USART_IDR_COMM_RX_OFFSET 31\n#define AVR32_USART_IDR_COMM_RX_SIZE 1\n#define AVR32_USART_IDR_COMM_TX 30\n#define AVR32_USART_IDR_COMM_TX_MASK 0x40000000\n#define AVR32_USART_IDR_COMM_TX_OFFSET 30\n#define AVR32_USART_IDR_COMM_TX_SIZE 1\n#define AVR32_USART_IDR_CTSIC 19\n#define AVR32_USART_IDR_CTSIC_MASK 0x00080000\n#define AVR32_USART_IDR_CTSIC_OFFSET 19\n#define AVR32_USART_IDR_CTSIC_SIZE 1\n#define AVR32_USART_IDR_DCDIC 18\n#define AVR32_USART_IDR_DCDIC_MASK 0x00040000\n#define AVR32_USART_IDR_DCDIC_OFFSET 18\n#define AVR32_USART_IDR_DCDIC_SIZE 1\n#define AVR32_USART_IDR_DSRIC 17\n#define AVR32_USART_IDR_DSRIC_MASK 0x00020000\n#define AVR32_USART_IDR_DSRIC_OFFSET 17\n#define AVR32_USART_IDR_DSRIC_SIZE 1\n#define AVR32_USART_IDR_ENDRX 3\n#define AVR32_USART_IDR_ENDRX_MASK 0x00000008\n#define AVR32_USART_IDR_ENDRX_OFFSET 3\n#define AVR32_USART_IDR_ENDRX_SIZE 1\n#define AVR32_USART_IDR_ENDTX 4\n#define AVR32_USART_IDR_ENDTX_MASK 0x00000010\n#define AVR32_USART_IDR_ENDTX_OFFSET 4\n#define AVR32_USART_IDR_ENDTX_SIZE 1\n#define AVR32_USART_IDR_FRAME 6\n#define AVR32_USART_IDR_FRAME_MASK 0x00000040\n#define AVR32_USART_IDR_FRAME_OFFSET 6\n#define AVR32_USART_IDR_FRAME_SIZE 1\n#define AVR32_USART_IDR_ITERATION 10\n#define AVR32_USART_IDR_ITERATION_MASK 0x00000400\n#define AVR32_USART_IDR_ITERATION_OFFSET 10\n#define AVR32_USART_IDR_ITERATION_SIZE 1\n#define AVR32_USART_IDR_LINBE 25\n#define AVR32_USART_IDR_LINBE_MASK 0x02000000\n#define AVR32_USART_IDR_LINBE_OFFSET 25\n#define AVR32_USART_IDR_LINBE_SIZE 1\n#define AVR32_USART_IDR_LINCE 28\n#define AVR32_USART_IDR_LINCE_MASK 0x10000000\n#define AVR32_USART_IDR_LINCE_OFFSET 28\n#define AVR32_USART_IDR_LINCE_SIZE 1\n#define AVR32_USART_IDR_LINIPE 27\n#define AVR32_USART_IDR_LINIPE_MASK 0x08000000\n#define AVR32_USART_IDR_LINIPE_OFFSET 27\n#define AVR32_USART_IDR_LINIPE_SIZE 1\n#define AVR32_USART_IDR_LINIR 14\n#define AVR32_USART_IDR_LINIR_MASK 0x00004000\n#define AVR32_USART_IDR_LINIR_OFFSET 14\n#define AVR32_USART_IDR_LINIR_SIZE 1\n#define AVR32_USART_IDR_LINISFE 26\n#define AVR32_USART_IDR_LINISFE_MASK 0x04000000\n#define AVR32_USART_IDR_LINISFE_OFFSET 26\n#define AVR32_USART_IDR_LINISFE_SIZE 1\n#define AVR32_USART_IDR_LINSNRE 29\n#define AVR32_USART_IDR_LINSNRE_MASK 0x20000000\n#define AVR32_USART_IDR_LINSNRE_OFFSET 29\n#define AVR32_USART_IDR_LINSNRE_SIZE 1\n#define AVR32_USART_IDR_LINTC 15\n#define AVR32_USART_IDR_LINTC_MASK 0x00008000\n#define AVR32_USART_IDR_LINTC_OFFSET 15\n#define AVR32_USART_IDR_LINTC_SIZE 1\n#define AVR32_USART_IDR_MANE 24\n#define AVR32_USART_IDR_MANE_MASK 0x01000000\n#define AVR32_USART_IDR_MANE_OFFSET 24\n#define AVR32_USART_IDR_MANE_SIZE 1\n#define AVR32_USART_IDR_NACK 13\n#define AVR32_USART_IDR_NACK_MASK 0x00002000\n#define AVR32_USART_IDR_NACK_OFFSET 13\n#define AVR32_USART_IDR_NACK_SIZE 1\n#define AVR32_USART_IDR_OVRE 5\n#define AVR32_USART_IDR_OVRE_MASK 0x00000020\n#define AVR32_USART_IDR_OVRE_OFFSET 5\n#define AVR32_USART_IDR_OVRE_SIZE 1\n#define AVR32_USART_IDR_PARE 7\n#define AVR32_USART_IDR_PARE_MASK 0x00000080\n#define AVR32_USART_IDR_PARE_OFFSET 7\n#define AVR32_USART_IDR_PARE_SIZE 1\n#define AVR32_USART_IDR_RIIC 16\n#define AVR32_USART_IDR_RIIC_MASK 0x00010000\n#define AVR32_USART_IDR_RIIC_OFFSET 16\n#define AVR32_USART_IDR_RIIC_SIZE 1\n#define AVR32_USART_IDR_RXBRK 2\n#define AVR32_USART_IDR_RXBRK_MASK 0x00000004\n#define AVR32_USART_IDR_RXBRK_OFFSET 2\n#define AVR32_USART_IDR_RXBRK_SIZE 1\n#define AVR32_USART_IDR_RXBUFF 12\n#define AVR32_USART_IDR_RXBUFF_MASK 0x00001000\n#define AVR32_USART_IDR_RXBUFF_OFFSET 12\n#define AVR32_USART_IDR_RXBUFF_SIZE 1\n#define AVR32_USART_IDR_RXRDY 0\n#define AVR32_USART_IDR_RXRDY_MASK 0x00000001\n#define AVR32_USART_IDR_RXRDY_OFFSET 0\n#define AVR32_USART_IDR_RXRDY_SIZE 1\n#define AVR32_USART_IDR_TIMEOUT 8\n#define AVR32_USART_IDR_TIMEOUT_MASK 0x00000100\n#define AVR32_USART_IDR_TIMEOUT_OFFSET 8\n#define AVR32_USART_IDR_TIMEOUT_SIZE 1\n#define AVR32_USART_IDR_TXBUFE 11\n#define AVR32_USART_IDR_TXBUFE_MASK 0x00000800\n#define AVR32_USART_IDR_TXBUFE_OFFSET 11\n#define AVR32_USART_IDR_TXBUFE_SIZE 1\n#define AVR32_USART_IDR_TXEMPTY 9\n#define AVR32_USART_IDR_TXEMPTY_MASK 0x00000200\n#define AVR32_USART_IDR_TXEMPTY_OFFSET 9\n#define AVR32_USART_IDR_TXEMPTY_SIZE 1\n#define AVR32_USART_IDR_TXRDY 1\n#define AVR32_USART_IDR_TXRDY_MASK 0x00000002\n#define AVR32_USART_IDR_TXRDY_OFFSET 1\n#define AVR32_USART_IDR_TXRDY_SIZE 1\n#define AVR32_USART_IER 0x00000008\n#define AVR32_USART_IER_COMM_RX 31\n#define AVR32_USART_IER_COMM_RX_MASK 0x80000000\n#define AVR32_USART_IER_COMM_RX_OFFSET 31\n#define AVR32_USART_IER_COMM_RX_SIZE 1\n#define AVR32_USART_IER_COMM_TX 30\n#define AVR32_USART_IER_COMM_TX_MASK 0x40000000\n#define AVR32_USART_IER_COMM_TX_OFFSET 30\n#define AVR32_USART_IER_COMM_TX_SIZE 1\n#define AVR32_USART_IER_CTSIC 19\n#define AVR32_USART_IER_CTSIC_MASK 0x00080000\n#define AVR32_USART_IER_CTSIC_OFFSET 19\n#define AVR32_USART_IER_CTSIC_SIZE 1\n#define AVR32_USART_IER_DCDIC 18\n#define AVR32_USART_IER_DCDIC_MASK 0x00040000\n#define AVR32_USART_IER_DCDIC_OFFSET 18\n#define AVR32_USART_IER_DCDIC_SIZE 1\n#define AVR32_USART_IER_DSRIC 17\n#define AVR32_USART_IER_DSRIC_MASK 0x00020000\n#define AVR32_USART_IER_DSRIC_OFFSET 17\n#define AVR32_USART_IER_DSRIC_SIZE 1\n#define AVR32_USART_IER_ENDRX 3\n#define AVR32_USART_IER_ENDRX_MASK 0x00000008\n#define AVR32_USART_IER_ENDRX_OFFSET 3\n#define AVR32_USART_IER_ENDRX_SIZE 1\n#define AVR32_USART_IER_ENDTX 4\n#define AVR32_USART_IER_ENDTX_MASK 0x00000010\n#define AVR32_USART_IER_ENDTX_OFFSET 4\n#define AVR32_USART_IER_ENDTX_SIZE 1\n#define AVR32_USART_IER_FRAME 6\n#define AVR32_USART_IER_FRAME_MASK 0x00000040\n#define AVR32_USART_IER_FRAME_OFFSET 6\n#define AVR32_USART_IER_FRAME_SIZE 1\n#define AVR32_USART_IER_ITERATION 10\n#define AVR32_USART_IER_ITERATION_MASK 0x00000400\n#define AVR32_USART_IER_ITERATION_OFFSET 10\n#define AVR32_USART_IER_ITERATION_SIZE 1\n#define AVR32_USART_IER_LINBE 25\n#define AVR32_USART_IER_LINBE_MASK 0x02000000\n#define AVR32_USART_IER_LINBE_OFFSET 25\n#define AVR32_USART_IER_LINBE_SIZE 1\n#define AVR32_USART_IER_LINCE 28\n#define AVR32_USART_IER_LINCE_MASK 0x10000000\n#define AVR32_USART_IER_LINCE_OFFSET 28\n#define AVR32_USART_IER_LINCE_SIZE 1\n#define AVR32_USART_IER_LINIPE 27\n#define AVR32_USART_IER_LINIPE_MASK 0x08000000\n#define AVR32_USART_IER_LINIPE_OFFSET 27\n#define AVR32_USART_IER_LINIPE_SIZE 1\n#define AVR32_USART_IER_LINIR 14\n#define AVR32_USART_IER_LINIR_MASK 0x00004000\n#define AVR32_USART_IER_LINIR_OFFSET 14\n#define AVR32_USART_IER_LINIR_SIZE 1\n#define AVR32_USART_IER_LINISFE 26\n#define AVR32_USART_IER_LINISFE_MASK 0x04000000\n#define AVR32_USART_IER_LINISFE_OFFSET 26\n#define AVR32_USART_IER_LINISFE_SIZE 1\n#define AVR32_USART_IER_LINSNRE 29\n#define AVR32_USART_IER_LINSNRE_MASK 0x20000000\n#define AVR32_USART_IER_LINSNRE_OFFSET 29\n#define AVR32_USART_IER_LINSNRE_SIZE 1\n#define AVR32_USART_IER_LINTC 15\n#define AVR32_USART_IER_LINTC_MASK 0x00008000\n#define AVR32_USART_IER_LINTC_OFFSET 15\n#define AVR32_USART_IER_LINTC_SIZE 1\n#define AVR32_USART_IER_MANE 24\n#define AVR32_USART_IER_MANE_MASK 0x01000000\n#define AVR32_USART_IER_MANE_OFFSET 24\n#define AVR32_USART_IER_MANE_SIZE 1\n#define AVR32_USART_IER_NACK 13\n#define AVR32_USART_IER_NACK_MASK 0x00002000\n#define AVR32_USART_IER_NACK_OFFSET 13\n#define AVR32_USART_IER_NACK_SIZE 1\n#define AVR32_USART_IER_OVRE 5\n#define AVR32_USART_IER_OVRE_MASK 0x00000020\n#define AVR32_USART_IER_OVRE_OFFSET 5\n#define AVR32_USART_IER_OVRE_SIZE 1\n#define AVR32_USART_IER_PARE 7\n#define AVR32_USART_IER_PARE_MASK 0x00000080\n#define AVR32_USART_IER_PARE_OFFSET 7\n#define AVR32_USART_IER_PARE_SIZE 1\n#define AVR32_USART_IER_RIIC 16\n#define AVR32_USART_IER_RIIC_MASK 0x00010000\n#define AVR32_USART_IER_RIIC_OFFSET 16\n#define AVR32_USART_IER_RIIC_SIZE 1\n#define AVR32_USART_IER_RXBRK 2\n#define AVR32_USART_IER_RXBRK_MASK 0x00000004\n#define AVR32_USART_IER_RXBRK_OFFSET 2\n#define AVR32_USART_IER_RXBRK_SIZE 1\n#define AVR32_USART_IER_RXBUFF 12\n#define AVR32_USART_IER_RXBUFF_MASK 0x00001000\n#define AVR32_USART_IER_RXBUFF_OFFSET 12\n#define AVR32_USART_IER_RXBUFF_SIZE 1\n#define AVR32_USART_IER_RXRDY 0\n#define AVR32_USART_IER_RXRDY_MASK 0x00000001\n#define AVR32_USART_IER_RXRDY_OFFSET 0\n#define AVR32_USART_IER_RXRDY_SIZE 1\n#define AVR32_USART_IER_TIMEOUT 8\n#define AVR32_USART_IER_TIMEOUT_MASK 0x00000100\n#define AVR32_USART_IER_TIMEOUT_OFFSET 8\n#define AVR32_USART_IER_TIMEOUT_SIZE 1\n#define AVR32_USART_IER_TXBUFE 11\n#define AVR32_USART_IER_TXBUFE_MASK 0x00000800\n#define AVR32_USART_IER_TXBUFE_OFFSET 11\n#define AVR32_USART_IER_TXBUFE_SIZE 1\n#define AVR32_USART_IER_TXEMPTY 9\n#define AVR32_USART_IER_TXEMPTY_MASK 0x00000200\n#define AVR32_USART_IER_TXEMPTY_OFFSET 9\n#define AVR32_USART_IER_TXEMPTY_SIZE 1\n#define AVR32_USART_IER_TXRDY 1\n#define AVR32_USART_IER_TXRDY_MASK 0x00000002\n#define AVR32_USART_IER_TXRDY_OFFSET 1\n#define AVR32_USART_IER_TXRDY_SIZE 1\n#define AVR32_USART_IFR 0x0000004c\n#define AVR32_USART_IFR_IRDA_FILTER 0\n#define AVR32_USART_IFR_IRDA_FILTER_MASK 0x000000ff\n#define AVR32_USART_IFR_IRDA_FILTER_OFFSET 0\n#define AVR32_USART_IFR_IRDA_FILTER_SIZE 8\n#define AVR32_USART_IGNORE 0x00000002\n#define AVR32_USART_IMR 0x00000010\n#define AVR32_USART_IMR_COMM_RX 31\n#define AVR32_USART_IMR_COMM_RX_MASK 0x80000000\n#define AVR32_USART_IMR_COMM_RX_OFFSET 31\n#define AVR32_USART_IMR_COMM_RX_SIZE 1\n#define AVR32_USART_IMR_COMM_TX 30\n#define AVR32_USART_IMR_COMM_TX_MASK 0x40000000\n#define AVR32_USART_IMR_COMM_TX_OFFSET 30\n#define AVR32_USART_IMR_COMM_TX_SIZE 1\n#define AVR32_USART_IMR_CTSIC 19\n#define AVR32_USART_IMR_CTSIC_MASK 0x00080000\n#define AVR32_USART_IMR_CTSIC_OFFSET 19\n#define AVR32_USART_IMR_CTSIC_SIZE 1\n#define AVR32_USART_IMR_DCDIC 18\n#define AVR32_USART_IMR_DCDIC_MASK 0x00040000\n#define AVR32_USART_IMR_DCDIC_OFFSET 18\n#define AVR32_USART_IMR_DCDIC_SIZE 1\n#define AVR32_USART_IMR_DSRIC 17\n#define AVR32_USART_IMR_DSRIC_MASK 0x00020000\n#define AVR32_USART_IMR_DSRIC_OFFSET 17\n#define AVR32_USART_IMR_DSRIC_SIZE 1\n#define AVR32_USART_IMR_ENDRX 3\n#define AVR32_USART_IMR_ENDRX_MASK 0x00000008\n#define AVR32_USART_IMR_ENDRX_OFFSET 3\n#define AVR32_USART_IMR_ENDRX_SIZE 1\n#define AVR32_USART_IMR_ENDTX 4\n#define AVR32_USART_IMR_ENDTX_MASK 0x00000010\n#define AVR32_USART_IMR_ENDTX_OFFSET 4\n#define AVR32_USART_IMR_ENDTX_SIZE 1\n#define AVR32_USART_IMR_FRAME 6\n#define AVR32_USART_IMR_FRAME_MASK 0x00000040\n#define AVR32_USART_IMR_FRAME_OFFSET 6\n#define AVR32_USART_IMR_FRAME_SIZE 1\n#define AVR32_USART_IMR_ITERATION 10\n#define AVR32_USART_IMR_ITERATION_MASK 0x00000400\n#define AVR32_USART_IMR_ITERATION_OFFSET 10\n#define AVR32_USART_IMR_ITERATION_SIZE 1\n#define AVR32_USART_IMR_LINBE 25\n#define AVR32_USART_IMR_LINBE_MASK 0x02000000\n#define AVR32_USART_IMR_LINBE_OFFSET 25\n#define AVR32_USART_IMR_LINBE_SIZE 1\n#define AVR32_USART_IMR_LINCE 28\n#define AVR32_USART_IMR_LINCE_MASK 0x10000000\n#define AVR32_USART_IMR_LINCE_OFFSET 28\n#define AVR32_USART_IMR_LINCE_SIZE 1\n#define AVR32_USART_IMR_LINIPE 27\n#define AVR32_USART_IMR_LINIPE_MASK 0x08000000\n#define AVR32_USART_IMR_LINIPE_OFFSET 27\n#define AVR32_USART_IMR_LINIPE_SIZE 1\n#define AVR32_USART_IMR_LINIR 14\n#define AVR32_USART_IMR_LINIR_MASK 0x00004000\n#define AVR32_USART_IMR_LINIR_OFFSET 14\n#define AVR32_USART_IMR_LINIR_SIZE 1\n#define AVR32_USART_IMR_LINISFE 26\n#define AVR32_USART_IMR_LINISFE_MASK 0x04000000\n#define AVR32_USART_IMR_LINISFE_OFFSET 26\n#define AVR32_USART_IMR_LINISFE_SIZE 1\n#define AVR32_USART_IMR_LINSNRE 29\n#define AVR32_USART_IMR_LINSNRE_MASK 0x20000000\n#define AVR32_USART_IMR_LINSNRE_OFFSET 29\n#define AVR32_USART_IMR_LINSNRE_SIZE 1\n#define AVR32_USART_IMR_LINTC 15\n#define AVR32_USART_IMR_LINTC_MASK 0x00008000\n#define AVR32_USART_IMR_LINTC_OFFSET 15\n#define AVR32_USART_IMR_LINTC_SIZE 1\n#define AVR32_USART_IMR_MANE 24\n#define AVR32_USART_IMR_MANE_MASK 0x01000000\n#define AVR32_USART_IMR_MANE_OFFSET 24\n#define AVR32_USART_IMR_MANE_SIZE 1\n#define AVR32_USART_IMR_NACK 13\n#define AVR32_USART_IMR_NACK_MASK 0x00002000\n#define AVR32_USART_IMR_NACK_OFFSET 13\n#define AVR32_USART_IMR_NACK_SIZE 1\n#define AVR32_USART_IMR_OVRE 5\n#define AVR32_USART_IMR_OVRE_MASK 0x00000020\n#define AVR32_USART_IMR_OVRE_OFFSET 5\n#define AVR32_USART_IMR_OVRE_SIZE 1\n#define AVR32_USART_IMR_PARE 7\n#define AVR32_USART_IMR_PARE_MASK 0x00000080\n#define AVR32_USART_IMR_PARE_OFFSET 7\n#define AVR32_USART_IMR_PARE_SIZE 1\n#define AVR32_USART_IMR_RIIC 16\n#define AVR32_USART_IMR_RIIC_MASK 0x00010000\n#define AVR32_USART_IMR_RIIC_OFFSET 16\n#define AVR32_USART_IMR_RIIC_SIZE 1\n#define AVR32_USART_IMR_RXBRK 2\n#define AVR32_USART_IMR_RXBRK_MASK 0x00000004\n#define AVR32_USART_IMR_RXBRK_OFFSET 2\n#define AVR32_USART_IMR_RXBRK_SIZE 1\n#define AVR32_USART_IMR_RXBUFF 12\n#define AVR32_USART_IMR_RXBUFF_MASK 0x00001000\n#define AVR32_USART_IMR_RXBUFF_OFFSET 12\n#define AVR32_USART_IMR_RXBUFF_SIZE 1\n#define AVR32_USART_IMR_RXRDY 0\n#define AVR32_USART_IMR_RXRDY_MASK 0x00000001\n#define AVR32_USART_IMR_RXRDY_OFFSET 0\n#define AVR32_USART_IMR_RXRDY_SIZE 1\n#define AVR32_USART_IMR_TIMEOUT 8\n#define AVR32_USART_IMR_TIMEOUT_MASK 0x00000100\n#define AVR32_USART_IMR_TIMEOUT_OFFSET 8\n#define AVR32_USART_IMR_TIMEOUT_SIZE 1\n#define AVR32_USART_IMR_TXBUFE 11\n#define AVR32_USART_IMR_TXBUFE_MASK 0x00000800\n#define AVR32_USART_IMR_TXBUFE_OFFSET 11\n#define AVR32_USART_IMR_TXBUFE_SIZE 1\n#define AVR32_USART_IMR_TXEMPTY 9\n#define AVR32_USART_IMR_TXEMPTY_MASK 0x00000200\n#define AVR32_USART_IMR_TXEMPTY_OFFSET 9\n#define AVR32_USART_IMR_TXEMPTY_SIZE 1\n#define AVR32_USART_IMR_TXRDY 1\n#define AVR32_USART_IMR_TXRDY_MASK 0x00000002\n#define AVR32_USART_IMR_TXRDY_OFFSET 1\n#define AVR32_USART_IMR_TXRDY_SIZE 1\n#define AVR32_USART_INACK 20\n#define AVR32_USART_INACK_MASK 0x00100000\n#define AVR32_USART_INACK_OFFSET 20\n#define AVR32_USART_INACK_SIZE 1\n#define AVR32_USART_IRDA 0x00000008\n#define AVR32_USART_IRDA_FILTER 0\n#define AVR32_USART_IRDA_FILTER_MASK 0x000000ff\n#define AVR32_USART_IRDA_FILTER_OFFSET 0\n#define AVR32_USART_IRDA_FILTER_SIZE 8\n#define AVR32_USART_ISO7816_T0 0x00000004\n#define AVR32_USART_ISO7816_T1 0x00000006\n#define AVR32_USART_ITERATION 10\n#define AVR32_USART_ITERATION_MASK 0x00000400\n#define AVR32_USART_ITERATION_OFFSET 10\n#define AVR32_USART_ITERATION_SIZE 1\n#define AVR32_USART_LINABT 20\n#define AVR32_USART_LINABT_MASK 0x00100000\n#define AVR32_USART_LINABT_OFFSET 20\n#define AVR32_USART_LINABT_SIZE 1\n#define AVR32_USART_LINBE 25\n#define AVR32_USART_LINBE_MASK 0x02000000\n#define AVR32_USART_LINBE_OFFSET 25\n#define AVR32_USART_LINBE_SIZE 1\n#define AVR32_USART_LINCE 28\n#define AVR32_USART_LINCE_MASK 0x10000000\n#define AVR32_USART_LINCE_OFFSET 28\n#define AVR32_USART_LINCE_SIZE 1\n#define AVR32_USART_LINIPE 27\n#define AVR32_USART_LINIPE_MASK 0x08000000\n#define AVR32_USART_LINIPE_OFFSET 27\n#define AVR32_USART_LINIPE_SIZE 1\n#define AVR32_USART_LINIR 0x00000058\n#define AVR32_USART_LINIR_IDCHR 0\n#define AVR32_USART_LINIR_IDCHR_MASK 0x000000ff\n#define AVR32_USART_LINIR_IDCHR_OFFSET 0\n#define AVR32_USART_LINIR_IDCHR_SIZE 8\n#define AVR32_USART_LINIR_MASK 0x00004000\n#define AVR32_USART_LINIR_OFFSET 14\n#define AVR32_USART_LINIR_SIZE 1\n#define AVR32_USART_LINISFE 26\n#define AVR32_USART_LINISFE_MASK 0x04000000\n#define AVR32_USART_LINISFE_OFFSET 26\n#define AVR32_USART_LINISFE_SIZE 1\n#define AVR32_USART_LINMR 0x00000054\n#define AVR32_USART_LINMR_CHKDIS 3\n#define AVR32_USART_LINMR_CHKDIS_MASK 0x00000008\n#define AVR32_USART_LINMR_CHKDIS_OFFSET 3\n#define AVR32_USART_LINMR_CHKDIS_SIZE 1\n#define AVR32_USART_LINMR_CHKTYP 4\n#define AVR32_USART_LINMR_CHKTYP_MASK 0x00000010\n#define AVR32_USART_LINMR_CHKTYP_OFFSET 4\n#define AVR32_USART_LINMR_CHKTYP_SIZE 1\n#define AVR32_USART_LINMR_DLC 8\n#define AVR32_USART_LINMR_DLC_MASK 0x0000ff00\n#define AVR32_USART_LINMR_DLC_OFFSET 8\n#define AVR32_USART_LINMR_DLC_SIZE 8\n#define AVR32_USART_LINMR_DLM 5\n#define AVR32_USART_LINMR_DLM_MASK 0x00000020\n#define AVR32_USART_LINMR_DLM_OFFSET 5\n#define AVR32_USART_LINMR_DLM_SIZE 1\n#define AVR32_USART_LINMR_FSDIS 6\n#define AVR32_USART_LINMR_FSDIS_MASK 0x00000040\n#define AVR32_USART_LINMR_FSDIS_OFFSET 6\n#define AVR32_USART_LINMR_FSDIS_SIZE 1\n#define AVR32_USART_LINMR_NACT 0\n#define AVR32_USART_LINMR_NACT_IGNORE 0x00000002\n#define AVR32_USART_LINMR_NACT_MASK 0x00000003\n#define AVR32_USART_LINMR_NACT_OFFSET 0\n#define AVR32_USART_LINMR_NACT_PUBLISH 0x00000000\n#define AVR32_USART_LINMR_NACT_SIZE 2\n#define AVR32_USART_LINMR_NACT_SUBSCRIBE 0x00000001\n#define AVR32_USART_LINMR_PARDIS 2\n#define AVR32_USART_LINMR_PARDIS_MASK 0x00000004\n#define AVR32_USART_LINMR_PARDIS_OFFSET 2\n#define AVR32_USART_LINMR_PARDIS_SIZE 1\n#define AVR32_USART_LINMR_PDCM 16\n#define AVR32_USART_LINMR_PDCM_MASK 0x00010000\n#define AVR32_USART_LINMR_PDCM_OFFSET 16\n#define AVR32_USART_LINMR_PDCM_SIZE 1\n#define AVR32_USART_LINMR_WKUPTYP 7\n#define AVR32_USART_LINMR_WKUPTYP_MASK 0x00000080\n#define AVR32_USART_LINMR_WKUPTYP_OFFSET 7\n#define AVR32_USART_LINMR_WKUPTYP_SIZE 1\n#define AVR32_USART_LINSNRE 29\n#define AVR32_USART_LINSNRE_MASK 0x20000000\n#define AVR32_USART_LINSNRE_OFFSET 29\n#define AVR32_USART_LINSNRE_SIZE 1\n#define AVR32_USART_LINTC 15\n#define AVR32_USART_LINTC_MASK 0x00008000\n#define AVR32_USART_LINTC_OFFSET 15\n#define AVR32_USART_LINTC_SIZE 1\n#define AVR32_USART_LINWKUP 21\n#define AVR32_USART_LINWKUP_MASK 0x00200000\n#define AVR32_USART_LINWKUP_OFFSET 21\n#define AVR32_USART_LINWKUP_SIZE 1\n#define AVR32_USART_LIN_MASTER 0x0000000a\n#define AVR32_USART_LIN_SLAVE 0x0000000b\n#define AVR32_USART_LOCAL_LOOP 0x00000002\n#define AVR32_USART_LSBF 0x00000000\n#define AVR32_USART_MAN 0x00000050\n#define AVR32_USART_MANE 24\n#define AVR32_USART_MANERR 24\n#define AVR32_USART_MANERR_MASK 0x01000000\n#define AVR32_USART_MANERR_OFFSET 24\n#define AVR32_USART_MANERR_SIZE 1\n#define AVR32_USART_MANE_MASK 0x01000000\n#define AVR32_USART_MANE_OFFSET 24\n#define AVR32_USART_MANE_SIZE 1\n#define AVR32_USART_MAN_DRIFT 30\n#define AVR32_USART_MAN_DRIFT_MASK 0x40000000\n#define AVR32_USART_MAN_DRIFT_OFFSET 30\n#define AVR32_USART_MAN_DRIFT_SIZE 1\n#define AVR32_USART_MAN_MASK 0x20000000\n#define AVR32_USART_MAN_OFFSET 29\n#define AVR32_USART_MAN_RX_MPOL 28\n#define AVR32_USART_MAN_RX_MPOL_MASK 0x10000000\n#define AVR32_USART_MAN_RX_MPOL_OFFSET 28\n#define AVR32_USART_MAN_RX_MPOL_SIZE 1\n#define AVR32_USART_MAN_RX_PL 16\n#define AVR32_USART_MAN_RX_PL_MASK 0x000f0000\n#define AVR32_USART_MAN_RX_PL_OFFSET 16\n#define AVR32_USART_MAN_RX_PL_SIZE 4\n#define AVR32_USART_MAN_RX_PP 24\n#define AVR32_USART_MAN_RX_PP_MASK 0x03000000\n#define AVR32_USART_MAN_RX_PP_OFFSET 24\n#define AVR32_USART_MAN_RX_PP_SIZE 2\n#define AVR32_USART_MAN_SIZE 1\n#define AVR32_USART_MAN_TX_MPOL 12\n#define AVR32_USART_MAN_TX_MPOL_MASK 0x00001000\n#define AVR32_USART_MAN_TX_MPOL_OFFSET 12\n#define AVR32_USART_MAN_TX_MPOL_SIZE 1\n#define AVR32_USART_MAN_TX_PL 0\n#define AVR32_USART_MAN_TX_PL_MASK 0x0000000f\n#define AVR32_USART_MAN_TX_PL_OFFSET 0\n#define AVR32_USART_MAN_TX_PL_SIZE 4\n#define AVR32_USART_MAN_TX_PP 8\n#define AVR32_USART_MAN_TX_PP_MASK 0x00000300\n#define AVR32_USART_MAN_TX_PP_OFFSET 8\n#define AVR32_USART_MAN_TX_PP_SIZE 2\n#define AVR32_USART_MARK 0x00000003\n#define AVR32_USART_MAX_ITERATION 24\n#define AVR32_USART_MAX_ITERATION_MASK 0x07000000\n#define AVR32_USART_MAX_ITERATION_OFFSET 24\n#define AVR32_USART_MAX_ITERATION_SIZE 3\n#define AVR32_USART_MCK 0x00000000\n#define AVR32_USART_MCK_DIV 0x00000001\n#define AVR32_USART_MODE 0\n#define AVR32_USART_MODE9 17\n#define AVR32_USART_MODE9_MASK 0x00020000\n#define AVR32_USART_MODE9_OFFSET 17\n#define AVR32_USART_MODE9_SIZE 1\n#define AVR32_USART_MODEM 0x00000003\n#define AVR32_USART_MODE_HARDWARE 0x00000002\n#define AVR32_USART_MODE_IRDA 0x00000008\n#define AVR32_USART_MODE_ISO7816_T0 0x00000004\n#define AVR32_USART_MODE_ISO7816_T1 0x00000006\n#define AVR32_USART_MODE_LIN_MASTER 0x0000000a\n#define AVR32_USART_MODE_LIN_SLAVE 0x0000000b\n#define AVR32_USART_MODE_MASK 0x0000000f\n#define AVR32_USART_MODE_MODEM 0x00000003\n#define AVR32_USART_MODE_NORMAL 0x00000000\n#define AVR32_USART_MODE_OFFSET 0\n#define AVR32_USART_MODE_RS485 0x00000001\n#define AVR32_USART_MODE_SIZE 4\n#define AVR32_USART_MODE_SPI_MASTER 0x0000000e\n#define AVR32_USART_MODE_SPI_SLAVE 0x0000000f\n#define AVR32_USART_MODSYNC 30\n#define AVR32_USART_MODSYNC_MASK 0x40000000\n#define AVR32_USART_MODSYNC_OFFSET 30\n#define AVR32_USART_MODSYNC_SIZE 1\n#define AVR32_USART_MR 0x00000004\n#define AVR32_USART_MR_CHMODE 14\n#define AVR32_USART_MR_CHMODE_ECHO 0x00000001\n#define AVR32_USART_MR_CHMODE_LOCAL_LOOP 0x00000002\n#define AVR32_USART_MR_CHMODE_MASK 0x0000c000\n#define AVR32_USART_MR_CHMODE_NORMAL 0x00000000\n#define AVR32_USART_MR_CHMODE_OFFSET 14\n#define AVR32_USART_MR_CHMODE_REMOTE_LOOP 0x00000003\n#define AVR32_USART_MR_CHMODE_SIZE 2\n#define AVR32_USART_MR_CHRL 6\n#define AVR32_USART_MR_CHRL_5 0x00000000\n#define AVR32_USART_MR_CHRL_6 0x00000001\n#define AVR32_USART_MR_CHRL_7 0x00000002\n#define AVR32_USART_MR_CHRL_8 0x00000003\n#define AVR32_USART_MR_CHRL_MASK 0x000000c0\n#define AVR32_USART_MR_CHRL_OFFSET 6\n#define AVR32_USART_MR_CHRL_SIZE 2\n#define AVR32_USART_MR_CLKO 18\n#define AVR32_USART_MR_CLKO_MASK 0x00040000\n#define AVR32_USART_MR_CLKO_OFFSET 18\n#define AVR32_USART_MR_CLKO_SIZE 1\n#define AVR32_USART_MR_DSNACK 21\n#define AVR32_USART_MR_DSNACK_MASK 0x00200000\n#define AVR32_USART_MR_DSNACK_OFFSET 21\n#define AVR32_USART_MR_DSNACK_SIZE 1\n#define AVR32_USART_MR_FILTER 28\n#define AVR32_USART_MR_FILTER_MASK 0x10000000\n#define AVR32_USART_MR_FILTER_OFFSET 28\n#define AVR32_USART_MR_FILTER_SIZE 1\n#define AVR32_USART_MR_INACK 20\n#define AVR32_USART_MR_INACK_MASK 0x00100000\n#define AVR32_USART_MR_INACK_OFFSET 20\n#define AVR32_USART_MR_INACK_SIZE 1\n#define AVR32_USART_MR_MAN 29\n#define AVR32_USART_MR_MAN_MASK 0x20000000\n#define AVR32_USART_MR_MAN_OFFSET 29\n#define AVR32_USART_MR_MAN_SIZE 1\n#define AVR32_USART_MR_MAX_ITERATION 24\n#define AVR32_USART_MR_MAX_ITERATION_MASK 0x07000000\n#define AVR32_USART_MR_MAX_ITERATION_OFFSET 24\n#define AVR32_USART_MR_MAX_ITERATION_SIZE 3\n#define AVR32_USART_MR_MODE 0\n#define AVR32_USART_MR_MODE9 17\n#define AVR32_USART_MR_MODE9_MASK 0x00020000\n#define AVR32_USART_MR_MODE9_OFFSET 17\n#define AVR32_USART_MR_MODE9_SIZE 1\n#define AVR32_USART_MR_MODE_HARDWARE 0x00000002\n#define AVR32_USART_MR_MODE_IRDA 0x00000008\n#define AVR32_USART_MR_MODE_ISO7816_T0 0x00000004\n#define AVR32_USART_MR_MODE_ISO7816_T1 0x00000006\n#define AVR32_USART_MR_MODE_LIN_MASTER 0x0000000a\n#define AVR32_USART_MR_MODE_LIN_SLAVE 0x0000000b\n#define AVR32_USART_MR_MODE_MASK 0x0000000f\n#define AVR32_USART_MR_MODE_MODEM 0x00000003\n#define AVR32_USART_MR_MODE_NORMAL 0x00000000\n#define AVR32_USART_MR_MODE_OFFSET 0\n#define AVR32_USART_MR_MODE_RS485 0x00000001\n#define AVR32_USART_MR_MODE_SIZE 4\n#define AVR32_USART_MR_MODE_SPI_MASTER 0x0000000e\n#define AVR32_USART_MR_MODE_SPI_SLAVE 0x0000000f\n#define AVR32_USART_MR_MODSYNC 30\n#define AVR32_USART_MR_MODSYNC_MASK 0x40000000\n#define AVR32_USART_MR_MODSYNC_OFFSET 30\n#define AVR32_USART_MR_MODSYNC_SIZE 1\n#define AVR32_USART_MR_MSBF 16\n#define AVR32_USART_MR_MSBF_LSBF 0x00000000\n#define AVR32_USART_MR_MSBF_MASK 0x00010000\n#define AVR32_USART_MR_MSBF_MSBF 0x00000001\n#define AVR32_USART_MR_MSBF_OFFSET 16\n#define AVR32_USART_MR_MSBF_SIZE 1\n#define AVR32_USART_MR_NBSTOP 12\n#define AVR32_USART_MR_NBSTOP_1 0x00000000\n#define AVR32_USART_MR_NBSTOP_1_5 0x00000001\n#define AVR32_USART_MR_NBSTOP_2 0x00000002\n#define AVR32_USART_MR_NBSTOP_MASK 0x00003000\n#define AVR32_USART_MR_NBSTOP_OFFSET 12\n#define AVR32_USART_MR_NBSTOP_SIZE 2\n#define AVR32_USART_MR_ONEBIT 31\n#define AVR32_USART_MR_ONEBIT_MASK 0x80000000\n#define AVR32_USART_MR_ONEBIT_OFFSET 31\n#define AVR32_USART_MR_ONEBIT_SIZE 1\n#define AVR32_USART_MR_OVER 19\n#define AVR32_USART_MR_OVER_MASK 0x00080000\n#define AVR32_USART_MR_OVER_OFFSET 19\n#define AVR32_USART_MR_OVER_SIZE 1\n#define AVR32_USART_MR_OVER_X16 0x00000000\n#define AVR32_USART_MR_OVER_X8 0x00000001\n#define AVR32_USART_MR_PAR 9\n#define AVR32_USART_MR_PAR_EVEN 0x00000000\n#define AVR32_USART_MR_PAR_MARK 0x00000003\n#define AVR32_USART_MR_PAR_MASK 0x00000e00\n#define AVR32_USART_MR_PAR_MULTI 0x00000006\n#define AVR32_USART_MR_PAR_NONE 0x00000004\n#define AVR32_USART_MR_PAR_ODD 0x00000001\n#define AVR32_USART_MR_PAR_OFFSET 9\n#define AVR32_USART_MR_PAR_SIZE 3\n#define AVR32_USART_MR_PAR_SPACE 0x00000002\n#define AVR32_USART_MR_SYNC 8\n#define AVR32_USART_MR_SYNC_MASK 0x00000100\n#define AVR32_USART_MR_SYNC_OFFSET 8\n#define AVR32_USART_MR_SYNC_SIZE 1\n#define AVR32_USART_MR_USCLKS 4\n#define AVR32_USART_MR_USCLKS_MASK 0x00000030\n#define AVR32_USART_MR_USCLKS_MCK 0x00000000\n#define AVR32_USART_MR_USCLKS_MCK_DIV 0x00000001\n#define AVR32_USART_MR_USCLKS_OFFSET 4\n#define AVR32_USART_MR_USCLKS_SCK 0x00000003\n#define AVR32_USART_MR_USCLKS_SIZE 2\n#define AVR32_USART_MR_VAR_SYNC 22\n#define AVR32_USART_MR_VAR_SYNC_MASK 0x00400000\n#define AVR32_USART_MR_VAR_SYNC_OFFSET 22\n#define AVR32_USART_MR_VAR_SYNC_SIZE 1\n#define AVR32_USART_MSBF_LSBF 0x00000000\n#define AVR32_USART_MSBF_MASK 0x00010000\n#define AVR32_USART_MSBF_MSBF 0x00000001\n#define AVR32_USART_MSBF_OFFSET 16\n#define AVR32_USART_MSBF_SIZE 1\n#define AVR32_USART_MULTI 0x00000006\n#define AVR32_USART_NACK 13\n#define AVR32_USART_NACK_MASK 0x00002000\n#define AVR32_USART_NACK_OFFSET 13\n#define AVR32_USART_NACK_SIZE 1\n#define AVR32_USART_NACT 0\n#define AVR32_USART_NACT_IGNORE 0x00000002\n#define AVR32_USART_NACT_MASK 0x00000003\n#define AVR32_USART_NACT_OFFSET 0\n#define AVR32_USART_NACT_PUBLISH 0x00000000\n#define AVR32_USART_NACT_SIZE 2\n#define AVR32_USART_NACT_SUBSCRIBE 0x00000001\n#define AVR32_USART_NBSTOP 12\n#define AVR32_USART_NBSTOP_1 0x00000000\n#define AVR32_USART_NBSTOP_1_5 0x00000001\n#define AVR32_USART_NBSTOP_2 0x00000002\n#define AVR32_USART_NBSTOP_MASK 0x00003000\n#define AVR32_USART_NBSTOP_OFFSET 12\n#define AVR32_USART_NBSTOP_SIZE 2\n#define AVR32_USART_NB_ERRORS 0\n#define AVR32_USART_NB_ERRORS_MASK 0x000000ff\n#define AVR32_USART_NB_ERRORS_OFFSET 0\n#define AVR32_USART_NB_ERRORS_SIZE 8\n#define AVR32_USART_NER 0x00000044\n#define AVR32_USART_NER_NB_ERRORS 0\n#define AVR32_USART_NER_NB_ERRORS_MASK 0x000000ff\n#define AVR32_USART_NER_NB_ERRORS_OFFSET 0\n#define AVR32_USART_NER_NB_ERRORS_SIZE 8\n#define AVR32_USART_NONE 0x00000004\n#define AVR32_USART_NORMAL 0x00000000\n#define AVR32_USART_ODD 0x00000001\n#define AVR32_USART_ONEBIT 31\n#define AVR32_USART_ONEBIT_MASK 0x80000000\n#define AVR32_USART_ONEBIT_OFFSET 31\n#define AVR32_USART_ONEBIT_SIZE 1\n#define AVR32_USART_OVER 19\n#define AVR32_USART_OVER_MASK 0x00080000\n#define AVR32_USART_OVER_OFFSET 19\n#define AVR32_USART_OVER_SIZE 1\n#define AVR32_USART_OVER_X16 0x00000000\n#define AVR32_USART_OVER_X8 0x00000001\n#define AVR32_USART_OVRE 5\n#define AVR32_USART_OVRE_MASK 0x00000020\n#define AVR32_USART_OVRE_OFFSET 5\n#define AVR32_USART_OVRE_SIZE 1\n#define AVR32_USART_PAR 9\n#define AVR32_USART_PARDIS 2\n#define AVR32_USART_PARDIS_MASK 0x00000004\n#define AVR32_USART_PARDIS_OFFSET 2\n#define AVR32_USART_PARDIS_SIZE 1\n#define AVR32_USART_PARE 7\n#define AVR32_USART_PARE_MASK 0x00000080\n#define AVR32_USART_PARE_OFFSET 7\n#define AVR32_USART_PARE_SIZE 1\n#define AVR32_USART_PAR_EVEN 0x00000000\n#define AVR32_USART_PAR_MARK 0x00000003\n#define AVR32_USART_PAR_MASK 0x00000e00\n#define AVR32_USART_PAR_MULTI 0x00000006\n#define AVR32_USART_PAR_NONE 0x00000004\n#define AVR32_USART_PAR_ODD 0x00000001\n#define AVR32_USART_PAR_OFFSET 9\n#define AVR32_USART_PAR_SIZE 3\n#define AVR32_USART_PAR_SPACE 0x00000002\n#define AVR32_USART_PDCM 16\n#define AVR32_USART_PDCM_MASK 0x00010000\n#define AVR32_USART_PDCM_OFFSET 16\n#define AVR32_USART_PDCM_SIZE 1\n#define AVR32_USART_PUBLISH 0x00000000\n#define AVR32_USART_REMOTE_LOOP 0x00000003\n#define AVR32_USART_RETTO 15\n#define AVR32_USART_RETTO_MASK 0x00008000\n#define AVR32_USART_RETTO_OFFSET 15\n#define AVR32_USART_RETTO_SIZE 1\n#define AVR32_USART_RHR 0x00000018\n#define AVR32_USART_RHR_RXCHR 0\n#define AVR32_USART_RHR_RXCHR_MASK 0x000001ff\n#define AVR32_USART_RHR_RXCHR_OFFSET 0\n#define AVR32_USART_RHR_RXCHR_SIZE 9\n#define AVR32_USART_RHR_RXSYNH 15\n#define AVR32_USART_RHR_RXSYNH_MASK 0x00008000\n#define AVR32_USART_RHR_RXSYNH_OFFSET 15\n#define AVR32_USART_RHR_RXSYNH_SIZE 1\n#define AVR32_USART_RI 20\n#define AVR32_USART_RIIC 16\n#define AVR32_USART_RIIC_MASK 0x00010000\n#define AVR32_USART_RIIC_OFFSET 16\n#define AVR32_USART_RIIC_SIZE 1\n#define AVR32_USART_RI_MASK 0x00100000\n#define AVR32_USART_RI_OFFSET 20\n#define AVR32_USART_RI_SIZE 1\n#define AVR32_USART_RS485 0x00000001\n#define AVR32_USART_RSTIT 13\n#define AVR32_USART_RSTIT_MASK 0x00002000\n#define AVR32_USART_RSTIT_OFFSET 13\n#define AVR32_USART_RSTIT_SIZE 1\n#define AVR32_USART_RSTNACK 14\n#define AVR32_USART_RSTNACK_MASK 0x00004000\n#define AVR32_USART_RSTNACK_OFFSET 14\n#define AVR32_USART_RSTNACK_SIZE 1\n#define AVR32_USART_RSTRX 2\n#define AVR32_USART_RSTRX_MASK 0x00000004\n#define AVR32_USART_RSTRX_OFFSET 2\n#define AVR32_USART_RSTRX_SIZE 1\n#define AVR32_USART_RSTSTA 8\n#define AVR32_USART_RSTSTA_MASK 0x00000100\n#define AVR32_USART_RSTSTA_OFFSET 8\n#define AVR32_USART_RSTSTA_SIZE 1\n#define AVR32_USART_RSTTX 3\n#define AVR32_USART_RSTTX_MASK 0x00000008\n#define AVR32_USART_RSTTX_OFFSET 3\n#define AVR32_USART_RSTTX_SIZE 1\n#define AVR32_USART_RTOR 0x00000024\n#define AVR32_USART_RTOR_TO 0\n#define AVR32_USART_RTOR_TO_DISABLE 0x00000000\n#define AVR32_USART_RTOR_TO_MASK 0x0000ffff\n#define AVR32_USART_RTOR_TO_OFFSET 0\n#define AVR32_USART_RTOR_TO_SIZE 16\n#define AVR32_USART_RTSDIS 19\n#define AVR32_USART_RTSDIS_MASK 0x00080000\n#define AVR32_USART_RTSDIS_OFFSET 19\n#define AVR32_USART_RTSDIS_SIZE 1\n#define AVR32_USART_RTSEN 18\n#define AVR32_USART_RTSEN_MASK 0x00040000\n#define AVR32_USART_RTSEN_OFFSET 18\n#define AVR32_USART_RTSEN_SIZE 1\n#define AVR32_USART_RXBRK 2\n#define AVR32_USART_RXBRK_MASK 0x00000004\n#define AVR32_USART_RXBRK_OFFSET 2\n#define AVR32_USART_RXBRK_SIZE 1\n#define AVR32_USART_RXBUFF 12\n#define AVR32_USART_RXBUFF_MASK 0x00001000\n#define AVR32_USART_RXBUFF_OFFSET 12\n#define AVR32_USART_RXBUFF_SIZE 1\n#define AVR32_USART_RXCHR 0\n#define AVR32_USART_RXCHR_MASK 0x000001ff\n#define AVR32_USART_RXCHR_OFFSET 0\n#define AVR32_USART_RXCHR_SIZE 9\n#define AVR32_USART_RXDIS 5\n#define AVR32_USART_RXDIS_MASK 0x00000020\n#define AVR32_USART_RXDIS_OFFSET 5\n#define AVR32_USART_RXDIS_SIZE 1\n#define AVR32_USART_RXEN 4\n#define AVR32_USART_RXEN_MASK 0x00000010\n#define AVR32_USART_RXEN_OFFSET 4\n#define AVR32_USART_RXEN_SIZE 1\n#define AVR32_USART_RXRDY 0\n#define AVR32_USART_RXRDY_MASK 0x00000001\n#define AVR32_USART_RXRDY_OFFSET 0\n#define AVR32_USART_RXRDY_SIZE 1\n#define AVR32_USART_RXSYNH 15\n#define AVR32_USART_RXSYNH_MASK 0x00008000\n#define AVR32_USART_RXSYNH_OFFSET 15\n#define AVR32_USART_RXSYNH_SIZE 1\n#define AVR32_USART_RX_MPOL 28\n#define AVR32_USART_RX_MPOL_MASK 0x10000000\n#define AVR32_USART_RX_MPOL_OFFSET 28\n#define AVR32_USART_RX_MPOL_SIZE 1\n#define AVR32_USART_RX_PL 16\n#define AVR32_USART_RX_PL_MASK 0x000f0000\n#define AVR32_USART_RX_PL_OFFSET 16\n#define AVR32_USART_RX_PL_SIZE 4\n#define AVR32_USART_RX_PP 24\n#define AVR32_USART_RX_PP_MASK 0x03000000\n#define AVR32_USART_RX_PP_OFFSET 24\n#define AVR32_USART_RX_PP_SIZE 2\n#define AVR32_USART_SCK 0x00000003\n#define AVR32_USART_SENDA 12\n#define AVR32_USART_SENDA_MASK 0x00001000\n#define AVR32_USART_SENDA_OFFSET 12\n#define AVR32_USART_SENDA_SIZE 1\n#define AVR32_USART_SPACE 0x00000002\n#define AVR32_USART_SPI_MASTER 0x0000000e\n#define AVR32_USART_SPI_SLAVE 0x0000000f\n#define AVR32_USART_STPBRK 10\n#define AVR32_USART_STPBRK_MASK 0x00000400\n#define AVR32_USART_STPBRK_OFFSET 10\n#define AVR32_USART_STPBRK_SIZE 1\n#define AVR32_USART_STTBRK 9\n#define AVR32_USART_STTBRK_MASK 0x00000200\n#define AVR32_USART_STTBRK_OFFSET 9\n#define AVR32_USART_STTBRK_SIZE 1\n#define AVR32_USART_STTTO 11\n#define AVR32_USART_STTTO_MASK 0x00000800\n#define AVR32_USART_STTTO_OFFSET 11\n#define AVR32_USART_STTTO_SIZE 1\n#define AVR32_USART_SUBSCRIBE 0x00000001\n#define AVR32_USART_SYNC 8\n#define AVR32_USART_SYNC_MASK 0x00000100\n#define AVR32_USART_SYNC_OFFSET 8\n#define AVR32_USART_SYNC_SIZE 1\n#define AVR32_USART_TG 0\n#define AVR32_USART_TG_DISABLE 0x00000000\n#define AVR32_USART_TG_MASK 0x000000ff\n#define AVR32_USART_TG_OFFSET 0\n#define AVR32_USART_TG_SIZE 8\n#define AVR32_USART_THR 0x0000001c\n#define AVR32_USART_THR_TXCHR 0\n#define AVR32_USART_THR_TXCHR_MASK 0x000001ff\n#define AVR32_USART_THR_TXCHR_OFFSET 0\n#define AVR32_USART_THR_TXCHR_SIZE 9\n#define AVR32_USART_THR_TXSYNH 15\n#define AVR32_USART_THR_TXSYNH_MASK 0x00008000\n#define AVR32_USART_THR_TXSYNH_OFFSET 15\n#define AVR32_USART_THR_TXSYNH_SIZE 1\n#define AVR32_USART_TIMEOUT 8\n#define AVR32_USART_TIMEOUT_MASK 0x00000100\n#define AVR32_USART_TIMEOUT_OFFSET 8\n#define AVR32_USART_TIMEOUT_SIZE 1\n#define AVR32_USART_TO 0\n#define AVR32_USART_TO_DISABLE 0x00000000\n#define AVR32_USART_TO_MASK 0x0000ffff\n#define AVR32_USART_TO_OFFSET 0\n#define AVR32_USART_TO_SIZE 16\n#define AVR32_USART_TTGR 0x00000028\n#define AVR32_USART_TTGR_TG 0\n#define AVR32_USART_TTGR_TG_DISABLE 0x00000000\n#define AVR32_USART_TTGR_TG_MASK 0x000000ff\n#define AVR32_USART_TTGR_TG_OFFSET 0\n#define AVR32_USART_TTGR_TG_SIZE 8\n#define AVR32_USART_TXBUFE 11\n#define AVR32_USART_TXBUFE_MASK 0x00000800\n#define AVR32_USART_TXBUFE_OFFSET 11\n#define AVR32_USART_TXBUFE_SIZE 1\n#define AVR32_USART_TXCHR 0\n#define AVR32_USART_TXCHR_MASK 0x000001ff\n#define AVR32_USART_TXCHR_OFFSET 0\n#define AVR32_USART_TXCHR_SIZE 9\n#define AVR32_USART_TXDIS 7\n#define AVR32_USART_TXDIS_MASK 0x00000080\n#define AVR32_USART_TXDIS_OFFSET 7\n#define AVR32_USART_TXDIS_SIZE 1\n#define AVR32_USART_TXEMPTY 9\n#define AVR32_USART_TXEMPTY_MASK 0x00000200\n#define AVR32_USART_TXEMPTY_OFFSET 9\n#define AVR32_USART_TXEMPTY_SIZE 1\n#define AVR32_USART_TXEN 6\n#define AVR32_USART_TXEN_MASK 0x00000040\n#define AVR32_USART_TXEN_OFFSET 6\n#define AVR32_USART_TXEN_SIZE 1\n#define AVR32_USART_TXRDY 1\n#define AVR32_USART_TXRDY_MASK 0x00000002\n#define AVR32_USART_TXRDY_OFFSET 1\n#define AVR32_USART_TXRDY_SIZE 1\n#define AVR32_USART_TXSYNH 15\n#define AVR32_USART_TXSYNH_MASK 0x00008000\n#define AVR32_USART_TXSYNH_OFFSET 15\n#define AVR32_USART_TXSYNH_SIZE 1\n#define AVR32_USART_TX_MPOL 12\n#define AVR32_USART_TX_MPOL_MASK 0x00001000\n#define AVR32_USART_TX_MPOL_OFFSET 12\n#define AVR32_USART_TX_MPOL_SIZE 1\n#define AVR32_USART_TX_PL 0\n#define AVR32_USART_TX_PL_MASK 0x0000000f\n#define AVR32_USART_TX_PL_OFFSET 0\n#define AVR32_USART_TX_PL_SIZE 4\n#define AVR32_USART_TX_PP 8\n#define AVR32_USART_TX_PP_MASK 0x00000300\n#define AVR32_USART_TX_PP_OFFSET 8\n#define AVR32_USART_TX_PP_SIZE 2\n#define AVR32_USART_USCLKS 4\n#define AVR32_USART_USCLKS_MASK 0x00000030\n#define AVR32_USART_USCLKS_MCK 0x00000000\n#define AVR32_USART_USCLKS_MCK_DIV 0x00000001\n#define AVR32_USART_USCLKS_OFFSET 4\n#define AVR32_USART_USCLKS_SCK 0x00000003\n#define AVR32_USART_USCLKS_SIZE 2\n#define AVR32_USART_VAR_SYNC 22\n#define AVR32_USART_VAR_SYNC_MASK 0x00400000\n#define AVR32_USART_VAR_SYNC_OFFSET 22\n#define AVR32_USART_VAR_SYNC_SIZE 1\n#define AVR32_USART_VERSION 0x000000fc\n#define AVR32_USART_WKUPTYP 7\n#define AVR32_USART_WKUPTYP_MASK 0x00000080\n#define AVR32_USART_WKUPTYP_OFFSET 7\n#define AVR32_USART_WKUPTYP_SIZE 1\n#define AVR32_USART_X16 0x00000000\n#define AVR32_USART_X8 0x00000001\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_usart_cr_t {\n unsigned int comm_rx : 1;\n unsigned int comm_tx : 1;\n unsigned int : 8;\n unsigned int linwkup : 1;\n unsigned int linabt : 1;\n unsigned int rtsdis : 1;\n unsigned int rtsen : 1;\n unsigned int dtrdis : 1;\n unsigned int dtren : 1;\n unsigned int retto : 1;\n unsigned int rstnack : 1;\n unsigned int rstit : 1;\n unsigned int senda : 1;\n unsigned int sttto : 1;\n unsigned int stpbrk : 1;\n unsigned int sttbrk : 1;\n unsigned int rststa : 1;\n unsigned int txdis : 1;\n unsigned int txen : 1;\n unsigned int rxdis : 1;\n unsigned int rxen : 1;\n unsigned int rsttx : 1;\n unsigned int rstrx : 1;\n unsigned int : 2;\n} avr32_usart_cr_t;\n\n\n\ntypedef struct avr32_usart_mr_t {\n unsigned int onebit : 1;\n unsigned int modsync : 1;\n unsigned int man : 1;\n unsigned int filter : 1;\n unsigned int : 1;\n unsigned int max_iteration : 3;\n unsigned int : 1;\n unsigned int var_sync : 1;\n unsigned int dsnack : 1;\n unsigned int inack : 1;\n unsigned int over : 1;\n unsigned int clko : 1;\n unsigned int mode9 : 1;\n unsigned int msbf : 1;\n unsigned int chmode : 2;\n unsigned int nbstop : 2;\n unsigned int par : 3;\n unsigned int sync : 1;\n unsigned int chrl : 2;\n unsigned int usclks : 2;\n unsigned int mode : 4;\n} avr32_usart_mr_t;\n\n\n\ntypedef struct avr32_usart_ier_t {\n unsigned int comm_rx : 1;\n unsigned int comm_tx : 1;\n unsigned int linsnre : 1;\n unsigned int lince : 1;\n unsigned int linipe : 1;\n unsigned int linisfe : 1;\n unsigned int linbe : 1;\n unsigned int mane : 1;\n unsigned int : 4;\n unsigned int ctsic : 1;\n unsigned int dcdic : 1;\n unsigned int dsric : 1;\n unsigned int riic : 1;\n unsigned int lintc : 1;\n unsigned int linir : 1;\n unsigned int nack : 1;\n unsigned int rxbuff : 1;\n unsigned int txbufe : 1;\n unsigned int iteration : 1;\n unsigned int txempty : 1;\n unsigned int timeout : 1;\n unsigned int pare : 1;\n unsigned int frame : 1;\n unsigned int ovre : 1;\n unsigned int endtx : 1;\n unsigned int endrx : 1;\n unsigned int rxbrk : 1;\n unsigned int txrdy : 1;\n unsigned int rxrdy : 1;\n} avr32_usart_ier_t;\n\n\n\ntypedef struct avr32_usart_idr_t {\n unsigned int comm_rx : 1;\n unsigned int comm_tx : 1;\n unsigned int linsnre : 1;\n unsigned int lince : 1;\n unsigned int linipe : 1;\n unsigned int linisfe : 1;\n unsigned int linbe : 1;\n unsigned int mane : 1;\n unsigned int : 4;\n unsigned int ctsic : 1;\n unsigned int dcdic : 1;\n unsigned int dsric : 1;\n unsigned int riic : 1;\n unsigned int lintc : 1;\n unsigned int linir : 1;\n unsigned int nack : 1;\n unsigned int rxbuff : 1;\n unsigned int txbufe : 1;\n unsigned int iteration : 1;\n unsigned int txempty : 1;\n unsigned int timeout : 1;\n unsigned int pare : 1;\n unsigned int frame : 1;\n unsigned int ovre : 1;\n unsigned int endtx : 1;\n unsigned int endrx : 1;\n unsigned int rxbrk : 1;\n unsigned int txrdy : 1;\n unsigned int rxrdy : 1;\n} avr32_usart_idr_t;\n\n\n\ntypedef struct avr32_usart_imr_t {\n unsigned int comm_rx : 1;\n unsigned int comm_tx : 1;\n unsigned int linsnre : 1;\n unsigned int lince : 1;\n unsigned int linipe : 1;\n unsigned int linisfe : 1;\n unsigned int linbe : 1;\n unsigned int mane : 1;\n unsigned int : 4;\n unsigned int ctsic : 1;\n unsigned int dcdic : 1;\n unsigned int dsric : 1;\n unsigned int riic : 1;\n unsigned int lintc : 1;\n unsigned int linir : 1;\n unsigned int nack : 1;\n unsigned int rxbuff : 1;\n unsigned int txbufe : 1;\n unsigned int iteration : 1;\n unsigned int txempty : 1;\n unsigned int timeout : 1;\n unsigned int pare : 1;\n unsigned int frame : 1;\n unsigned int ovre : 1;\n unsigned int endtx : 1;\n unsigned int endrx : 1;\n unsigned int rxbrk : 1;\n unsigned int txrdy : 1;\n unsigned int rxrdy : 1;\n} avr32_usart_imr_t;\n\n\n\ntypedef struct avr32_usart_csr_t {\n unsigned int comm_rx : 1;\n unsigned int comm_tx : 1;\n unsigned int linsnre : 1;\n unsigned int lince : 1;\n unsigned int linipe : 1;\n unsigned int linisfe : 1;\n unsigned int linbe : 1;\n unsigned int manerr : 1;\n unsigned int cts : 1;\n unsigned int dcd : 1;\n unsigned int dsr : 1;\n unsigned int ri : 1;\n unsigned int ctsic : 1;\n unsigned int dcdic : 1;\n unsigned int dsric : 1;\n unsigned int riic : 1;\n unsigned int lintc : 1;\n unsigned int linir : 1;\n unsigned int nack : 1;\n unsigned int rxbuff : 1;\n unsigned int txbufe : 1;\n unsigned int iteration : 1;\n unsigned int txempty : 1;\n unsigned int timeout : 1;\n unsigned int pare : 1;\n unsigned int frame : 1;\n unsigned int ovre : 1;\n unsigned int endtx : 1;\n unsigned int endrx : 1;\n unsigned int rxbrk : 1;\n unsigned int txrdy : 1;\n unsigned int rxrdy : 1;\n} avr32_usart_csr_t;\n\n\n\ntypedef struct avr32_usart_rhr_t {\n unsigned int :16;\n unsigned int rxsynh : 1;\n unsigned int : 6;\n unsigned int rxchr : 9;\n} avr32_usart_rhr_t;\n\n\n\ntypedef struct avr32_usart_thr_t {\n unsigned int :16;\n unsigned int txsynh : 1;\n unsigned int : 6;\n unsigned int txchr : 9;\n} avr32_usart_thr_t;\n\n\n\ntypedef struct avr32_usart_brgr_t {\n unsigned int :13;\n unsigned int fp : 3;\n unsigned int cd :16;\n} avr32_usart_brgr_t;\n\n\n\ntypedef struct avr32_usart_rtor_t {\n unsigned int :16;\n unsigned int to :16;\n} avr32_usart_rtor_t;\n\n\n\ntypedef struct avr32_usart_ttgr_t {\n unsigned int :24;\n unsigned int tg : 8;\n} avr32_usart_ttgr_t;\n\n\n\ntypedef struct avr32_usart_fidi_t {\n unsigned int :21;\n unsigned int fi_di_ratio :11;\n} avr32_usart_fidi_t;\n\n\n\ntypedef struct avr32_usart_ner_t {\n unsigned int :24;\n unsigned int nb_errors : 8;\n} avr32_usart_ner_t;\n\n\n\ntypedef struct avr32_usart_ifr_t {\n unsigned int :24;\n unsigned int irda_filter : 8;\n} avr32_usart_ifr_t;\n\n\n\ntypedef struct avr32_usart_man_t {\n unsigned int : 1;\n unsigned int drift : 1;\n unsigned int : 1;\n unsigned int rx_mpol : 1;\n unsigned int : 2;\n unsigned int rx_pp : 2;\n unsigned int : 4;\n unsigned int rx_pl : 4;\n unsigned int : 3;\n unsigned int tx_mpol : 1;\n unsigned int : 2;\n unsigned int tx_pp : 2;\n unsigned int : 4;\n unsigned int tx_pl : 4;\n} avr32_usart_man_t;\n\n\n\ntypedef struct avr32_usart_linmr_t {\n unsigned int :15;\n unsigned int pdcm : 1;\n unsigned int dlc : 8;\n unsigned int wkuptyp : 1;\n unsigned int fsdis : 1;\n unsigned int dlm : 1;\n unsigned int chktyp : 1;\n unsigned int chkdis : 1;\n unsigned int pardis : 1;\n unsigned int nact : 2;\n} avr32_usart_linmr_t;\n\n\n\ntypedef struct avr32_usart_linir_t {\n unsigned int :24;\n unsigned int idchr : 8;\n} avr32_usart_linir_t;\n\n\n\ntypedef struct avr32_usart_t {\n union {\n unsigned long cr ;//0x0000\n avr32_usart_cr_t CR ;\n };\n union {\n unsigned long mr ;//0x0004\n avr32_usart_mr_t MR ;\n };\n union {\n unsigned long ier ;//0x0008\n avr32_usart_ier_t IER ;\n };\n union {\n unsigned long idr ;//0x000c\n avr32_usart_idr_t IDR ;\n };\n union {\n const unsigned long imr ;//0x0010\n const avr32_usart_imr_t IMR ;\n };\n union {\n const unsigned long csr ;//0x0014\n const avr32_usart_csr_t CSR ;\n };\n union {\n const unsigned long rhr ;//0x0018\n const avr32_usart_rhr_t RHR ;\n };\n union {\n unsigned long thr ;//0x001c\n avr32_usart_thr_t THR ;\n };\n union {\n unsigned long brgr ;//0x0020\n avr32_usart_brgr_t BRGR ;\n };\n union {\n unsigned long rtor ;//0x0024\n avr32_usart_rtor_t RTOR ;\n };\n union {\n unsigned long ttgr ;//0x0028\n avr32_usart_ttgr_t TTGR ;\n };\n unsigned int :32 ;//0x002c\n unsigned int :32 ;//0x0030\n unsigned int :32 ;//0x0034\n unsigned int :32 ;//0x0038\n unsigned int :32 ;//0x003c\n union {\n unsigned long fidi ;//0x0040\n avr32_usart_fidi_t FIDI ;\n };\n union {\n const unsigned long ner ;//0x0044\n const avr32_usart_ner_t NER ;\n };\n unsigned int :32 ;//0x0048\n union {\n unsigned long ifr ;//0x004c\n avr32_usart_ifr_t IFR ;\n };\n union {\n unsigned long man ;//0x0050\n avr32_usart_man_t MAN ;\n };\n union {\n unsigned long linmr ;//0x0054\n avr32_usart_linmr_t LINMR ;\n };\n union {\n unsigned long linir ;//0x0058\n avr32_usart_linir_t LINIR ;\n };\n unsigned int :32 ;//0x005c\n unsigned int :32 ;//0x0060\n unsigned int :32 ;//0x0064\n unsigned int :32 ;//0x0068\n unsigned int :32 ;//0x006c\n unsigned int :32 ;//0x0070\n unsigned int :32 ;//0x0074\n unsigned int :32 ;//0x0078\n unsigned int :32 ;//0x007c\n unsigned int :32 ;//0x0080\n unsigned int :32 ;//0x0084\n unsigned int :32 ;//0x0088\n unsigned int :32 ;//0x008c\n unsigned int :32 ;//0x0090\n unsigned int :32 ;//0x0094\n unsigned int :32 ;//0x0098\n unsigned int :32 ;//0x009c\n unsigned int :32 ;//0x00a0\n unsigned int :32 ;//0x00a4\n unsigned int :32 ;//0x00a8\n unsigned int :32 ;//0x00ac\n unsigned int :32 ;//0x00b0\n unsigned int :32 ;//0x00b4\n unsigned int :32 ;//0x00b8\n unsigned int :32 ;//0x00bc\n unsigned int :32 ;//0x00c0\n unsigned int :32 ;//0x00c4\n unsigned int :32 ;//0x00c8\n unsigned int :32 ;//0x00cc\n unsigned int :32 ;//0x00d0\n unsigned int :32 ;//0x00d4\n unsigned int :32 ;//0x00d8\n unsigned int :32 ;//0x00dc\n unsigned int :32 ;//0x00e0\n unsigned int :32 ;//0x00e4\n unsigned int :32 ;//0x00e8\n unsigned int :32 ;//0x00ec\n unsigned int :32 ;//0x00f0\n unsigned int :32 ;//0x00f4\n unsigned int :32 ;//0x00f8\n const unsigned long version ;//0x00fc\n} avr32_usart_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n/*#ifdef AVR32_USART_400_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/usbb_310.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3000\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_USBB_310_H_INCLUDED\n#define AVR32_USBB_310_H_INCLUDED\n\n#define AVR32_USBB_H_VERSION 310\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_USBB_\n - Bitfield mask: AVR32_USBB__\n - Bitfield offset: AVR32_USBB___OFFSET\n - Bitfield size: AVR32_USBB___SIZE\n - Bitfield values: AVR32_USBB___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_USBB_\n - Bitfield offset: AVR32_USBB__OFFSET\n - Bitfield size: AVR32_USBB__SIZE\n - Bitfield values: AVR32_USBB__\n - Bitfield values: AVR32_USBB_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_USBB_1024 0x00000007\n#define AVR32_USBB_128 0x00000004\n#define AVR32_USBB_16 0x00000001\n#define AVR32_USBB_16_BITS 0x00000000\n#define AVR32_USBB_24_BITS 0x00000001\n#define AVR32_USBB_256 0x00000005\n#define AVR32_USBB_32 0x00000002\n#define AVR32_USBB_512 0x00000006\n#define AVR32_USBB_64 0x00000003\n#define AVR32_USBB_8 0x00000000\n#define AVR32_USBB_ADDEN 7\n#define AVR32_USBB_ADDEN_MASK 0x00000080\n#define AVR32_USBB_ADDEN_OFFSET 7\n#define AVR32_USBB_ADDEN_SIZE 1\n#define AVR32_USBB_ALLOC 1\n#define AVR32_USBB_ALLOC_MASK 0x00000002\n#define AVR32_USBB_ALLOC_OFFSET 1\n#define AVR32_USBB_ALLOC_SIZE 1\n#define AVR32_USBB_AUTOSW_SIZE 1\n#define AVR32_USBB_A_HOST 0x00000003\n#define AVR32_USBB_A_IDLE 0x00000000\n#define AVR32_USBB_A_PERIPHERAL 0x00000005\n#define AVR32_USBB_A_SUSPEND 0x00000004\n#define AVR32_USBB_A_VBUS_ERR 0x00000007\n#define AVR32_USBB_A_WAIT_BCON 0x00000002\n#define AVR32_USBB_A_WAIT_DISCHARGE 0x00000008\n#define AVR32_USBB_A_WAIT_VFALL 0x00000006\n#define AVR32_USBB_A_WAIT_VRISE_100_MS 0x00000003\n#define AVR32_USBB_A_WAIT_VRISE_20_MS 0x00000000\n#define AVR32_USBB_A_WAIT_VRISE_50_MS 0x00000001\n#define AVR32_USBB_A_WAIT_VRISE_70_MS 0x00000002\n#define AVR32_USBB_BCERRE 4\n#define AVR32_USBB_BCERRE_MASK 0x00000010\n#define AVR32_USBB_BCERRE_OFFSET 4\n#define AVR32_USBB_BCERRE_SIZE 1\n#define AVR32_USBB_BCERRI 4\n#define AVR32_USBB_BCERRIC 4\n#define AVR32_USBB_BCERRIC_MASK 0x00000010\n#define AVR32_USBB_BCERRIC_OFFSET 4\n#define AVR32_USBB_BCERRIC_SIZE 1\n#define AVR32_USBB_BCERRIS 4\n#define AVR32_USBB_BCERRIS_MASK 0x00000010\n#define AVR32_USBB_BCERRIS_OFFSET 4\n#define AVR32_USBB_BCERRIS_SIZE 1\n#define AVR32_USBB_BCERRI_MASK 0x00000010\n#define AVR32_USBB_BCERRI_OFFSET 4\n#define AVR32_USBB_BCERRI_SIZE 1\n#define AVR32_USBB_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_BULK 0x00000002\n#define AVR32_USBB_BURST_LOCK_EN 7\n#define AVR32_USBB_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_BYCT 20\n#define AVR32_USBB_BYCT_MASK 0x7ff00000\n#define AVR32_USBB_BYCT_OFFSET 20\n#define AVR32_USBB_BYCT_SIZE 11\n#define AVR32_USBB_BYPASSDPLL 5\n#define AVR32_USBB_BYPASSDPLL_MASK 0x00000020\n#define AVR32_USBB_BYPASSDPLL_OFFSET 5\n#define AVR32_USBB_BYPASSDPLL_SIZE 1\n#define AVR32_USBB_BYTE_WRITE_DPRAM 15\n#define AVR32_USBB_BYTE_WRITE_DPRAM_MASK 0x00008000\n#define AVR32_USBB_BYTE_WRITE_DPRAM_OFFSET 15\n#define AVR32_USBB_BYTE_WRITE_DPRAM_SIZE 1\n#define AVR32_USBB_B_HOST 0x0000000e\n#define AVR32_USBB_B_IDLE 0x00000009\n#define AVR32_USBB_B_PERIPHERAL 0x0000000a\n#define AVR32_USBB_B_SRP_INIT 0x0000000f\n#define AVR32_USBB_B_WAIT_ACON 0x0000000d\n#define AVR32_USBB_B_WAIT_BEGIN_HNP 0x0000000b\n#define AVR32_USBB_B_WAIT_DISCHARGE 0x0000000c\n#define AVR32_USBB_CFGOK 18\n#define AVR32_USBB_CFGOK_MASK 0x00040000\n#define AVR32_USBB_CFGOK_OFFSET 18\n#define AVR32_USBB_CFGOK_SIZE 1\n#define AVR32_USBB_CH_ACTIVE 1\n#define AVR32_USBB_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_CH_BYTE_CNT 16\n#define AVR32_USBB_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_CH_BYTE_LENGTH 16\n#define AVR32_USBB_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_CH_EN 0\n#define AVR32_USBB_CH_EN_MASK 0x00000001\n#define AVR32_USBB_CH_EN_OFFSET 0\n#define AVR32_USBB_CH_EN_SIZE 1\n#define AVR32_USBB_CLKUSABLE_SIZE 1\n#define AVR32_USBB_CONTROL 0x00000000\n#define AVR32_USBB_COUNTER 5\n#define AVR32_USBB_COUNTERA 0\n#define AVR32_USBB_COUNTERA_MASK 0x00007fff\n#define AVR32_USBB_COUNTERA_OFFSET 0\n#define AVR32_USBB_COUNTERA_SIZE 15\n#define AVR32_USBB_COUNTERB 16\n#define AVR32_USBB_COUNTERB_MASK 0x003f0000\n#define AVR32_USBB_COUNTERB_OFFSET 16\n#define AVR32_USBB_COUNTERB_SIZE 6\n#define AVR32_USBB_COUNTER_MASK 0x00000060\n#define AVR32_USBB_COUNTER_OFFSET 5\n#define AVR32_USBB_COUNTER_SIZE 2\n#define AVR32_USBB_CRC16 4\n#define AVR32_USBB_CRC16_MASK 0x00000010\n#define AVR32_USBB_CRC16_OFFSET 4\n#define AVR32_USBB_CRC16_SIZE 1\n#define AVR32_USBB_CTRLDIR 17\n#define AVR32_USBB_CTRLDIR_IN 0x00000001\n#define AVR32_USBB_CTRLDIR_MASK 0x00020000\n#define AVR32_USBB_CTRLDIR_OFFSET 17\n#define AVR32_USBB_CTRLDIR_OUT 0x00000000\n#define AVR32_USBB_CTRLDIR_SIZE 1\n#define AVR32_USBB_CURRBK 14\n#define AVR32_USBB_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_CURRBK_OFFSET 14\n#define AVR32_USBB_CURRBK_SIZE 2\n#define AVR32_USBB_DAM6INTEC 30\n#define AVR32_USBB_DAM6INTEC_MASK 0x40000000\n#define AVR32_USBB_DAM6INTEC_OFFSET 30\n#define AVR32_USBB_DAM6INTEC_SIZE 1\n#define AVR32_USBB_DATAPID 1\n#define AVR32_USBB_DATAPID_MASK 0x00000002\n#define AVR32_USBB_DATAPID_OFFSET 1\n#define AVR32_USBB_DATAPID_SIZE 1\n#define AVR32_USBB_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_DATATGL 0\n#define AVR32_USBB_DATATGL_MASK 0x00000001\n#define AVR32_USBB_DATATGL_OFFSET 0\n#define AVR32_USBB_DATATGL_SIZE 1\n#define AVR32_USBB_DATAXE 9\n#define AVR32_USBB_DATAXEC 9\n#define AVR32_USBB_DATAXEC_MASK 0x00000200\n#define AVR32_USBB_DATAXEC_OFFSET 9\n#define AVR32_USBB_DATAXEC_SIZE 1\n#define AVR32_USBB_DATAXES 9\n#define AVR32_USBB_DATAXES_MASK 0x00000200\n#define AVR32_USBB_DATAXES_OFFSET 9\n#define AVR32_USBB_DATAXES_SIZE 1\n#define AVR32_USBB_DATAXE_MASK 0x00000200\n#define AVR32_USBB_DATAXE_OFFSET 9\n#define AVR32_USBB_DATAXE_SIZE 1\n#define AVR32_USBB_DATA_BUS_8_16 16\n#define AVR32_USBB_DATA_BUS_8_16_MASK 0x00010000\n#define AVR32_USBB_DATA_BUS_8_16_OFFSET 16\n#define AVR32_USBB_DATA_BUS_8_16_SIZE 1\n#define AVR32_USBB_DCONNI 0\n#define AVR32_USBB_DCONNIC 0\n#define AVR32_USBB_DCONNIC_MASK 0x00000001\n#define AVR32_USBB_DCONNIC_OFFSET 0\n#define AVR32_USBB_DCONNIC_SIZE 1\n#define AVR32_USBB_DCONNIE 0\n#define AVR32_USBB_DCONNIEC 0\n#define AVR32_USBB_DCONNIEC_MASK 0x00000001\n#define AVR32_USBB_DCONNIEC_OFFSET 0\n#define AVR32_USBB_DCONNIEC_SIZE 1\n#define AVR32_USBB_DCONNIES 0\n#define AVR32_USBB_DCONNIES_MASK 0x00000001\n#define AVR32_USBB_DCONNIES_OFFSET 0\n#define AVR32_USBB_DCONNIES_SIZE 1\n#define AVR32_USBB_DCONNIE_MASK 0x00000001\n#define AVR32_USBB_DCONNIE_OFFSET 0\n#define AVR32_USBB_DCONNIE_SIZE 1\n#define AVR32_USBB_DCONNIS 0\n#define AVR32_USBB_DCONNIS_MASK 0x00000001\n#define AVR32_USBB_DCONNIS_OFFSET 0\n#define AVR32_USBB_DCONNIS_SIZE 1\n#define AVR32_USBB_DCONNI_MASK 0x00000001\n#define AVR32_USBB_DCONNI_OFFSET 0\n#define AVR32_USBB_DCONNI_SIZE 1\n#define AVR32_USBB_DDISCI 1\n#define AVR32_USBB_DDISCIC 1\n#define AVR32_USBB_DDISCIC_MASK 0x00000002\n#define AVR32_USBB_DDISCIC_OFFSET 1\n#define AVR32_USBB_DDISCIC_SIZE 1\n#define AVR32_USBB_DDISCIE 1\n#define AVR32_USBB_DDISCIEC 1\n#define AVR32_USBB_DDISCIEC_MASK 0x00000002\n#define AVR32_USBB_DDISCIEC_OFFSET 1\n#define AVR32_USBB_DDISCIEC_SIZE 1\n#define AVR32_USBB_DDISCIES 1\n#define AVR32_USBB_DDISCIES_MASK 0x00000002\n#define AVR32_USBB_DDISCIES_OFFSET 1\n#define AVR32_USBB_DDISCIES_SIZE 1\n#define AVR32_USBB_DDISCIE_MASK 0x00000002\n#define AVR32_USBB_DDISCIE_OFFSET 1\n#define AVR32_USBB_DDISCIE_SIZE 1\n#define AVR32_USBB_DDISCIS 1\n#define AVR32_USBB_DDISCIS_MASK 0x00000002\n#define AVR32_USBB_DDISCIS_OFFSET 1\n#define AVR32_USBB_DDISCIS_SIZE 1\n#define AVR32_USBB_DDISCI_MASK 0x00000002\n#define AVR32_USBB_DDISCI_OFFSET 1\n#define AVR32_USBB_DDISCI_SIZE 1\n#define AVR32_USBB_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_DESC_LD_STA 6\n#define AVR32_USBB_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_DETACH 8\n#define AVR32_USBB_DETACH_MASK 0x00000100\n#define AVR32_USBB_DETACH_OFFSET 8\n#define AVR32_USBB_DETACH_SIZE 1\n#define AVR32_USBB_DISBALEGATEDCLOCK 3\n#define AVR32_USBB_DISBALEGATEDCLOCK_MASK 0x00000008\n#define AVR32_USBB_DISBALEGATEDCLOCK_OFFSET 3\n#define AVR32_USBB_DISBALEGATEDCLOCK_SIZE 1\n#define AVR32_USBB_DMA1INT 25\n#define AVR32_USBB_DMA1INTE 25\n#define AVR32_USBB_DMA1INTEC 25\n#define AVR32_USBB_DMA1INTEC_MASK 0x02000000\n#define AVR32_USBB_DMA1INTEC_OFFSET 25\n#define AVR32_USBB_DMA1INTEC_SIZE 1\n#define AVR32_USBB_DMA1INTES 25\n#define AVR32_USBB_DMA1INTES_MASK 0x02000000\n#define AVR32_USBB_DMA1INTES_OFFSET 25\n#define AVR32_USBB_DMA1INTES_SIZE 1\n#define AVR32_USBB_DMA1INTE_MASK 0x02000000\n#define AVR32_USBB_DMA1INTE_OFFSET 25\n#define AVR32_USBB_DMA1INTE_SIZE 1\n#define AVR32_USBB_DMA1INTS 25\n#define AVR32_USBB_DMA1INTS_MASK 0x02000000\n#define AVR32_USBB_DMA1INTS_OFFSET 25\n#define AVR32_USBB_DMA1INTS_SIZE 1\n#define AVR32_USBB_DMA1INT_MASK 0x02000000\n#define AVR32_USBB_DMA1INT_OFFSET 25\n#define AVR32_USBB_DMA1INT_SIZE 1\n#define AVR32_USBB_DMA2INT 26\n#define AVR32_USBB_DMA2INTE 26\n#define AVR32_USBB_DMA2INTEC 26\n#define AVR32_USBB_DMA2INTEC_MASK 0x04000000\n#define AVR32_USBB_DMA2INTEC_OFFSET 26\n#define AVR32_USBB_DMA2INTEC_SIZE 1\n#define AVR32_USBB_DMA2INTES 26\n#define AVR32_USBB_DMA2INTES_MASK 0x04000000\n#define AVR32_USBB_DMA2INTES_OFFSET 26\n#define AVR32_USBB_DMA2INTES_SIZE 1\n#define AVR32_USBB_DMA2INTE_MASK 0x04000000\n#define AVR32_USBB_DMA2INTE_OFFSET 26\n#define AVR32_USBB_DMA2INTE_SIZE 1\n#define AVR32_USBB_DMA2INTS 26\n#define AVR32_USBB_DMA2INTS_MASK 0x04000000\n#define AVR32_USBB_DMA2INTS_OFFSET 26\n#define AVR32_USBB_DMA2INTS_SIZE 1\n#define AVR32_USBB_DMA2INT_MASK 0x04000000\n#define AVR32_USBB_DMA2INT_OFFSET 26\n#define AVR32_USBB_DMA2INT_SIZE 1\n#define AVR32_USBB_DMA3INT 27\n#define AVR32_USBB_DMA3INTE 27\n#define AVR32_USBB_DMA3INTEC 27\n#define AVR32_USBB_DMA3INTEC_MASK 0x08000000\n#define AVR32_USBB_DMA3INTEC_OFFSET 27\n#define AVR32_USBB_DMA3INTEC_SIZE 1\n#define AVR32_USBB_DMA3INTES 27\n#define AVR32_USBB_DMA3INTES_MASK 0x08000000\n#define AVR32_USBB_DMA3INTES_OFFSET 27\n#define AVR32_USBB_DMA3INTES_SIZE 1\n#define AVR32_USBB_DMA3INTE_MASK 0x08000000\n#define AVR32_USBB_DMA3INTE_OFFSET 27\n#define AVR32_USBB_DMA3INTE_SIZE 1\n#define AVR32_USBB_DMA3INTS 27\n#define AVR32_USBB_DMA3INTS_MASK 0x08000000\n#define AVR32_USBB_DMA3INTS_OFFSET 27\n#define AVR32_USBB_DMA3INTS_SIZE 1\n#define AVR32_USBB_DMA3INT_MASK 0x08000000\n#define AVR32_USBB_DMA3INT_OFFSET 27\n#define AVR32_USBB_DMA3INT_SIZE 1\n#define AVR32_USBB_DMA4INT 28\n#define AVR32_USBB_DMA4INTE 28\n#define AVR32_USBB_DMA4INTEC 28\n#define AVR32_USBB_DMA4INTEC_MASK 0x10000000\n#define AVR32_USBB_DMA4INTEC_OFFSET 28\n#define AVR32_USBB_DMA4INTEC_SIZE 1\n#define AVR32_USBB_DMA4INTES 28\n#define AVR32_USBB_DMA4INTES_MASK 0x10000000\n#define AVR32_USBB_DMA4INTES_OFFSET 28\n#define AVR32_USBB_DMA4INTES_SIZE 1\n#define AVR32_USBB_DMA4INTE_MASK 0x10000000\n#define AVR32_USBB_DMA4INTE_OFFSET 28\n#define AVR32_USBB_DMA4INTE_SIZE 1\n#define AVR32_USBB_DMA4INTS 28\n#define AVR32_USBB_DMA4INTS_MASK 0x10000000\n#define AVR32_USBB_DMA4INTS_OFFSET 28\n#define AVR32_USBB_DMA4INTS_SIZE 1\n#define AVR32_USBB_DMA4INT_MASK 0x10000000\n#define AVR32_USBB_DMA4INT_OFFSET 28\n#define AVR32_USBB_DMA4INT_SIZE 1\n#define AVR32_USBB_DMA5INT 29\n#define AVR32_USBB_DMA5INTE 29\n#define AVR32_USBB_DMA5INTEC 29\n#define AVR32_USBB_DMA5INTEC_MASK 0x20000000\n#define AVR32_USBB_DMA5INTEC_OFFSET 29\n#define AVR32_USBB_DMA5INTEC_SIZE 1\n#define AVR32_USBB_DMA5INTES 29\n#define AVR32_USBB_DMA5INTES_MASK 0x20000000\n#define AVR32_USBB_DMA5INTES_OFFSET 29\n#define AVR32_USBB_DMA5INTES_SIZE 1\n#define AVR32_USBB_DMA5INTE_MASK 0x20000000\n#define AVR32_USBB_DMA5INTE_OFFSET 29\n#define AVR32_USBB_DMA5INTE_SIZE 1\n#define AVR32_USBB_DMA5INTS 29\n#define AVR32_USBB_DMA5INTS_MASK 0x20000000\n#define AVR32_USBB_DMA5INTS_OFFSET 29\n#define AVR32_USBB_DMA5INTS_SIZE 1\n#define AVR32_USBB_DMA5INT_MASK 0x20000000\n#define AVR32_USBB_DMA5INT_OFFSET 29\n#define AVR32_USBB_DMA5INT_SIZE 1\n#define AVR32_USBB_DMA6INT 30\n#define AVR32_USBB_DMA6INTE 30\n#define AVR32_USBB_DMA6INTEC 30\n#define AVR32_USBB_DMA6INTEC_MASK 0x40000000\n#define AVR32_USBB_DMA6INTEC_OFFSET 30\n#define AVR32_USBB_DMA6INTEC_SIZE 1\n#define AVR32_USBB_DMA6INTES 30\n#define AVR32_USBB_DMA6INTES_MASK 0x40000000\n#define AVR32_USBB_DMA6INTES_OFFSET 30\n#define AVR32_USBB_DMA6INTES_SIZE 1\n#define AVR32_USBB_DMA6INTE_MASK 0x40000000\n#define AVR32_USBB_DMA6INTE_OFFSET 30\n#define AVR32_USBB_DMA6INTE_SIZE 1\n#define AVR32_USBB_DMA6INTS 30\n#define AVR32_USBB_DMA6INTS_MASK 0x40000000\n#define AVR32_USBB_DMA6INTS_OFFSET 30\n#define AVR32_USBB_DMA6INTS_SIZE 1\n#define AVR32_USBB_DMA6INT_MASK 0x40000000\n#define AVR32_USBB_DMA6INT_OFFSET 30\n#define AVR32_USBB_DMA6INT_SIZE 1\n#define AVR32_USBB_DMAEND_EN 3\n#define AVR32_USBB_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_DMAEND_EN_SIZE 1\n#define AVR32_USBB_DMA_BUFFER_SIZE 7\n#define AVR32_USBB_DMA_BUFFER_SIZE_16_BITS 0x00000000\n#define AVR32_USBB_DMA_BUFFER_SIZE_24_BITS 0x00000001\n#define AVR32_USBB_DMA_BUFFER_SIZE_MASK 0x00000080\n#define AVR32_USBB_DMA_BUFFER_SIZE_OFFSET 7\n#define AVR32_USBB_DMA_BUFFER_SIZE_SIZE 1\n#define AVR32_USBB_DMA_CHANNEL_NBR 4\n#define AVR32_USBB_DMA_CHANNEL_NBR_MASK 0x00000070\n#define AVR32_USBB_DMA_CHANNEL_NBR_OFFSET 4\n#define AVR32_USBB_DMA_CHANNEL_NBR_SIZE 3\n#define AVR32_USBB_DMA_FIFO_WORD_DEPTH 8\n#define AVR32_USBB_DMA_FIFO_WORD_DEPTH_MASK 0x00000f00\n#define AVR32_USBB_DMA_FIFO_WORD_DEPTH_OFFSET 8\n#define AVR32_USBB_DMA_FIFO_WORD_DEPTH_SIZE 4\n#define AVR32_USBB_DOUBLE 0x00000001\n#define AVR32_USBB_DRDSTATE 0\n#define AVR32_USBB_DRDSTATE_A_HOST 0x00000003\n#define AVR32_USBB_DRDSTATE_A_IDLE 0x00000000\n#define AVR32_USBB_DRDSTATE_A_PERIPHERAL 0x00000005\n#define AVR32_USBB_DRDSTATE_A_SUSPEND 0x00000004\n#define AVR32_USBB_DRDSTATE_A_VBUS_ERR 0x00000007\n#define AVR32_USBB_DRDSTATE_A_WAIT_BCON 0x00000002\n#define AVR32_USBB_DRDSTATE_A_WAIT_DISCHARGE 0x00000008\n#define AVR32_USBB_DRDSTATE_A_WAIT_VFALL 0x00000006\n#define AVR32_USBB_DRDSTATE_A_WAIT_VRISE 0x00000001\n#define AVR32_USBB_DRDSTATE_B_HOST 0x0000000e\n#define AVR32_USBB_DRDSTATE_B_IDLE 0x00000009\n#define AVR32_USBB_DRDSTATE_B_PERIPHERAL 0x0000000a\n#define AVR32_USBB_DRDSTATE_B_SRP_INIT 0x0000000f\n#define AVR32_USBB_DRDSTATE_B_WAIT_ACON 0x0000000d\n#define AVR32_USBB_DRDSTATE_B_WAIT_BEGIN_HNP 0x0000000b\n#define AVR32_USBB_DRDSTATE_B_WAIT_DISCHARGE 0x0000000c\n#define AVR32_USBB_DRDSTATE_MASK 0x0000000f\n#define AVR32_USBB_DRDSTATE_OFFSET 0\n#define AVR32_USBB_DRDSTATE_SIZE 4\n#define AVR32_USBB_DTSEQ 8\n#define AVR32_USBB_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_DTSEQ_OFFSET 8\n#define AVR32_USBB_DTSEQ_SIZE 2\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_1 17\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_10 26\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_10_MASK 0x04000000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_10_OFFSET 26\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_10_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_11 27\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_11_MASK 0x08000000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_11_OFFSET 27\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_11_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_12 28\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_12_MASK 0x10000000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_12_OFFSET 28\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_12_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_13 29\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_13_MASK 0x20000000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_13_OFFSET 29\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_13_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_14 30\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_14_MASK 0x40000000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_14_OFFSET 30\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_14_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_15 31\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_15_MASK 0x80000000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_15_OFFSET 31\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_15_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_1_MASK 0x00020000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_1_OFFSET 17\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_1_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_2 18\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_2_MASK 0x00040000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_2_OFFSET 18\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_2_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_3 19\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_3_MASK 0x00080000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_3_OFFSET 19\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_3_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_4 20\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_4_MASK 0x00100000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_4_OFFSET 20\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_4_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_5 21\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_5_MASK 0x00200000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_5_OFFSET 21\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_5_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_6 22\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_6_MASK 0x00400000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_6_OFFSET 22\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_6_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_7 23\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_7_MASK 0x00800000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_7_OFFSET 23\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_7_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_8 24\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_8_MASK 0x01000000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_8_OFFSET 24\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_8_SIZE 1\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_9 25\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_9_MASK 0x02000000\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_9_OFFSET 25\n#define AVR32_USBB_EN_HIGH_BD_ISO_EPT_9_SIZE 1\n#define AVR32_USBB_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_EOCH_BUFF_STA 5\n#define AVR32_USBB_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_EORSM 5\n#define AVR32_USBB_EORSMC 5\n#define AVR32_USBB_EORSMC_MASK 0x00000020\n#define AVR32_USBB_EORSMC_OFFSET 5\n#define AVR32_USBB_EORSMC_SIZE 1\n#define AVR32_USBB_EORSME 5\n#define AVR32_USBB_EORSMEC 5\n#define AVR32_USBB_EORSMEC_MASK 0x00000020\n#define AVR32_USBB_EORSMEC_OFFSET 5\n#define AVR32_USBB_EORSMEC_SIZE 1\n#define AVR32_USBB_EORSMES 5\n#define AVR32_USBB_EORSMES_MASK 0x00000020\n#define AVR32_USBB_EORSMES_OFFSET 5\n#define AVR32_USBB_EORSMES_SIZE 1\n#define AVR32_USBB_EORSME_MASK 0x00000020\n#define AVR32_USBB_EORSME_OFFSET 5\n#define AVR32_USBB_EORSME_SIZE 1\n#define AVR32_USBB_EORSMS 5\n#define AVR32_USBB_EORSMS_MASK 0x00000020\n#define AVR32_USBB_EORSMS_OFFSET 5\n#define AVR32_USBB_EORSMS_SIZE 1\n#define AVR32_USBB_EORSM_MASK 0x00000020\n#define AVR32_USBB_EORSM_OFFSET 5\n#define AVR32_USBB_EORSM_SIZE 1\n#define AVR32_USBB_EORST 3\n#define AVR32_USBB_EORSTC 3\n#define AVR32_USBB_EORSTC_MASK 0x00000008\n#define AVR32_USBB_EORSTC_OFFSET 3\n#define AVR32_USBB_EORSTC_SIZE 1\n#define AVR32_USBB_EORSTE 3\n#define AVR32_USBB_EORSTEC 3\n#define AVR32_USBB_EORSTEC_MASK 0x00000008\n#define AVR32_USBB_EORSTEC_OFFSET 3\n#define AVR32_USBB_EORSTEC_SIZE 1\n#define AVR32_USBB_EORSTES 3\n#define AVR32_USBB_EORSTES_MASK 0x00000008\n#define AVR32_USBB_EORSTES_OFFSET 3\n#define AVR32_USBB_EORSTES_SIZE 1\n#define AVR32_USBB_EORSTE_MASK 0x00000008\n#define AVR32_USBB_EORSTE_OFFSET 3\n#define AVR32_USBB_EORSTE_SIZE 1\n#define AVR32_USBB_EORSTS 3\n#define AVR32_USBB_EORSTS_MASK 0x00000008\n#define AVR32_USBB_EORSTS_OFFSET 3\n#define AVR32_USBB_EORSTS_SIZE 1\n#define AVR32_USBB_EORST_MASK 0x00000008\n#define AVR32_USBB_EORST_OFFSET 3\n#define AVR32_USBB_EORST_SIZE 1\n#define AVR32_USBB_EOT_IRQ_EN 4\n#define AVR32_USBB_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_EOT_STA 4\n#define AVR32_USBB_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_EOT_STA_OFFSET 4\n#define AVR32_USBB_EOT_STA_SIZE 1\n#define AVR32_USBB_EP0INT 12\n#define AVR32_USBB_EP0INTE 12\n#define AVR32_USBB_EP0INTEC 12\n#define AVR32_USBB_EP0INTEC_MASK 0x00001000\n#define AVR32_USBB_EP0INTEC_OFFSET 12\n#define AVR32_USBB_EP0INTEC_SIZE 1\n#define AVR32_USBB_EP0INTES 12\n#define AVR32_USBB_EP0INTES_MASK 0x00001000\n#define AVR32_USBB_EP0INTES_OFFSET 12\n#define AVR32_USBB_EP0INTES_SIZE 1\n#define AVR32_USBB_EP0INTE_MASK 0x00001000\n#define AVR32_USBB_EP0INTE_OFFSET 12\n#define AVR32_USBB_EP0INTE_SIZE 1\n#define AVR32_USBB_EP0INT_MASK 0x00001000\n#define AVR32_USBB_EP0INT_OFFSET 12\n#define AVR32_USBB_EP0INT_SIZE 1\n#define AVR32_USBB_EP1INT 13\n#define AVR32_USBB_EP1INTE 13\n#define AVR32_USBB_EP1INTEC 13\n#define AVR32_USBB_EP1INTEC_MASK 0x00002000\n#define AVR32_USBB_EP1INTEC_OFFSET 13\n#define AVR32_USBB_EP1INTEC_SIZE 1\n#define AVR32_USBB_EP1INTES 13\n#define AVR32_USBB_EP1INTES_MASK 0x00002000\n#define AVR32_USBB_EP1INTES_OFFSET 13\n#define AVR32_USBB_EP1INTES_SIZE 1\n#define AVR32_USBB_EP1INTE_MASK 0x00002000\n#define AVR32_USBB_EP1INTE_OFFSET 13\n#define AVR32_USBB_EP1INTE_SIZE 1\n#define AVR32_USBB_EP1INT_MASK 0x00002000\n#define AVR32_USBB_EP1INT_OFFSET 13\n#define AVR32_USBB_EP1INT_SIZE 1\n#define AVR32_USBB_EP2INT 14\n#define AVR32_USBB_EP2INTE 14\n#define AVR32_USBB_EP2INTEC 14\n#define AVR32_USBB_EP2INTEC_MASK 0x00004000\n#define AVR32_USBB_EP2INTEC_OFFSET 14\n#define AVR32_USBB_EP2INTEC_SIZE 1\n#define AVR32_USBB_EP2INTES 14\n#define AVR32_USBB_EP2INTES_MASK 0x00004000\n#define AVR32_USBB_EP2INTES_OFFSET 14\n#define AVR32_USBB_EP2INTES_SIZE 1\n#define AVR32_USBB_EP2INTE_MASK 0x00004000\n#define AVR32_USBB_EP2INTE_OFFSET 14\n#define AVR32_USBB_EP2INTE_SIZE 1\n#define AVR32_USBB_EP2INT_MASK 0x00004000\n#define AVR32_USBB_EP2INT_OFFSET 14\n#define AVR32_USBB_EP2INT_SIZE 1\n#define AVR32_USBB_EP3INT 15\n#define AVR32_USBB_EP3INTE 15\n#define AVR32_USBB_EP3INTEC 15\n#define AVR32_USBB_EP3INTEC_MASK 0x00008000\n#define AVR32_USBB_EP3INTEC_OFFSET 15\n#define AVR32_USBB_EP3INTEC_SIZE 1\n#define AVR32_USBB_EP3INTES 15\n#define AVR32_USBB_EP3INTES_MASK 0x00008000\n#define AVR32_USBB_EP3INTES_OFFSET 15\n#define AVR32_USBB_EP3INTES_SIZE 1\n#define AVR32_USBB_EP3INTE_MASK 0x00008000\n#define AVR32_USBB_EP3INTE_OFFSET 15\n#define AVR32_USBB_EP3INTE_SIZE 1\n#define AVR32_USBB_EP3INT_MASK 0x00008000\n#define AVR32_USBB_EP3INT_OFFSET 15\n#define AVR32_USBB_EP3INT_SIZE 1\n#define AVR32_USBB_EP4INT 16\n#define AVR32_USBB_EP4INTE 16\n#define AVR32_USBB_EP4INTEC 16\n#define AVR32_USBB_EP4INTEC_MASK 0x00010000\n#define AVR32_USBB_EP4INTEC_OFFSET 16\n#define AVR32_USBB_EP4INTEC_SIZE 1\n#define AVR32_USBB_EP4INTES 16\n#define AVR32_USBB_EP4INTES_MASK 0x00010000\n#define AVR32_USBB_EP4INTES_OFFSET 16\n#define AVR32_USBB_EP4INTES_SIZE 1\n#define AVR32_USBB_EP4INTE_MASK 0x00010000\n#define AVR32_USBB_EP4INTE_OFFSET 16\n#define AVR32_USBB_EP4INTE_SIZE 1\n#define AVR32_USBB_EP4INT_MASK 0x00010000\n#define AVR32_USBB_EP4INT_OFFSET 16\n#define AVR32_USBB_EP4INT_SIZE 1\n#define AVR32_USBB_EP5INT 17\n#define AVR32_USBB_EP5INTE 17\n#define AVR32_USBB_EP5INTEC 17\n#define AVR32_USBB_EP5INTEC_MASK 0x00020000\n#define AVR32_USBB_EP5INTEC_OFFSET 17\n#define AVR32_USBB_EP5INTEC_SIZE 1\n#define AVR32_USBB_EP5INTES 17\n#define AVR32_USBB_EP5INTES_MASK 0x00020000\n#define AVR32_USBB_EP5INTES_OFFSET 17\n#define AVR32_USBB_EP5INTES_SIZE 1\n#define AVR32_USBB_EP5INTE_MASK 0x00020000\n#define AVR32_USBB_EP5INTE_OFFSET 17\n#define AVR32_USBB_EP5INTE_SIZE 1\n#define AVR32_USBB_EP5INT_MASK 0x00020000\n#define AVR32_USBB_EP5INT_OFFSET 17\n#define AVR32_USBB_EP5INT_SIZE 1\n#define AVR32_USBB_EP6INT 18\n#define AVR32_USBB_EP6INTE 18\n#define AVR32_USBB_EP6INTEC 18\n#define AVR32_USBB_EP6INTEC_MASK 0x00040000\n#define AVR32_USBB_EP6INTEC_OFFSET 18\n#define AVR32_USBB_EP6INTEC_SIZE 1\n#define AVR32_USBB_EP6INTES 18\n#define AVR32_USBB_EP6INTES_MASK 0x00040000\n#define AVR32_USBB_EP6INTES_OFFSET 18\n#define AVR32_USBB_EP6INTES_SIZE 1\n#define AVR32_USBB_EP6INTE_MASK 0x00040000\n#define AVR32_USBB_EP6INTE_OFFSET 18\n#define AVR32_USBB_EP6INTE_SIZE 1\n#define AVR32_USBB_EP6INT_MASK 0x00040000\n#define AVR32_USBB_EP6INT_OFFSET 18\n#define AVR32_USBB_EP6INT_SIZE 1\n#define AVR32_USBB_EPBK 2\n#define AVR32_USBB_EPBK_DOUBLE 0x00000001\n#define AVR32_USBB_EPBK_MASK 0x0000000c\n#define AVR32_USBB_EPBK_OFFSET 2\n#define AVR32_USBB_EPBK_SINGLE 0x00000000\n#define AVR32_USBB_EPBK_SIZE 2\n#define AVR32_USBB_EPBK_TRIPLE 0x00000002\n#define AVR32_USBB_EPDIR 8\n#define AVR32_USBB_EPDIR_IN 0x00000001\n#define AVR32_USBB_EPDIR_MASK 0x00000100\n#define AVR32_USBB_EPDIR_OFFSET 8\n#define AVR32_USBB_EPDIR_OUT 0x00000000\n#define AVR32_USBB_EPDIR_SIZE 1\n#define AVR32_USBB_EPDISHDMA 16\n#define AVR32_USBB_EPDISHDMAC 16\n#define AVR32_USBB_EPDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_EPDISHDMAC_OFFSET 16\n#define AVR32_USBB_EPDISHDMAC_SIZE 1\n#define AVR32_USBB_EPDISHDMAS 16\n#define AVR32_USBB_EPDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_EPDISHDMAS_OFFSET 16\n#define AVR32_USBB_EPDISHDMAS_SIZE 1\n#define AVR32_USBB_EPDISHDMA_MASK 0x00010000\n#define AVR32_USBB_EPDISHDMA_OFFSET 16\n#define AVR32_USBB_EPDISHDMA_SIZE 1\n#define AVR32_USBB_EPEN0 0\n#define AVR32_USBB_EPEN0_MASK 0x00000001\n#define AVR32_USBB_EPEN0_OFFSET 0\n#define AVR32_USBB_EPEN0_SIZE 1\n#define AVR32_USBB_EPEN1 1\n#define AVR32_USBB_EPEN1_MASK 0x00000002\n#define AVR32_USBB_EPEN1_OFFSET 1\n#define AVR32_USBB_EPEN1_SIZE 1\n#define AVR32_USBB_EPEN2 2\n#define AVR32_USBB_EPEN2_MASK 0x00000004\n#define AVR32_USBB_EPEN2_OFFSET 2\n#define AVR32_USBB_EPEN2_SIZE 1\n#define AVR32_USBB_EPEN3 3\n#define AVR32_USBB_EPEN3_MASK 0x00000008\n#define AVR32_USBB_EPEN3_OFFSET 3\n#define AVR32_USBB_EPEN3_SIZE 1\n#define AVR32_USBB_EPEN4 4\n#define AVR32_USBB_EPEN4_MASK 0x00000010\n#define AVR32_USBB_EPEN4_OFFSET 4\n#define AVR32_USBB_EPEN4_SIZE 1\n#define AVR32_USBB_EPEN5 5\n#define AVR32_USBB_EPEN5_MASK 0x00000020\n#define AVR32_USBB_EPEN5_OFFSET 5\n#define AVR32_USBB_EPEN5_SIZE 1\n#define AVR32_USBB_EPEN6 6\n#define AVR32_USBB_EPEN6_MASK 0x00000040\n#define AVR32_USBB_EPEN6_OFFSET 6\n#define AVR32_USBB_EPEN6_SIZE 1\n#define AVR32_USBB_EPRST0 16\n#define AVR32_USBB_EPRST0_MASK 0x00010000\n#define AVR32_USBB_EPRST0_OFFSET 16\n#define AVR32_USBB_EPRST0_SIZE 1\n#define AVR32_USBB_EPRST1 17\n#define AVR32_USBB_EPRST1_MASK 0x00020000\n#define AVR32_USBB_EPRST1_OFFSET 17\n#define AVR32_USBB_EPRST1_SIZE 1\n#define AVR32_USBB_EPRST2 18\n#define AVR32_USBB_EPRST2_MASK 0x00040000\n#define AVR32_USBB_EPRST2_OFFSET 18\n#define AVR32_USBB_EPRST2_SIZE 1\n#define AVR32_USBB_EPRST3 19\n#define AVR32_USBB_EPRST3_MASK 0x00080000\n#define AVR32_USBB_EPRST3_OFFSET 19\n#define AVR32_USBB_EPRST3_SIZE 1\n#define AVR32_USBB_EPRST4 20\n#define AVR32_USBB_EPRST4_MASK 0x00100000\n#define AVR32_USBB_EPRST4_OFFSET 20\n#define AVR32_USBB_EPRST4_SIZE 1\n#define AVR32_USBB_EPRST5 21\n#define AVR32_USBB_EPRST5_MASK 0x00200000\n#define AVR32_USBB_EPRST5_OFFSET 21\n#define AVR32_USBB_EPRST5_SIZE 1\n#define AVR32_USBB_EPRST6 22\n#define AVR32_USBB_EPRST6_MASK 0x00400000\n#define AVR32_USBB_EPRST6_OFFSET 22\n#define AVR32_USBB_EPRST6_SIZE 1\n#define AVR32_USBB_EPSIZE 4\n#define AVR32_USBB_EPSIZE_1024 0x00000007\n#define AVR32_USBB_EPSIZE_128 0x00000004\n#define AVR32_USBB_EPSIZE_16 0x00000001\n#define AVR32_USBB_EPSIZE_256 0x00000005\n#define AVR32_USBB_EPSIZE_32 0x00000002\n#define AVR32_USBB_EPSIZE_512 0x00000006\n#define AVR32_USBB_EPSIZE_64 0x00000003\n#define AVR32_USBB_EPSIZE_8 0x00000000\n#define AVR32_USBB_EPSIZE_MASK 0x00000070\n#define AVR32_USBB_EPSIZE_OFFSET 4\n#define AVR32_USBB_EPSIZE_SIZE 3\n#define AVR32_USBB_EPTYPE 11\n#define AVR32_USBB_EPTYPE_BULK 0x00000002\n#define AVR32_USBB_EPTYPE_CONTROL 0x00000000\n#define AVR32_USBB_EPTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_EPTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_EPTYPE_MASK 0x00001800\n#define AVR32_USBB_EPTYPE_OFFSET 11\n#define AVR32_USBB_EPTYPE_SIZE 2\n#define AVR32_USBB_EPT_NBR_MAX 0\n#define AVR32_USBB_EPT_NBR_MAX_MASK 0x0000000f\n#define AVR32_USBB_EPT_NBR_MAX_OFFSET 0\n#define AVR32_USBB_EPT_NBR_MAX_SIZE 4\n#define AVR32_USBB_EP_DATA 0\n#define AVR32_USBB_EP_DATA_MASK 0xffffffff\n#define AVR32_USBB_EP_DATA_OFFSET 0\n#define AVR32_USBB_EP_DATA_SIZE 32\n#define AVR32_USBB_ERRORTRANS 10\n#define AVR32_USBB_ERRORTRANSE 10\n#define AVR32_USBB_ERRORTRANSEC 10\n#define AVR32_USBB_ERRORTRANSEC_MASK 0x00000400\n#define AVR32_USBB_ERRORTRANSEC_OFFSET 10\n#define AVR32_USBB_ERRORTRANSEC_SIZE 1\n#define AVR32_USBB_ERRORTRANSES 10\n#define AVR32_USBB_ERRORTRANSES_MASK 0x00000400\n#define AVR32_USBB_ERRORTRANSES_OFFSET 10\n#define AVR32_USBB_ERRORTRANSES_SIZE 1\n#define AVR32_USBB_ERRORTRANSE_MASK 0x00000400\n#define AVR32_USBB_ERRORTRANSE_OFFSET 10\n#define AVR32_USBB_ERRORTRANSE_SIZE 1\n#define AVR32_USBB_ERRORTRANSS 10\n#define AVR32_USBB_ERRORTRANSS_MASK 0x00000400\n#define AVR32_USBB_ERRORTRANSS_OFFSET 10\n#define AVR32_USBB_ERRORTRANSS_SIZE 1\n#define AVR32_USBB_ERRORTRANS_MASK 0x00000400\n#define AVR32_USBB_ERRORTRANS_OFFSET 10\n#define AVR32_USBB_ERRORTRANS_SIZE 1\n#define AVR32_USBB_FIFOCON 14\n#define AVR32_USBB_FIFOCONC 14\n#define AVR32_USBB_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_FIFOCONC_OFFSET 14\n#define AVR32_USBB_FIFOCONC_SIZE 1\n#define AVR32_USBB_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_FIFOCON_OFFSET 14\n#define AVR32_USBB_FIFOCON_SIZE 1\n#define AVR32_USBB_FIFO_MAX_SIZE 12\n#define AVR32_USBB_FIFO_MAX_SIZE_GE_16384 0x00000007\n#define AVR32_USBB_FIFO_MAX_SIZE_LT_1024 0x00000002\n#define AVR32_USBB_FIFO_MAX_SIZE_LT_16384 0x00000006\n#define AVR32_USBB_FIFO_MAX_SIZE_LT_2048 0x00000003\n#define AVR32_USBB_FIFO_MAX_SIZE_LT_256 0x00000000\n#define AVR32_USBB_FIFO_MAX_SIZE_LT_4096 0x00000004\n#define AVR32_USBB_FIFO_MAX_SIZE_LT_512 0x00000001\n#define AVR32_USBB_FIFO_MAX_SIZE_LT_8192 0x00000005\n#define AVR32_USBB_FIFO_MAX_SIZE_MASK 0x00007000\n#define AVR32_USBB_FIFO_MAX_SIZE_OFFSET 12\n#define AVR32_USBB_FIFO_MAX_SIZE_SIZE 3\n#define AVR32_USBB_FLENHIGH 16\n#define AVR32_USBB_FLENHIGH_MASK 0x00ff0000\n#define AVR32_USBB_FLENHIGH_OFFSET 16\n#define AVR32_USBB_FLENHIGH_SIZE 8\n#define AVR32_USBB_FNCERR 15\n#define AVR32_USBB_FNCERR_MASK 0x00008000\n#define AVR32_USBB_FNCERR_OFFSET 15\n#define AVR32_USBB_FNCERR_SIZE 1\n#define AVR32_USBB_FNUM 3\n#define AVR32_USBB_FNUM_MASK 0x00003ff8\n#define AVR32_USBB_FNUM_OFFSET 3\n#define AVR32_USBB_FNUM_SIZE 11\n#define AVR32_USBB_FORCEHSRESETTO50MS 7\n#define AVR32_USBB_FORCEHSRESETTO50MS_MASK 0x00000080\n#define AVR32_USBB_FORCEHSRESETTO50MS_OFFSET 7\n#define AVR32_USBB_FORCEHSRESETTO50MS_SIZE 1\n#define AVR32_USBB_FORCESUSPENDMTO1 4\n#define AVR32_USBB_FORCESUSPENDMTO1_MASK 0x00000010\n#define AVR32_USBB_FORCESUSPENDMTO1_OFFSET 4\n#define AVR32_USBB_FORCESUSPENDMTO1_SIZE 1\n#define AVR32_USBB_FRZCLK_SIZE 1\n#define AVR32_USBB_FULL 0x00000000\n#define AVR32_USBB_FULLDETACHEN 0\n#define AVR32_USBB_FULLDETACHEN_MASK 0x00000001\n#define AVR32_USBB_FULLDETACHEN_OFFSET 0\n#define AVR32_USBB_FULLDETACHEN_SIZE 1\n#define AVR32_USBB_GE_16384 0x00000007\n#define AVR32_USBB_HNPERRE 6\n#define AVR32_USBB_HNPERRE_MASK 0x00000040\n#define AVR32_USBB_HNPERRE_OFFSET 6\n#define AVR32_USBB_HNPERRE_SIZE 1\n#define AVR32_USBB_HNPERRI 6\n#define AVR32_USBB_HNPERRIC 6\n#define AVR32_USBB_HNPERRIC_MASK 0x00000040\n#define AVR32_USBB_HNPERRIC_OFFSET 6\n#define AVR32_USBB_HNPERRIC_SIZE 1\n#define AVR32_USBB_HNPERRIS 6\n#define AVR32_USBB_HNPERRIS_MASK 0x00000040\n#define AVR32_USBB_HNPERRIS_OFFSET 6\n#define AVR32_USBB_HNPERRIS_SIZE 1\n#define AVR32_USBB_HNPERRI_MASK 0x00000040\n#define AVR32_USBB_HNPERRI_OFFSET 6\n#define AVR32_USBB_HNPERRI_SIZE 1\n#define AVR32_USBB_HNPREQ 11\n#define AVR32_USBB_HNPREQ_MASK 0x00000800\n#define AVR32_USBB_HNPREQ_OFFSET 11\n#define AVR32_USBB_HNPREQ_SIZE 1\n#define AVR32_USBB_HOSTHSDISCONNECTDISABLE 6\n#define AVR32_USBB_HOSTHSDISCONNECTDISABLE_MASK 0x00000040\n#define AVR32_USBB_HOSTHSDISCONNECTDISABLE_OFFSET 6\n#define AVR32_USBB_HOSTHSDISCONNECTDISABLE_SIZE 1\n#define AVR32_USBB_HSB_ADDR 0\n#define AVR32_USBB_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_HSB_ADDR_SIZE 32\n#define AVR32_USBB_HSOFI 5\n#define AVR32_USBB_HSOFIC 5\n#define AVR32_USBB_HSOFIC_MASK 0x00000020\n#define AVR32_USBB_HSOFIC_OFFSET 5\n#define AVR32_USBB_HSOFIC_SIZE 1\n#define AVR32_USBB_HSOFIE 5\n#define AVR32_USBB_HSOFIEC 5\n#define AVR32_USBB_HSOFIEC_MASK 0x00000020\n#define AVR32_USBB_HSOFIEC_OFFSET 5\n#define AVR32_USBB_HSOFIEC_SIZE 1\n#define AVR32_USBB_HSOFIES 5\n#define AVR32_USBB_HSOFIES_MASK 0x00000020\n#define AVR32_USBB_HSOFIES_OFFSET 5\n#define AVR32_USBB_HSOFIES_SIZE 1\n#define AVR32_USBB_HSOFIE_MASK 0x00000020\n#define AVR32_USBB_HSOFIE_OFFSET 5\n#define AVR32_USBB_HSOFIE_SIZE 1\n#define AVR32_USBB_HSOFIS 5\n#define AVR32_USBB_HSOFIS_MASK 0x00000020\n#define AVR32_USBB_HSOFIS_OFFSET 5\n#define AVR32_USBB_HSOFIS_SIZE 1\n#define AVR32_USBB_HSOFI_MASK 0x00000020\n#define AVR32_USBB_HSOFI_OFFSET 5\n#define AVR32_USBB_HSOFI_SIZE 1\n#define AVR32_USBB_HSSERIALMODE 1\n#define AVR32_USBB_HSSERIALMODE_MASK 0x00000002\n#define AVR32_USBB_HSSERIALMODE_OFFSET 1\n#define AVR32_USBB_HSSERIALMODE_SIZE 1\n#define AVR32_USBB_HWUPI 6\n#define AVR32_USBB_HWUPIC 6\n#define AVR32_USBB_HWUPIC_MASK 0x00000040\n#define AVR32_USBB_HWUPIC_OFFSET 6\n#define AVR32_USBB_HWUPIC_SIZE 1\n#define AVR32_USBB_HWUPIE 6\n#define AVR32_USBB_HWUPIEC 6\n#define AVR32_USBB_HWUPIEC_MASK 0x00000040\n#define AVR32_USBB_HWUPIEC_OFFSET 6\n#define AVR32_USBB_HWUPIEC_SIZE 1\n#define AVR32_USBB_HWUPIES 6\n#define AVR32_USBB_HWUPIES_MASK 0x00000040\n#define AVR32_USBB_HWUPIES_OFFSET 6\n#define AVR32_USBB_HWUPIES_SIZE 1\n#define AVR32_USBB_HWUPIE_MASK 0x00000040\n#define AVR32_USBB_HWUPIE_OFFSET 6\n#define AVR32_USBB_HWUPIE_SIZE 1\n#define AVR32_USBB_HWUPIS 6\n#define AVR32_USBB_HWUPIS_MASK 0x00000040\n#define AVR32_USBB_HWUPIS_OFFSET 6\n#define AVR32_USBB_HWUPIS_SIZE 1\n#define AVR32_USBB_HWUPI_MASK 0x00000040\n#define AVR32_USBB_HWUPI_OFFSET 6\n#define AVR32_USBB_HWUPI_SIZE 1\n#define AVR32_USBB_ID 10\n#define AVR32_USBB_IDTE 0\n#define AVR32_USBB_IDTE_MASK 0x00000001\n#define AVR32_USBB_IDTE_OFFSET 0\n#define AVR32_USBB_IDTE_SIZE 1\n#define AVR32_USBB_IDTI 0\n#define AVR32_USBB_IDTIC 0\n#define AVR32_USBB_IDTIC_MASK 0x00000001\n#define AVR32_USBB_IDTIC_OFFSET 0\n#define AVR32_USBB_IDTIC_SIZE 1\n#define AVR32_USBB_IDTIS 0\n#define AVR32_USBB_IDTIS_MASK 0x00000001\n#define AVR32_USBB_IDTIS_OFFSET 0\n#define AVR32_USBB_IDTIS_SIZE 1\n#define AVR32_USBB_IDTI_MASK 0x00000001\n#define AVR32_USBB_IDTI_OFFSET 0\n#define AVR32_USBB_IDTI_SIZE 1\n#define AVR32_USBB_ID_MASK 0x00000400\n#define AVR32_USBB_ID_OFFSET 10\n#define AVR32_USBB_ID_SIZE 1\n#define AVR32_USBB_IN 0x00000001\n#define AVR32_USBB_INMODE 8\n#define AVR32_USBB_INMODE_MASK 0x00000100\n#define AVR32_USBB_INMODE_OFFSET 8\n#define AVR32_USBB_INMODE_SIZE 1\n#define AVR32_USBB_INRQ 0\n#define AVR32_USBB_INRQ_MASK 0x000000ff\n#define AVR32_USBB_INRQ_OFFSET 0\n#define AVR32_USBB_INRQ_SIZE 8\n#define AVR32_USBB_INTERRUPT 0x00000003\n#define AVR32_USBB_INTFRQ 24\n#define AVR32_USBB_INTFRQ_MASK 0xff000000\n#define AVR32_USBB_INTFRQ_OFFSET 24\n#define AVR32_USBB_INTFRQ_SIZE 8\n#define AVR32_USBB_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_KILLBK 13\n#define AVR32_USBB_KILLBKS 13\n#define AVR32_USBB_KILLBKS_MASK 0x00002000\n#define AVR32_USBB_KILLBKS_OFFSET 13\n#define AVR32_USBB_KILLBKS_SIZE 1\n#define AVR32_USBB_KILLBK_MASK 0x00002000\n#define AVR32_USBB_KILLBK_OFFSET 13\n#define AVR32_USBB_KILLBK_SIZE 1\n#define AVR32_USBB_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_LOADCNTA 15\n#define AVR32_USBB_LOADCNTA_MASK 0x00008000\n#define AVR32_USBB_LOADCNTA_OFFSET 15\n#define AVR32_USBB_LOADCNTA_SIZE 1\n#define AVR32_USBB_LOADCNTB 23\n#define AVR32_USBB_LOADCNTB_MASK 0x00800000\n#define AVR32_USBB_LOADCNTB_OFFSET 23\n#define AVR32_USBB_LOADCNTB_SIZE 1\n#define AVR32_USBB_LOADSOFCNT 31\n#define AVR32_USBB_LOADSOFCNT_MASK 0x80000000\n#define AVR32_USBB_LOADSOFCNT_OFFSET 31\n#define AVR32_USBB_LOADSOFCNT_SIZE 1\n#define AVR32_USBB_LOOPBACKMODE 2\n#define AVR32_USBB_LOOPBACKMODE_MASK 0x00000004\n#define AVR32_USBB_LOOPBACKMODE_OFFSET 2\n#define AVR32_USBB_LOOPBACKMODE_SIZE 1\n#define AVR32_USBB_LOW 0x00000002\n#define AVR32_USBB_LS 12\n#define AVR32_USBB_LS_MASK 0x00001000\n#define AVR32_USBB_LS_OFFSET 12\n#define AVR32_USBB_LS_SIZE 1\n#define AVR32_USBB_LT_1024 0x00000002\n#define AVR32_USBB_LT_16384 0x00000006\n#define AVR32_USBB_LT_2048 0x00000003\n#define AVR32_USBB_LT_256 0x00000000\n#define AVR32_USBB_LT_4096 0x00000004\n#define AVR32_USBB_LT_512 0x00000001\n#define AVR32_USBB_LT_8192 0x00000005\n#define AVR32_USBB_MDATAE 8\n#define AVR32_USBB_MDATAEC 8\n#define AVR32_USBB_MDATAEC_MASK 0x00000100\n#define AVR32_USBB_MDATAEC_OFFSET 8\n#define AVR32_USBB_MDATAEC_SIZE 1\n#define AVR32_USBB_MDATAES 8\n#define AVR32_USBB_MDATAES_MASK 0x00000100\n#define AVR32_USBB_MDATAES_OFFSET 8\n#define AVR32_USBB_MDATAES_SIZE 1\n#define AVR32_USBB_MDATAE_MASK 0x00000100\n#define AVR32_USBB_MDATAE_OFFSET 8\n#define AVR32_USBB_MDATAE_SIZE 1\n#define AVR32_USBB_METAL_FIX_NUM 16\n#define AVR32_USBB_METAL_FIX_NUM_MASK 0x00070000\n#define AVR32_USBB_METAL_FIX_NUM_OFFSET 16\n#define AVR32_USBB_METAL_FIX_NUM_SIZE 3\n#define AVR32_USBB_MFNUM 0\n#define AVR32_USBB_MFNUM_MASK 0x00000007\n#define AVR32_USBB_MFNUM_OFFSET 0\n#define AVR32_USBB_MFNUM_SIZE 3\n#define AVR32_USBB_MSOF 1\n#define AVR32_USBB_MSOFC 1\n#define AVR32_USBB_MSOFC_MASK 0x00000002\n#define AVR32_USBB_MSOFC_OFFSET 1\n#define AVR32_USBB_MSOFC_SIZE 1\n#define AVR32_USBB_MSOFE 1\n#define AVR32_USBB_MSOFEC 1\n#define AVR32_USBB_MSOFEC_MASK 0x00000002\n#define AVR32_USBB_MSOFEC_OFFSET 1\n#define AVR32_USBB_MSOFEC_SIZE 1\n#define AVR32_USBB_MSOFES 1\n#define AVR32_USBB_MSOFES_MASK 0x00000002\n#define AVR32_USBB_MSOFES_OFFSET 1\n#define AVR32_USBB_MSOFES_SIZE 1\n#define AVR32_USBB_MSOFE_MASK 0x00000002\n#define AVR32_USBB_MSOFE_OFFSET 1\n#define AVR32_USBB_MSOFE_SIZE 1\n#define AVR32_USBB_MSOFS 1\n#define AVR32_USBB_MSOFS_MASK 0x00000002\n#define AVR32_USBB_MSOFS_OFFSET 1\n#define AVR32_USBB_MSOFS_SIZE 1\n#define AVR32_USBB_MSOF_MASK 0x00000002\n#define AVR32_USBB_MSOF_OFFSET 1\n#define AVR32_USBB_MSOF_SIZE 1\n#define AVR32_USBB_NAKEDE 4\n#define AVR32_USBB_NAKEDEC 4\n#define AVR32_USBB_NAKEDEC_MASK 0x00000010\n#define AVR32_USBB_NAKEDEC_OFFSET 4\n#define AVR32_USBB_NAKEDEC_SIZE 1\n#define AVR32_USBB_NAKEDES 4\n#define AVR32_USBB_NAKEDES_MASK 0x00000010\n#define AVR32_USBB_NAKEDES_OFFSET 4\n#define AVR32_USBB_NAKEDES_SIZE 1\n#define AVR32_USBB_NAKEDE_MASK 0x00000010\n#define AVR32_USBB_NAKEDE_OFFSET 4\n#define AVR32_USBB_NAKEDE_SIZE 1\n#define AVR32_USBB_NAKEDI 4\n#define AVR32_USBB_NAKEDIC 4\n#define AVR32_USBB_NAKEDIC_MASK 0x00000010\n#define AVR32_USBB_NAKEDIC_OFFSET 4\n#define AVR32_USBB_NAKEDIC_SIZE 1\n#define AVR32_USBB_NAKEDIS 4\n#define AVR32_USBB_NAKEDIS_MASK 0x00000010\n#define AVR32_USBB_NAKEDIS_OFFSET 4\n#define AVR32_USBB_NAKEDIS_SIZE 1\n#define AVR32_USBB_NAKEDI_MASK 0x00000010\n#define AVR32_USBB_NAKEDI_OFFSET 4\n#define AVR32_USBB_NAKEDI_SIZE 1\n#define AVR32_USBB_NAKINE 4\n#define AVR32_USBB_NAKINEC 4\n#define AVR32_USBB_NAKINEC_MASK 0x00000010\n#define AVR32_USBB_NAKINEC_OFFSET 4\n#define AVR32_USBB_NAKINEC_SIZE 1\n#define AVR32_USBB_NAKINES 4\n#define AVR32_USBB_NAKINES_MASK 0x00000010\n#define AVR32_USBB_NAKINES_OFFSET 4\n#define AVR32_USBB_NAKINES_SIZE 1\n#define AVR32_USBB_NAKINE_MASK 0x00000010\n#define AVR32_USBB_NAKINE_OFFSET 4\n#define AVR32_USBB_NAKINE_SIZE 1\n#define AVR32_USBB_NAKINI 4\n#define AVR32_USBB_NAKINIC 4\n#define AVR32_USBB_NAKINIC_MASK 0x00000010\n#define AVR32_USBB_NAKINIC_OFFSET 4\n#define AVR32_USBB_NAKINIC_SIZE 1\n#define AVR32_USBB_NAKINIS 4\n#define AVR32_USBB_NAKINIS_MASK 0x00000010\n#define AVR32_USBB_NAKINIS_OFFSET 4\n#define AVR32_USBB_NAKINIS_SIZE 1\n#define AVR32_USBB_NAKINI_MASK 0x00000010\n#define AVR32_USBB_NAKINI_OFFSET 4\n#define AVR32_USBB_NAKINI_SIZE 1\n#define AVR32_USBB_NAKOUTE 3\n#define AVR32_USBB_NAKOUTEC 3\n#define AVR32_USBB_NAKOUTEC_MASK 0x00000008\n#define AVR32_USBB_NAKOUTEC_OFFSET 3\n#define AVR32_USBB_NAKOUTEC_SIZE 1\n#define AVR32_USBB_NAKOUTES 3\n#define AVR32_USBB_NAKOUTES_MASK 0x00000008\n#define AVR32_USBB_NAKOUTES_OFFSET 3\n#define AVR32_USBB_NAKOUTES_SIZE 1\n#define AVR32_USBB_NAKOUTE_MASK 0x00000008\n#define AVR32_USBB_NAKOUTE_OFFSET 3\n#define AVR32_USBB_NAKOUTE_SIZE 1\n#define AVR32_USBB_NAKOUTI 3\n#define AVR32_USBB_NAKOUTIC 3\n#define AVR32_USBB_NAKOUTIC_MASK 0x00000008\n#define AVR32_USBB_NAKOUTIC_OFFSET 3\n#define AVR32_USBB_NAKOUTIC_SIZE 1\n#define AVR32_USBB_NAKOUTIS 3\n#define AVR32_USBB_NAKOUTIS_MASK 0x00000008\n#define AVR32_USBB_NAKOUTIS_OFFSET 3\n#define AVR32_USBB_NAKOUTIS_SIZE 1\n#define AVR32_USBB_NAKOUTI_MASK 0x00000008\n#define AVR32_USBB_NAKOUTI_OFFSET 3\n#define AVR32_USBB_NAKOUTI_SIZE 1\n#define AVR32_USBB_NBTRANS 13\n#define AVR32_USBB_NBTRANS_MASK 0x00006000\n#define AVR32_USBB_NBTRANS_OFFSET 13\n#define AVR32_USBB_NBTRANS_SIZE 2\n#define AVR32_USBB_NBUSYBK 12\n#define AVR32_USBB_NBUSYBKE 12\n#define AVR32_USBB_NBUSYBKEC 12\n#define AVR32_USBB_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_NBUSYBKES 12\n#define AVR32_USBB_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_NBUSYBKES_SIZE 1\n#define AVR32_USBB_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_NBUSYBKE_SIZE 1\n#define AVR32_USBB_NBUSYBKS 12\n#define AVR32_USBB_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_NBUSYBKS_SIZE 1\n#define AVR32_USBB_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_NBUSYBK_OFFSET 12\n#define AVR32_USBB_NBUSYBK_SIZE 2\n#define AVR32_USBB_NOTHOSTDISCONNECT 6\n#define AVR32_USBB_NOTHOSTDISCONNECT_MASK 0x00000040\n#define AVR32_USBB_NOTHOSTDISCONNECT_OFFSET 6\n#define AVR32_USBB_NOTHOSTDISCONNECT_SIZE 1\n#define AVR32_USBB_NXT_DESC_ADDR 4\n#define AVR32_USBB_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_NYETDIS 17\n#define AVR32_USBB_NYETDISC 17\n#define AVR32_USBB_NYETDISC_MASK 0x00020000\n#define AVR32_USBB_NYETDISC_OFFSET 17\n#define AVR32_USBB_NYETDISC_SIZE 1\n#define AVR32_USBB_NYETDISS 17\n#define AVR32_USBB_NYETDISS_MASK 0x00020000\n#define AVR32_USBB_NYETDISS_OFFSET 17\n#define AVR32_USBB_NYETDISS_SIZE 1\n#define AVR32_USBB_NYETDIS_MASK 0x00020000\n#define AVR32_USBB_NYETDIS_OFFSET 17\n#define AVR32_USBB_NYETDIS_SIZE 1\n#define AVR32_USBB_OPMODE2 16\n#define AVR32_USBB_OPMODE2_MASK 0x00010000\n#define AVR32_USBB_OPMODE2_OFFSET 16\n#define AVR32_USBB_OPMODE2_SIZE 1\n#define AVR32_USBB_OTGPADE 12\n#define AVR32_USBB_OTGPADE_MASK 0x00001000\n#define AVR32_USBB_OTGPADE_OFFSET 12\n#define AVR32_USBB_OTGPADE_SIZE 1\n#define AVR32_USBB_OVERFE 5\n#define AVR32_USBB_OVERFEC 5\n#define AVR32_USBB_OVERFEC_MASK 0x00000020\n#define AVR32_USBB_OVERFEC_OFFSET 5\n#define AVR32_USBB_OVERFEC_SIZE 1\n#define AVR32_USBB_OVERFES 5\n#define AVR32_USBB_OVERFES_MASK 0x00000020\n#define AVR32_USBB_OVERFES_OFFSET 5\n#define AVR32_USBB_OVERFES_SIZE 1\n#define AVR32_USBB_OVERFE_MASK 0x00000020\n#define AVR32_USBB_OVERFE_OFFSET 5\n#define AVR32_USBB_OVERFE_SIZE 1\n#define AVR32_USBB_OVERFI 5\n#define AVR32_USBB_OVERFIC 5\n#define AVR32_USBB_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_OVERFIC_OFFSET 5\n#define AVR32_USBB_OVERFIC_SIZE 1\n#define AVR32_USBB_OVERFIE 5\n#define AVR32_USBB_OVERFIEC 5\n#define AVR32_USBB_OVERFIEC_MASK 0x00000020\n#define AVR32_USBB_OVERFIEC_OFFSET 5\n#define AVR32_USBB_OVERFIEC_SIZE 1\n#define AVR32_USBB_OVERFIES 5\n#define AVR32_USBB_OVERFIES_MASK 0x00000020\n#define AVR32_USBB_OVERFIES_OFFSET 5\n#define AVR32_USBB_OVERFIES_SIZE 1\n#define AVR32_USBB_OVERFIE_MASK 0x00000020\n#define AVR32_USBB_OVERFIE_OFFSET 5\n#define AVR32_USBB_OVERFIE_SIZE 1\n#define AVR32_USBB_OVERFIS 5\n#define AVR32_USBB_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_OVERFIS_OFFSET 5\n#define AVR32_USBB_OVERFIS_SIZE 1\n#define AVR32_USBB_OVERFI_MASK 0x00000020\n#define AVR32_USBB_OVERFI_OFFSET 5\n#define AVR32_USBB_OVERFI_SIZE 1\n#define AVR32_USBB_P0INT 8\n#define AVR32_USBB_P0INTE 8\n#define AVR32_USBB_P0INTEC 8\n#define AVR32_USBB_P0INTEC_MASK 0x00000100\n#define AVR32_USBB_P0INTEC_OFFSET 8\n#define AVR32_USBB_P0INTEC_SIZE 1\n#define AVR32_USBB_P0INTES 8\n#define AVR32_USBB_P0INTES_MASK 0x00000100\n#define AVR32_USBB_P0INTES_OFFSET 8\n#define AVR32_USBB_P0INTES_SIZE 1\n#define AVR32_USBB_P0INTE_MASK 0x00000100\n#define AVR32_USBB_P0INTE_OFFSET 8\n#define AVR32_USBB_P0INTE_SIZE 1\n#define AVR32_USBB_P0INT_MASK 0x00000100\n#define AVR32_USBB_P0INT_OFFSET 8\n#define AVR32_USBB_P0INT_SIZE 1\n#define AVR32_USBB_P1INT 9\n#define AVR32_USBB_P1INTE 9\n#define AVR32_USBB_P1INTEC 9\n#define AVR32_USBB_P1INTEC_MASK 0x00000200\n#define AVR32_USBB_P1INTEC_OFFSET 9\n#define AVR32_USBB_P1INTEC_SIZE 1\n#define AVR32_USBB_P1INTES 9\n#define AVR32_USBB_P1INTES_MASK 0x00000200\n#define AVR32_USBB_P1INTES_OFFSET 9\n#define AVR32_USBB_P1INTES_SIZE 1\n#define AVR32_USBB_P1INTE_MASK 0x00000200\n#define AVR32_USBB_P1INTE_OFFSET 9\n#define AVR32_USBB_P1INTE_SIZE 1\n#define AVR32_USBB_P1INT_MASK 0x00000200\n#define AVR32_USBB_P1INT_OFFSET 9\n#define AVR32_USBB_P1INT_SIZE 1\n#define AVR32_USBB_P2INT 10\n#define AVR32_USBB_P2INTE 10\n#define AVR32_USBB_P2INTEC 10\n#define AVR32_USBB_P2INTEC_MASK 0x00000400\n#define AVR32_USBB_P2INTEC_OFFSET 10\n#define AVR32_USBB_P2INTEC_SIZE 1\n#define AVR32_USBB_P2INTES 10\n#define AVR32_USBB_P2INTES_MASK 0x00000400\n#define AVR32_USBB_P2INTES_OFFSET 10\n#define AVR32_USBB_P2INTES_SIZE 1\n#define AVR32_USBB_P2INTE_MASK 0x00000400\n#define AVR32_USBB_P2INTE_OFFSET 10\n#define AVR32_USBB_P2INTE_SIZE 1\n#define AVR32_USBB_P2INT_MASK 0x00000400\n#define AVR32_USBB_P2INT_OFFSET 10\n#define AVR32_USBB_P2INT_SIZE 1\n#define AVR32_USBB_P3INT 11\n#define AVR32_USBB_P3INTE 11\n#define AVR32_USBB_P3INTEC 11\n#define AVR32_USBB_P3INTEC_MASK 0x00000800\n#define AVR32_USBB_P3INTEC_OFFSET 11\n#define AVR32_USBB_P3INTEC_SIZE 1\n#define AVR32_USBB_P3INTES 11\n#define AVR32_USBB_P3INTES_MASK 0x00000800\n#define AVR32_USBB_P3INTES_OFFSET 11\n#define AVR32_USBB_P3INTES_SIZE 1\n#define AVR32_USBB_P3INTE_MASK 0x00000800\n#define AVR32_USBB_P3INTE_OFFSET 11\n#define AVR32_USBB_P3INTE_SIZE 1\n#define AVR32_USBB_P3INT_MASK 0x00000800\n#define AVR32_USBB_P3INT_OFFSET 11\n#define AVR32_USBB_P3INT_SIZE 1\n#define AVR32_USBB_P4INT 12\n#define AVR32_USBB_P4INTE 12\n#define AVR32_USBB_P4INTEC 12\n#define AVR32_USBB_P4INTEC_MASK 0x00001000\n#define AVR32_USBB_P4INTEC_OFFSET 12\n#define AVR32_USBB_P4INTEC_SIZE 1\n#define AVR32_USBB_P4INTES 12\n#define AVR32_USBB_P4INTES_MASK 0x00001000\n#define AVR32_USBB_P4INTES_OFFSET 12\n#define AVR32_USBB_P4INTES_SIZE 1\n#define AVR32_USBB_P4INTE_MASK 0x00001000\n#define AVR32_USBB_P4INTE_OFFSET 12\n#define AVR32_USBB_P4INTE_SIZE 1\n#define AVR32_USBB_P4INT_MASK 0x00001000\n#define AVR32_USBB_P4INT_OFFSET 12\n#define AVR32_USBB_P4INT_SIZE 1\n#define AVR32_USBB_P5INT 13\n#define AVR32_USBB_P5INTE 13\n#define AVR32_USBB_P5INTEC 13\n#define AVR32_USBB_P5INTEC_MASK 0x00002000\n#define AVR32_USBB_P5INTEC_OFFSET 13\n#define AVR32_USBB_P5INTEC_SIZE 1\n#define AVR32_USBB_P5INTES 13\n#define AVR32_USBB_P5INTES_MASK 0x00002000\n#define AVR32_USBB_P5INTES_OFFSET 13\n#define AVR32_USBB_P5INTES_SIZE 1\n#define AVR32_USBB_P5INTE_MASK 0x00002000\n#define AVR32_USBB_P5INTE_OFFSET 13\n#define AVR32_USBB_P5INTE_SIZE 1\n#define AVR32_USBB_P5INT_MASK 0x00002000\n#define AVR32_USBB_P5INT_OFFSET 13\n#define AVR32_USBB_P5INT_SIZE 1\n#define AVR32_USBB_P6INT 14\n#define AVR32_USBB_P6INTE 14\n#define AVR32_USBB_P6INTEC 14\n#define AVR32_USBB_P6INTEC_MASK 0x00004000\n#define AVR32_USBB_P6INTEC_OFFSET 14\n#define AVR32_USBB_P6INTEC_SIZE 1\n#define AVR32_USBB_P6INTES 14\n#define AVR32_USBB_P6INTES_MASK 0x00004000\n#define AVR32_USBB_P6INTES_OFFSET 14\n#define AVR32_USBB_P6INTES_SIZE 1\n#define AVR32_USBB_P6INTE_MASK 0x00004000\n#define AVR32_USBB_P6INTE_OFFSET 14\n#define AVR32_USBB_P6INTE_SIZE 1\n#define AVR32_USBB_P6INT_MASK 0x00004000\n#define AVR32_USBB_P6INT_OFFSET 14\n#define AVR32_USBB_P6INT_SIZE 1\n#define AVR32_USBB_PBK 2\n#define AVR32_USBB_PBK_DOUBLE 0x00000001\n#define AVR32_USBB_PBK_MASK 0x0000000c\n#define AVR32_USBB_PBK_OFFSET 2\n#define AVR32_USBB_PBK_SINGLE 0x00000000\n#define AVR32_USBB_PBK_SIZE 2\n#define AVR32_USBB_PBK_TRIPLE 0x00000002\n#define AVR32_USBB_PBYCT 20\n#define AVR32_USBB_PBYCT_MASK 0x7ff00000\n#define AVR32_USBB_PBYCT_OFFSET 20\n#define AVR32_USBB_PBYCT_SIZE 11\n#define AVR32_USBB_PDISHDMA 16\n#define AVR32_USBB_PDISHDMAC 16\n#define AVR32_USBB_PDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_PDISHDMAC_OFFSET 16\n#define AVR32_USBB_PDISHDMAC_SIZE 1\n#define AVR32_USBB_PDISHDMAS 16\n#define AVR32_USBB_PDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_PDISHDMAS_OFFSET 16\n#define AVR32_USBB_PDISHDMAS_SIZE 1\n#define AVR32_USBB_PDISHDMA_MASK 0x00010000\n#define AVR32_USBB_PDISHDMA_OFFSET 16\n#define AVR32_USBB_PDISHDMA_SIZE 1\n#define AVR32_USBB_PD_TMOUT_CNT 0x00000002\n#define AVR32_USBB_PD_TMOUT_CNT_105_MS 0x00000001\n#define AVR32_USBB_PD_TMOUT_CNT_118_MS 0x00000002\n#define AVR32_USBB_PD_TMOUT_CNT_131_MS 0x00000003\n#define AVR32_USBB_PD_TMOUT_CNT_93_MS 0x00000000\n#define AVR32_USBB_PEN0 0\n#define AVR32_USBB_PEN0_MASK 0x00000001\n#define AVR32_USBB_PEN0_OFFSET 0\n#define AVR32_USBB_PEN0_SIZE 1\n#define AVR32_USBB_PEN1 1\n#define AVR32_USBB_PEN1_MASK 0x00000002\n#define AVR32_USBB_PEN1_OFFSET 1\n#define AVR32_USBB_PEN1_SIZE 1\n#define AVR32_USBB_PEN2 2\n#define AVR32_USBB_PEN2_MASK 0x00000004\n#define AVR32_USBB_PEN2_OFFSET 2\n#define AVR32_USBB_PEN2_SIZE 1\n#define AVR32_USBB_PEN3 3\n#define AVR32_USBB_PEN3_MASK 0x00000008\n#define AVR32_USBB_PEN3_OFFSET 3\n#define AVR32_USBB_PEN3_SIZE 1\n#define AVR32_USBB_PEN4 4\n#define AVR32_USBB_PEN4_MASK 0x00000010\n#define AVR32_USBB_PEN4_OFFSET 4\n#define AVR32_USBB_PEN4_SIZE 1\n#define AVR32_USBB_PEN5 5\n#define AVR32_USBB_PEN5_MASK 0x00000020\n#define AVR32_USBB_PEN5_OFFSET 5\n#define AVR32_USBB_PEN5_SIZE 1\n#define AVR32_USBB_PEN6 6\n#define AVR32_USBB_PEN6_MASK 0x00000040\n#define AVR32_USBB_PEN6_OFFSET 6\n#define AVR32_USBB_PEN6_SIZE 1\n#define AVR32_USBB_PEPNUM 16\n#define AVR32_USBB_PEPNUM_MASK 0x000f0000\n#define AVR32_USBB_PEPNUM_OFFSET 16\n#define AVR32_USBB_PEPNUM_SIZE 4\n#define AVR32_USBB_PERRE 3\n#define AVR32_USBB_PERREC 3\n#define AVR32_USBB_PERREC_MASK 0x00000008\n#define AVR32_USBB_PERREC_OFFSET 3\n#define AVR32_USBB_PERREC_SIZE 1\n#define AVR32_USBB_PERRES 3\n#define AVR32_USBB_PERRES_MASK 0x00000008\n#define AVR32_USBB_PERRES_OFFSET 3\n#define AVR32_USBB_PERRES_SIZE 1\n#define AVR32_USBB_PERRE_MASK 0x00000008\n#define AVR32_USBB_PERRE_OFFSET 3\n#define AVR32_USBB_PERRE_SIZE 1\n#define AVR32_USBB_PERRI 3\n#define AVR32_USBB_PERRIS 3\n#define AVR32_USBB_PERRIS_MASK 0x00000008\n#define AVR32_USBB_PERRIS_OFFSET 3\n#define AVR32_USBB_PERRIS_SIZE 1\n#define AVR32_USBB_PERRI_MASK 0x00000008\n#define AVR32_USBB_PERRI_OFFSET 3\n#define AVR32_USBB_PERRI_SIZE 1\n#define AVR32_USBB_PFREEZE 17\n#define AVR32_USBB_PFREEZEC 17\n#define AVR32_USBB_PFREEZEC_MASK 0x00020000\n#define AVR32_USBB_PFREEZEC_OFFSET 17\n#define AVR32_USBB_PFREEZEC_SIZE 1\n#define AVR32_USBB_PFREEZES 17\n#define AVR32_USBB_PFREEZES_MASK 0x00020000\n#define AVR32_USBB_PFREEZES_OFFSET 17\n#define AVR32_USBB_PFREEZES_SIZE 1\n#define AVR32_USBB_PFREEZE_MASK 0x00020000\n#define AVR32_USBB_PFREEZE_OFFSET 17\n#define AVR32_USBB_PFREEZE_SIZE 1\n#define AVR32_USBB_PID 2\n#define AVR32_USBB_PID_MASK 0x00000004\n#define AVR32_USBB_PID_OFFSET 2\n#define AVR32_USBB_PID_SIZE 1\n#define AVR32_USBB_PINGEN 20\n#define AVR32_USBB_PINGEN_MASK 0x00100000\n#define AVR32_USBB_PINGEN_OFFSET 20\n#define AVR32_USBB_PINGEN_SIZE 1\n#define AVR32_USBB_PRST0 16\n#define AVR32_USBB_PRST0_MASK 0x00010000\n#define AVR32_USBB_PRST0_OFFSET 16\n#define AVR32_USBB_PRST0_SIZE 1\n#define AVR32_USBB_PRST1 17\n#define AVR32_USBB_PRST1_MASK 0x00020000\n#define AVR32_USBB_PRST1_OFFSET 17\n#define AVR32_USBB_PRST1_SIZE 1\n#define AVR32_USBB_PRST2 18\n#define AVR32_USBB_PRST2_MASK 0x00040000\n#define AVR32_USBB_PRST2_OFFSET 18\n#define AVR32_USBB_PRST2_SIZE 1\n#define AVR32_USBB_PRST3 19\n#define AVR32_USBB_PRST3_MASK 0x00080000\n#define AVR32_USBB_PRST3_OFFSET 19\n#define AVR32_USBB_PRST3_SIZE 1\n#define AVR32_USBB_PRST4 20\n#define AVR32_USBB_PRST4_MASK 0x00100000\n#define AVR32_USBB_PRST4_OFFSET 20\n#define AVR32_USBB_PRST4_SIZE 1\n#define AVR32_USBB_PRST5 21\n#define AVR32_USBB_PRST5_MASK 0x00200000\n#define AVR32_USBB_PRST5_OFFSET 21\n#define AVR32_USBB_PRST5_SIZE 1\n#define AVR32_USBB_PRST6 22\n#define AVR32_USBB_PRST6_MASK 0x00400000\n#define AVR32_USBB_PRST6_OFFSET 22\n#define AVR32_USBB_PRST6_SIZE 1\n#define AVR32_USBB_PSIZE 4\n#define AVR32_USBB_PSIZE_1024 0x00000007\n#define AVR32_USBB_PSIZE_128 0x00000004\n#define AVR32_USBB_PSIZE_16 0x00000001\n#define AVR32_USBB_PSIZE_256 0x00000005\n#define AVR32_USBB_PSIZE_32 0x00000002\n#define AVR32_USBB_PSIZE_512 0x00000006\n#define AVR32_USBB_PSIZE_64 0x00000003\n#define AVR32_USBB_PSIZE_8 0x00000000\n#define AVR32_USBB_PSIZE_MASK 0x00000070\n#define AVR32_USBB_PSIZE_OFFSET 4\n#define AVR32_USBB_PSIZE_SIZE 3\n#define AVR32_USBB_PTOKEN 8\n#define AVR32_USBB_PTOKEN_IN 0x00000001\n#define AVR32_USBB_PTOKEN_MASK 0x00000300\n#define AVR32_USBB_PTOKEN_OFFSET 8\n#define AVR32_USBB_PTOKEN_OUT 0x00000002\n#define AVR32_USBB_PTOKEN_SETUP 0x00000000\n#define AVR32_USBB_PTOKEN_SIZE 2\n#define AVR32_USBB_PTYPE 12\n#define AVR32_USBB_PTYPE_BULK 0x00000002\n#define AVR32_USBB_PTYPE_CONTROL 0x00000000\n#define AVR32_USBB_PTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_PTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_PTYPE_MASK 0x00003000\n#define AVR32_USBB_PTYPE_OFFSET 12\n#define AVR32_USBB_PTYPE_SIZE 2\n#define AVR32_USBB_P_DATA 0\n#define AVR32_USBB_P_DATA_MASK 0xffffffff\n#define AVR32_USBB_P_DATA_OFFSET 0\n#define AVR32_USBB_P_DATA_SIZE 32\n#define AVR32_USBB_RESET 9\n#define AVR32_USBB_RESET_MASK 0x00000200\n#define AVR32_USBB_RESET_OFFSET 9\n#define AVR32_USBB_RESET_SIZE 1\n#define AVR32_USBB_RESUME 10\n#define AVR32_USBB_RESUME_MASK 0x00000400\n#define AVR32_USBB_RESUME_OFFSET 10\n#define AVR32_USBB_RESUME_SIZE 1\n#define AVR32_USBB_RMWKUP 9\n#define AVR32_USBB_RMWKUP_MASK 0x00000200\n#define AVR32_USBB_RMWKUP_OFFSET 9\n#define AVR32_USBB_RMWKUP_SIZE 1\n#define AVR32_USBB_ROLEEXE 5\n#define AVR32_USBB_ROLEEXE_MASK 0x00000020\n#define AVR32_USBB_ROLEEXE_OFFSET 5\n#define AVR32_USBB_ROLEEXE_SIZE 1\n#define AVR32_USBB_ROLEEXI 5\n#define AVR32_USBB_ROLEEXIC 5\n#define AVR32_USBB_ROLEEXIC_MASK 0x00000020\n#define AVR32_USBB_ROLEEXIC_OFFSET 5\n#define AVR32_USBB_ROLEEXIC_SIZE 1\n#define AVR32_USBB_ROLEEXIS 5\n#define AVR32_USBB_ROLEEXIS_MASK 0x00000020\n#define AVR32_USBB_ROLEEXIS_OFFSET 5\n#define AVR32_USBB_ROLEEXIS_SIZE 1\n#define AVR32_USBB_ROLEEXI_MASK 0x00000020\n#define AVR32_USBB_ROLEEXI_OFFSET 5\n#define AVR32_USBB_ROLEEXI_SIZE 1\n#define AVR32_USBB_RSMEDI 3\n#define AVR32_USBB_RSMEDIC 3\n#define AVR32_USBB_RSMEDIC_MASK 0x00000008\n#define AVR32_USBB_RSMEDIC_OFFSET 3\n#define AVR32_USBB_RSMEDIC_SIZE 1\n#define AVR32_USBB_RSMEDIE 3\n#define AVR32_USBB_RSMEDIEC 3\n#define AVR32_USBB_RSMEDIEC_MASK 0x00000008\n#define AVR32_USBB_RSMEDIEC_OFFSET 3\n#define AVR32_USBB_RSMEDIEC_SIZE 1\n#define AVR32_USBB_RSMEDIES 3\n#define AVR32_USBB_RSMEDIES_MASK 0x00000008\n#define AVR32_USBB_RSMEDIES_OFFSET 3\n#define AVR32_USBB_RSMEDIES_SIZE 1\n#define AVR32_USBB_RSMEDIE_MASK 0x00000008\n#define AVR32_USBB_RSMEDIE_OFFSET 3\n#define AVR32_USBB_RSMEDIE_SIZE 1\n#define AVR32_USBB_RSMEDIS 3\n#define AVR32_USBB_RSMEDIS_MASK 0x00000008\n#define AVR32_USBB_RSMEDIS_OFFSET 3\n#define AVR32_USBB_RSMEDIS_SIZE 1\n#define AVR32_USBB_RSMEDI_MASK 0x00000008\n#define AVR32_USBB_RSMEDI_OFFSET 3\n#define AVR32_USBB_RSMEDI_SIZE 1\n#define AVR32_USBB_RSTDT 18\n#define AVR32_USBB_RSTDTS 18\n#define AVR32_USBB_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_RSTDTS_OFFSET 18\n#define AVR32_USBB_RSTDTS_SIZE 1\n#define AVR32_USBB_RSTDT_MASK 0x00040000\n#define AVR32_USBB_RSTDT_OFFSET 18\n#define AVR32_USBB_RSTDT_SIZE 1\n#define AVR32_USBB_RSTI 2\n#define AVR32_USBB_RSTIC 2\n#define AVR32_USBB_RSTIC_MASK 0x00000004\n#define AVR32_USBB_RSTIC_OFFSET 2\n#define AVR32_USBB_RSTIC_SIZE 1\n#define AVR32_USBB_RSTIE 2\n#define AVR32_USBB_RSTIEC 2\n#define AVR32_USBB_RSTIEC_MASK 0x00000004\n#define AVR32_USBB_RSTIEC_OFFSET 2\n#define AVR32_USBB_RSTIEC_SIZE 1\n#define AVR32_USBB_RSTIES 2\n#define AVR32_USBB_RSTIES_MASK 0x00000004\n#define AVR32_USBB_RSTIES_OFFSET 2\n#define AVR32_USBB_RSTIES_SIZE 1\n#define AVR32_USBB_RSTIE_MASK 0x00000004\n#define AVR32_USBB_RSTIE_OFFSET 2\n#define AVR32_USBB_RSTIE_SIZE 1\n#define AVR32_USBB_RSTIS 2\n#define AVR32_USBB_RSTIS_MASK 0x00000004\n#define AVR32_USBB_RSTIS_OFFSET 2\n#define AVR32_USBB_RSTIS_SIZE 1\n#define AVR32_USBB_RSTI_MASK 0x00000004\n#define AVR32_USBB_RSTI_OFFSET 2\n#define AVR32_USBB_RSTI_SIZE 1\n#define AVR32_USBB_RWALL 16\n#define AVR32_USBB_RWALL_MASK 0x00010000\n#define AVR32_USBB_RWALL_OFFSET 16\n#define AVR32_USBB_RWALL_SIZE 1\n#define AVR32_USBB_RXINE 0\n#define AVR32_USBB_RXINEC 0\n#define AVR32_USBB_RXINEC_MASK 0x00000001\n#define AVR32_USBB_RXINEC_OFFSET 0\n#define AVR32_USBB_RXINEC_SIZE 1\n#define AVR32_USBB_RXINES 0\n#define AVR32_USBB_RXINES_MASK 0x00000001\n#define AVR32_USBB_RXINES_OFFSET 0\n#define AVR32_USBB_RXINES_SIZE 1\n#define AVR32_USBB_RXINE_MASK 0x00000001\n#define AVR32_USBB_RXINE_OFFSET 0\n#define AVR32_USBB_RXINE_SIZE 1\n#define AVR32_USBB_RXINI 0\n#define AVR32_USBB_RXINIC 0\n#define AVR32_USBB_RXINIC_MASK 0x00000001\n#define AVR32_USBB_RXINIC_OFFSET 0\n#define AVR32_USBB_RXINIC_SIZE 1\n#define AVR32_USBB_RXINIS 0\n#define AVR32_USBB_RXINIS_MASK 0x00000001\n#define AVR32_USBB_RXINIS_OFFSET 0\n#define AVR32_USBB_RXINIS_SIZE 1\n#define AVR32_USBB_RXINI_MASK 0x00000001\n#define AVR32_USBB_RXINI_OFFSET 0\n#define AVR32_USBB_RXINI_SIZE 1\n#define AVR32_USBB_RXOUTE 1\n#define AVR32_USBB_RXOUTEC 1\n#define AVR32_USBB_RXOUTEC_MASK 0x00000002\n#define AVR32_USBB_RXOUTEC_OFFSET 1\n#define AVR32_USBB_RXOUTEC_SIZE 1\n#define AVR32_USBB_RXOUTES 1\n#define AVR32_USBB_RXOUTES_MASK 0x00000002\n#define AVR32_USBB_RXOUTES_OFFSET 1\n#define AVR32_USBB_RXOUTES_SIZE 1\n#define AVR32_USBB_RXOUTE_MASK 0x00000002\n#define AVR32_USBB_RXOUTE_OFFSET 1\n#define AVR32_USBB_RXOUTE_SIZE 1\n#define AVR32_USBB_RXOUTI 1\n#define AVR32_USBB_RXOUTIC 1\n#define AVR32_USBB_RXOUTIC_MASK 0x00000002\n#define AVR32_USBB_RXOUTIC_OFFSET 1\n#define AVR32_USBB_RXOUTIC_SIZE 1\n#define AVR32_USBB_RXOUTIS 1\n#define AVR32_USBB_RXOUTIS_MASK 0x00000002\n#define AVR32_USBB_RXOUTIS_OFFSET 1\n#define AVR32_USBB_RXOUTIS_SIZE 1\n#define AVR32_USBB_RXOUTI_MASK 0x00000002\n#define AVR32_USBB_RXOUTI_OFFSET 1\n#define AVR32_USBB_RXOUTI_SIZE 1\n#define AVR32_USBB_RXRSMI 4\n#define AVR32_USBB_RXRSMIC 4\n#define AVR32_USBB_RXRSMIC_MASK 0x00000010\n#define AVR32_USBB_RXRSMIC_OFFSET 4\n#define AVR32_USBB_RXRSMIC_SIZE 1\n#define AVR32_USBB_RXRSMIE 4\n#define AVR32_USBB_RXRSMIEC 4\n#define AVR32_USBB_RXRSMIEC_MASK 0x00000010\n#define AVR32_USBB_RXRSMIEC_OFFSET 4\n#define AVR32_USBB_RXRSMIEC_SIZE 1\n#define AVR32_USBB_RXRSMIES 4\n#define AVR32_USBB_RXRSMIES_MASK 0x00000010\n#define AVR32_USBB_RXRSMIES_OFFSET 4\n#define AVR32_USBB_RXRSMIES_SIZE 1\n#define AVR32_USBB_RXRSMIE_MASK 0x00000010\n#define AVR32_USBB_RXRSMIE_OFFSET 4\n#define AVR32_USBB_RXRSMIE_SIZE 1\n#define AVR32_USBB_RXRSMIS 4\n#define AVR32_USBB_RXRSMIS_MASK 0x00000010\n#define AVR32_USBB_RXRSMIS_OFFSET 4\n#define AVR32_USBB_RXRSMIS_SIZE 1\n#define AVR32_USBB_RXRSMI_MASK 0x00000010\n#define AVR32_USBB_RXRSMI_OFFSET 4\n#define AVR32_USBB_RXRSMI_SIZE 1\n#define AVR32_USBB_RXSTALLDE 6\n#define AVR32_USBB_RXSTALLDEC 6\n#define AVR32_USBB_RXSTALLDEC_MASK 0x00000040\n#define AVR32_USBB_RXSTALLDEC_OFFSET 6\n#define AVR32_USBB_RXSTALLDEC_SIZE 1\n#define AVR32_USBB_RXSTALLDES 6\n#define AVR32_USBB_RXSTALLDES_MASK 0x00000040\n#define AVR32_USBB_RXSTALLDES_OFFSET 6\n#define AVR32_USBB_RXSTALLDES_SIZE 1\n#define AVR32_USBB_RXSTALLDE_MASK 0x00000040\n#define AVR32_USBB_RXSTALLDE_OFFSET 6\n#define AVR32_USBB_RXSTALLDE_SIZE 1\n#define AVR32_USBB_RXSTALLDI 6\n#define AVR32_USBB_RXSTALLDIC 6\n#define AVR32_USBB_RXSTALLDIC_MASK 0x00000040\n#define AVR32_USBB_RXSTALLDIC_OFFSET 6\n#define AVR32_USBB_RXSTALLDIC_SIZE 1\n#define AVR32_USBB_RXSTALLDIS 6\n#define AVR32_USBB_RXSTALLDIS_MASK 0x00000040\n#define AVR32_USBB_RXSTALLDIS_OFFSET 6\n#define AVR32_USBB_RXSTALLDIS_SIZE 1\n#define AVR32_USBB_RXSTALLDI_MASK 0x00000040\n#define AVR32_USBB_RXSTALLDI_OFFSET 6\n#define AVR32_USBB_RXSTALLDI_SIZE 1\n#define AVR32_USBB_RXSTPE 2\n#define AVR32_USBB_RXSTPEC 2\n#define AVR32_USBB_RXSTPEC_MASK 0x00000004\n#define AVR32_USBB_RXSTPEC_OFFSET 2\n#define AVR32_USBB_RXSTPEC_SIZE 1\n#define AVR32_USBB_RXSTPES 2\n#define AVR32_USBB_RXSTPES_MASK 0x00000004\n#define AVR32_USBB_RXSTPES_OFFSET 2\n#define AVR32_USBB_RXSTPES_SIZE 1\n#define AVR32_USBB_RXSTPE_MASK 0x00000004\n#define AVR32_USBB_RXSTPE_OFFSET 2\n#define AVR32_USBB_RXSTPE_SIZE 1\n#define AVR32_USBB_RXSTPI 2\n#define AVR32_USBB_RXSTPIC 2\n#define AVR32_USBB_RXSTPIC_MASK 0x00000004\n#define AVR32_USBB_RXSTPIC_OFFSET 2\n#define AVR32_USBB_RXSTPIC_SIZE 1\n#define AVR32_USBB_RXSTPIS 2\n#define AVR32_USBB_RXSTPIS_MASK 0x00000004\n#define AVR32_USBB_RXSTPIS_OFFSET 2\n#define AVR32_USBB_RXSTPIS_SIZE 1\n#define AVR32_USBB_RXSTPI_MASK 0x00000004\n#define AVR32_USBB_RXSTPI_OFFSET 2\n#define AVR32_USBB_RXSTPI_SIZE 1\n#define AVR32_USBB_SETMDATA 8\n#define AVR32_USBB_SETMDATA_MASK 0x00000100\n#define AVR32_USBB_SETMDATA_OFFSET 8\n#define AVR32_USBB_SETMDATA_SIZE 1\n#define AVR32_USBB_SETUP 0x00000000\n#define AVR32_USBB_SHORTPACKET 7\n#define AVR32_USBB_SHORTPACKETC 7\n#define AVR32_USBB_SHORTPACKETC_MASK 0x00000080\n#define AVR32_USBB_SHORTPACKETC_OFFSET 7\n#define AVR32_USBB_SHORTPACKETC_SIZE 1\n#define AVR32_USBB_SHORTPACKETE 7\n#define AVR32_USBB_SHORTPACKETEC 7\n#define AVR32_USBB_SHORTPACKETEC_MASK 0x00000080\n#define AVR32_USBB_SHORTPACKETEC_OFFSET 7\n#define AVR32_USBB_SHORTPACKETEC_SIZE 1\n#define AVR32_USBB_SHORTPACKETES 7\n#define AVR32_USBB_SHORTPACKETES_MASK 0x00000080\n#define AVR32_USBB_SHORTPACKETES_OFFSET 7\n#define AVR32_USBB_SHORTPACKETES_SIZE 1\n#define AVR32_USBB_SHORTPACKETE_MASK 0x00000080\n#define AVR32_USBB_SHORTPACKETE_OFFSET 7\n#define AVR32_USBB_SHORTPACKETE_SIZE 1\n#define AVR32_USBB_SHORTPACKETI 7\n#define AVR32_USBB_SHORTPACKETIC 7\n#define AVR32_USBB_SHORTPACKETIC_MASK 0x00000080\n#define AVR32_USBB_SHORTPACKETIC_OFFSET 7\n#define AVR32_USBB_SHORTPACKETIC_SIZE 1\n#define AVR32_USBB_SHORTPACKETIE 7\n#define AVR32_USBB_SHORTPACKETIEC 7\n#define AVR32_USBB_SHORTPACKETIEC_MASK 0x00000080\n#define AVR32_USBB_SHORTPACKETIEC_OFFSET 7\n#define AVR32_USBB_SHORTPACKETIEC_SIZE 1\n#define AVR32_USBB_SHORTPACKETIES 7\n#define AVR32_USBB_SHORTPACKETIES_MASK 0x00000080\n#define AVR32_USBB_SHORTPACKETIES_OFFSET 7\n#define AVR32_USBB_SHORTPACKETIES_SIZE 1\n#define AVR32_USBB_SHORTPACKETIE_MASK 0x00000080\n#define AVR32_USBB_SHORTPACKETIE_OFFSET 7\n#define AVR32_USBB_SHORTPACKETIE_SIZE 1\n#define AVR32_USBB_SHORTPACKETIS 7\n#define AVR32_USBB_SHORTPACKETIS_MASK 0x00000080\n#define AVR32_USBB_SHORTPACKETIS_OFFSET 7\n#define AVR32_USBB_SHORTPACKETIS_SIZE 1\n#define AVR32_USBB_SHORTPACKETI_MASK 0x00000080\n#define AVR32_USBB_SHORTPACKETI_OFFSET 7\n#define AVR32_USBB_SHORTPACKETI_SIZE 1\n#define AVR32_USBB_SHORTPACKETS 7\n#define AVR32_USBB_SHORTPACKETS_MASK 0x00000080\n#define AVR32_USBB_SHORTPACKETS_OFFSET 7\n#define AVR32_USBB_SHORTPACKETS_SIZE 1\n#define AVR32_USBB_SHORTPACKET_MASK 0x00000080\n#define AVR32_USBB_SHORTPACKET_OFFSET 7\n#define AVR32_USBB_SHORTPACKET_SIZE 1\n#define AVR32_USBB_SINGLE 0x00000000\n#define AVR32_USBB_SOF 2\n#define AVR32_USBB_SOFC 2\n#define AVR32_USBB_SOFCNTMAX 24\n#define AVR32_USBB_SOFCNTMAX_MASK 0x7f000000\n#define AVR32_USBB_SOFCNTMAX_OFFSET 24\n#define AVR32_USBB_SOFCNTMAX_SIZE 7\n#define AVR32_USBB_SOFC_MASK 0x00000004\n#define AVR32_USBB_SOFC_OFFSET 2\n#define AVR32_USBB_SOFC_SIZE 1\n#define AVR32_USBB_SOFEC 2\n#define AVR32_USBB_SOFEC_MASK 0x00000004\n#define AVR32_USBB_SOFEC_OFFSET 2\n#define AVR32_USBB_SOFEC_SIZE 1\n#define AVR32_USBB_SOFES 2\n#define AVR32_USBB_SOFES_MASK 0x00000004\n#define AVR32_USBB_SOFES_OFFSET 2\n#define AVR32_USBB_SOFES_SIZE 1\n#define AVR32_USBB_SOFE_SIZE 1\n#define AVR32_USBB_SOFS 2\n#define AVR32_USBB_SOFS_MASK 0x00000004\n#define AVR32_USBB_SOFS_OFFSET 2\n#define AVR32_USBB_SOFS_SIZE 1\n#define AVR32_USBB_SOF_MASK 0x00000004\n#define AVR32_USBB_SOF_OFFSET 2\n#define AVR32_USBB_SOF_SIZE 1\n#define AVR32_USBB_SPDCONF_SIZE 2\n#define AVR32_USBB_SPEED_FULL 0x00000000\n#define AVR32_USBB_SPEED_LOW 0x00000002\n#define AVR32_USBB_SRPE 2\n#define AVR32_USBB_SRPE_MASK 0x00000004\n#define AVR32_USBB_SRPE_OFFSET 2\n#define AVR32_USBB_SRPE_SIZE 1\n#define AVR32_USBB_SRPI 2\n#define AVR32_USBB_SRPIC 2\n#define AVR32_USBB_SRPIC_MASK 0x00000004\n#define AVR32_USBB_SRPIC_OFFSET 2\n#define AVR32_USBB_SRPIC_SIZE 1\n#define AVR32_USBB_SRPIS 2\n#define AVR32_USBB_SRPIS_MASK 0x00000004\n#define AVR32_USBB_SRPIS_OFFSET 2\n#define AVR32_USBB_SRPIS_SIZE 1\n#define AVR32_USBB_SRPI_MASK 0x00000004\n#define AVR32_USBB_SRPI_OFFSET 2\n#define AVR32_USBB_SRPI_SIZE 1\n#define AVR32_USBB_SRPREQ 10\n#define AVR32_USBB_SRPREQ_MASK 0x00000400\n#define AVR32_USBB_SRPREQ_OFFSET 10\n#define AVR32_USBB_SRPREQ_SIZE 1\n#define AVR32_USBB_SRPSEL 9\n#define AVR32_USBB_SRPSEL_MASK 0x00000200\n#define AVR32_USBB_SRPSEL_OFFSET 9\n#define AVR32_USBB_SRPSEL_SIZE 1\n#define AVR32_USBB_SRP_DET_TMOUT 0x00000003\n#define AVR32_USBB_SRP_DET_TMOUT_100_US 0x00000001\n#define AVR32_USBB_SRP_DET_TMOUT_10_US 0x00000000\n#define AVR32_USBB_SRP_DET_TMOUT_11_MS 0x00000003\n#define AVR32_USBB_SRP_DET_TMOUT_1_MS 0x00000002\n#define AVR32_USBB_STALLEDE 6\n#define AVR32_USBB_STALLEDEC 6\n#define AVR32_USBB_STALLEDEC_MASK 0x00000040\n#define AVR32_USBB_STALLEDEC_OFFSET 6\n#define AVR32_USBB_STALLEDEC_SIZE 1\n#define AVR32_USBB_STALLEDES 6\n#define AVR32_USBB_STALLEDES_MASK 0x00000040\n#define AVR32_USBB_STALLEDES_OFFSET 6\n#define AVR32_USBB_STALLEDES_SIZE 1\n#define AVR32_USBB_STALLEDE_MASK 0x00000040\n#define AVR32_USBB_STALLEDE_OFFSET 6\n#define AVR32_USBB_STALLEDE_SIZE 1\n#define AVR32_USBB_STALLEDI 6\n#define AVR32_USBB_STALLEDIC 6\n#define AVR32_USBB_STALLEDIC_MASK 0x00000040\n#define AVR32_USBB_STALLEDIC_OFFSET 6\n#define AVR32_USBB_STALLEDIC_SIZE 1\n#define AVR32_USBB_STALLEDIS 6\n#define AVR32_USBB_STALLEDIS_MASK 0x00000040\n#define AVR32_USBB_STALLEDIS_OFFSET 6\n#define AVR32_USBB_STALLEDIS_SIZE 1\n#define AVR32_USBB_STALLEDI_MASK 0x00000040\n#define AVR32_USBB_STALLEDI_OFFSET 6\n#define AVR32_USBB_STALLEDI_SIZE 1\n#define AVR32_USBB_STALLRQ 19\n#define AVR32_USBB_STALLRQC 19\n#define AVR32_USBB_STALLRQC_MASK 0x00080000\n#define AVR32_USBB_STALLRQC_OFFSET 19\n#define AVR32_USBB_STALLRQC_SIZE 1\n#define AVR32_USBB_STALLRQS 19\n#define AVR32_USBB_STALLRQS_MASK 0x00080000\n#define AVR32_USBB_STALLRQS_OFFSET 19\n#define AVR32_USBB_STALLRQS_SIZE 1\n#define AVR32_USBB_STALLRQ_MASK 0x00080000\n#define AVR32_USBB_STALLRQ_OFFSET 19\n#define AVR32_USBB_STALLRQ_SIZE 1\n#define AVR32_USBB_STOE 7\n#define AVR32_USBB_STOE_MASK 0x00000080\n#define AVR32_USBB_STOE_OFFSET 7\n#define AVR32_USBB_STOE_SIZE 1\n#define AVR32_USBB_STOI 7\n#define AVR32_USBB_STOIC 7\n#define AVR32_USBB_STOIC_MASK 0x00000080\n#define AVR32_USBB_STOIC_OFFSET 7\n#define AVR32_USBB_STOIC_SIZE 1\n#define AVR32_USBB_STOIS 7\n#define AVR32_USBB_STOIS_MASK 0x00000080\n#define AVR32_USBB_STOIS_OFFSET 7\n#define AVR32_USBB_STOIS_SIZE 1\n#define AVR32_USBB_STOI_MASK 0x00000080\n#define AVR32_USBB_STOI_OFFSET 7\n#define AVR32_USBB_STOI_SIZE 1\n#define AVR32_USBB_SUSP 0\n#define AVR32_USBB_SUSPC 0\n#define AVR32_USBB_SUSPC_MASK 0x00000001\n#define AVR32_USBB_SUSPC_OFFSET 0\n#define AVR32_USBB_SUSPC_SIZE 1\n#define AVR32_USBB_SUSPE 0\n#define AVR32_USBB_SUSPEC 0\n#define AVR32_USBB_SUSPEC_MASK 0x00000001\n#define AVR32_USBB_SUSPEC_OFFSET 0\n#define AVR32_USBB_SUSPEC_SIZE 1\n#define AVR32_USBB_SUSPES 0\n#define AVR32_USBB_SUSPES_MASK 0x00000001\n#define AVR32_USBB_SUSPES_OFFSET 0\n#define AVR32_USBB_SUSPES_SIZE 1\n#define AVR32_USBB_SUSPE_MASK 0x00000001\n#define AVR32_USBB_SUSPE_OFFSET 0\n#define AVR32_USBB_SUSPE_SIZE 1\n#define AVR32_USBB_SUSPS 0\n#define AVR32_USBB_SUSPS_MASK 0x00000001\n#define AVR32_USBB_SUSPS_OFFSET 0\n#define AVR32_USBB_SUSPS_SIZE 1\n#define AVR32_USBB_SUSP_MASK 0x00000001\n#define AVR32_USBB_SUSP_OFFSET 0\n#define AVR32_USBB_SUSP_SIZE 1\n#define AVR32_USBB_TIMEOUT 3\n#define AVR32_USBB_TIMEOUT_MASK 0x00000008\n#define AVR32_USBB_TIMEOUT_OFFSET 3\n#define AVR32_USBB_TIMEOUT_SIZE 1\n#define AVR32_USBB_TIMPAGE 20\n#define AVR32_USBB_TIMPAGE_A_WAIT_VRISE 0x00000000\n#define AVR32_USBB_TIMPAGE_MASK 0x00300000\n#define AVR32_USBB_TIMPAGE_OFFSET 20\n#define AVR32_USBB_TIMPAGE_PD_TMOUT_CNT 0x00000002\n#define AVR32_USBB_TIMPAGE_SIZE 2\n#define AVR32_USBB_TIMPAGE_SRP_DET_TMOUT 0x00000003\n#define AVR32_USBB_TIMPAGE_VB_BUS_PULSING 0x00000001\n#define AVR32_USBB_TIMVALUE 16\n#define AVR32_USBB_TIMVALUE_A_WAIT_VRISE_100_MS 0x00000003\n#define AVR32_USBB_TIMVALUE_A_WAIT_VRISE_20_MS 0x00000000\n#define AVR32_USBB_TIMVALUE_A_WAIT_VRISE_50_MS 0x00000001\n#define AVR32_USBB_TIMVALUE_A_WAIT_VRISE_70_MS 0x00000002\n#define AVR32_USBB_TIMVALUE_MASK 0x00030000\n#define AVR32_USBB_TIMVALUE_OFFSET 16\n#define AVR32_USBB_TIMVALUE_PD_TMOUT_CNT_105_MS 0x00000001\n#define AVR32_USBB_TIMVALUE_PD_TMOUT_CNT_118_MS 0x00000002\n#define AVR32_USBB_TIMVALUE_PD_TMOUT_CNT_131_MS 0x00000003\n#define AVR32_USBB_TIMVALUE_PD_TMOUT_CNT_93_MS 0x00000000\n#define AVR32_USBB_TIMVALUE_SIZE 2\n#define AVR32_USBB_TIMVALUE_SRP_DET_TMOUT_100_US 0x00000001\n#define AVR32_USBB_TIMVALUE_SRP_DET_TMOUT_10_US 0x00000000\n#define AVR32_USBB_TIMVALUE_SRP_DET_TMOUT_11_MS 0x00000003\n#define AVR32_USBB_TIMVALUE_SRP_DET_TMOUT_1_MS 0x00000002\n#define AVR32_USBB_TIMVALUE_VB_BUS_PULSING_15_MS 0x00000000\n#define AVR32_USBB_TIMVALUE_VB_BUS_PULSING_23_MS 0x00000001\n#define AVR32_USBB_TIMVALUE_VB_BUS_PULSING_31_MS 0x00000002\n#define AVR32_USBB_TIMVALUE_VB_BUS_PULSING_40_MS 0x00000003\n#define AVR32_USBB_TRIPLE 0x00000002\n#define AVR32_USBB_TSTJ 13\n#define AVR32_USBB_TSTJ_MASK 0x00002000\n#define AVR32_USBB_TSTJ_OFFSET 13\n#define AVR32_USBB_TSTJ_SIZE 1\n#define AVR32_USBB_TSTK 14\n#define AVR32_USBB_TSTK_MASK 0x00004000\n#define AVR32_USBB_TSTK_OFFSET 14\n#define AVR32_USBB_TSTK_SIZE 1\n#define AVR32_USBB_TSTPCKT 15\n#define AVR32_USBB_TSTPCKT_MASK 0x00008000\n#define AVR32_USBB_TSTPCKT_OFFSET 15\n#define AVR32_USBB_TSTPCKT_SIZE 1\n#define AVR32_USBB_TXINE 0\n#define AVR32_USBB_TXINEC 0\n#define AVR32_USBB_TXINEC_MASK 0x00000001\n#define AVR32_USBB_TXINEC_OFFSET 0\n#define AVR32_USBB_TXINEC_SIZE 1\n#define AVR32_USBB_TXINES 0\n#define AVR32_USBB_TXINES_MASK 0x00000001\n#define AVR32_USBB_TXINES_OFFSET 0\n#define AVR32_USBB_TXINES_SIZE 1\n#define AVR32_USBB_TXINE_MASK 0x00000001\n#define AVR32_USBB_TXINE_OFFSET 0\n#define AVR32_USBB_TXINE_SIZE 1\n#define AVR32_USBB_TXINI 0\n#define AVR32_USBB_TXINIC 0\n#define AVR32_USBB_TXINIC_MASK 0x00000001\n#define AVR32_USBB_TXINIC_OFFSET 0\n#define AVR32_USBB_TXINIC_SIZE 1\n#define AVR32_USBB_TXINIS 0\n#define AVR32_USBB_TXINIS_MASK 0x00000001\n#define AVR32_USBB_TXINIS_OFFSET 0\n#define AVR32_USBB_TXINIS_SIZE 1\n#define AVR32_USBB_TXINI_MASK 0x00000001\n#define AVR32_USBB_TXINI_OFFSET 0\n#define AVR32_USBB_TXINI_SIZE 1\n#define AVR32_USBB_TXOUTE 1\n#define AVR32_USBB_TXOUTEC 1\n#define AVR32_USBB_TXOUTEC_MASK 0x00000002\n#define AVR32_USBB_TXOUTEC_OFFSET 1\n#define AVR32_USBB_TXOUTEC_SIZE 1\n#define AVR32_USBB_TXOUTES 1\n#define AVR32_USBB_TXOUTES_MASK 0x00000002\n#define AVR32_USBB_TXOUTES_OFFSET 1\n#define AVR32_USBB_TXOUTES_SIZE 1\n#define AVR32_USBB_TXOUTE_MASK 0x00000002\n#define AVR32_USBB_TXOUTE_OFFSET 1\n#define AVR32_USBB_TXOUTE_SIZE 1\n#define AVR32_USBB_TXOUTI 1\n#define AVR32_USBB_TXOUTIC 1\n#define AVR32_USBB_TXOUTIC_MASK 0x00000002\n#define AVR32_USBB_TXOUTIC_OFFSET 1\n#define AVR32_USBB_TXOUTIC_SIZE 1\n#define AVR32_USBB_TXOUTIS 1\n#define AVR32_USBB_TXOUTIS_MASK 0x00000002\n#define AVR32_USBB_TXOUTIS_OFFSET 1\n#define AVR32_USBB_TXOUTIS_SIZE 1\n#define AVR32_USBB_TXOUTI_MASK 0x00000002\n#define AVR32_USBB_TXOUTI_OFFSET 1\n#define AVR32_USBB_TXOUTI_SIZE 1\n#define AVR32_USBB_TXSTPE 2\n#define AVR32_USBB_TXSTPEC 2\n#define AVR32_USBB_TXSTPEC_MASK 0x00000004\n#define AVR32_USBB_TXSTPEC_OFFSET 2\n#define AVR32_USBB_TXSTPEC_SIZE 1\n#define AVR32_USBB_TXSTPES 2\n#define AVR32_USBB_TXSTPES_MASK 0x00000004\n#define AVR32_USBB_TXSTPES_OFFSET 2\n#define AVR32_USBB_TXSTPES_SIZE 1\n#define AVR32_USBB_TXSTPE_MASK 0x00000004\n#define AVR32_USBB_TXSTPE_OFFSET 2\n#define AVR32_USBB_TXSTPE_SIZE 1\n#define AVR32_USBB_TXSTPI 2\n#define AVR32_USBB_TXSTPIC 2\n#define AVR32_USBB_TXSTPIC_MASK 0x00000004\n#define AVR32_USBB_TXSTPIC_OFFSET 2\n#define AVR32_USBB_TXSTPIC_SIZE 1\n#define AVR32_USBB_TXSTPIS 2\n#define AVR32_USBB_TXSTPIS_MASK 0x00000004\n#define AVR32_USBB_TXSTPIS_OFFSET 2\n#define AVR32_USBB_TXSTPIS_SIZE 1\n#define AVR32_USBB_TXSTPI_MASK 0x00000004\n#define AVR32_USBB_TXSTPI_OFFSET 2\n#define AVR32_USBB_TXSTPI_SIZE 1\n#define AVR32_USBB_UADD 0\n#define AVR32_USBB_UADDRSIZE 0x00000820\n#define AVR32_USBB_UADDRSIZE_MASK 0xffffffff\n#define AVR32_USBB_UADDRSIZE_OFFSET 0\n#define AVR32_USBB_UADDRSIZE_SIZE 32\n#define AVR32_USBB_UADDRSIZE_UADDRSIZE 0\n#define AVR32_USBB_UADDRSIZE_UADDRSIZE_MASK 0xffffffff\n#define AVR32_USBB_UADDRSIZE_UADDRSIZE_OFFSET 0\n#define AVR32_USBB_UADDRSIZE_UADDRSIZE_SIZE 32\n#define AVR32_USBB_UADD_MASK 0x0000007f\n#define AVR32_USBB_UADD_OFFSET 0\n#define AVR32_USBB_UADD_SIZE 7\n#define AVR32_USBB_UATST1 0x00000810\n#define AVR32_USBB_UATST1_COUNTERA 0\n#define AVR32_USBB_UATST1_COUNTERA_MASK 0x00007fff\n#define AVR32_USBB_UATST1_COUNTERA_OFFSET 0\n#define AVR32_USBB_UATST1_COUNTERA_SIZE 15\n#define AVR32_USBB_UATST1_COUNTERB 16\n#define AVR32_USBB_UATST1_COUNTERB_MASK 0x003f0000\n#define AVR32_USBB_UATST1_COUNTERB_OFFSET 16\n#define AVR32_USBB_UATST1_COUNTERB_SIZE 6\n#define AVR32_USBB_UATST1_LOADCNTA 15\n#define AVR32_USBB_UATST1_LOADCNTA_MASK 0x00008000\n#define AVR32_USBB_UATST1_LOADCNTA_OFFSET 15\n#define AVR32_USBB_UATST1_LOADCNTA_SIZE 1\n#define AVR32_USBB_UATST1_LOADCNTB 23\n#define AVR32_USBB_UATST1_LOADCNTB_MASK 0x00800000\n#define AVR32_USBB_UATST1_LOADCNTB_OFFSET 23\n#define AVR32_USBB_UATST1_LOADCNTB_SIZE 1\n#define AVR32_USBB_UATST1_LOADSOFCNT 31\n#define AVR32_USBB_UATST1_LOADSOFCNT_MASK 0x80000000\n#define AVR32_USBB_UATST1_LOADSOFCNT_OFFSET 31\n#define AVR32_USBB_UATST1_LOADSOFCNT_SIZE 1\n#define AVR32_USBB_UATST1_SOFCNTMAX 24\n#define AVR32_USBB_UATST1_SOFCNTMAX_MASK 0x7f000000\n#define AVR32_USBB_UATST1_SOFCNTMAX_OFFSET 24\n#define AVR32_USBB_UATST1_SOFCNTMAX_SIZE 7\n#define AVR32_USBB_UATST2 0x00000814\n#define AVR32_USBB_UATST2_BYPASSDPLL 5\n#define AVR32_USBB_UATST2_BYPASSDPLL_MASK 0x00000020\n#define AVR32_USBB_UATST2_BYPASSDPLL_OFFSET 5\n#define AVR32_USBB_UATST2_BYPASSDPLL_SIZE 1\n#define AVR32_USBB_UATST2_DISBALEGATEDCLOCK 3\n#define AVR32_USBB_UATST2_DISBALEGATEDCLOCK_MASK 0x00000008\n#define AVR32_USBB_UATST2_DISBALEGATEDCLOCK_OFFSET 3\n#define AVR32_USBB_UATST2_DISBALEGATEDCLOCK_SIZE 1\n#define AVR32_USBB_UATST2_FORCEHSRESETTO50MS 7\n#define AVR32_USBB_UATST2_FORCEHSRESETTO50MS_MASK 0x00000080\n#define AVR32_USBB_UATST2_FORCEHSRESETTO50MS_OFFSET 7\n#define AVR32_USBB_UATST2_FORCEHSRESETTO50MS_SIZE 1\n#define AVR32_USBB_UATST2_FORCESUSPENDMTO1 4\n#define AVR32_USBB_UATST2_FORCESUSPENDMTO1_MASK 0x00000010\n#define AVR32_USBB_UATST2_FORCESUSPENDMTO1_OFFSET 4\n#define AVR32_USBB_UATST2_FORCESUSPENDMTO1_SIZE 1\n#define AVR32_USBB_UATST2_FULLDETACHEN 0\n#define AVR32_USBB_UATST2_FULLDETACHEN_MASK 0x00000001\n#define AVR32_USBB_UATST2_FULLDETACHEN_OFFSET 0\n#define AVR32_USBB_UATST2_FULLDETACHEN_SIZE 1\n#define AVR32_USBB_UATST2_HOSTHSDISCONNECTDISABLE 6\n#define AVR32_USBB_UATST2_HOSTHSDISCONNECTDISABLE_MASK 0x00000040\n#define AVR32_USBB_UATST2_HOSTHSDISCONNECTDISABLE_OFFSET 6\n#define AVR32_USBB_UATST2_HOSTHSDISCONNECTDISABLE_SIZE 1\n#define AVR32_USBB_UATST2_HSSERIALMODE 1\n#define AVR32_USBB_UATST2_HSSERIALMODE_MASK 0x00000002\n#define AVR32_USBB_UATST2_HSSERIALMODE_OFFSET 1\n#define AVR32_USBB_UATST2_HSSERIALMODE_SIZE 1\n#define AVR32_USBB_UATST2_LOOPBACKMODE 2\n#define AVR32_USBB_UATST2_LOOPBACKMODE_MASK 0x00000004\n#define AVR32_USBB_UATST2_LOOPBACKMODE_OFFSET 2\n#define AVR32_USBB_UATST2_LOOPBACKMODE_SIZE 1\n#define AVR32_USBB_UATST2_UTMIRESET 8\n#define AVR32_USBB_UATST2_UTMIRESET_MASK 0x00000100\n#define AVR32_USBB_UATST2_UTMIRESET_OFFSET 8\n#define AVR32_USBB_UATST2_UTMIRESET_SIZE 1\n#define AVR32_USBB_UDADDRSIZE 0x00000034\n#define AVR32_USBB_UDCON 0x00000000\n#define AVR32_USBB_UDCON_ADDEN 7\n#define AVR32_USBB_UDCON_ADDEN_MASK 0x00000080\n#define AVR32_USBB_UDCON_ADDEN_OFFSET 7\n#define AVR32_USBB_UDCON_ADDEN_SIZE 1\n#define AVR32_USBB_UDCON_DETACH 8\n#define AVR32_USBB_UDCON_DETACH_MASK 0x00000100\n#define AVR32_USBB_UDCON_DETACH_OFFSET 8\n#define AVR32_USBB_UDCON_DETACH_SIZE 1\n#define AVR32_USBB_UDCON_FRZCLK 18\n#define AVR32_USBB_UDCON_FRZCLK_MASK 0x00040000\n#define AVR32_USBB_UDCON_FRZCLK_OFFSET 18\n#define AVR32_USBB_UDCON_FRZCLK_SIZE 1\n#define AVR32_USBB_UDCON_LS 12\n#define AVR32_USBB_UDCON_LS_MASK 0x00001000\n#define AVR32_USBB_UDCON_LS_OFFSET 12\n#define AVR32_USBB_UDCON_LS_SIZE 1\n#define AVR32_USBB_UDCON_OPMODE2 16\n#define AVR32_USBB_UDCON_OPMODE2_MASK 0x00010000\n#define AVR32_USBB_UDCON_OPMODE2_OFFSET 16\n#define AVR32_USBB_UDCON_OPMODE2_SIZE 1\n#define AVR32_USBB_UDCON_RMWKUP 9\n#define AVR32_USBB_UDCON_RMWKUP_MASK 0x00000200\n#define AVR32_USBB_UDCON_RMWKUP_OFFSET 9\n#define AVR32_USBB_UDCON_RMWKUP_SIZE 1\n#define AVR32_USBB_UDCON_SPDCONF 10\n#define AVR32_USBB_UDCON_SPDCONF_MASK 0x00000c00\n#define AVR32_USBB_UDCON_SPDCONF_OFFSET 10\n#define AVR32_USBB_UDCON_SPDCONF_SIZE 2\n#define AVR32_USBB_UDCON_TSTJ 13\n#define AVR32_USBB_UDCON_TSTJ_MASK 0x00002000\n#define AVR32_USBB_UDCON_TSTJ_OFFSET 13\n#define AVR32_USBB_UDCON_TSTJ_SIZE 1\n#define AVR32_USBB_UDCON_TSTK 14\n#define AVR32_USBB_UDCON_TSTK_MASK 0x00004000\n#define AVR32_USBB_UDCON_TSTK_OFFSET 14\n#define AVR32_USBB_UDCON_TSTK_SIZE 1\n#define AVR32_USBB_UDCON_TSTPCKT 15\n#define AVR32_USBB_UDCON_TSTPCKT_MASK 0x00008000\n#define AVR32_USBB_UDCON_TSTPCKT_OFFSET 15\n#define AVR32_USBB_UDCON_TSTPCKT_SIZE 1\n#define AVR32_USBB_UDCON_UADD 0\n#define AVR32_USBB_UDCON_UADD_MASK 0x0000007f\n#define AVR32_USBB_UDCON_UADD_OFFSET 0\n#define AVR32_USBB_UDCON_UADD_SIZE 7\n#define AVR32_USBB_UDCON_USBE 17\n#define AVR32_USBB_UDCON_USBE_MASK 0x00020000\n#define AVR32_USBB_UDCON_USBE_OFFSET 17\n#define AVR32_USBB_UDCON_USBE_SIZE 1\n#define AVR32_USBB_UDDMA1_ADDR 0x00000314\n#define AVR32_USBB_UDDMA1_ADDR_HSB_ADDR 0\n#define AVR32_USBB_UDDMA1_ADDR_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_UDDMA1_ADDR_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_UDDMA1_ADDR_HSB_ADDR_SIZE 32\n#define AVR32_USBB_UDDMA1_CONTROL 0x00000318\n#define AVR32_USBB_UDDMA1_CONTROL_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_UDDMA1_CONTROL_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_UDDMA1_CONTROL_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_UDDMA1_CONTROL_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_UDDMA1_CONTROL_BURST_LOCK_EN 7\n#define AVR32_USBB_UDDMA1_CONTROL_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_UDDMA1_CONTROL_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_UDDMA1_CONTROL_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH 16\n#define AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_UDDMA1_CONTROL_CH_EN 0\n#define AVR32_USBB_UDDMA1_CONTROL_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UDDMA1_CONTROL_CH_EN_OFFSET 0\n#define AVR32_USBB_UDDMA1_CONTROL_CH_EN_SIZE 1\n#define AVR32_USBB_UDDMA1_CONTROL_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_UDDMA1_CONTROL_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_UDDMA1_CONTROL_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_UDDMA1_CONTROL_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA1_CONTROL_DMAEND_EN 3\n#define AVR32_USBB_UDDMA1_CONTROL_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_UDDMA1_CONTROL_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_UDDMA1_CONTROL_DMAEND_EN_SIZE 1\n#define AVR32_USBB_UDDMA1_CONTROL_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_UDDMA1_CONTROL_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_UDDMA1_CONTROL_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_UDDMA1_CONTROL_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA1_CONTROL_EOT_IRQ_EN 4\n#define AVR32_USBB_UDDMA1_CONTROL_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_UDDMA1_CONTROL_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_UDDMA1_CONTROL_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA1_CONTROL_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_UDDMA1_CONTROL_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_UDDMA1_CONTROL_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_UDDMA1_CONTROL_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_UDDMA1_NEXTDESC 0x00000310\n#define AVR32_USBB_UDDMA1_NEXTDESC_NXT_DESC_ADDR 4\n#define AVR32_USBB_UDDMA1_NEXTDESC_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_UDDMA1_NEXTDESC_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_UDDMA1_NEXTDESC_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_UDDMA1_STATUS 0x0000031c\n#define AVR32_USBB_UDDMA1_STATUS_CH_ACTIVE 1\n#define AVR32_USBB_UDDMA1_STATUS_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_UDDMA1_STATUS_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_UDDMA1_STATUS_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_UDDMA1_STATUS_CH_BYTE_CNT 16\n#define AVR32_USBB_UDDMA1_STATUS_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_UDDMA1_STATUS_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_UDDMA1_STATUS_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_UDDMA1_STATUS_CH_EN 0\n#define AVR32_USBB_UDDMA1_STATUS_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UDDMA1_STATUS_CH_EN_OFFSET 0\n#define AVR32_USBB_UDDMA1_STATUS_CH_EN_SIZE 1\n#define AVR32_USBB_UDDMA1_STATUS_DESC_LD_STA 6\n#define AVR32_USBB_UDDMA1_STATUS_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_UDDMA1_STATUS_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_UDDMA1_STATUS_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_UDDMA1_STATUS_EOCH_BUFF_STA 5\n#define AVR32_USBB_UDDMA1_STATUS_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_UDDMA1_STATUS_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_UDDMA1_STATUS_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_UDDMA1_STATUS_EOT_STA 4\n#define AVR32_USBB_UDDMA1_STATUS_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_UDDMA1_STATUS_EOT_STA_OFFSET 4\n#define AVR32_USBB_UDDMA1_STATUS_EOT_STA_SIZE 1\n#define AVR32_USBB_UDDMA2_ADDR 0x00000324\n#define AVR32_USBB_UDDMA2_ADDR_HSB_ADDR 0\n#define AVR32_USBB_UDDMA2_ADDR_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_UDDMA2_ADDR_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_UDDMA2_ADDR_HSB_ADDR_SIZE 32\n#define AVR32_USBB_UDDMA2_CONTROL 0x00000328\n#define AVR32_USBB_UDDMA2_CONTROL_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_UDDMA2_CONTROL_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_UDDMA2_CONTROL_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_UDDMA2_CONTROL_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_UDDMA2_CONTROL_BURST_LOCK_EN 7\n#define AVR32_USBB_UDDMA2_CONTROL_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_UDDMA2_CONTROL_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_UDDMA2_CONTROL_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_UDDMA2_CONTROL_CH_BYTE_LENGTH 16\n#define AVR32_USBB_UDDMA2_CONTROL_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_UDDMA2_CONTROL_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_UDDMA2_CONTROL_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_UDDMA2_CONTROL_CH_EN 0\n#define AVR32_USBB_UDDMA2_CONTROL_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UDDMA2_CONTROL_CH_EN_OFFSET 0\n#define AVR32_USBB_UDDMA2_CONTROL_CH_EN_SIZE 1\n#define AVR32_USBB_UDDMA2_CONTROL_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_UDDMA2_CONTROL_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_UDDMA2_CONTROL_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_UDDMA2_CONTROL_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA2_CONTROL_DMAEND_EN 3\n#define AVR32_USBB_UDDMA2_CONTROL_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_UDDMA2_CONTROL_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_UDDMA2_CONTROL_DMAEND_EN_SIZE 1\n#define AVR32_USBB_UDDMA2_CONTROL_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_UDDMA2_CONTROL_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_UDDMA2_CONTROL_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_UDDMA2_CONTROL_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA2_CONTROL_EOT_IRQ_EN 4\n#define AVR32_USBB_UDDMA2_CONTROL_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_UDDMA2_CONTROL_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_UDDMA2_CONTROL_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA2_CONTROL_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_UDDMA2_CONTROL_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_UDDMA2_CONTROL_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_UDDMA2_CONTROL_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_UDDMA2_NEXTDESC 0x00000320\n#define AVR32_USBB_UDDMA2_NEXTDESC_NXT_DESC_ADDR 4\n#define AVR32_USBB_UDDMA2_NEXTDESC_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_UDDMA2_NEXTDESC_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_UDDMA2_NEXTDESC_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_UDDMA2_STATUS 0x0000032c\n#define AVR32_USBB_UDDMA2_STATUS_CH_ACTIVE 1\n#define AVR32_USBB_UDDMA2_STATUS_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_UDDMA2_STATUS_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_UDDMA2_STATUS_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_UDDMA2_STATUS_CH_BYTE_CNT 16\n#define AVR32_USBB_UDDMA2_STATUS_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_UDDMA2_STATUS_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_UDDMA2_STATUS_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_UDDMA2_STATUS_CH_EN 0\n#define AVR32_USBB_UDDMA2_STATUS_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UDDMA2_STATUS_CH_EN_OFFSET 0\n#define AVR32_USBB_UDDMA2_STATUS_CH_EN_SIZE 1\n#define AVR32_USBB_UDDMA2_STATUS_DESC_LD_STA 6\n#define AVR32_USBB_UDDMA2_STATUS_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_UDDMA2_STATUS_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_UDDMA2_STATUS_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_UDDMA2_STATUS_EOCH_BUFF_STA 5\n#define AVR32_USBB_UDDMA2_STATUS_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_UDDMA2_STATUS_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_UDDMA2_STATUS_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_UDDMA2_STATUS_EOT_STA 4\n#define AVR32_USBB_UDDMA2_STATUS_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_UDDMA2_STATUS_EOT_STA_OFFSET 4\n#define AVR32_USBB_UDDMA2_STATUS_EOT_STA_SIZE 1\n#define AVR32_USBB_UDDMA3_ADDR 0x00000334\n#define AVR32_USBB_UDDMA3_ADDR_HSB_ADDR 0\n#define AVR32_USBB_UDDMA3_ADDR_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_UDDMA3_ADDR_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_UDDMA3_ADDR_HSB_ADDR_SIZE 32\n#define AVR32_USBB_UDDMA3_CONTROL 0x00000338\n#define AVR32_USBB_UDDMA3_CONTROL_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_UDDMA3_CONTROL_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_UDDMA3_CONTROL_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_UDDMA3_CONTROL_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_UDDMA3_CONTROL_BURST_LOCK_EN 7\n#define AVR32_USBB_UDDMA3_CONTROL_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_UDDMA3_CONTROL_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_UDDMA3_CONTROL_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_UDDMA3_CONTROL_CH_BYTE_LENGTH 16\n#define AVR32_USBB_UDDMA3_CONTROL_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_UDDMA3_CONTROL_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_UDDMA3_CONTROL_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_UDDMA3_CONTROL_CH_EN 0\n#define AVR32_USBB_UDDMA3_CONTROL_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UDDMA3_CONTROL_CH_EN_OFFSET 0\n#define AVR32_USBB_UDDMA3_CONTROL_CH_EN_SIZE 1\n#define AVR32_USBB_UDDMA3_CONTROL_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_UDDMA3_CONTROL_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_UDDMA3_CONTROL_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_UDDMA3_CONTROL_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA3_CONTROL_DMAEND_EN 3\n#define AVR32_USBB_UDDMA3_CONTROL_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_UDDMA3_CONTROL_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_UDDMA3_CONTROL_DMAEND_EN_SIZE 1\n#define AVR32_USBB_UDDMA3_CONTROL_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_UDDMA3_CONTROL_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_UDDMA3_CONTROL_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_UDDMA3_CONTROL_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA3_CONTROL_EOT_IRQ_EN 4\n#define AVR32_USBB_UDDMA3_CONTROL_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_UDDMA3_CONTROL_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_UDDMA3_CONTROL_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA3_CONTROL_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_UDDMA3_CONTROL_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_UDDMA3_CONTROL_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_UDDMA3_CONTROL_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_UDDMA3_NEXTDESC 0x00000330\n#define AVR32_USBB_UDDMA3_NEXTDESC_NXT_DESC_ADDR 4\n#define AVR32_USBB_UDDMA3_NEXTDESC_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_UDDMA3_NEXTDESC_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_UDDMA3_NEXTDESC_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_UDDMA3_STATUS 0x0000033c\n#define AVR32_USBB_UDDMA3_STATUS_CH_ACTIVE 1\n#define AVR32_USBB_UDDMA3_STATUS_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_UDDMA3_STATUS_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_UDDMA3_STATUS_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_UDDMA3_STATUS_CH_BYTE_CNT 16\n#define AVR32_USBB_UDDMA3_STATUS_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_UDDMA3_STATUS_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_UDDMA3_STATUS_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_UDDMA3_STATUS_CH_EN 0\n#define AVR32_USBB_UDDMA3_STATUS_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UDDMA3_STATUS_CH_EN_OFFSET 0\n#define AVR32_USBB_UDDMA3_STATUS_CH_EN_SIZE 1\n#define AVR32_USBB_UDDMA3_STATUS_DESC_LD_STA 6\n#define AVR32_USBB_UDDMA3_STATUS_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_UDDMA3_STATUS_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_UDDMA3_STATUS_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_UDDMA3_STATUS_EOCH_BUFF_STA 5\n#define AVR32_USBB_UDDMA3_STATUS_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_UDDMA3_STATUS_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_UDDMA3_STATUS_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_UDDMA3_STATUS_EOT_STA 4\n#define AVR32_USBB_UDDMA3_STATUS_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_UDDMA3_STATUS_EOT_STA_OFFSET 4\n#define AVR32_USBB_UDDMA3_STATUS_EOT_STA_SIZE 1\n#define AVR32_USBB_UDDMA4_ADDR 0x00000344\n#define AVR32_USBB_UDDMA4_ADDR_HSB_ADDR 0\n#define AVR32_USBB_UDDMA4_ADDR_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_UDDMA4_ADDR_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_UDDMA4_ADDR_HSB_ADDR_SIZE 32\n#define AVR32_USBB_UDDMA4_CONTROL 0x00000348\n#define AVR32_USBB_UDDMA4_CONTROL_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_UDDMA4_CONTROL_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_UDDMA4_CONTROL_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_UDDMA4_CONTROL_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_UDDMA4_CONTROL_BURST_LOCK_EN 7\n#define AVR32_USBB_UDDMA4_CONTROL_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_UDDMA4_CONTROL_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_UDDMA4_CONTROL_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_UDDMA4_CONTROL_CH_BYTE_LENGTH 16\n#define AVR32_USBB_UDDMA4_CONTROL_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_UDDMA4_CONTROL_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_UDDMA4_CONTROL_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_UDDMA4_CONTROL_CH_EN 0\n#define AVR32_USBB_UDDMA4_CONTROL_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UDDMA4_CONTROL_CH_EN_OFFSET 0\n#define AVR32_USBB_UDDMA4_CONTROL_CH_EN_SIZE 1\n#define AVR32_USBB_UDDMA4_CONTROL_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_UDDMA4_CONTROL_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_UDDMA4_CONTROL_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_UDDMA4_CONTROL_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA4_CONTROL_DMAEND_EN 3\n#define AVR32_USBB_UDDMA4_CONTROL_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_UDDMA4_CONTROL_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_UDDMA4_CONTROL_DMAEND_EN_SIZE 1\n#define AVR32_USBB_UDDMA4_CONTROL_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_UDDMA4_CONTROL_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_UDDMA4_CONTROL_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_UDDMA4_CONTROL_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA4_CONTROL_EOT_IRQ_EN 4\n#define AVR32_USBB_UDDMA4_CONTROL_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_UDDMA4_CONTROL_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_UDDMA4_CONTROL_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA4_CONTROL_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_UDDMA4_CONTROL_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_UDDMA4_CONTROL_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_UDDMA4_CONTROL_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_UDDMA4_NEXTDESC 0x00000340\n#define AVR32_USBB_UDDMA4_NEXTDESC_NXT_DESC_ADDR 4\n#define AVR32_USBB_UDDMA4_NEXTDESC_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_UDDMA4_NEXTDESC_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_UDDMA4_NEXTDESC_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_UDDMA4_STATUS 0x0000034c\n#define AVR32_USBB_UDDMA4_STATUS_CH_ACTIVE 1\n#define AVR32_USBB_UDDMA4_STATUS_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_UDDMA4_STATUS_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_UDDMA4_STATUS_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_UDDMA4_STATUS_CH_BYTE_CNT 16\n#define AVR32_USBB_UDDMA4_STATUS_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_UDDMA4_STATUS_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_UDDMA4_STATUS_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_UDDMA4_STATUS_CH_EN 0\n#define AVR32_USBB_UDDMA4_STATUS_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UDDMA4_STATUS_CH_EN_OFFSET 0\n#define AVR32_USBB_UDDMA4_STATUS_CH_EN_SIZE 1\n#define AVR32_USBB_UDDMA4_STATUS_DESC_LD_STA 6\n#define AVR32_USBB_UDDMA4_STATUS_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_UDDMA4_STATUS_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_UDDMA4_STATUS_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_UDDMA4_STATUS_EOCH_BUFF_STA 5\n#define AVR32_USBB_UDDMA4_STATUS_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_UDDMA4_STATUS_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_UDDMA4_STATUS_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_UDDMA4_STATUS_EOT_STA 4\n#define AVR32_USBB_UDDMA4_STATUS_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_UDDMA4_STATUS_EOT_STA_OFFSET 4\n#define AVR32_USBB_UDDMA4_STATUS_EOT_STA_SIZE 1\n#define AVR32_USBB_UDDMA5_ADDR 0x00000354\n#define AVR32_USBB_UDDMA5_ADDR_HSB_ADDR 0\n#define AVR32_USBB_UDDMA5_ADDR_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_UDDMA5_ADDR_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_UDDMA5_ADDR_HSB_ADDR_SIZE 32\n#define AVR32_USBB_UDDMA5_CONTROL 0x00000358\n#define AVR32_USBB_UDDMA5_CONTROL_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_UDDMA5_CONTROL_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_UDDMA5_CONTROL_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_UDDMA5_CONTROL_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_UDDMA5_CONTROL_BURST_LOCK_EN 7\n#define AVR32_USBB_UDDMA5_CONTROL_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_UDDMA5_CONTROL_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_UDDMA5_CONTROL_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_UDDMA5_CONTROL_CH_BYTE_LENGTH 16\n#define AVR32_USBB_UDDMA5_CONTROL_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_UDDMA5_CONTROL_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_UDDMA5_CONTROL_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_UDDMA5_CONTROL_CH_EN 0\n#define AVR32_USBB_UDDMA5_CONTROL_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UDDMA5_CONTROL_CH_EN_OFFSET 0\n#define AVR32_USBB_UDDMA5_CONTROL_CH_EN_SIZE 1\n#define AVR32_USBB_UDDMA5_CONTROL_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_UDDMA5_CONTROL_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_UDDMA5_CONTROL_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_UDDMA5_CONTROL_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA5_CONTROL_DMAEND_EN 3\n#define AVR32_USBB_UDDMA5_CONTROL_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_UDDMA5_CONTROL_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_UDDMA5_CONTROL_DMAEND_EN_SIZE 1\n#define AVR32_USBB_UDDMA5_CONTROL_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_UDDMA5_CONTROL_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_UDDMA5_CONTROL_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_UDDMA5_CONTROL_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA5_CONTROL_EOT_IRQ_EN 4\n#define AVR32_USBB_UDDMA5_CONTROL_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_UDDMA5_CONTROL_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_UDDMA5_CONTROL_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA5_CONTROL_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_UDDMA5_CONTROL_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_UDDMA5_CONTROL_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_UDDMA5_CONTROL_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_UDDMA5_NEXTDESC 0x00000350\n#define AVR32_USBB_UDDMA5_NEXTDESC_NXT_DESC_ADDR 4\n#define AVR32_USBB_UDDMA5_NEXTDESC_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_UDDMA5_NEXTDESC_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_UDDMA5_NEXTDESC_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_UDDMA5_STATUS 0x0000035c\n#define AVR32_USBB_UDDMA5_STATUS_CH_ACTIVE 1\n#define AVR32_USBB_UDDMA5_STATUS_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_UDDMA5_STATUS_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_UDDMA5_STATUS_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_UDDMA5_STATUS_CH_BYTE_CNT 16\n#define AVR32_USBB_UDDMA5_STATUS_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_UDDMA5_STATUS_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_UDDMA5_STATUS_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_UDDMA5_STATUS_CH_EN 0\n#define AVR32_USBB_UDDMA5_STATUS_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UDDMA5_STATUS_CH_EN_OFFSET 0\n#define AVR32_USBB_UDDMA5_STATUS_CH_EN_SIZE 1\n#define AVR32_USBB_UDDMA5_STATUS_DESC_LD_STA 6\n#define AVR32_USBB_UDDMA5_STATUS_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_UDDMA5_STATUS_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_UDDMA5_STATUS_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_UDDMA5_STATUS_EOCH_BUFF_STA 5\n#define AVR32_USBB_UDDMA5_STATUS_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_UDDMA5_STATUS_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_UDDMA5_STATUS_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_UDDMA5_STATUS_EOT_STA 4\n#define AVR32_USBB_UDDMA5_STATUS_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_UDDMA5_STATUS_EOT_STA_OFFSET 4\n#define AVR32_USBB_UDDMA5_STATUS_EOT_STA_SIZE 1\n#define AVR32_USBB_UDDMA6_ADDR 0x00000364\n#define AVR32_USBB_UDDMA6_ADDR_HSB_ADDR 0\n#define AVR32_USBB_UDDMA6_ADDR_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_UDDMA6_ADDR_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_UDDMA6_ADDR_HSB_ADDR_SIZE 32\n#define AVR32_USBB_UDDMA6_CONTROL 0x00000368\n#define AVR32_USBB_UDDMA6_CONTROL_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_UDDMA6_CONTROL_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_UDDMA6_CONTROL_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_UDDMA6_CONTROL_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_UDDMA6_CONTROL_BURST_LOCK_EN 7\n#define AVR32_USBB_UDDMA6_CONTROL_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_UDDMA6_CONTROL_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_UDDMA6_CONTROL_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_UDDMA6_CONTROL_CH_BYTE_LENGTH 16\n#define AVR32_USBB_UDDMA6_CONTROL_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_UDDMA6_CONTROL_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_UDDMA6_CONTROL_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_UDDMA6_CONTROL_CH_EN 0\n#define AVR32_USBB_UDDMA6_CONTROL_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UDDMA6_CONTROL_CH_EN_OFFSET 0\n#define AVR32_USBB_UDDMA6_CONTROL_CH_EN_SIZE 1\n#define AVR32_USBB_UDDMA6_CONTROL_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_UDDMA6_CONTROL_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_UDDMA6_CONTROL_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_UDDMA6_CONTROL_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA6_CONTROL_DMAEND_EN 3\n#define AVR32_USBB_UDDMA6_CONTROL_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_UDDMA6_CONTROL_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_UDDMA6_CONTROL_DMAEND_EN_SIZE 1\n#define AVR32_USBB_UDDMA6_CONTROL_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_UDDMA6_CONTROL_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_UDDMA6_CONTROL_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_UDDMA6_CONTROL_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA6_CONTROL_EOT_IRQ_EN 4\n#define AVR32_USBB_UDDMA6_CONTROL_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_UDDMA6_CONTROL_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_UDDMA6_CONTROL_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_UDDMA6_CONTROL_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_UDDMA6_CONTROL_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_UDDMA6_CONTROL_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_UDDMA6_CONTROL_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_UDDMA6_NEXTDESC 0x00000360\n#define AVR32_USBB_UDDMA6_NEXTDESC_NXT_DESC_ADDR 4\n#define AVR32_USBB_UDDMA6_NEXTDESC_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_UDDMA6_NEXTDESC_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_UDDMA6_NEXTDESC_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_UDDMA6_STATUS 0x0000036c\n#define AVR32_USBB_UDDMA6_STATUS_CH_ACTIVE 1\n#define AVR32_USBB_UDDMA6_STATUS_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_UDDMA6_STATUS_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_UDDMA6_STATUS_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_UDDMA6_STATUS_CH_BYTE_CNT 16\n#define AVR32_USBB_UDDMA6_STATUS_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_UDDMA6_STATUS_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_UDDMA6_STATUS_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_UDDMA6_STATUS_CH_EN 0\n#define AVR32_USBB_UDDMA6_STATUS_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UDDMA6_STATUS_CH_EN_OFFSET 0\n#define AVR32_USBB_UDDMA6_STATUS_CH_EN_SIZE 1\n#define AVR32_USBB_UDDMA6_STATUS_DESC_LD_STA 6\n#define AVR32_USBB_UDDMA6_STATUS_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_UDDMA6_STATUS_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_UDDMA6_STATUS_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_UDDMA6_STATUS_EOCH_BUFF_STA 5\n#define AVR32_USBB_UDDMA6_STATUS_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_UDDMA6_STATUS_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_UDDMA6_STATUS_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_UDDMA6_STATUS_EOT_STA 4\n#define AVR32_USBB_UDDMA6_STATUS_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_UDDMA6_STATUS_EOT_STA_OFFSET 4\n#define AVR32_USBB_UDDMA6_STATUS_EOT_STA_SIZE 1\n#define AVR32_USBB_UDFEATURES 0x00000030\n#define AVR32_USBB_UDFEATURES_BYTE_WRITE_DPRAM 15\n#define AVR32_USBB_UDFEATURES_BYTE_WRITE_DPRAM_MASK 0x00008000\n#define AVR32_USBB_UDFEATURES_BYTE_WRITE_DPRAM_OFFSET 15\n#define AVR32_USBB_UDFEATURES_BYTE_WRITE_DPRAM_SIZE 1\n#define AVR32_USBB_UDFEATURES_DATA_BUS_8_16 16\n#define AVR32_USBB_UDFEATURES_DATA_BUS_8_16_MASK 0x00010000\n#define AVR32_USBB_UDFEATURES_DATA_BUS_8_16_OFFSET 16\n#define AVR32_USBB_UDFEATURES_DATA_BUS_8_16_SIZE 1\n#define AVR32_USBB_UDFEATURES_DMA_BUFFER_SIZE 7\n#define AVR32_USBB_UDFEATURES_DMA_BUFFER_SIZE_16_BITS 0x00000000\n#define AVR32_USBB_UDFEATURES_DMA_BUFFER_SIZE_24_BITS 0x00000001\n#define AVR32_USBB_UDFEATURES_DMA_BUFFER_SIZE_MASK 0x00000080\n#define AVR32_USBB_UDFEATURES_DMA_BUFFER_SIZE_OFFSET 7\n#define AVR32_USBB_UDFEATURES_DMA_BUFFER_SIZE_SIZE 1\n#define AVR32_USBB_UDFEATURES_DMA_CHANNEL_NBR 4\n#define AVR32_USBB_UDFEATURES_DMA_CHANNEL_NBR_MASK 0x00000070\n#define AVR32_USBB_UDFEATURES_DMA_CHANNEL_NBR_OFFSET 4\n#define AVR32_USBB_UDFEATURES_DMA_CHANNEL_NBR_SIZE 3\n#define AVR32_USBB_UDFEATURES_DMA_FIFO_WORD_DEPTH 8\n#define AVR32_USBB_UDFEATURES_DMA_FIFO_WORD_DEPTH_MASK 0x00000f00\n#define AVR32_USBB_UDFEATURES_DMA_FIFO_WORD_DEPTH_OFFSET 8\n#define AVR32_USBB_UDFEATURES_DMA_FIFO_WORD_DEPTH_SIZE 4\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_1 17\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_10 26\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_10_MASK 0x04000000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_10_OFFSET 26\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_10_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_11 27\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_11_MASK 0x08000000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_11_OFFSET 27\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_11_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_12 28\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_12_MASK 0x10000000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_12_OFFSET 28\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_12_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_13 29\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_13_MASK 0x20000000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_13_OFFSET 29\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_13_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_14 30\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_14_MASK 0x40000000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_14_OFFSET 30\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_14_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_15 31\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_15_MASK 0x80000000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_15_OFFSET 31\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_15_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_1_MASK 0x00020000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_1_OFFSET 17\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_1_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_2 18\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_2_MASK 0x00040000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_2_OFFSET 18\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_2_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_3 19\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_3_MASK 0x00080000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_3_OFFSET 19\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_3_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_4 20\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_4_MASK 0x00100000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_4_OFFSET 20\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_4_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_5 21\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_5_MASK 0x00200000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_5_OFFSET 21\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_5_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_6 22\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_6_MASK 0x00400000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_6_OFFSET 22\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_6_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_7 23\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_7_MASK 0x00800000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_7_OFFSET 23\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_7_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_8 24\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_8_MASK 0x01000000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_8_OFFSET 24\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_8_SIZE 1\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_9 25\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_9_MASK 0x02000000\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_9_OFFSET 25\n#define AVR32_USBB_UDFEATURES_EN_HIGH_BD_ISO_EPT_9_SIZE 1\n#define AVR32_USBB_UDFEATURES_EPT_NBR_MAX 0\n#define AVR32_USBB_UDFEATURES_EPT_NBR_MAX_MASK 0x0000000f\n#define AVR32_USBB_UDFEATURES_EPT_NBR_MAX_OFFSET 0\n#define AVR32_USBB_UDFEATURES_EPT_NBR_MAX_SIZE 4\n#define AVR32_USBB_UDFEATURES_FIFO_MAX_SIZE 12\n#define AVR32_USBB_UDFEATURES_FIFO_MAX_SIZE_GE_16384 0x00000007\n#define AVR32_USBB_UDFEATURES_FIFO_MAX_SIZE_LT_1024 0x00000002\n#define AVR32_USBB_UDFEATURES_FIFO_MAX_SIZE_LT_16384 0x00000006\n#define AVR32_USBB_UDFEATURES_FIFO_MAX_SIZE_LT_2048 0x00000003\n#define AVR32_USBB_UDFEATURES_FIFO_MAX_SIZE_LT_256 0x00000000\n#define AVR32_USBB_UDFEATURES_FIFO_MAX_SIZE_LT_4096 0x00000004\n#define AVR32_USBB_UDFEATURES_FIFO_MAX_SIZE_LT_512 0x00000001\n#define AVR32_USBB_UDFEATURES_FIFO_MAX_SIZE_LT_8192 0x00000005\n#define AVR32_USBB_UDFEATURES_FIFO_MAX_SIZE_MASK 0x00007000\n#define AVR32_USBB_UDFEATURES_FIFO_MAX_SIZE_OFFSET 12\n#define AVR32_USBB_UDFEATURES_FIFO_MAX_SIZE_SIZE 3\n#define AVR32_USBB_UDFNUM 0x00000020\n#define AVR32_USBB_UDFNUM_FNCERR 15\n#define AVR32_USBB_UDFNUM_FNCERR_MASK 0x00008000\n#define AVR32_USBB_UDFNUM_FNCERR_OFFSET 15\n#define AVR32_USBB_UDFNUM_FNCERR_SIZE 1\n#define AVR32_USBB_UDFNUM_FNUM 3\n#define AVR32_USBB_UDFNUM_FNUM_MASK 0x00003ff8\n#define AVR32_USBB_UDFNUM_FNUM_OFFSET 3\n#define AVR32_USBB_UDFNUM_FNUM_SIZE 11\n#define AVR32_USBB_UDFNUM_MFNUM 0\n#define AVR32_USBB_UDFNUM_MFNUM_MASK 0x00000007\n#define AVR32_USBB_UDFNUM_MFNUM_OFFSET 0\n#define AVR32_USBB_UDFNUM_MFNUM_SIZE 3\n#define AVR32_USBB_UDINT 0x00000004\n#define AVR32_USBB_UDINTCLR 0x00000008\n#define AVR32_USBB_UDINTCLR_EORSMC 5\n#define AVR32_USBB_UDINTCLR_EORSMC_MASK 0x00000020\n#define AVR32_USBB_UDINTCLR_EORSMC_OFFSET 5\n#define AVR32_USBB_UDINTCLR_EORSMC_SIZE 1\n#define AVR32_USBB_UDINTCLR_EORSTC 3\n#define AVR32_USBB_UDINTCLR_EORSTC_MASK 0x00000008\n#define AVR32_USBB_UDINTCLR_EORSTC_OFFSET 3\n#define AVR32_USBB_UDINTCLR_EORSTC_SIZE 1\n#define AVR32_USBB_UDINTCLR_MSOFC 1\n#define AVR32_USBB_UDINTCLR_MSOFC_MASK 0x00000002\n#define AVR32_USBB_UDINTCLR_MSOFC_OFFSET 1\n#define AVR32_USBB_UDINTCLR_MSOFC_SIZE 1\n#define AVR32_USBB_UDINTCLR_SOFC 2\n#define AVR32_USBB_UDINTCLR_SOFC_MASK 0x00000004\n#define AVR32_USBB_UDINTCLR_SOFC_OFFSET 2\n#define AVR32_USBB_UDINTCLR_SOFC_SIZE 1\n#define AVR32_USBB_UDINTCLR_SUSPC 0\n#define AVR32_USBB_UDINTCLR_SUSPC_MASK 0x00000001\n#define AVR32_USBB_UDINTCLR_SUSPC_OFFSET 0\n#define AVR32_USBB_UDINTCLR_SUSPC_SIZE 1\n#define AVR32_USBB_UDINTCLR_UPRSMC 6\n#define AVR32_USBB_UDINTCLR_UPRSMC_MASK 0x00000040\n#define AVR32_USBB_UDINTCLR_UPRSMC_OFFSET 6\n#define AVR32_USBB_UDINTCLR_UPRSMC_SIZE 1\n#define AVR32_USBB_UDINTCLR_VBUSTIC 7\n#define AVR32_USBB_UDINTCLR_VBUSTIC_MASK 0x00000080\n#define AVR32_USBB_UDINTCLR_VBUSTIC_OFFSET 7\n#define AVR32_USBB_UDINTCLR_VBUSTIC_SIZE 1\n#define AVR32_USBB_UDINTCLR_WAKEUPC 4\n#define AVR32_USBB_UDINTCLR_WAKEUPC_MASK 0x00000010\n#define AVR32_USBB_UDINTCLR_WAKEUPC_OFFSET 4\n#define AVR32_USBB_UDINTCLR_WAKEUPC_SIZE 1\n#define AVR32_USBB_UDINTE 0x00000010\n#define AVR32_USBB_UDINTECLR 0x00000014\n#define AVR32_USBB_UDINTECLR_DAM6INTEC 30\n#define AVR32_USBB_UDINTECLR_DAM6INTEC_MASK 0x40000000\n#define AVR32_USBB_UDINTECLR_DAM6INTEC_OFFSET 30\n#define AVR32_USBB_UDINTECLR_DAM6INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_DMA1INTEC 25\n#define AVR32_USBB_UDINTECLR_DMA1INTEC_MASK 0x02000000\n#define AVR32_USBB_UDINTECLR_DMA1INTEC_OFFSET 25\n#define AVR32_USBB_UDINTECLR_DMA1INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_DMA2INTEC 26\n#define AVR32_USBB_UDINTECLR_DMA2INTEC_MASK 0x04000000\n#define AVR32_USBB_UDINTECLR_DMA2INTEC_OFFSET 26\n#define AVR32_USBB_UDINTECLR_DMA2INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_DMA3INTEC 27\n#define AVR32_USBB_UDINTECLR_DMA3INTEC_MASK 0x08000000\n#define AVR32_USBB_UDINTECLR_DMA3INTEC_OFFSET 27\n#define AVR32_USBB_UDINTECLR_DMA3INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_DMA4INTEC 28\n#define AVR32_USBB_UDINTECLR_DMA4INTEC_MASK 0x10000000\n#define AVR32_USBB_UDINTECLR_DMA4INTEC_OFFSET 28\n#define AVR32_USBB_UDINTECLR_DMA4INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_DMA5INTEC 29\n#define AVR32_USBB_UDINTECLR_DMA5INTEC_MASK 0x20000000\n#define AVR32_USBB_UDINTECLR_DMA5INTEC_OFFSET 29\n#define AVR32_USBB_UDINTECLR_DMA5INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_EORSMEC 5\n#define AVR32_USBB_UDINTECLR_EORSMEC_MASK 0x00000020\n#define AVR32_USBB_UDINTECLR_EORSMEC_OFFSET 5\n#define AVR32_USBB_UDINTECLR_EORSMEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_EORSTEC 3\n#define AVR32_USBB_UDINTECLR_EORSTEC_MASK 0x00000008\n#define AVR32_USBB_UDINTECLR_EORSTEC_OFFSET 3\n#define AVR32_USBB_UDINTECLR_EORSTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_EP0INTEC 12\n#define AVR32_USBB_UDINTECLR_EP0INTEC_MASK 0x00001000\n#define AVR32_USBB_UDINTECLR_EP0INTEC_OFFSET 12\n#define AVR32_USBB_UDINTECLR_EP0INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_EP1INTEC 13\n#define AVR32_USBB_UDINTECLR_EP1INTEC_MASK 0x00002000\n#define AVR32_USBB_UDINTECLR_EP1INTEC_OFFSET 13\n#define AVR32_USBB_UDINTECLR_EP1INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_EP2INTEC 14\n#define AVR32_USBB_UDINTECLR_EP2INTEC_MASK 0x00004000\n#define AVR32_USBB_UDINTECLR_EP2INTEC_OFFSET 14\n#define AVR32_USBB_UDINTECLR_EP2INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_EP3INTEC 15\n#define AVR32_USBB_UDINTECLR_EP3INTEC_MASK 0x00008000\n#define AVR32_USBB_UDINTECLR_EP3INTEC_OFFSET 15\n#define AVR32_USBB_UDINTECLR_EP3INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_EP4INTEC 16\n#define AVR32_USBB_UDINTECLR_EP4INTEC_MASK 0x00010000\n#define AVR32_USBB_UDINTECLR_EP4INTEC_OFFSET 16\n#define AVR32_USBB_UDINTECLR_EP4INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_EP5INTEC 17\n#define AVR32_USBB_UDINTECLR_EP5INTEC_MASK 0x00020000\n#define AVR32_USBB_UDINTECLR_EP5INTEC_OFFSET 17\n#define AVR32_USBB_UDINTECLR_EP5INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_EP6INTEC 18\n#define AVR32_USBB_UDINTECLR_EP6INTEC_MASK 0x00040000\n#define AVR32_USBB_UDINTECLR_EP6INTEC_OFFSET 18\n#define AVR32_USBB_UDINTECLR_EP6INTEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_MSOFEC 1\n#define AVR32_USBB_UDINTECLR_MSOFEC_MASK 0x00000002\n#define AVR32_USBB_UDINTECLR_MSOFEC_OFFSET 1\n#define AVR32_USBB_UDINTECLR_MSOFEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_SOFEC 2\n#define AVR32_USBB_UDINTECLR_SOFEC_MASK 0x00000004\n#define AVR32_USBB_UDINTECLR_SOFEC_OFFSET 2\n#define AVR32_USBB_UDINTECLR_SOFEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_SUSPEC 0\n#define AVR32_USBB_UDINTECLR_SUSPEC_MASK 0x00000001\n#define AVR32_USBB_UDINTECLR_SUSPEC_OFFSET 0\n#define AVR32_USBB_UDINTECLR_SUSPEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_UPRSMEC 6\n#define AVR32_USBB_UDINTECLR_UPRSMEC_MASK 0x00000040\n#define AVR32_USBB_UDINTECLR_UPRSMEC_OFFSET 6\n#define AVR32_USBB_UDINTECLR_UPRSMEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_VBUSEC 7\n#define AVR32_USBB_UDINTECLR_VBUSEC_MASK 0x00000080\n#define AVR32_USBB_UDINTECLR_VBUSEC_OFFSET 7\n#define AVR32_USBB_UDINTECLR_VBUSEC_SIZE 1\n#define AVR32_USBB_UDINTECLR_WAKEUPEC 4\n#define AVR32_USBB_UDINTECLR_WAKEUPEC_MASK 0x00000010\n#define AVR32_USBB_UDINTECLR_WAKEUPEC_OFFSET 4\n#define AVR32_USBB_UDINTECLR_WAKEUPEC_SIZE 1\n#define AVR32_USBB_UDINTESET 0x00000018\n#define AVR32_USBB_UDINTESET_DMA1INTES 25\n#define AVR32_USBB_UDINTESET_DMA1INTES_MASK 0x02000000\n#define AVR32_USBB_UDINTESET_DMA1INTES_OFFSET 25\n#define AVR32_USBB_UDINTESET_DMA1INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_DMA2INTES 26\n#define AVR32_USBB_UDINTESET_DMA2INTES_MASK 0x04000000\n#define AVR32_USBB_UDINTESET_DMA2INTES_OFFSET 26\n#define AVR32_USBB_UDINTESET_DMA2INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_DMA3INTES 27\n#define AVR32_USBB_UDINTESET_DMA3INTES_MASK 0x08000000\n#define AVR32_USBB_UDINTESET_DMA3INTES_OFFSET 27\n#define AVR32_USBB_UDINTESET_DMA3INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_DMA4INTES 28\n#define AVR32_USBB_UDINTESET_DMA4INTES_MASK 0x10000000\n#define AVR32_USBB_UDINTESET_DMA4INTES_OFFSET 28\n#define AVR32_USBB_UDINTESET_DMA4INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_DMA5INTES 29\n#define AVR32_USBB_UDINTESET_DMA5INTES_MASK 0x20000000\n#define AVR32_USBB_UDINTESET_DMA5INTES_OFFSET 29\n#define AVR32_USBB_UDINTESET_DMA5INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_DMA6INTES 30\n#define AVR32_USBB_UDINTESET_DMA6INTES_MASK 0x40000000\n#define AVR32_USBB_UDINTESET_DMA6INTES_OFFSET 30\n#define AVR32_USBB_UDINTESET_DMA6INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_EORSMES 5\n#define AVR32_USBB_UDINTESET_EORSMES_MASK 0x00000020\n#define AVR32_USBB_UDINTESET_EORSMES_OFFSET 5\n#define AVR32_USBB_UDINTESET_EORSMES_SIZE 1\n#define AVR32_USBB_UDINTESET_EORSTES 3\n#define AVR32_USBB_UDINTESET_EORSTES_MASK 0x00000008\n#define AVR32_USBB_UDINTESET_EORSTES_OFFSET 3\n#define AVR32_USBB_UDINTESET_EORSTES_SIZE 1\n#define AVR32_USBB_UDINTESET_EP0INTES 12\n#define AVR32_USBB_UDINTESET_EP0INTES_MASK 0x00001000\n#define AVR32_USBB_UDINTESET_EP0INTES_OFFSET 12\n#define AVR32_USBB_UDINTESET_EP0INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_EP1INTES 13\n#define AVR32_USBB_UDINTESET_EP1INTES_MASK 0x00002000\n#define AVR32_USBB_UDINTESET_EP1INTES_OFFSET 13\n#define AVR32_USBB_UDINTESET_EP1INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_EP2INTES 14\n#define AVR32_USBB_UDINTESET_EP2INTES_MASK 0x00004000\n#define AVR32_USBB_UDINTESET_EP2INTES_OFFSET 14\n#define AVR32_USBB_UDINTESET_EP2INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_EP3INTES 15\n#define AVR32_USBB_UDINTESET_EP3INTES_MASK 0x00008000\n#define AVR32_USBB_UDINTESET_EP3INTES_OFFSET 15\n#define AVR32_USBB_UDINTESET_EP3INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_EP4INTES 16\n#define AVR32_USBB_UDINTESET_EP4INTES_MASK 0x00010000\n#define AVR32_USBB_UDINTESET_EP4INTES_OFFSET 16\n#define AVR32_USBB_UDINTESET_EP4INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_EP5INTES 17\n#define AVR32_USBB_UDINTESET_EP5INTES_MASK 0x00020000\n#define AVR32_USBB_UDINTESET_EP5INTES_OFFSET 17\n#define AVR32_USBB_UDINTESET_EP5INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_EP6INTES 18\n#define AVR32_USBB_UDINTESET_EP6INTES_MASK 0x00040000\n#define AVR32_USBB_UDINTESET_EP6INTES_OFFSET 18\n#define AVR32_USBB_UDINTESET_EP6INTES_SIZE 1\n#define AVR32_USBB_UDINTESET_MSOFES 1\n#define AVR32_USBB_UDINTESET_MSOFES_MASK 0x00000002\n#define AVR32_USBB_UDINTESET_MSOFES_OFFSET 1\n#define AVR32_USBB_UDINTESET_MSOFES_SIZE 1\n#define AVR32_USBB_UDINTESET_SOFES 2\n#define AVR32_USBB_UDINTESET_SOFES_MASK 0x00000004\n#define AVR32_USBB_UDINTESET_SOFES_OFFSET 2\n#define AVR32_USBB_UDINTESET_SOFES_SIZE 1\n#define AVR32_USBB_UDINTESET_SUSPES 0\n#define AVR32_USBB_UDINTESET_SUSPES_MASK 0x00000001\n#define AVR32_USBB_UDINTESET_SUSPES_OFFSET 0\n#define AVR32_USBB_UDINTESET_SUSPES_SIZE 1\n#define AVR32_USBB_UDINTESET_UPRSMES 6\n#define AVR32_USBB_UDINTESET_UPRSMES_MASK 0x00000040\n#define AVR32_USBB_UDINTESET_UPRSMES_OFFSET 6\n#define AVR32_USBB_UDINTESET_UPRSMES_SIZE 1\n#define AVR32_USBB_UDINTESET_VBUSES 7\n#define AVR32_USBB_UDINTESET_VBUSES_MASK 0x00000080\n#define AVR32_USBB_UDINTESET_VBUSES_OFFSET 7\n#define AVR32_USBB_UDINTESET_VBUSES_SIZE 1\n#define AVR32_USBB_UDINTESET_WAKEUPES 4\n#define AVR32_USBB_UDINTESET_WAKEUPES_MASK 0x00000010\n#define AVR32_USBB_UDINTESET_WAKEUPES_OFFSET 4\n#define AVR32_USBB_UDINTESET_WAKEUPES_SIZE 1\n#define AVR32_USBB_UDINTE_DMA1INTE 25\n#define AVR32_USBB_UDINTE_DMA1INTE_MASK 0x02000000\n#define AVR32_USBB_UDINTE_DMA1INTE_OFFSET 25\n#define AVR32_USBB_UDINTE_DMA1INTE_SIZE 1\n#define AVR32_USBB_UDINTE_DMA2INTE 26\n#define AVR32_USBB_UDINTE_DMA2INTE_MASK 0x04000000\n#define AVR32_USBB_UDINTE_DMA2INTE_OFFSET 26\n#define AVR32_USBB_UDINTE_DMA2INTE_SIZE 1\n#define AVR32_USBB_UDINTE_DMA3INTE 27\n#define AVR32_USBB_UDINTE_DMA3INTE_MASK 0x08000000\n#define AVR32_USBB_UDINTE_DMA3INTE_OFFSET 27\n#define AVR32_USBB_UDINTE_DMA3INTE_SIZE 1\n#define AVR32_USBB_UDINTE_DMA4INTE 28\n#define AVR32_USBB_UDINTE_DMA4INTE_MASK 0x10000000\n#define AVR32_USBB_UDINTE_DMA4INTE_OFFSET 28\n#define AVR32_USBB_UDINTE_DMA4INTE_SIZE 1\n#define AVR32_USBB_UDINTE_DMA5INTE 29\n#define AVR32_USBB_UDINTE_DMA5INTE_MASK 0x20000000\n#define AVR32_USBB_UDINTE_DMA5INTE_OFFSET 29\n#define AVR32_USBB_UDINTE_DMA5INTE_SIZE 1\n#define AVR32_USBB_UDINTE_DMA6INTE 30\n#define AVR32_USBB_UDINTE_DMA6INTE_MASK 0x40000000\n#define AVR32_USBB_UDINTE_DMA6INTE_OFFSET 30\n#define AVR32_USBB_UDINTE_DMA6INTE_SIZE 1\n#define AVR32_USBB_UDINTE_EORSME 5\n#define AVR32_USBB_UDINTE_EORSME_MASK 0x00000020\n#define AVR32_USBB_UDINTE_EORSME_OFFSET 5\n#define AVR32_USBB_UDINTE_EORSME_SIZE 1\n#define AVR32_USBB_UDINTE_EORSTE 3\n#define AVR32_USBB_UDINTE_EORSTE_MASK 0x00000008\n#define AVR32_USBB_UDINTE_EORSTE_OFFSET 3\n#define AVR32_USBB_UDINTE_EORSTE_SIZE 1\n#define AVR32_USBB_UDINTE_EP0INTE 12\n#define AVR32_USBB_UDINTE_EP0INTE_MASK 0x00001000\n#define AVR32_USBB_UDINTE_EP0INTE_OFFSET 12\n#define AVR32_USBB_UDINTE_EP0INTE_SIZE 1\n#define AVR32_USBB_UDINTE_EP1INTE 13\n#define AVR32_USBB_UDINTE_EP1INTE_MASK 0x00002000\n#define AVR32_USBB_UDINTE_EP1INTE_OFFSET 13\n#define AVR32_USBB_UDINTE_EP1INTE_SIZE 1\n#define AVR32_USBB_UDINTE_EP2INTE 14\n#define AVR32_USBB_UDINTE_EP2INTE_MASK 0x00004000\n#define AVR32_USBB_UDINTE_EP2INTE_OFFSET 14\n#define AVR32_USBB_UDINTE_EP2INTE_SIZE 1\n#define AVR32_USBB_UDINTE_EP3INTE 15\n#define AVR32_USBB_UDINTE_EP3INTE_MASK 0x00008000\n#define AVR32_USBB_UDINTE_EP3INTE_OFFSET 15\n#define AVR32_USBB_UDINTE_EP3INTE_SIZE 1\n#define AVR32_USBB_UDINTE_EP4INTE 16\n#define AVR32_USBB_UDINTE_EP4INTE_MASK 0x00010000\n#define AVR32_USBB_UDINTE_EP4INTE_OFFSET 16\n#define AVR32_USBB_UDINTE_EP4INTE_SIZE 1\n#define AVR32_USBB_UDINTE_EP5INTE 17\n#define AVR32_USBB_UDINTE_EP5INTE_MASK 0x00020000\n#define AVR32_USBB_UDINTE_EP5INTE_OFFSET 17\n#define AVR32_USBB_UDINTE_EP5INTE_SIZE 1\n#define AVR32_USBB_UDINTE_EP6INTE 18\n#define AVR32_USBB_UDINTE_EP6INTE_MASK 0x00040000\n#define AVR32_USBB_UDINTE_EP6INTE_OFFSET 18\n#define AVR32_USBB_UDINTE_EP6INTE_SIZE 1\n#define AVR32_USBB_UDINTE_MSOFE 1\n#define AVR32_USBB_UDINTE_MSOFE_MASK 0x00000002\n#define AVR32_USBB_UDINTE_MSOFE_OFFSET 1\n#define AVR32_USBB_UDINTE_MSOFE_SIZE 1\n#define AVR32_USBB_UDINTE_SOFE 2\n#define AVR32_USBB_UDINTE_SOFE_MASK 0x00000004\n#define AVR32_USBB_UDINTE_SOFE_OFFSET 2\n#define AVR32_USBB_UDINTE_SOFE_SIZE 1\n#define AVR32_USBB_UDINTE_SUSPE 0\n#define AVR32_USBB_UDINTE_SUSPE_MASK 0x00000001\n#define AVR32_USBB_UDINTE_SUSPE_OFFSET 0\n#define AVR32_USBB_UDINTE_SUSPE_SIZE 1\n#define AVR32_USBB_UDINTE_UPRSME 6\n#define AVR32_USBB_UDINTE_UPRSME_MASK 0x00000040\n#define AVR32_USBB_UDINTE_UPRSME_OFFSET 6\n#define AVR32_USBB_UDINTE_UPRSME_SIZE 1\n#define AVR32_USBB_UDINTE_VBUSE 7\n#define AVR32_USBB_UDINTE_VBUSE_MASK 0x00000080\n#define AVR32_USBB_UDINTE_VBUSE_OFFSET 7\n#define AVR32_USBB_UDINTE_VBUSE_SIZE 1\n#define AVR32_USBB_UDINTE_WAKEUPE 4\n#define AVR32_USBB_UDINTE_WAKEUPE_MASK 0x00000010\n#define AVR32_USBB_UDINTE_WAKEUPE_OFFSET 4\n#define AVR32_USBB_UDINTE_WAKEUPE_SIZE 1\n#define AVR32_USBB_UDINTSET 0x0000000c\n#define AVR32_USBB_UDINTSET_DMA1INTS 25\n#define AVR32_USBB_UDINTSET_DMA1INTS_MASK 0x02000000\n#define AVR32_USBB_UDINTSET_DMA1INTS_OFFSET 25\n#define AVR32_USBB_UDINTSET_DMA1INTS_SIZE 1\n#define AVR32_USBB_UDINTSET_DMA2INTS 26\n#define AVR32_USBB_UDINTSET_DMA2INTS_MASK 0x04000000\n#define AVR32_USBB_UDINTSET_DMA2INTS_OFFSET 26\n#define AVR32_USBB_UDINTSET_DMA2INTS_SIZE 1\n#define AVR32_USBB_UDINTSET_DMA3INTS 27\n#define AVR32_USBB_UDINTSET_DMA3INTS_MASK 0x08000000\n#define AVR32_USBB_UDINTSET_DMA3INTS_OFFSET 27\n#define AVR32_USBB_UDINTSET_DMA3INTS_SIZE 1\n#define AVR32_USBB_UDINTSET_DMA4INTS 28\n#define AVR32_USBB_UDINTSET_DMA4INTS_MASK 0x10000000\n#define AVR32_USBB_UDINTSET_DMA4INTS_OFFSET 28\n#define AVR32_USBB_UDINTSET_DMA4INTS_SIZE 1\n#define AVR32_USBB_UDINTSET_DMA5INTS 29\n#define AVR32_USBB_UDINTSET_DMA5INTS_MASK 0x20000000\n#define AVR32_USBB_UDINTSET_DMA5INTS_OFFSET 29\n#define AVR32_USBB_UDINTSET_DMA5INTS_SIZE 1\n#define AVR32_USBB_UDINTSET_DMA6INTS 30\n#define AVR32_USBB_UDINTSET_DMA6INTS_MASK 0x40000000\n#define AVR32_USBB_UDINTSET_DMA6INTS_OFFSET 30\n#define AVR32_USBB_UDINTSET_DMA6INTS_SIZE 1\n#define AVR32_USBB_UDINTSET_EORSMS 5\n#define AVR32_USBB_UDINTSET_EORSMS_MASK 0x00000020\n#define AVR32_USBB_UDINTSET_EORSMS_OFFSET 5\n#define AVR32_USBB_UDINTSET_EORSMS_SIZE 1\n#define AVR32_USBB_UDINTSET_EORSTS 3\n#define AVR32_USBB_UDINTSET_EORSTS_MASK 0x00000008\n#define AVR32_USBB_UDINTSET_EORSTS_OFFSET 3\n#define AVR32_USBB_UDINTSET_EORSTS_SIZE 1\n#define AVR32_USBB_UDINTSET_MSOFS 1\n#define AVR32_USBB_UDINTSET_MSOFS_MASK 0x00000002\n#define AVR32_USBB_UDINTSET_MSOFS_OFFSET 1\n#define AVR32_USBB_UDINTSET_MSOFS_SIZE 1\n#define AVR32_USBB_UDINTSET_SOFS 2\n#define AVR32_USBB_UDINTSET_SOFS_MASK 0x00000004\n#define AVR32_USBB_UDINTSET_SOFS_OFFSET 2\n#define AVR32_USBB_UDINTSET_SOFS_SIZE 1\n#define AVR32_USBB_UDINTSET_SUSPS 0\n#define AVR32_USBB_UDINTSET_SUSPS_MASK 0x00000001\n#define AVR32_USBB_UDINTSET_SUSPS_OFFSET 0\n#define AVR32_USBB_UDINTSET_SUSPS_SIZE 1\n#define AVR32_USBB_UDINTSET_UPRSMS 6\n#define AVR32_USBB_UDINTSET_UPRSMS_MASK 0x00000040\n#define AVR32_USBB_UDINTSET_UPRSMS_OFFSET 6\n#define AVR32_USBB_UDINTSET_UPRSMS_SIZE 1\n#define AVR32_USBB_UDINTSET_VBUSTIS 7\n#define AVR32_USBB_UDINTSET_VBUSTIS_MASK 0x00000080\n#define AVR32_USBB_UDINTSET_VBUSTIS_OFFSET 7\n#define AVR32_USBB_UDINTSET_VBUSTIS_SIZE 1\n#define AVR32_USBB_UDINTSET_WAKEUPS 4\n#define AVR32_USBB_UDINTSET_WAKEUPS_MASK 0x00000010\n#define AVR32_USBB_UDINTSET_WAKEUPS_OFFSET 4\n#define AVR32_USBB_UDINTSET_WAKEUPS_SIZE 1\n#define AVR32_USBB_UDINT_CLKUSABLE 10\n#define AVR32_USBB_UDINT_CLKUSABLE_MASK 0x00000400\n#define AVR32_USBB_UDINT_CLKUSABLE_OFFSET 10\n#define AVR32_USBB_UDINT_CLKUSABLE_SIZE 1\n#define AVR32_USBB_UDINT_DMA1INT 25\n#define AVR32_USBB_UDINT_DMA1INT_MASK 0x02000000\n#define AVR32_USBB_UDINT_DMA1INT_OFFSET 25\n#define AVR32_USBB_UDINT_DMA1INT_SIZE 1\n#define AVR32_USBB_UDINT_DMA2INT 26\n#define AVR32_USBB_UDINT_DMA2INT_MASK 0x04000000\n#define AVR32_USBB_UDINT_DMA2INT_OFFSET 26\n#define AVR32_USBB_UDINT_DMA2INT_SIZE 1\n#define AVR32_USBB_UDINT_DMA3INT 27\n#define AVR32_USBB_UDINT_DMA3INT_MASK 0x08000000\n#define AVR32_USBB_UDINT_DMA3INT_OFFSET 27\n#define AVR32_USBB_UDINT_DMA3INT_SIZE 1\n#define AVR32_USBB_UDINT_DMA4INT 28\n#define AVR32_USBB_UDINT_DMA4INT_MASK 0x10000000\n#define AVR32_USBB_UDINT_DMA4INT_OFFSET 28\n#define AVR32_USBB_UDINT_DMA4INT_SIZE 1\n#define AVR32_USBB_UDINT_DMA5INT 29\n#define AVR32_USBB_UDINT_DMA5INT_MASK 0x20000000\n#define AVR32_USBB_UDINT_DMA5INT_OFFSET 29\n#define AVR32_USBB_UDINT_DMA5INT_SIZE 1\n#define AVR32_USBB_UDINT_DMA6INT 30\n#define AVR32_USBB_UDINT_DMA6INT_MASK 0x40000000\n#define AVR32_USBB_UDINT_DMA6INT_OFFSET 30\n#define AVR32_USBB_UDINT_DMA6INT_SIZE 1\n#define AVR32_USBB_UDINT_EORSM 5\n#define AVR32_USBB_UDINT_EORSM_MASK 0x00000020\n#define AVR32_USBB_UDINT_EORSM_OFFSET 5\n#define AVR32_USBB_UDINT_EORSM_SIZE 1\n#define AVR32_USBB_UDINT_EORST 3\n#define AVR32_USBB_UDINT_EORST_MASK 0x00000008\n#define AVR32_USBB_UDINT_EORST_OFFSET 3\n#define AVR32_USBB_UDINT_EORST_SIZE 1\n#define AVR32_USBB_UDINT_EP0INT 12\n#define AVR32_USBB_UDINT_EP0INT_MASK 0x00001000\n#define AVR32_USBB_UDINT_EP0INT_OFFSET 12\n#define AVR32_USBB_UDINT_EP0INT_SIZE 1\n#define AVR32_USBB_UDINT_EP1INT 13\n#define AVR32_USBB_UDINT_EP1INT_MASK 0x00002000\n#define AVR32_USBB_UDINT_EP1INT_OFFSET 13\n#define AVR32_USBB_UDINT_EP1INT_SIZE 1\n#define AVR32_USBB_UDINT_EP2INT 14\n#define AVR32_USBB_UDINT_EP2INT_MASK 0x00004000\n#define AVR32_USBB_UDINT_EP2INT_OFFSET 14\n#define AVR32_USBB_UDINT_EP2INT_SIZE 1\n#define AVR32_USBB_UDINT_EP3INT 15\n#define AVR32_USBB_UDINT_EP3INT_MASK 0x00008000\n#define AVR32_USBB_UDINT_EP3INT_OFFSET 15\n#define AVR32_USBB_UDINT_EP3INT_SIZE 1\n#define AVR32_USBB_UDINT_EP4INT 16\n#define AVR32_USBB_UDINT_EP4INT_MASK 0x00010000\n#define AVR32_USBB_UDINT_EP4INT_OFFSET 16\n#define AVR32_USBB_UDINT_EP4INT_SIZE 1\n#define AVR32_USBB_UDINT_EP5INT 17\n#define AVR32_USBB_UDINT_EP5INT_MASK 0x00020000\n#define AVR32_USBB_UDINT_EP5INT_OFFSET 17\n#define AVR32_USBB_UDINT_EP5INT_SIZE 1\n#define AVR32_USBB_UDINT_EP6INT 18\n#define AVR32_USBB_UDINT_EP6INT_MASK 0x00040000\n#define AVR32_USBB_UDINT_EP6INT_OFFSET 18\n#define AVR32_USBB_UDINT_EP6INT_SIZE 1\n#define AVR32_USBB_UDINT_MSOF 1\n#define AVR32_USBB_UDINT_MSOF_MASK 0x00000002\n#define AVR32_USBB_UDINT_MSOF_OFFSET 1\n#define AVR32_USBB_UDINT_MSOF_SIZE 1\n#define AVR32_USBB_UDINT_SOF 2\n#define AVR32_USBB_UDINT_SOF_MASK 0x00000004\n#define AVR32_USBB_UDINT_SOF_OFFSET 2\n#define AVR32_USBB_UDINT_SOF_SIZE 1\n#define AVR32_USBB_UDINT_SPEED 9\n#define AVR32_USBB_UDINT_SPEED_MASK 0x00000200\n#define AVR32_USBB_UDINT_SPEED_OFFSET 9\n#define AVR32_USBB_UDINT_SPEED_SIZE 1\n#define AVR32_USBB_UDINT_SUSP 0\n#define AVR32_USBB_UDINT_SUSP_MASK 0x00000001\n#define AVR32_USBB_UDINT_SUSP_OFFSET 0\n#define AVR32_USBB_UDINT_SUSP_SIZE 1\n#define AVR32_USBB_UDINT_UPRSM 6\n#define AVR32_USBB_UDINT_UPRSM_MASK 0x00000040\n#define AVR32_USBB_UDINT_UPRSM_OFFSET 6\n#define AVR32_USBB_UDINT_UPRSM_SIZE 1\n#define AVR32_USBB_UDINT_VBUS 8\n#define AVR32_USBB_UDINT_VBUSTI 7\n#define AVR32_USBB_UDINT_VBUSTI_MASK 0x00000080\n#define AVR32_USBB_UDINT_VBUSTI_OFFSET 7\n#define AVR32_USBB_UDINT_VBUSTI_SIZE 1\n#define AVR32_USBB_UDINT_VBUS_MASK 0x00000100\n#define AVR32_USBB_UDINT_VBUS_OFFSET 8\n#define AVR32_USBB_UDINT_VBUS_SIZE 1\n#define AVR32_USBB_UDINT_WAKEUP 4\n#define AVR32_USBB_UDINT_WAKEUP_MASK 0x00000010\n#define AVR32_USBB_UDINT_WAKEUP_OFFSET 4\n#define AVR32_USBB_UDINT_WAKEUP_SIZE 1\n#define AVR32_USBB_UDNAME1 0x00000038\n#define AVR32_USBB_UDNAME2 0x0000003c\n#define AVR32_USBB_UDTST1 0x00000024\n#define AVR32_USBB_UDTST1_COUNTERA 0\n#define AVR32_USBB_UDTST1_COUNTERA_MASK 0x00007fff\n#define AVR32_USBB_UDTST1_COUNTERA_OFFSET 0\n#define AVR32_USBB_UDTST1_COUNTERA_SIZE 15\n#define AVR32_USBB_UDTST1_COUNTERB 16\n#define AVR32_USBB_UDTST1_COUNTERB_MASK 0x003f0000\n#define AVR32_USBB_UDTST1_COUNTERB_OFFSET 16\n#define AVR32_USBB_UDTST1_COUNTERB_SIZE 6\n#define AVR32_USBB_UDTST1_LOADCNTA 15\n#define AVR32_USBB_UDTST1_LOADCNTA_MASK 0x00008000\n#define AVR32_USBB_UDTST1_LOADCNTA_OFFSET 15\n#define AVR32_USBB_UDTST1_LOADCNTA_SIZE 1\n#define AVR32_USBB_UDTST1_LOADCNTB 23\n#define AVR32_USBB_UDTST1_LOADCNTB_MASK 0x00800000\n#define AVR32_USBB_UDTST1_LOADCNTB_OFFSET 23\n#define AVR32_USBB_UDTST1_LOADCNTB_SIZE 1\n#define AVR32_USBB_UDTST1_LOADSOFCNT 31\n#define AVR32_USBB_UDTST1_LOADSOFCNT_MASK 0x80000000\n#define AVR32_USBB_UDTST1_LOADSOFCNT_OFFSET 31\n#define AVR32_USBB_UDTST1_LOADSOFCNT_SIZE 1\n#define AVR32_USBB_UDTST1_SOFCNTMAX 24\n#define AVR32_USBB_UDTST1_SOFCNTMAX_MASK 0x7f000000\n#define AVR32_USBB_UDTST1_SOFCNTMAX_OFFSET 24\n#define AVR32_USBB_UDTST1_SOFCNTMAX_SIZE 7\n#define AVR32_USBB_UDTST2 0x00000028\n#define AVR32_USBB_UDTST2_BYPASSDPLL 5\n#define AVR32_USBB_UDTST2_BYPASSDPLL_MASK 0x00000020\n#define AVR32_USBB_UDTST2_BYPASSDPLL_OFFSET 5\n#define AVR32_USBB_UDTST2_BYPASSDPLL_SIZE 1\n#define AVR32_USBB_UDTST2_DISBALEGATEDCLOCK 3\n#define AVR32_USBB_UDTST2_DISBALEGATEDCLOCK_MASK 0x00000008\n#define AVR32_USBB_UDTST2_DISBALEGATEDCLOCK_OFFSET 3\n#define AVR32_USBB_UDTST2_DISBALEGATEDCLOCK_SIZE 1\n#define AVR32_USBB_UDTST2_FORCESUSPENDMTO1 4\n#define AVR32_USBB_UDTST2_FORCESUSPENDMTO1_MASK 0x00000010\n#define AVR32_USBB_UDTST2_FORCESUSPENDMTO1_OFFSET 4\n#define AVR32_USBB_UDTST2_FORCESUSPENDMTO1_SIZE 1\n#define AVR32_USBB_UDTST2_FULLDETACHEN 0\n#define AVR32_USBB_UDTST2_FULLDETACHEN_MASK 0x00000001\n#define AVR32_USBB_UDTST2_FULLDETACHEN_OFFSET 0\n#define AVR32_USBB_UDTST2_FULLDETACHEN_SIZE 1\n#define AVR32_USBB_UDTST2_HSSERIALMODE 1\n#define AVR32_USBB_UDTST2_HSSERIALMODE_MASK 0x00000002\n#define AVR32_USBB_UDTST2_HSSERIALMODE_OFFSET 1\n#define AVR32_USBB_UDTST2_HSSERIALMODE_SIZE 1\n#define AVR32_USBB_UDTST2_LOOPBACKMODE 2\n#define AVR32_USBB_UDTST2_LOOPBACKMODE_MASK 0x00000004\n#define AVR32_USBB_UDTST2_LOOPBACKMODE_OFFSET 2\n#define AVR32_USBB_UDTST2_LOOPBACKMODE_SIZE 1\n#define AVR32_USBB_UDTST2_NOTHOSTDISCONNECT 6\n#define AVR32_USBB_UDTST2_NOTHOSTDISCONNECT_MASK 0x00000040\n#define AVR32_USBB_UDTST2_NOTHOSTDISCONNECT_OFFSET 6\n#define AVR32_USBB_UDTST2_NOTHOSTDISCONNECT_SIZE 1\n#define AVR32_USBB_UDVERS 0x0000002c\n#define AVR32_USBB_UECFG0 0x00000100\n#define AVR32_USBB_UECFG0_ALLOC 1\n#define AVR32_USBB_UECFG0_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UECFG0_ALLOC_OFFSET 1\n#define AVR32_USBB_UECFG0_ALLOC_SIZE 1\n#define AVR32_USBB_UECFG0_AUTOSW 9\n#define AVR32_USBB_UECFG0_AUTOSW_MASK 0x00000200\n#define AVR32_USBB_UECFG0_AUTOSW_OFFSET 9\n#define AVR32_USBB_UECFG0_AUTOSW_SIZE 1\n#define AVR32_USBB_UECFG0_DATASIZERDWR 30\n#define AVR32_USBB_UECFG0_DATASIZERDWR_MASK 0xc0000000\n#define AVR32_USBB_UECFG0_DATASIZERDWR_OFFSET 30\n#define AVR32_USBB_UECFG0_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UECFG0_EPBK 2\n#define AVR32_USBB_UECFG0_EPBK_DOUBLE 0x00000001\n#define AVR32_USBB_UECFG0_EPBK_MASK 0x0000000c\n#define AVR32_USBB_UECFG0_EPBK_OFFSET 2\n#define AVR32_USBB_UECFG0_EPBK_SINGLE 0x00000000\n#define AVR32_USBB_UECFG0_EPBK_SIZE 2\n#define AVR32_USBB_UECFG0_EPBK_TRIPLE 0x00000002\n#define AVR32_USBB_UECFG0_EPDIR 8\n#define AVR32_USBB_UECFG0_EPDIR_IN 0x00000001\n#define AVR32_USBB_UECFG0_EPDIR_MASK 0x00000100\n#define AVR32_USBB_UECFG0_EPDIR_OFFSET 8\n#define AVR32_USBB_UECFG0_EPDIR_OUT 0x00000000\n#define AVR32_USBB_UECFG0_EPDIR_SIZE 1\n#define AVR32_USBB_UECFG0_EPSIZE 4\n#define AVR32_USBB_UECFG0_EPSIZE_1024 0x00000007\n#define AVR32_USBB_UECFG0_EPSIZE_128 0x00000004\n#define AVR32_USBB_UECFG0_EPSIZE_16 0x00000001\n#define AVR32_USBB_UECFG0_EPSIZE_256 0x00000005\n#define AVR32_USBB_UECFG0_EPSIZE_32 0x00000002\n#define AVR32_USBB_UECFG0_EPSIZE_512 0x00000006\n#define AVR32_USBB_UECFG0_EPSIZE_64 0x00000003\n#define AVR32_USBB_UECFG0_EPSIZE_8 0x00000000\n#define AVR32_USBB_UECFG0_EPSIZE_MASK 0x00000070\n#define AVR32_USBB_UECFG0_EPSIZE_OFFSET 4\n#define AVR32_USBB_UECFG0_EPSIZE_SIZE 3\n#define AVR32_USBB_UECFG0_EPTYPE 11\n#define AVR32_USBB_UECFG0_EPTYPE_BULK 0x00000002\n#define AVR32_USBB_UECFG0_EPTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UECFG0_EPTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UECFG0_EPTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UECFG0_EPTYPE_MASK 0x00001800\n#define AVR32_USBB_UECFG0_EPTYPE_OFFSET 11\n#define AVR32_USBB_UECFG0_EPTYPE_SIZE 2\n#define AVR32_USBB_UECFG0_NBTRANS 13\n#define AVR32_USBB_UECFG0_NBTRANS_MASK 0x00006000\n#define AVR32_USBB_UECFG0_NBTRANS_OFFSET 13\n#define AVR32_USBB_UECFG0_NBTRANS_SIZE 2\n#define AVR32_USBB_UECFG1 0x00000104\n#define AVR32_USBB_UECFG1_ALLOC 1\n#define AVR32_USBB_UECFG1_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UECFG1_ALLOC_OFFSET 1\n#define AVR32_USBB_UECFG1_ALLOC_SIZE 1\n#define AVR32_USBB_UECFG1_AUTOSW 9\n#define AVR32_USBB_UECFG1_AUTOSW_MASK 0x00000200\n#define AVR32_USBB_UECFG1_AUTOSW_OFFSET 9\n#define AVR32_USBB_UECFG1_AUTOSW_SIZE 1\n#define AVR32_USBB_UECFG1_DATASIZERDWR 30\n#define AVR32_USBB_UECFG1_DATASIZERDWR_MASK 0xc0000000\n#define AVR32_USBB_UECFG1_DATASIZERDWR_OFFSET 30\n#define AVR32_USBB_UECFG1_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UECFG1_EPBK 2\n#define AVR32_USBB_UECFG1_EPBK_DOUBLE 0x00000001\n#define AVR32_USBB_UECFG1_EPBK_MASK 0x0000000c\n#define AVR32_USBB_UECFG1_EPBK_OFFSET 2\n#define AVR32_USBB_UECFG1_EPBK_SINGLE 0x00000000\n#define AVR32_USBB_UECFG1_EPBK_SIZE 2\n#define AVR32_USBB_UECFG1_EPBK_TRIPLE 0x00000002\n#define AVR32_USBB_UECFG1_EPDIR 8\n#define AVR32_USBB_UECFG1_EPDIR_IN 0x00000001\n#define AVR32_USBB_UECFG1_EPDIR_MASK 0x00000100\n#define AVR32_USBB_UECFG1_EPDIR_OFFSET 8\n#define AVR32_USBB_UECFG1_EPDIR_OUT 0x00000000\n#define AVR32_USBB_UECFG1_EPDIR_SIZE 1\n#define AVR32_USBB_UECFG1_EPSIZE 4\n#define AVR32_USBB_UECFG1_EPSIZE_1024 0x00000007\n#define AVR32_USBB_UECFG1_EPSIZE_128 0x00000004\n#define AVR32_USBB_UECFG1_EPSIZE_16 0x00000001\n#define AVR32_USBB_UECFG1_EPSIZE_256 0x00000005\n#define AVR32_USBB_UECFG1_EPSIZE_32 0x00000002\n#define AVR32_USBB_UECFG1_EPSIZE_512 0x00000006\n#define AVR32_USBB_UECFG1_EPSIZE_64 0x00000003\n#define AVR32_USBB_UECFG1_EPSIZE_8 0x00000000\n#define AVR32_USBB_UECFG1_EPSIZE_MASK 0x00000070\n#define AVR32_USBB_UECFG1_EPSIZE_OFFSET 4\n#define AVR32_USBB_UECFG1_EPSIZE_SIZE 3\n#define AVR32_USBB_UECFG1_EPTYPE 11\n#define AVR32_USBB_UECFG1_EPTYPE_BULK 0x00000002\n#define AVR32_USBB_UECFG1_EPTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UECFG1_EPTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UECFG1_EPTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UECFG1_EPTYPE_MASK 0x00001800\n#define AVR32_USBB_UECFG1_EPTYPE_OFFSET 11\n#define AVR32_USBB_UECFG1_EPTYPE_SIZE 2\n#define AVR32_USBB_UECFG1_NBTRANS 13\n#define AVR32_USBB_UECFG1_NBTRANS_MASK 0x00006000\n#define AVR32_USBB_UECFG1_NBTRANS_OFFSET 13\n#define AVR32_USBB_UECFG1_NBTRANS_SIZE 2\n#define AVR32_USBB_UECFG2 0x00000108\n#define AVR32_USBB_UECFG2_ALLOC 1\n#define AVR32_USBB_UECFG2_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UECFG2_ALLOC_OFFSET 1\n#define AVR32_USBB_UECFG2_ALLOC_SIZE 1\n#define AVR32_USBB_UECFG2_AUTOSW 9\n#define AVR32_USBB_UECFG2_AUTOSW_MASK 0x00000200\n#define AVR32_USBB_UECFG2_AUTOSW_OFFSET 9\n#define AVR32_USBB_UECFG2_AUTOSW_SIZE 1\n#define AVR32_USBB_UECFG2_DATASIZERDWR 30\n#define AVR32_USBB_UECFG2_DATASIZERDWR_MASK 0xc0000000\n#define AVR32_USBB_UECFG2_DATASIZERDWR_OFFSET 30\n#define AVR32_USBB_UECFG2_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UECFG2_EPBK 2\n#define AVR32_USBB_UECFG2_EPBK_DOUBLE 0x00000001\n#define AVR32_USBB_UECFG2_EPBK_MASK 0x0000000c\n#define AVR32_USBB_UECFG2_EPBK_OFFSET 2\n#define AVR32_USBB_UECFG2_EPBK_SINGLE 0x00000000\n#define AVR32_USBB_UECFG2_EPBK_SIZE 2\n#define AVR32_USBB_UECFG2_EPBK_TRIPLE 0x00000002\n#define AVR32_USBB_UECFG2_EPDIR 8\n#define AVR32_USBB_UECFG2_EPDIR_IN 0x00000001\n#define AVR32_USBB_UECFG2_EPDIR_MASK 0x00000100\n#define AVR32_USBB_UECFG2_EPDIR_OFFSET 8\n#define AVR32_USBB_UECFG2_EPDIR_OUT 0x00000000\n#define AVR32_USBB_UECFG2_EPDIR_SIZE 1\n#define AVR32_USBB_UECFG2_EPSIZE 4\n#define AVR32_USBB_UECFG2_EPSIZE_1024 0x00000007\n#define AVR32_USBB_UECFG2_EPSIZE_128 0x00000004\n#define AVR32_USBB_UECFG2_EPSIZE_16 0x00000001\n#define AVR32_USBB_UECFG2_EPSIZE_256 0x00000005\n#define AVR32_USBB_UECFG2_EPSIZE_32 0x00000002\n#define AVR32_USBB_UECFG2_EPSIZE_512 0x00000006\n#define AVR32_USBB_UECFG2_EPSIZE_64 0x00000003\n#define AVR32_USBB_UECFG2_EPSIZE_8 0x00000000\n#define AVR32_USBB_UECFG2_EPSIZE_MASK 0x00000070\n#define AVR32_USBB_UECFG2_EPSIZE_OFFSET 4\n#define AVR32_USBB_UECFG2_EPSIZE_SIZE 3\n#define AVR32_USBB_UECFG2_EPTYPE 11\n#define AVR32_USBB_UECFG2_EPTYPE_BULK 0x00000002\n#define AVR32_USBB_UECFG2_EPTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UECFG2_EPTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UECFG2_EPTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UECFG2_EPTYPE_MASK 0x00001800\n#define AVR32_USBB_UECFG2_EPTYPE_OFFSET 11\n#define AVR32_USBB_UECFG2_EPTYPE_SIZE 2\n#define AVR32_USBB_UECFG2_NBTRANS 13\n#define AVR32_USBB_UECFG2_NBTRANS_MASK 0x00006000\n#define AVR32_USBB_UECFG2_NBTRANS_OFFSET 13\n#define AVR32_USBB_UECFG2_NBTRANS_SIZE 2\n#define AVR32_USBB_UECFG3 0x0000010c\n#define AVR32_USBB_UECFG3_ALLOC 1\n#define AVR32_USBB_UECFG3_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UECFG3_ALLOC_OFFSET 1\n#define AVR32_USBB_UECFG3_ALLOC_SIZE 1\n#define AVR32_USBB_UECFG3_AUTOSW 9\n#define AVR32_USBB_UECFG3_AUTOSW_MASK 0x00000200\n#define AVR32_USBB_UECFG3_AUTOSW_OFFSET 9\n#define AVR32_USBB_UECFG3_AUTOSW_SIZE 1\n#define AVR32_USBB_UECFG3_DATASIZERDWR 30\n#define AVR32_USBB_UECFG3_DATASIZERDWR_MASK 0xc0000000\n#define AVR32_USBB_UECFG3_DATASIZERDWR_OFFSET 30\n#define AVR32_USBB_UECFG3_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UECFG3_EPBK 2\n#define AVR32_USBB_UECFG3_EPBK_DOUBLE 0x00000001\n#define AVR32_USBB_UECFG3_EPBK_MASK 0x0000000c\n#define AVR32_USBB_UECFG3_EPBK_OFFSET 2\n#define AVR32_USBB_UECFG3_EPBK_SINGLE 0x00000000\n#define AVR32_USBB_UECFG3_EPBK_SIZE 2\n#define AVR32_USBB_UECFG3_EPBK_TRIPLE 0x00000002\n#define AVR32_USBB_UECFG3_EPDIR 8\n#define AVR32_USBB_UECFG3_EPDIR_IN 0x00000001\n#define AVR32_USBB_UECFG3_EPDIR_MASK 0x00000100\n#define AVR32_USBB_UECFG3_EPDIR_OFFSET 8\n#define AVR32_USBB_UECFG3_EPDIR_OUT 0x00000000\n#define AVR32_USBB_UECFG3_EPDIR_SIZE 1\n#define AVR32_USBB_UECFG3_EPSIZE 4\n#define AVR32_USBB_UECFG3_EPSIZE_1024 0x00000007\n#define AVR32_USBB_UECFG3_EPSIZE_128 0x00000004\n#define AVR32_USBB_UECFG3_EPSIZE_16 0x00000001\n#define AVR32_USBB_UECFG3_EPSIZE_256 0x00000005\n#define AVR32_USBB_UECFG3_EPSIZE_32 0x00000002\n#define AVR32_USBB_UECFG3_EPSIZE_512 0x00000006\n#define AVR32_USBB_UECFG3_EPSIZE_64 0x00000003\n#define AVR32_USBB_UECFG3_EPSIZE_8 0x00000000\n#define AVR32_USBB_UECFG3_EPSIZE_MASK 0x00000070\n#define AVR32_USBB_UECFG3_EPSIZE_OFFSET 4\n#define AVR32_USBB_UECFG3_EPSIZE_SIZE 3\n#define AVR32_USBB_UECFG3_EPTYPE 11\n#define AVR32_USBB_UECFG3_EPTYPE_BULK 0x00000002\n#define AVR32_USBB_UECFG3_EPTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UECFG3_EPTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UECFG3_EPTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UECFG3_EPTYPE_MASK 0x00001800\n#define AVR32_USBB_UECFG3_EPTYPE_OFFSET 11\n#define AVR32_USBB_UECFG3_EPTYPE_SIZE 2\n#define AVR32_USBB_UECFG3_NBTRANS 13\n#define AVR32_USBB_UECFG3_NBTRANS_MASK 0x00006000\n#define AVR32_USBB_UECFG3_NBTRANS_OFFSET 13\n#define AVR32_USBB_UECFG3_NBTRANS_SIZE 2\n#define AVR32_USBB_UECFG4 0x00000110\n#define AVR32_USBB_UECFG4_ALLOC 1\n#define AVR32_USBB_UECFG4_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UECFG4_ALLOC_OFFSET 1\n#define AVR32_USBB_UECFG4_ALLOC_SIZE 1\n#define AVR32_USBB_UECFG4_AUTOSW 9\n#define AVR32_USBB_UECFG4_AUTOSW_MASK 0x00000200\n#define AVR32_USBB_UECFG4_AUTOSW_OFFSET 9\n#define AVR32_USBB_UECFG4_AUTOSW_SIZE 1\n#define AVR32_USBB_UECFG4_DATASIZERDWR 30\n#define AVR32_USBB_UECFG4_DATASIZERDWR_MASK 0xc0000000\n#define AVR32_USBB_UECFG4_DATASIZERDWR_OFFSET 30\n#define AVR32_USBB_UECFG4_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UECFG4_EPBK 2\n#define AVR32_USBB_UECFG4_EPBK_DOUBLE 0x00000001\n#define AVR32_USBB_UECFG4_EPBK_MASK 0x0000000c\n#define AVR32_USBB_UECFG4_EPBK_OFFSET 2\n#define AVR32_USBB_UECFG4_EPBK_SINGLE 0x00000000\n#define AVR32_USBB_UECFG4_EPBK_SIZE 2\n#define AVR32_USBB_UECFG4_EPBK_TRIPLE 0x00000002\n#define AVR32_USBB_UECFG4_EPDIR 8\n#define AVR32_USBB_UECFG4_EPDIR_IN 0x00000001\n#define AVR32_USBB_UECFG4_EPDIR_MASK 0x00000100\n#define AVR32_USBB_UECFG4_EPDIR_OFFSET 8\n#define AVR32_USBB_UECFG4_EPDIR_OUT 0x00000000\n#define AVR32_USBB_UECFG4_EPDIR_SIZE 1\n#define AVR32_USBB_UECFG4_EPSIZE 4\n#define AVR32_USBB_UECFG4_EPSIZE_1024 0x00000007\n#define AVR32_USBB_UECFG4_EPSIZE_128 0x00000004\n#define AVR32_USBB_UECFG4_EPSIZE_16 0x00000001\n#define AVR32_USBB_UECFG4_EPSIZE_256 0x00000005\n#define AVR32_USBB_UECFG4_EPSIZE_32 0x00000002\n#define AVR32_USBB_UECFG4_EPSIZE_512 0x00000006\n#define AVR32_USBB_UECFG4_EPSIZE_64 0x00000003\n#define AVR32_USBB_UECFG4_EPSIZE_8 0x00000000\n#define AVR32_USBB_UECFG4_EPSIZE_MASK 0x00000070\n#define AVR32_USBB_UECFG4_EPSIZE_OFFSET 4\n#define AVR32_USBB_UECFG4_EPSIZE_SIZE 3\n#define AVR32_USBB_UECFG4_EPTYPE 11\n#define AVR32_USBB_UECFG4_EPTYPE_BULK 0x00000002\n#define AVR32_USBB_UECFG4_EPTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UECFG4_EPTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UECFG4_EPTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UECFG4_EPTYPE_MASK 0x00001800\n#define AVR32_USBB_UECFG4_EPTYPE_OFFSET 11\n#define AVR32_USBB_UECFG4_EPTYPE_SIZE 2\n#define AVR32_USBB_UECFG4_NBTRANS 13\n#define AVR32_USBB_UECFG4_NBTRANS_MASK 0x00006000\n#define AVR32_USBB_UECFG4_NBTRANS_OFFSET 13\n#define AVR32_USBB_UECFG4_NBTRANS_SIZE 2\n#define AVR32_USBB_UECFG5 0x00000114\n#define AVR32_USBB_UECFG5_ALLOC 1\n#define AVR32_USBB_UECFG5_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UECFG5_ALLOC_OFFSET 1\n#define AVR32_USBB_UECFG5_ALLOC_SIZE 1\n#define AVR32_USBB_UECFG5_AUTOSW 9\n#define AVR32_USBB_UECFG5_AUTOSW_MASK 0x00000200\n#define AVR32_USBB_UECFG5_AUTOSW_OFFSET 9\n#define AVR32_USBB_UECFG5_AUTOSW_SIZE 1\n#define AVR32_USBB_UECFG5_DATASIZERDWR 30\n#define AVR32_USBB_UECFG5_DATASIZERDWR_MASK 0xc0000000\n#define AVR32_USBB_UECFG5_DATASIZERDWR_OFFSET 30\n#define AVR32_USBB_UECFG5_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UECFG5_EPBK 2\n#define AVR32_USBB_UECFG5_EPBK_DOUBLE 0x00000001\n#define AVR32_USBB_UECFG5_EPBK_MASK 0x0000000c\n#define AVR32_USBB_UECFG5_EPBK_OFFSET 2\n#define AVR32_USBB_UECFG5_EPBK_SINGLE 0x00000000\n#define AVR32_USBB_UECFG5_EPBK_SIZE 2\n#define AVR32_USBB_UECFG5_EPBK_TRIPLE 0x00000002\n#define AVR32_USBB_UECFG5_EPDIR 8\n#define AVR32_USBB_UECFG5_EPDIR_IN 0x00000001\n#define AVR32_USBB_UECFG5_EPDIR_MASK 0x00000100\n#define AVR32_USBB_UECFG5_EPDIR_OFFSET 8\n#define AVR32_USBB_UECFG5_EPDIR_OUT 0x00000000\n#define AVR32_USBB_UECFG5_EPDIR_SIZE 1\n#define AVR32_USBB_UECFG5_EPSIZE 4\n#define AVR32_USBB_UECFG5_EPSIZE_1024 0x00000007\n#define AVR32_USBB_UECFG5_EPSIZE_128 0x00000004\n#define AVR32_USBB_UECFG5_EPSIZE_16 0x00000001\n#define AVR32_USBB_UECFG5_EPSIZE_256 0x00000005\n#define AVR32_USBB_UECFG5_EPSIZE_32 0x00000002\n#define AVR32_USBB_UECFG5_EPSIZE_512 0x00000006\n#define AVR32_USBB_UECFG5_EPSIZE_64 0x00000003\n#define AVR32_USBB_UECFG5_EPSIZE_8 0x00000000\n#define AVR32_USBB_UECFG5_EPSIZE_MASK 0x00000070\n#define AVR32_USBB_UECFG5_EPSIZE_OFFSET 4\n#define AVR32_USBB_UECFG5_EPSIZE_SIZE 3\n#define AVR32_USBB_UECFG5_EPTYPE 11\n#define AVR32_USBB_UECFG5_EPTYPE_BULK 0x00000002\n#define AVR32_USBB_UECFG5_EPTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UECFG5_EPTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UECFG5_EPTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UECFG5_EPTYPE_MASK 0x00001800\n#define AVR32_USBB_UECFG5_EPTYPE_OFFSET 11\n#define AVR32_USBB_UECFG5_EPTYPE_SIZE 2\n#define AVR32_USBB_UECFG5_NBTRANS 13\n#define AVR32_USBB_UECFG5_NBTRANS_MASK 0x00006000\n#define AVR32_USBB_UECFG5_NBTRANS_OFFSET 13\n#define AVR32_USBB_UECFG5_NBTRANS_SIZE 2\n#define AVR32_USBB_UECFG6 0x00000118\n#define AVR32_USBB_UECFG6_ALLOC 1\n#define AVR32_USBB_UECFG6_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UECFG6_ALLOC_OFFSET 1\n#define AVR32_USBB_UECFG6_ALLOC_SIZE 1\n#define AVR32_USBB_UECFG6_AUTOSW 9\n#define AVR32_USBB_UECFG6_AUTOSW_MASK 0x00000200\n#define AVR32_USBB_UECFG6_AUTOSW_OFFSET 9\n#define AVR32_USBB_UECFG6_AUTOSW_SIZE 1\n#define AVR32_USBB_UECFG6_DATASIZERDWR 30\n#define AVR32_USBB_UECFG6_DATASIZERDWR_MASK 0xc0000000\n#define AVR32_USBB_UECFG6_DATASIZERDWR_OFFSET 30\n#define AVR32_USBB_UECFG6_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UECFG6_EPBK 2\n#define AVR32_USBB_UECFG6_EPBK_DOUBLE 0x00000001\n#define AVR32_USBB_UECFG6_EPBK_MASK 0x0000000c\n#define AVR32_USBB_UECFG6_EPBK_OFFSET 2\n#define AVR32_USBB_UECFG6_EPBK_SINGLE 0x00000000\n#define AVR32_USBB_UECFG6_EPBK_SIZE 2\n#define AVR32_USBB_UECFG6_EPBK_TRIPLE 0x00000002\n#define AVR32_USBB_UECFG6_EPDIR 8\n#define AVR32_USBB_UECFG6_EPDIR_IN 0x00000001\n#define AVR32_USBB_UECFG6_EPDIR_MASK 0x00000100\n#define AVR32_USBB_UECFG6_EPDIR_OFFSET 8\n#define AVR32_USBB_UECFG6_EPDIR_OUT 0x00000000\n#define AVR32_USBB_UECFG6_EPDIR_SIZE 1\n#define AVR32_USBB_UECFG6_EPSIZE 4\n#define AVR32_USBB_UECFG6_EPSIZE_1024 0x00000007\n#define AVR32_USBB_UECFG6_EPSIZE_128 0x00000004\n#define AVR32_USBB_UECFG6_EPSIZE_16 0x00000001\n#define AVR32_USBB_UECFG6_EPSIZE_256 0x00000005\n#define AVR32_USBB_UECFG6_EPSIZE_32 0x00000002\n#define AVR32_USBB_UECFG6_EPSIZE_512 0x00000006\n#define AVR32_USBB_UECFG6_EPSIZE_64 0x00000003\n#define AVR32_USBB_UECFG6_EPSIZE_8 0x00000000\n#define AVR32_USBB_UECFG6_EPSIZE_MASK 0x00000070\n#define AVR32_USBB_UECFG6_EPSIZE_OFFSET 4\n#define AVR32_USBB_UECFG6_EPSIZE_SIZE 3\n#define AVR32_USBB_UECFG6_EPTYPE 11\n#define AVR32_USBB_UECFG6_EPTYPE_BULK 0x00000002\n#define AVR32_USBB_UECFG6_EPTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UECFG6_EPTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UECFG6_EPTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UECFG6_EPTYPE_MASK 0x00001800\n#define AVR32_USBB_UECFG6_EPTYPE_OFFSET 11\n#define AVR32_USBB_UECFG6_EPTYPE_SIZE 2\n#define AVR32_USBB_UECFG6_NBTRANS 13\n#define AVR32_USBB_UECFG6_NBTRANS_MASK 0x00006000\n#define AVR32_USBB_UECFG6_NBTRANS_OFFSET 13\n#define AVR32_USBB_UECFG6_NBTRANS_SIZE 2\n#define AVR32_USBB_UECON0 0x000001c0\n#define AVR32_USBB_UECON0CLR 0x00000220\n#define AVR32_USBB_UECON0CLR_DATAXEC 9\n#define AVR32_USBB_UECON0CLR_DATAXEC_MASK 0x00000200\n#define AVR32_USBB_UECON0CLR_DATAXEC_OFFSET 9\n#define AVR32_USBB_UECON0CLR_DATAXEC_SIZE 1\n#define AVR32_USBB_UECON0CLR_EPDISHDMAC 16\n#define AVR32_USBB_UECON0CLR_EPDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UECON0CLR_EPDISHDMAC_OFFSET 16\n#define AVR32_USBB_UECON0CLR_EPDISHDMAC_SIZE 1\n#define AVR32_USBB_UECON0CLR_ERRORTRANSEC 10\n#define AVR32_USBB_UECON0CLR_ERRORTRANSEC_MASK 0x00000400\n#define AVR32_USBB_UECON0CLR_ERRORTRANSEC_OFFSET 10\n#define AVR32_USBB_UECON0CLR_ERRORTRANSEC_SIZE 1\n#define AVR32_USBB_UECON0CLR_FIFOCONC 14\n#define AVR32_USBB_UECON0CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UECON0CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UECON0CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UECON0CLR_MDATAEC 8\n#define AVR32_USBB_UECON0CLR_MDATAEC_MASK 0x00000100\n#define AVR32_USBB_UECON0CLR_MDATAEC_OFFSET 8\n#define AVR32_USBB_UECON0CLR_MDATAEC_SIZE 1\n#define AVR32_USBB_UECON0CLR_NAKINEC 4\n#define AVR32_USBB_UECON0CLR_NAKINEC_MASK 0x00000010\n#define AVR32_USBB_UECON0CLR_NAKINEC_OFFSET 4\n#define AVR32_USBB_UECON0CLR_NAKINEC_SIZE 1\n#define AVR32_USBB_UECON0CLR_NAKOUTEC 3\n#define AVR32_USBB_UECON0CLR_NAKOUTEC_MASK 0x00000008\n#define AVR32_USBB_UECON0CLR_NAKOUTEC_OFFSET 3\n#define AVR32_USBB_UECON0CLR_NAKOUTEC_SIZE 1\n#define AVR32_USBB_UECON0CLR_NBUSYBKEC 12\n#define AVR32_USBB_UECON0CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UECON0CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UECON0CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UECON0CLR_NYETDISC 17\n#define AVR32_USBB_UECON0CLR_NYETDISC_MASK 0x00020000\n#define AVR32_USBB_UECON0CLR_NYETDISC_OFFSET 17\n#define AVR32_USBB_UECON0CLR_NYETDISC_SIZE 1\n#define AVR32_USBB_UECON0CLR_OVERFEC 5\n#define AVR32_USBB_UECON0CLR_OVERFEC_MASK 0x00000020\n#define AVR32_USBB_UECON0CLR_OVERFEC_OFFSET 5\n#define AVR32_USBB_UECON0CLR_OVERFEC_SIZE 1\n#define AVR32_USBB_UECON0CLR_RXOUTEC 1\n#define AVR32_USBB_UECON0CLR_RXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UECON0CLR_RXOUTEC_OFFSET 1\n#define AVR32_USBB_UECON0CLR_RXOUTEC_SIZE 1\n#define AVR32_USBB_UECON0CLR_RXSTPEC 2\n#define AVR32_USBB_UECON0CLR_RXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UECON0CLR_RXSTPEC_OFFSET 2\n#define AVR32_USBB_UECON0CLR_RXSTPEC_SIZE 1\n#define AVR32_USBB_UECON0CLR_SHORTPACKETEC 7\n#define AVR32_USBB_UECON0CLR_SHORTPACKETEC_MASK 0x00000080\n#define AVR32_USBB_UECON0CLR_SHORTPACKETEC_OFFSET 7\n#define AVR32_USBB_UECON0CLR_SHORTPACKETEC_SIZE 1\n#define AVR32_USBB_UECON0CLR_STALLEDEC 6\n#define AVR32_USBB_UECON0CLR_STALLEDEC_MASK 0x00000040\n#define AVR32_USBB_UECON0CLR_STALLEDEC_OFFSET 6\n#define AVR32_USBB_UECON0CLR_STALLEDEC_SIZE 1\n#define AVR32_USBB_UECON0CLR_STALLRQC 19\n#define AVR32_USBB_UECON0CLR_STALLRQC_MASK 0x00080000\n#define AVR32_USBB_UECON0CLR_STALLRQC_OFFSET 19\n#define AVR32_USBB_UECON0CLR_STALLRQC_SIZE 1\n#define AVR32_USBB_UECON0CLR_TXINEC 0\n#define AVR32_USBB_UECON0CLR_TXINEC_MASK 0x00000001\n#define AVR32_USBB_UECON0CLR_TXINEC_OFFSET 0\n#define AVR32_USBB_UECON0CLR_TXINEC_SIZE 1\n#define AVR32_USBB_UECON0SET 0x000001f0\n#define AVR32_USBB_UECON0SET_DATAXES 9\n#define AVR32_USBB_UECON0SET_DATAXES_MASK 0x00000200\n#define AVR32_USBB_UECON0SET_DATAXES_OFFSET 9\n#define AVR32_USBB_UECON0SET_DATAXES_SIZE 1\n#define AVR32_USBB_UECON0SET_EPDISHDMAS 16\n#define AVR32_USBB_UECON0SET_EPDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UECON0SET_EPDISHDMAS_OFFSET 16\n#define AVR32_USBB_UECON0SET_EPDISHDMAS_SIZE 1\n#define AVR32_USBB_UECON0SET_ERRORTRANSES 10\n#define AVR32_USBB_UECON0SET_ERRORTRANSES_MASK 0x00000400\n#define AVR32_USBB_UECON0SET_ERRORTRANSES_OFFSET 10\n#define AVR32_USBB_UECON0SET_ERRORTRANSES_SIZE 1\n#define AVR32_USBB_UECON0SET_KILLBKS 13\n#define AVR32_USBB_UECON0SET_KILLBKS_MASK 0x00002000\n#define AVR32_USBB_UECON0SET_KILLBKS_OFFSET 13\n#define AVR32_USBB_UECON0SET_KILLBKS_SIZE 1\n#define AVR32_USBB_UECON0SET_MDATAES 8\n#define AVR32_USBB_UECON0SET_MDATAES_MASK 0x00000100\n#define AVR32_USBB_UECON0SET_MDATAES_OFFSET 8\n#define AVR32_USBB_UECON0SET_MDATAES_SIZE 1\n#define AVR32_USBB_UECON0SET_NAKINES 4\n#define AVR32_USBB_UECON0SET_NAKINES_MASK 0x00000010\n#define AVR32_USBB_UECON0SET_NAKINES_OFFSET 4\n#define AVR32_USBB_UECON0SET_NAKINES_SIZE 1\n#define AVR32_USBB_UECON0SET_NAKOUTES 3\n#define AVR32_USBB_UECON0SET_NAKOUTES_MASK 0x00000008\n#define AVR32_USBB_UECON0SET_NAKOUTES_OFFSET 3\n#define AVR32_USBB_UECON0SET_NAKOUTES_SIZE 1\n#define AVR32_USBB_UECON0SET_NBUSYBKES 12\n#define AVR32_USBB_UECON0SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UECON0SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UECON0SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UECON0SET_NYETDISS 17\n#define AVR32_USBB_UECON0SET_NYETDISS_MASK 0x00020000\n#define AVR32_USBB_UECON0SET_NYETDISS_OFFSET 17\n#define AVR32_USBB_UECON0SET_NYETDISS_SIZE 1\n#define AVR32_USBB_UECON0SET_OVERFES 5\n#define AVR32_USBB_UECON0SET_OVERFES_MASK 0x00000020\n#define AVR32_USBB_UECON0SET_OVERFES_OFFSET 5\n#define AVR32_USBB_UECON0SET_OVERFES_SIZE 1\n#define AVR32_USBB_UECON0SET_RSTDTS 18\n#define AVR32_USBB_UECON0SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UECON0SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UECON0SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UECON0SET_RXOUTES 1\n#define AVR32_USBB_UECON0SET_RXOUTES_MASK 0x00000002\n#define AVR32_USBB_UECON0SET_RXOUTES_OFFSET 1\n#define AVR32_USBB_UECON0SET_RXOUTES_SIZE 1\n#define AVR32_USBB_UECON0SET_RXSTPES 2\n#define AVR32_USBB_UECON0SET_RXSTPES_MASK 0x00000004\n#define AVR32_USBB_UECON0SET_RXSTPES_OFFSET 2\n#define AVR32_USBB_UECON0SET_RXSTPES_SIZE 1\n#define AVR32_USBB_UECON0SET_SHORTPACKETES 7\n#define AVR32_USBB_UECON0SET_SHORTPACKETES_MASK 0x00000080\n#define AVR32_USBB_UECON0SET_SHORTPACKETES_OFFSET 7\n#define AVR32_USBB_UECON0SET_SHORTPACKETES_SIZE 1\n#define AVR32_USBB_UECON0SET_STALLEDES 6\n#define AVR32_USBB_UECON0SET_STALLEDES_MASK 0x00000040\n#define AVR32_USBB_UECON0SET_STALLEDES_OFFSET 6\n#define AVR32_USBB_UECON0SET_STALLEDES_SIZE 1\n#define AVR32_USBB_UECON0SET_STALLRQS 19\n#define AVR32_USBB_UECON0SET_STALLRQS_MASK 0x00080000\n#define AVR32_USBB_UECON0SET_STALLRQS_OFFSET 19\n#define AVR32_USBB_UECON0SET_STALLRQS_SIZE 1\n#define AVR32_USBB_UECON0SET_TXINES 0\n#define AVR32_USBB_UECON0SET_TXINES_MASK 0x00000001\n#define AVR32_USBB_UECON0SET_TXINES_OFFSET 0\n#define AVR32_USBB_UECON0SET_TXINES_SIZE 1\n#define AVR32_USBB_UECON0_DATAXE 9\n#define AVR32_USBB_UECON0_DATAXE_MASK 0x00000200\n#define AVR32_USBB_UECON0_DATAXE_OFFSET 9\n#define AVR32_USBB_UECON0_DATAXE_SIZE 1\n#define AVR32_USBB_UECON0_EPDISHDMA 16\n#define AVR32_USBB_UECON0_EPDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UECON0_EPDISHDMA_OFFSET 16\n#define AVR32_USBB_UECON0_EPDISHDMA_SIZE 1\n#define AVR32_USBB_UECON0_ERRORTRANSE 10\n#define AVR32_USBB_UECON0_ERRORTRANSE_MASK 0x00000400\n#define AVR32_USBB_UECON0_ERRORTRANSE_OFFSET 10\n#define AVR32_USBB_UECON0_ERRORTRANSE_SIZE 1\n#define AVR32_USBB_UECON0_FIFOCON 14\n#define AVR32_USBB_UECON0_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UECON0_FIFOCON_OFFSET 14\n#define AVR32_USBB_UECON0_FIFOCON_SIZE 1\n#define AVR32_USBB_UECON0_KILLBK 13\n#define AVR32_USBB_UECON0_KILLBK_MASK 0x00002000\n#define AVR32_USBB_UECON0_KILLBK_OFFSET 13\n#define AVR32_USBB_UECON0_KILLBK_SIZE 1\n#define AVR32_USBB_UECON0_MDATAE 8\n#define AVR32_USBB_UECON0_MDATAE_MASK 0x00000100\n#define AVR32_USBB_UECON0_MDATAE_OFFSET 8\n#define AVR32_USBB_UECON0_MDATAE_SIZE 1\n#define AVR32_USBB_UECON0_NAKINE 4\n#define AVR32_USBB_UECON0_NAKINE_MASK 0x00000010\n#define AVR32_USBB_UECON0_NAKINE_OFFSET 4\n#define AVR32_USBB_UECON0_NAKINE_SIZE 1\n#define AVR32_USBB_UECON0_NAKOUTE 3\n#define AVR32_USBB_UECON0_NAKOUTE_MASK 0x00000008\n#define AVR32_USBB_UECON0_NAKOUTE_OFFSET 3\n#define AVR32_USBB_UECON0_NAKOUTE_SIZE 1\n#define AVR32_USBB_UECON0_NBUSYBKE 12\n#define AVR32_USBB_UECON0_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UECON0_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UECON0_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UECON0_NYETDIS 17\n#define AVR32_USBB_UECON0_NYETDIS_MASK 0x00020000\n#define AVR32_USBB_UECON0_NYETDIS_OFFSET 17\n#define AVR32_USBB_UECON0_NYETDIS_SIZE 1\n#define AVR32_USBB_UECON0_OVERFE 5\n#define AVR32_USBB_UECON0_OVERFE_MASK 0x00000020\n#define AVR32_USBB_UECON0_OVERFE_OFFSET 5\n#define AVR32_USBB_UECON0_OVERFE_SIZE 1\n#define AVR32_USBB_UECON0_RSTDT 18\n#define AVR32_USBB_UECON0_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UECON0_RSTDT_OFFSET 18\n#define AVR32_USBB_UECON0_RSTDT_SIZE 1\n#define AVR32_USBB_UECON0_RXOUTE 1\n#define AVR32_USBB_UECON0_RXOUTE_MASK 0x00000002\n#define AVR32_USBB_UECON0_RXOUTE_OFFSET 1\n#define AVR32_USBB_UECON0_RXOUTE_SIZE 1\n#define AVR32_USBB_UECON0_RXSTPE 2\n#define AVR32_USBB_UECON0_RXSTPE_MASK 0x00000004\n#define AVR32_USBB_UECON0_RXSTPE_OFFSET 2\n#define AVR32_USBB_UECON0_RXSTPE_SIZE 1\n#define AVR32_USBB_UECON0_SHORTPACKETE 7\n#define AVR32_USBB_UECON0_SHORTPACKETE_MASK 0x00000080\n#define AVR32_USBB_UECON0_SHORTPACKETE_OFFSET 7\n#define AVR32_USBB_UECON0_SHORTPACKETE_SIZE 1\n#define AVR32_USBB_UECON0_STALLEDE 6\n#define AVR32_USBB_UECON0_STALLEDE_MASK 0x00000040\n#define AVR32_USBB_UECON0_STALLEDE_OFFSET 6\n#define AVR32_USBB_UECON0_STALLEDE_SIZE 1\n#define AVR32_USBB_UECON0_STALLRQ 19\n#define AVR32_USBB_UECON0_STALLRQ_MASK 0x00080000\n#define AVR32_USBB_UECON0_STALLRQ_OFFSET 19\n#define AVR32_USBB_UECON0_STALLRQ_SIZE 1\n#define AVR32_USBB_UECON0_TXINE 0\n#define AVR32_USBB_UECON0_TXINE_MASK 0x00000001\n#define AVR32_USBB_UECON0_TXINE_OFFSET 0\n#define AVR32_USBB_UECON0_TXINE_SIZE 1\n#define AVR32_USBB_UECON1 0x000001c4\n#define AVR32_USBB_UECON1CLR 0x00000224\n#define AVR32_USBB_UECON1CLR_DATAXEC 9\n#define AVR32_USBB_UECON1CLR_DATAXEC_MASK 0x00000200\n#define AVR32_USBB_UECON1CLR_DATAXEC_OFFSET 9\n#define AVR32_USBB_UECON1CLR_DATAXEC_SIZE 1\n#define AVR32_USBB_UECON1CLR_EPDISHDMAC 16\n#define AVR32_USBB_UECON1CLR_EPDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UECON1CLR_EPDISHDMAC_OFFSET 16\n#define AVR32_USBB_UECON1CLR_EPDISHDMAC_SIZE 1\n#define AVR32_USBB_UECON1CLR_ERRORTRANSEC 10\n#define AVR32_USBB_UECON1CLR_ERRORTRANSEC_MASK 0x00000400\n#define AVR32_USBB_UECON1CLR_ERRORTRANSEC_OFFSET 10\n#define AVR32_USBB_UECON1CLR_ERRORTRANSEC_SIZE 1\n#define AVR32_USBB_UECON1CLR_FIFOCONC 14\n#define AVR32_USBB_UECON1CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UECON1CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UECON1CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UECON1CLR_MDATAEC 8\n#define AVR32_USBB_UECON1CLR_MDATAEC_MASK 0x00000100\n#define AVR32_USBB_UECON1CLR_MDATAEC_OFFSET 8\n#define AVR32_USBB_UECON1CLR_MDATAEC_SIZE 1\n#define AVR32_USBB_UECON1CLR_NAKINEC 4\n#define AVR32_USBB_UECON1CLR_NAKINEC_MASK 0x00000010\n#define AVR32_USBB_UECON1CLR_NAKINEC_OFFSET 4\n#define AVR32_USBB_UECON1CLR_NAKINEC_SIZE 1\n#define AVR32_USBB_UECON1CLR_NAKOUTEC 3\n#define AVR32_USBB_UECON1CLR_NAKOUTEC_MASK 0x00000008\n#define AVR32_USBB_UECON1CLR_NAKOUTEC_OFFSET 3\n#define AVR32_USBB_UECON1CLR_NAKOUTEC_SIZE 1\n#define AVR32_USBB_UECON1CLR_NBUSYBKEC 12\n#define AVR32_USBB_UECON1CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UECON1CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UECON1CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UECON1CLR_NYETDISC 17\n#define AVR32_USBB_UECON1CLR_NYETDISC_MASK 0x00020000\n#define AVR32_USBB_UECON1CLR_NYETDISC_OFFSET 17\n#define AVR32_USBB_UECON1CLR_NYETDISC_SIZE 1\n#define AVR32_USBB_UECON1CLR_OVERFEC 5\n#define AVR32_USBB_UECON1CLR_OVERFEC_MASK 0x00000020\n#define AVR32_USBB_UECON1CLR_OVERFEC_OFFSET 5\n#define AVR32_USBB_UECON1CLR_OVERFEC_SIZE 1\n#define AVR32_USBB_UECON1CLR_RXOUTEC 1\n#define AVR32_USBB_UECON1CLR_RXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UECON1CLR_RXOUTEC_OFFSET 1\n#define AVR32_USBB_UECON1CLR_RXOUTEC_SIZE 1\n#define AVR32_USBB_UECON1CLR_RXSTPEC 2\n#define AVR32_USBB_UECON1CLR_RXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UECON1CLR_RXSTPEC_OFFSET 2\n#define AVR32_USBB_UECON1CLR_RXSTPEC_SIZE 1\n#define AVR32_USBB_UECON1CLR_SHORTPACKETEC 7\n#define AVR32_USBB_UECON1CLR_SHORTPACKETEC_MASK 0x00000080\n#define AVR32_USBB_UECON1CLR_SHORTPACKETEC_OFFSET 7\n#define AVR32_USBB_UECON1CLR_SHORTPACKETEC_SIZE 1\n#define AVR32_USBB_UECON1CLR_STALLEDEC 6\n#define AVR32_USBB_UECON1CLR_STALLEDEC_MASK 0x00000040\n#define AVR32_USBB_UECON1CLR_STALLEDEC_OFFSET 6\n#define AVR32_USBB_UECON1CLR_STALLEDEC_SIZE 1\n#define AVR32_USBB_UECON1CLR_STALLRQC 19\n#define AVR32_USBB_UECON1CLR_STALLRQC_MASK 0x00080000\n#define AVR32_USBB_UECON1CLR_STALLRQC_OFFSET 19\n#define AVR32_USBB_UECON1CLR_STALLRQC_SIZE 1\n#define AVR32_USBB_UECON1CLR_TXINEC 0\n#define AVR32_USBB_UECON1CLR_TXINEC_MASK 0x00000001\n#define AVR32_USBB_UECON1CLR_TXINEC_OFFSET 0\n#define AVR32_USBB_UECON1CLR_TXINEC_SIZE 1\n#define AVR32_USBB_UECON1SET 0x000001f4\n#define AVR32_USBB_UECON1SET_DATAXES 9\n#define AVR32_USBB_UECON1SET_DATAXES_MASK 0x00000200\n#define AVR32_USBB_UECON1SET_DATAXES_OFFSET 9\n#define AVR32_USBB_UECON1SET_DATAXES_SIZE 1\n#define AVR32_USBB_UECON1SET_EPDISHDMAS 16\n#define AVR32_USBB_UECON1SET_EPDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UECON1SET_EPDISHDMAS_OFFSET 16\n#define AVR32_USBB_UECON1SET_EPDISHDMAS_SIZE 1\n#define AVR32_USBB_UECON1SET_ERRORTRANSES 10\n#define AVR32_USBB_UECON1SET_ERRORTRANSES_MASK 0x00000400\n#define AVR32_USBB_UECON1SET_ERRORTRANSES_OFFSET 10\n#define AVR32_USBB_UECON1SET_ERRORTRANSES_SIZE 1\n#define AVR32_USBB_UECON1SET_KILLBKS 13\n#define AVR32_USBB_UECON1SET_KILLBKS_MASK 0x00002000\n#define AVR32_USBB_UECON1SET_KILLBKS_OFFSET 13\n#define AVR32_USBB_UECON1SET_KILLBKS_SIZE 1\n#define AVR32_USBB_UECON1SET_MDATAES 8\n#define AVR32_USBB_UECON1SET_MDATAES_MASK 0x00000100\n#define AVR32_USBB_UECON1SET_MDATAES_OFFSET 8\n#define AVR32_USBB_UECON1SET_MDATAES_SIZE 1\n#define AVR32_USBB_UECON1SET_NAKINES 4\n#define AVR32_USBB_UECON1SET_NAKINES_MASK 0x00000010\n#define AVR32_USBB_UECON1SET_NAKINES_OFFSET 4\n#define AVR32_USBB_UECON1SET_NAKINES_SIZE 1\n#define AVR32_USBB_UECON1SET_NAKOUTES 3\n#define AVR32_USBB_UECON1SET_NAKOUTES_MASK 0x00000008\n#define AVR32_USBB_UECON1SET_NAKOUTES_OFFSET 3\n#define AVR32_USBB_UECON1SET_NAKOUTES_SIZE 1\n#define AVR32_USBB_UECON1SET_NBUSYBKES 12\n#define AVR32_USBB_UECON1SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UECON1SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UECON1SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UECON1SET_NYETDISS 17\n#define AVR32_USBB_UECON1SET_NYETDISS_MASK 0x00020000\n#define AVR32_USBB_UECON1SET_NYETDISS_OFFSET 17\n#define AVR32_USBB_UECON1SET_NYETDISS_SIZE 1\n#define AVR32_USBB_UECON1SET_OVERFES 5\n#define AVR32_USBB_UECON1SET_OVERFES_MASK 0x00000020\n#define AVR32_USBB_UECON1SET_OVERFES_OFFSET 5\n#define AVR32_USBB_UECON1SET_OVERFES_SIZE 1\n#define AVR32_USBB_UECON1SET_RSTDTS 18\n#define AVR32_USBB_UECON1SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UECON1SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UECON1SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UECON1SET_RXOUTES 1\n#define AVR32_USBB_UECON1SET_RXOUTES_MASK 0x00000002\n#define AVR32_USBB_UECON1SET_RXOUTES_OFFSET 1\n#define AVR32_USBB_UECON1SET_RXOUTES_SIZE 1\n#define AVR32_USBB_UECON1SET_RXSTPES 2\n#define AVR32_USBB_UECON1SET_RXSTPES_MASK 0x00000004\n#define AVR32_USBB_UECON1SET_RXSTPES_OFFSET 2\n#define AVR32_USBB_UECON1SET_RXSTPES_SIZE 1\n#define AVR32_USBB_UECON1SET_SHORTPACKETES 7\n#define AVR32_USBB_UECON1SET_SHORTPACKETES_MASK 0x00000080\n#define AVR32_USBB_UECON1SET_SHORTPACKETES_OFFSET 7\n#define AVR32_USBB_UECON1SET_SHORTPACKETES_SIZE 1\n#define AVR32_USBB_UECON1SET_STALLEDES 6\n#define AVR32_USBB_UECON1SET_STALLEDES_MASK 0x00000040\n#define AVR32_USBB_UECON1SET_STALLEDES_OFFSET 6\n#define AVR32_USBB_UECON1SET_STALLEDES_SIZE 1\n#define AVR32_USBB_UECON1SET_STALLRQS 19\n#define AVR32_USBB_UECON1SET_STALLRQS_MASK 0x00080000\n#define AVR32_USBB_UECON1SET_STALLRQS_OFFSET 19\n#define AVR32_USBB_UECON1SET_STALLRQS_SIZE 1\n#define AVR32_USBB_UECON1SET_TXINES 0\n#define AVR32_USBB_UECON1SET_TXINES_MASK 0x00000001\n#define AVR32_USBB_UECON1SET_TXINES_OFFSET 0\n#define AVR32_USBB_UECON1SET_TXINES_SIZE 1\n#define AVR32_USBB_UECON1_DATAXE 9\n#define AVR32_USBB_UECON1_DATAXE_MASK 0x00000200\n#define AVR32_USBB_UECON1_DATAXE_OFFSET 9\n#define AVR32_USBB_UECON1_DATAXE_SIZE 1\n#define AVR32_USBB_UECON1_EPDISHDMA 16\n#define AVR32_USBB_UECON1_EPDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UECON1_EPDISHDMA_OFFSET 16\n#define AVR32_USBB_UECON1_EPDISHDMA_SIZE 1\n#define AVR32_USBB_UECON1_ERRORTRANSE 10\n#define AVR32_USBB_UECON1_ERRORTRANSE_MASK 0x00000400\n#define AVR32_USBB_UECON1_ERRORTRANSE_OFFSET 10\n#define AVR32_USBB_UECON1_ERRORTRANSE_SIZE 1\n#define AVR32_USBB_UECON1_FIFOCON 14\n#define AVR32_USBB_UECON1_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UECON1_FIFOCON_OFFSET 14\n#define AVR32_USBB_UECON1_FIFOCON_SIZE 1\n#define AVR32_USBB_UECON1_KILLBK 13\n#define AVR32_USBB_UECON1_KILLBK_MASK 0x00002000\n#define AVR32_USBB_UECON1_KILLBK_OFFSET 13\n#define AVR32_USBB_UECON1_KILLBK_SIZE 1\n#define AVR32_USBB_UECON1_MDATAE 8\n#define AVR32_USBB_UECON1_MDATAE_MASK 0x00000100\n#define AVR32_USBB_UECON1_MDATAE_OFFSET 8\n#define AVR32_USBB_UECON1_MDATAE_SIZE 1\n#define AVR32_USBB_UECON1_NAKINE 4\n#define AVR32_USBB_UECON1_NAKINE_MASK 0x00000010\n#define AVR32_USBB_UECON1_NAKINE_OFFSET 4\n#define AVR32_USBB_UECON1_NAKINE_SIZE 1\n#define AVR32_USBB_UECON1_NAKOUTE 3\n#define AVR32_USBB_UECON1_NAKOUTE_MASK 0x00000008\n#define AVR32_USBB_UECON1_NAKOUTE_OFFSET 3\n#define AVR32_USBB_UECON1_NAKOUTE_SIZE 1\n#define AVR32_USBB_UECON1_NBUSYBKE 12\n#define AVR32_USBB_UECON1_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UECON1_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UECON1_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UECON1_NYETDIS 17\n#define AVR32_USBB_UECON1_NYETDIS_MASK 0x00020000\n#define AVR32_USBB_UECON1_NYETDIS_OFFSET 17\n#define AVR32_USBB_UECON1_NYETDIS_SIZE 1\n#define AVR32_USBB_UECON1_OVERFE 5\n#define AVR32_USBB_UECON1_OVERFE_MASK 0x00000020\n#define AVR32_USBB_UECON1_OVERFE_OFFSET 5\n#define AVR32_USBB_UECON1_OVERFE_SIZE 1\n#define AVR32_USBB_UECON1_RSTDT 18\n#define AVR32_USBB_UECON1_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UECON1_RSTDT_OFFSET 18\n#define AVR32_USBB_UECON1_RSTDT_SIZE 1\n#define AVR32_USBB_UECON1_RXOUTE 1\n#define AVR32_USBB_UECON1_RXOUTE_MASK 0x00000002\n#define AVR32_USBB_UECON1_RXOUTE_OFFSET 1\n#define AVR32_USBB_UECON1_RXOUTE_SIZE 1\n#define AVR32_USBB_UECON1_RXSTPE 2\n#define AVR32_USBB_UECON1_RXSTPE_MASK 0x00000004\n#define AVR32_USBB_UECON1_RXSTPE_OFFSET 2\n#define AVR32_USBB_UECON1_RXSTPE_SIZE 1\n#define AVR32_USBB_UECON1_SHORTPACKETE 7\n#define AVR32_USBB_UECON1_SHORTPACKETE_MASK 0x00000080\n#define AVR32_USBB_UECON1_SHORTPACKETE_OFFSET 7\n#define AVR32_USBB_UECON1_SHORTPACKETE_SIZE 1\n#define AVR32_USBB_UECON1_STALLEDE 6\n#define AVR32_USBB_UECON1_STALLEDE_MASK 0x00000040\n#define AVR32_USBB_UECON1_STALLEDE_OFFSET 6\n#define AVR32_USBB_UECON1_STALLEDE_SIZE 1\n#define AVR32_USBB_UECON1_STALLRQ 19\n#define AVR32_USBB_UECON1_STALLRQ_MASK 0x00080000\n#define AVR32_USBB_UECON1_STALLRQ_OFFSET 19\n#define AVR32_USBB_UECON1_STALLRQ_SIZE 1\n#define AVR32_USBB_UECON1_TXINE 0\n#define AVR32_USBB_UECON1_TXINE_MASK 0x00000001\n#define AVR32_USBB_UECON1_TXINE_OFFSET 0\n#define AVR32_USBB_UECON1_TXINE_SIZE 1\n#define AVR32_USBB_UECON2 0x000001c8\n#define AVR32_USBB_UECON2CLR 0x00000228\n#define AVR32_USBB_UECON2CLR_DATAXEC 9\n#define AVR32_USBB_UECON2CLR_DATAXEC_MASK 0x00000200\n#define AVR32_USBB_UECON2CLR_DATAXEC_OFFSET 9\n#define AVR32_USBB_UECON2CLR_DATAXEC_SIZE 1\n#define AVR32_USBB_UECON2CLR_EPDISHDMAC 16\n#define AVR32_USBB_UECON2CLR_EPDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UECON2CLR_EPDISHDMAC_OFFSET 16\n#define AVR32_USBB_UECON2CLR_EPDISHDMAC_SIZE 1\n#define AVR32_USBB_UECON2CLR_ERRORTRANSEC 10\n#define AVR32_USBB_UECON2CLR_ERRORTRANSEC_MASK 0x00000400\n#define AVR32_USBB_UECON2CLR_ERRORTRANSEC_OFFSET 10\n#define AVR32_USBB_UECON2CLR_ERRORTRANSEC_SIZE 1\n#define AVR32_USBB_UECON2CLR_FIFOCONC 14\n#define AVR32_USBB_UECON2CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UECON2CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UECON2CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UECON2CLR_MDATAEC 8\n#define AVR32_USBB_UECON2CLR_MDATAEC_MASK 0x00000100\n#define AVR32_USBB_UECON2CLR_MDATAEC_OFFSET 8\n#define AVR32_USBB_UECON2CLR_MDATAEC_SIZE 1\n#define AVR32_USBB_UECON2CLR_NAKINEC 4\n#define AVR32_USBB_UECON2CLR_NAKINEC_MASK 0x00000010\n#define AVR32_USBB_UECON2CLR_NAKINEC_OFFSET 4\n#define AVR32_USBB_UECON2CLR_NAKINEC_SIZE 1\n#define AVR32_USBB_UECON2CLR_NAKOUTEC 3\n#define AVR32_USBB_UECON2CLR_NAKOUTEC_MASK 0x00000008\n#define AVR32_USBB_UECON2CLR_NAKOUTEC_OFFSET 3\n#define AVR32_USBB_UECON2CLR_NAKOUTEC_SIZE 1\n#define AVR32_USBB_UECON2CLR_NBUSYBKEC 12\n#define AVR32_USBB_UECON2CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UECON2CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UECON2CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UECON2CLR_NYETDISC 17\n#define AVR32_USBB_UECON2CLR_NYETDISC_MASK 0x00020000\n#define AVR32_USBB_UECON2CLR_NYETDISC_OFFSET 17\n#define AVR32_USBB_UECON2CLR_NYETDISC_SIZE 1\n#define AVR32_USBB_UECON2CLR_OVERFEC 5\n#define AVR32_USBB_UECON2CLR_OVERFEC_MASK 0x00000020\n#define AVR32_USBB_UECON2CLR_OVERFEC_OFFSET 5\n#define AVR32_USBB_UECON2CLR_OVERFEC_SIZE 1\n#define AVR32_USBB_UECON2CLR_RXOUTEC 1\n#define AVR32_USBB_UECON2CLR_RXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UECON2CLR_RXOUTEC_OFFSET 1\n#define AVR32_USBB_UECON2CLR_RXOUTEC_SIZE 1\n#define AVR32_USBB_UECON2CLR_RXSTPEC 2\n#define AVR32_USBB_UECON2CLR_RXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UECON2CLR_RXSTPEC_OFFSET 2\n#define AVR32_USBB_UECON2CLR_RXSTPEC_SIZE 1\n#define AVR32_USBB_UECON2CLR_SHORTPACKETEC 7\n#define AVR32_USBB_UECON2CLR_SHORTPACKETEC_MASK 0x00000080\n#define AVR32_USBB_UECON2CLR_SHORTPACKETEC_OFFSET 7\n#define AVR32_USBB_UECON2CLR_SHORTPACKETEC_SIZE 1\n#define AVR32_USBB_UECON2CLR_STALLEDEC 6\n#define AVR32_USBB_UECON2CLR_STALLEDEC_MASK 0x00000040\n#define AVR32_USBB_UECON2CLR_STALLEDEC_OFFSET 6\n#define AVR32_USBB_UECON2CLR_STALLEDEC_SIZE 1\n#define AVR32_USBB_UECON2CLR_STALLRQC 19\n#define AVR32_USBB_UECON2CLR_STALLRQC_MASK 0x00080000\n#define AVR32_USBB_UECON2CLR_STALLRQC_OFFSET 19\n#define AVR32_USBB_UECON2CLR_STALLRQC_SIZE 1\n#define AVR32_USBB_UECON2CLR_TXINEC 0\n#define AVR32_USBB_UECON2CLR_TXINEC_MASK 0x00000001\n#define AVR32_USBB_UECON2CLR_TXINEC_OFFSET 0\n#define AVR32_USBB_UECON2CLR_TXINEC_SIZE 1\n#define AVR32_USBB_UECON2SET 0x000001f8\n#define AVR32_USBB_UECON2SET_DATAXES 9\n#define AVR32_USBB_UECON2SET_DATAXES_MASK 0x00000200\n#define AVR32_USBB_UECON2SET_DATAXES_OFFSET 9\n#define AVR32_USBB_UECON2SET_DATAXES_SIZE 1\n#define AVR32_USBB_UECON2SET_EPDISHDMAS 16\n#define AVR32_USBB_UECON2SET_EPDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UECON2SET_EPDISHDMAS_OFFSET 16\n#define AVR32_USBB_UECON2SET_EPDISHDMAS_SIZE 1\n#define AVR32_USBB_UECON2SET_ERRORTRANSES 10\n#define AVR32_USBB_UECON2SET_ERRORTRANSES_MASK 0x00000400\n#define AVR32_USBB_UECON2SET_ERRORTRANSES_OFFSET 10\n#define AVR32_USBB_UECON2SET_ERRORTRANSES_SIZE 1\n#define AVR32_USBB_UECON2SET_KILLBKS 13\n#define AVR32_USBB_UECON2SET_KILLBKS_MASK 0x00002000\n#define AVR32_USBB_UECON2SET_KILLBKS_OFFSET 13\n#define AVR32_USBB_UECON2SET_KILLBKS_SIZE 1\n#define AVR32_USBB_UECON2SET_MDATAES 8\n#define AVR32_USBB_UECON2SET_MDATAES_MASK 0x00000100\n#define AVR32_USBB_UECON2SET_MDATAES_OFFSET 8\n#define AVR32_USBB_UECON2SET_MDATAES_SIZE 1\n#define AVR32_USBB_UECON2SET_NAKINES 4\n#define AVR32_USBB_UECON2SET_NAKINES_MASK 0x00000010\n#define AVR32_USBB_UECON2SET_NAKINES_OFFSET 4\n#define AVR32_USBB_UECON2SET_NAKINES_SIZE 1\n#define AVR32_USBB_UECON2SET_NAKOUTES 3\n#define AVR32_USBB_UECON2SET_NAKOUTES_MASK 0x00000008\n#define AVR32_USBB_UECON2SET_NAKOUTES_OFFSET 3\n#define AVR32_USBB_UECON2SET_NAKOUTES_SIZE 1\n#define AVR32_USBB_UECON2SET_NBUSYBKES 12\n#define AVR32_USBB_UECON2SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UECON2SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UECON2SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UECON2SET_NYETDISS 17\n#define AVR32_USBB_UECON2SET_NYETDISS_MASK 0x00020000\n#define AVR32_USBB_UECON2SET_NYETDISS_OFFSET 17\n#define AVR32_USBB_UECON2SET_NYETDISS_SIZE 1\n#define AVR32_USBB_UECON2SET_OVERFES 5\n#define AVR32_USBB_UECON2SET_OVERFES_MASK 0x00000020\n#define AVR32_USBB_UECON2SET_OVERFES_OFFSET 5\n#define AVR32_USBB_UECON2SET_OVERFES_SIZE 1\n#define AVR32_USBB_UECON2SET_RSTDTS 18\n#define AVR32_USBB_UECON2SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UECON2SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UECON2SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UECON2SET_RXOUTES 1\n#define AVR32_USBB_UECON2SET_RXOUTES_MASK 0x00000002\n#define AVR32_USBB_UECON2SET_RXOUTES_OFFSET 1\n#define AVR32_USBB_UECON2SET_RXOUTES_SIZE 1\n#define AVR32_USBB_UECON2SET_RXSTPES 2\n#define AVR32_USBB_UECON2SET_RXSTPES_MASK 0x00000004\n#define AVR32_USBB_UECON2SET_RXSTPES_OFFSET 2\n#define AVR32_USBB_UECON2SET_RXSTPES_SIZE 1\n#define AVR32_USBB_UECON2SET_SHORTPACKETES 7\n#define AVR32_USBB_UECON2SET_SHORTPACKETES_MASK 0x00000080\n#define AVR32_USBB_UECON2SET_SHORTPACKETES_OFFSET 7\n#define AVR32_USBB_UECON2SET_SHORTPACKETES_SIZE 1\n#define AVR32_USBB_UECON2SET_STALLEDES 6\n#define AVR32_USBB_UECON2SET_STALLEDES_MASK 0x00000040\n#define AVR32_USBB_UECON2SET_STALLEDES_OFFSET 6\n#define AVR32_USBB_UECON2SET_STALLEDES_SIZE 1\n#define AVR32_USBB_UECON2SET_STALLRQS 19\n#define AVR32_USBB_UECON2SET_STALLRQS_MASK 0x00080000\n#define AVR32_USBB_UECON2SET_STALLRQS_OFFSET 19\n#define AVR32_USBB_UECON2SET_STALLRQS_SIZE 1\n#define AVR32_USBB_UECON2SET_TXINES 0\n#define AVR32_USBB_UECON2SET_TXINES_MASK 0x00000001\n#define AVR32_USBB_UECON2SET_TXINES_OFFSET 0\n#define AVR32_USBB_UECON2SET_TXINES_SIZE 1\n#define AVR32_USBB_UECON2_DATAXE 9\n#define AVR32_USBB_UECON2_DATAXE_MASK 0x00000200\n#define AVR32_USBB_UECON2_DATAXE_OFFSET 9\n#define AVR32_USBB_UECON2_DATAXE_SIZE 1\n#define AVR32_USBB_UECON2_EPDISHDMA 16\n#define AVR32_USBB_UECON2_EPDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UECON2_EPDISHDMA_OFFSET 16\n#define AVR32_USBB_UECON2_EPDISHDMA_SIZE 1\n#define AVR32_USBB_UECON2_ERRORTRANSE 10\n#define AVR32_USBB_UECON2_ERRORTRANSE_MASK 0x00000400\n#define AVR32_USBB_UECON2_ERRORTRANSE_OFFSET 10\n#define AVR32_USBB_UECON2_ERRORTRANSE_SIZE 1\n#define AVR32_USBB_UECON2_FIFOCON 14\n#define AVR32_USBB_UECON2_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UECON2_FIFOCON_OFFSET 14\n#define AVR32_USBB_UECON2_FIFOCON_SIZE 1\n#define AVR32_USBB_UECON2_KILLBK 13\n#define AVR32_USBB_UECON2_KILLBK_MASK 0x00002000\n#define AVR32_USBB_UECON2_KILLBK_OFFSET 13\n#define AVR32_USBB_UECON2_KILLBK_SIZE 1\n#define AVR32_USBB_UECON2_MDATAE 8\n#define AVR32_USBB_UECON2_MDATAE_MASK 0x00000100\n#define AVR32_USBB_UECON2_MDATAE_OFFSET 8\n#define AVR32_USBB_UECON2_MDATAE_SIZE 1\n#define AVR32_USBB_UECON2_NAKINE 4\n#define AVR32_USBB_UECON2_NAKINE_MASK 0x00000010\n#define AVR32_USBB_UECON2_NAKINE_OFFSET 4\n#define AVR32_USBB_UECON2_NAKINE_SIZE 1\n#define AVR32_USBB_UECON2_NAKOUTE 3\n#define AVR32_USBB_UECON2_NAKOUTE_MASK 0x00000008\n#define AVR32_USBB_UECON2_NAKOUTE_OFFSET 3\n#define AVR32_USBB_UECON2_NAKOUTE_SIZE 1\n#define AVR32_USBB_UECON2_NBUSYBKE 12\n#define AVR32_USBB_UECON2_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UECON2_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UECON2_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UECON2_NYETDIS 17\n#define AVR32_USBB_UECON2_NYETDIS_MASK 0x00020000\n#define AVR32_USBB_UECON2_NYETDIS_OFFSET 17\n#define AVR32_USBB_UECON2_NYETDIS_SIZE 1\n#define AVR32_USBB_UECON2_OVERFE 5\n#define AVR32_USBB_UECON2_OVERFE_MASK 0x00000020\n#define AVR32_USBB_UECON2_OVERFE_OFFSET 5\n#define AVR32_USBB_UECON2_OVERFE_SIZE 1\n#define AVR32_USBB_UECON2_RSTDT 18\n#define AVR32_USBB_UECON2_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UECON2_RSTDT_OFFSET 18\n#define AVR32_USBB_UECON2_RSTDT_SIZE 1\n#define AVR32_USBB_UECON2_RXOUTE 1\n#define AVR32_USBB_UECON2_RXOUTE_MASK 0x00000002\n#define AVR32_USBB_UECON2_RXOUTE_OFFSET 1\n#define AVR32_USBB_UECON2_RXOUTE_SIZE 1\n#define AVR32_USBB_UECON2_RXSTPE 2\n#define AVR32_USBB_UECON2_RXSTPE_MASK 0x00000004\n#define AVR32_USBB_UECON2_RXSTPE_OFFSET 2\n#define AVR32_USBB_UECON2_RXSTPE_SIZE 1\n#define AVR32_USBB_UECON2_SHORTPACKETE 7\n#define AVR32_USBB_UECON2_SHORTPACKETE_MASK 0x00000080\n#define AVR32_USBB_UECON2_SHORTPACKETE_OFFSET 7\n#define AVR32_USBB_UECON2_SHORTPACKETE_SIZE 1\n#define AVR32_USBB_UECON2_STALLEDE 6\n#define AVR32_USBB_UECON2_STALLEDE_MASK 0x00000040\n#define AVR32_USBB_UECON2_STALLEDE_OFFSET 6\n#define AVR32_USBB_UECON2_STALLEDE_SIZE 1\n#define AVR32_USBB_UECON2_STALLRQ 19\n#define AVR32_USBB_UECON2_STALLRQ_MASK 0x00080000\n#define AVR32_USBB_UECON2_STALLRQ_OFFSET 19\n#define AVR32_USBB_UECON2_STALLRQ_SIZE 1\n#define AVR32_USBB_UECON2_TXINE 0\n#define AVR32_USBB_UECON2_TXINE_MASK 0x00000001\n#define AVR32_USBB_UECON2_TXINE_OFFSET 0\n#define AVR32_USBB_UECON2_TXINE_SIZE 1\n#define AVR32_USBB_UECON3 0x000001cc\n#define AVR32_USBB_UECON3CLR 0x0000022c\n#define AVR32_USBB_UECON3CLR_DATAXEC 9\n#define AVR32_USBB_UECON3CLR_DATAXEC_MASK 0x00000200\n#define AVR32_USBB_UECON3CLR_DATAXEC_OFFSET 9\n#define AVR32_USBB_UECON3CLR_DATAXEC_SIZE 1\n#define AVR32_USBB_UECON3CLR_EPDISHDMAC 16\n#define AVR32_USBB_UECON3CLR_EPDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UECON3CLR_EPDISHDMAC_OFFSET 16\n#define AVR32_USBB_UECON3CLR_EPDISHDMAC_SIZE 1\n#define AVR32_USBB_UECON3CLR_ERRORTRANSEC 10\n#define AVR32_USBB_UECON3CLR_ERRORTRANSEC_MASK 0x00000400\n#define AVR32_USBB_UECON3CLR_ERRORTRANSEC_OFFSET 10\n#define AVR32_USBB_UECON3CLR_ERRORTRANSEC_SIZE 1\n#define AVR32_USBB_UECON3CLR_FIFOCONC 14\n#define AVR32_USBB_UECON3CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UECON3CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UECON3CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UECON3CLR_MDATAEC 8\n#define AVR32_USBB_UECON3CLR_MDATAEC_MASK 0x00000100\n#define AVR32_USBB_UECON3CLR_MDATAEC_OFFSET 8\n#define AVR32_USBB_UECON3CLR_MDATAEC_SIZE 1\n#define AVR32_USBB_UECON3CLR_NAKINEC 4\n#define AVR32_USBB_UECON3CLR_NAKINEC_MASK 0x00000010\n#define AVR32_USBB_UECON3CLR_NAKINEC_OFFSET 4\n#define AVR32_USBB_UECON3CLR_NAKINEC_SIZE 1\n#define AVR32_USBB_UECON3CLR_NAKOUTEC 3\n#define AVR32_USBB_UECON3CLR_NAKOUTEC_MASK 0x00000008\n#define AVR32_USBB_UECON3CLR_NAKOUTEC_OFFSET 3\n#define AVR32_USBB_UECON3CLR_NAKOUTEC_SIZE 1\n#define AVR32_USBB_UECON3CLR_NBUSYBKEC 12\n#define AVR32_USBB_UECON3CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UECON3CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UECON3CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UECON3CLR_NYETDISC 17\n#define AVR32_USBB_UECON3CLR_NYETDISC_MASK 0x00020000\n#define AVR32_USBB_UECON3CLR_NYETDISC_OFFSET 17\n#define AVR32_USBB_UECON3CLR_NYETDISC_SIZE 1\n#define AVR32_USBB_UECON3CLR_OVERFEC 5\n#define AVR32_USBB_UECON3CLR_OVERFEC_MASK 0x00000020\n#define AVR32_USBB_UECON3CLR_OVERFEC_OFFSET 5\n#define AVR32_USBB_UECON3CLR_OVERFEC_SIZE 1\n#define AVR32_USBB_UECON3CLR_RXOUTEC 1\n#define AVR32_USBB_UECON3CLR_RXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UECON3CLR_RXOUTEC_OFFSET 1\n#define AVR32_USBB_UECON3CLR_RXOUTEC_SIZE 1\n#define AVR32_USBB_UECON3CLR_RXSTPEC 2\n#define AVR32_USBB_UECON3CLR_RXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UECON3CLR_RXSTPEC_OFFSET 2\n#define AVR32_USBB_UECON3CLR_RXSTPEC_SIZE 1\n#define AVR32_USBB_UECON3CLR_SHORTPACKETEC 7\n#define AVR32_USBB_UECON3CLR_SHORTPACKETEC_MASK 0x00000080\n#define AVR32_USBB_UECON3CLR_SHORTPACKETEC_OFFSET 7\n#define AVR32_USBB_UECON3CLR_SHORTPACKETEC_SIZE 1\n#define AVR32_USBB_UECON3CLR_STALLEDEC 6\n#define AVR32_USBB_UECON3CLR_STALLEDEC_MASK 0x00000040\n#define AVR32_USBB_UECON3CLR_STALLEDEC_OFFSET 6\n#define AVR32_USBB_UECON3CLR_STALLEDEC_SIZE 1\n#define AVR32_USBB_UECON3CLR_STALLRQC 19\n#define AVR32_USBB_UECON3CLR_STALLRQC_MASK 0x00080000\n#define AVR32_USBB_UECON3CLR_STALLRQC_OFFSET 19\n#define AVR32_USBB_UECON3CLR_STALLRQC_SIZE 1\n#define AVR32_USBB_UECON3CLR_TXINEC 0\n#define AVR32_USBB_UECON3CLR_TXINEC_MASK 0x00000001\n#define AVR32_USBB_UECON3CLR_TXINEC_OFFSET 0\n#define AVR32_USBB_UECON3CLR_TXINEC_SIZE 1\n#define AVR32_USBB_UECON3SET 0x000001fc\n#define AVR32_USBB_UECON3SET_DATAXES 9\n#define AVR32_USBB_UECON3SET_DATAXES_MASK 0x00000200\n#define AVR32_USBB_UECON3SET_DATAXES_OFFSET 9\n#define AVR32_USBB_UECON3SET_DATAXES_SIZE 1\n#define AVR32_USBB_UECON3SET_EPDISHDMAS 16\n#define AVR32_USBB_UECON3SET_EPDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UECON3SET_EPDISHDMAS_OFFSET 16\n#define AVR32_USBB_UECON3SET_EPDISHDMAS_SIZE 1\n#define AVR32_USBB_UECON3SET_ERRORTRANSES 10\n#define AVR32_USBB_UECON3SET_ERRORTRANSES_MASK 0x00000400\n#define AVR32_USBB_UECON3SET_ERRORTRANSES_OFFSET 10\n#define AVR32_USBB_UECON3SET_ERRORTRANSES_SIZE 1\n#define AVR32_USBB_UECON3SET_KILLBKS 13\n#define AVR32_USBB_UECON3SET_KILLBKS_MASK 0x00002000\n#define AVR32_USBB_UECON3SET_KILLBKS_OFFSET 13\n#define AVR32_USBB_UECON3SET_KILLBKS_SIZE 1\n#define AVR32_USBB_UECON3SET_MDATAES 8\n#define AVR32_USBB_UECON3SET_MDATAES_MASK 0x00000100\n#define AVR32_USBB_UECON3SET_MDATAES_OFFSET 8\n#define AVR32_USBB_UECON3SET_MDATAES_SIZE 1\n#define AVR32_USBB_UECON3SET_NAKINES 4\n#define AVR32_USBB_UECON3SET_NAKINES_MASK 0x00000010\n#define AVR32_USBB_UECON3SET_NAKINES_OFFSET 4\n#define AVR32_USBB_UECON3SET_NAKINES_SIZE 1\n#define AVR32_USBB_UECON3SET_NAKOUTES 3\n#define AVR32_USBB_UECON3SET_NAKOUTES_MASK 0x00000008\n#define AVR32_USBB_UECON3SET_NAKOUTES_OFFSET 3\n#define AVR32_USBB_UECON3SET_NAKOUTES_SIZE 1\n#define AVR32_USBB_UECON3SET_NBUSYBKES 12\n#define AVR32_USBB_UECON3SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UECON3SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UECON3SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UECON3SET_NYETDISS 17\n#define AVR32_USBB_UECON3SET_NYETDISS_MASK 0x00020000\n#define AVR32_USBB_UECON3SET_NYETDISS_OFFSET 17\n#define AVR32_USBB_UECON3SET_NYETDISS_SIZE 1\n#define AVR32_USBB_UECON3SET_OVERFES 5\n#define AVR32_USBB_UECON3SET_OVERFES_MASK 0x00000020\n#define AVR32_USBB_UECON3SET_OVERFES_OFFSET 5\n#define AVR32_USBB_UECON3SET_OVERFES_SIZE 1\n#define AVR32_USBB_UECON3SET_RSTDTS 18\n#define AVR32_USBB_UECON3SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UECON3SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UECON3SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UECON3SET_RXOUTES 1\n#define AVR32_USBB_UECON3SET_RXOUTES_MASK 0x00000002\n#define AVR32_USBB_UECON3SET_RXOUTES_OFFSET 1\n#define AVR32_USBB_UECON3SET_RXOUTES_SIZE 1\n#define AVR32_USBB_UECON3SET_RXSTPES 2\n#define AVR32_USBB_UECON3SET_RXSTPES_MASK 0x00000004\n#define AVR32_USBB_UECON3SET_RXSTPES_OFFSET 2\n#define AVR32_USBB_UECON3SET_RXSTPES_SIZE 1\n#define AVR32_USBB_UECON3SET_SHORTPACKETES 7\n#define AVR32_USBB_UECON3SET_SHORTPACKETES_MASK 0x00000080\n#define AVR32_USBB_UECON3SET_SHORTPACKETES_OFFSET 7\n#define AVR32_USBB_UECON3SET_SHORTPACKETES_SIZE 1\n#define AVR32_USBB_UECON3SET_STALLEDES 6\n#define AVR32_USBB_UECON3SET_STALLEDES_MASK 0x00000040\n#define AVR32_USBB_UECON3SET_STALLEDES_OFFSET 6\n#define AVR32_USBB_UECON3SET_STALLEDES_SIZE 1\n#define AVR32_USBB_UECON3SET_STALLRQS 19\n#define AVR32_USBB_UECON3SET_STALLRQS_MASK 0x00080000\n#define AVR32_USBB_UECON3SET_STALLRQS_OFFSET 19\n#define AVR32_USBB_UECON3SET_STALLRQS_SIZE 1\n#define AVR32_USBB_UECON3SET_TXINES 0\n#define AVR32_USBB_UECON3SET_TXINES_MASK 0x00000001\n#define AVR32_USBB_UECON3SET_TXINES_OFFSET 0\n#define AVR32_USBB_UECON3SET_TXINES_SIZE 1\n#define AVR32_USBB_UECON3_DATAXE 9\n#define AVR32_USBB_UECON3_DATAXE_MASK 0x00000200\n#define AVR32_USBB_UECON3_DATAXE_OFFSET 9\n#define AVR32_USBB_UECON3_DATAXE_SIZE 1\n#define AVR32_USBB_UECON3_EPDISHDMA 16\n#define AVR32_USBB_UECON3_EPDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UECON3_EPDISHDMA_OFFSET 16\n#define AVR32_USBB_UECON3_EPDISHDMA_SIZE 1\n#define AVR32_USBB_UECON3_ERRORTRANSE 10\n#define AVR32_USBB_UECON3_ERRORTRANSE_MASK 0x00000400\n#define AVR32_USBB_UECON3_ERRORTRANSE_OFFSET 10\n#define AVR32_USBB_UECON3_ERRORTRANSE_SIZE 1\n#define AVR32_USBB_UECON3_FIFOCON 14\n#define AVR32_USBB_UECON3_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UECON3_FIFOCON_OFFSET 14\n#define AVR32_USBB_UECON3_FIFOCON_SIZE 1\n#define AVR32_USBB_UECON3_KILLBK 13\n#define AVR32_USBB_UECON3_KILLBK_MASK 0x00002000\n#define AVR32_USBB_UECON3_KILLBK_OFFSET 13\n#define AVR32_USBB_UECON3_KILLBK_SIZE 1\n#define AVR32_USBB_UECON3_MDATAE 8\n#define AVR32_USBB_UECON3_MDATAE_MASK 0x00000100\n#define AVR32_USBB_UECON3_MDATAE_OFFSET 8\n#define AVR32_USBB_UECON3_MDATAE_SIZE 1\n#define AVR32_USBB_UECON3_NAKINE 4\n#define AVR32_USBB_UECON3_NAKINE_MASK 0x00000010\n#define AVR32_USBB_UECON3_NAKINE_OFFSET 4\n#define AVR32_USBB_UECON3_NAKINE_SIZE 1\n#define AVR32_USBB_UECON3_NAKOUTE 3\n#define AVR32_USBB_UECON3_NAKOUTE_MASK 0x00000008\n#define AVR32_USBB_UECON3_NAKOUTE_OFFSET 3\n#define AVR32_USBB_UECON3_NAKOUTE_SIZE 1\n#define AVR32_USBB_UECON3_NBUSYBKE 12\n#define AVR32_USBB_UECON3_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UECON3_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UECON3_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UECON3_NYETDIS 17\n#define AVR32_USBB_UECON3_NYETDIS_MASK 0x00020000\n#define AVR32_USBB_UECON3_NYETDIS_OFFSET 17\n#define AVR32_USBB_UECON3_NYETDIS_SIZE 1\n#define AVR32_USBB_UECON3_OVERFE 5\n#define AVR32_USBB_UECON3_OVERFE_MASK 0x00000020\n#define AVR32_USBB_UECON3_OVERFE_OFFSET 5\n#define AVR32_USBB_UECON3_OVERFE_SIZE 1\n#define AVR32_USBB_UECON3_RSTDT 18\n#define AVR32_USBB_UECON3_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UECON3_RSTDT_OFFSET 18\n#define AVR32_USBB_UECON3_RSTDT_SIZE 1\n#define AVR32_USBB_UECON3_RXOUTE 1\n#define AVR32_USBB_UECON3_RXOUTE_MASK 0x00000002\n#define AVR32_USBB_UECON3_RXOUTE_OFFSET 1\n#define AVR32_USBB_UECON3_RXOUTE_SIZE 1\n#define AVR32_USBB_UECON3_RXSTPE 2\n#define AVR32_USBB_UECON3_RXSTPE_MASK 0x00000004\n#define AVR32_USBB_UECON3_RXSTPE_OFFSET 2\n#define AVR32_USBB_UECON3_RXSTPE_SIZE 1\n#define AVR32_USBB_UECON3_SHORTPACKETE 7\n#define AVR32_USBB_UECON3_SHORTPACKETE_MASK 0x00000080\n#define AVR32_USBB_UECON3_SHORTPACKETE_OFFSET 7\n#define AVR32_USBB_UECON3_SHORTPACKETE_SIZE 1\n#define AVR32_USBB_UECON3_STALLEDE 6\n#define AVR32_USBB_UECON3_STALLEDE_MASK 0x00000040\n#define AVR32_USBB_UECON3_STALLEDE_OFFSET 6\n#define AVR32_USBB_UECON3_STALLEDE_SIZE 1\n#define AVR32_USBB_UECON3_STALLRQ 19\n#define AVR32_USBB_UECON3_STALLRQ_MASK 0x00080000\n#define AVR32_USBB_UECON3_STALLRQ_OFFSET 19\n#define AVR32_USBB_UECON3_STALLRQ_SIZE 1\n#define AVR32_USBB_UECON3_TXINE 0\n#define AVR32_USBB_UECON3_TXINE_MASK 0x00000001\n#define AVR32_USBB_UECON3_TXINE_OFFSET 0\n#define AVR32_USBB_UECON3_TXINE_SIZE 1\n#define AVR32_USBB_UECON4 0x000001d0\n#define AVR32_USBB_UECON4CLR 0x00000230\n#define AVR32_USBB_UECON4CLR_DATAXEC 9\n#define AVR32_USBB_UECON4CLR_DATAXEC_MASK 0x00000200\n#define AVR32_USBB_UECON4CLR_DATAXEC_OFFSET 9\n#define AVR32_USBB_UECON4CLR_DATAXEC_SIZE 1\n#define AVR32_USBB_UECON4CLR_EPDISHDMAC 16\n#define AVR32_USBB_UECON4CLR_EPDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UECON4CLR_EPDISHDMAC_OFFSET 16\n#define AVR32_USBB_UECON4CLR_EPDISHDMAC_SIZE 1\n#define AVR32_USBB_UECON4CLR_ERRORTRANSEC 10\n#define AVR32_USBB_UECON4CLR_ERRORTRANSEC_MASK 0x00000400\n#define AVR32_USBB_UECON4CLR_ERRORTRANSEC_OFFSET 10\n#define AVR32_USBB_UECON4CLR_ERRORTRANSEC_SIZE 1\n#define AVR32_USBB_UECON4CLR_FIFOCONC 14\n#define AVR32_USBB_UECON4CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UECON4CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UECON4CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UECON4CLR_MDATAEC 8\n#define AVR32_USBB_UECON4CLR_MDATAEC_MASK 0x00000100\n#define AVR32_USBB_UECON4CLR_MDATAEC_OFFSET 8\n#define AVR32_USBB_UECON4CLR_MDATAEC_SIZE 1\n#define AVR32_USBB_UECON4CLR_NAKINEC 4\n#define AVR32_USBB_UECON4CLR_NAKINEC_MASK 0x00000010\n#define AVR32_USBB_UECON4CLR_NAKINEC_OFFSET 4\n#define AVR32_USBB_UECON4CLR_NAKINEC_SIZE 1\n#define AVR32_USBB_UECON4CLR_NAKOUTEC 3\n#define AVR32_USBB_UECON4CLR_NAKOUTEC_MASK 0x00000008\n#define AVR32_USBB_UECON4CLR_NAKOUTEC_OFFSET 3\n#define AVR32_USBB_UECON4CLR_NAKOUTEC_SIZE 1\n#define AVR32_USBB_UECON4CLR_NBUSYBKEC 12\n#define AVR32_USBB_UECON4CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UECON4CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UECON4CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UECON4CLR_NYETDISC 17\n#define AVR32_USBB_UECON4CLR_NYETDISC_MASK 0x00020000\n#define AVR32_USBB_UECON4CLR_NYETDISC_OFFSET 17\n#define AVR32_USBB_UECON4CLR_NYETDISC_SIZE 1\n#define AVR32_USBB_UECON4CLR_OVERFEC 5\n#define AVR32_USBB_UECON4CLR_OVERFEC_MASK 0x00000020\n#define AVR32_USBB_UECON4CLR_OVERFEC_OFFSET 5\n#define AVR32_USBB_UECON4CLR_OVERFEC_SIZE 1\n#define AVR32_USBB_UECON4CLR_RXOUTEC 1\n#define AVR32_USBB_UECON4CLR_RXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UECON4CLR_RXOUTEC_OFFSET 1\n#define AVR32_USBB_UECON4CLR_RXOUTEC_SIZE 1\n#define AVR32_USBB_UECON4CLR_RXSTPEC 2\n#define AVR32_USBB_UECON4CLR_RXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UECON4CLR_RXSTPEC_OFFSET 2\n#define AVR32_USBB_UECON4CLR_RXSTPEC_SIZE 1\n#define AVR32_USBB_UECON4CLR_SHORTPACKETEC 7\n#define AVR32_USBB_UECON4CLR_SHORTPACKETEC_MASK 0x00000080\n#define AVR32_USBB_UECON4CLR_SHORTPACKETEC_OFFSET 7\n#define AVR32_USBB_UECON4CLR_SHORTPACKETEC_SIZE 1\n#define AVR32_USBB_UECON4CLR_STALLEDEC 6\n#define AVR32_USBB_UECON4CLR_STALLEDEC_MASK 0x00000040\n#define AVR32_USBB_UECON4CLR_STALLEDEC_OFFSET 6\n#define AVR32_USBB_UECON4CLR_STALLEDEC_SIZE 1\n#define AVR32_USBB_UECON4CLR_STALLRQC 19\n#define AVR32_USBB_UECON4CLR_STALLRQC_MASK 0x00080000\n#define AVR32_USBB_UECON4CLR_STALLRQC_OFFSET 19\n#define AVR32_USBB_UECON4CLR_STALLRQC_SIZE 1\n#define AVR32_USBB_UECON4CLR_TXINEC 0\n#define AVR32_USBB_UECON4CLR_TXINEC_MASK 0x00000001\n#define AVR32_USBB_UECON4CLR_TXINEC_OFFSET 0\n#define AVR32_USBB_UECON4CLR_TXINEC_SIZE 1\n#define AVR32_USBB_UECON4SET 0x00000200\n#define AVR32_USBB_UECON4SET_DATAXES 9\n#define AVR32_USBB_UECON4SET_DATAXES_MASK 0x00000200\n#define AVR32_USBB_UECON4SET_DATAXES_OFFSET 9\n#define AVR32_USBB_UECON4SET_DATAXES_SIZE 1\n#define AVR32_USBB_UECON4SET_EPDISHDMAS 16\n#define AVR32_USBB_UECON4SET_EPDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UECON4SET_EPDISHDMAS_OFFSET 16\n#define AVR32_USBB_UECON4SET_EPDISHDMAS_SIZE 1\n#define AVR32_USBB_UECON4SET_ERRORTRANSES 10\n#define AVR32_USBB_UECON4SET_ERRORTRANSES_MASK 0x00000400\n#define AVR32_USBB_UECON4SET_ERRORTRANSES_OFFSET 10\n#define AVR32_USBB_UECON4SET_ERRORTRANSES_SIZE 1\n#define AVR32_USBB_UECON4SET_KILLBKS 13\n#define AVR32_USBB_UECON4SET_KILLBKS_MASK 0x00002000\n#define AVR32_USBB_UECON4SET_KILLBKS_OFFSET 13\n#define AVR32_USBB_UECON4SET_KILLBKS_SIZE 1\n#define AVR32_USBB_UECON4SET_MDATAES 8\n#define AVR32_USBB_UECON4SET_MDATAES_MASK 0x00000100\n#define AVR32_USBB_UECON4SET_MDATAES_OFFSET 8\n#define AVR32_USBB_UECON4SET_MDATAES_SIZE 1\n#define AVR32_USBB_UECON4SET_NAKINES 4\n#define AVR32_USBB_UECON4SET_NAKINES_MASK 0x00000010\n#define AVR32_USBB_UECON4SET_NAKINES_OFFSET 4\n#define AVR32_USBB_UECON4SET_NAKINES_SIZE 1\n#define AVR32_USBB_UECON4SET_NAKOUTES 3\n#define AVR32_USBB_UECON4SET_NAKOUTES_MASK 0x00000008\n#define AVR32_USBB_UECON4SET_NAKOUTES_OFFSET 3\n#define AVR32_USBB_UECON4SET_NAKOUTES_SIZE 1\n#define AVR32_USBB_UECON4SET_NBUSYBKES 12\n#define AVR32_USBB_UECON4SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UECON4SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UECON4SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UECON4SET_NYETDISS 17\n#define AVR32_USBB_UECON4SET_NYETDISS_MASK 0x00020000\n#define AVR32_USBB_UECON4SET_NYETDISS_OFFSET 17\n#define AVR32_USBB_UECON4SET_NYETDISS_SIZE 1\n#define AVR32_USBB_UECON4SET_OVERFES 5\n#define AVR32_USBB_UECON4SET_OVERFES_MASK 0x00000020\n#define AVR32_USBB_UECON4SET_OVERFES_OFFSET 5\n#define AVR32_USBB_UECON4SET_OVERFES_SIZE 1\n#define AVR32_USBB_UECON4SET_RSTDTS 18\n#define AVR32_USBB_UECON4SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UECON4SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UECON4SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UECON4SET_RXOUTES 1\n#define AVR32_USBB_UECON4SET_RXOUTES_MASK 0x00000002\n#define AVR32_USBB_UECON4SET_RXOUTES_OFFSET 1\n#define AVR32_USBB_UECON4SET_RXOUTES_SIZE 1\n#define AVR32_USBB_UECON4SET_RXSTPES 2\n#define AVR32_USBB_UECON4SET_RXSTPES_MASK 0x00000004\n#define AVR32_USBB_UECON4SET_RXSTPES_OFFSET 2\n#define AVR32_USBB_UECON4SET_RXSTPES_SIZE 1\n#define AVR32_USBB_UECON4SET_SHORTPACKETES 7\n#define AVR32_USBB_UECON4SET_SHORTPACKETES_MASK 0x00000080\n#define AVR32_USBB_UECON4SET_SHORTPACKETES_OFFSET 7\n#define AVR32_USBB_UECON4SET_SHORTPACKETES_SIZE 1\n#define AVR32_USBB_UECON4SET_STALLEDES 6\n#define AVR32_USBB_UECON4SET_STALLEDES_MASK 0x00000040\n#define AVR32_USBB_UECON4SET_STALLEDES_OFFSET 6\n#define AVR32_USBB_UECON4SET_STALLEDES_SIZE 1\n#define AVR32_USBB_UECON4SET_STALLRQS 19\n#define AVR32_USBB_UECON4SET_STALLRQS_MASK 0x00080000\n#define AVR32_USBB_UECON4SET_STALLRQS_OFFSET 19\n#define AVR32_USBB_UECON4SET_STALLRQS_SIZE 1\n#define AVR32_USBB_UECON4SET_TXINES 0\n#define AVR32_USBB_UECON4SET_TXINES_MASK 0x00000001\n#define AVR32_USBB_UECON4SET_TXINES_OFFSET 0\n#define AVR32_USBB_UECON4SET_TXINES_SIZE 1\n#define AVR32_USBB_UECON4_DATAXE 9\n#define AVR32_USBB_UECON4_DATAXE_MASK 0x00000200\n#define AVR32_USBB_UECON4_DATAXE_OFFSET 9\n#define AVR32_USBB_UECON4_DATAXE_SIZE 1\n#define AVR32_USBB_UECON4_EPDISHDMA 16\n#define AVR32_USBB_UECON4_EPDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UECON4_EPDISHDMA_OFFSET 16\n#define AVR32_USBB_UECON4_EPDISHDMA_SIZE 1\n#define AVR32_USBB_UECON4_ERRORTRANSE 10\n#define AVR32_USBB_UECON4_ERRORTRANSE_MASK 0x00000400\n#define AVR32_USBB_UECON4_ERRORTRANSE_OFFSET 10\n#define AVR32_USBB_UECON4_ERRORTRANSE_SIZE 1\n#define AVR32_USBB_UECON4_FIFOCON 14\n#define AVR32_USBB_UECON4_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UECON4_FIFOCON_OFFSET 14\n#define AVR32_USBB_UECON4_FIFOCON_SIZE 1\n#define AVR32_USBB_UECON4_KILLBK 13\n#define AVR32_USBB_UECON4_KILLBK_MASK 0x00002000\n#define AVR32_USBB_UECON4_KILLBK_OFFSET 13\n#define AVR32_USBB_UECON4_KILLBK_SIZE 1\n#define AVR32_USBB_UECON4_MDATAE 8\n#define AVR32_USBB_UECON4_MDATAE_MASK 0x00000100\n#define AVR32_USBB_UECON4_MDATAE_OFFSET 8\n#define AVR32_USBB_UECON4_MDATAE_SIZE 1\n#define AVR32_USBB_UECON4_NAKINE 4\n#define AVR32_USBB_UECON4_NAKINE_MASK 0x00000010\n#define AVR32_USBB_UECON4_NAKINE_OFFSET 4\n#define AVR32_USBB_UECON4_NAKINE_SIZE 1\n#define AVR32_USBB_UECON4_NAKOUTE 3\n#define AVR32_USBB_UECON4_NAKOUTE_MASK 0x00000008\n#define AVR32_USBB_UECON4_NAKOUTE_OFFSET 3\n#define AVR32_USBB_UECON4_NAKOUTE_SIZE 1\n#define AVR32_USBB_UECON4_NBUSYBKE 12\n#define AVR32_USBB_UECON4_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UECON4_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UECON4_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UECON4_NYETDIS 17\n#define AVR32_USBB_UECON4_NYETDIS_MASK 0x00020000\n#define AVR32_USBB_UECON4_NYETDIS_OFFSET 17\n#define AVR32_USBB_UECON4_NYETDIS_SIZE 1\n#define AVR32_USBB_UECON4_OVERFE 5\n#define AVR32_USBB_UECON4_OVERFE_MASK 0x00000020\n#define AVR32_USBB_UECON4_OVERFE_OFFSET 5\n#define AVR32_USBB_UECON4_OVERFE_SIZE 1\n#define AVR32_USBB_UECON4_RSTDT 18\n#define AVR32_USBB_UECON4_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UECON4_RSTDT_OFFSET 18\n#define AVR32_USBB_UECON4_RSTDT_SIZE 1\n#define AVR32_USBB_UECON4_RXOUTE 1\n#define AVR32_USBB_UECON4_RXOUTE_MASK 0x00000002\n#define AVR32_USBB_UECON4_RXOUTE_OFFSET 1\n#define AVR32_USBB_UECON4_RXOUTE_SIZE 1\n#define AVR32_USBB_UECON4_RXSTPE 2\n#define AVR32_USBB_UECON4_RXSTPE_MASK 0x00000004\n#define AVR32_USBB_UECON4_RXSTPE_OFFSET 2\n#define AVR32_USBB_UECON4_RXSTPE_SIZE 1\n#define AVR32_USBB_UECON4_SHORTPACKETE 7\n#define AVR32_USBB_UECON4_SHORTPACKETE_MASK 0x00000080\n#define AVR32_USBB_UECON4_SHORTPACKETE_OFFSET 7\n#define AVR32_USBB_UECON4_SHORTPACKETE_SIZE 1\n#define AVR32_USBB_UECON4_STALLEDE 6\n#define AVR32_USBB_UECON4_STALLEDE_MASK 0x00000040\n#define AVR32_USBB_UECON4_STALLEDE_OFFSET 6\n#define AVR32_USBB_UECON4_STALLEDE_SIZE 1\n#define AVR32_USBB_UECON4_STALLRQ 19\n#define AVR32_USBB_UECON4_STALLRQ_MASK 0x00080000\n#define AVR32_USBB_UECON4_STALLRQ_OFFSET 19\n#define AVR32_USBB_UECON4_STALLRQ_SIZE 1\n#define AVR32_USBB_UECON4_TXINE 0\n#define AVR32_USBB_UECON4_TXINE_MASK 0x00000001\n#define AVR32_USBB_UECON4_TXINE_OFFSET 0\n#define AVR32_USBB_UECON4_TXINE_SIZE 1\n#define AVR32_USBB_UECON5 0x000001d4\n#define AVR32_USBB_UECON5CLR 0x00000234\n#define AVR32_USBB_UECON5CLR_DATAXEC 9\n#define AVR32_USBB_UECON5CLR_DATAXEC_MASK 0x00000200\n#define AVR32_USBB_UECON5CLR_DATAXEC_OFFSET 9\n#define AVR32_USBB_UECON5CLR_DATAXEC_SIZE 1\n#define AVR32_USBB_UECON5CLR_EPDISHDMAC 16\n#define AVR32_USBB_UECON5CLR_EPDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UECON5CLR_EPDISHDMAC_OFFSET 16\n#define AVR32_USBB_UECON5CLR_EPDISHDMAC_SIZE 1\n#define AVR32_USBB_UECON5CLR_ERRORTRANSEC 10\n#define AVR32_USBB_UECON5CLR_ERRORTRANSEC_MASK 0x00000400\n#define AVR32_USBB_UECON5CLR_ERRORTRANSEC_OFFSET 10\n#define AVR32_USBB_UECON5CLR_ERRORTRANSEC_SIZE 1\n#define AVR32_USBB_UECON5CLR_FIFOCONC 14\n#define AVR32_USBB_UECON5CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UECON5CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UECON5CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UECON5CLR_MDATAEC 8\n#define AVR32_USBB_UECON5CLR_MDATAEC_MASK 0x00000100\n#define AVR32_USBB_UECON5CLR_MDATAEC_OFFSET 8\n#define AVR32_USBB_UECON5CLR_MDATAEC_SIZE 1\n#define AVR32_USBB_UECON5CLR_NAKINEC 4\n#define AVR32_USBB_UECON5CLR_NAKINEC_MASK 0x00000010\n#define AVR32_USBB_UECON5CLR_NAKINEC_OFFSET 4\n#define AVR32_USBB_UECON5CLR_NAKINEC_SIZE 1\n#define AVR32_USBB_UECON5CLR_NAKOUTEC 3\n#define AVR32_USBB_UECON5CLR_NAKOUTEC_MASK 0x00000008\n#define AVR32_USBB_UECON5CLR_NAKOUTEC_OFFSET 3\n#define AVR32_USBB_UECON5CLR_NAKOUTEC_SIZE 1\n#define AVR32_USBB_UECON5CLR_NBUSYBKEC 12\n#define AVR32_USBB_UECON5CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UECON5CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UECON5CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UECON5CLR_NYETDISC 17\n#define AVR32_USBB_UECON5CLR_NYETDISC_MASK 0x00020000\n#define AVR32_USBB_UECON5CLR_NYETDISC_OFFSET 17\n#define AVR32_USBB_UECON5CLR_NYETDISC_SIZE 1\n#define AVR32_USBB_UECON5CLR_OVERFEC 5\n#define AVR32_USBB_UECON5CLR_OVERFEC_MASK 0x00000020\n#define AVR32_USBB_UECON5CLR_OVERFEC_OFFSET 5\n#define AVR32_USBB_UECON5CLR_OVERFEC_SIZE 1\n#define AVR32_USBB_UECON5CLR_RXOUTEC 1\n#define AVR32_USBB_UECON5CLR_RXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UECON5CLR_RXOUTEC_OFFSET 1\n#define AVR32_USBB_UECON5CLR_RXOUTEC_SIZE 1\n#define AVR32_USBB_UECON5CLR_RXSTPEC 2\n#define AVR32_USBB_UECON5CLR_RXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UECON5CLR_RXSTPEC_OFFSET 2\n#define AVR32_USBB_UECON5CLR_RXSTPEC_SIZE 1\n#define AVR32_USBB_UECON5CLR_SHORTPACKETEC 7\n#define AVR32_USBB_UECON5CLR_SHORTPACKETEC_MASK 0x00000080\n#define AVR32_USBB_UECON5CLR_SHORTPACKETEC_OFFSET 7\n#define AVR32_USBB_UECON5CLR_SHORTPACKETEC_SIZE 1\n#define AVR32_USBB_UECON5CLR_STALLEDEC 6\n#define AVR32_USBB_UECON5CLR_STALLEDEC_MASK 0x00000040\n#define AVR32_USBB_UECON5CLR_STALLEDEC_OFFSET 6\n#define AVR32_USBB_UECON5CLR_STALLEDEC_SIZE 1\n#define AVR32_USBB_UECON5CLR_STALLRQC 19\n#define AVR32_USBB_UECON5CLR_STALLRQC_MASK 0x00080000\n#define AVR32_USBB_UECON5CLR_STALLRQC_OFFSET 19\n#define AVR32_USBB_UECON5CLR_STALLRQC_SIZE 1\n#define AVR32_USBB_UECON5CLR_TXINEC 0\n#define AVR32_USBB_UECON5CLR_TXINEC_MASK 0x00000001\n#define AVR32_USBB_UECON5CLR_TXINEC_OFFSET 0\n#define AVR32_USBB_UECON5CLR_TXINEC_SIZE 1\n#define AVR32_USBB_UECON5SET 0x00000204\n#define AVR32_USBB_UECON5SET_DATAXES 9\n#define AVR32_USBB_UECON5SET_DATAXES_MASK 0x00000200\n#define AVR32_USBB_UECON5SET_DATAXES_OFFSET 9\n#define AVR32_USBB_UECON5SET_DATAXES_SIZE 1\n#define AVR32_USBB_UECON5SET_EPDISHDMAS 16\n#define AVR32_USBB_UECON5SET_EPDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UECON5SET_EPDISHDMAS_OFFSET 16\n#define AVR32_USBB_UECON5SET_EPDISHDMAS_SIZE 1\n#define AVR32_USBB_UECON5SET_ERRORTRANSES 10\n#define AVR32_USBB_UECON5SET_ERRORTRANSES_MASK 0x00000400\n#define AVR32_USBB_UECON5SET_ERRORTRANSES_OFFSET 10\n#define AVR32_USBB_UECON5SET_ERRORTRANSES_SIZE 1\n#define AVR32_USBB_UECON5SET_KILLBKS 13\n#define AVR32_USBB_UECON5SET_KILLBKS_MASK 0x00002000\n#define AVR32_USBB_UECON5SET_KILLBKS_OFFSET 13\n#define AVR32_USBB_UECON5SET_KILLBKS_SIZE 1\n#define AVR32_USBB_UECON5SET_MDATAES 8\n#define AVR32_USBB_UECON5SET_MDATAES_MASK 0x00000100\n#define AVR32_USBB_UECON5SET_MDATAES_OFFSET 8\n#define AVR32_USBB_UECON5SET_MDATAES_SIZE 1\n#define AVR32_USBB_UECON5SET_NAKINES 4\n#define AVR32_USBB_UECON5SET_NAKINES_MASK 0x00000010\n#define AVR32_USBB_UECON5SET_NAKINES_OFFSET 4\n#define AVR32_USBB_UECON5SET_NAKINES_SIZE 1\n#define AVR32_USBB_UECON5SET_NAKOUTES 3\n#define AVR32_USBB_UECON5SET_NAKOUTES_MASK 0x00000008\n#define AVR32_USBB_UECON5SET_NAKOUTES_OFFSET 3\n#define AVR32_USBB_UECON5SET_NAKOUTES_SIZE 1\n#define AVR32_USBB_UECON5SET_NBUSYBKES 12\n#define AVR32_USBB_UECON5SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UECON5SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UECON5SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UECON5SET_NYETDISS 17\n#define AVR32_USBB_UECON5SET_NYETDISS_MASK 0x00020000\n#define AVR32_USBB_UECON5SET_NYETDISS_OFFSET 17\n#define AVR32_USBB_UECON5SET_NYETDISS_SIZE 1\n#define AVR32_USBB_UECON5SET_OVERFES 5\n#define AVR32_USBB_UECON5SET_OVERFES_MASK 0x00000020\n#define AVR32_USBB_UECON5SET_OVERFES_OFFSET 5\n#define AVR32_USBB_UECON5SET_OVERFES_SIZE 1\n#define AVR32_USBB_UECON5SET_RSTDTS 18\n#define AVR32_USBB_UECON5SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UECON5SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UECON5SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UECON5SET_RXOUTES 1\n#define AVR32_USBB_UECON5SET_RXOUTES_MASK 0x00000002\n#define AVR32_USBB_UECON5SET_RXOUTES_OFFSET 1\n#define AVR32_USBB_UECON5SET_RXOUTES_SIZE 1\n#define AVR32_USBB_UECON5SET_RXSTPES 2\n#define AVR32_USBB_UECON5SET_RXSTPES_MASK 0x00000004\n#define AVR32_USBB_UECON5SET_RXSTPES_OFFSET 2\n#define AVR32_USBB_UECON5SET_RXSTPES_SIZE 1\n#define AVR32_USBB_UECON5SET_SHORTPACKETES 7\n#define AVR32_USBB_UECON5SET_SHORTPACKETES_MASK 0x00000080\n#define AVR32_USBB_UECON5SET_SHORTPACKETES_OFFSET 7\n#define AVR32_USBB_UECON5SET_SHORTPACKETES_SIZE 1\n#define AVR32_USBB_UECON5SET_STALLEDES 6\n#define AVR32_USBB_UECON5SET_STALLEDES_MASK 0x00000040\n#define AVR32_USBB_UECON5SET_STALLEDES_OFFSET 6\n#define AVR32_USBB_UECON5SET_STALLEDES_SIZE 1\n#define AVR32_USBB_UECON5SET_STALLRQS 19\n#define AVR32_USBB_UECON5SET_STALLRQS_MASK 0x00080000\n#define AVR32_USBB_UECON5SET_STALLRQS_OFFSET 19\n#define AVR32_USBB_UECON5SET_STALLRQS_SIZE 1\n#define AVR32_USBB_UECON5SET_TXINES 0\n#define AVR32_USBB_UECON5SET_TXINES_MASK 0x00000001\n#define AVR32_USBB_UECON5SET_TXINES_OFFSET 0\n#define AVR32_USBB_UECON5SET_TXINES_SIZE 1\n#define AVR32_USBB_UECON5_DATAXE 9\n#define AVR32_USBB_UECON5_DATAXE_MASK 0x00000200\n#define AVR32_USBB_UECON5_DATAXE_OFFSET 9\n#define AVR32_USBB_UECON5_DATAXE_SIZE 1\n#define AVR32_USBB_UECON5_EPDISHDMA 16\n#define AVR32_USBB_UECON5_EPDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UECON5_EPDISHDMA_OFFSET 16\n#define AVR32_USBB_UECON5_EPDISHDMA_SIZE 1\n#define AVR32_USBB_UECON5_ERRORTRANSE 10\n#define AVR32_USBB_UECON5_ERRORTRANSE_MASK 0x00000400\n#define AVR32_USBB_UECON5_ERRORTRANSE_OFFSET 10\n#define AVR32_USBB_UECON5_ERRORTRANSE_SIZE 1\n#define AVR32_USBB_UECON5_FIFOCON 14\n#define AVR32_USBB_UECON5_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UECON5_FIFOCON_OFFSET 14\n#define AVR32_USBB_UECON5_FIFOCON_SIZE 1\n#define AVR32_USBB_UECON5_KILLBK 13\n#define AVR32_USBB_UECON5_KILLBK_MASK 0x00002000\n#define AVR32_USBB_UECON5_KILLBK_OFFSET 13\n#define AVR32_USBB_UECON5_KILLBK_SIZE 1\n#define AVR32_USBB_UECON5_MDATAE 8\n#define AVR32_USBB_UECON5_MDATAE_MASK 0x00000100\n#define AVR32_USBB_UECON5_MDATAE_OFFSET 8\n#define AVR32_USBB_UECON5_MDATAE_SIZE 1\n#define AVR32_USBB_UECON5_NAKINE 4\n#define AVR32_USBB_UECON5_NAKINE_MASK 0x00000010\n#define AVR32_USBB_UECON5_NAKINE_OFFSET 4\n#define AVR32_USBB_UECON5_NAKINE_SIZE 1\n#define AVR32_USBB_UECON5_NAKOUTE 3\n#define AVR32_USBB_UECON5_NAKOUTE_MASK 0x00000008\n#define AVR32_USBB_UECON5_NAKOUTE_OFFSET 3\n#define AVR32_USBB_UECON5_NAKOUTE_SIZE 1\n#define AVR32_USBB_UECON5_NBUSYBKE 12\n#define AVR32_USBB_UECON5_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UECON5_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UECON5_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UECON5_NYETDIS 17\n#define AVR32_USBB_UECON5_NYETDIS_MASK 0x00020000\n#define AVR32_USBB_UECON5_NYETDIS_OFFSET 17\n#define AVR32_USBB_UECON5_NYETDIS_SIZE 1\n#define AVR32_USBB_UECON5_OVERFE 5\n#define AVR32_USBB_UECON5_OVERFE_MASK 0x00000020\n#define AVR32_USBB_UECON5_OVERFE_OFFSET 5\n#define AVR32_USBB_UECON5_OVERFE_SIZE 1\n#define AVR32_USBB_UECON5_RSTDT 18\n#define AVR32_USBB_UECON5_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UECON5_RSTDT_OFFSET 18\n#define AVR32_USBB_UECON5_RSTDT_SIZE 1\n#define AVR32_USBB_UECON5_RXOUTE 1\n#define AVR32_USBB_UECON5_RXOUTE_MASK 0x00000002\n#define AVR32_USBB_UECON5_RXOUTE_OFFSET 1\n#define AVR32_USBB_UECON5_RXOUTE_SIZE 1\n#define AVR32_USBB_UECON5_RXSTPE 2\n#define AVR32_USBB_UECON5_RXSTPE_MASK 0x00000004\n#define AVR32_USBB_UECON5_RXSTPE_OFFSET 2\n#define AVR32_USBB_UECON5_RXSTPE_SIZE 1\n#define AVR32_USBB_UECON5_SHORTPACKETE 7\n#define AVR32_USBB_UECON5_SHORTPACKETE_MASK 0x00000080\n#define AVR32_USBB_UECON5_SHORTPACKETE_OFFSET 7\n#define AVR32_USBB_UECON5_SHORTPACKETE_SIZE 1\n#define AVR32_USBB_UECON5_STALLEDE 6\n#define AVR32_USBB_UECON5_STALLEDE_MASK 0x00000040\n#define AVR32_USBB_UECON5_STALLEDE_OFFSET 6\n#define AVR32_USBB_UECON5_STALLEDE_SIZE 1\n#define AVR32_USBB_UECON5_STALLRQ 19\n#define AVR32_USBB_UECON5_STALLRQ_MASK 0x00080000\n#define AVR32_USBB_UECON5_STALLRQ_OFFSET 19\n#define AVR32_USBB_UECON5_STALLRQ_SIZE 1\n#define AVR32_USBB_UECON5_TXINE 0\n#define AVR32_USBB_UECON5_TXINE_MASK 0x00000001\n#define AVR32_USBB_UECON5_TXINE_OFFSET 0\n#define AVR32_USBB_UECON5_TXINE_SIZE 1\n#define AVR32_USBB_UECON6 0x000001d8\n#define AVR32_USBB_UECON6CLR 0x00000238\n#define AVR32_USBB_UECON6CLR_DATAXEC 9\n#define AVR32_USBB_UECON6CLR_DATAXEC_MASK 0x00000200\n#define AVR32_USBB_UECON6CLR_DATAXEC_OFFSET 9\n#define AVR32_USBB_UECON6CLR_DATAXEC_SIZE 1\n#define AVR32_USBB_UECON6CLR_EPDISHDMAC 16\n#define AVR32_USBB_UECON6CLR_EPDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UECON6CLR_EPDISHDMAC_OFFSET 16\n#define AVR32_USBB_UECON6CLR_EPDISHDMAC_SIZE 1\n#define AVR32_USBB_UECON6CLR_ERRORTRANSEC 10\n#define AVR32_USBB_UECON6CLR_ERRORTRANSEC_MASK 0x00000400\n#define AVR32_USBB_UECON6CLR_ERRORTRANSEC_OFFSET 10\n#define AVR32_USBB_UECON6CLR_ERRORTRANSEC_SIZE 1\n#define AVR32_USBB_UECON6CLR_FIFOCONC 14\n#define AVR32_USBB_UECON6CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UECON6CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UECON6CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UECON6CLR_MDATAEC 8\n#define AVR32_USBB_UECON6CLR_MDATAEC_MASK 0x00000100\n#define AVR32_USBB_UECON6CLR_MDATAEC_OFFSET 8\n#define AVR32_USBB_UECON6CLR_MDATAEC_SIZE 1\n#define AVR32_USBB_UECON6CLR_NAKINEC 4\n#define AVR32_USBB_UECON6CLR_NAKINEC_MASK 0x00000010\n#define AVR32_USBB_UECON6CLR_NAKINEC_OFFSET 4\n#define AVR32_USBB_UECON6CLR_NAKINEC_SIZE 1\n#define AVR32_USBB_UECON6CLR_NAKOUTEC 3\n#define AVR32_USBB_UECON6CLR_NAKOUTEC_MASK 0x00000008\n#define AVR32_USBB_UECON6CLR_NAKOUTEC_OFFSET 3\n#define AVR32_USBB_UECON6CLR_NAKOUTEC_SIZE 1\n#define AVR32_USBB_UECON6CLR_NBUSYBKEC 12\n#define AVR32_USBB_UECON6CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UECON6CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UECON6CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UECON6CLR_NYETDISC 17\n#define AVR32_USBB_UECON6CLR_NYETDISC_MASK 0x00020000\n#define AVR32_USBB_UECON6CLR_NYETDISC_OFFSET 17\n#define AVR32_USBB_UECON6CLR_NYETDISC_SIZE 1\n#define AVR32_USBB_UECON6CLR_OVERFEC 5\n#define AVR32_USBB_UECON6CLR_OVERFEC_MASK 0x00000020\n#define AVR32_USBB_UECON6CLR_OVERFEC_OFFSET 5\n#define AVR32_USBB_UECON6CLR_OVERFEC_SIZE 1\n#define AVR32_USBB_UECON6CLR_RXOUTEC 1\n#define AVR32_USBB_UECON6CLR_RXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UECON6CLR_RXOUTEC_OFFSET 1\n#define AVR32_USBB_UECON6CLR_RXOUTEC_SIZE 1\n#define AVR32_USBB_UECON6CLR_RXSTPEC 2\n#define AVR32_USBB_UECON6CLR_RXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UECON6CLR_RXSTPEC_OFFSET 2\n#define AVR32_USBB_UECON6CLR_RXSTPEC_SIZE 1\n#define AVR32_USBB_UECON6CLR_SHORTPACKETEC 7\n#define AVR32_USBB_UECON6CLR_SHORTPACKETEC_MASK 0x00000080\n#define AVR32_USBB_UECON6CLR_SHORTPACKETEC_OFFSET 7\n#define AVR32_USBB_UECON6CLR_SHORTPACKETEC_SIZE 1\n#define AVR32_USBB_UECON6CLR_STALLEDEC 6\n#define AVR32_USBB_UECON6CLR_STALLEDEC_MASK 0x00000040\n#define AVR32_USBB_UECON6CLR_STALLEDEC_OFFSET 6\n#define AVR32_USBB_UECON6CLR_STALLEDEC_SIZE 1\n#define AVR32_USBB_UECON6CLR_STALLRQC 19\n#define AVR32_USBB_UECON6CLR_STALLRQC_MASK 0x00080000\n#define AVR32_USBB_UECON6CLR_STALLRQC_OFFSET 19\n#define AVR32_USBB_UECON6CLR_STALLRQC_SIZE 1\n#define AVR32_USBB_UECON6CLR_TXINEC 0\n#define AVR32_USBB_UECON6CLR_TXINEC_MASK 0x00000001\n#define AVR32_USBB_UECON6CLR_TXINEC_OFFSET 0\n#define AVR32_USBB_UECON6CLR_TXINEC_SIZE 1\n#define AVR32_USBB_UECON6SET 0x00000208\n#define AVR32_USBB_UECON6SET_DATAXES 9\n#define AVR32_USBB_UECON6SET_DATAXES_MASK 0x00000200\n#define AVR32_USBB_UECON6SET_DATAXES_OFFSET 9\n#define AVR32_USBB_UECON6SET_DATAXES_SIZE 1\n#define AVR32_USBB_UECON6SET_EPDISHDMAS 16\n#define AVR32_USBB_UECON6SET_EPDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UECON6SET_EPDISHDMAS_OFFSET 16\n#define AVR32_USBB_UECON6SET_EPDISHDMAS_SIZE 1\n#define AVR32_USBB_UECON6SET_ERRORTRANSES 10\n#define AVR32_USBB_UECON6SET_ERRORTRANSES_MASK 0x00000400\n#define AVR32_USBB_UECON6SET_ERRORTRANSES_OFFSET 10\n#define AVR32_USBB_UECON6SET_ERRORTRANSES_SIZE 1\n#define AVR32_USBB_UECON6SET_KILLBKS 13\n#define AVR32_USBB_UECON6SET_KILLBKS_MASK 0x00002000\n#define AVR32_USBB_UECON6SET_KILLBKS_OFFSET 13\n#define AVR32_USBB_UECON6SET_KILLBKS_SIZE 1\n#define AVR32_USBB_UECON6SET_MDATAES 8\n#define AVR32_USBB_UECON6SET_MDATAES_MASK 0x00000100\n#define AVR32_USBB_UECON6SET_MDATAES_OFFSET 8\n#define AVR32_USBB_UECON6SET_MDATAES_SIZE 1\n#define AVR32_USBB_UECON6SET_NAKINES 4\n#define AVR32_USBB_UECON6SET_NAKINES_MASK 0x00000010\n#define AVR32_USBB_UECON6SET_NAKINES_OFFSET 4\n#define AVR32_USBB_UECON6SET_NAKINES_SIZE 1\n#define AVR32_USBB_UECON6SET_NAKOUTES 3\n#define AVR32_USBB_UECON6SET_NAKOUTES_MASK 0x00000008\n#define AVR32_USBB_UECON6SET_NAKOUTES_OFFSET 3\n#define AVR32_USBB_UECON6SET_NAKOUTES_SIZE 1\n#define AVR32_USBB_UECON6SET_NBUSYBKES 12\n#define AVR32_USBB_UECON6SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UECON6SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UECON6SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UECON6SET_NYETDISS 17\n#define AVR32_USBB_UECON6SET_NYETDISS_MASK 0x00020000\n#define AVR32_USBB_UECON6SET_NYETDISS_OFFSET 17\n#define AVR32_USBB_UECON6SET_NYETDISS_SIZE 1\n#define AVR32_USBB_UECON6SET_OVERFES 5\n#define AVR32_USBB_UECON6SET_OVERFES_MASK 0x00000020\n#define AVR32_USBB_UECON6SET_OVERFES_OFFSET 5\n#define AVR32_USBB_UECON6SET_OVERFES_SIZE 1\n#define AVR32_USBB_UECON6SET_RSTDTS 18\n#define AVR32_USBB_UECON6SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UECON6SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UECON6SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UECON6SET_RXOUTES 1\n#define AVR32_USBB_UECON6SET_RXOUTES_MASK 0x00000002\n#define AVR32_USBB_UECON6SET_RXOUTES_OFFSET 1\n#define AVR32_USBB_UECON6SET_RXOUTES_SIZE 1\n#define AVR32_USBB_UECON6SET_RXSTPES 2\n#define AVR32_USBB_UECON6SET_RXSTPES_MASK 0x00000004\n#define AVR32_USBB_UECON6SET_RXSTPES_OFFSET 2\n#define AVR32_USBB_UECON6SET_RXSTPES_SIZE 1\n#define AVR32_USBB_UECON6SET_SHORTPACKETES 7\n#define AVR32_USBB_UECON6SET_SHORTPACKETES_MASK 0x00000080\n#define AVR32_USBB_UECON6SET_SHORTPACKETES_OFFSET 7\n#define AVR32_USBB_UECON6SET_SHORTPACKETES_SIZE 1\n#define AVR32_USBB_UECON6SET_STALLEDES 6\n#define AVR32_USBB_UECON6SET_STALLEDES_MASK 0x00000040\n#define AVR32_USBB_UECON6SET_STALLEDES_OFFSET 6\n#define AVR32_USBB_UECON6SET_STALLEDES_SIZE 1\n#define AVR32_USBB_UECON6SET_STALLRQS 19\n#define AVR32_USBB_UECON6SET_STALLRQS_MASK 0x00080000\n#define AVR32_USBB_UECON6SET_STALLRQS_OFFSET 19\n#define AVR32_USBB_UECON6SET_STALLRQS_SIZE 1\n#define AVR32_USBB_UECON6SET_TXINES 0\n#define AVR32_USBB_UECON6SET_TXINES_MASK 0x00000001\n#define AVR32_USBB_UECON6SET_TXINES_OFFSET 0\n#define AVR32_USBB_UECON6SET_TXINES_SIZE 1\n#define AVR32_USBB_UECON6_DATAXE 9\n#define AVR32_USBB_UECON6_DATAXE_MASK 0x00000200\n#define AVR32_USBB_UECON6_DATAXE_OFFSET 9\n#define AVR32_USBB_UECON6_DATAXE_SIZE 1\n#define AVR32_USBB_UECON6_EPDISHDMA 16\n#define AVR32_USBB_UECON6_EPDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UECON6_EPDISHDMA_OFFSET 16\n#define AVR32_USBB_UECON6_EPDISHDMA_SIZE 1\n#define AVR32_USBB_UECON6_ERRORTRANSE 10\n#define AVR32_USBB_UECON6_ERRORTRANSE_MASK 0x00000400\n#define AVR32_USBB_UECON6_ERRORTRANSE_OFFSET 10\n#define AVR32_USBB_UECON6_ERRORTRANSE_SIZE 1\n#define AVR32_USBB_UECON6_FIFOCON 14\n#define AVR32_USBB_UECON6_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UECON6_FIFOCON_OFFSET 14\n#define AVR32_USBB_UECON6_FIFOCON_SIZE 1\n#define AVR32_USBB_UECON6_KILLBK 13\n#define AVR32_USBB_UECON6_KILLBK_MASK 0x00002000\n#define AVR32_USBB_UECON6_KILLBK_OFFSET 13\n#define AVR32_USBB_UECON6_KILLBK_SIZE 1\n#define AVR32_USBB_UECON6_MDATAE 8\n#define AVR32_USBB_UECON6_MDATAE_MASK 0x00000100\n#define AVR32_USBB_UECON6_MDATAE_OFFSET 8\n#define AVR32_USBB_UECON6_MDATAE_SIZE 1\n#define AVR32_USBB_UECON6_NAKINE 4\n#define AVR32_USBB_UECON6_NAKINE_MASK 0x00000010\n#define AVR32_USBB_UECON6_NAKINE_OFFSET 4\n#define AVR32_USBB_UECON6_NAKINE_SIZE 1\n#define AVR32_USBB_UECON6_NAKOUTE 3\n#define AVR32_USBB_UECON6_NAKOUTE_MASK 0x00000008\n#define AVR32_USBB_UECON6_NAKOUTE_OFFSET 3\n#define AVR32_USBB_UECON6_NAKOUTE_SIZE 1\n#define AVR32_USBB_UECON6_NBUSYBKE 12\n#define AVR32_USBB_UECON6_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UECON6_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UECON6_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UECON6_NYETDIS 17\n#define AVR32_USBB_UECON6_NYETDIS_MASK 0x00020000\n#define AVR32_USBB_UECON6_NYETDIS_OFFSET 17\n#define AVR32_USBB_UECON6_NYETDIS_SIZE 1\n#define AVR32_USBB_UECON6_OVERFE 5\n#define AVR32_USBB_UECON6_OVERFE_MASK 0x00000020\n#define AVR32_USBB_UECON6_OVERFE_OFFSET 5\n#define AVR32_USBB_UECON6_OVERFE_SIZE 1\n#define AVR32_USBB_UECON6_RSTDT 18\n#define AVR32_USBB_UECON6_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UECON6_RSTDT_OFFSET 18\n#define AVR32_USBB_UECON6_RSTDT_SIZE 1\n#define AVR32_USBB_UECON6_RXOUTE 1\n#define AVR32_USBB_UECON6_RXOUTE_MASK 0x00000002\n#define AVR32_USBB_UECON6_RXOUTE_OFFSET 1\n#define AVR32_USBB_UECON6_RXOUTE_SIZE 1\n#define AVR32_USBB_UECON6_RXSTPE 2\n#define AVR32_USBB_UECON6_RXSTPE_MASK 0x00000004\n#define AVR32_USBB_UECON6_RXSTPE_OFFSET 2\n#define AVR32_USBB_UECON6_RXSTPE_SIZE 1\n#define AVR32_USBB_UECON6_SHORTPACKETE 7\n#define AVR32_USBB_UECON6_SHORTPACKETE_MASK 0x00000080\n#define AVR32_USBB_UECON6_SHORTPACKETE_OFFSET 7\n#define AVR32_USBB_UECON6_SHORTPACKETE_SIZE 1\n#define AVR32_USBB_UECON6_STALLEDE 6\n#define AVR32_USBB_UECON6_STALLEDE_MASK 0x00000040\n#define AVR32_USBB_UECON6_STALLEDE_OFFSET 6\n#define AVR32_USBB_UECON6_STALLEDE_SIZE 1\n#define AVR32_USBB_UECON6_STALLRQ 19\n#define AVR32_USBB_UECON6_STALLRQ_MASK 0x00080000\n#define AVR32_USBB_UECON6_STALLRQ_OFFSET 19\n#define AVR32_USBB_UECON6_STALLRQ_SIZE 1\n#define AVR32_USBB_UECON6_TXINE 0\n#define AVR32_USBB_UECON6_TXINE_MASK 0x00000001\n#define AVR32_USBB_UECON6_TXINE_OFFSET 0\n#define AVR32_USBB_UECON6_TXINE_SIZE 1\n#define AVR32_USBB_UEDAT0 0x00000250\n#define AVR32_USBB_UEDAT0_EP_DATA 0\n#define AVR32_USBB_UEDAT0_EP_DATA_MASK 0xffffffff\n#define AVR32_USBB_UEDAT0_EP_DATA_OFFSET 0\n#define AVR32_USBB_UEDAT0_EP_DATA_SIZE 32\n#define AVR32_USBB_UEDAT1 0x00000254\n#define AVR32_USBB_UEDAT1_EP_DATA 0\n#define AVR32_USBB_UEDAT1_EP_DATA_MASK 0xffffffff\n#define AVR32_USBB_UEDAT1_EP_DATA_OFFSET 0\n#define AVR32_USBB_UEDAT1_EP_DATA_SIZE 32\n#define AVR32_USBB_UEDAT2 0x00000258\n#define AVR32_USBB_UEDAT2_EP_DATA 0\n#define AVR32_USBB_UEDAT2_EP_DATA_MASK 0xffffffff\n#define AVR32_USBB_UEDAT2_EP_DATA_OFFSET 0\n#define AVR32_USBB_UEDAT2_EP_DATA_SIZE 32\n#define AVR32_USBB_UEDAT3 0x0000025c\n#define AVR32_USBB_UEDAT3_EP_DATA 0\n#define AVR32_USBB_UEDAT3_EP_DATA_MASK 0xffffffff\n#define AVR32_USBB_UEDAT3_EP_DATA_OFFSET 0\n#define AVR32_USBB_UEDAT3_EP_DATA_SIZE 32\n#define AVR32_USBB_UEDAT4 0x00000260\n#define AVR32_USBB_UEDAT4_EP_DATA 0\n#define AVR32_USBB_UEDAT4_EP_DATA_MASK 0xffffffff\n#define AVR32_USBB_UEDAT4_EP_DATA_OFFSET 0\n#define AVR32_USBB_UEDAT4_EP_DATA_SIZE 32\n#define AVR32_USBB_UEDAT5 0x00000264\n#define AVR32_USBB_UEDAT5_EP_DATA 0\n#define AVR32_USBB_UEDAT5_EP_DATA_MASK 0xffffffff\n#define AVR32_USBB_UEDAT5_EP_DATA_OFFSET 0\n#define AVR32_USBB_UEDAT5_EP_DATA_SIZE 32\n#define AVR32_USBB_UEDAT6 0x00000268\n#define AVR32_USBB_UEDAT6_EP_DATA 0\n#define AVR32_USBB_UEDAT6_EP_DATA_MASK 0xffffffff\n#define AVR32_USBB_UEDAT6_EP_DATA_OFFSET 0\n#define AVR32_USBB_UEDAT6_EP_DATA_SIZE 32\n#define AVR32_USBB_UERST 0x0000001c\n#define AVR32_USBB_UERST_EPEN0 0\n#define AVR32_USBB_UERST_EPEN0_MASK 0x00000001\n#define AVR32_USBB_UERST_EPEN0_OFFSET 0\n#define AVR32_USBB_UERST_EPEN0_SIZE 1\n#define AVR32_USBB_UERST_EPEN1 1\n#define AVR32_USBB_UERST_EPEN1_MASK 0x00000002\n#define AVR32_USBB_UERST_EPEN1_OFFSET 1\n#define AVR32_USBB_UERST_EPEN1_SIZE 1\n#define AVR32_USBB_UERST_EPEN2 2\n#define AVR32_USBB_UERST_EPEN2_MASK 0x00000004\n#define AVR32_USBB_UERST_EPEN2_OFFSET 2\n#define AVR32_USBB_UERST_EPEN2_SIZE 1\n#define AVR32_USBB_UERST_EPEN3 3\n#define AVR32_USBB_UERST_EPEN3_MASK 0x00000008\n#define AVR32_USBB_UERST_EPEN3_OFFSET 3\n#define AVR32_USBB_UERST_EPEN3_SIZE 1\n#define AVR32_USBB_UERST_EPEN4 4\n#define AVR32_USBB_UERST_EPEN4_MASK 0x00000010\n#define AVR32_USBB_UERST_EPEN4_OFFSET 4\n#define AVR32_USBB_UERST_EPEN4_SIZE 1\n#define AVR32_USBB_UERST_EPEN5 5\n#define AVR32_USBB_UERST_EPEN5_MASK 0x00000020\n#define AVR32_USBB_UERST_EPEN5_OFFSET 5\n#define AVR32_USBB_UERST_EPEN5_SIZE 1\n#define AVR32_USBB_UERST_EPEN6 6\n#define AVR32_USBB_UERST_EPEN6_MASK 0x00000040\n#define AVR32_USBB_UERST_EPEN6_OFFSET 6\n#define AVR32_USBB_UERST_EPEN6_SIZE 1\n#define AVR32_USBB_UERST_EPRST0 16\n#define AVR32_USBB_UERST_EPRST0_MASK 0x00010000\n#define AVR32_USBB_UERST_EPRST0_OFFSET 16\n#define AVR32_USBB_UERST_EPRST0_SIZE 1\n#define AVR32_USBB_UERST_EPRST1 17\n#define AVR32_USBB_UERST_EPRST1_MASK 0x00020000\n#define AVR32_USBB_UERST_EPRST1_OFFSET 17\n#define AVR32_USBB_UERST_EPRST1_SIZE 1\n#define AVR32_USBB_UERST_EPRST2 18\n#define AVR32_USBB_UERST_EPRST2_MASK 0x00040000\n#define AVR32_USBB_UERST_EPRST2_OFFSET 18\n#define AVR32_USBB_UERST_EPRST2_SIZE 1\n#define AVR32_USBB_UERST_EPRST3 19\n#define AVR32_USBB_UERST_EPRST3_MASK 0x00080000\n#define AVR32_USBB_UERST_EPRST3_OFFSET 19\n#define AVR32_USBB_UERST_EPRST3_SIZE 1\n#define AVR32_USBB_UERST_EPRST4 20\n#define AVR32_USBB_UERST_EPRST4_MASK 0x00100000\n#define AVR32_USBB_UERST_EPRST4_OFFSET 20\n#define AVR32_USBB_UERST_EPRST4_SIZE 1\n#define AVR32_USBB_UERST_EPRST5 21\n#define AVR32_USBB_UERST_EPRST5_MASK 0x00200000\n#define AVR32_USBB_UERST_EPRST5_OFFSET 21\n#define AVR32_USBB_UERST_EPRST5_SIZE 1\n#define AVR32_USBB_UERST_EPRST6 22\n#define AVR32_USBB_UERST_EPRST6_MASK 0x00400000\n#define AVR32_USBB_UERST_EPRST6_OFFSET 22\n#define AVR32_USBB_UERST_EPRST6_SIZE 1\n#define AVR32_USBB_UESTA0 0x00000130\n#define AVR32_USBB_UESTA0CLR 0x00000160\n#define AVR32_USBB_UESTA0CLR_NAKINIC 4\n#define AVR32_USBB_UESTA0CLR_NAKINIC_MASK 0x00000010\n#define AVR32_USBB_UESTA0CLR_NAKINIC_OFFSET 4\n#define AVR32_USBB_UESTA0CLR_NAKINIC_SIZE 1\n#define AVR32_USBB_UESTA0CLR_NAKOUTIC 3\n#define AVR32_USBB_UESTA0CLR_NAKOUTIC_MASK 0x00000008\n#define AVR32_USBB_UESTA0CLR_NAKOUTIC_OFFSET 3\n#define AVR32_USBB_UESTA0CLR_NAKOUTIC_SIZE 1\n#define AVR32_USBB_UESTA0CLR_OVERFIC 5\n#define AVR32_USBB_UESTA0CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UESTA0CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UESTA0CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UESTA0CLR_RXOUTIC 1\n#define AVR32_USBB_UESTA0CLR_RXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UESTA0CLR_RXOUTIC_OFFSET 1\n#define AVR32_USBB_UESTA0CLR_RXOUTIC_SIZE 1\n#define AVR32_USBB_UESTA0CLR_RXSTPIC 2\n#define AVR32_USBB_UESTA0CLR_RXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UESTA0CLR_RXSTPIC_OFFSET 2\n#define AVR32_USBB_UESTA0CLR_RXSTPIC_SIZE 1\n#define AVR32_USBB_UESTA0CLR_SHORTPACKETC 7\n#define AVR32_USBB_UESTA0CLR_SHORTPACKETC_MASK 0x00000080\n#define AVR32_USBB_UESTA0CLR_SHORTPACKETC_OFFSET 7\n#define AVR32_USBB_UESTA0CLR_SHORTPACKETC_SIZE 1\n#define AVR32_USBB_UESTA0CLR_STALLEDIC 6\n#define AVR32_USBB_UESTA0CLR_STALLEDIC_MASK 0x00000040\n#define AVR32_USBB_UESTA0CLR_STALLEDIC_OFFSET 6\n#define AVR32_USBB_UESTA0CLR_STALLEDIC_SIZE 1\n#define AVR32_USBB_UESTA0CLR_TXINIC 0\n#define AVR32_USBB_UESTA0CLR_TXINIC_MASK 0x00000001\n#define AVR32_USBB_UESTA0CLR_TXINIC_OFFSET 0\n#define AVR32_USBB_UESTA0CLR_TXINIC_SIZE 1\n#define AVR32_USBB_UESTA0SET 0x00000190\n#define AVR32_USBB_UESTA0SET_ERRORTRANSS 10\n#define AVR32_USBB_UESTA0SET_ERRORTRANSS_MASK 0x00000400\n#define AVR32_USBB_UESTA0SET_ERRORTRANSS_OFFSET 10\n#define AVR32_USBB_UESTA0SET_ERRORTRANSS_SIZE 1\n#define AVR32_USBB_UESTA0SET_NAKINIS 4\n#define AVR32_USBB_UESTA0SET_NAKINIS_MASK 0x00000010\n#define AVR32_USBB_UESTA0SET_NAKINIS_OFFSET 4\n#define AVR32_USBB_UESTA0SET_NAKINIS_SIZE 1\n#define AVR32_USBB_UESTA0SET_NAKOUTIS 3\n#define AVR32_USBB_UESTA0SET_NAKOUTIS_MASK 0x00000008\n#define AVR32_USBB_UESTA0SET_NAKOUTIS_OFFSET 3\n#define AVR32_USBB_UESTA0SET_NAKOUTIS_SIZE 1\n#define AVR32_USBB_UESTA0SET_NBUSYBKS 12\n#define AVR32_USBB_UESTA0SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UESTA0SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UESTA0SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UESTA0SET_OVERFIS 5\n#define AVR32_USBB_UESTA0SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UESTA0SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UESTA0SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UESTA0SET_RXOUTIS 1\n#define AVR32_USBB_UESTA0SET_RXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UESTA0SET_RXOUTIS_OFFSET 1\n#define AVR32_USBB_UESTA0SET_RXOUTIS_SIZE 1\n#define AVR32_USBB_UESTA0SET_RXSTPIS 2\n#define AVR32_USBB_UESTA0SET_RXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UESTA0SET_RXSTPIS_OFFSET 2\n#define AVR32_USBB_UESTA0SET_RXSTPIS_SIZE 1\n#define AVR32_USBB_UESTA0SET_SETMDATA 8\n#define AVR32_USBB_UESTA0SET_SETMDATA_MASK 0x00000100\n#define AVR32_USBB_UESTA0SET_SETMDATA_OFFSET 8\n#define AVR32_USBB_UESTA0SET_SETMDATA_SIZE 1\n#define AVR32_USBB_UESTA0SET_SHORTPACKETS 7\n#define AVR32_USBB_UESTA0SET_SHORTPACKETS_MASK 0x00000080\n#define AVR32_USBB_UESTA0SET_SHORTPACKETS_OFFSET 7\n#define AVR32_USBB_UESTA0SET_SHORTPACKETS_SIZE 1\n#define AVR32_USBB_UESTA0SET_STALLEDIS 6\n#define AVR32_USBB_UESTA0SET_STALLEDIS_MASK 0x00000040\n#define AVR32_USBB_UESTA0SET_STALLEDIS_OFFSET 6\n#define AVR32_USBB_UESTA0SET_STALLEDIS_SIZE 1\n#define AVR32_USBB_UESTA0SET_TXINIS 0\n#define AVR32_USBB_UESTA0SET_TXINIS_MASK 0x00000001\n#define AVR32_USBB_UESTA0SET_TXINIS_OFFSET 0\n#define AVR32_USBB_UESTA0SET_TXINIS_SIZE 1\n#define AVR32_USBB_UESTA0_BYCT 20\n#define AVR32_USBB_UESTA0_BYCT_MASK 0x7ff00000\n#define AVR32_USBB_UESTA0_BYCT_OFFSET 20\n#define AVR32_USBB_UESTA0_BYCT_SIZE 11\n#define AVR32_USBB_UESTA0_CFGOK 18\n#define AVR32_USBB_UESTA0_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UESTA0_CFGOK_OFFSET 18\n#define AVR32_USBB_UESTA0_CFGOK_SIZE 1\n#define AVR32_USBB_UESTA0_CTRLDIR 17\n#define AVR32_USBB_UESTA0_CTRLDIR_IN 0x00000001\n#define AVR32_USBB_UESTA0_CTRLDIR_MASK 0x00020000\n#define AVR32_USBB_UESTA0_CTRLDIR_OFFSET 17\n#define AVR32_USBB_UESTA0_CTRLDIR_OUT 0x00000000\n#define AVR32_USBB_UESTA0_CTRLDIR_SIZE 1\n#define AVR32_USBB_UESTA0_CURRBK 14\n#define AVR32_USBB_UESTA0_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UESTA0_CURRBK_OFFSET 14\n#define AVR32_USBB_UESTA0_CURRBK_SIZE 2\n#define AVR32_USBB_UESTA0_DTSEQ 8\n#define AVR32_USBB_UESTA0_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UESTA0_DTSEQ_OFFSET 8\n#define AVR32_USBB_UESTA0_DTSEQ_SIZE 2\n#define AVR32_USBB_UESTA0_ERRORTRANS 10\n#define AVR32_USBB_UESTA0_ERRORTRANS_MASK 0x00000400\n#define AVR32_USBB_UESTA0_ERRORTRANS_OFFSET 10\n#define AVR32_USBB_UESTA0_ERRORTRANS_SIZE 1\n#define AVR32_USBB_UESTA0_NAKINI 4\n#define AVR32_USBB_UESTA0_NAKINI_MASK 0x00000010\n#define AVR32_USBB_UESTA0_NAKINI_OFFSET 4\n#define AVR32_USBB_UESTA0_NAKINI_SIZE 1\n#define AVR32_USBB_UESTA0_NAKOUTI 3\n#define AVR32_USBB_UESTA0_NAKOUTI_MASK 0x00000008\n#define AVR32_USBB_UESTA0_NAKOUTI_OFFSET 3\n#define AVR32_USBB_UESTA0_NAKOUTI_SIZE 1\n#define AVR32_USBB_UESTA0_NBUSYBK 12\n#define AVR32_USBB_UESTA0_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UESTA0_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UESTA0_NBUSYBK_SIZE 2\n#define AVR32_USBB_UESTA0_OVERFI 5\n#define AVR32_USBB_UESTA0_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UESTA0_OVERFI_OFFSET 5\n#define AVR32_USBB_UESTA0_OVERFI_SIZE 1\n#define AVR32_USBB_UESTA0_RWALL 16\n#define AVR32_USBB_UESTA0_RWALL_MASK 0x00010000\n#define AVR32_USBB_UESTA0_RWALL_OFFSET 16\n#define AVR32_USBB_UESTA0_RWALL_SIZE 1\n#define AVR32_USBB_UESTA0_RXOUTI 1\n#define AVR32_USBB_UESTA0_RXOUTI_MASK 0x00000002\n#define AVR32_USBB_UESTA0_RXOUTI_OFFSET 1\n#define AVR32_USBB_UESTA0_RXOUTI_SIZE 1\n#define AVR32_USBB_UESTA0_RXSTPI 2\n#define AVR32_USBB_UESTA0_RXSTPI_MASK 0x00000004\n#define AVR32_USBB_UESTA0_RXSTPI_OFFSET 2\n#define AVR32_USBB_UESTA0_RXSTPI_SIZE 1\n#define AVR32_USBB_UESTA0_SHORTPACKET 7\n#define AVR32_USBB_UESTA0_SHORTPACKET_MASK 0x00000080\n#define AVR32_USBB_UESTA0_SHORTPACKET_OFFSET 7\n#define AVR32_USBB_UESTA0_SHORTPACKET_SIZE 1\n#define AVR32_USBB_UESTA0_STALLEDI 6\n#define AVR32_USBB_UESTA0_STALLEDI_MASK 0x00000040\n#define AVR32_USBB_UESTA0_STALLEDI_OFFSET 6\n#define AVR32_USBB_UESTA0_STALLEDI_SIZE 1\n#define AVR32_USBB_UESTA0_TXINI 0\n#define AVR32_USBB_UESTA0_TXINI_MASK 0x00000001\n#define AVR32_USBB_UESTA0_TXINI_OFFSET 0\n#define AVR32_USBB_UESTA0_TXINI_SIZE 1\n#define AVR32_USBB_UESTA1 0x00000134\n#define AVR32_USBB_UESTA1CLR 0x00000164\n#define AVR32_USBB_UESTA1CLR_NAKINIC 4\n#define AVR32_USBB_UESTA1CLR_NAKINIC_MASK 0x00000010\n#define AVR32_USBB_UESTA1CLR_NAKINIC_OFFSET 4\n#define AVR32_USBB_UESTA1CLR_NAKINIC_SIZE 1\n#define AVR32_USBB_UESTA1CLR_NAKOUTIC 3\n#define AVR32_USBB_UESTA1CLR_NAKOUTIC_MASK 0x00000008\n#define AVR32_USBB_UESTA1CLR_NAKOUTIC_OFFSET 3\n#define AVR32_USBB_UESTA1CLR_NAKOUTIC_SIZE 1\n#define AVR32_USBB_UESTA1CLR_OVERFIC 5\n#define AVR32_USBB_UESTA1CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UESTA1CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UESTA1CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UESTA1CLR_RXOUTIC 1\n#define AVR32_USBB_UESTA1CLR_RXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UESTA1CLR_RXOUTIC_OFFSET 1\n#define AVR32_USBB_UESTA1CLR_RXOUTIC_SIZE 1\n#define AVR32_USBB_UESTA1CLR_RXSTPIC 2\n#define AVR32_USBB_UESTA1CLR_RXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UESTA1CLR_RXSTPIC_OFFSET 2\n#define AVR32_USBB_UESTA1CLR_RXSTPIC_SIZE 1\n#define AVR32_USBB_UESTA1CLR_SHORTPACKETC 7\n#define AVR32_USBB_UESTA1CLR_SHORTPACKETC_MASK 0x00000080\n#define AVR32_USBB_UESTA1CLR_SHORTPACKETC_OFFSET 7\n#define AVR32_USBB_UESTA1CLR_SHORTPACKETC_SIZE 1\n#define AVR32_USBB_UESTA1CLR_STALLEDIC 6\n#define AVR32_USBB_UESTA1CLR_STALLEDIC_MASK 0x00000040\n#define AVR32_USBB_UESTA1CLR_STALLEDIC_OFFSET 6\n#define AVR32_USBB_UESTA1CLR_STALLEDIC_SIZE 1\n#define AVR32_USBB_UESTA1CLR_TXINIC 0\n#define AVR32_USBB_UESTA1CLR_TXINIC_MASK 0x00000001\n#define AVR32_USBB_UESTA1CLR_TXINIC_OFFSET 0\n#define AVR32_USBB_UESTA1CLR_TXINIC_SIZE 1\n#define AVR32_USBB_UESTA1SET 0x00000194\n#define AVR32_USBB_UESTA1SET_ERRORTRANSS 10\n#define AVR32_USBB_UESTA1SET_ERRORTRANSS_MASK 0x00000400\n#define AVR32_USBB_UESTA1SET_ERRORTRANSS_OFFSET 10\n#define AVR32_USBB_UESTA1SET_ERRORTRANSS_SIZE 1\n#define AVR32_USBB_UESTA1SET_NAKINIS 4\n#define AVR32_USBB_UESTA1SET_NAKINIS_MASK 0x00000010\n#define AVR32_USBB_UESTA1SET_NAKINIS_OFFSET 4\n#define AVR32_USBB_UESTA1SET_NAKINIS_SIZE 1\n#define AVR32_USBB_UESTA1SET_NAKOUTIS 3\n#define AVR32_USBB_UESTA1SET_NAKOUTIS_MASK 0x00000008\n#define AVR32_USBB_UESTA1SET_NAKOUTIS_OFFSET 3\n#define AVR32_USBB_UESTA1SET_NAKOUTIS_SIZE 1\n#define AVR32_USBB_UESTA1SET_NBUSYBKS 12\n#define AVR32_USBB_UESTA1SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UESTA1SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UESTA1SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UESTA1SET_OVERFIS 5\n#define AVR32_USBB_UESTA1SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UESTA1SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UESTA1SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UESTA1SET_RXOUTIS 1\n#define AVR32_USBB_UESTA1SET_RXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UESTA1SET_RXOUTIS_OFFSET 1\n#define AVR32_USBB_UESTA1SET_RXOUTIS_SIZE 1\n#define AVR32_USBB_UESTA1SET_RXSTPIS 2\n#define AVR32_USBB_UESTA1SET_RXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UESTA1SET_RXSTPIS_OFFSET 2\n#define AVR32_USBB_UESTA1SET_RXSTPIS_SIZE 1\n#define AVR32_USBB_UESTA1SET_SETMDATA 8\n#define AVR32_USBB_UESTA1SET_SETMDATA_MASK 0x00000100\n#define AVR32_USBB_UESTA1SET_SETMDATA_OFFSET 8\n#define AVR32_USBB_UESTA1SET_SETMDATA_SIZE 1\n#define AVR32_USBB_UESTA1SET_SHORTPACKETS 7\n#define AVR32_USBB_UESTA1SET_SHORTPACKETS_MASK 0x00000080\n#define AVR32_USBB_UESTA1SET_SHORTPACKETS_OFFSET 7\n#define AVR32_USBB_UESTA1SET_SHORTPACKETS_SIZE 1\n#define AVR32_USBB_UESTA1SET_STALLEDIS 6\n#define AVR32_USBB_UESTA1SET_STALLEDIS_MASK 0x00000040\n#define AVR32_USBB_UESTA1SET_STALLEDIS_OFFSET 6\n#define AVR32_USBB_UESTA1SET_STALLEDIS_SIZE 1\n#define AVR32_USBB_UESTA1SET_TXINIS 0\n#define AVR32_USBB_UESTA1SET_TXINIS_MASK 0x00000001\n#define AVR32_USBB_UESTA1SET_TXINIS_OFFSET 0\n#define AVR32_USBB_UESTA1SET_TXINIS_SIZE 1\n#define AVR32_USBB_UESTA1_BYCT 20\n#define AVR32_USBB_UESTA1_BYCT_MASK 0x7ff00000\n#define AVR32_USBB_UESTA1_BYCT_OFFSET 20\n#define AVR32_USBB_UESTA1_BYCT_SIZE 11\n#define AVR32_USBB_UESTA1_CFGOK 18\n#define AVR32_USBB_UESTA1_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UESTA1_CFGOK_OFFSET 18\n#define AVR32_USBB_UESTA1_CFGOK_SIZE 1\n#define AVR32_USBB_UESTA1_CTRLDIR 17\n#define AVR32_USBB_UESTA1_CTRLDIR_IN 0x00000001\n#define AVR32_USBB_UESTA1_CTRLDIR_MASK 0x00020000\n#define AVR32_USBB_UESTA1_CTRLDIR_OFFSET 17\n#define AVR32_USBB_UESTA1_CTRLDIR_OUT 0x00000000\n#define AVR32_USBB_UESTA1_CTRLDIR_SIZE 1\n#define AVR32_USBB_UESTA1_CURRBK 14\n#define AVR32_USBB_UESTA1_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UESTA1_CURRBK_OFFSET 14\n#define AVR32_USBB_UESTA1_CURRBK_SIZE 2\n#define AVR32_USBB_UESTA1_DTSEQ 8\n#define AVR32_USBB_UESTA1_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UESTA1_DTSEQ_OFFSET 8\n#define AVR32_USBB_UESTA1_DTSEQ_SIZE 2\n#define AVR32_USBB_UESTA1_ERRORTRANS 10\n#define AVR32_USBB_UESTA1_ERRORTRANS_MASK 0x00000400\n#define AVR32_USBB_UESTA1_ERRORTRANS_OFFSET 10\n#define AVR32_USBB_UESTA1_ERRORTRANS_SIZE 1\n#define AVR32_USBB_UESTA1_NAKINI 4\n#define AVR32_USBB_UESTA1_NAKINI_MASK 0x00000010\n#define AVR32_USBB_UESTA1_NAKINI_OFFSET 4\n#define AVR32_USBB_UESTA1_NAKINI_SIZE 1\n#define AVR32_USBB_UESTA1_NAKOUTI 3\n#define AVR32_USBB_UESTA1_NAKOUTI_MASK 0x00000008\n#define AVR32_USBB_UESTA1_NAKOUTI_OFFSET 3\n#define AVR32_USBB_UESTA1_NAKOUTI_SIZE 1\n#define AVR32_USBB_UESTA1_NBUSYBK 12\n#define AVR32_USBB_UESTA1_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UESTA1_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UESTA1_NBUSYBK_SIZE 2\n#define AVR32_USBB_UESTA1_OVERFI 5\n#define AVR32_USBB_UESTA1_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UESTA1_OVERFI_OFFSET 5\n#define AVR32_USBB_UESTA1_OVERFI_SIZE 1\n#define AVR32_USBB_UESTA1_RWALL 16\n#define AVR32_USBB_UESTA1_RWALL_MASK 0x00010000\n#define AVR32_USBB_UESTA1_RWALL_OFFSET 16\n#define AVR32_USBB_UESTA1_RWALL_SIZE 1\n#define AVR32_USBB_UESTA1_RXOUTI 1\n#define AVR32_USBB_UESTA1_RXOUTI_MASK 0x00000002\n#define AVR32_USBB_UESTA1_RXOUTI_OFFSET 1\n#define AVR32_USBB_UESTA1_RXOUTI_SIZE 1\n#define AVR32_USBB_UESTA1_RXSTPI 2\n#define AVR32_USBB_UESTA1_RXSTPI_MASK 0x00000004\n#define AVR32_USBB_UESTA1_RXSTPI_OFFSET 2\n#define AVR32_USBB_UESTA1_RXSTPI_SIZE 1\n#define AVR32_USBB_UESTA1_SHORTPACKET 7\n#define AVR32_USBB_UESTA1_SHORTPACKET_MASK 0x00000080\n#define AVR32_USBB_UESTA1_SHORTPACKET_OFFSET 7\n#define AVR32_USBB_UESTA1_SHORTPACKET_SIZE 1\n#define AVR32_USBB_UESTA1_STALLEDI 6\n#define AVR32_USBB_UESTA1_STALLEDI_MASK 0x00000040\n#define AVR32_USBB_UESTA1_STALLEDI_OFFSET 6\n#define AVR32_USBB_UESTA1_STALLEDI_SIZE 1\n#define AVR32_USBB_UESTA1_TXINI 0\n#define AVR32_USBB_UESTA1_TXINI_MASK 0x00000001\n#define AVR32_USBB_UESTA1_TXINI_OFFSET 0\n#define AVR32_USBB_UESTA1_TXINI_SIZE 1\n#define AVR32_USBB_UESTA2 0x00000138\n#define AVR32_USBB_UESTA2CLR 0x00000168\n#define AVR32_USBB_UESTA2CLR_NAKINIC 4\n#define AVR32_USBB_UESTA2CLR_NAKINIC_MASK 0x00000010\n#define AVR32_USBB_UESTA2CLR_NAKINIC_OFFSET 4\n#define AVR32_USBB_UESTA2CLR_NAKINIC_SIZE 1\n#define AVR32_USBB_UESTA2CLR_NAKOUTIC 3\n#define AVR32_USBB_UESTA2CLR_NAKOUTIC_MASK 0x00000008\n#define AVR32_USBB_UESTA2CLR_NAKOUTIC_OFFSET 3\n#define AVR32_USBB_UESTA2CLR_NAKOUTIC_SIZE 1\n#define AVR32_USBB_UESTA2CLR_OVERFIC 5\n#define AVR32_USBB_UESTA2CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UESTA2CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UESTA2CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UESTA2CLR_RXOUTIC 1\n#define AVR32_USBB_UESTA2CLR_RXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UESTA2CLR_RXOUTIC_OFFSET 1\n#define AVR32_USBB_UESTA2CLR_RXOUTIC_SIZE 1\n#define AVR32_USBB_UESTA2CLR_RXSTPIC 2\n#define AVR32_USBB_UESTA2CLR_RXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UESTA2CLR_RXSTPIC_OFFSET 2\n#define AVR32_USBB_UESTA2CLR_RXSTPIC_SIZE 1\n#define AVR32_USBB_UESTA2CLR_SHORTPACKETC 7\n#define AVR32_USBB_UESTA2CLR_SHORTPACKETC_MASK 0x00000080\n#define AVR32_USBB_UESTA2CLR_SHORTPACKETC_OFFSET 7\n#define AVR32_USBB_UESTA2CLR_SHORTPACKETC_SIZE 1\n#define AVR32_USBB_UESTA2CLR_STALLEDIC 6\n#define AVR32_USBB_UESTA2CLR_STALLEDIC_MASK 0x00000040\n#define AVR32_USBB_UESTA2CLR_STALLEDIC_OFFSET 6\n#define AVR32_USBB_UESTA2CLR_STALLEDIC_SIZE 1\n#define AVR32_USBB_UESTA2CLR_TXINIC 0\n#define AVR32_USBB_UESTA2CLR_TXINIC_MASK 0x00000001\n#define AVR32_USBB_UESTA2CLR_TXINIC_OFFSET 0\n#define AVR32_USBB_UESTA2CLR_TXINIC_SIZE 1\n#define AVR32_USBB_UESTA2SET 0x00000198\n#define AVR32_USBB_UESTA2SET_ERRORTRANSS 10\n#define AVR32_USBB_UESTA2SET_ERRORTRANSS_MASK 0x00000400\n#define AVR32_USBB_UESTA2SET_ERRORTRANSS_OFFSET 10\n#define AVR32_USBB_UESTA2SET_ERRORTRANSS_SIZE 1\n#define AVR32_USBB_UESTA2SET_NAKINIS 4\n#define AVR32_USBB_UESTA2SET_NAKINIS_MASK 0x00000010\n#define AVR32_USBB_UESTA2SET_NAKINIS_OFFSET 4\n#define AVR32_USBB_UESTA2SET_NAKINIS_SIZE 1\n#define AVR32_USBB_UESTA2SET_NAKOUTIS 3\n#define AVR32_USBB_UESTA2SET_NAKOUTIS_MASK 0x00000008\n#define AVR32_USBB_UESTA2SET_NAKOUTIS_OFFSET 3\n#define AVR32_USBB_UESTA2SET_NAKOUTIS_SIZE 1\n#define AVR32_USBB_UESTA2SET_NBUSYBKS 12\n#define AVR32_USBB_UESTA2SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UESTA2SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UESTA2SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UESTA2SET_OVERFIS 5\n#define AVR32_USBB_UESTA2SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UESTA2SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UESTA2SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UESTA2SET_RXOUTIS 1\n#define AVR32_USBB_UESTA2SET_RXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UESTA2SET_RXOUTIS_OFFSET 1\n#define AVR32_USBB_UESTA2SET_RXOUTIS_SIZE 1\n#define AVR32_USBB_UESTA2SET_RXSTPIS 2\n#define AVR32_USBB_UESTA2SET_RXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UESTA2SET_RXSTPIS_OFFSET 2\n#define AVR32_USBB_UESTA2SET_RXSTPIS_SIZE 1\n#define AVR32_USBB_UESTA2SET_SETMDATA 8\n#define AVR32_USBB_UESTA2SET_SETMDATA_MASK 0x00000100\n#define AVR32_USBB_UESTA2SET_SETMDATA_OFFSET 8\n#define AVR32_USBB_UESTA2SET_SETMDATA_SIZE 1\n#define AVR32_USBB_UESTA2SET_SHORTPACKETS 7\n#define AVR32_USBB_UESTA2SET_SHORTPACKETS_MASK 0x00000080\n#define AVR32_USBB_UESTA2SET_SHORTPACKETS_OFFSET 7\n#define AVR32_USBB_UESTA2SET_SHORTPACKETS_SIZE 1\n#define AVR32_USBB_UESTA2SET_STALLEDIS 6\n#define AVR32_USBB_UESTA2SET_STALLEDIS_MASK 0x00000040\n#define AVR32_USBB_UESTA2SET_STALLEDIS_OFFSET 6\n#define AVR32_USBB_UESTA2SET_STALLEDIS_SIZE 1\n#define AVR32_USBB_UESTA2SET_TXINIS 0\n#define AVR32_USBB_UESTA2SET_TXINIS_MASK 0x00000001\n#define AVR32_USBB_UESTA2SET_TXINIS_OFFSET 0\n#define AVR32_USBB_UESTA2SET_TXINIS_SIZE 1\n#define AVR32_USBB_UESTA2_BYCT 20\n#define AVR32_USBB_UESTA2_BYCT_MASK 0x7ff00000\n#define AVR32_USBB_UESTA2_BYCT_OFFSET 20\n#define AVR32_USBB_UESTA2_BYCT_SIZE 11\n#define AVR32_USBB_UESTA2_CFGOK 18\n#define AVR32_USBB_UESTA2_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UESTA2_CFGOK_OFFSET 18\n#define AVR32_USBB_UESTA2_CFGOK_SIZE 1\n#define AVR32_USBB_UESTA2_CTRLDIR 17\n#define AVR32_USBB_UESTA2_CTRLDIR_IN 0x00000001\n#define AVR32_USBB_UESTA2_CTRLDIR_MASK 0x00020000\n#define AVR32_USBB_UESTA2_CTRLDIR_OFFSET 17\n#define AVR32_USBB_UESTA2_CTRLDIR_OUT 0x00000000\n#define AVR32_USBB_UESTA2_CTRLDIR_SIZE 1\n#define AVR32_USBB_UESTA2_CURRBK 14\n#define AVR32_USBB_UESTA2_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UESTA2_CURRBK_OFFSET 14\n#define AVR32_USBB_UESTA2_CURRBK_SIZE 2\n#define AVR32_USBB_UESTA2_DTSEQ 8\n#define AVR32_USBB_UESTA2_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UESTA2_DTSEQ_OFFSET 8\n#define AVR32_USBB_UESTA2_DTSEQ_SIZE 2\n#define AVR32_USBB_UESTA2_ERRORTRANS 10\n#define AVR32_USBB_UESTA2_ERRORTRANS_MASK 0x00000400\n#define AVR32_USBB_UESTA2_ERRORTRANS_OFFSET 10\n#define AVR32_USBB_UESTA2_ERRORTRANS_SIZE 1\n#define AVR32_USBB_UESTA2_NAKINI 4\n#define AVR32_USBB_UESTA2_NAKINI_MASK 0x00000010\n#define AVR32_USBB_UESTA2_NAKINI_OFFSET 4\n#define AVR32_USBB_UESTA2_NAKINI_SIZE 1\n#define AVR32_USBB_UESTA2_NAKOUTI 3\n#define AVR32_USBB_UESTA2_NAKOUTI_MASK 0x00000008\n#define AVR32_USBB_UESTA2_NAKOUTI_OFFSET 3\n#define AVR32_USBB_UESTA2_NAKOUTI_SIZE 1\n#define AVR32_USBB_UESTA2_NBUSYBK 12\n#define AVR32_USBB_UESTA2_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UESTA2_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UESTA2_NBUSYBK_SIZE 2\n#define AVR32_USBB_UESTA2_OVERFI 5\n#define AVR32_USBB_UESTA2_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UESTA2_OVERFI_OFFSET 5\n#define AVR32_USBB_UESTA2_OVERFI_SIZE 1\n#define AVR32_USBB_UESTA2_RWALL 16\n#define AVR32_USBB_UESTA2_RWALL_MASK 0x00010000\n#define AVR32_USBB_UESTA2_RWALL_OFFSET 16\n#define AVR32_USBB_UESTA2_RWALL_SIZE 1\n#define AVR32_USBB_UESTA2_RXOUTI 1\n#define AVR32_USBB_UESTA2_RXOUTI_MASK 0x00000002\n#define AVR32_USBB_UESTA2_RXOUTI_OFFSET 1\n#define AVR32_USBB_UESTA2_RXOUTI_SIZE 1\n#define AVR32_USBB_UESTA2_RXSTPI 2\n#define AVR32_USBB_UESTA2_RXSTPI_MASK 0x00000004\n#define AVR32_USBB_UESTA2_RXSTPI_OFFSET 2\n#define AVR32_USBB_UESTA2_RXSTPI_SIZE 1\n#define AVR32_USBB_UESTA2_SHORTPACKET 7\n#define AVR32_USBB_UESTA2_SHORTPACKET_MASK 0x00000080\n#define AVR32_USBB_UESTA2_SHORTPACKET_OFFSET 7\n#define AVR32_USBB_UESTA2_SHORTPACKET_SIZE 1\n#define AVR32_USBB_UESTA2_STALLEDI 6\n#define AVR32_USBB_UESTA2_STALLEDI_MASK 0x00000040\n#define AVR32_USBB_UESTA2_STALLEDI_OFFSET 6\n#define AVR32_USBB_UESTA2_STALLEDI_SIZE 1\n#define AVR32_USBB_UESTA2_TXINI 0\n#define AVR32_USBB_UESTA2_TXINI_MASK 0x00000001\n#define AVR32_USBB_UESTA2_TXINI_OFFSET 0\n#define AVR32_USBB_UESTA2_TXINI_SIZE 1\n#define AVR32_USBB_UESTA3 0x0000013c\n#define AVR32_USBB_UESTA3CLR 0x0000016c\n#define AVR32_USBB_UESTA3CLR_NAKINIC 4\n#define AVR32_USBB_UESTA3CLR_NAKINIC_MASK 0x00000010\n#define AVR32_USBB_UESTA3CLR_NAKINIC_OFFSET 4\n#define AVR32_USBB_UESTA3CLR_NAKINIC_SIZE 1\n#define AVR32_USBB_UESTA3CLR_NAKOUTIC 3\n#define AVR32_USBB_UESTA3CLR_NAKOUTIC_MASK 0x00000008\n#define AVR32_USBB_UESTA3CLR_NAKOUTIC_OFFSET 3\n#define AVR32_USBB_UESTA3CLR_NAKOUTIC_SIZE 1\n#define AVR32_USBB_UESTA3CLR_OVERFIC 5\n#define AVR32_USBB_UESTA3CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UESTA3CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UESTA3CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UESTA3CLR_RXOUTIC 1\n#define AVR32_USBB_UESTA3CLR_RXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UESTA3CLR_RXOUTIC_OFFSET 1\n#define AVR32_USBB_UESTA3CLR_RXOUTIC_SIZE 1\n#define AVR32_USBB_UESTA3CLR_RXSTPIC 2\n#define AVR32_USBB_UESTA3CLR_RXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UESTA3CLR_RXSTPIC_OFFSET 2\n#define AVR32_USBB_UESTA3CLR_RXSTPIC_SIZE 1\n#define AVR32_USBB_UESTA3CLR_SHORTPACKETC 7\n#define AVR32_USBB_UESTA3CLR_SHORTPACKETC_MASK 0x00000080\n#define AVR32_USBB_UESTA3CLR_SHORTPACKETC_OFFSET 7\n#define AVR32_USBB_UESTA3CLR_SHORTPACKETC_SIZE 1\n#define AVR32_USBB_UESTA3CLR_STALLEDIC 6\n#define AVR32_USBB_UESTA3CLR_STALLEDIC_MASK 0x00000040\n#define AVR32_USBB_UESTA3CLR_STALLEDIC_OFFSET 6\n#define AVR32_USBB_UESTA3CLR_STALLEDIC_SIZE 1\n#define AVR32_USBB_UESTA3CLR_TXINIC 0\n#define AVR32_USBB_UESTA3CLR_TXINIC_MASK 0x00000001\n#define AVR32_USBB_UESTA3CLR_TXINIC_OFFSET 0\n#define AVR32_USBB_UESTA3CLR_TXINIC_SIZE 1\n#define AVR32_USBB_UESTA3SET 0x0000019c\n#define AVR32_USBB_UESTA3SET_ERRORTRANSS 10\n#define AVR32_USBB_UESTA3SET_ERRORTRANSS_MASK 0x00000400\n#define AVR32_USBB_UESTA3SET_ERRORTRANSS_OFFSET 10\n#define AVR32_USBB_UESTA3SET_ERRORTRANSS_SIZE 1\n#define AVR32_USBB_UESTA3SET_NAKINIS 4\n#define AVR32_USBB_UESTA3SET_NAKINIS_MASK 0x00000010\n#define AVR32_USBB_UESTA3SET_NAKINIS_OFFSET 4\n#define AVR32_USBB_UESTA3SET_NAKINIS_SIZE 1\n#define AVR32_USBB_UESTA3SET_NAKOUTIS 3\n#define AVR32_USBB_UESTA3SET_NAKOUTIS_MASK 0x00000008\n#define AVR32_USBB_UESTA3SET_NAKOUTIS_OFFSET 3\n#define AVR32_USBB_UESTA3SET_NAKOUTIS_SIZE 1\n#define AVR32_USBB_UESTA3SET_NBUSYBKS 12\n#define AVR32_USBB_UESTA3SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UESTA3SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UESTA3SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UESTA3SET_OVERFIS 5\n#define AVR32_USBB_UESTA3SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UESTA3SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UESTA3SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UESTA3SET_RXOUTIS 1\n#define AVR32_USBB_UESTA3SET_RXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UESTA3SET_RXOUTIS_OFFSET 1\n#define AVR32_USBB_UESTA3SET_RXOUTIS_SIZE 1\n#define AVR32_USBB_UESTA3SET_RXSTPIS 2\n#define AVR32_USBB_UESTA3SET_RXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UESTA3SET_RXSTPIS_OFFSET 2\n#define AVR32_USBB_UESTA3SET_RXSTPIS_SIZE 1\n#define AVR32_USBB_UESTA3SET_SETMDATA 8\n#define AVR32_USBB_UESTA3SET_SETMDATA_MASK 0x00000100\n#define AVR32_USBB_UESTA3SET_SETMDATA_OFFSET 8\n#define AVR32_USBB_UESTA3SET_SETMDATA_SIZE 1\n#define AVR32_USBB_UESTA3SET_SHORTPACKETS 7\n#define AVR32_USBB_UESTA3SET_SHORTPACKETS_MASK 0x00000080\n#define AVR32_USBB_UESTA3SET_SHORTPACKETS_OFFSET 7\n#define AVR32_USBB_UESTA3SET_SHORTPACKETS_SIZE 1\n#define AVR32_USBB_UESTA3SET_STALLEDIS 6\n#define AVR32_USBB_UESTA3SET_STALLEDIS_MASK 0x00000040\n#define AVR32_USBB_UESTA3SET_STALLEDIS_OFFSET 6\n#define AVR32_USBB_UESTA3SET_STALLEDIS_SIZE 1\n#define AVR32_USBB_UESTA3SET_TXINIS 0\n#define AVR32_USBB_UESTA3SET_TXINIS_MASK 0x00000001\n#define AVR32_USBB_UESTA3SET_TXINIS_OFFSET 0\n#define AVR32_USBB_UESTA3SET_TXINIS_SIZE 1\n#define AVR32_USBB_UESTA3_BYCT 20\n#define AVR32_USBB_UESTA3_BYCT_MASK 0x7ff00000\n#define AVR32_USBB_UESTA3_BYCT_OFFSET 20\n#define AVR32_USBB_UESTA3_BYCT_SIZE 11\n#define AVR32_USBB_UESTA3_CFGOK 18\n#define AVR32_USBB_UESTA3_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UESTA3_CFGOK_OFFSET 18\n#define AVR32_USBB_UESTA3_CFGOK_SIZE 1\n#define AVR32_USBB_UESTA3_CTRLDIR 17\n#define AVR32_USBB_UESTA3_CTRLDIR_IN 0x00000001\n#define AVR32_USBB_UESTA3_CTRLDIR_MASK 0x00020000\n#define AVR32_USBB_UESTA3_CTRLDIR_OFFSET 17\n#define AVR32_USBB_UESTA3_CTRLDIR_OUT 0x00000000\n#define AVR32_USBB_UESTA3_CTRLDIR_SIZE 1\n#define AVR32_USBB_UESTA3_CURRBK 14\n#define AVR32_USBB_UESTA3_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UESTA3_CURRBK_OFFSET 14\n#define AVR32_USBB_UESTA3_CURRBK_SIZE 2\n#define AVR32_USBB_UESTA3_DTSEQ 8\n#define AVR32_USBB_UESTA3_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UESTA3_DTSEQ_OFFSET 8\n#define AVR32_USBB_UESTA3_DTSEQ_SIZE 2\n#define AVR32_USBB_UESTA3_ERRORTRANS 10\n#define AVR32_USBB_UESTA3_ERRORTRANS_MASK 0x00000400\n#define AVR32_USBB_UESTA3_ERRORTRANS_OFFSET 10\n#define AVR32_USBB_UESTA3_ERRORTRANS_SIZE 1\n#define AVR32_USBB_UESTA3_NAKINI 4\n#define AVR32_USBB_UESTA3_NAKINI_MASK 0x00000010\n#define AVR32_USBB_UESTA3_NAKINI_OFFSET 4\n#define AVR32_USBB_UESTA3_NAKINI_SIZE 1\n#define AVR32_USBB_UESTA3_NAKOUTI 3\n#define AVR32_USBB_UESTA3_NAKOUTI_MASK 0x00000008\n#define AVR32_USBB_UESTA3_NAKOUTI_OFFSET 3\n#define AVR32_USBB_UESTA3_NAKOUTI_SIZE 1\n#define AVR32_USBB_UESTA3_NBUSYBK 12\n#define AVR32_USBB_UESTA3_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UESTA3_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UESTA3_NBUSYBK_SIZE 2\n#define AVR32_USBB_UESTA3_OVERFI 5\n#define AVR32_USBB_UESTA3_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UESTA3_OVERFI_OFFSET 5\n#define AVR32_USBB_UESTA3_OVERFI_SIZE 1\n#define AVR32_USBB_UESTA3_RWALL 16\n#define AVR32_USBB_UESTA3_RWALL_MASK 0x00010000\n#define AVR32_USBB_UESTA3_RWALL_OFFSET 16\n#define AVR32_USBB_UESTA3_RWALL_SIZE 1\n#define AVR32_USBB_UESTA3_RXOUTI 1\n#define AVR32_USBB_UESTA3_RXOUTI_MASK 0x00000002\n#define AVR32_USBB_UESTA3_RXOUTI_OFFSET 1\n#define AVR32_USBB_UESTA3_RXOUTI_SIZE 1\n#define AVR32_USBB_UESTA3_RXSTPI 2\n#define AVR32_USBB_UESTA3_RXSTPI_MASK 0x00000004\n#define AVR32_USBB_UESTA3_RXSTPI_OFFSET 2\n#define AVR32_USBB_UESTA3_RXSTPI_SIZE 1\n#define AVR32_USBB_UESTA3_SHORTPACKET 7\n#define AVR32_USBB_UESTA3_SHORTPACKET_MASK 0x00000080\n#define AVR32_USBB_UESTA3_SHORTPACKET_OFFSET 7\n#define AVR32_USBB_UESTA3_SHORTPACKET_SIZE 1\n#define AVR32_USBB_UESTA3_STALLEDI 6\n#define AVR32_USBB_UESTA3_STALLEDI_MASK 0x00000040\n#define AVR32_USBB_UESTA3_STALLEDI_OFFSET 6\n#define AVR32_USBB_UESTA3_STALLEDI_SIZE 1\n#define AVR32_USBB_UESTA3_TXINI 0\n#define AVR32_USBB_UESTA3_TXINI_MASK 0x00000001\n#define AVR32_USBB_UESTA3_TXINI_OFFSET 0\n#define AVR32_USBB_UESTA3_TXINI_SIZE 1\n#define AVR32_USBB_UESTA4 0x00000140\n#define AVR32_USBB_UESTA4CLR 0x00000170\n#define AVR32_USBB_UESTA4CLR_NAKINIC 4\n#define AVR32_USBB_UESTA4CLR_NAKINIC_MASK 0x00000010\n#define AVR32_USBB_UESTA4CLR_NAKINIC_OFFSET 4\n#define AVR32_USBB_UESTA4CLR_NAKINIC_SIZE 1\n#define AVR32_USBB_UESTA4CLR_NAKOUTIC 3\n#define AVR32_USBB_UESTA4CLR_NAKOUTIC_MASK 0x00000008\n#define AVR32_USBB_UESTA4CLR_NAKOUTIC_OFFSET 3\n#define AVR32_USBB_UESTA4CLR_NAKOUTIC_SIZE 1\n#define AVR32_USBB_UESTA4CLR_OVERFIC 5\n#define AVR32_USBB_UESTA4CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UESTA4CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UESTA4CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UESTA4CLR_RXOUTIC 1\n#define AVR32_USBB_UESTA4CLR_RXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UESTA4CLR_RXOUTIC_OFFSET 1\n#define AVR32_USBB_UESTA4CLR_RXOUTIC_SIZE 1\n#define AVR32_USBB_UESTA4CLR_RXSTPIC 2\n#define AVR32_USBB_UESTA4CLR_RXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UESTA4CLR_RXSTPIC_OFFSET 2\n#define AVR32_USBB_UESTA4CLR_RXSTPIC_SIZE 1\n#define AVR32_USBB_UESTA4CLR_SHORTPACKETC 7\n#define AVR32_USBB_UESTA4CLR_SHORTPACKETC_MASK 0x00000080\n#define AVR32_USBB_UESTA4CLR_SHORTPACKETC_OFFSET 7\n#define AVR32_USBB_UESTA4CLR_SHORTPACKETC_SIZE 1\n#define AVR32_USBB_UESTA4CLR_STALLEDIC 6\n#define AVR32_USBB_UESTA4CLR_STALLEDIC_MASK 0x00000040\n#define AVR32_USBB_UESTA4CLR_STALLEDIC_OFFSET 6\n#define AVR32_USBB_UESTA4CLR_STALLEDIC_SIZE 1\n#define AVR32_USBB_UESTA4CLR_TXINIC 0\n#define AVR32_USBB_UESTA4CLR_TXINIC_MASK 0x00000001\n#define AVR32_USBB_UESTA4CLR_TXINIC_OFFSET 0\n#define AVR32_USBB_UESTA4CLR_TXINIC_SIZE 1\n#define AVR32_USBB_UESTA4SET 0x000001a0\n#define AVR32_USBB_UESTA4SET_ERRORTRANSS 10\n#define AVR32_USBB_UESTA4SET_ERRORTRANSS_MASK 0x00000400\n#define AVR32_USBB_UESTA4SET_ERRORTRANSS_OFFSET 10\n#define AVR32_USBB_UESTA4SET_ERRORTRANSS_SIZE 1\n#define AVR32_USBB_UESTA4SET_NAKINIS 4\n#define AVR32_USBB_UESTA4SET_NAKINIS_MASK 0x00000010\n#define AVR32_USBB_UESTA4SET_NAKINIS_OFFSET 4\n#define AVR32_USBB_UESTA4SET_NAKINIS_SIZE 1\n#define AVR32_USBB_UESTA4SET_NAKOUTIS 3\n#define AVR32_USBB_UESTA4SET_NAKOUTIS_MASK 0x00000008\n#define AVR32_USBB_UESTA4SET_NAKOUTIS_OFFSET 3\n#define AVR32_USBB_UESTA4SET_NAKOUTIS_SIZE 1\n#define AVR32_USBB_UESTA4SET_NBUSYBKS 12\n#define AVR32_USBB_UESTA4SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UESTA4SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UESTA4SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UESTA4SET_OVERFIS 5\n#define AVR32_USBB_UESTA4SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UESTA4SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UESTA4SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UESTA4SET_RXOUTIS 1\n#define AVR32_USBB_UESTA4SET_RXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UESTA4SET_RXOUTIS_OFFSET 1\n#define AVR32_USBB_UESTA4SET_RXOUTIS_SIZE 1\n#define AVR32_USBB_UESTA4SET_RXSTPIS 2\n#define AVR32_USBB_UESTA4SET_RXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UESTA4SET_RXSTPIS_OFFSET 2\n#define AVR32_USBB_UESTA4SET_RXSTPIS_SIZE 1\n#define AVR32_USBB_UESTA4SET_SETMDATA 8\n#define AVR32_USBB_UESTA4SET_SETMDATA_MASK 0x00000100\n#define AVR32_USBB_UESTA4SET_SETMDATA_OFFSET 8\n#define AVR32_USBB_UESTA4SET_SETMDATA_SIZE 1\n#define AVR32_USBB_UESTA4SET_SHORTPACKETS 7\n#define AVR32_USBB_UESTA4SET_SHORTPACKETS_MASK 0x00000080\n#define AVR32_USBB_UESTA4SET_SHORTPACKETS_OFFSET 7\n#define AVR32_USBB_UESTA4SET_SHORTPACKETS_SIZE 1\n#define AVR32_USBB_UESTA4SET_STALLEDIS 6\n#define AVR32_USBB_UESTA4SET_STALLEDIS_MASK 0x00000040\n#define AVR32_USBB_UESTA4SET_STALLEDIS_OFFSET 6\n#define AVR32_USBB_UESTA4SET_STALLEDIS_SIZE 1\n#define AVR32_USBB_UESTA4SET_TXINIS 0\n#define AVR32_USBB_UESTA4SET_TXINIS_MASK 0x00000001\n#define AVR32_USBB_UESTA4SET_TXINIS_OFFSET 0\n#define AVR32_USBB_UESTA4SET_TXINIS_SIZE 1\n#define AVR32_USBB_UESTA4_BYCT 20\n#define AVR32_USBB_UESTA4_BYCT_MASK 0x7ff00000\n#define AVR32_USBB_UESTA4_BYCT_OFFSET 20\n#define AVR32_USBB_UESTA4_BYCT_SIZE 11\n#define AVR32_USBB_UESTA4_CFGOK 18\n#define AVR32_USBB_UESTA4_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UESTA4_CFGOK_OFFSET 18\n#define AVR32_USBB_UESTA4_CFGOK_SIZE 1\n#define AVR32_USBB_UESTA4_CTRLDIR 17\n#define AVR32_USBB_UESTA4_CTRLDIR_IN 0x00000001\n#define AVR32_USBB_UESTA4_CTRLDIR_MASK 0x00020000\n#define AVR32_USBB_UESTA4_CTRLDIR_OFFSET 17\n#define AVR32_USBB_UESTA4_CTRLDIR_OUT 0x00000000\n#define AVR32_USBB_UESTA4_CTRLDIR_SIZE 1\n#define AVR32_USBB_UESTA4_CURRBK 14\n#define AVR32_USBB_UESTA4_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UESTA4_CURRBK_OFFSET 14\n#define AVR32_USBB_UESTA4_CURRBK_SIZE 2\n#define AVR32_USBB_UESTA4_DTSEQ 8\n#define AVR32_USBB_UESTA4_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UESTA4_DTSEQ_OFFSET 8\n#define AVR32_USBB_UESTA4_DTSEQ_SIZE 2\n#define AVR32_USBB_UESTA4_ERRORTRANS 10\n#define AVR32_USBB_UESTA4_ERRORTRANS_MASK 0x00000400\n#define AVR32_USBB_UESTA4_ERRORTRANS_OFFSET 10\n#define AVR32_USBB_UESTA4_ERRORTRANS_SIZE 1\n#define AVR32_USBB_UESTA4_NAKINI 4\n#define AVR32_USBB_UESTA4_NAKINI_MASK 0x00000010\n#define AVR32_USBB_UESTA4_NAKINI_OFFSET 4\n#define AVR32_USBB_UESTA4_NAKINI_SIZE 1\n#define AVR32_USBB_UESTA4_NAKOUTI 3\n#define AVR32_USBB_UESTA4_NAKOUTI_MASK 0x00000008\n#define AVR32_USBB_UESTA4_NAKOUTI_OFFSET 3\n#define AVR32_USBB_UESTA4_NAKOUTI_SIZE 1\n#define AVR32_USBB_UESTA4_NBUSYBK 12\n#define AVR32_USBB_UESTA4_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UESTA4_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UESTA4_NBUSYBK_SIZE 2\n#define AVR32_USBB_UESTA4_OVERFI 5\n#define AVR32_USBB_UESTA4_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UESTA4_OVERFI_OFFSET 5\n#define AVR32_USBB_UESTA4_OVERFI_SIZE 1\n#define AVR32_USBB_UESTA4_RWALL 16\n#define AVR32_USBB_UESTA4_RWALL_MASK 0x00010000\n#define AVR32_USBB_UESTA4_RWALL_OFFSET 16\n#define AVR32_USBB_UESTA4_RWALL_SIZE 1\n#define AVR32_USBB_UESTA4_RXOUTI 1\n#define AVR32_USBB_UESTA4_RXOUTI_MASK 0x00000002\n#define AVR32_USBB_UESTA4_RXOUTI_OFFSET 1\n#define AVR32_USBB_UESTA4_RXOUTI_SIZE 1\n#define AVR32_USBB_UESTA4_RXSTPI 2\n#define AVR32_USBB_UESTA4_RXSTPI_MASK 0x00000004\n#define AVR32_USBB_UESTA4_RXSTPI_OFFSET 2\n#define AVR32_USBB_UESTA4_RXSTPI_SIZE 1\n#define AVR32_USBB_UESTA4_SHORTPACKET 7\n#define AVR32_USBB_UESTA4_SHORTPACKET_MASK 0x00000080\n#define AVR32_USBB_UESTA4_SHORTPACKET_OFFSET 7\n#define AVR32_USBB_UESTA4_SHORTPACKET_SIZE 1\n#define AVR32_USBB_UESTA4_STALLEDI 6\n#define AVR32_USBB_UESTA4_STALLEDI_MASK 0x00000040\n#define AVR32_USBB_UESTA4_STALLEDI_OFFSET 6\n#define AVR32_USBB_UESTA4_STALLEDI_SIZE 1\n#define AVR32_USBB_UESTA4_TXINI 0\n#define AVR32_USBB_UESTA4_TXINI_MASK 0x00000001\n#define AVR32_USBB_UESTA4_TXINI_OFFSET 0\n#define AVR32_USBB_UESTA4_TXINI_SIZE 1\n#define AVR32_USBB_UESTA5 0x00000144\n#define AVR32_USBB_UESTA5CLR 0x00000174\n#define AVR32_USBB_UESTA5CLR_NAKINIC 4\n#define AVR32_USBB_UESTA5CLR_NAKINIC_MASK 0x00000010\n#define AVR32_USBB_UESTA5CLR_NAKINIC_OFFSET 4\n#define AVR32_USBB_UESTA5CLR_NAKINIC_SIZE 1\n#define AVR32_USBB_UESTA5CLR_NAKOUTIC 3\n#define AVR32_USBB_UESTA5CLR_NAKOUTIC_MASK 0x00000008\n#define AVR32_USBB_UESTA5CLR_NAKOUTIC_OFFSET 3\n#define AVR32_USBB_UESTA5CLR_NAKOUTIC_SIZE 1\n#define AVR32_USBB_UESTA5CLR_OVERFIC 5\n#define AVR32_USBB_UESTA5CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UESTA5CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UESTA5CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UESTA5CLR_RXOUTIC 1\n#define AVR32_USBB_UESTA5CLR_RXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UESTA5CLR_RXOUTIC_OFFSET 1\n#define AVR32_USBB_UESTA5CLR_RXOUTIC_SIZE 1\n#define AVR32_USBB_UESTA5CLR_RXSTPIC 2\n#define AVR32_USBB_UESTA5CLR_RXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UESTA5CLR_RXSTPIC_OFFSET 2\n#define AVR32_USBB_UESTA5CLR_RXSTPIC_SIZE 1\n#define AVR32_USBB_UESTA5CLR_SHORTPACKETC 7\n#define AVR32_USBB_UESTA5CLR_SHORTPACKETC_MASK 0x00000080\n#define AVR32_USBB_UESTA5CLR_SHORTPACKETC_OFFSET 7\n#define AVR32_USBB_UESTA5CLR_SHORTPACKETC_SIZE 1\n#define AVR32_USBB_UESTA5CLR_STALLEDIC 6\n#define AVR32_USBB_UESTA5CLR_STALLEDIC_MASK 0x00000040\n#define AVR32_USBB_UESTA5CLR_STALLEDIC_OFFSET 6\n#define AVR32_USBB_UESTA5CLR_STALLEDIC_SIZE 1\n#define AVR32_USBB_UESTA5CLR_TXINIC 0\n#define AVR32_USBB_UESTA5CLR_TXINIC_MASK 0x00000001\n#define AVR32_USBB_UESTA5CLR_TXINIC_OFFSET 0\n#define AVR32_USBB_UESTA5CLR_TXINIC_SIZE 1\n#define AVR32_USBB_UESTA5SET 0x000001a4\n#define AVR32_USBB_UESTA5SET_ERRORTRANSS 10\n#define AVR32_USBB_UESTA5SET_ERRORTRANSS_MASK 0x00000400\n#define AVR32_USBB_UESTA5SET_ERRORTRANSS_OFFSET 10\n#define AVR32_USBB_UESTA5SET_ERRORTRANSS_SIZE 1\n#define AVR32_USBB_UESTA5SET_NAKINIS 4\n#define AVR32_USBB_UESTA5SET_NAKINIS_MASK 0x00000010\n#define AVR32_USBB_UESTA5SET_NAKINIS_OFFSET 4\n#define AVR32_USBB_UESTA5SET_NAKINIS_SIZE 1\n#define AVR32_USBB_UESTA5SET_NAKOUTIS 3\n#define AVR32_USBB_UESTA5SET_NAKOUTIS_MASK 0x00000008\n#define AVR32_USBB_UESTA5SET_NAKOUTIS_OFFSET 3\n#define AVR32_USBB_UESTA5SET_NAKOUTIS_SIZE 1\n#define AVR32_USBB_UESTA5SET_NBUSYBKS 12\n#define AVR32_USBB_UESTA5SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UESTA5SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UESTA5SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UESTA5SET_OVERFIS 5\n#define AVR32_USBB_UESTA5SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UESTA5SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UESTA5SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UESTA5SET_RXOUTIS 1\n#define AVR32_USBB_UESTA5SET_RXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UESTA5SET_RXOUTIS_OFFSET 1\n#define AVR32_USBB_UESTA5SET_RXOUTIS_SIZE 1\n#define AVR32_USBB_UESTA5SET_RXSTPIS 2\n#define AVR32_USBB_UESTA5SET_RXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UESTA5SET_RXSTPIS_OFFSET 2\n#define AVR32_USBB_UESTA5SET_RXSTPIS_SIZE 1\n#define AVR32_USBB_UESTA5SET_SETMDATA 8\n#define AVR32_USBB_UESTA5SET_SETMDATA_MASK 0x00000100\n#define AVR32_USBB_UESTA5SET_SETMDATA_OFFSET 8\n#define AVR32_USBB_UESTA5SET_SETMDATA_SIZE 1\n#define AVR32_USBB_UESTA5SET_SHORTPACKETS 7\n#define AVR32_USBB_UESTA5SET_SHORTPACKETS_MASK 0x00000080\n#define AVR32_USBB_UESTA5SET_SHORTPACKETS_OFFSET 7\n#define AVR32_USBB_UESTA5SET_SHORTPACKETS_SIZE 1\n#define AVR32_USBB_UESTA5SET_STALLEDIS 6\n#define AVR32_USBB_UESTA5SET_STALLEDIS_MASK 0x00000040\n#define AVR32_USBB_UESTA5SET_STALLEDIS_OFFSET 6\n#define AVR32_USBB_UESTA5SET_STALLEDIS_SIZE 1\n#define AVR32_USBB_UESTA5SET_TXINIS 0\n#define AVR32_USBB_UESTA5SET_TXINIS_MASK 0x00000001\n#define AVR32_USBB_UESTA5SET_TXINIS_OFFSET 0\n#define AVR32_USBB_UESTA5SET_TXINIS_SIZE 1\n#define AVR32_USBB_UESTA5_BYCT 20\n#define AVR32_USBB_UESTA5_BYCT_MASK 0x7ff00000\n#define AVR32_USBB_UESTA5_BYCT_OFFSET 20\n#define AVR32_USBB_UESTA5_BYCT_SIZE 11\n#define AVR32_USBB_UESTA5_CFGOK 18\n#define AVR32_USBB_UESTA5_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UESTA5_CFGOK_OFFSET 18\n#define AVR32_USBB_UESTA5_CFGOK_SIZE 1\n#define AVR32_USBB_UESTA5_CTRLDIR 17\n#define AVR32_USBB_UESTA5_CTRLDIR_IN 0x00000001\n#define AVR32_USBB_UESTA5_CTRLDIR_MASK 0x00020000\n#define AVR32_USBB_UESTA5_CTRLDIR_OFFSET 17\n#define AVR32_USBB_UESTA5_CTRLDIR_OUT 0x00000000\n#define AVR32_USBB_UESTA5_CTRLDIR_SIZE 1\n#define AVR32_USBB_UESTA5_CURRBK 14\n#define AVR32_USBB_UESTA5_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UESTA5_CURRBK_OFFSET 14\n#define AVR32_USBB_UESTA5_CURRBK_SIZE 2\n#define AVR32_USBB_UESTA5_DTSEQ 8\n#define AVR32_USBB_UESTA5_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UESTA5_DTSEQ_OFFSET 8\n#define AVR32_USBB_UESTA5_DTSEQ_SIZE 2\n#define AVR32_USBB_UESTA5_ERRORTRANS 10\n#define AVR32_USBB_UESTA5_ERRORTRANS_MASK 0x00000400\n#define AVR32_USBB_UESTA5_ERRORTRANS_OFFSET 10\n#define AVR32_USBB_UESTA5_ERRORTRANS_SIZE 1\n#define AVR32_USBB_UESTA5_NAKINI 4\n#define AVR32_USBB_UESTA5_NAKINI_MASK 0x00000010\n#define AVR32_USBB_UESTA5_NAKINI_OFFSET 4\n#define AVR32_USBB_UESTA5_NAKINI_SIZE 1\n#define AVR32_USBB_UESTA5_NAKOUTI 3\n#define AVR32_USBB_UESTA5_NAKOUTI_MASK 0x00000008\n#define AVR32_USBB_UESTA5_NAKOUTI_OFFSET 3\n#define AVR32_USBB_UESTA5_NAKOUTI_SIZE 1\n#define AVR32_USBB_UESTA5_NBUSYBK 12\n#define AVR32_USBB_UESTA5_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UESTA5_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UESTA5_NBUSYBK_SIZE 2\n#define AVR32_USBB_UESTA5_OVERFI 5\n#define AVR32_USBB_UESTA5_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UESTA5_OVERFI_OFFSET 5\n#define AVR32_USBB_UESTA5_OVERFI_SIZE 1\n#define AVR32_USBB_UESTA5_RWALL 16\n#define AVR32_USBB_UESTA5_RWALL_MASK 0x00010000\n#define AVR32_USBB_UESTA5_RWALL_OFFSET 16\n#define AVR32_USBB_UESTA5_RWALL_SIZE 1\n#define AVR32_USBB_UESTA5_RXOUTI 1\n#define AVR32_USBB_UESTA5_RXOUTI_MASK 0x00000002\n#define AVR32_USBB_UESTA5_RXOUTI_OFFSET 1\n#define AVR32_USBB_UESTA5_RXOUTI_SIZE 1\n#define AVR32_USBB_UESTA5_RXSTPI 2\n#define AVR32_USBB_UESTA5_RXSTPI_MASK 0x00000004\n#define AVR32_USBB_UESTA5_RXSTPI_OFFSET 2\n#define AVR32_USBB_UESTA5_RXSTPI_SIZE 1\n#define AVR32_USBB_UESTA5_SHORTPACKET 7\n#define AVR32_USBB_UESTA5_SHORTPACKET_MASK 0x00000080\n#define AVR32_USBB_UESTA5_SHORTPACKET_OFFSET 7\n#define AVR32_USBB_UESTA5_SHORTPACKET_SIZE 1\n#define AVR32_USBB_UESTA5_STALLEDI 6\n#define AVR32_USBB_UESTA5_STALLEDI_MASK 0x00000040\n#define AVR32_USBB_UESTA5_STALLEDI_OFFSET 6\n#define AVR32_USBB_UESTA5_STALLEDI_SIZE 1\n#define AVR32_USBB_UESTA5_TXINI 0\n#define AVR32_USBB_UESTA5_TXINI_MASK 0x00000001\n#define AVR32_USBB_UESTA5_TXINI_OFFSET 0\n#define AVR32_USBB_UESTA5_TXINI_SIZE 1\n#define AVR32_USBB_UESTA6 0x00000148\n#define AVR32_USBB_UESTA6CLR 0x00000178\n#define AVR32_USBB_UESTA6CLR_NAKINIC 4\n#define AVR32_USBB_UESTA6CLR_NAKINIC_MASK 0x00000010\n#define AVR32_USBB_UESTA6CLR_NAKINIC_OFFSET 4\n#define AVR32_USBB_UESTA6CLR_NAKINIC_SIZE 1\n#define AVR32_USBB_UESTA6CLR_NAKOUTIC 3\n#define AVR32_USBB_UESTA6CLR_NAKOUTIC_MASK 0x00000008\n#define AVR32_USBB_UESTA6CLR_NAKOUTIC_OFFSET 3\n#define AVR32_USBB_UESTA6CLR_NAKOUTIC_SIZE 1\n#define AVR32_USBB_UESTA6CLR_OVERFIC 5\n#define AVR32_USBB_UESTA6CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UESTA6CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UESTA6CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UESTA6CLR_RXOUTIC 1\n#define AVR32_USBB_UESTA6CLR_RXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UESTA6CLR_RXOUTIC_OFFSET 1\n#define AVR32_USBB_UESTA6CLR_RXOUTIC_SIZE 1\n#define AVR32_USBB_UESTA6CLR_RXSTPIC 2\n#define AVR32_USBB_UESTA6CLR_RXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UESTA6CLR_RXSTPIC_OFFSET 2\n#define AVR32_USBB_UESTA6CLR_RXSTPIC_SIZE 1\n#define AVR32_USBB_UESTA6CLR_SHORTPACKETC 7\n#define AVR32_USBB_UESTA6CLR_SHORTPACKETC_MASK 0x00000080\n#define AVR32_USBB_UESTA6CLR_SHORTPACKETC_OFFSET 7\n#define AVR32_USBB_UESTA6CLR_SHORTPACKETC_SIZE 1\n#define AVR32_USBB_UESTA6CLR_STALLEDIC 6\n#define AVR32_USBB_UESTA6CLR_STALLEDIC_MASK 0x00000040\n#define AVR32_USBB_UESTA6CLR_STALLEDIC_OFFSET 6\n#define AVR32_USBB_UESTA6CLR_STALLEDIC_SIZE 1\n#define AVR32_USBB_UESTA6CLR_TXINIC 0\n#define AVR32_USBB_UESTA6CLR_TXINIC_MASK 0x00000001\n#define AVR32_USBB_UESTA6CLR_TXINIC_OFFSET 0\n#define AVR32_USBB_UESTA6CLR_TXINIC_SIZE 1\n#define AVR32_USBB_UESTA6SET 0x000001a8\n#define AVR32_USBB_UESTA6SET_ERRORTRANSS 10\n#define AVR32_USBB_UESTA6SET_ERRORTRANSS_MASK 0x00000400\n#define AVR32_USBB_UESTA6SET_ERRORTRANSS_OFFSET 10\n#define AVR32_USBB_UESTA6SET_ERRORTRANSS_SIZE 1\n#define AVR32_USBB_UESTA6SET_NAKINIS 4\n#define AVR32_USBB_UESTA6SET_NAKINIS_MASK 0x00000010\n#define AVR32_USBB_UESTA6SET_NAKINIS_OFFSET 4\n#define AVR32_USBB_UESTA6SET_NAKINIS_SIZE 1\n#define AVR32_USBB_UESTA6SET_NAKOUTIS 3\n#define AVR32_USBB_UESTA6SET_NAKOUTIS_MASK 0x00000008\n#define AVR32_USBB_UESTA6SET_NAKOUTIS_OFFSET 3\n#define AVR32_USBB_UESTA6SET_NAKOUTIS_SIZE 1\n#define AVR32_USBB_UESTA6SET_NBUSYBKS 12\n#define AVR32_USBB_UESTA6SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UESTA6SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UESTA6SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UESTA6SET_OVERFIS 5\n#define AVR32_USBB_UESTA6SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UESTA6SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UESTA6SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UESTA6SET_RXOUTIS 1\n#define AVR32_USBB_UESTA6SET_RXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UESTA6SET_RXOUTIS_OFFSET 1\n#define AVR32_USBB_UESTA6SET_RXOUTIS_SIZE 1\n#define AVR32_USBB_UESTA6SET_RXSTPIS 2\n#define AVR32_USBB_UESTA6SET_RXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UESTA6SET_RXSTPIS_OFFSET 2\n#define AVR32_USBB_UESTA6SET_RXSTPIS_SIZE 1\n#define AVR32_USBB_UESTA6SET_SETMDATA 8\n#define AVR32_USBB_UESTA6SET_SETMDATA_MASK 0x00000100\n#define AVR32_USBB_UESTA6SET_SETMDATA_OFFSET 8\n#define AVR32_USBB_UESTA6SET_SETMDATA_SIZE 1\n#define AVR32_USBB_UESTA6SET_SHORTPACKETS 7\n#define AVR32_USBB_UESTA6SET_SHORTPACKETS_MASK 0x00000080\n#define AVR32_USBB_UESTA6SET_SHORTPACKETS_OFFSET 7\n#define AVR32_USBB_UESTA6SET_SHORTPACKETS_SIZE 1\n#define AVR32_USBB_UESTA6SET_STALLEDIS 6\n#define AVR32_USBB_UESTA6SET_STALLEDIS_MASK 0x00000040\n#define AVR32_USBB_UESTA6SET_STALLEDIS_OFFSET 6\n#define AVR32_USBB_UESTA6SET_STALLEDIS_SIZE 1\n#define AVR32_USBB_UESTA6SET_TXINIS 0\n#define AVR32_USBB_UESTA6SET_TXINIS_MASK 0x00000001\n#define AVR32_USBB_UESTA6SET_TXINIS_OFFSET 0\n#define AVR32_USBB_UESTA6SET_TXINIS_SIZE 1\n#define AVR32_USBB_UESTA6_BYCT 20\n#define AVR32_USBB_UESTA6_BYCT_MASK 0x7ff00000\n#define AVR32_USBB_UESTA6_BYCT_OFFSET 20\n#define AVR32_USBB_UESTA6_BYCT_SIZE 11\n#define AVR32_USBB_UESTA6_CFGOK 18\n#define AVR32_USBB_UESTA6_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UESTA6_CFGOK_OFFSET 18\n#define AVR32_USBB_UESTA6_CFGOK_SIZE 1\n#define AVR32_USBB_UESTA6_CTRLDIR 17\n#define AVR32_USBB_UESTA6_CTRLDIR_IN 0x00000001\n#define AVR32_USBB_UESTA6_CTRLDIR_MASK 0x00020000\n#define AVR32_USBB_UESTA6_CTRLDIR_OFFSET 17\n#define AVR32_USBB_UESTA6_CTRLDIR_OUT 0x00000000\n#define AVR32_USBB_UESTA6_CTRLDIR_SIZE 1\n#define AVR32_USBB_UESTA6_CURRBK 14\n#define AVR32_USBB_UESTA6_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UESTA6_CURRBK_OFFSET 14\n#define AVR32_USBB_UESTA6_CURRBK_SIZE 2\n#define AVR32_USBB_UESTA6_DTSEQ 8\n#define AVR32_USBB_UESTA6_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UESTA6_DTSEQ_OFFSET 8\n#define AVR32_USBB_UESTA6_DTSEQ_SIZE 2\n#define AVR32_USBB_UESTA6_ERRORTRANS 10\n#define AVR32_USBB_UESTA6_ERRORTRANS_MASK 0x00000400\n#define AVR32_USBB_UESTA6_ERRORTRANS_OFFSET 10\n#define AVR32_USBB_UESTA6_ERRORTRANS_SIZE 1\n#define AVR32_USBB_UESTA6_NAKINI 4\n#define AVR32_USBB_UESTA6_NAKINI_MASK 0x00000010\n#define AVR32_USBB_UESTA6_NAKINI_OFFSET 4\n#define AVR32_USBB_UESTA6_NAKINI_SIZE 1\n#define AVR32_USBB_UESTA6_NAKOUTI 3\n#define AVR32_USBB_UESTA6_NAKOUTI_MASK 0x00000008\n#define AVR32_USBB_UESTA6_NAKOUTI_OFFSET 3\n#define AVR32_USBB_UESTA6_NAKOUTI_SIZE 1\n#define AVR32_USBB_UESTA6_NBUSYBK 12\n#define AVR32_USBB_UESTA6_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UESTA6_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UESTA6_NBUSYBK_SIZE 2\n#define AVR32_USBB_UESTA6_OVERFI 5\n#define AVR32_USBB_UESTA6_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UESTA6_OVERFI_OFFSET 5\n#define AVR32_USBB_UESTA6_OVERFI_SIZE 1\n#define AVR32_USBB_UESTA6_RWALL 16\n#define AVR32_USBB_UESTA6_RWALL_MASK 0x00010000\n#define AVR32_USBB_UESTA6_RWALL_OFFSET 16\n#define AVR32_USBB_UESTA6_RWALL_SIZE 1\n#define AVR32_USBB_UESTA6_RXOUTI 1\n#define AVR32_USBB_UESTA6_RXOUTI_MASK 0x00000002\n#define AVR32_USBB_UESTA6_RXOUTI_OFFSET 1\n#define AVR32_USBB_UESTA6_RXOUTI_SIZE 1\n#define AVR32_USBB_UESTA6_RXSTPI 2\n#define AVR32_USBB_UESTA6_RXSTPI_MASK 0x00000004\n#define AVR32_USBB_UESTA6_RXSTPI_OFFSET 2\n#define AVR32_USBB_UESTA6_RXSTPI_SIZE 1\n#define AVR32_USBB_UESTA6_SHORTPACKET 7\n#define AVR32_USBB_UESTA6_SHORTPACKET_MASK 0x00000080\n#define AVR32_USBB_UESTA6_SHORTPACKET_OFFSET 7\n#define AVR32_USBB_UESTA6_SHORTPACKET_SIZE 1\n#define AVR32_USBB_UESTA6_STALLEDI 6\n#define AVR32_USBB_UESTA6_STALLEDI_MASK 0x00000040\n#define AVR32_USBB_UESTA6_STALLEDI_OFFSET 6\n#define AVR32_USBB_UESTA6_STALLEDI_SIZE 1\n#define AVR32_USBB_UESTA6_TXINI 0\n#define AVR32_USBB_UESTA6_TXINI_MASK 0x00000001\n#define AVR32_USBB_UESTA6_TXINI_OFFSET 0\n#define AVR32_USBB_UESTA6_TXINI_SIZE 1\n#define AVR32_USBB_UFEATURES 0x0000081c\n#define AVR32_USBB_UFEATURES_BYTE_WRITE_DPRAM 15\n#define AVR32_USBB_UFEATURES_BYTE_WRITE_DPRAM_MASK 0x00008000\n#define AVR32_USBB_UFEATURES_BYTE_WRITE_DPRAM_OFFSET 15\n#define AVR32_USBB_UFEATURES_BYTE_WRITE_DPRAM_SIZE 1\n#define AVR32_USBB_UFEATURES_DATA_BUS_8_16 16\n#define AVR32_USBB_UFEATURES_DATA_BUS_8_16_MASK 0x00010000\n#define AVR32_USBB_UFEATURES_DATA_BUS_8_16_OFFSET 16\n#define AVR32_USBB_UFEATURES_DATA_BUS_8_16_SIZE 1\n#define AVR32_USBB_UFEATURES_DMA_BUFFER_SIZE 7\n#define AVR32_USBB_UFEATURES_DMA_BUFFER_SIZE_16_BITS 0x00000000\n#define AVR32_USBB_UFEATURES_DMA_BUFFER_SIZE_24_BITS 0x00000001\n#define AVR32_USBB_UFEATURES_DMA_BUFFER_SIZE_MASK 0x00000080\n#define AVR32_USBB_UFEATURES_DMA_BUFFER_SIZE_OFFSET 7\n#define AVR32_USBB_UFEATURES_DMA_BUFFER_SIZE_SIZE 1\n#define AVR32_USBB_UFEATURES_DMA_CHANNEL_NBR 4\n#define AVR32_USBB_UFEATURES_DMA_CHANNEL_NBR_MASK 0x00000070\n#define AVR32_USBB_UFEATURES_DMA_CHANNEL_NBR_OFFSET 4\n#define AVR32_USBB_UFEATURES_DMA_CHANNEL_NBR_SIZE 3\n#define AVR32_USBB_UFEATURES_DMA_FIFO_WORD_DEPTH 8\n#define AVR32_USBB_UFEATURES_DMA_FIFO_WORD_DEPTH_MASK 0x00000f00\n#define AVR32_USBB_UFEATURES_DMA_FIFO_WORD_DEPTH_OFFSET 8\n#define AVR32_USBB_UFEATURES_DMA_FIFO_WORD_DEPTH_SIZE 4\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_1 17\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_10 26\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_10_MASK 0x04000000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_10_OFFSET 26\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_10_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_11 27\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_11_MASK 0x08000000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_11_OFFSET 27\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_11_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_12 28\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_12_MASK 0x10000000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_12_OFFSET 28\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_12_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_13 29\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_13_MASK 0x20000000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_13_OFFSET 29\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_13_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_14 30\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_14_MASK 0x40000000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_14_OFFSET 30\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_14_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_15 31\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_15_MASK 0x80000000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_15_OFFSET 31\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_15_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_1_MASK 0x00020000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_1_OFFSET 17\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_1_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_2 18\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_2_MASK 0x00040000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_2_OFFSET 18\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_2_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_3 19\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_3_MASK 0x00080000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_3_OFFSET 19\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_3_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_4 20\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_4_MASK 0x00100000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_4_OFFSET 20\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_4_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_5 21\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_5_MASK 0x00200000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_5_OFFSET 21\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_5_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_6 22\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_6_MASK 0x00400000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_6_OFFSET 22\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_6_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_7 23\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_7_MASK 0x00800000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_7_OFFSET 23\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_7_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_8 24\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_8_MASK 0x01000000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_8_OFFSET 24\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_8_SIZE 1\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_9 25\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_9_MASK 0x02000000\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_9_OFFSET 25\n#define AVR32_USBB_UFEATURES_EN_HIGH_BD_ISO_EPT_9_SIZE 1\n#define AVR32_USBB_UFEATURES_EPT_NBR_MAX 0\n#define AVR32_USBB_UFEATURES_EPT_NBR_MAX_MASK 0x0000000f\n#define AVR32_USBB_UFEATURES_EPT_NBR_MAX_OFFSET 0\n#define AVR32_USBB_UFEATURES_EPT_NBR_MAX_SIZE 4\n#define AVR32_USBB_UFEATURES_FIFO_MAX_SIZE 12\n#define AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_GE_16384 0x00000007\n#define AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_LT_1024 0x00000002\n#define AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_LT_16384 0x00000006\n#define AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_LT_2048 0x00000003\n#define AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_LT_256 0x00000000\n#define AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_LT_4096 0x00000004\n#define AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_LT_512 0x00000001\n#define AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_LT_8192 0x00000005\n#define AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_MASK 0x00007000\n#define AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_OFFSET 12\n#define AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_SIZE 3\n#define AVR32_USBB_UHADDR1 0x00000424\n#define AVR32_USBB_UHADDR1_UHADDR_P0 0\n#define AVR32_USBB_UHADDR1_UHADDR_P0_MASK 0x0000007f\n#define AVR32_USBB_UHADDR1_UHADDR_P0_OFFSET 0\n#define AVR32_USBB_UHADDR1_UHADDR_P0_SIZE 7\n#define AVR32_USBB_UHADDR1_UHADDR_P1 8\n#define AVR32_USBB_UHADDR1_UHADDR_P1_MASK 0x00007f00\n#define AVR32_USBB_UHADDR1_UHADDR_P1_OFFSET 8\n#define AVR32_USBB_UHADDR1_UHADDR_P1_SIZE 7\n#define AVR32_USBB_UHADDR1_UHADDR_P2 16\n#define AVR32_USBB_UHADDR1_UHADDR_P2_MASK 0x007f0000\n#define AVR32_USBB_UHADDR1_UHADDR_P2_OFFSET 16\n#define AVR32_USBB_UHADDR1_UHADDR_P2_SIZE 7\n#define AVR32_USBB_UHADDR1_UHADDR_P3 24\n#define AVR32_USBB_UHADDR1_UHADDR_P3_MASK 0x7f000000\n#define AVR32_USBB_UHADDR1_UHADDR_P3_OFFSET 24\n#define AVR32_USBB_UHADDR1_UHADDR_P3_SIZE 7\n#define AVR32_USBB_UHADDR2 0x00000428\n#define AVR32_USBB_UHADDR2_UHADDR_P4 0\n#define AVR32_USBB_UHADDR2_UHADDR_P4_MASK 0x0000007f\n#define AVR32_USBB_UHADDR2_UHADDR_P4_OFFSET 0\n#define AVR32_USBB_UHADDR2_UHADDR_P4_SIZE 7\n#define AVR32_USBB_UHADDR2_UHADDR_P5 8\n#define AVR32_USBB_UHADDR2_UHADDR_P5_MASK 0x00007f00\n#define AVR32_USBB_UHADDR2_UHADDR_P5_OFFSET 8\n#define AVR32_USBB_UHADDR2_UHADDR_P5_SIZE 7\n#define AVR32_USBB_UHADDR2_UHADDR_P6 16\n#define AVR32_USBB_UHADDR2_UHADDR_P6_MASK 0x007f0000\n#define AVR32_USBB_UHADDR2_UHADDR_P6_OFFSET 16\n#define AVR32_USBB_UHADDR2_UHADDR_P6_SIZE 7\n#define AVR32_USBB_UHADDR2_UHADDR_P7 24\n#define AVR32_USBB_UHADDR2_UHADDR_P7_MASK 0x7f000000\n#define AVR32_USBB_UHADDR2_UHADDR_P7_OFFSET 24\n#define AVR32_USBB_UHADDR2_UHADDR_P7_SIZE 7\n#define AVR32_USBB_UHADDR3 0x0000042c\n#define AVR32_USBB_UHADDR3_UHADDR_P10 16\n#define AVR32_USBB_UHADDR3_UHADDR_P10_MASK 0x007f0000\n#define AVR32_USBB_UHADDR3_UHADDR_P10_OFFSET 16\n#define AVR32_USBB_UHADDR3_UHADDR_P10_SIZE 7\n#define AVR32_USBB_UHADDR3_UHADDR_P11 24\n#define AVR32_USBB_UHADDR3_UHADDR_P11_MASK 0x7f000000\n#define AVR32_USBB_UHADDR3_UHADDR_P11_OFFSET 24\n#define AVR32_USBB_UHADDR3_UHADDR_P11_SIZE 7\n#define AVR32_USBB_UHADDR3_UHADDR_P8 0\n#define AVR32_USBB_UHADDR3_UHADDR_P8_MASK 0x0000007f\n#define AVR32_USBB_UHADDR3_UHADDR_P8_OFFSET 0\n#define AVR32_USBB_UHADDR3_UHADDR_P8_SIZE 7\n#define AVR32_USBB_UHADDR3_UHADDR_P9 8\n#define AVR32_USBB_UHADDR3_UHADDR_P9_MASK 0x00007f00\n#define AVR32_USBB_UHADDR3_UHADDR_P9_OFFSET 8\n#define AVR32_USBB_UHADDR3_UHADDR_P9_SIZE 7\n#define AVR32_USBB_UHADDR_P0 0\n#define AVR32_USBB_UHADDR_P0_MASK 0x0000007f\n#define AVR32_USBB_UHADDR_P0_OFFSET 0\n#define AVR32_USBB_UHADDR_P0_SIZE 7\n#define AVR32_USBB_UHADDR_P1 8\n#define AVR32_USBB_UHADDR_P10 16\n#define AVR32_USBB_UHADDR_P10_MASK 0x007f0000\n#define AVR32_USBB_UHADDR_P10_OFFSET 16\n#define AVR32_USBB_UHADDR_P10_SIZE 7\n#define AVR32_USBB_UHADDR_P11 24\n#define AVR32_USBB_UHADDR_P11_MASK 0x7f000000\n#define AVR32_USBB_UHADDR_P11_OFFSET 24\n#define AVR32_USBB_UHADDR_P11_SIZE 7\n#define AVR32_USBB_UHADDR_P1_MASK 0x00007f00\n#define AVR32_USBB_UHADDR_P1_OFFSET 8\n#define AVR32_USBB_UHADDR_P1_SIZE 7\n#define AVR32_USBB_UHADDR_P2 16\n#define AVR32_USBB_UHADDR_P2_MASK 0x007f0000\n#define AVR32_USBB_UHADDR_P2_OFFSET 16\n#define AVR32_USBB_UHADDR_P2_SIZE 7\n#define AVR32_USBB_UHADDR_P3 24\n#define AVR32_USBB_UHADDR_P3_MASK 0x7f000000\n#define AVR32_USBB_UHADDR_P3_OFFSET 24\n#define AVR32_USBB_UHADDR_P3_SIZE 7\n#define AVR32_USBB_UHADDR_P4 0\n#define AVR32_USBB_UHADDR_P4_MASK 0x0000007f\n#define AVR32_USBB_UHADDR_P4_OFFSET 0\n#define AVR32_USBB_UHADDR_P4_SIZE 7\n#define AVR32_USBB_UHADDR_P5 8\n#define AVR32_USBB_UHADDR_P5_MASK 0x00007f00\n#define AVR32_USBB_UHADDR_P5_OFFSET 8\n#define AVR32_USBB_UHADDR_P5_SIZE 7\n#define AVR32_USBB_UHADDR_P6 16\n#define AVR32_USBB_UHADDR_P6_MASK 0x007f0000\n#define AVR32_USBB_UHADDR_P6_OFFSET 16\n#define AVR32_USBB_UHADDR_P6_SIZE 7\n#define AVR32_USBB_UHADDR_P7 24\n#define AVR32_USBB_UHADDR_P7_MASK 0x7f000000\n#define AVR32_USBB_UHADDR_P7_OFFSET 24\n#define AVR32_USBB_UHADDR_P7_SIZE 7\n#define AVR32_USBB_UHADDR_P8 0\n#define AVR32_USBB_UHADDR_P8_MASK 0x0000007f\n#define AVR32_USBB_UHADDR_P8_OFFSET 0\n#define AVR32_USBB_UHADDR_P8_SIZE 7\n#define AVR32_USBB_UHADDR_P9 8\n#define AVR32_USBB_UHADDR_P9_MASK 0x00007f00\n#define AVR32_USBB_UHADDR_P9_OFFSET 8\n#define AVR32_USBB_UHADDR_P9_SIZE 7\n#define AVR32_USBB_UHCON 0x00000400\n#define AVR32_USBB_UHCON_RESET 9\n#define AVR32_USBB_UHCON_RESET_MASK 0x00000200\n#define AVR32_USBB_UHCON_RESET_OFFSET 9\n#define AVR32_USBB_UHCON_RESET_SIZE 1\n#define AVR32_USBB_UHCON_RESUME 10\n#define AVR32_USBB_UHCON_RESUME_MASK 0x00000400\n#define AVR32_USBB_UHCON_RESUME_OFFSET 10\n#define AVR32_USBB_UHCON_RESUME_SIZE 1\n#define AVR32_USBB_UHCON_SOFE 8\n#define AVR32_USBB_UHCON_SOFE_MASK 0x00000100\n#define AVR32_USBB_UHCON_SOFE_OFFSET 8\n#define AVR32_USBB_UHCON_SOFE_SIZE 1\n#define AVR32_USBB_UHCON_SPDCONF 12\n#define AVR32_USBB_UHCON_SPDCONF_MASK 0x00003000\n#define AVR32_USBB_UHCON_SPDCONF_OFFSET 12\n#define AVR32_USBB_UHCON_SPDCONF_SIZE 2\n#define AVR32_USBB_UHDMA1_ADDR 0x00000714\n#define AVR32_USBB_UHDMA1_ADDR_HSB_ADDR 0\n#define AVR32_USBB_UHDMA1_ADDR_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_UHDMA1_ADDR_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_UHDMA1_ADDR_HSB_ADDR_SIZE 32\n#define AVR32_USBB_UHDMA1_CONTROL 0x00000718\n#define AVR32_USBB_UHDMA1_CONTROL_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_UHDMA1_CONTROL_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_UHDMA1_CONTROL_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_UHDMA1_CONTROL_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_UHDMA1_CONTROL_BURST_LOCK_EN 7\n#define AVR32_USBB_UHDMA1_CONTROL_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_UHDMA1_CONTROL_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_UHDMA1_CONTROL_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_UHDMA1_CONTROL_CH_BYTE_LENGTH 16\n#define AVR32_USBB_UHDMA1_CONTROL_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_UHDMA1_CONTROL_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_UHDMA1_CONTROL_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_UHDMA1_CONTROL_CH_EN 0\n#define AVR32_USBB_UHDMA1_CONTROL_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UHDMA1_CONTROL_CH_EN_OFFSET 0\n#define AVR32_USBB_UHDMA1_CONTROL_CH_EN_SIZE 1\n#define AVR32_USBB_UHDMA1_CONTROL_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_UHDMA1_CONTROL_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_UHDMA1_CONTROL_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_UHDMA1_CONTROL_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA1_CONTROL_DMAEND_EN 3\n#define AVR32_USBB_UHDMA1_CONTROL_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_UHDMA1_CONTROL_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_UHDMA1_CONTROL_DMAEND_EN_SIZE 1\n#define AVR32_USBB_UHDMA1_CONTROL_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_UHDMA1_CONTROL_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_UHDMA1_CONTROL_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_UHDMA1_CONTROL_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA1_CONTROL_EOT_IRQ_EN 4\n#define AVR32_USBB_UHDMA1_CONTROL_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_UHDMA1_CONTROL_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_UHDMA1_CONTROL_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA1_CONTROL_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_UHDMA1_CONTROL_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_UHDMA1_CONTROL_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_UHDMA1_CONTROL_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_UHDMA1_NEXTDESC 0x00000710\n#define AVR32_USBB_UHDMA1_NEXTDESC_NXT_DESC_ADDR 4\n#define AVR32_USBB_UHDMA1_NEXTDESC_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_UHDMA1_NEXTDESC_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_UHDMA1_NEXTDESC_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_UHDMA1_STATUS 0x0000071c\n#define AVR32_USBB_UHDMA1_STATUS_CH_ACTIVE 1\n#define AVR32_USBB_UHDMA1_STATUS_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_UHDMA1_STATUS_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_UHDMA1_STATUS_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_UHDMA1_STATUS_CH_BYTE_CNT 16\n#define AVR32_USBB_UHDMA1_STATUS_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_UHDMA1_STATUS_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_UHDMA1_STATUS_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_UHDMA1_STATUS_CH_EN 0\n#define AVR32_USBB_UHDMA1_STATUS_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UHDMA1_STATUS_CH_EN_OFFSET 0\n#define AVR32_USBB_UHDMA1_STATUS_CH_EN_SIZE 1\n#define AVR32_USBB_UHDMA1_STATUS_DESC_LD_STA 6\n#define AVR32_USBB_UHDMA1_STATUS_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_UHDMA1_STATUS_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_UHDMA1_STATUS_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_UHDMA1_STATUS_EOCH_BUFF_STA 5\n#define AVR32_USBB_UHDMA1_STATUS_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_UHDMA1_STATUS_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_UHDMA1_STATUS_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_UHDMA1_STATUS_EOT_STA 4\n#define AVR32_USBB_UHDMA1_STATUS_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_UHDMA1_STATUS_EOT_STA_OFFSET 4\n#define AVR32_USBB_UHDMA1_STATUS_EOT_STA_SIZE 1\n#define AVR32_USBB_UHDMA2_ADDR 0x00000724\n#define AVR32_USBB_UHDMA2_ADDR_HSB_ADDR 0\n#define AVR32_USBB_UHDMA2_ADDR_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_UHDMA2_ADDR_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_UHDMA2_ADDR_HSB_ADDR_SIZE 32\n#define AVR32_USBB_UHDMA2_CONTROL 0x00000728\n#define AVR32_USBB_UHDMA2_CONTROL_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_UHDMA2_CONTROL_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_UHDMA2_CONTROL_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_UHDMA2_CONTROL_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_UHDMA2_CONTROL_BURST_LOCK_EN 7\n#define AVR32_USBB_UHDMA2_CONTROL_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_UHDMA2_CONTROL_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_UHDMA2_CONTROL_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_UHDMA2_CONTROL_CH_BYTE_LENGTH 16\n#define AVR32_USBB_UHDMA2_CONTROL_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_UHDMA2_CONTROL_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_UHDMA2_CONTROL_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_UHDMA2_CONTROL_CH_EN 0\n#define AVR32_USBB_UHDMA2_CONTROL_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UHDMA2_CONTROL_CH_EN_OFFSET 0\n#define AVR32_USBB_UHDMA2_CONTROL_CH_EN_SIZE 1\n#define AVR32_USBB_UHDMA2_CONTROL_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_UHDMA2_CONTROL_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_UHDMA2_CONTROL_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_UHDMA2_CONTROL_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA2_CONTROL_DMAEND_EN 3\n#define AVR32_USBB_UHDMA2_CONTROL_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_UHDMA2_CONTROL_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_UHDMA2_CONTROL_DMAEND_EN_SIZE 1\n#define AVR32_USBB_UHDMA2_CONTROL_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_UHDMA2_CONTROL_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_UHDMA2_CONTROL_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_UHDMA2_CONTROL_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA2_CONTROL_EOT_IRQ_EN 4\n#define AVR32_USBB_UHDMA2_CONTROL_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_UHDMA2_CONTROL_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_UHDMA2_CONTROL_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA2_CONTROL_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_UHDMA2_CONTROL_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_UHDMA2_CONTROL_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_UHDMA2_CONTROL_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_UHDMA2_NEXTDESC 0x00000720\n#define AVR32_USBB_UHDMA2_NEXTDESC_NXT_DESC_ADDR 4\n#define AVR32_USBB_UHDMA2_NEXTDESC_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_UHDMA2_NEXTDESC_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_UHDMA2_NEXTDESC_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_UHDMA2_STATUS 0x0000072c\n#define AVR32_USBB_UHDMA2_STATUS_CH_ACTIVE 1\n#define AVR32_USBB_UHDMA2_STATUS_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_UHDMA2_STATUS_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_UHDMA2_STATUS_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_UHDMA2_STATUS_CH_BYTE_CNT 16\n#define AVR32_USBB_UHDMA2_STATUS_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_UHDMA2_STATUS_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_UHDMA2_STATUS_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_UHDMA2_STATUS_CH_EN 0\n#define AVR32_USBB_UHDMA2_STATUS_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UHDMA2_STATUS_CH_EN_OFFSET 0\n#define AVR32_USBB_UHDMA2_STATUS_CH_EN_SIZE 1\n#define AVR32_USBB_UHDMA2_STATUS_DESC_LD_STA 6\n#define AVR32_USBB_UHDMA2_STATUS_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_UHDMA2_STATUS_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_UHDMA2_STATUS_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_UHDMA2_STATUS_EOCH_BUFF_STA 5\n#define AVR32_USBB_UHDMA2_STATUS_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_UHDMA2_STATUS_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_UHDMA2_STATUS_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_UHDMA2_STATUS_EOT_STA 4\n#define AVR32_USBB_UHDMA2_STATUS_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_UHDMA2_STATUS_EOT_STA_OFFSET 4\n#define AVR32_USBB_UHDMA2_STATUS_EOT_STA_SIZE 1\n#define AVR32_USBB_UHDMA3_ADDR 0x00000734\n#define AVR32_USBB_UHDMA3_ADDR_HSB_ADDR 0\n#define AVR32_USBB_UHDMA3_ADDR_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_UHDMA3_ADDR_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_UHDMA3_ADDR_HSB_ADDR_SIZE 32\n#define AVR32_USBB_UHDMA3_CONTROL 0x00000738\n#define AVR32_USBB_UHDMA3_CONTROL_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_UHDMA3_CONTROL_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_UHDMA3_CONTROL_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_UHDMA3_CONTROL_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_UHDMA3_CONTROL_BURST_LOCK_EN 7\n#define AVR32_USBB_UHDMA3_CONTROL_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_UHDMA3_CONTROL_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_UHDMA3_CONTROL_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_UHDMA3_CONTROL_CH_BYTE_LENGTH 16\n#define AVR32_USBB_UHDMA3_CONTROL_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_UHDMA3_CONTROL_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_UHDMA3_CONTROL_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_UHDMA3_CONTROL_CH_EN 0\n#define AVR32_USBB_UHDMA3_CONTROL_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UHDMA3_CONTROL_CH_EN_OFFSET 0\n#define AVR32_USBB_UHDMA3_CONTROL_CH_EN_SIZE 1\n#define AVR32_USBB_UHDMA3_CONTROL_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_UHDMA3_CONTROL_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_UHDMA3_CONTROL_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_UHDMA3_CONTROL_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA3_CONTROL_DMAEND_EN 3\n#define AVR32_USBB_UHDMA3_CONTROL_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_UHDMA3_CONTROL_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_UHDMA3_CONTROL_DMAEND_EN_SIZE 1\n#define AVR32_USBB_UHDMA3_CONTROL_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_UHDMA3_CONTROL_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_UHDMA3_CONTROL_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_UHDMA3_CONTROL_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA3_CONTROL_EOT_IRQ_EN 4\n#define AVR32_USBB_UHDMA3_CONTROL_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_UHDMA3_CONTROL_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_UHDMA3_CONTROL_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA3_CONTROL_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_UHDMA3_CONTROL_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_UHDMA3_CONTROL_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_UHDMA3_CONTROL_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_UHDMA3_NEXTDESC 0x00000730\n#define AVR32_USBB_UHDMA3_NEXTDESC_NXT_DESC_ADDR 4\n#define AVR32_USBB_UHDMA3_NEXTDESC_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_UHDMA3_NEXTDESC_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_UHDMA3_NEXTDESC_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_UHDMA3_STATUS 0x0000073c\n#define AVR32_USBB_UHDMA3_STATUS_CH_ACTIVE 1\n#define AVR32_USBB_UHDMA3_STATUS_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_UHDMA3_STATUS_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_UHDMA3_STATUS_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_UHDMA3_STATUS_CH_BYTE_CNT 16\n#define AVR32_USBB_UHDMA3_STATUS_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_UHDMA3_STATUS_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_UHDMA3_STATUS_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_UHDMA3_STATUS_CH_EN 0\n#define AVR32_USBB_UHDMA3_STATUS_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UHDMA3_STATUS_CH_EN_OFFSET 0\n#define AVR32_USBB_UHDMA3_STATUS_CH_EN_SIZE 1\n#define AVR32_USBB_UHDMA3_STATUS_DESC_LD_STA 6\n#define AVR32_USBB_UHDMA3_STATUS_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_UHDMA3_STATUS_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_UHDMA3_STATUS_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_UHDMA3_STATUS_EOCH_BUFF_STA 5\n#define AVR32_USBB_UHDMA3_STATUS_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_UHDMA3_STATUS_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_UHDMA3_STATUS_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_UHDMA3_STATUS_EOT_STA 4\n#define AVR32_USBB_UHDMA3_STATUS_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_UHDMA3_STATUS_EOT_STA_OFFSET 4\n#define AVR32_USBB_UHDMA3_STATUS_EOT_STA_SIZE 1\n#define AVR32_USBB_UHDMA4_ADDR 0x00000744\n#define AVR32_USBB_UHDMA4_ADDR_HSB_ADDR 0\n#define AVR32_USBB_UHDMA4_ADDR_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_UHDMA4_ADDR_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_UHDMA4_ADDR_HSB_ADDR_SIZE 32\n#define AVR32_USBB_UHDMA4_CONTROL 0x00000748\n#define AVR32_USBB_UHDMA4_CONTROL_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_UHDMA4_CONTROL_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_UHDMA4_CONTROL_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_UHDMA4_CONTROL_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_UHDMA4_CONTROL_BURST_LOCK_EN 7\n#define AVR32_USBB_UHDMA4_CONTROL_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_UHDMA4_CONTROL_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_UHDMA4_CONTROL_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_UHDMA4_CONTROL_CH_BYTE_LENGTH 16\n#define AVR32_USBB_UHDMA4_CONTROL_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_UHDMA4_CONTROL_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_UHDMA4_CONTROL_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_UHDMA4_CONTROL_CH_EN 0\n#define AVR32_USBB_UHDMA4_CONTROL_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UHDMA4_CONTROL_CH_EN_OFFSET 0\n#define AVR32_USBB_UHDMA4_CONTROL_CH_EN_SIZE 1\n#define AVR32_USBB_UHDMA4_CONTROL_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_UHDMA4_CONTROL_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_UHDMA4_CONTROL_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_UHDMA4_CONTROL_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA4_CONTROL_DMAEND_EN 3\n#define AVR32_USBB_UHDMA4_CONTROL_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_UHDMA4_CONTROL_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_UHDMA4_CONTROL_DMAEND_EN_SIZE 1\n#define AVR32_USBB_UHDMA4_CONTROL_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_UHDMA4_CONTROL_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_UHDMA4_CONTROL_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_UHDMA4_CONTROL_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA4_CONTROL_EOT_IRQ_EN 4\n#define AVR32_USBB_UHDMA4_CONTROL_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_UHDMA4_CONTROL_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_UHDMA4_CONTROL_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA4_CONTROL_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_UHDMA4_CONTROL_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_UHDMA4_CONTROL_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_UHDMA4_CONTROL_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_UHDMA4_NEXTDESC 0x00000740\n#define AVR32_USBB_UHDMA4_NEXTDESC_NXT_DESC_ADDR 4\n#define AVR32_USBB_UHDMA4_NEXTDESC_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_UHDMA4_NEXTDESC_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_UHDMA4_NEXTDESC_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_UHDMA4_STATUS 0x0000074c\n#define AVR32_USBB_UHDMA4_STATUS_CH_ACTIVE 1\n#define AVR32_USBB_UHDMA4_STATUS_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_UHDMA4_STATUS_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_UHDMA4_STATUS_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_UHDMA4_STATUS_CH_BYTE_CNT 16\n#define AVR32_USBB_UHDMA4_STATUS_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_UHDMA4_STATUS_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_UHDMA4_STATUS_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_UHDMA4_STATUS_CH_EN 0\n#define AVR32_USBB_UHDMA4_STATUS_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UHDMA4_STATUS_CH_EN_OFFSET 0\n#define AVR32_USBB_UHDMA4_STATUS_CH_EN_SIZE 1\n#define AVR32_USBB_UHDMA4_STATUS_DESC_LD_STA 6\n#define AVR32_USBB_UHDMA4_STATUS_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_UHDMA4_STATUS_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_UHDMA4_STATUS_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_UHDMA4_STATUS_EOCH_BUFF_STA 5\n#define AVR32_USBB_UHDMA4_STATUS_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_UHDMA4_STATUS_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_UHDMA4_STATUS_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_UHDMA4_STATUS_EOT_STA 4\n#define AVR32_USBB_UHDMA4_STATUS_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_UHDMA4_STATUS_EOT_STA_OFFSET 4\n#define AVR32_USBB_UHDMA4_STATUS_EOT_STA_SIZE 1\n#define AVR32_USBB_UHDMA5_ADDR 0x00000754\n#define AVR32_USBB_UHDMA5_ADDR_HSB_ADDR 0\n#define AVR32_USBB_UHDMA5_ADDR_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_UHDMA5_ADDR_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_UHDMA5_ADDR_HSB_ADDR_SIZE 32\n#define AVR32_USBB_UHDMA5_CONTROL 0x00000758\n#define AVR32_USBB_UHDMA5_CONTROL_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_UHDMA5_CONTROL_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_UHDMA5_CONTROL_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_UHDMA5_CONTROL_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_UHDMA5_CONTROL_BURST_LOCK_EN 7\n#define AVR32_USBB_UHDMA5_CONTROL_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_UHDMA5_CONTROL_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_UHDMA5_CONTROL_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_UHDMA5_CONTROL_CH_BYTE_LENGTH 16\n#define AVR32_USBB_UHDMA5_CONTROL_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_UHDMA5_CONTROL_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_UHDMA5_CONTROL_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_UHDMA5_CONTROL_CH_EN 0\n#define AVR32_USBB_UHDMA5_CONTROL_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UHDMA5_CONTROL_CH_EN_OFFSET 0\n#define AVR32_USBB_UHDMA5_CONTROL_CH_EN_SIZE 1\n#define AVR32_USBB_UHDMA5_CONTROL_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_UHDMA5_CONTROL_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_UHDMA5_CONTROL_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_UHDMA5_CONTROL_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA5_CONTROL_DMAEND_EN 3\n#define AVR32_USBB_UHDMA5_CONTROL_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_UHDMA5_CONTROL_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_UHDMA5_CONTROL_DMAEND_EN_SIZE 1\n#define AVR32_USBB_UHDMA5_CONTROL_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_UHDMA5_CONTROL_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_UHDMA5_CONTROL_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_UHDMA5_CONTROL_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA5_CONTROL_EOT_IRQ_EN 4\n#define AVR32_USBB_UHDMA5_CONTROL_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_UHDMA5_CONTROL_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_UHDMA5_CONTROL_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA5_CONTROL_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_UHDMA5_CONTROL_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_UHDMA5_CONTROL_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_UHDMA5_CONTROL_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_UHDMA5_NEXTDESC 0x00000750\n#define AVR32_USBB_UHDMA5_NEXTDESC_NXT_DESC_ADDR 4\n#define AVR32_USBB_UHDMA5_NEXTDESC_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_UHDMA5_NEXTDESC_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_UHDMA5_NEXTDESC_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_UHDMA5_STATUS 0x0000075c\n#define AVR32_USBB_UHDMA5_STATUS_CH_ACTIVE 1\n#define AVR32_USBB_UHDMA5_STATUS_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_UHDMA5_STATUS_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_UHDMA5_STATUS_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_UHDMA5_STATUS_CH_BYTE_CNT 16\n#define AVR32_USBB_UHDMA5_STATUS_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_UHDMA5_STATUS_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_UHDMA5_STATUS_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_UHDMA5_STATUS_CH_EN 0\n#define AVR32_USBB_UHDMA5_STATUS_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UHDMA5_STATUS_CH_EN_OFFSET 0\n#define AVR32_USBB_UHDMA5_STATUS_CH_EN_SIZE 1\n#define AVR32_USBB_UHDMA5_STATUS_DESC_LD_STA 6\n#define AVR32_USBB_UHDMA5_STATUS_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_UHDMA5_STATUS_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_UHDMA5_STATUS_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_UHDMA5_STATUS_EOCH_BUFF_STA 5\n#define AVR32_USBB_UHDMA5_STATUS_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_UHDMA5_STATUS_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_UHDMA5_STATUS_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_UHDMA5_STATUS_EOT_STA 4\n#define AVR32_USBB_UHDMA5_STATUS_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_UHDMA5_STATUS_EOT_STA_OFFSET 4\n#define AVR32_USBB_UHDMA5_STATUS_EOT_STA_SIZE 1\n#define AVR32_USBB_UHDMA6_ADDR 0x00000764\n#define AVR32_USBB_UHDMA6_ADDR_HSB_ADDR 0\n#define AVR32_USBB_UHDMA6_ADDR_HSB_ADDR_MASK 0xffffffff\n#define AVR32_USBB_UHDMA6_ADDR_HSB_ADDR_OFFSET 0\n#define AVR32_USBB_UHDMA6_ADDR_HSB_ADDR_SIZE 32\n#define AVR32_USBB_UHDMA6_CONTROL 0x00000768\n#define AVR32_USBB_UHDMA6_CONTROL_BUFF_CLOSE_IN_EN 2\n#define AVR32_USBB_UHDMA6_CONTROL_BUFF_CLOSE_IN_EN_MASK 0x00000004\n#define AVR32_USBB_UHDMA6_CONTROL_BUFF_CLOSE_IN_EN_OFFSET 2\n#define AVR32_USBB_UHDMA6_CONTROL_BUFF_CLOSE_IN_EN_SIZE 1\n#define AVR32_USBB_UHDMA6_CONTROL_BURST_LOCK_EN 7\n#define AVR32_USBB_UHDMA6_CONTROL_BURST_LOCK_EN_MASK 0x00000080\n#define AVR32_USBB_UHDMA6_CONTROL_BURST_LOCK_EN_OFFSET 7\n#define AVR32_USBB_UHDMA6_CONTROL_BURST_LOCK_EN_SIZE 1\n#define AVR32_USBB_UHDMA6_CONTROL_CH_BYTE_LENGTH 16\n#define AVR32_USBB_UHDMA6_CONTROL_CH_BYTE_LENGTH_MASK 0xffff0000\n#define AVR32_USBB_UHDMA6_CONTROL_CH_BYTE_LENGTH_OFFSET 16\n#define AVR32_USBB_UHDMA6_CONTROL_CH_BYTE_LENGTH_SIZE 16\n#define AVR32_USBB_UHDMA6_CONTROL_CH_EN 0\n#define AVR32_USBB_UHDMA6_CONTROL_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UHDMA6_CONTROL_CH_EN_OFFSET 0\n#define AVR32_USBB_UHDMA6_CONTROL_CH_EN_SIZE 1\n#define AVR32_USBB_UHDMA6_CONTROL_DESC_LD_IRQ_EN 6\n#define AVR32_USBB_UHDMA6_CONTROL_DESC_LD_IRQ_EN_MASK 0x00000040\n#define AVR32_USBB_UHDMA6_CONTROL_DESC_LD_IRQ_EN_OFFSET 6\n#define AVR32_USBB_UHDMA6_CONTROL_DESC_LD_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA6_CONTROL_DMAEND_EN 3\n#define AVR32_USBB_UHDMA6_CONTROL_DMAEND_EN_MASK 0x00000008\n#define AVR32_USBB_UHDMA6_CONTROL_DMAEND_EN_OFFSET 3\n#define AVR32_USBB_UHDMA6_CONTROL_DMAEND_EN_SIZE 1\n#define AVR32_USBB_UHDMA6_CONTROL_EOBUFF_IRQ_EN 5\n#define AVR32_USBB_UHDMA6_CONTROL_EOBUFF_IRQ_EN_MASK 0x00000020\n#define AVR32_USBB_UHDMA6_CONTROL_EOBUFF_IRQ_EN_OFFSET 5\n#define AVR32_USBB_UHDMA6_CONTROL_EOBUFF_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA6_CONTROL_EOT_IRQ_EN 4\n#define AVR32_USBB_UHDMA6_CONTROL_EOT_IRQ_EN_MASK 0x00000010\n#define AVR32_USBB_UHDMA6_CONTROL_EOT_IRQ_EN_OFFSET 4\n#define AVR32_USBB_UHDMA6_CONTROL_EOT_IRQ_EN_SIZE 1\n#define AVR32_USBB_UHDMA6_CONTROL_LD_NXT_CH_DESC_EN 1\n#define AVR32_USBB_UHDMA6_CONTROL_LD_NXT_CH_DESC_EN_MASK 0x00000002\n#define AVR32_USBB_UHDMA6_CONTROL_LD_NXT_CH_DESC_EN_OFFSET 1\n#define AVR32_USBB_UHDMA6_CONTROL_LD_NXT_CH_DESC_EN_SIZE 1\n#define AVR32_USBB_UHDMA6_NEXTDESC 0x00000760\n#define AVR32_USBB_UHDMA6_NEXTDESC_NXT_DESC_ADDR 4\n#define AVR32_USBB_UHDMA6_NEXTDESC_NXT_DESC_ADDR_MASK 0xfffffff0\n#define AVR32_USBB_UHDMA6_NEXTDESC_NXT_DESC_ADDR_OFFSET 4\n#define AVR32_USBB_UHDMA6_NEXTDESC_NXT_DESC_ADDR_SIZE 28\n#define AVR32_USBB_UHDMA6_STATUS 0x0000076c\n#define AVR32_USBB_UHDMA6_STATUS_CH_ACTIVE 1\n#define AVR32_USBB_UHDMA6_STATUS_CH_ACTIVE_MASK 0x00000002\n#define AVR32_USBB_UHDMA6_STATUS_CH_ACTIVE_OFFSET 1\n#define AVR32_USBB_UHDMA6_STATUS_CH_ACTIVE_SIZE 1\n#define AVR32_USBB_UHDMA6_STATUS_CH_BYTE_CNT 16\n#define AVR32_USBB_UHDMA6_STATUS_CH_BYTE_CNT_MASK 0xffff0000\n#define AVR32_USBB_UHDMA6_STATUS_CH_BYTE_CNT_OFFSET 16\n#define AVR32_USBB_UHDMA6_STATUS_CH_BYTE_CNT_SIZE 16\n#define AVR32_USBB_UHDMA6_STATUS_CH_EN 0\n#define AVR32_USBB_UHDMA6_STATUS_CH_EN_MASK 0x00000001\n#define AVR32_USBB_UHDMA6_STATUS_CH_EN_OFFSET 0\n#define AVR32_USBB_UHDMA6_STATUS_CH_EN_SIZE 1\n#define AVR32_USBB_UHDMA6_STATUS_DESC_LD_STA 6\n#define AVR32_USBB_UHDMA6_STATUS_DESC_LD_STA_MASK 0x00000040\n#define AVR32_USBB_UHDMA6_STATUS_DESC_LD_STA_OFFSET 6\n#define AVR32_USBB_UHDMA6_STATUS_DESC_LD_STA_SIZE 1\n#define AVR32_USBB_UHDMA6_STATUS_EOCH_BUFF_STA 5\n#define AVR32_USBB_UHDMA6_STATUS_EOCH_BUFF_STA_MASK 0x00000020\n#define AVR32_USBB_UHDMA6_STATUS_EOCH_BUFF_STA_OFFSET 5\n#define AVR32_USBB_UHDMA6_STATUS_EOCH_BUFF_STA_SIZE 1\n#define AVR32_USBB_UHDMA6_STATUS_EOT_STA 4\n#define AVR32_USBB_UHDMA6_STATUS_EOT_STA_MASK 0x00000010\n#define AVR32_USBB_UHDMA6_STATUS_EOT_STA_OFFSET 4\n#define AVR32_USBB_UHDMA6_STATUS_EOT_STA_SIZE 1\n#define AVR32_USBB_UHFNUM 0x00000420\n#define AVR32_USBB_UHFNUM_FLENHIGH 16\n#define AVR32_USBB_UHFNUM_FLENHIGH_MASK 0x00ff0000\n#define AVR32_USBB_UHFNUM_FLENHIGH_OFFSET 16\n#define AVR32_USBB_UHFNUM_FLENHIGH_SIZE 8\n#define AVR32_USBB_UHFNUM_FNUM 3\n#define AVR32_USBB_UHFNUM_FNUM_MASK 0x00003ff8\n#define AVR32_USBB_UHFNUM_FNUM_OFFSET 3\n#define AVR32_USBB_UHFNUM_FNUM_SIZE 11\n#define AVR32_USBB_UHFNUM_MFNUM 0\n#define AVR32_USBB_UHFNUM_MFNUM_MASK 0x00000007\n#define AVR32_USBB_UHFNUM_MFNUM_OFFSET 0\n#define AVR32_USBB_UHFNUM_MFNUM_SIZE 3\n#define AVR32_USBB_UHINT 0x00000404\n#define AVR32_USBB_UHINTCLR 0x00000408\n#define AVR32_USBB_UHINTCLR_DCONNIC 0\n#define AVR32_USBB_UHINTCLR_DCONNIC_MASK 0x00000001\n#define AVR32_USBB_UHINTCLR_DCONNIC_OFFSET 0\n#define AVR32_USBB_UHINTCLR_DCONNIC_SIZE 1\n#define AVR32_USBB_UHINTCLR_DDISCIC 1\n#define AVR32_USBB_UHINTCLR_DDISCIC_MASK 0x00000002\n#define AVR32_USBB_UHINTCLR_DDISCIC_OFFSET 1\n#define AVR32_USBB_UHINTCLR_DDISCIC_SIZE 1\n#define AVR32_USBB_UHINTCLR_HSOFIC 5\n#define AVR32_USBB_UHINTCLR_HSOFIC_MASK 0x00000020\n#define AVR32_USBB_UHINTCLR_HSOFIC_OFFSET 5\n#define AVR32_USBB_UHINTCLR_HSOFIC_SIZE 1\n#define AVR32_USBB_UHINTCLR_HWUPIC 6\n#define AVR32_USBB_UHINTCLR_HWUPIC_MASK 0x00000040\n#define AVR32_USBB_UHINTCLR_HWUPIC_OFFSET 6\n#define AVR32_USBB_UHINTCLR_HWUPIC_SIZE 1\n#define AVR32_USBB_UHINTCLR_RSMEDIC 3\n#define AVR32_USBB_UHINTCLR_RSMEDIC_MASK 0x00000008\n#define AVR32_USBB_UHINTCLR_RSMEDIC_OFFSET 3\n#define AVR32_USBB_UHINTCLR_RSMEDIC_SIZE 1\n#define AVR32_USBB_UHINTCLR_RSTIC 2\n#define AVR32_USBB_UHINTCLR_RSTIC_MASK 0x00000004\n#define AVR32_USBB_UHINTCLR_RSTIC_OFFSET 2\n#define AVR32_USBB_UHINTCLR_RSTIC_SIZE 1\n#define AVR32_USBB_UHINTCLR_RXRSMIC 4\n#define AVR32_USBB_UHINTCLR_RXRSMIC_MASK 0x00000010\n#define AVR32_USBB_UHINTCLR_RXRSMIC_OFFSET 4\n#define AVR32_USBB_UHINTCLR_RXRSMIC_SIZE 1\n#define AVR32_USBB_UHINTE 0x00000410\n#define AVR32_USBB_UHINTECLR 0x00000414\n#define AVR32_USBB_UHINTECLR_DCONNIEC 0\n#define AVR32_USBB_UHINTECLR_DCONNIEC_MASK 0x00000001\n#define AVR32_USBB_UHINTECLR_DCONNIEC_OFFSET 0\n#define AVR32_USBB_UHINTECLR_DCONNIEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_DDISCIEC 1\n#define AVR32_USBB_UHINTECLR_DDISCIEC_MASK 0x00000002\n#define AVR32_USBB_UHINTECLR_DDISCIEC_OFFSET 1\n#define AVR32_USBB_UHINTECLR_DDISCIEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_DMA1INTEC 25\n#define AVR32_USBB_UHINTECLR_DMA1INTEC_MASK 0x02000000\n#define AVR32_USBB_UHINTECLR_DMA1INTEC_OFFSET 25\n#define AVR32_USBB_UHINTECLR_DMA1INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_DMA2INTEC 26\n#define AVR32_USBB_UHINTECLR_DMA2INTEC_MASK 0x04000000\n#define AVR32_USBB_UHINTECLR_DMA2INTEC_OFFSET 26\n#define AVR32_USBB_UHINTECLR_DMA2INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_DMA3INTEC 27\n#define AVR32_USBB_UHINTECLR_DMA3INTEC_MASK 0x08000000\n#define AVR32_USBB_UHINTECLR_DMA3INTEC_OFFSET 27\n#define AVR32_USBB_UHINTECLR_DMA3INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_DMA4INTEC 28\n#define AVR32_USBB_UHINTECLR_DMA4INTEC_MASK 0x10000000\n#define AVR32_USBB_UHINTECLR_DMA4INTEC_OFFSET 28\n#define AVR32_USBB_UHINTECLR_DMA4INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_DMA5INTEC 29\n#define AVR32_USBB_UHINTECLR_DMA5INTEC_MASK 0x20000000\n#define AVR32_USBB_UHINTECLR_DMA5INTEC_OFFSET 29\n#define AVR32_USBB_UHINTECLR_DMA5INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_DMA6INTEC 30\n#define AVR32_USBB_UHINTECLR_DMA6INTEC_MASK 0x40000000\n#define AVR32_USBB_UHINTECLR_DMA6INTEC_OFFSET 30\n#define AVR32_USBB_UHINTECLR_DMA6INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_HSOFIEC 5\n#define AVR32_USBB_UHINTECLR_HSOFIEC_MASK 0x00000020\n#define AVR32_USBB_UHINTECLR_HSOFIEC_OFFSET 5\n#define AVR32_USBB_UHINTECLR_HSOFIEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_HWUPIEC 6\n#define AVR32_USBB_UHINTECLR_HWUPIEC_MASK 0x00000040\n#define AVR32_USBB_UHINTECLR_HWUPIEC_OFFSET 6\n#define AVR32_USBB_UHINTECLR_HWUPIEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_P0INTEC 8\n#define AVR32_USBB_UHINTECLR_P0INTEC_MASK 0x00000100\n#define AVR32_USBB_UHINTECLR_P0INTEC_OFFSET 8\n#define AVR32_USBB_UHINTECLR_P0INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_P1INTEC 9\n#define AVR32_USBB_UHINTECLR_P1INTEC_MASK 0x00000200\n#define AVR32_USBB_UHINTECLR_P1INTEC_OFFSET 9\n#define AVR32_USBB_UHINTECLR_P1INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_P2INTEC 10\n#define AVR32_USBB_UHINTECLR_P2INTEC_MASK 0x00000400\n#define AVR32_USBB_UHINTECLR_P2INTEC_OFFSET 10\n#define AVR32_USBB_UHINTECLR_P2INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_P3INTEC 11\n#define AVR32_USBB_UHINTECLR_P3INTEC_MASK 0x00000800\n#define AVR32_USBB_UHINTECLR_P3INTEC_OFFSET 11\n#define AVR32_USBB_UHINTECLR_P3INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_P4INTEC 12\n#define AVR32_USBB_UHINTECLR_P4INTEC_MASK 0x00001000\n#define AVR32_USBB_UHINTECLR_P4INTEC_OFFSET 12\n#define AVR32_USBB_UHINTECLR_P4INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_P5INTEC 13\n#define AVR32_USBB_UHINTECLR_P5INTEC_MASK 0x00002000\n#define AVR32_USBB_UHINTECLR_P5INTEC_OFFSET 13\n#define AVR32_USBB_UHINTECLR_P5INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_P6INTEC 14\n#define AVR32_USBB_UHINTECLR_P6INTEC_MASK 0x00004000\n#define AVR32_USBB_UHINTECLR_P6INTEC_OFFSET 14\n#define AVR32_USBB_UHINTECLR_P6INTEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_RSMEDIEC 3\n#define AVR32_USBB_UHINTECLR_RSMEDIEC_MASK 0x00000008\n#define AVR32_USBB_UHINTECLR_RSMEDIEC_OFFSET 3\n#define AVR32_USBB_UHINTECLR_RSMEDIEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_RSTIEC 2\n#define AVR32_USBB_UHINTECLR_RSTIEC_MASK 0x00000004\n#define AVR32_USBB_UHINTECLR_RSTIEC_OFFSET 2\n#define AVR32_USBB_UHINTECLR_RSTIEC_SIZE 1\n#define AVR32_USBB_UHINTECLR_RXRSMIEC 4\n#define AVR32_USBB_UHINTECLR_RXRSMIEC_MASK 0x00000010\n#define AVR32_USBB_UHINTECLR_RXRSMIEC_OFFSET 4\n#define AVR32_USBB_UHINTECLR_RXRSMIEC_SIZE 1\n#define AVR32_USBB_UHINTESET 0x00000418\n#define AVR32_USBB_UHINTESET_DCONNIES 0\n#define AVR32_USBB_UHINTESET_DCONNIES_MASK 0x00000001\n#define AVR32_USBB_UHINTESET_DCONNIES_OFFSET 0\n#define AVR32_USBB_UHINTESET_DCONNIES_SIZE 1\n#define AVR32_USBB_UHINTESET_DDISCIES 1\n#define AVR32_USBB_UHINTESET_DDISCIES_MASK 0x00000002\n#define AVR32_USBB_UHINTESET_DDISCIES_OFFSET 1\n#define AVR32_USBB_UHINTESET_DDISCIES_SIZE 1\n#define AVR32_USBB_UHINTESET_DMA1INTES 25\n#define AVR32_USBB_UHINTESET_DMA1INTES_MASK 0x02000000\n#define AVR32_USBB_UHINTESET_DMA1INTES_OFFSET 25\n#define AVR32_USBB_UHINTESET_DMA1INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_DMA2INTES 26\n#define AVR32_USBB_UHINTESET_DMA2INTES_MASK 0x04000000\n#define AVR32_USBB_UHINTESET_DMA2INTES_OFFSET 26\n#define AVR32_USBB_UHINTESET_DMA2INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_DMA3INTES 27\n#define AVR32_USBB_UHINTESET_DMA3INTES_MASK 0x08000000\n#define AVR32_USBB_UHINTESET_DMA3INTES_OFFSET 27\n#define AVR32_USBB_UHINTESET_DMA3INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_DMA4INTES 28\n#define AVR32_USBB_UHINTESET_DMA4INTES_MASK 0x10000000\n#define AVR32_USBB_UHINTESET_DMA4INTES_OFFSET 28\n#define AVR32_USBB_UHINTESET_DMA4INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_DMA5INTES 29\n#define AVR32_USBB_UHINTESET_DMA5INTES_MASK 0x20000000\n#define AVR32_USBB_UHINTESET_DMA5INTES_OFFSET 29\n#define AVR32_USBB_UHINTESET_DMA5INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_DMA6INTES 30\n#define AVR32_USBB_UHINTESET_DMA6INTES_MASK 0x40000000\n#define AVR32_USBB_UHINTESET_DMA6INTES_OFFSET 30\n#define AVR32_USBB_UHINTESET_DMA6INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_HSOFIES 5\n#define AVR32_USBB_UHINTESET_HSOFIES_MASK 0x00000020\n#define AVR32_USBB_UHINTESET_HSOFIES_OFFSET 5\n#define AVR32_USBB_UHINTESET_HSOFIES_SIZE 1\n#define AVR32_USBB_UHINTESET_HWUPIES 6\n#define AVR32_USBB_UHINTESET_HWUPIES_MASK 0x00000040\n#define AVR32_USBB_UHINTESET_HWUPIES_OFFSET 6\n#define AVR32_USBB_UHINTESET_HWUPIES_SIZE 1\n#define AVR32_USBB_UHINTESET_P0INTES 8\n#define AVR32_USBB_UHINTESET_P0INTES_MASK 0x00000100\n#define AVR32_USBB_UHINTESET_P0INTES_OFFSET 8\n#define AVR32_USBB_UHINTESET_P0INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_P1INTES 9\n#define AVR32_USBB_UHINTESET_P1INTES_MASK 0x00000200\n#define AVR32_USBB_UHINTESET_P1INTES_OFFSET 9\n#define AVR32_USBB_UHINTESET_P1INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_P2INTES 10\n#define AVR32_USBB_UHINTESET_P2INTES_MASK 0x00000400\n#define AVR32_USBB_UHINTESET_P2INTES_OFFSET 10\n#define AVR32_USBB_UHINTESET_P2INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_P3INTES 11\n#define AVR32_USBB_UHINTESET_P3INTES_MASK 0x00000800\n#define AVR32_USBB_UHINTESET_P3INTES_OFFSET 11\n#define AVR32_USBB_UHINTESET_P3INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_P4INTES 12\n#define AVR32_USBB_UHINTESET_P4INTES_MASK 0x00001000\n#define AVR32_USBB_UHINTESET_P4INTES_OFFSET 12\n#define AVR32_USBB_UHINTESET_P4INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_P5INTES 13\n#define AVR32_USBB_UHINTESET_P5INTES_MASK 0x00002000\n#define AVR32_USBB_UHINTESET_P5INTES_OFFSET 13\n#define AVR32_USBB_UHINTESET_P5INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_P6INTES 14\n#define AVR32_USBB_UHINTESET_P6INTES_MASK 0x00004000\n#define AVR32_USBB_UHINTESET_P6INTES_OFFSET 14\n#define AVR32_USBB_UHINTESET_P6INTES_SIZE 1\n#define AVR32_USBB_UHINTESET_RSMEDIES 3\n#define AVR32_USBB_UHINTESET_RSMEDIES_MASK 0x00000008\n#define AVR32_USBB_UHINTESET_RSMEDIES_OFFSET 3\n#define AVR32_USBB_UHINTESET_RSMEDIES_SIZE 1\n#define AVR32_USBB_UHINTESET_RSTIES 2\n#define AVR32_USBB_UHINTESET_RSTIES_MASK 0x00000004\n#define AVR32_USBB_UHINTESET_RSTIES_OFFSET 2\n#define AVR32_USBB_UHINTESET_RSTIES_SIZE 1\n#define AVR32_USBB_UHINTESET_RXRSMIES 4\n#define AVR32_USBB_UHINTESET_RXRSMIES_MASK 0x00000010\n#define AVR32_USBB_UHINTESET_RXRSMIES_OFFSET 4\n#define AVR32_USBB_UHINTESET_RXRSMIES_SIZE 1\n#define AVR32_USBB_UHINTE_DCONNIE 0\n#define AVR32_USBB_UHINTE_DCONNIE_MASK 0x00000001\n#define AVR32_USBB_UHINTE_DCONNIE_OFFSET 0\n#define AVR32_USBB_UHINTE_DCONNIE_SIZE 1\n#define AVR32_USBB_UHINTE_DDISCIE 1\n#define AVR32_USBB_UHINTE_DDISCIE_MASK 0x00000002\n#define AVR32_USBB_UHINTE_DDISCIE_OFFSET 1\n#define AVR32_USBB_UHINTE_DDISCIE_SIZE 1\n#define AVR32_USBB_UHINTE_DMA1INTE 25\n#define AVR32_USBB_UHINTE_DMA1INTE_MASK 0x02000000\n#define AVR32_USBB_UHINTE_DMA1INTE_OFFSET 25\n#define AVR32_USBB_UHINTE_DMA1INTE_SIZE 1\n#define AVR32_USBB_UHINTE_DMA2INTE 26\n#define AVR32_USBB_UHINTE_DMA2INTE_MASK 0x04000000\n#define AVR32_USBB_UHINTE_DMA2INTE_OFFSET 26\n#define AVR32_USBB_UHINTE_DMA2INTE_SIZE 1\n#define AVR32_USBB_UHINTE_DMA3INTE 27\n#define AVR32_USBB_UHINTE_DMA3INTE_MASK 0x08000000\n#define AVR32_USBB_UHINTE_DMA3INTE_OFFSET 27\n#define AVR32_USBB_UHINTE_DMA3INTE_SIZE 1\n#define AVR32_USBB_UHINTE_DMA4INTE 28\n#define AVR32_USBB_UHINTE_DMA4INTE_MASK 0x10000000\n#define AVR32_USBB_UHINTE_DMA4INTE_OFFSET 28\n#define AVR32_USBB_UHINTE_DMA4INTE_SIZE 1\n#define AVR32_USBB_UHINTE_DMA5INTE 29\n#define AVR32_USBB_UHINTE_DMA5INTE_MASK 0x20000000\n#define AVR32_USBB_UHINTE_DMA5INTE_OFFSET 29\n#define AVR32_USBB_UHINTE_DMA5INTE_SIZE 1\n#define AVR32_USBB_UHINTE_DMA6INTE 30\n#define AVR32_USBB_UHINTE_DMA6INTE_MASK 0x40000000\n#define AVR32_USBB_UHINTE_DMA6INTE_OFFSET 30\n#define AVR32_USBB_UHINTE_DMA6INTE_SIZE 1\n#define AVR32_USBB_UHINTE_HSOFIE 5\n#define AVR32_USBB_UHINTE_HSOFIE_MASK 0x00000020\n#define AVR32_USBB_UHINTE_HSOFIE_OFFSET 5\n#define AVR32_USBB_UHINTE_HSOFIE_SIZE 1\n#define AVR32_USBB_UHINTE_HWUPIE 6\n#define AVR32_USBB_UHINTE_HWUPIE_MASK 0x00000040\n#define AVR32_USBB_UHINTE_HWUPIE_OFFSET 6\n#define AVR32_USBB_UHINTE_HWUPIE_SIZE 1\n#define AVR32_USBB_UHINTE_P0INTE 8\n#define AVR32_USBB_UHINTE_P0INTE_MASK 0x00000100\n#define AVR32_USBB_UHINTE_P0INTE_OFFSET 8\n#define AVR32_USBB_UHINTE_P0INTE_SIZE 1\n#define AVR32_USBB_UHINTE_P1INTE 9\n#define AVR32_USBB_UHINTE_P1INTE_MASK 0x00000200\n#define AVR32_USBB_UHINTE_P1INTE_OFFSET 9\n#define AVR32_USBB_UHINTE_P1INTE_SIZE 1\n#define AVR32_USBB_UHINTE_P2INTE 10\n#define AVR32_USBB_UHINTE_P2INTE_MASK 0x00000400\n#define AVR32_USBB_UHINTE_P2INTE_OFFSET 10\n#define AVR32_USBB_UHINTE_P2INTE_SIZE 1\n#define AVR32_USBB_UHINTE_P3INTE 11\n#define AVR32_USBB_UHINTE_P3INTE_MASK 0x00000800\n#define AVR32_USBB_UHINTE_P3INTE_OFFSET 11\n#define AVR32_USBB_UHINTE_P3INTE_SIZE 1\n#define AVR32_USBB_UHINTE_P4INTE 12\n#define AVR32_USBB_UHINTE_P4INTE_MASK 0x00001000\n#define AVR32_USBB_UHINTE_P4INTE_OFFSET 12\n#define AVR32_USBB_UHINTE_P4INTE_SIZE 1\n#define AVR32_USBB_UHINTE_P5INTE 13\n#define AVR32_USBB_UHINTE_P5INTE_MASK 0x00002000\n#define AVR32_USBB_UHINTE_P5INTE_OFFSET 13\n#define AVR32_USBB_UHINTE_P5INTE_SIZE 1\n#define AVR32_USBB_UHINTE_P6INTE 14\n#define AVR32_USBB_UHINTE_P6INTE_MASK 0x00004000\n#define AVR32_USBB_UHINTE_P6INTE_OFFSET 14\n#define AVR32_USBB_UHINTE_P6INTE_SIZE 1\n#define AVR32_USBB_UHINTE_RSMEDIE 3\n#define AVR32_USBB_UHINTE_RSMEDIE_MASK 0x00000008\n#define AVR32_USBB_UHINTE_RSMEDIE_OFFSET 3\n#define AVR32_USBB_UHINTE_RSMEDIE_SIZE 1\n#define AVR32_USBB_UHINTE_RSTIE 2\n#define AVR32_USBB_UHINTE_RSTIE_MASK 0x00000004\n#define AVR32_USBB_UHINTE_RSTIE_OFFSET 2\n#define AVR32_USBB_UHINTE_RSTIE_SIZE 1\n#define AVR32_USBB_UHINTE_RXRSMIE 4\n#define AVR32_USBB_UHINTE_RXRSMIE_MASK 0x00000010\n#define AVR32_USBB_UHINTE_RXRSMIE_OFFSET 4\n#define AVR32_USBB_UHINTE_RXRSMIE_SIZE 1\n#define AVR32_USBB_UHINTSET 0x0000040c\n#define AVR32_USBB_UHINTSET_DCONNIS 0\n#define AVR32_USBB_UHINTSET_DCONNIS_MASK 0x00000001\n#define AVR32_USBB_UHINTSET_DCONNIS_OFFSET 0\n#define AVR32_USBB_UHINTSET_DCONNIS_SIZE 1\n#define AVR32_USBB_UHINTSET_DDISCIS 1\n#define AVR32_USBB_UHINTSET_DDISCIS_MASK 0x00000002\n#define AVR32_USBB_UHINTSET_DDISCIS_OFFSET 1\n#define AVR32_USBB_UHINTSET_DDISCIS_SIZE 1\n#define AVR32_USBB_UHINTSET_DMA1INTS 25\n#define AVR32_USBB_UHINTSET_DMA1INTS_MASK 0x02000000\n#define AVR32_USBB_UHINTSET_DMA1INTS_OFFSET 25\n#define AVR32_USBB_UHINTSET_DMA1INTS_SIZE 1\n#define AVR32_USBB_UHINTSET_DMA2INTS 26\n#define AVR32_USBB_UHINTSET_DMA2INTS_MASK 0x04000000\n#define AVR32_USBB_UHINTSET_DMA2INTS_OFFSET 26\n#define AVR32_USBB_UHINTSET_DMA2INTS_SIZE 1\n#define AVR32_USBB_UHINTSET_DMA3INTS 27\n#define AVR32_USBB_UHINTSET_DMA3INTS_MASK 0x08000000\n#define AVR32_USBB_UHINTSET_DMA3INTS_OFFSET 27\n#define AVR32_USBB_UHINTSET_DMA3INTS_SIZE 1\n#define AVR32_USBB_UHINTSET_DMA4INTS 28\n#define AVR32_USBB_UHINTSET_DMA4INTS_MASK 0x10000000\n#define AVR32_USBB_UHINTSET_DMA4INTS_OFFSET 28\n#define AVR32_USBB_UHINTSET_DMA4INTS_SIZE 1\n#define AVR32_USBB_UHINTSET_DMA5INTS 29\n#define AVR32_USBB_UHINTSET_DMA5INTS_MASK 0x20000000\n#define AVR32_USBB_UHINTSET_DMA5INTS_OFFSET 29\n#define AVR32_USBB_UHINTSET_DMA5INTS_SIZE 1\n#define AVR32_USBB_UHINTSET_DMA6INTS 30\n#define AVR32_USBB_UHINTSET_DMA6INTS_MASK 0x40000000\n#define AVR32_USBB_UHINTSET_DMA6INTS_OFFSET 30\n#define AVR32_USBB_UHINTSET_DMA6INTS_SIZE 1\n#define AVR32_USBB_UHINTSET_HSOFIS 5\n#define AVR32_USBB_UHINTSET_HSOFIS_MASK 0x00000020\n#define AVR32_USBB_UHINTSET_HSOFIS_OFFSET 5\n#define AVR32_USBB_UHINTSET_HSOFIS_SIZE 1\n#define AVR32_USBB_UHINTSET_HWUPIS 6\n#define AVR32_USBB_UHINTSET_HWUPIS_MASK 0x00000040\n#define AVR32_USBB_UHINTSET_HWUPIS_OFFSET 6\n#define AVR32_USBB_UHINTSET_HWUPIS_SIZE 1\n#define AVR32_USBB_UHINTSET_RSMEDIS 3\n#define AVR32_USBB_UHINTSET_RSMEDIS_MASK 0x00000008\n#define AVR32_USBB_UHINTSET_RSMEDIS_OFFSET 3\n#define AVR32_USBB_UHINTSET_RSMEDIS_SIZE 1\n#define AVR32_USBB_UHINTSET_RSTIS 2\n#define AVR32_USBB_UHINTSET_RSTIS_MASK 0x00000004\n#define AVR32_USBB_UHINTSET_RSTIS_OFFSET 2\n#define AVR32_USBB_UHINTSET_RSTIS_SIZE 1\n#define AVR32_USBB_UHINTSET_RXRSMIS 4\n#define AVR32_USBB_UHINTSET_RXRSMIS_MASK 0x00000010\n#define AVR32_USBB_UHINTSET_RXRSMIS_OFFSET 4\n#define AVR32_USBB_UHINTSET_RXRSMIS_SIZE 1\n#define AVR32_USBB_UHINT_DCONNI 0\n#define AVR32_USBB_UHINT_DCONNI_MASK 0x00000001\n#define AVR32_USBB_UHINT_DCONNI_OFFSET 0\n#define AVR32_USBB_UHINT_DCONNI_SIZE 1\n#define AVR32_USBB_UHINT_DDISCI 1\n#define AVR32_USBB_UHINT_DDISCI_MASK 0x00000002\n#define AVR32_USBB_UHINT_DDISCI_OFFSET 1\n#define AVR32_USBB_UHINT_DDISCI_SIZE 1\n#define AVR32_USBB_UHINT_DMA1INT 25\n#define AVR32_USBB_UHINT_DMA1INT_MASK 0x02000000\n#define AVR32_USBB_UHINT_DMA1INT_OFFSET 25\n#define AVR32_USBB_UHINT_DMA1INT_SIZE 1\n#define AVR32_USBB_UHINT_DMA2INT 26\n#define AVR32_USBB_UHINT_DMA2INT_MASK 0x04000000\n#define AVR32_USBB_UHINT_DMA2INT_OFFSET 26\n#define AVR32_USBB_UHINT_DMA2INT_SIZE 1\n#define AVR32_USBB_UHINT_DMA3INT 27\n#define AVR32_USBB_UHINT_DMA3INT_MASK 0x08000000\n#define AVR32_USBB_UHINT_DMA3INT_OFFSET 27\n#define AVR32_USBB_UHINT_DMA3INT_SIZE 1\n#define AVR32_USBB_UHINT_DMA4INT 28\n#define AVR32_USBB_UHINT_DMA4INT_MASK 0x10000000\n#define AVR32_USBB_UHINT_DMA4INT_OFFSET 28\n#define AVR32_USBB_UHINT_DMA4INT_SIZE 1\n#define AVR32_USBB_UHINT_DMA5INT 29\n#define AVR32_USBB_UHINT_DMA5INT_MASK 0x20000000\n#define AVR32_USBB_UHINT_DMA5INT_OFFSET 29\n#define AVR32_USBB_UHINT_DMA5INT_SIZE 1\n#define AVR32_USBB_UHINT_DMA6INT 30\n#define AVR32_USBB_UHINT_DMA6INT_MASK 0x40000000\n#define AVR32_USBB_UHINT_DMA6INT_OFFSET 30\n#define AVR32_USBB_UHINT_DMA6INT_SIZE 1\n#define AVR32_USBB_UHINT_HSOFI 5\n#define AVR32_USBB_UHINT_HSOFI_MASK 0x00000020\n#define AVR32_USBB_UHINT_HSOFI_OFFSET 5\n#define AVR32_USBB_UHINT_HSOFI_SIZE 1\n#define AVR32_USBB_UHINT_HWUPI 6\n#define AVR32_USBB_UHINT_HWUPI_MASK 0x00000040\n#define AVR32_USBB_UHINT_HWUPI_OFFSET 6\n#define AVR32_USBB_UHINT_HWUPI_SIZE 1\n#define AVR32_USBB_UHINT_P0INT 8\n#define AVR32_USBB_UHINT_P0INT_MASK 0x00000100\n#define AVR32_USBB_UHINT_P0INT_OFFSET 8\n#define AVR32_USBB_UHINT_P0INT_SIZE 1\n#define AVR32_USBB_UHINT_P1INT 9\n#define AVR32_USBB_UHINT_P1INT_MASK 0x00000200\n#define AVR32_USBB_UHINT_P1INT_OFFSET 9\n#define AVR32_USBB_UHINT_P1INT_SIZE 1\n#define AVR32_USBB_UHINT_P2INT 10\n#define AVR32_USBB_UHINT_P2INT_MASK 0x00000400\n#define AVR32_USBB_UHINT_P2INT_OFFSET 10\n#define AVR32_USBB_UHINT_P2INT_SIZE 1\n#define AVR32_USBB_UHINT_P3INT 11\n#define AVR32_USBB_UHINT_P3INT_MASK 0x00000800\n#define AVR32_USBB_UHINT_P3INT_OFFSET 11\n#define AVR32_USBB_UHINT_P3INT_SIZE 1\n#define AVR32_USBB_UHINT_P4INT 12\n#define AVR32_USBB_UHINT_P4INT_MASK 0x00001000\n#define AVR32_USBB_UHINT_P4INT_OFFSET 12\n#define AVR32_USBB_UHINT_P4INT_SIZE 1\n#define AVR32_USBB_UHINT_P5INT 13\n#define AVR32_USBB_UHINT_P5INT_MASK 0x00002000\n#define AVR32_USBB_UHINT_P5INT_OFFSET 13\n#define AVR32_USBB_UHINT_P5INT_SIZE 1\n#define AVR32_USBB_UHINT_P6INT 14\n#define AVR32_USBB_UHINT_P6INT_MASK 0x00004000\n#define AVR32_USBB_UHINT_P6INT_OFFSET 14\n#define AVR32_USBB_UHINT_P6INT_SIZE 1\n#define AVR32_USBB_UHINT_RSMEDI 3\n#define AVR32_USBB_UHINT_RSMEDI_MASK 0x00000008\n#define AVR32_USBB_UHINT_RSMEDI_OFFSET 3\n#define AVR32_USBB_UHINT_RSMEDI_SIZE 1\n#define AVR32_USBB_UHINT_RSTI 2\n#define AVR32_USBB_UHINT_RSTI_MASK 0x00000004\n#define AVR32_USBB_UHINT_RSTI_OFFSET 2\n#define AVR32_USBB_UHINT_RSTI_SIZE 1\n#define AVR32_USBB_UHINT_RXRSMI 4\n#define AVR32_USBB_UHINT_RXRSMI_MASK 0x00000010\n#define AVR32_USBB_UHINT_RXRSMI_OFFSET 4\n#define AVR32_USBB_UHINT_RXRSMI_SIZE 1\n#define AVR32_USBB_UIDE 24\n#define AVR32_USBB_UIDE_MASK 0x01000000\n#define AVR32_USBB_UIDE_OFFSET 24\n#define AVR32_USBB_UIDE_SIZE 1\n#define AVR32_USBB_UIMOD 25\n#define AVR32_USBB_UIMOD_MASK 0x02000000\n#define AVR32_USBB_UIMOD_OFFSET 25\n#define AVR32_USBB_UIMOD_SIZE 1\n#define AVR32_USBB_UNAME1 0x00000824\n#define AVR32_USBB_UNAME1_MASK 0xffffffff\n#define AVR32_USBB_UNAME1_OFFSET 0\n#define AVR32_USBB_UNAME1_SIZE 32\n#define AVR32_USBB_UNAME1_UNAME1 0\n#define AVR32_USBB_UNAME1_UNAME1_MASK 0xffffffff\n#define AVR32_USBB_UNAME1_UNAME1_OFFSET 0\n#define AVR32_USBB_UNAME1_UNAME1_SIZE 32\n#define AVR32_USBB_UNAME2 0x00000828\n#define AVR32_USBB_UNAME2_MASK 0xffffffff\n#define AVR32_USBB_UNAME2_OFFSET 0\n#define AVR32_USBB_UNAME2_SIZE 32\n#define AVR32_USBB_UNAME2_UNAME2 0\n#define AVR32_USBB_UNAME2_UNAME2_MASK 0xffffffff\n#define AVR32_USBB_UNAME2_UNAME2_OFFSET 0\n#define AVR32_USBB_UNAME2_UNAME2_SIZE 32\n#define AVR32_USBB_UNLOCK 22\n#define AVR32_USBB_UNLOCK_MASK 0x00400000\n#define AVR32_USBB_UNLOCK_OFFSET 22\n#define AVR32_USBB_UNLOCK_SIZE 1\n#define AVR32_USBB_UPCFG0 0x00000500\n#define AVR32_USBB_UPCFG0_ALLOC 1\n#define AVR32_USBB_UPCFG0_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UPCFG0_ALLOC_OFFSET 1\n#define AVR32_USBB_UPCFG0_ALLOC_SIZE 1\n#define AVR32_USBB_UPCFG0_AUTOSW 10\n#define AVR32_USBB_UPCFG0_AUTOSW_MASK 0x00000400\n#define AVR32_USBB_UPCFG0_AUTOSW_OFFSET 10\n#define AVR32_USBB_UPCFG0_AUTOSW_SIZE 1\n#define AVR32_USBB_UPCFG0_DATASIZERDWR 22\n#define AVR32_USBB_UPCFG0_DATASIZERDWR_MASK 0x00c00000\n#define AVR32_USBB_UPCFG0_DATASIZERDWR_OFFSET 22\n#define AVR32_USBB_UPCFG0_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UPCFG0_INTFRQ 24\n#define AVR32_USBB_UPCFG0_INTFRQ_MASK 0xff000000\n#define AVR32_USBB_UPCFG0_INTFRQ_OFFSET 24\n#define AVR32_USBB_UPCFG0_INTFRQ_SIZE 8\n#define AVR32_USBB_UPCFG0_PBK 2\n#define AVR32_USBB_UPCFG0_PBK_DOUBLE 0x00000001\n#define AVR32_USBB_UPCFG0_PBK_MASK 0x0000000c\n#define AVR32_USBB_UPCFG0_PBK_OFFSET 2\n#define AVR32_USBB_UPCFG0_PBK_SINGLE 0x00000000\n#define AVR32_USBB_UPCFG0_PBK_SIZE 2\n#define AVR32_USBB_UPCFG0_PBK_TRIPLE 0x00000002\n#define AVR32_USBB_UPCFG0_PEPNUM 16\n#define AVR32_USBB_UPCFG0_PEPNUM_MASK 0x000f0000\n#define AVR32_USBB_UPCFG0_PEPNUM_OFFSET 16\n#define AVR32_USBB_UPCFG0_PEPNUM_SIZE 4\n#define AVR32_USBB_UPCFG0_PINGEN 20\n#define AVR32_USBB_UPCFG0_PINGEN_MASK 0x00100000\n#define AVR32_USBB_UPCFG0_PINGEN_OFFSET 20\n#define AVR32_USBB_UPCFG0_PINGEN_SIZE 1\n#define AVR32_USBB_UPCFG0_PSIZE 4\n#define AVR32_USBB_UPCFG0_PSIZE_1024 0x00000007\n#define AVR32_USBB_UPCFG0_PSIZE_128 0x00000004\n#define AVR32_USBB_UPCFG0_PSIZE_16 0x00000001\n#define AVR32_USBB_UPCFG0_PSIZE_256 0x00000005\n#define AVR32_USBB_UPCFG0_PSIZE_32 0x00000002\n#define AVR32_USBB_UPCFG0_PSIZE_512 0x00000006\n#define AVR32_USBB_UPCFG0_PSIZE_64 0x00000003\n#define AVR32_USBB_UPCFG0_PSIZE_8 0x00000000\n#define AVR32_USBB_UPCFG0_PSIZE_MASK 0x00000070\n#define AVR32_USBB_UPCFG0_PSIZE_OFFSET 4\n#define AVR32_USBB_UPCFG0_PSIZE_SIZE 3\n#define AVR32_USBB_UPCFG0_PTOKEN 8\n#define AVR32_USBB_UPCFG0_PTOKEN_IN 0x00000001\n#define AVR32_USBB_UPCFG0_PTOKEN_MASK 0x00000300\n#define AVR32_USBB_UPCFG0_PTOKEN_OFFSET 8\n#define AVR32_USBB_UPCFG0_PTOKEN_OUT 0x00000002\n#define AVR32_USBB_UPCFG0_PTOKEN_SETUP 0x00000000\n#define AVR32_USBB_UPCFG0_PTOKEN_SIZE 2\n#define AVR32_USBB_UPCFG0_PTYPE 12\n#define AVR32_USBB_UPCFG0_PTYPE_BULK 0x00000002\n#define AVR32_USBB_UPCFG0_PTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UPCFG0_PTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UPCFG0_PTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UPCFG0_PTYPE_MASK 0x00003000\n#define AVR32_USBB_UPCFG0_PTYPE_OFFSET 12\n#define AVR32_USBB_UPCFG0_PTYPE_SIZE 2\n#define AVR32_USBB_UPCFG1 0x00000504\n#define AVR32_USBB_UPCFG1_ALLOC 1\n#define AVR32_USBB_UPCFG1_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UPCFG1_ALLOC_OFFSET 1\n#define AVR32_USBB_UPCFG1_ALLOC_SIZE 1\n#define AVR32_USBB_UPCFG1_AUTOSW 10\n#define AVR32_USBB_UPCFG1_AUTOSW_MASK 0x00000400\n#define AVR32_USBB_UPCFG1_AUTOSW_OFFSET 10\n#define AVR32_USBB_UPCFG1_AUTOSW_SIZE 1\n#define AVR32_USBB_UPCFG1_DATASIZERDWR 22\n#define AVR32_USBB_UPCFG1_DATASIZERDWR_MASK 0x00c00000\n#define AVR32_USBB_UPCFG1_DATASIZERDWR_OFFSET 22\n#define AVR32_USBB_UPCFG1_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UPCFG1_INTFRQ 24\n#define AVR32_USBB_UPCFG1_INTFRQ_MASK 0xff000000\n#define AVR32_USBB_UPCFG1_INTFRQ_OFFSET 24\n#define AVR32_USBB_UPCFG1_INTFRQ_SIZE 8\n#define AVR32_USBB_UPCFG1_PBK 2\n#define AVR32_USBB_UPCFG1_PBK_DOUBLE 0x00000001\n#define AVR32_USBB_UPCFG1_PBK_MASK 0x0000000c\n#define AVR32_USBB_UPCFG1_PBK_OFFSET 2\n#define AVR32_USBB_UPCFG1_PBK_SINGLE 0x00000000\n#define AVR32_USBB_UPCFG1_PBK_SIZE 2\n#define AVR32_USBB_UPCFG1_PBK_TRIPLE 0x00000002\n#define AVR32_USBB_UPCFG1_PEPNUM 16\n#define AVR32_USBB_UPCFG1_PEPNUM_MASK 0x000f0000\n#define AVR32_USBB_UPCFG1_PEPNUM_OFFSET 16\n#define AVR32_USBB_UPCFG1_PEPNUM_SIZE 4\n#define AVR32_USBB_UPCFG1_PINGEN 20\n#define AVR32_USBB_UPCFG1_PINGEN_MASK 0x00100000\n#define AVR32_USBB_UPCFG1_PINGEN_OFFSET 20\n#define AVR32_USBB_UPCFG1_PINGEN_SIZE 1\n#define AVR32_USBB_UPCFG1_PSIZE 4\n#define AVR32_USBB_UPCFG1_PSIZE_1024 0x00000007\n#define AVR32_USBB_UPCFG1_PSIZE_128 0x00000004\n#define AVR32_USBB_UPCFG1_PSIZE_16 0x00000001\n#define AVR32_USBB_UPCFG1_PSIZE_256 0x00000005\n#define AVR32_USBB_UPCFG1_PSIZE_32 0x00000002\n#define AVR32_USBB_UPCFG1_PSIZE_512 0x00000006\n#define AVR32_USBB_UPCFG1_PSIZE_64 0x00000003\n#define AVR32_USBB_UPCFG1_PSIZE_8 0x00000000\n#define AVR32_USBB_UPCFG1_PSIZE_MASK 0x00000070\n#define AVR32_USBB_UPCFG1_PSIZE_OFFSET 4\n#define AVR32_USBB_UPCFG1_PSIZE_SIZE 3\n#define AVR32_USBB_UPCFG1_PTOKEN 8\n#define AVR32_USBB_UPCFG1_PTOKEN_IN 0x00000001\n#define AVR32_USBB_UPCFG1_PTOKEN_MASK 0x00000300\n#define AVR32_USBB_UPCFG1_PTOKEN_OFFSET 8\n#define AVR32_USBB_UPCFG1_PTOKEN_OUT 0x00000002\n#define AVR32_USBB_UPCFG1_PTOKEN_SETUP 0x00000000\n#define AVR32_USBB_UPCFG1_PTOKEN_SIZE 2\n#define AVR32_USBB_UPCFG1_PTYPE 12\n#define AVR32_USBB_UPCFG1_PTYPE_BULK 0x00000002\n#define AVR32_USBB_UPCFG1_PTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UPCFG1_PTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UPCFG1_PTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UPCFG1_PTYPE_MASK 0x00003000\n#define AVR32_USBB_UPCFG1_PTYPE_OFFSET 12\n#define AVR32_USBB_UPCFG1_PTYPE_SIZE 2\n#define AVR32_USBB_UPCFG2 0x00000508\n#define AVR32_USBB_UPCFG2_ALLOC 1\n#define AVR32_USBB_UPCFG2_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UPCFG2_ALLOC_OFFSET 1\n#define AVR32_USBB_UPCFG2_ALLOC_SIZE 1\n#define AVR32_USBB_UPCFG2_AUTOSW 10\n#define AVR32_USBB_UPCFG2_AUTOSW_MASK 0x00000400\n#define AVR32_USBB_UPCFG2_AUTOSW_OFFSET 10\n#define AVR32_USBB_UPCFG2_AUTOSW_SIZE 1\n#define AVR32_USBB_UPCFG2_DATASIZERDWR 22\n#define AVR32_USBB_UPCFG2_DATASIZERDWR_MASK 0x00c00000\n#define AVR32_USBB_UPCFG2_DATASIZERDWR_OFFSET 22\n#define AVR32_USBB_UPCFG2_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UPCFG2_INTFRQ 24\n#define AVR32_USBB_UPCFG2_INTFRQ_MASK 0xff000000\n#define AVR32_USBB_UPCFG2_INTFRQ_OFFSET 24\n#define AVR32_USBB_UPCFG2_INTFRQ_SIZE 8\n#define AVR32_USBB_UPCFG2_PBK 2\n#define AVR32_USBB_UPCFG2_PBK_DOUBLE 0x00000001\n#define AVR32_USBB_UPCFG2_PBK_MASK 0x0000000c\n#define AVR32_USBB_UPCFG2_PBK_OFFSET 2\n#define AVR32_USBB_UPCFG2_PBK_SINGLE 0x00000000\n#define AVR32_USBB_UPCFG2_PBK_SIZE 2\n#define AVR32_USBB_UPCFG2_PBK_TRIPLE 0x00000002\n#define AVR32_USBB_UPCFG2_PEPNUM 16\n#define AVR32_USBB_UPCFG2_PEPNUM_MASK 0x000f0000\n#define AVR32_USBB_UPCFG2_PEPNUM_OFFSET 16\n#define AVR32_USBB_UPCFG2_PEPNUM_SIZE 4\n#define AVR32_USBB_UPCFG2_PINGEN 20\n#define AVR32_USBB_UPCFG2_PINGEN_MASK 0x00100000\n#define AVR32_USBB_UPCFG2_PINGEN_OFFSET 20\n#define AVR32_USBB_UPCFG2_PINGEN_SIZE 1\n#define AVR32_USBB_UPCFG2_PSIZE 4\n#define AVR32_USBB_UPCFG2_PSIZE_1024 0x00000007\n#define AVR32_USBB_UPCFG2_PSIZE_128 0x00000004\n#define AVR32_USBB_UPCFG2_PSIZE_16 0x00000001\n#define AVR32_USBB_UPCFG2_PSIZE_256 0x00000005\n#define AVR32_USBB_UPCFG2_PSIZE_32 0x00000002\n#define AVR32_USBB_UPCFG2_PSIZE_512 0x00000006\n#define AVR32_USBB_UPCFG2_PSIZE_64 0x00000003\n#define AVR32_USBB_UPCFG2_PSIZE_8 0x00000000\n#define AVR32_USBB_UPCFG2_PSIZE_MASK 0x00000070\n#define AVR32_USBB_UPCFG2_PSIZE_OFFSET 4\n#define AVR32_USBB_UPCFG2_PSIZE_SIZE 3\n#define AVR32_USBB_UPCFG2_PTOKEN 8\n#define AVR32_USBB_UPCFG2_PTOKEN_IN 0x00000001\n#define AVR32_USBB_UPCFG2_PTOKEN_MASK 0x00000300\n#define AVR32_USBB_UPCFG2_PTOKEN_OFFSET 8\n#define AVR32_USBB_UPCFG2_PTOKEN_OUT 0x00000002\n#define AVR32_USBB_UPCFG2_PTOKEN_SETUP 0x00000000\n#define AVR32_USBB_UPCFG2_PTOKEN_SIZE 2\n#define AVR32_USBB_UPCFG2_PTYPE 12\n#define AVR32_USBB_UPCFG2_PTYPE_BULK 0x00000002\n#define AVR32_USBB_UPCFG2_PTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UPCFG2_PTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UPCFG2_PTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UPCFG2_PTYPE_MASK 0x00003000\n#define AVR32_USBB_UPCFG2_PTYPE_OFFSET 12\n#define AVR32_USBB_UPCFG2_PTYPE_SIZE 2\n#define AVR32_USBB_UPCFG3 0x0000050c\n#define AVR32_USBB_UPCFG3_ALLOC 1\n#define AVR32_USBB_UPCFG3_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UPCFG3_ALLOC_OFFSET 1\n#define AVR32_USBB_UPCFG3_ALLOC_SIZE 1\n#define AVR32_USBB_UPCFG3_AUTOSW 10\n#define AVR32_USBB_UPCFG3_AUTOSW_MASK 0x00000400\n#define AVR32_USBB_UPCFG3_AUTOSW_OFFSET 10\n#define AVR32_USBB_UPCFG3_AUTOSW_SIZE 1\n#define AVR32_USBB_UPCFG3_DATASIZERDWR 22\n#define AVR32_USBB_UPCFG3_DATASIZERDWR_MASK 0x00c00000\n#define AVR32_USBB_UPCFG3_DATASIZERDWR_OFFSET 22\n#define AVR32_USBB_UPCFG3_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UPCFG3_INTFRQ 24\n#define AVR32_USBB_UPCFG3_INTFRQ_MASK 0xff000000\n#define AVR32_USBB_UPCFG3_INTFRQ_OFFSET 24\n#define AVR32_USBB_UPCFG3_INTFRQ_SIZE 8\n#define AVR32_USBB_UPCFG3_PBK 2\n#define AVR32_USBB_UPCFG3_PBK_DOUBLE 0x00000001\n#define AVR32_USBB_UPCFG3_PBK_MASK 0x0000000c\n#define AVR32_USBB_UPCFG3_PBK_OFFSET 2\n#define AVR32_USBB_UPCFG3_PBK_SINGLE 0x00000000\n#define AVR32_USBB_UPCFG3_PBK_SIZE 2\n#define AVR32_USBB_UPCFG3_PBK_TRIPLE 0x00000002\n#define AVR32_USBB_UPCFG3_PEPNUM 16\n#define AVR32_USBB_UPCFG3_PEPNUM_MASK 0x000f0000\n#define AVR32_USBB_UPCFG3_PEPNUM_OFFSET 16\n#define AVR32_USBB_UPCFG3_PEPNUM_SIZE 4\n#define AVR32_USBB_UPCFG3_PINGEN 20\n#define AVR32_USBB_UPCFG3_PINGEN_MASK 0x00100000\n#define AVR32_USBB_UPCFG3_PINGEN_OFFSET 20\n#define AVR32_USBB_UPCFG3_PINGEN_SIZE 1\n#define AVR32_USBB_UPCFG3_PSIZE 4\n#define AVR32_USBB_UPCFG3_PSIZE_1024 0x00000007\n#define AVR32_USBB_UPCFG3_PSIZE_128 0x00000004\n#define AVR32_USBB_UPCFG3_PSIZE_16 0x00000001\n#define AVR32_USBB_UPCFG3_PSIZE_256 0x00000005\n#define AVR32_USBB_UPCFG3_PSIZE_32 0x00000002\n#define AVR32_USBB_UPCFG3_PSIZE_512 0x00000006\n#define AVR32_USBB_UPCFG3_PSIZE_64 0x00000003\n#define AVR32_USBB_UPCFG3_PSIZE_8 0x00000000\n#define AVR32_USBB_UPCFG3_PSIZE_MASK 0x00000070\n#define AVR32_USBB_UPCFG3_PSIZE_OFFSET 4\n#define AVR32_USBB_UPCFG3_PSIZE_SIZE 3\n#define AVR32_USBB_UPCFG3_PTOKEN 8\n#define AVR32_USBB_UPCFG3_PTOKEN_IN 0x00000001\n#define AVR32_USBB_UPCFG3_PTOKEN_MASK 0x00000300\n#define AVR32_USBB_UPCFG3_PTOKEN_OFFSET 8\n#define AVR32_USBB_UPCFG3_PTOKEN_OUT 0x00000002\n#define AVR32_USBB_UPCFG3_PTOKEN_SETUP 0x00000000\n#define AVR32_USBB_UPCFG3_PTOKEN_SIZE 2\n#define AVR32_USBB_UPCFG3_PTYPE 12\n#define AVR32_USBB_UPCFG3_PTYPE_BULK 0x00000002\n#define AVR32_USBB_UPCFG3_PTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UPCFG3_PTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UPCFG3_PTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UPCFG3_PTYPE_MASK 0x00003000\n#define AVR32_USBB_UPCFG3_PTYPE_OFFSET 12\n#define AVR32_USBB_UPCFG3_PTYPE_SIZE 2\n#define AVR32_USBB_UPCFG4 0x00000510\n#define AVR32_USBB_UPCFG4_ALLOC 1\n#define AVR32_USBB_UPCFG4_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UPCFG4_ALLOC_OFFSET 1\n#define AVR32_USBB_UPCFG4_ALLOC_SIZE 1\n#define AVR32_USBB_UPCFG4_AUTOSW 10\n#define AVR32_USBB_UPCFG4_AUTOSW_MASK 0x00000400\n#define AVR32_USBB_UPCFG4_AUTOSW_OFFSET 10\n#define AVR32_USBB_UPCFG4_AUTOSW_SIZE 1\n#define AVR32_USBB_UPCFG4_DATASIZERDWR 22\n#define AVR32_USBB_UPCFG4_DATASIZERDWR_MASK 0x00c00000\n#define AVR32_USBB_UPCFG4_DATASIZERDWR_OFFSET 22\n#define AVR32_USBB_UPCFG4_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UPCFG4_INTFRQ 24\n#define AVR32_USBB_UPCFG4_INTFRQ_MASK 0xff000000\n#define AVR32_USBB_UPCFG4_INTFRQ_OFFSET 24\n#define AVR32_USBB_UPCFG4_INTFRQ_SIZE 8\n#define AVR32_USBB_UPCFG4_PBK 2\n#define AVR32_USBB_UPCFG4_PBK_DOUBLE 0x00000001\n#define AVR32_USBB_UPCFG4_PBK_MASK 0x0000000c\n#define AVR32_USBB_UPCFG4_PBK_OFFSET 2\n#define AVR32_USBB_UPCFG4_PBK_SINGLE 0x00000000\n#define AVR32_USBB_UPCFG4_PBK_SIZE 2\n#define AVR32_USBB_UPCFG4_PBK_TRIPLE 0x00000002\n#define AVR32_USBB_UPCFG4_PEPNUM 16\n#define AVR32_USBB_UPCFG4_PEPNUM_MASK 0x000f0000\n#define AVR32_USBB_UPCFG4_PEPNUM_OFFSET 16\n#define AVR32_USBB_UPCFG4_PEPNUM_SIZE 4\n#define AVR32_USBB_UPCFG4_PINGEN 20\n#define AVR32_USBB_UPCFG4_PINGEN_MASK 0x00100000\n#define AVR32_USBB_UPCFG4_PINGEN_OFFSET 20\n#define AVR32_USBB_UPCFG4_PINGEN_SIZE 1\n#define AVR32_USBB_UPCFG4_PSIZE 4\n#define AVR32_USBB_UPCFG4_PSIZE_1024 0x00000007\n#define AVR32_USBB_UPCFG4_PSIZE_128 0x00000004\n#define AVR32_USBB_UPCFG4_PSIZE_16 0x00000001\n#define AVR32_USBB_UPCFG4_PSIZE_256 0x00000005\n#define AVR32_USBB_UPCFG4_PSIZE_32 0x00000002\n#define AVR32_USBB_UPCFG4_PSIZE_512 0x00000006\n#define AVR32_USBB_UPCFG4_PSIZE_64 0x00000003\n#define AVR32_USBB_UPCFG4_PSIZE_8 0x00000000\n#define AVR32_USBB_UPCFG4_PSIZE_MASK 0x00000070\n#define AVR32_USBB_UPCFG4_PSIZE_OFFSET 4\n#define AVR32_USBB_UPCFG4_PSIZE_SIZE 3\n#define AVR32_USBB_UPCFG4_PTOKEN 8\n#define AVR32_USBB_UPCFG4_PTOKEN_IN 0x00000001\n#define AVR32_USBB_UPCFG4_PTOKEN_MASK 0x00000300\n#define AVR32_USBB_UPCFG4_PTOKEN_OFFSET 8\n#define AVR32_USBB_UPCFG4_PTOKEN_OUT 0x00000002\n#define AVR32_USBB_UPCFG4_PTOKEN_SETUP 0x00000000\n#define AVR32_USBB_UPCFG4_PTOKEN_SIZE 2\n#define AVR32_USBB_UPCFG4_PTYPE 12\n#define AVR32_USBB_UPCFG4_PTYPE_BULK 0x00000002\n#define AVR32_USBB_UPCFG4_PTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UPCFG4_PTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UPCFG4_PTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UPCFG4_PTYPE_MASK 0x00003000\n#define AVR32_USBB_UPCFG4_PTYPE_OFFSET 12\n#define AVR32_USBB_UPCFG4_PTYPE_SIZE 2\n#define AVR32_USBB_UPCFG5 0x00000514\n#define AVR32_USBB_UPCFG5_ALLOC 1\n#define AVR32_USBB_UPCFG5_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UPCFG5_ALLOC_OFFSET 1\n#define AVR32_USBB_UPCFG5_ALLOC_SIZE 1\n#define AVR32_USBB_UPCFG5_AUTOSW 10\n#define AVR32_USBB_UPCFG5_AUTOSW_MASK 0x00000400\n#define AVR32_USBB_UPCFG5_AUTOSW_OFFSET 10\n#define AVR32_USBB_UPCFG5_AUTOSW_SIZE 1\n#define AVR32_USBB_UPCFG5_DATASIZERDWR 22\n#define AVR32_USBB_UPCFG5_DATASIZERDWR_MASK 0x00c00000\n#define AVR32_USBB_UPCFG5_DATASIZERDWR_OFFSET 22\n#define AVR32_USBB_UPCFG5_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UPCFG5_INTFRQ 24\n#define AVR32_USBB_UPCFG5_INTFRQ_MASK 0xff000000\n#define AVR32_USBB_UPCFG5_INTFRQ_OFFSET 24\n#define AVR32_USBB_UPCFG5_INTFRQ_SIZE 8\n#define AVR32_USBB_UPCFG5_PBK 2\n#define AVR32_USBB_UPCFG5_PBK_DOUBLE 0x00000001\n#define AVR32_USBB_UPCFG5_PBK_MASK 0x0000000c\n#define AVR32_USBB_UPCFG5_PBK_OFFSET 2\n#define AVR32_USBB_UPCFG5_PBK_SINGLE 0x00000000\n#define AVR32_USBB_UPCFG5_PBK_SIZE 2\n#define AVR32_USBB_UPCFG5_PBK_TRIPLE 0x00000002\n#define AVR32_USBB_UPCFG5_PEPNUM 16\n#define AVR32_USBB_UPCFG5_PEPNUM_MASK 0x000f0000\n#define AVR32_USBB_UPCFG5_PEPNUM_OFFSET 16\n#define AVR32_USBB_UPCFG5_PEPNUM_SIZE 4\n#define AVR32_USBB_UPCFG5_PINGEN 20\n#define AVR32_USBB_UPCFG5_PINGEN_MASK 0x00100000\n#define AVR32_USBB_UPCFG5_PINGEN_OFFSET 20\n#define AVR32_USBB_UPCFG5_PINGEN_SIZE 1\n#define AVR32_USBB_UPCFG5_PSIZE 4\n#define AVR32_USBB_UPCFG5_PSIZE_1024 0x00000007\n#define AVR32_USBB_UPCFG5_PSIZE_128 0x00000004\n#define AVR32_USBB_UPCFG5_PSIZE_16 0x00000001\n#define AVR32_USBB_UPCFG5_PSIZE_256 0x00000005\n#define AVR32_USBB_UPCFG5_PSIZE_32 0x00000002\n#define AVR32_USBB_UPCFG5_PSIZE_512 0x00000006\n#define AVR32_USBB_UPCFG5_PSIZE_64 0x00000003\n#define AVR32_USBB_UPCFG5_PSIZE_8 0x00000000\n#define AVR32_USBB_UPCFG5_PSIZE_MASK 0x00000070\n#define AVR32_USBB_UPCFG5_PSIZE_OFFSET 4\n#define AVR32_USBB_UPCFG5_PSIZE_SIZE 3\n#define AVR32_USBB_UPCFG5_PTOKEN 8\n#define AVR32_USBB_UPCFG5_PTOKEN_IN 0x00000001\n#define AVR32_USBB_UPCFG5_PTOKEN_MASK 0x00000300\n#define AVR32_USBB_UPCFG5_PTOKEN_OFFSET 8\n#define AVR32_USBB_UPCFG5_PTOKEN_OUT 0x00000002\n#define AVR32_USBB_UPCFG5_PTOKEN_SETUP 0x00000000\n#define AVR32_USBB_UPCFG5_PTOKEN_SIZE 2\n#define AVR32_USBB_UPCFG5_PTYPE 12\n#define AVR32_USBB_UPCFG5_PTYPE_BULK 0x00000002\n#define AVR32_USBB_UPCFG5_PTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UPCFG5_PTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UPCFG5_PTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UPCFG5_PTYPE_MASK 0x00003000\n#define AVR32_USBB_UPCFG5_PTYPE_OFFSET 12\n#define AVR32_USBB_UPCFG5_PTYPE_SIZE 2\n#define AVR32_USBB_UPCFG6 0x00000518\n#define AVR32_USBB_UPCFG6_ALLOC 1\n#define AVR32_USBB_UPCFG6_ALLOC_MASK 0x00000002\n#define AVR32_USBB_UPCFG6_ALLOC_OFFSET 1\n#define AVR32_USBB_UPCFG6_ALLOC_SIZE 1\n#define AVR32_USBB_UPCFG6_AUTOSW 10\n#define AVR32_USBB_UPCFG6_AUTOSW_MASK 0x00000400\n#define AVR32_USBB_UPCFG6_AUTOSW_OFFSET 10\n#define AVR32_USBB_UPCFG6_AUTOSW_SIZE 1\n#define AVR32_USBB_UPCFG6_DATASIZERDWR 22\n#define AVR32_USBB_UPCFG6_DATASIZERDWR_MASK 0x00c00000\n#define AVR32_USBB_UPCFG6_DATASIZERDWR_OFFSET 22\n#define AVR32_USBB_UPCFG6_DATASIZERDWR_SIZE 2\n#define AVR32_USBB_UPCFG6_INTFRQ 24\n#define AVR32_USBB_UPCFG6_INTFRQ_MASK 0xff000000\n#define AVR32_USBB_UPCFG6_INTFRQ_OFFSET 24\n#define AVR32_USBB_UPCFG6_INTFRQ_SIZE 8\n#define AVR32_USBB_UPCFG6_PBK 2\n#define AVR32_USBB_UPCFG6_PBK_DOUBLE 0x00000001\n#define AVR32_USBB_UPCFG6_PBK_MASK 0x0000000c\n#define AVR32_USBB_UPCFG6_PBK_OFFSET 2\n#define AVR32_USBB_UPCFG6_PBK_SINGLE 0x00000000\n#define AVR32_USBB_UPCFG6_PBK_SIZE 2\n#define AVR32_USBB_UPCFG6_PBK_TRIPLE 0x00000002\n#define AVR32_USBB_UPCFG6_PEPNUM 16\n#define AVR32_USBB_UPCFG6_PEPNUM_MASK 0x000f0000\n#define AVR32_USBB_UPCFG6_PEPNUM_OFFSET 16\n#define AVR32_USBB_UPCFG6_PEPNUM_SIZE 4\n#define AVR32_USBB_UPCFG6_PINGEN 20\n#define AVR32_USBB_UPCFG6_PINGEN_MASK 0x00100000\n#define AVR32_USBB_UPCFG6_PINGEN_OFFSET 20\n#define AVR32_USBB_UPCFG6_PINGEN_SIZE 1\n#define AVR32_USBB_UPCFG6_PSIZE 4\n#define AVR32_USBB_UPCFG6_PSIZE_1024 0x00000007\n#define AVR32_USBB_UPCFG6_PSIZE_128 0x00000004\n#define AVR32_USBB_UPCFG6_PSIZE_16 0x00000001\n#define AVR32_USBB_UPCFG6_PSIZE_256 0x00000005\n#define AVR32_USBB_UPCFG6_PSIZE_32 0x00000002\n#define AVR32_USBB_UPCFG6_PSIZE_512 0x00000006\n#define AVR32_USBB_UPCFG6_PSIZE_64 0x00000003\n#define AVR32_USBB_UPCFG6_PSIZE_8 0x00000000\n#define AVR32_USBB_UPCFG6_PSIZE_MASK 0x00000070\n#define AVR32_USBB_UPCFG6_PSIZE_OFFSET 4\n#define AVR32_USBB_UPCFG6_PSIZE_SIZE 3\n#define AVR32_USBB_UPCFG6_PTOKEN 8\n#define AVR32_USBB_UPCFG6_PTOKEN_IN 0x00000001\n#define AVR32_USBB_UPCFG6_PTOKEN_MASK 0x00000300\n#define AVR32_USBB_UPCFG6_PTOKEN_OFFSET 8\n#define AVR32_USBB_UPCFG6_PTOKEN_OUT 0x00000002\n#define AVR32_USBB_UPCFG6_PTOKEN_SETUP 0x00000000\n#define AVR32_USBB_UPCFG6_PTOKEN_SIZE 2\n#define AVR32_USBB_UPCFG6_PTYPE 12\n#define AVR32_USBB_UPCFG6_PTYPE_BULK 0x00000002\n#define AVR32_USBB_UPCFG6_PTYPE_CONTROL 0x00000000\n#define AVR32_USBB_UPCFG6_PTYPE_INTERRUPT 0x00000003\n#define AVR32_USBB_UPCFG6_PTYPE_ISOCHRONOUS 0x00000001\n#define AVR32_USBB_UPCFG6_PTYPE_MASK 0x00003000\n#define AVR32_USBB_UPCFG6_PTYPE_OFFSET 12\n#define AVR32_USBB_UPCFG6_PTYPE_SIZE 2\n#define AVR32_USBB_UPCON0 0x000005c0\n#define AVR32_USBB_UPCON0CLR 0x00000620\n#define AVR32_USBB_UPCON0CLR_FIFOCONC 14\n#define AVR32_USBB_UPCON0CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UPCON0CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UPCON0CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UPCON0CLR_NAKEDEC 4\n#define AVR32_USBB_UPCON0CLR_NAKEDEC_MASK 0x00000010\n#define AVR32_USBB_UPCON0CLR_NAKEDEC_OFFSET 4\n#define AVR32_USBB_UPCON0CLR_NAKEDEC_SIZE 1\n#define AVR32_USBB_UPCON0CLR_NBUSYBKEC 12\n#define AVR32_USBB_UPCON0CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UPCON0CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UPCON0CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UPCON0CLR_OVERFIEC 5\n#define AVR32_USBB_UPCON0CLR_OVERFIEC_MASK 0x00000020\n#define AVR32_USBB_UPCON0CLR_OVERFIEC_OFFSET 5\n#define AVR32_USBB_UPCON0CLR_OVERFIEC_SIZE 1\n#define AVR32_USBB_UPCON0CLR_PDISHDMAC 16\n#define AVR32_USBB_UPCON0CLR_PDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UPCON0CLR_PDISHDMAC_OFFSET 16\n#define AVR32_USBB_UPCON0CLR_PDISHDMAC_SIZE 1\n#define AVR32_USBB_UPCON0CLR_PERREC 3\n#define AVR32_USBB_UPCON0CLR_PERREC_MASK 0x00000008\n#define AVR32_USBB_UPCON0CLR_PERREC_OFFSET 3\n#define AVR32_USBB_UPCON0CLR_PERREC_SIZE 1\n#define AVR32_USBB_UPCON0CLR_PFREEZEC 17\n#define AVR32_USBB_UPCON0CLR_PFREEZEC_MASK 0x00020000\n#define AVR32_USBB_UPCON0CLR_PFREEZEC_OFFSET 17\n#define AVR32_USBB_UPCON0CLR_PFREEZEC_SIZE 1\n#define AVR32_USBB_UPCON0CLR_RXINEC 0\n#define AVR32_USBB_UPCON0CLR_RXINEC_MASK 0x00000001\n#define AVR32_USBB_UPCON0CLR_RXINEC_OFFSET 0\n#define AVR32_USBB_UPCON0CLR_RXINEC_SIZE 1\n#define AVR32_USBB_UPCON0CLR_RXSTALLDEC 6\n#define AVR32_USBB_UPCON0CLR_RXSTALLDEC_MASK 0x00000040\n#define AVR32_USBB_UPCON0CLR_RXSTALLDEC_OFFSET 6\n#define AVR32_USBB_UPCON0CLR_RXSTALLDEC_SIZE 1\n#define AVR32_USBB_UPCON0CLR_SHORTPACKETIEC 7\n#define AVR32_USBB_UPCON0CLR_SHORTPACKETIEC_MASK 0x00000080\n#define AVR32_USBB_UPCON0CLR_SHORTPACKETIEC_OFFSET 7\n#define AVR32_USBB_UPCON0CLR_SHORTPACKETIEC_SIZE 1\n#define AVR32_USBB_UPCON0CLR_TXOUTEC 1\n#define AVR32_USBB_UPCON0CLR_TXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UPCON0CLR_TXOUTEC_OFFSET 1\n#define AVR32_USBB_UPCON0CLR_TXOUTEC_SIZE 1\n#define AVR32_USBB_UPCON0CLR_TXSTPEC 2\n#define AVR32_USBB_UPCON0CLR_TXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UPCON0CLR_TXSTPEC_OFFSET 2\n#define AVR32_USBB_UPCON0CLR_TXSTPEC_SIZE 1\n#define AVR32_USBB_UPCON0SET 0x000005f0\n#define AVR32_USBB_UPCON0SET_NAKEDES 4\n#define AVR32_USBB_UPCON0SET_NAKEDES_MASK 0x00000010\n#define AVR32_USBB_UPCON0SET_NAKEDES_OFFSET 4\n#define AVR32_USBB_UPCON0SET_NAKEDES_SIZE 1\n#define AVR32_USBB_UPCON0SET_NBUSYBKES 12\n#define AVR32_USBB_UPCON0SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UPCON0SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UPCON0SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UPCON0SET_OVERFIES 5\n#define AVR32_USBB_UPCON0SET_OVERFIES_MASK 0x00000020\n#define AVR32_USBB_UPCON0SET_OVERFIES_OFFSET 5\n#define AVR32_USBB_UPCON0SET_OVERFIES_SIZE 1\n#define AVR32_USBB_UPCON0SET_PDISHDMAS 16\n#define AVR32_USBB_UPCON0SET_PDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UPCON0SET_PDISHDMAS_OFFSET 16\n#define AVR32_USBB_UPCON0SET_PDISHDMAS_SIZE 1\n#define AVR32_USBB_UPCON0SET_PERRES 3\n#define AVR32_USBB_UPCON0SET_PERRES_MASK 0x00000008\n#define AVR32_USBB_UPCON0SET_PERRES_OFFSET 3\n#define AVR32_USBB_UPCON0SET_PERRES_SIZE 1\n#define AVR32_USBB_UPCON0SET_PFREEZES 17\n#define AVR32_USBB_UPCON0SET_PFREEZES_MASK 0x00020000\n#define AVR32_USBB_UPCON0SET_PFREEZES_OFFSET 17\n#define AVR32_USBB_UPCON0SET_PFREEZES_SIZE 1\n#define AVR32_USBB_UPCON0SET_RSTDTS 18\n#define AVR32_USBB_UPCON0SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UPCON0SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UPCON0SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UPCON0SET_RXINES 0\n#define AVR32_USBB_UPCON0SET_RXINES_MASK 0x00000001\n#define AVR32_USBB_UPCON0SET_RXINES_OFFSET 0\n#define AVR32_USBB_UPCON0SET_RXINES_SIZE 1\n#define AVR32_USBB_UPCON0SET_RXSTALLDES 6\n#define AVR32_USBB_UPCON0SET_RXSTALLDES_MASK 0x00000040\n#define AVR32_USBB_UPCON0SET_RXSTALLDES_OFFSET 6\n#define AVR32_USBB_UPCON0SET_RXSTALLDES_SIZE 1\n#define AVR32_USBB_UPCON0SET_SHORTPACKETIES 7\n#define AVR32_USBB_UPCON0SET_SHORTPACKETIES_MASK 0x00000080\n#define AVR32_USBB_UPCON0SET_SHORTPACKETIES_OFFSET 7\n#define AVR32_USBB_UPCON0SET_SHORTPACKETIES_SIZE 1\n#define AVR32_USBB_UPCON0SET_TXOUTES 1\n#define AVR32_USBB_UPCON0SET_TXOUTES_MASK 0x00000002\n#define AVR32_USBB_UPCON0SET_TXOUTES_OFFSET 1\n#define AVR32_USBB_UPCON0SET_TXOUTES_SIZE 1\n#define AVR32_USBB_UPCON0SET_TXSTPES 2\n#define AVR32_USBB_UPCON0SET_TXSTPES_MASK 0x00000004\n#define AVR32_USBB_UPCON0SET_TXSTPES_OFFSET 2\n#define AVR32_USBB_UPCON0SET_TXSTPES_SIZE 1\n#define AVR32_USBB_UPCON0_FIFOCON 14\n#define AVR32_USBB_UPCON0_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UPCON0_FIFOCON_OFFSET 14\n#define AVR32_USBB_UPCON0_FIFOCON_SIZE 1\n#define AVR32_USBB_UPCON0_NAKEDE 4\n#define AVR32_USBB_UPCON0_NAKEDE_MASK 0x00000010\n#define AVR32_USBB_UPCON0_NAKEDE_OFFSET 4\n#define AVR32_USBB_UPCON0_NAKEDE_SIZE 1\n#define AVR32_USBB_UPCON0_NBUSYBKE 12\n#define AVR32_USBB_UPCON0_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UPCON0_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UPCON0_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UPCON0_OVERFIE 5\n#define AVR32_USBB_UPCON0_OVERFIE_MASK 0x00000020\n#define AVR32_USBB_UPCON0_OVERFIE_OFFSET 5\n#define AVR32_USBB_UPCON0_OVERFIE_SIZE 1\n#define AVR32_USBB_UPCON0_PDISHDMA 16\n#define AVR32_USBB_UPCON0_PDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UPCON0_PDISHDMA_OFFSET 16\n#define AVR32_USBB_UPCON0_PDISHDMA_SIZE 1\n#define AVR32_USBB_UPCON0_PERRE 3\n#define AVR32_USBB_UPCON0_PERRE_MASK 0x00000008\n#define AVR32_USBB_UPCON0_PERRE_OFFSET 3\n#define AVR32_USBB_UPCON0_PERRE_SIZE 1\n#define AVR32_USBB_UPCON0_PFREEZE 17\n#define AVR32_USBB_UPCON0_PFREEZE_MASK 0x00020000\n#define AVR32_USBB_UPCON0_PFREEZE_OFFSET 17\n#define AVR32_USBB_UPCON0_PFREEZE_SIZE 1\n#define AVR32_USBB_UPCON0_RSTDT 18\n#define AVR32_USBB_UPCON0_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UPCON0_RSTDT_OFFSET 18\n#define AVR32_USBB_UPCON0_RSTDT_SIZE 1\n#define AVR32_USBB_UPCON0_RXINE 0\n#define AVR32_USBB_UPCON0_RXINE_MASK 0x00000001\n#define AVR32_USBB_UPCON0_RXINE_OFFSET 0\n#define AVR32_USBB_UPCON0_RXINE_SIZE 1\n#define AVR32_USBB_UPCON0_RXSTALLDE 6\n#define AVR32_USBB_UPCON0_RXSTALLDE_MASK 0x00000040\n#define AVR32_USBB_UPCON0_RXSTALLDE_OFFSET 6\n#define AVR32_USBB_UPCON0_RXSTALLDE_SIZE 1\n#define AVR32_USBB_UPCON0_SHORTPACKETIE 7\n#define AVR32_USBB_UPCON0_SHORTPACKETIE_MASK 0x00000080\n#define AVR32_USBB_UPCON0_SHORTPACKETIE_OFFSET 7\n#define AVR32_USBB_UPCON0_SHORTPACKETIE_SIZE 1\n#define AVR32_USBB_UPCON0_TXOUTE 1\n#define AVR32_USBB_UPCON0_TXOUTE_MASK 0x00000002\n#define AVR32_USBB_UPCON0_TXOUTE_OFFSET 1\n#define AVR32_USBB_UPCON0_TXOUTE_SIZE 1\n#define AVR32_USBB_UPCON0_TXSTPE 2\n#define AVR32_USBB_UPCON0_TXSTPE_MASK 0x00000004\n#define AVR32_USBB_UPCON0_TXSTPE_OFFSET 2\n#define AVR32_USBB_UPCON0_TXSTPE_SIZE 1\n#define AVR32_USBB_UPCON1 0x000005c4\n#define AVR32_USBB_UPCON1CLR 0x00000624\n#define AVR32_USBB_UPCON1CLR_FIFOCONC 14\n#define AVR32_USBB_UPCON1CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UPCON1CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UPCON1CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UPCON1CLR_NAKEDEC 4\n#define AVR32_USBB_UPCON1CLR_NAKEDEC_MASK 0x00000010\n#define AVR32_USBB_UPCON1CLR_NAKEDEC_OFFSET 4\n#define AVR32_USBB_UPCON1CLR_NAKEDEC_SIZE 1\n#define AVR32_USBB_UPCON1CLR_NBUSYBKEC 12\n#define AVR32_USBB_UPCON1CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UPCON1CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UPCON1CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UPCON1CLR_OVERFIEC 5\n#define AVR32_USBB_UPCON1CLR_OVERFIEC_MASK 0x00000020\n#define AVR32_USBB_UPCON1CLR_OVERFIEC_OFFSET 5\n#define AVR32_USBB_UPCON1CLR_OVERFIEC_SIZE 1\n#define AVR32_USBB_UPCON1CLR_PDISHDMAC 16\n#define AVR32_USBB_UPCON1CLR_PDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UPCON1CLR_PDISHDMAC_OFFSET 16\n#define AVR32_USBB_UPCON1CLR_PDISHDMAC_SIZE 1\n#define AVR32_USBB_UPCON1CLR_PERREC 3\n#define AVR32_USBB_UPCON1CLR_PERREC_MASK 0x00000008\n#define AVR32_USBB_UPCON1CLR_PERREC_OFFSET 3\n#define AVR32_USBB_UPCON1CLR_PERREC_SIZE 1\n#define AVR32_USBB_UPCON1CLR_PFREEZEC 17\n#define AVR32_USBB_UPCON1CLR_PFREEZEC_MASK 0x00020000\n#define AVR32_USBB_UPCON1CLR_PFREEZEC_OFFSET 17\n#define AVR32_USBB_UPCON1CLR_PFREEZEC_SIZE 1\n#define AVR32_USBB_UPCON1CLR_RXINEC 0\n#define AVR32_USBB_UPCON1CLR_RXINEC_MASK 0x00000001\n#define AVR32_USBB_UPCON1CLR_RXINEC_OFFSET 0\n#define AVR32_USBB_UPCON1CLR_RXINEC_SIZE 1\n#define AVR32_USBB_UPCON1CLR_RXSTALLDEC 6\n#define AVR32_USBB_UPCON1CLR_RXSTALLDEC_MASK 0x00000040\n#define AVR32_USBB_UPCON1CLR_RXSTALLDEC_OFFSET 6\n#define AVR32_USBB_UPCON1CLR_RXSTALLDEC_SIZE 1\n#define AVR32_USBB_UPCON1CLR_SHORTPACKETIEC 7\n#define AVR32_USBB_UPCON1CLR_SHORTPACKETIEC_MASK 0x00000080\n#define AVR32_USBB_UPCON1CLR_SHORTPACKETIEC_OFFSET 7\n#define AVR32_USBB_UPCON1CLR_SHORTPACKETIEC_SIZE 1\n#define AVR32_USBB_UPCON1CLR_TXOUTEC 1\n#define AVR32_USBB_UPCON1CLR_TXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UPCON1CLR_TXOUTEC_OFFSET 1\n#define AVR32_USBB_UPCON1CLR_TXOUTEC_SIZE 1\n#define AVR32_USBB_UPCON1CLR_TXSTPEC 2\n#define AVR32_USBB_UPCON1CLR_TXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UPCON1CLR_TXSTPEC_OFFSET 2\n#define AVR32_USBB_UPCON1CLR_TXSTPEC_SIZE 1\n#define AVR32_USBB_UPCON1SET 0x000005f4\n#define AVR32_USBB_UPCON1SET_NAKEDES 4\n#define AVR32_USBB_UPCON1SET_NAKEDES_MASK 0x00000010\n#define AVR32_USBB_UPCON1SET_NAKEDES_OFFSET 4\n#define AVR32_USBB_UPCON1SET_NAKEDES_SIZE 1\n#define AVR32_USBB_UPCON1SET_NBUSYBKES 12\n#define AVR32_USBB_UPCON1SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UPCON1SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UPCON1SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UPCON1SET_OVERFIES 5\n#define AVR32_USBB_UPCON1SET_OVERFIES_MASK 0x00000020\n#define AVR32_USBB_UPCON1SET_OVERFIES_OFFSET 5\n#define AVR32_USBB_UPCON1SET_OVERFIES_SIZE 1\n#define AVR32_USBB_UPCON1SET_PDISHDMAS 16\n#define AVR32_USBB_UPCON1SET_PDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UPCON1SET_PDISHDMAS_OFFSET 16\n#define AVR32_USBB_UPCON1SET_PDISHDMAS_SIZE 1\n#define AVR32_USBB_UPCON1SET_PERRES 3\n#define AVR32_USBB_UPCON1SET_PERRES_MASK 0x00000008\n#define AVR32_USBB_UPCON1SET_PERRES_OFFSET 3\n#define AVR32_USBB_UPCON1SET_PERRES_SIZE 1\n#define AVR32_USBB_UPCON1SET_PFREEZES 17\n#define AVR32_USBB_UPCON1SET_PFREEZES_MASK 0x00020000\n#define AVR32_USBB_UPCON1SET_PFREEZES_OFFSET 17\n#define AVR32_USBB_UPCON1SET_PFREEZES_SIZE 1\n#define AVR32_USBB_UPCON1SET_RSTDTS 18\n#define AVR32_USBB_UPCON1SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UPCON1SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UPCON1SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UPCON1SET_RXINES 0\n#define AVR32_USBB_UPCON1SET_RXINES_MASK 0x00000001\n#define AVR32_USBB_UPCON1SET_RXINES_OFFSET 0\n#define AVR32_USBB_UPCON1SET_RXINES_SIZE 1\n#define AVR32_USBB_UPCON1SET_RXSTALLDES 6\n#define AVR32_USBB_UPCON1SET_RXSTALLDES_MASK 0x00000040\n#define AVR32_USBB_UPCON1SET_RXSTALLDES_OFFSET 6\n#define AVR32_USBB_UPCON1SET_RXSTALLDES_SIZE 1\n#define AVR32_USBB_UPCON1SET_SHORTPACKETIES 7\n#define AVR32_USBB_UPCON1SET_SHORTPACKETIES_MASK 0x00000080\n#define AVR32_USBB_UPCON1SET_SHORTPACKETIES_OFFSET 7\n#define AVR32_USBB_UPCON1SET_SHORTPACKETIES_SIZE 1\n#define AVR32_USBB_UPCON1SET_TXOUTES 1\n#define AVR32_USBB_UPCON1SET_TXOUTES_MASK 0x00000002\n#define AVR32_USBB_UPCON1SET_TXOUTES_OFFSET 1\n#define AVR32_USBB_UPCON1SET_TXOUTES_SIZE 1\n#define AVR32_USBB_UPCON1SET_TXSTPES 2\n#define AVR32_USBB_UPCON1SET_TXSTPES_MASK 0x00000004\n#define AVR32_USBB_UPCON1SET_TXSTPES_OFFSET 2\n#define AVR32_USBB_UPCON1SET_TXSTPES_SIZE 1\n#define AVR32_USBB_UPCON1_FIFOCON 14\n#define AVR32_USBB_UPCON1_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UPCON1_FIFOCON_OFFSET 14\n#define AVR32_USBB_UPCON1_FIFOCON_SIZE 1\n#define AVR32_USBB_UPCON1_NAKEDE 4\n#define AVR32_USBB_UPCON1_NAKEDE_MASK 0x00000010\n#define AVR32_USBB_UPCON1_NAKEDE_OFFSET 4\n#define AVR32_USBB_UPCON1_NAKEDE_SIZE 1\n#define AVR32_USBB_UPCON1_NBUSYBKE 12\n#define AVR32_USBB_UPCON1_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UPCON1_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UPCON1_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UPCON1_OVERFIE 5\n#define AVR32_USBB_UPCON1_OVERFIE_MASK 0x00000020\n#define AVR32_USBB_UPCON1_OVERFIE_OFFSET 5\n#define AVR32_USBB_UPCON1_OVERFIE_SIZE 1\n#define AVR32_USBB_UPCON1_PDISHDMA 16\n#define AVR32_USBB_UPCON1_PDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UPCON1_PDISHDMA_OFFSET 16\n#define AVR32_USBB_UPCON1_PDISHDMA_SIZE 1\n#define AVR32_USBB_UPCON1_PERRE 3\n#define AVR32_USBB_UPCON1_PERRE_MASK 0x00000008\n#define AVR32_USBB_UPCON1_PERRE_OFFSET 3\n#define AVR32_USBB_UPCON1_PERRE_SIZE 1\n#define AVR32_USBB_UPCON1_PFREEZE 17\n#define AVR32_USBB_UPCON1_PFREEZE_MASK 0x00020000\n#define AVR32_USBB_UPCON1_PFREEZE_OFFSET 17\n#define AVR32_USBB_UPCON1_PFREEZE_SIZE 1\n#define AVR32_USBB_UPCON1_RSTDT 18\n#define AVR32_USBB_UPCON1_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UPCON1_RSTDT_OFFSET 18\n#define AVR32_USBB_UPCON1_RSTDT_SIZE 1\n#define AVR32_USBB_UPCON1_RXINE 0\n#define AVR32_USBB_UPCON1_RXINE_MASK 0x00000001\n#define AVR32_USBB_UPCON1_RXINE_OFFSET 0\n#define AVR32_USBB_UPCON1_RXINE_SIZE 1\n#define AVR32_USBB_UPCON1_RXSTALLDE 6\n#define AVR32_USBB_UPCON1_RXSTALLDE_MASK 0x00000040\n#define AVR32_USBB_UPCON1_RXSTALLDE_OFFSET 6\n#define AVR32_USBB_UPCON1_RXSTALLDE_SIZE 1\n#define AVR32_USBB_UPCON1_SHORTPACKETIE 7\n#define AVR32_USBB_UPCON1_SHORTPACKETIE_MASK 0x00000080\n#define AVR32_USBB_UPCON1_SHORTPACKETIE_OFFSET 7\n#define AVR32_USBB_UPCON1_SHORTPACKETIE_SIZE 1\n#define AVR32_USBB_UPCON1_TXOUTE 1\n#define AVR32_USBB_UPCON1_TXOUTE_MASK 0x00000002\n#define AVR32_USBB_UPCON1_TXOUTE_OFFSET 1\n#define AVR32_USBB_UPCON1_TXOUTE_SIZE 1\n#define AVR32_USBB_UPCON1_TXSTPE 2\n#define AVR32_USBB_UPCON1_TXSTPE_MASK 0x00000004\n#define AVR32_USBB_UPCON1_TXSTPE_OFFSET 2\n#define AVR32_USBB_UPCON1_TXSTPE_SIZE 1\n#define AVR32_USBB_UPCON2 0x000005c8\n#define AVR32_USBB_UPCON2CLR 0x00000628\n#define AVR32_USBB_UPCON2CLR_FIFOCONC 14\n#define AVR32_USBB_UPCON2CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UPCON2CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UPCON2CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UPCON2CLR_NAKEDEC 4\n#define AVR32_USBB_UPCON2CLR_NAKEDEC_MASK 0x00000010\n#define AVR32_USBB_UPCON2CLR_NAKEDEC_OFFSET 4\n#define AVR32_USBB_UPCON2CLR_NAKEDEC_SIZE 1\n#define AVR32_USBB_UPCON2CLR_NBUSYBKEC 12\n#define AVR32_USBB_UPCON2CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UPCON2CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UPCON2CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UPCON2CLR_OVERFIEC 5\n#define AVR32_USBB_UPCON2CLR_OVERFIEC_MASK 0x00000020\n#define AVR32_USBB_UPCON2CLR_OVERFIEC_OFFSET 5\n#define AVR32_USBB_UPCON2CLR_OVERFIEC_SIZE 1\n#define AVR32_USBB_UPCON2CLR_PDISHDMAC 16\n#define AVR32_USBB_UPCON2CLR_PDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UPCON2CLR_PDISHDMAC_OFFSET 16\n#define AVR32_USBB_UPCON2CLR_PDISHDMAC_SIZE 1\n#define AVR32_USBB_UPCON2CLR_PERREC 3\n#define AVR32_USBB_UPCON2CLR_PERREC_MASK 0x00000008\n#define AVR32_USBB_UPCON2CLR_PERREC_OFFSET 3\n#define AVR32_USBB_UPCON2CLR_PERREC_SIZE 1\n#define AVR32_USBB_UPCON2CLR_PFREEZEC 17\n#define AVR32_USBB_UPCON2CLR_PFREEZEC_MASK 0x00020000\n#define AVR32_USBB_UPCON2CLR_PFREEZEC_OFFSET 17\n#define AVR32_USBB_UPCON2CLR_PFREEZEC_SIZE 1\n#define AVR32_USBB_UPCON2CLR_RXINEC 0\n#define AVR32_USBB_UPCON2CLR_RXINEC_MASK 0x00000001\n#define AVR32_USBB_UPCON2CLR_RXINEC_OFFSET 0\n#define AVR32_USBB_UPCON2CLR_RXINEC_SIZE 1\n#define AVR32_USBB_UPCON2CLR_RXSTALLDEC 6\n#define AVR32_USBB_UPCON2CLR_RXSTALLDEC_MASK 0x00000040\n#define AVR32_USBB_UPCON2CLR_RXSTALLDEC_OFFSET 6\n#define AVR32_USBB_UPCON2CLR_RXSTALLDEC_SIZE 1\n#define AVR32_USBB_UPCON2CLR_SHORTPACKETIEC 7\n#define AVR32_USBB_UPCON2CLR_SHORTPACKETIEC_MASK 0x00000080\n#define AVR32_USBB_UPCON2CLR_SHORTPACKETIEC_OFFSET 7\n#define AVR32_USBB_UPCON2CLR_SHORTPACKETIEC_SIZE 1\n#define AVR32_USBB_UPCON2CLR_TXOUTEC 1\n#define AVR32_USBB_UPCON2CLR_TXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UPCON2CLR_TXOUTEC_OFFSET 1\n#define AVR32_USBB_UPCON2CLR_TXOUTEC_SIZE 1\n#define AVR32_USBB_UPCON2CLR_TXSTPEC 2\n#define AVR32_USBB_UPCON2CLR_TXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UPCON2CLR_TXSTPEC_OFFSET 2\n#define AVR32_USBB_UPCON2CLR_TXSTPEC_SIZE 1\n#define AVR32_USBB_UPCON2SET 0x000005f8\n#define AVR32_USBB_UPCON2SET_NAKEDES 4\n#define AVR32_USBB_UPCON2SET_NAKEDES_MASK 0x00000010\n#define AVR32_USBB_UPCON2SET_NAKEDES_OFFSET 4\n#define AVR32_USBB_UPCON2SET_NAKEDES_SIZE 1\n#define AVR32_USBB_UPCON2SET_NBUSYBKES 12\n#define AVR32_USBB_UPCON2SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UPCON2SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UPCON2SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UPCON2SET_OVERFIES 5\n#define AVR32_USBB_UPCON2SET_OVERFIES_MASK 0x00000020\n#define AVR32_USBB_UPCON2SET_OVERFIES_OFFSET 5\n#define AVR32_USBB_UPCON2SET_OVERFIES_SIZE 1\n#define AVR32_USBB_UPCON2SET_PDISHDMAS 16\n#define AVR32_USBB_UPCON2SET_PDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UPCON2SET_PDISHDMAS_OFFSET 16\n#define AVR32_USBB_UPCON2SET_PDISHDMAS_SIZE 1\n#define AVR32_USBB_UPCON2SET_PERRES 3\n#define AVR32_USBB_UPCON2SET_PERRES_MASK 0x00000008\n#define AVR32_USBB_UPCON2SET_PERRES_OFFSET 3\n#define AVR32_USBB_UPCON2SET_PERRES_SIZE 1\n#define AVR32_USBB_UPCON2SET_PFREEZES 17\n#define AVR32_USBB_UPCON2SET_PFREEZES_MASK 0x00020000\n#define AVR32_USBB_UPCON2SET_PFREEZES_OFFSET 17\n#define AVR32_USBB_UPCON2SET_PFREEZES_SIZE 1\n#define AVR32_USBB_UPCON2SET_RSTDTS 18\n#define AVR32_USBB_UPCON2SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UPCON2SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UPCON2SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UPCON2SET_RXINES 0\n#define AVR32_USBB_UPCON2SET_RXINES_MASK 0x00000001\n#define AVR32_USBB_UPCON2SET_RXINES_OFFSET 0\n#define AVR32_USBB_UPCON2SET_RXINES_SIZE 1\n#define AVR32_USBB_UPCON2SET_RXSTALLDES 6\n#define AVR32_USBB_UPCON2SET_RXSTALLDES_MASK 0x00000040\n#define AVR32_USBB_UPCON2SET_RXSTALLDES_OFFSET 6\n#define AVR32_USBB_UPCON2SET_RXSTALLDES_SIZE 1\n#define AVR32_USBB_UPCON2SET_SHORTPACKETIES 7\n#define AVR32_USBB_UPCON2SET_SHORTPACKETIES_MASK 0x00000080\n#define AVR32_USBB_UPCON2SET_SHORTPACKETIES_OFFSET 7\n#define AVR32_USBB_UPCON2SET_SHORTPACKETIES_SIZE 1\n#define AVR32_USBB_UPCON2SET_TXOUTES 1\n#define AVR32_USBB_UPCON2SET_TXOUTES_MASK 0x00000002\n#define AVR32_USBB_UPCON2SET_TXOUTES_OFFSET 1\n#define AVR32_USBB_UPCON2SET_TXOUTES_SIZE 1\n#define AVR32_USBB_UPCON2SET_TXSTPES 2\n#define AVR32_USBB_UPCON2SET_TXSTPES_MASK 0x00000004\n#define AVR32_USBB_UPCON2SET_TXSTPES_OFFSET 2\n#define AVR32_USBB_UPCON2SET_TXSTPES_SIZE 1\n#define AVR32_USBB_UPCON2_FIFOCON 14\n#define AVR32_USBB_UPCON2_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UPCON2_FIFOCON_OFFSET 14\n#define AVR32_USBB_UPCON2_FIFOCON_SIZE 1\n#define AVR32_USBB_UPCON2_NAKEDE 4\n#define AVR32_USBB_UPCON2_NAKEDE_MASK 0x00000010\n#define AVR32_USBB_UPCON2_NAKEDE_OFFSET 4\n#define AVR32_USBB_UPCON2_NAKEDE_SIZE 1\n#define AVR32_USBB_UPCON2_NBUSYBKE 12\n#define AVR32_USBB_UPCON2_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UPCON2_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UPCON2_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UPCON2_OVERFIE 5\n#define AVR32_USBB_UPCON2_OVERFIE_MASK 0x00000020\n#define AVR32_USBB_UPCON2_OVERFIE_OFFSET 5\n#define AVR32_USBB_UPCON2_OVERFIE_SIZE 1\n#define AVR32_USBB_UPCON2_PDISHDMA 16\n#define AVR32_USBB_UPCON2_PDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UPCON2_PDISHDMA_OFFSET 16\n#define AVR32_USBB_UPCON2_PDISHDMA_SIZE 1\n#define AVR32_USBB_UPCON2_PERRE 3\n#define AVR32_USBB_UPCON2_PERRE_MASK 0x00000008\n#define AVR32_USBB_UPCON2_PERRE_OFFSET 3\n#define AVR32_USBB_UPCON2_PERRE_SIZE 1\n#define AVR32_USBB_UPCON2_PFREEZE 17\n#define AVR32_USBB_UPCON2_PFREEZE_MASK 0x00020000\n#define AVR32_USBB_UPCON2_PFREEZE_OFFSET 17\n#define AVR32_USBB_UPCON2_PFREEZE_SIZE 1\n#define AVR32_USBB_UPCON2_RSTDT 18\n#define AVR32_USBB_UPCON2_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UPCON2_RSTDT_OFFSET 18\n#define AVR32_USBB_UPCON2_RSTDT_SIZE 1\n#define AVR32_USBB_UPCON2_RXINE 0\n#define AVR32_USBB_UPCON2_RXINE_MASK 0x00000001\n#define AVR32_USBB_UPCON2_RXINE_OFFSET 0\n#define AVR32_USBB_UPCON2_RXINE_SIZE 1\n#define AVR32_USBB_UPCON2_RXSTALLDE 6\n#define AVR32_USBB_UPCON2_RXSTALLDE_MASK 0x00000040\n#define AVR32_USBB_UPCON2_RXSTALLDE_OFFSET 6\n#define AVR32_USBB_UPCON2_RXSTALLDE_SIZE 1\n#define AVR32_USBB_UPCON2_SHORTPACKETIE 7\n#define AVR32_USBB_UPCON2_SHORTPACKETIE_MASK 0x00000080\n#define AVR32_USBB_UPCON2_SHORTPACKETIE_OFFSET 7\n#define AVR32_USBB_UPCON2_SHORTPACKETIE_SIZE 1\n#define AVR32_USBB_UPCON2_TXOUTE 1\n#define AVR32_USBB_UPCON2_TXOUTE_MASK 0x00000002\n#define AVR32_USBB_UPCON2_TXOUTE_OFFSET 1\n#define AVR32_USBB_UPCON2_TXOUTE_SIZE 1\n#define AVR32_USBB_UPCON2_TXSTPE 2\n#define AVR32_USBB_UPCON2_TXSTPE_MASK 0x00000004\n#define AVR32_USBB_UPCON2_TXSTPE_OFFSET 2\n#define AVR32_USBB_UPCON2_TXSTPE_SIZE 1\n#define AVR32_USBB_UPCON3 0x000005cc\n#define AVR32_USBB_UPCON3CLR 0x0000062c\n#define AVR32_USBB_UPCON3CLR_FIFOCONC 14\n#define AVR32_USBB_UPCON3CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UPCON3CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UPCON3CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UPCON3CLR_NAKEDEC 4\n#define AVR32_USBB_UPCON3CLR_NAKEDEC_MASK 0x00000010\n#define AVR32_USBB_UPCON3CLR_NAKEDEC_OFFSET 4\n#define AVR32_USBB_UPCON3CLR_NAKEDEC_SIZE 1\n#define AVR32_USBB_UPCON3CLR_NBUSYBKEC 12\n#define AVR32_USBB_UPCON3CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UPCON3CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UPCON3CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UPCON3CLR_OVERFIEC 5\n#define AVR32_USBB_UPCON3CLR_OVERFIEC_MASK 0x00000020\n#define AVR32_USBB_UPCON3CLR_OVERFIEC_OFFSET 5\n#define AVR32_USBB_UPCON3CLR_OVERFIEC_SIZE 1\n#define AVR32_USBB_UPCON3CLR_PDISHDMAC 16\n#define AVR32_USBB_UPCON3CLR_PDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UPCON3CLR_PDISHDMAC_OFFSET 16\n#define AVR32_USBB_UPCON3CLR_PDISHDMAC_SIZE 1\n#define AVR32_USBB_UPCON3CLR_PERREC 3\n#define AVR32_USBB_UPCON3CLR_PERREC_MASK 0x00000008\n#define AVR32_USBB_UPCON3CLR_PERREC_OFFSET 3\n#define AVR32_USBB_UPCON3CLR_PERREC_SIZE 1\n#define AVR32_USBB_UPCON3CLR_PFREEZEC 17\n#define AVR32_USBB_UPCON3CLR_PFREEZEC_MASK 0x00020000\n#define AVR32_USBB_UPCON3CLR_PFREEZEC_OFFSET 17\n#define AVR32_USBB_UPCON3CLR_PFREEZEC_SIZE 1\n#define AVR32_USBB_UPCON3CLR_RXINEC 0\n#define AVR32_USBB_UPCON3CLR_RXINEC_MASK 0x00000001\n#define AVR32_USBB_UPCON3CLR_RXINEC_OFFSET 0\n#define AVR32_USBB_UPCON3CLR_RXINEC_SIZE 1\n#define AVR32_USBB_UPCON3CLR_RXSTALLDEC 6\n#define AVR32_USBB_UPCON3CLR_RXSTALLDEC_MASK 0x00000040\n#define AVR32_USBB_UPCON3CLR_RXSTALLDEC_OFFSET 6\n#define AVR32_USBB_UPCON3CLR_RXSTALLDEC_SIZE 1\n#define AVR32_USBB_UPCON3CLR_SHORTPACKETIEC 7\n#define AVR32_USBB_UPCON3CLR_SHORTPACKETIEC_MASK 0x00000080\n#define AVR32_USBB_UPCON3CLR_SHORTPACKETIEC_OFFSET 7\n#define AVR32_USBB_UPCON3CLR_SHORTPACKETIEC_SIZE 1\n#define AVR32_USBB_UPCON3CLR_TXOUTEC 1\n#define AVR32_USBB_UPCON3CLR_TXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UPCON3CLR_TXOUTEC_OFFSET 1\n#define AVR32_USBB_UPCON3CLR_TXOUTEC_SIZE 1\n#define AVR32_USBB_UPCON3CLR_TXSTPEC 2\n#define AVR32_USBB_UPCON3CLR_TXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UPCON3CLR_TXSTPEC_OFFSET 2\n#define AVR32_USBB_UPCON3CLR_TXSTPEC_SIZE 1\n#define AVR32_USBB_UPCON3SET 0x000005fc\n#define AVR32_USBB_UPCON3SET_NAKEDES 4\n#define AVR32_USBB_UPCON3SET_NAKEDES_MASK 0x00000010\n#define AVR32_USBB_UPCON3SET_NAKEDES_OFFSET 4\n#define AVR32_USBB_UPCON3SET_NAKEDES_SIZE 1\n#define AVR32_USBB_UPCON3SET_NBUSYBKES 12\n#define AVR32_USBB_UPCON3SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UPCON3SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UPCON3SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UPCON3SET_OVERFIES 5\n#define AVR32_USBB_UPCON3SET_OVERFIES_MASK 0x00000020\n#define AVR32_USBB_UPCON3SET_OVERFIES_OFFSET 5\n#define AVR32_USBB_UPCON3SET_OVERFIES_SIZE 1\n#define AVR32_USBB_UPCON3SET_PDISHDMAS 16\n#define AVR32_USBB_UPCON3SET_PDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UPCON3SET_PDISHDMAS_OFFSET 16\n#define AVR32_USBB_UPCON3SET_PDISHDMAS_SIZE 1\n#define AVR32_USBB_UPCON3SET_PERRES 3\n#define AVR32_USBB_UPCON3SET_PERRES_MASK 0x00000008\n#define AVR32_USBB_UPCON3SET_PERRES_OFFSET 3\n#define AVR32_USBB_UPCON3SET_PERRES_SIZE 1\n#define AVR32_USBB_UPCON3SET_PFREEZES 17\n#define AVR32_USBB_UPCON3SET_PFREEZES_MASK 0x00020000\n#define AVR32_USBB_UPCON3SET_PFREEZES_OFFSET 17\n#define AVR32_USBB_UPCON3SET_PFREEZES_SIZE 1\n#define AVR32_USBB_UPCON3SET_RSTDTS 18\n#define AVR32_USBB_UPCON3SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UPCON3SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UPCON3SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UPCON3SET_RXINES 0\n#define AVR32_USBB_UPCON3SET_RXINES_MASK 0x00000001\n#define AVR32_USBB_UPCON3SET_RXINES_OFFSET 0\n#define AVR32_USBB_UPCON3SET_RXINES_SIZE 1\n#define AVR32_USBB_UPCON3SET_RXSTALLDES 6\n#define AVR32_USBB_UPCON3SET_RXSTALLDES_MASK 0x00000040\n#define AVR32_USBB_UPCON3SET_RXSTALLDES_OFFSET 6\n#define AVR32_USBB_UPCON3SET_RXSTALLDES_SIZE 1\n#define AVR32_USBB_UPCON3SET_SHORTPACKETIES 7\n#define AVR32_USBB_UPCON3SET_SHORTPACKETIES_MASK 0x00000080\n#define AVR32_USBB_UPCON3SET_SHORTPACKETIES_OFFSET 7\n#define AVR32_USBB_UPCON3SET_SHORTPACKETIES_SIZE 1\n#define AVR32_USBB_UPCON3SET_TXOUTES 1\n#define AVR32_USBB_UPCON3SET_TXOUTES_MASK 0x00000002\n#define AVR32_USBB_UPCON3SET_TXOUTES_OFFSET 1\n#define AVR32_USBB_UPCON3SET_TXOUTES_SIZE 1\n#define AVR32_USBB_UPCON3SET_TXSTPES 2\n#define AVR32_USBB_UPCON3SET_TXSTPES_MASK 0x00000004\n#define AVR32_USBB_UPCON3SET_TXSTPES_OFFSET 2\n#define AVR32_USBB_UPCON3SET_TXSTPES_SIZE 1\n#define AVR32_USBB_UPCON3_FIFOCON 14\n#define AVR32_USBB_UPCON3_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UPCON3_FIFOCON_OFFSET 14\n#define AVR32_USBB_UPCON3_FIFOCON_SIZE 1\n#define AVR32_USBB_UPCON3_NAKEDE 4\n#define AVR32_USBB_UPCON3_NAKEDE_MASK 0x00000010\n#define AVR32_USBB_UPCON3_NAKEDE_OFFSET 4\n#define AVR32_USBB_UPCON3_NAKEDE_SIZE 1\n#define AVR32_USBB_UPCON3_NBUSYBKE 12\n#define AVR32_USBB_UPCON3_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UPCON3_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UPCON3_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UPCON3_OVERFIE 5\n#define AVR32_USBB_UPCON3_OVERFIE_MASK 0x00000020\n#define AVR32_USBB_UPCON3_OVERFIE_OFFSET 5\n#define AVR32_USBB_UPCON3_OVERFIE_SIZE 1\n#define AVR32_USBB_UPCON3_PDISHDMA 16\n#define AVR32_USBB_UPCON3_PDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UPCON3_PDISHDMA_OFFSET 16\n#define AVR32_USBB_UPCON3_PDISHDMA_SIZE 1\n#define AVR32_USBB_UPCON3_PERRE 3\n#define AVR32_USBB_UPCON3_PERRE_MASK 0x00000008\n#define AVR32_USBB_UPCON3_PERRE_OFFSET 3\n#define AVR32_USBB_UPCON3_PERRE_SIZE 1\n#define AVR32_USBB_UPCON3_PFREEZE 17\n#define AVR32_USBB_UPCON3_PFREEZE_MASK 0x00020000\n#define AVR32_USBB_UPCON3_PFREEZE_OFFSET 17\n#define AVR32_USBB_UPCON3_PFREEZE_SIZE 1\n#define AVR32_USBB_UPCON3_RSTDT 18\n#define AVR32_USBB_UPCON3_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UPCON3_RSTDT_OFFSET 18\n#define AVR32_USBB_UPCON3_RSTDT_SIZE 1\n#define AVR32_USBB_UPCON3_RXINE 0\n#define AVR32_USBB_UPCON3_RXINE_MASK 0x00000001\n#define AVR32_USBB_UPCON3_RXINE_OFFSET 0\n#define AVR32_USBB_UPCON3_RXINE_SIZE 1\n#define AVR32_USBB_UPCON3_RXSTALLDE 6\n#define AVR32_USBB_UPCON3_RXSTALLDE_MASK 0x00000040\n#define AVR32_USBB_UPCON3_RXSTALLDE_OFFSET 6\n#define AVR32_USBB_UPCON3_RXSTALLDE_SIZE 1\n#define AVR32_USBB_UPCON3_SHORTPACKETIE 7\n#define AVR32_USBB_UPCON3_SHORTPACKETIE_MASK 0x00000080\n#define AVR32_USBB_UPCON3_SHORTPACKETIE_OFFSET 7\n#define AVR32_USBB_UPCON3_SHORTPACKETIE_SIZE 1\n#define AVR32_USBB_UPCON3_TXOUTE 1\n#define AVR32_USBB_UPCON3_TXOUTE_MASK 0x00000002\n#define AVR32_USBB_UPCON3_TXOUTE_OFFSET 1\n#define AVR32_USBB_UPCON3_TXOUTE_SIZE 1\n#define AVR32_USBB_UPCON3_TXSTPE 2\n#define AVR32_USBB_UPCON3_TXSTPE_MASK 0x00000004\n#define AVR32_USBB_UPCON3_TXSTPE_OFFSET 2\n#define AVR32_USBB_UPCON3_TXSTPE_SIZE 1\n#define AVR32_USBB_UPCON4 0x000005d0\n#define AVR32_USBB_UPCON4CLR 0x00000630\n#define AVR32_USBB_UPCON4CLR_FIFOCONC 14\n#define AVR32_USBB_UPCON4CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UPCON4CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UPCON4CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UPCON4CLR_NAKEDEC 4\n#define AVR32_USBB_UPCON4CLR_NAKEDEC_MASK 0x00000010\n#define AVR32_USBB_UPCON4CLR_NAKEDEC_OFFSET 4\n#define AVR32_USBB_UPCON4CLR_NAKEDEC_SIZE 1\n#define AVR32_USBB_UPCON4CLR_NBUSYBKEC 12\n#define AVR32_USBB_UPCON4CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UPCON4CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UPCON4CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UPCON4CLR_OVERFIEC 5\n#define AVR32_USBB_UPCON4CLR_OVERFIEC_MASK 0x00000020\n#define AVR32_USBB_UPCON4CLR_OVERFIEC_OFFSET 5\n#define AVR32_USBB_UPCON4CLR_OVERFIEC_SIZE 1\n#define AVR32_USBB_UPCON4CLR_PDISHDMAC 16\n#define AVR32_USBB_UPCON4CLR_PDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UPCON4CLR_PDISHDMAC_OFFSET 16\n#define AVR32_USBB_UPCON4CLR_PDISHDMAC_SIZE 1\n#define AVR32_USBB_UPCON4CLR_PERREC 3\n#define AVR32_USBB_UPCON4CLR_PERREC_MASK 0x00000008\n#define AVR32_USBB_UPCON4CLR_PERREC_OFFSET 3\n#define AVR32_USBB_UPCON4CLR_PERREC_SIZE 1\n#define AVR32_USBB_UPCON4CLR_PFREEZEC 17\n#define AVR32_USBB_UPCON4CLR_PFREEZEC_MASK 0x00020000\n#define AVR32_USBB_UPCON4CLR_PFREEZEC_OFFSET 17\n#define AVR32_USBB_UPCON4CLR_PFREEZEC_SIZE 1\n#define AVR32_USBB_UPCON4CLR_RXINEC 0\n#define AVR32_USBB_UPCON4CLR_RXINEC_MASK 0x00000001\n#define AVR32_USBB_UPCON4CLR_RXINEC_OFFSET 0\n#define AVR32_USBB_UPCON4CLR_RXINEC_SIZE 1\n#define AVR32_USBB_UPCON4CLR_RXSTALLDEC 6\n#define AVR32_USBB_UPCON4CLR_RXSTALLDEC_MASK 0x00000040\n#define AVR32_USBB_UPCON4CLR_RXSTALLDEC_OFFSET 6\n#define AVR32_USBB_UPCON4CLR_RXSTALLDEC_SIZE 1\n#define AVR32_USBB_UPCON4CLR_SHORTPACKETIEC 7\n#define AVR32_USBB_UPCON4CLR_SHORTPACKETIEC_MASK 0x00000080\n#define AVR32_USBB_UPCON4CLR_SHORTPACKETIEC_OFFSET 7\n#define AVR32_USBB_UPCON4CLR_SHORTPACKETIEC_SIZE 1\n#define AVR32_USBB_UPCON4CLR_TXOUTEC 1\n#define AVR32_USBB_UPCON4CLR_TXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UPCON4CLR_TXOUTEC_OFFSET 1\n#define AVR32_USBB_UPCON4CLR_TXOUTEC_SIZE 1\n#define AVR32_USBB_UPCON4CLR_TXSTPEC 2\n#define AVR32_USBB_UPCON4CLR_TXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UPCON4CLR_TXSTPEC_OFFSET 2\n#define AVR32_USBB_UPCON4CLR_TXSTPEC_SIZE 1\n#define AVR32_USBB_UPCON4SET 0x00000600\n#define AVR32_USBB_UPCON4SET_NAKEDES 4\n#define AVR32_USBB_UPCON4SET_NAKEDES_MASK 0x00000010\n#define AVR32_USBB_UPCON4SET_NAKEDES_OFFSET 4\n#define AVR32_USBB_UPCON4SET_NAKEDES_SIZE 1\n#define AVR32_USBB_UPCON4SET_NBUSYBKES 12\n#define AVR32_USBB_UPCON4SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UPCON4SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UPCON4SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UPCON4SET_OVERFIES 5\n#define AVR32_USBB_UPCON4SET_OVERFIES_MASK 0x00000020\n#define AVR32_USBB_UPCON4SET_OVERFIES_OFFSET 5\n#define AVR32_USBB_UPCON4SET_OVERFIES_SIZE 1\n#define AVR32_USBB_UPCON4SET_PDISHDMAS 16\n#define AVR32_USBB_UPCON4SET_PDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UPCON4SET_PDISHDMAS_OFFSET 16\n#define AVR32_USBB_UPCON4SET_PDISHDMAS_SIZE 1\n#define AVR32_USBB_UPCON4SET_PERRES 3\n#define AVR32_USBB_UPCON4SET_PERRES_MASK 0x00000008\n#define AVR32_USBB_UPCON4SET_PERRES_OFFSET 3\n#define AVR32_USBB_UPCON4SET_PERRES_SIZE 1\n#define AVR32_USBB_UPCON4SET_PFREEZES 17\n#define AVR32_USBB_UPCON4SET_PFREEZES_MASK 0x00020000\n#define AVR32_USBB_UPCON4SET_PFREEZES_OFFSET 17\n#define AVR32_USBB_UPCON4SET_PFREEZES_SIZE 1\n#define AVR32_USBB_UPCON4SET_RSTDTS 18\n#define AVR32_USBB_UPCON4SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UPCON4SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UPCON4SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UPCON4SET_RXINES 0\n#define AVR32_USBB_UPCON4SET_RXINES_MASK 0x00000001\n#define AVR32_USBB_UPCON4SET_RXINES_OFFSET 0\n#define AVR32_USBB_UPCON4SET_RXINES_SIZE 1\n#define AVR32_USBB_UPCON4SET_RXSTALLDES 6\n#define AVR32_USBB_UPCON4SET_RXSTALLDES_MASK 0x00000040\n#define AVR32_USBB_UPCON4SET_RXSTALLDES_OFFSET 6\n#define AVR32_USBB_UPCON4SET_RXSTALLDES_SIZE 1\n#define AVR32_USBB_UPCON4SET_SHORTPACKETIES 7\n#define AVR32_USBB_UPCON4SET_SHORTPACKETIES_MASK 0x00000080\n#define AVR32_USBB_UPCON4SET_SHORTPACKETIES_OFFSET 7\n#define AVR32_USBB_UPCON4SET_SHORTPACKETIES_SIZE 1\n#define AVR32_USBB_UPCON4SET_TXOUTES 1\n#define AVR32_USBB_UPCON4SET_TXOUTES_MASK 0x00000002\n#define AVR32_USBB_UPCON4SET_TXOUTES_OFFSET 1\n#define AVR32_USBB_UPCON4SET_TXOUTES_SIZE 1\n#define AVR32_USBB_UPCON4SET_TXSTPES 2\n#define AVR32_USBB_UPCON4SET_TXSTPES_MASK 0x00000004\n#define AVR32_USBB_UPCON4SET_TXSTPES_OFFSET 2\n#define AVR32_USBB_UPCON4SET_TXSTPES_SIZE 1\n#define AVR32_USBB_UPCON4_FIFOCON 14\n#define AVR32_USBB_UPCON4_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UPCON4_FIFOCON_OFFSET 14\n#define AVR32_USBB_UPCON4_FIFOCON_SIZE 1\n#define AVR32_USBB_UPCON4_NAKEDE 4\n#define AVR32_USBB_UPCON4_NAKEDE_MASK 0x00000010\n#define AVR32_USBB_UPCON4_NAKEDE_OFFSET 4\n#define AVR32_USBB_UPCON4_NAKEDE_SIZE 1\n#define AVR32_USBB_UPCON4_NBUSYBKE 12\n#define AVR32_USBB_UPCON4_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UPCON4_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UPCON4_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UPCON4_OVERFIE 5\n#define AVR32_USBB_UPCON4_OVERFIE_MASK 0x00000020\n#define AVR32_USBB_UPCON4_OVERFIE_OFFSET 5\n#define AVR32_USBB_UPCON4_OVERFIE_SIZE 1\n#define AVR32_USBB_UPCON4_PDISHDMA 16\n#define AVR32_USBB_UPCON4_PDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UPCON4_PDISHDMA_OFFSET 16\n#define AVR32_USBB_UPCON4_PDISHDMA_SIZE 1\n#define AVR32_USBB_UPCON4_PERRE 3\n#define AVR32_USBB_UPCON4_PERRE_MASK 0x00000008\n#define AVR32_USBB_UPCON4_PERRE_OFFSET 3\n#define AVR32_USBB_UPCON4_PERRE_SIZE 1\n#define AVR32_USBB_UPCON4_PFREEZE 17\n#define AVR32_USBB_UPCON4_PFREEZE_MASK 0x00020000\n#define AVR32_USBB_UPCON4_PFREEZE_OFFSET 17\n#define AVR32_USBB_UPCON4_PFREEZE_SIZE 1\n#define AVR32_USBB_UPCON4_RSTDT 18\n#define AVR32_USBB_UPCON4_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UPCON4_RSTDT_OFFSET 18\n#define AVR32_USBB_UPCON4_RSTDT_SIZE 1\n#define AVR32_USBB_UPCON4_RXINE 0\n#define AVR32_USBB_UPCON4_RXINE_MASK 0x00000001\n#define AVR32_USBB_UPCON4_RXINE_OFFSET 0\n#define AVR32_USBB_UPCON4_RXINE_SIZE 1\n#define AVR32_USBB_UPCON4_RXSTALLDE 6\n#define AVR32_USBB_UPCON4_RXSTALLDE_MASK 0x00000040\n#define AVR32_USBB_UPCON4_RXSTALLDE_OFFSET 6\n#define AVR32_USBB_UPCON4_RXSTALLDE_SIZE 1\n#define AVR32_USBB_UPCON4_SHORTPACKETIE 7\n#define AVR32_USBB_UPCON4_SHORTPACKETIE_MASK 0x00000080\n#define AVR32_USBB_UPCON4_SHORTPACKETIE_OFFSET 7\n#define AVR32_USBB_UPCON4_SHORTPACKETIE_SIZE 1\n#define AVR32_USBB_UPCON4_TXOUTE 1\n#define AVR32_USBB_UPCON4_TXOUTE_MASK 0x00000002\n#define AVR32_USBB_UPCON4_TXOUTE_OFFSET 1\n#define AVR32_USBB_UPCON4_TXOUTE_SIZE 1\n#define AVR32_USBB_UPCON4_TXSTPE 2\n#define AVR32_USBB_UPCON4_TXSTPE_MASK 0x00000004\n#define AVR32_USBB_UPCON4_TXSTPE_OFFSET 2\n#define AVR32_USBB_UPCON4_TXSTPE_SIZE 1\n#define AVR32_USBB_UPCON5 0x000005d4\n#define AVR32_USBB_UPCON5CLR 0x00000634\n#define AVR32_USBB_UPCON5CLR_FIFOCONC 14\n#define AVR32_USBB_UPCON5CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UPCON5CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UPCON5CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UPCON5CLR_NAKEDEC 4\n#define AVR32_USBB_UPCON5CLR_NAKEDEC_MASK 0x00000010\n#define AVR32_USBB_UPCON5CLR_NAKEDEC_OFFSET 4\n#define AVR32_USBB_UPCON5CLR_NAKEDEC_SIZE 1\n#define AVR32_USBB_UPCON5CLR_NBUSYBKEC 12\n#define AVR32_USBB_UPCON5CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UPCON5CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UPCON5CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UPCON5CLR_OVERFIEC 5\n#define AVR32_USBB_UPCON5CLR_OVERFIEC_MASK 0x00000020\n#define AVR32_USBB_UPCON5CLR_OVERFIEC_OFFSET 5\n#define AVR32_USBB_UPCON5CLR_OVERFIEC_SIZE 1\n#define AVR32_USBB_UPCON5CLR_PDISHDMAC 16\n#define AVR32_USBB_UPCON5CLR_PDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UPCON5CLR_PDISHDMAC_OFFSET 16\n#define AVR32_USBB_UPCON5CLR_PDISHDMAC_SIZE 1\n#define AVR32_USBB_UPCON5CLR_PERREC 3\n#define AVR32_USBB_UPCON5CLR_PERREC_MASK 0x00000008\n#define AVR32_USBB_UPCON5CLR_PERREC_OFFSET 3\n#define AVR32_USBB_UPCON5CLR_PERREC_SIZE 1\n#define AVR32_USBB_UPCON5CLR_PFREEZEC 17\n#define AVR32_USBB_UPCON5CLR_PFREEZEC_MASK 0x00020000\n#define AVR32_USBB_UPCON5CLR_PFREEZEC_OFFSET 17\n#define AVR32_USBB_UPCON5CLR_PFREEZEC_SIZE 1\n#define AVR32_USBB_UPCON5CLR_RXINEC 0\n#define AVR32_USBB_UPCON5CLR_RXINEC_MASK 0x00000001\n#define AVR32_USBB_UPCON5CLR_RXINEC_OFFSET 0\n#define AVR32_USBB_UPCON5CLR_RXINEC_SIZE 1\n#define AVR32_USBB_UPCON5CLR_RXSTALLDEC 6\n#define AVR32_USBB_UPCON5CLR_RXSTALLDEC_MASK 0x00000040\n#define AVR32_USBB_UPCON5CLR_RXSTALLDEC_OFFSET 6\n#define AVR32_USBB_UPCON5CLR_RXSTALLDEC_SIZE 1\n#define AVR32_USBB_UPCON5CLR_SHORTPACKETIEC 7\n#define AVR32_USBB_UPCON5CLR_SHORTPACKETIEC_MASK 0x00000080\n#define AVR32_USBB_UPCON5CLR_SHORTPACKETIEC_OFFSET 7\n#define AVR32_USBB_UPCON5CLR_SHORTPACKETIEC_SIZE 1\n#define AVR32_USBB_UPCON5CLR_TXOUTEC 1\n#define AVR32_USBB_UPCON5CLR_TXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UPCON5CLR_TXOUTEC_OFFSET 1\n#define AVR32_USBB_UPCON5CLR_TXOUTEC_SIZE 1\n#define AVR32_USBB_UPCON5CLR_TXSTPEC 2\n#define AVR32_USBB_UPCON5CLR_TXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UPCON5CLR_TXSTPEC_OFFSET 2\n#define AVR32_USBB_UPCON5CLR_TXSTPEC_SIZE 1\n#define AVR32_USBB_UPCON5SET 0x00000604\n#define AVR32_USBB_UPCON5SET_NAKEDES 4\n#define AVR32_USBB_UPCON5SET_NAKEDES_MASK 0x00000010\n#define AVR32_USBB_UPCON5SET_NAKEDES_OFFSET 4\n#define AVR32_USBB_UPCON5SET_NAKEDES_SIZE 1\n#define AVR32_USBB_UPCON5SET_NBUSYBKES 12\n#define AVR32_USBB_UPCON5SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UPCON5SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UPCON5SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UPCON5SET_OVERFIES 5\n#define AVR32_USBB_UPCON5SET_OVERFIES_MASK 0x00000020\n#define AVR32_USBB_UPCON5SET_OVERFIES_OFFSET 5\n#define AVR32_USBB_UPCON5SET_OVERFIES_SIZE 1\n#define AVR32_USBB_UPCON5SET_PDISHDMAS 16\n#define AVR32_USBB_UPCON5SET_PDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UPCON5SET_PDISHDMAS_OFFSET 16\n#define AVR32_USBB_UPCON5SET_PDISHDMAS_SIZE 1\n#define AVR32_USBB_UPCON5SET_PERRES 3\n#define AVR32_USBB_UPCON5SET_PERRES_MASK 0x00000008\n#define AVR32_USBB_UPCON5SET_PERRES_OFFSET 3\n#define AVR32_USBB_UPCON5SET_PERRES_SIZE 1\n#define AVR32_USBB_UPCON5SET_PFREEZES 17\n#define AVR32_USBB_UPCON5SET_PFREEZES_MASK 0x00020000\n#define AVR32_USBB_UPCON5SET_PFREEZES_OFFSET 17\n#define AVR32_USBB_UPCON5SET_PFREEZES_SIZE 1\n#define AVR32_USBB_UPCON5SET_RSTDTS 18\n#define AVR32_USBB_UPCON5SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UPCON5SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UPCON5SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UPCON5SET_RXINES 0\n#define AVR32_USBB_UPCON5SET_RXINES_MASK 0x00000001\n#define AVR32_USBB_UPCON5SET_RXINES_OFFSET 0\n#define AVR32_USBB_UPCON5SET_RXINES_SIZE 1\n#define AVR32_USBB_UPCON5SET_RXSTALLDES 6\n#define AVR32_USBB_UPCON5SET_RXSTALLDES_MASK 0x00000040\n#define AVR32_USBB_UPCON5SET_RXSTALLDES_OFFSET 6\n#define AVR32_USBB_UPCON5SET_RXSTALLDES_SIZE 1\n#define AVR32_USBB_UPCON5SET_SHORTPACKETIES 7\n#define AVR32_USBB_UPCON5SET_SHORTPACKETIES_MASK 0x00000080\n#define AVR32_USBB_UPCON5SET_SHORTPACKETIES_OFFSET 7\n#define AVR32_USBB_UPCON5SET_SHORTPACKETIES_SIZE 1\n#define AVR32_USBB_UPCON5SET_TXOUTES 1\n#define AVR32_USBB_UPCON5SET_TXOUTES_MASK 0x00000002\n#define AVR32_USBB_UPCON5SET_TXOUTES_OFFSET 1\n#define AVR32_USBB_UPCON5SET_TXOUTES_SIZE 1\n#define AVR32_USBB_UPCON5SET_TXSTPES 2\n#define AVR32_USBB_UPCON5SET_TXSTPES_MASK 0x00000004\n#define AVR32_USBB_UPCON5SET_TXSTPES_OFFSET 2\n#define AVR32_USBB_UPCON5SET_TXSTPES_SIZE 1\n#define AVR32_USBB_UPCON5_FIFOCON 14\n#define AVR32_USBB_UPCON5_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UPCON5_FIFOCON_OFFSET 14\n#define AVR32_USBB_UPCON5_FIFOCON_SIZE 1\n#define AVR32_USBB_UPCON5_NAKEDE 4\n#define AVR32_USBB_UPCON5_NAKEDE_MASK 0x00000010\n#define AVR32_USBB_UPCON5_NAKEDE_OFFSET 4\n#define AVR32_USBB_UPCON5_NAKEDE_SIZE 1\n#define AVR32_USBB_UPCON5_NBUSYBKE 12\n#define AVR32_USBB_UPCON5_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UPCON5_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UPCON5_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UPCON5_OVERFIE 5\n#define AVR32_USBB_UPCON5_OVERFIE_MASK 0x00000020\n#define AVR32_USBB_UPCON5_OVERFIE_OFFSET 5\n#define AVR32_USBB_UPCON5_OVERFIE_SIZE 1\n#define AVR32_USBB_UPCON5_PDISHDMA 16\n#define AVR32_USBB_UPCON5_PDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UPCON5_PDISHDMA_OFFSET 16\n#define AVR32_USBB_UPCON5_PDISHDMA_SIZE 1\n#define AVR32_USBB_UPCON5_PERRE 3\n#define AVR32_USBB_UPCON5_PERRE_MASK 0x00000008\n#define AVR32_USBB_UPCON5_PERRE_OFFSET 3\n#define AVR32_USBB_UPCON5_PERRE_SIZE 1\n#define AVR32_USBB_UPCON5_PFREEZE 17\n#define AVR32_USBB_UPCON5_PFREEZE_MASK 0x00020000\n#define AVR32_USBB_UPCON5_PFREEZE_OFFSET 17\n#define AVR32_USBB_UPCON5_PFREEZE_SIZE 1\n#define AVR32_USBB_UPCON5_RSTDT 18\n#define AVR32_USBB_UPCON5_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UPCON5_RSTDT_OFFSET 18\n#define AVR32_USBB_UPCON5_RSTDT_SIZE 1\n#define AVR32_USBB_UPCON5_RXINE 0\n#define AVR32_USBB_UPCON5_RXINE_MASK 0x00000001\n#define AVR32_USBB_UPCON5_RXINE_OFFSET 0\n#define AVR32_USBB_UPCON5_RXINE_SIZE 1\n#define AVR32_USBB_UPCON5_RXSTALLDE 6\n#define AVR32_USBB_UPCON5_RXSTALLDE_MASK 0x00000040\n#define AVR32_USBB_UPCON5_RXSTALLDE_OFFSET 6\n#define AVR32_USBB_UPCON5_RXSTALLDE_SIZE 1\n#define AVR32_USBB_UPCON5_SHORTPACKETIE 7\n#define AVR32_USBB_UPCON5_SHORTPACKETIE_MASK 0x00000080\n#define AVR32_USBB_UPCON5_SHORTPACKETIE_OFFSET 7\n#define AVR32_USBB_UPCON5_SHORTPACKETIE_SIZE 1\n#define AVR32_USBB_UPCON5_TXOUTE 1\n#define AVR32_USBB_UPCON5_TXOUTE_MASK 0x00000002\n#define AVR32_USBB_UPCON5_TXOUTE_OFFSET 1\n#define AVR32_USBB_UPCON5_TXOUTE_SIZE 1\n#define AVR32_USBB_UPCON5_TXSTPE 2\n#define AVR32_USBB_UPCON5_TXSTPE_MASK 0x00000004\n#define AVR32_USBB_UPCON5_TXSTPE_OFFSET 2\n#define AVR32_USBB_UPCON5_TXSTPE_SIZE 1\n#define AVR32_USBB_UPCON6 0x000005d8\n#define AVR32_USBB_UPCON6CLR 0x00000638\n#define AVR32_USBB_UPCON6CLR_FIFOCONC 14\n#define AVR32_USBB_UPCON6CLR_FIFOCONC_MASK 0x00004000\n#define AVR32_USBB_UPCON6CLR_FIFOCONC_OFFSET 14\n#define AVR32_USBB_UPCON6CLR_FIFOCONC_SIZE 1\n#define AVR32_USBB_UPCON6CLR_NAKEDEC 4\n#define AVR32_USBB_UPCON6CLR_NAKEDEC_MASK 0x00000010\n#define AVR32_USBB_UPCON6CLR_NAKEDEC_OFFSET 4\n#define AVR32_USBB_UPCON6CLR_NAKEDEC_SIZE 1\n#define AVR32_USBB_UPCON6CLR_NBUSYBKEC 12\n#define AVR32_USBB_UPCON6CLR_NBUSYBKEC_MASK 0x00001000\n#define AVR32_USBB_UPCON6CLR_NBUSYBKEC_OFFSET 12\n#define AVR32_USBB_UPCON6CLR_NBUSYBKEC_SIZE 1\n#define AVR32_USBB_UPCON6CLR_OVERFIEC 5\n#define AVR32_USBB_UPCON6CLR_OVERFIEC_MASK 0x00000020\n#define AVR32_USBB_UPCON6CLR_OVERFIEC_OFFSET 5\n#define AVR32_USBB_UPCON6CLR_OVERFIEC_SIZE 1\n#define AVR32_USBB_UPCON6CLR_PDISHDMAC 16\n#define AVR32_USBB_UPCON6CLR_PDISHDMAC_MASK 0x00010000\n#define AVR32_USBB_UPCON6CLR_PDISHDMAC_OFFSET 16\n#define AVR32_USBB_UPCON6CLR_PDISHDMAC_SIZE 1\n#define AVR32_USBB_UPCON6CLR_PERREC 3\n#define AVR32_USBB_UPCON6CLR_PERREC_MASK 0x00000008\n#define AVR32_USBB_UPCON6CLR_PERREC_OFFSET 3\n#define AVR32_USBB_UPCON6CLR_PERREC_SIZE 1\n#define AVR32_USBB_UPCON6CLR_PFREEZEC 17\n#define AVR32_USBB_UPCON6CLR_PFREEZEC_MASK 0x00020000\n#define AVR32_USBB_UPCON6CLR_PFREEZEC_OFFSET 17\n#define AVR32_USBB_UPCON6CLR_PFREEZEC_SIZE 1\n#define AVR32_USBB_UPCON6CLR_RXINEC 0\n#define AVR32_USBB_UPCON6CLR_RXINEC_MASK 0x00000001\n#define AVR32_USBB_UPCON6CLR_RXINEC_OFFSET 0\n#define AVR32_USBB_UPCON6CLR_RXINEC_SIZE 1\n#define AVR32_USBB_UPCON6CLR_RXSTALLDEC 6\n#define AVR32_USBB_UPCON6CLR_RXSTALLDEC_MASK 0x00000040\n#define AVR32_USBB_UPCON6CLR_RXSTALLDEC_OFFSET 6\n#define AVR32_USBB_UPCON6CLR_RXSTALLDEC_SIZE 1\n#define AVR32_USBB_UPCON6CLR_SHORTPACKETIEC 7\n#define AVR32_USBB_UPCON6CLR_SHORTPACKETIEC_MASK 0x00000080\n#define AVR32_USBB_UPCON6CLR_SHORTPACKETIEC_OFFSET 7\n#define AVR32_USBB_UPCON6CLR_SHORTPACKETIEC_SIZE 1\n#define AVR32_USBB_UPCON6CLR_TXOUTEC 1\n#define AVR32_USBB_UPCON6CLR_TXOUTEC_MASK 0x00000002\n#define AVR32_USBB_UPCON6CLR_TXOUTEC_OFFSET 1\n#define AVR32_USBB_UPCON6CLR_TXOUTEC_SIZE 1\n#define AVR32_USBB_UPCON6CLR_TXSTPEC 2\n#define AVR32_USBB_UPCON6CLR_TXSTPEC_MASK 0x00000004\n#define AVR32_USBB_UPCON6CLR_TXSTPEC_OFFSET 2\n#define AVR32_USBB_UPCON6CLR_TXSTPEC_SIZE 1\n#define AVR32_USBB_UPCON6SET 0x00000608\n#define AVR32_USBB_UPCON6SET_NAKEDES 4\n#define AVR32_USBB_UPCON6SET_NAKEDES_MASK 0x00000010\n#define AVR32_USBB_UPCON6SET_NAKEDES_OFFSET 4\n#define AVR32_USBB_UPCON6SET_NAKEDES_SIZE 1\n#define AVR32_USBB_UPCON6SET_NBUSYBKES 12\n#define AVR32_USBB_UPCON6SET_NBUSYBKES_MASK 0x00001000\n#define AVR32_USBB_UPCON6SET_NBUSYBKES_OFFSET 12\n#define AVR32_USBB_UPCON6SET_NBUSYBKES_SIZE 1\n#define AVR32_USBB_UPCON6SET_OVERFIES 5\n#define AVR32_USBB_UPCON6SET_OVERFIES_MASK 0x00000020\n#define AVR32_USBB_UPCON6SET_OVERFIES_OFFSET 5\n#define AVR32_USBB_UPCON6SET_OVERFIES_SIZE 1\n#define AVR32_USBB_UPCON6SET_PDISHDMAS 16\n#define AVR32_USBB_UPCON6SET_PDISHDMAS_MASK 0x00010000\n#define AVR32_USBB_UPCON6SET_PDISHDMAS_OFFSET 16\n#define AVR32_USBB_UPCON6SET_PDISHDMAS_SIZE 1\n#define AVR32_USBB_UPCON6SET_PERRES 3\n#define AVR32_USBB_UPCON6SET_PERRES_MASK 0x00000008\n#define AVR32_USBB_UPCON6SET_PERRES_OFFSET 3\n#define AVR32_USBB_UPCON6SET_PERRES_SIZE 1\n#define AVR32_USBB_UPCON6SET_PFREEZES 17\n#define AVR32_USBB_UPCON6SET_PFREEZES_MASK 0x00020000\n#define AVR32_USBB_UPCON6SET_PFREEZES_OFFSET 17\n#define AVR32_USBB_UPCON6SET_PFREEZES_SIZE 1\n#define AVR32_USBB_UPCON6SET_RSTDTS 18\n#define AVR32_USBB_UPCON6SET_RSTDTS_MASK 0x00040000\n#define AVR32_USBB_UPCON6SET_RSTDTS_OFFSET 18\n#define AVR32_USBB_UPCON6SET_RSTDTS_SIZE 1\n#define AVR32_USBB_UPCON6SET_RXINES 0\n#define AVR32_USBB_UPCON6SET_RXINES_MASK 0x00000001\n#define AVR32_USBB_UPCON6SET_RXINES_OFFSET 0\n#define AVR32_USBB_UPCON6SET_RXINES_SIZE 1\n#define AVR32_USBB_UPCON6SET_RXSTALLDES 6\n#define AVR32_USBB_UPCON6SET_RXSTALLDES_MASK 0x00000040\n#define AVR32_USBB_UPCON6SET_RXSTALLDES_OFFSET 6\n#define AVR32_USBB_UPCON6SET_RXSTALLDES_SIZE 1\n#define AVR32_USBB_UPCON6SET_SHORTPACKETIES 7\n#define AVR32_USBB_UPCON6SET_SHORTPACKETIES_MASK 0x00000080\n#define AVR32_USBB_UPCON6SET_SHORTPACKETIES_OFFSET 7\n#define AVR32_USBB_UPCON6SET_SHORTPACKETIES_SIZE 1\n#define AVR32_USBB_UPCON6SET_TXOUTES 1\n#define AVR32_USBB_UPCON6SET_TXOUTES_MASK 0x00000002\n#define AVR32_USBB_UPCON6SET_TXOUTES_OFFSET 1\n#define AVR32_USBB_UPCON6SET_TXOUTES_SIZE 1\n#define AVR32_USBB_UPCON6SET_TXSTPES 2\n#define AVR32_USBB_UPCON6SET_TXSTPES_MASK 0x00000004\n#define AVR32_USBB_UPCON6SET_TXSTPES_OFFSET 2\n#define AVR32_USBB_UPCON6SET_TXSTPES_SIZE 1\n#define AVR32_USBB_UPCON6_FIFOCON 14\n#define AVR32_USBB_UPCON6_FIFOCON_MASK 0x00004000\n#define AVR32_USBB_UPCON6_FIFOCON_OFFSET 14\n#define AVR32_USBB_UPCON6_FIFOCON_SIZE 1\n#define AVR32_USBB_UPCON6_NAKEDE 4\n#define AVR32_USBB_UPCON6_NAKEDE_MASK 0x00000010\n#define AVR32_USBB_UPCON6_NAKEDE_OFFSET 4\n#define AVR32_USBB_UPCON6_NAKEDE_SIZE 1\n#define AVR32_USBB_UPCON6_NBUSYBKE 12\n#define AVR32_USBB_UPCON6_NBUSYBKE_MASK 0x00001000\n#define AVR32_USBB_UPCON6_NBUSYBKE_OFFSET 12\n#define AVR32_USBB_UPCON6_NBUSYBKE_SIZE 1\n#define AVR32_USBB_UPCON6_OVERFIE 5\n#define AVR32_USBB_UPCON6_OVERFIE_MASK 0x00000020\n#define AVR32_USBB_UPCON6_OVERFIE_OFFSET 5\n#define AVR32_USBB_UPCON6_OVERFIE_SIZE 1\n#define AVR32_USBB_UPCON6_PDISHDMA 16\n#define AVR32_USBB_UPCON6_PDISHDMA_MASK 0x00010000\n#define AVR32_USBB_UPCON6_PDISHDMA_OFFSET 16\n#define AVR32_USBB_UPCON6_PDISHDMA_SIZE 1\n#define AVR32_USBB_UPCON6_PERRE 3\n#define AVR32_USBB_UPCON6_PERRE_MASK 0x00000008\n#define AVR32_USBB_UPCON6_PERRE_OFFSET 3\n#define AVR32_USBB_UPCON6_PERRE_SIZE 1\n#define AVR32_USBB_UPCON6_PFREEZE 17\n#define AVR32_USBB_UPCON6_PFREEZE_MASK 0x00020000\n#define AVR32_USBB_UPCON6_PFREEZE_OFFSET 17\n#define AVR32_USBB_UPCON6_PFREEZE_SIZE 1\n#define AVR32_USBB_UPCON6_RSTDT 18\n#define AVR32_USBB_UPCON6_RSTDT_MASK 0x00040000\n#define AVR32_USBB_UPCON6_RSTDT_OFFSET 18\n#define AVR32_USBB_UPCON6_RSTDT_SIZE 1\n#define AVR32_USBB_UPCON6_RXINE 0\n#define AVR32_USBB_UPCON6_RXINE_MASK 0x00000001\n#define AVR32_USBB_UPCON6_RXINE_OFFSET 0\n#define AVR32_USBB_UPCON6_RXINE_SIZE 1\n#define AVR32_USBB_UPCON6_RXSTALLDE 6\n#define AVR32_USBB_UPCON6_RXSTALLDE_MASK 0x00000040\n#define AVR32_USBB_UPCON6_RXSTALLDE_OFFSET 6\n#define AVR32_USBB_UPCON6_RXSTALLDE_SIZE 1\n#define AVR32_USBB_UPCON6_SHORTPACKETIE 7\n#define AVR32_USBB_UPCON6_SHORTPACKETIE_MASK 0x00000080\n#define AVR32_USBB_UPCON6_SHORTPACKETIE_OFFSET 7\n#define AVR32_USBB_UPCON6_SHORTPACKETIE_SIZE 1\n#define AVR32_USBB_UPCON6_TXOUTE 1\n#define AVR32_USBB_UPCON6_TXOUTE_MASK 0x00000002\n#define AVR32_USBB_UPCON6_TXOUTE_OFFSET 1\n#define AVR32_USBB_UPCON6_TXOUTE_SIZE 1\n#define AVR32_USBB_UPCON6_TXSTPE 2\n#define AVR32_USBB_UPCON6_TXSTPE_MASK 0x00000004\n#define AVR32_USBB_UPCON6_TXSTPE_OFFSET 2\n#define AVR32_USBB_UPCON6_TXSTPE_SIZE 1\n#define AVR32_USBB_UPDAT0 0x000006b0\n#define AVR32_USBB_UPDAT0_P_DATA 0\n#define AVR32_USBB_UPDAT0_P_DATA_MASK 0xffffffff\n#define AVR32_USBB_UPDAT0_P_DATA_OFFSET 0\n#define AVR32_USBB_UPDAT0_P_DATA_SIZE 32\n#define AVR32_USBB_UPDAT1 0x000006b4\n#define AVR32_USBB_UPDAT1_P_DATA 0\n#define AVR32_USBB_UPDAT1_P_DATA_MASK 0xffffffff\n#define AVR32_USBB_UPDAT1_P_DATA_OFFSET 0\n#define AVR32_USBB_UPDAT1_P_DATA_SIZE 32\n#define AVR32_USBB_UPDAT2 0x000006b8\n#define AVR32_USBB_UPDAT2_P_DATA 0\n#define AVR32_USBB_UPDAT2_P_DATA_MASK 0xffffffff\n#define AVR32_USBB_UPDAT2_P_DATA_OFFSET 0\n#define AVR32_USBB_UPDAT2_P_DATA_SIZE 32\n#define AVR32_USBB_UPDAT3 0x000006bc\n#define AVR32_USBB_UPDAT3_P_DATA 0\n#define AVR32_USBB_UPDAT3_P_DATA_MASK 0xffffffff\n#define AVR32_USBB_UPDAT3_P_DATA_OFFSET 0\n#define AVR32_USBB_UPDAT3_P_DATA_SIZE 32\n#define AVR32_USBB_UPDAT4 0x000006c0\n#define AVR32_USBB_UPDAT4_P_DATA 0\n#define AVR32_USBB_UPDAT4_P_DATA_MASK 0xffffffff\n#define AVR32_USBB_UPDAT4_P_DATA_OFFSET 0\n#define AVR32_USBB_UPDAT4_P_DATA_SIZE 32\n#define AVR32_USBB_UPDAT5 0x000006c4\n#define AVR32_USBB_UPDAT5_P_DATA 0\n#define AVR32_USBB_UPDAT5_P_DATA_MASK 0xffffffff\n#define AVR32_USBB_UPDAT5_P_DATA_OFFSET 0\n#define AVR32_USBB_UPDAT5_P_DATA_SIZE 32\n#define AVR32_USBB_UPDAT6 0x000006c8\n#define AVR32_USBB_UPDAT6_P_DATA 0\n#define AVR32_USBB_UPDAT6_P_DATA_MASK 0xffffffff\n#define AVR32_USBB_UPDAT6_P_DATA_OFFSET 0\n#define AVR32_USBB_UPDAT6_P_DATA_SIZE 32\n#define AVR32_USBB_UPERR0 0x00000680\n#define AVR32_USBB_UPERR0_COUNTER 5\n#define AVR32_USBB_UPERR0_COUNTER_MASK 0x00000060\n#define AVR32_USBB_UPERR0_COUNTER_OFFSET 5\n#define AVR32_USBB_UPERR0_COUNTER_SIZE 2\n#define AVR32_USBB_UPERR0_CRC16 4\n#define AVR32_USBB_UPERR0_CRC16_MASK 0x00000010\n#define AVR32_USBB_UPERR0_CRC16_OFFSET 4\n#define AVR32_USBB_UPERR0_CRC16_SIZE 1\n#define AVR32_USBB_UPERR0_DATAPID 1\n#define AVR32_USBB_UPERR0_DATAPID_MASK 0x00000002\n#define AVR32_USBB_UPERR0_DATAPID_OFFSET 1\n#define AVR32_USBB_UPERR0_DATAPID_SIZE 1\n#define AVR32_USBB_UPERR0_DATATGL 0\n#define AVR32_USBB_UPERR0_DATATGL_MASK 0x00000001\n#define AVR32_USBB_UPERR0_DATATGL_OFFSET 0\n#define AVR32_USBB_UPERR0_DATATGL_SIZE 1\n#define AVR32_USBB_UPERR0_PID 2\n#define AVR32_USBB_UPERR0_PID_MASK 0x00000004\n#define AVR32_USBB_UPERR0_PID_OFFSET 2\n#define AVR32_USBB_UPERR0_PID_SIZE 1\n#define AVR32_USBB_UPERR0_TIMEOUT 3\n#define AVR32_USBB_UPERR0_TIMEOUT_MASK 0x00000008\n#define AVR32_USBB_UPERR0_TIMEOUT_OFFSET 3\n#define AVR32_USBB_UPERR0_TIMEOUT_SIZE 1\n#define AVR32_USBB_UPERR1 0x00000684\n#define AVR32_USBB_UPERR1_COUNTER 5\n#define AVR32_USBB_UPERR1_COUNTER_MASK 0x00000060\n#define AVR32_USBB_UPERR1_COUNTER_OFFSET 5\n#define AVR32_USBB_UPERR1_COUNTER_SIZE 2\n#define AVR32_USBB_UPERR1_CRC16 4\n#define AVR32_USBB_UPERR1_CRC16_MASK 0x00000010\n#define AVR32_USBB_UPERR1_CRC16_OFFSET 4\n#define AVR32_USBB_UPERR1_CRC16_SIZE 1\n#define AVR32_USBB_UPERR1_DATAPID 1\n#define AVR32_USBB_UPERR1_DATAPID_MASK 0x00000002\n#define AVR32_USBB_UPERR1_DATAPID_OFFSET 1\n#define AVR32_USBB_UPERR1_DATAPID_SIZE 1\n#define AVR32_USBB_UPERR1_DATATGL 0\n#define AVR32_USBB_UPERR1_DATATGL_MASK 0x00000001\n#define AVR32_USBB_UPERR1_DATATGL_OFFSET 0\n#define AVR32_USBB_UPERR1_DATATGL_SIZE 1\n#define AVR32_USBB_UPERR1_PID 2\n#define AVR32_USBB_UPERR1_PID_MASK 0x00000004\n#define AVR32_USBB_UPERR1_PID_OFFSET 2\n#define AVR32_USBB_UPERR1_PID_SIZE 1\n#define AVR32_USBB_UPERR1_TIMEOUT 3\n#define AVR32_USBB_UPERR1_TIMEOUT_MASK 0x00000008\n#define AVR32_USBB_UPERR1_TIMEOUT_OFFSET 3\n#define AVR32_USBB_UPERR1_TIMEOUT_SIZE 1\n#define AVR32_USBB_UPERR2 0x00000688\n#define AVR32_USBB_UPERR2_COUNTER 5\n#define AVR32_USBB_UPERR2_COUNTER_MASK 0x00000060\n#define AVR32_USBB_UPERR2_COUNTER_OFFSET 5\n#define AVR32_USBB_UPERR2_COUNTER_SIZE 2\n#define AVR32_USBB_UPERR2_CRC16 4\n#define AVR32_USBB_UPERR2_CRC16_MASK 0x00000010\n#define AVR32_USBB_UPERR2_CRC16_OFFSET 4\n#define AVR32_USBB_UPERR2_CRC16_SIZE 1\n#define AVR32_USBB_UPERR2_DATAPID 1\n#define AVR32_USBB_UPERR2_DATAPID_MASK 0x00000002\n#define AVR32_USBB_UPERR2_DATAPID_OFFSET 1\n#define AVR32_USBB_UPERR2_DATAPID_SIZE 1\n#define AVR32_USBB_UPERR2_DATATGL 0\n#define AVR32_USBB_UPERR2_DATATGL_MASK 0x00000001\n#define AVR32_USBB_UPERR2_DATATGL_OFFSET 0\n#define AVR32_USBB_UPERR2_DATATGL_SIZE 1\n#define AVR32_USBB_UPERR2_PID 2\n#define AVR32_USBB_UPERR2_PID_MASK 0x00000004\n#define AVR32_USBB_UPERR2_PID_OFFSET 2\n#define AVR32_USBB_UPERR2_PID_SIZE 1\n#define AVR32_USBB_UPERR2_TIMEOUT 3\n#define AVR32_USBB_UPERR2_TIMEOUT_MASK 0x00000008\n#define AVR32_USBB_UPERR2_TIMEOUT_OFFSET 3\n#define AVR32_USBB_UPERR2_TIMEOUT_SIZE 1\n#define AVR32_USBB_UPERR3 0x0000068c\n#define AVR32_USBB_UPERR3_COUNTER 5\n#define AVR32_USBB_UPERR3_COUNTER_MASK 0x00000060\n#define AVR32_USBB_UPERR3_COUNTER_OFFSET 5\n#define AVR32_USBB_UPERR3_COUNTER_SIZE 2\n#define AVR32_USBB_UPERR3_CRC16 4\n#define AVR32_USBB_UPERR3_CRC16_MASK 0x00000010\n#define AVR32_USBB_UPERR3_CRC16_OFFSET 4\n#define AVR32_USBB_UPERR3_CRC16_SIZE 1\n#define AVR32_USBB_UPERR3_DATAPID 1\n#define AVR32_USBB_UPERR3_DATAPID_MASK 0x00000002\n#define AVR32_USBB_UPERR3_DATAPID_OFFSET 1\n#define AVR32_USBB_UPERR3_DATAPID_SIZE 1\n#define AVR32_USBB_UPERR3_DATATGL 0\n#define AVR32_USBB_UPERR3_DATATGL_MASK 0x00000001\n#define AVR32_USBB_UPERR3_DATATGL_OFFSET 0\n#define AVR32_USBB_UPERR3_DATATGL_SIZE 1\n#define AVR32_USBB_UPERR3_PID 2\n#define AVR32_USBB_UPERR3_PID_MASK 0x00000004\n#define AVR32_USBB_UPERR3_PID_OFFSET 2\n#define AVR32_USBB_UPERR3_PID_SIZE 1\n#define AVR32_USBB_UPERR3_TIMEOUT 3\n#define AVR32_USBB_UPERR3_TIMEOUT_MASK 0x00000008\n#define AVR32_USBB_UPERR3_TIMEOUT_OFFSET 3\n#define AVR32_USBB_UPERR3_TIMEOUT_SIZE 1\n#define AVR32_USBB_UPERR4 0x00000690\n#define AVR32_USBB_UPERR4_COUNTER 5\n#define AVR32_USBB_UPERR4_COUNTER_MASK 0x00000060\n#define AVR32_USBB_UPERR4_COUNTER_OFFSET 5\n#define AVR32_USBB_UPERR4_COUNTER_SIZE 2\n#define AVR32_USBB_UPERR4_CRC16 4\n#define AVR32_USBB_UPERR4_CRC16_MASK 0x00000010\n#define AVR32_USBB_UPERR4_CRC16_OFFSET 4\n#define AVR32_USBB_UPERR4_CRC16_SIZE 1\n#define AVR32_USBB_UPERR4_DATAPID 1\n#define AVR32_USBB_UPERR4_DATAPID_MASK 0x00000002\n#define AVR32_USBB_UPERR4_DATAPID_OFFSET 1\n#define AVR32_USBB_UPERR4_DATAPID_SIZE 1\n#define AVR32_USBB_UPERR4_DATATGL 0\n#define AVR32_USBB_UPERR4_DATATGL_MASK 0x00000001\n#define AVR32_USBB_UPERR4_DATATGL_OFFSET 0\n#define AVR32_USBB_UPERR4_DATATGL_SIZE 1\n#define AVR32_USBB_UPERR4_PID 2\n#define AVR32_USBB_UPERR4_PID_MASK 0x00000004\n#define AVR32_USBB_UPERR4_PID_OFFSET 2\n#define AVR32_USBB_UPERR4_PID_SIZE 1\n#define AVR32_USBB_UPERR4_TIMEOUT 3\n#define AVR32_USBB_UPERR4_TIMEOUT_MASK 0x00000008\n#define AVR32_USBB_UPERR4_TIMEOUT_OFFSET 3\n#define AVR32_USBB_UPERR4_TIMEOUT_SIZE 1\n#define AVR32_USBB_UPERR5 0x00000694\n#define AVR32_USBB_UPERR5_COUNTER 5\n#define AVR32_USBB_UPERR5_COUNTER_MASK 0x00000060\n#define AVR32_USBB_UPERR5_COUNTER_OFFSET 5\n#define AVR32_USBB_UPERR5_COUNTER_SIZE 2\n#define AVR32_USBB_UPERR5_CRC16 4\n#define AVR32_USBB_UPERR5_CRC16_MASK 0x00000010\n#define AVR32_USBB_UPERR5_CRC16_OFFSET 4\n#define AVR32_USBB_UPERR5_CRC16_SIZE 1\n#define AVR32_USBB_UPERR5_DATAPID 1\n#define AVR32_USBB_UPERR5_DATAPID_MASK 0x00000002\n#define AVR32_USBB_UPERR5_DATAPID_OFFSET 1\n#define AVR32_USBB_UPERR5_DATAPID_SIZE 1\n#define AVR32_USBB_UPERR5_DATATGL 0\n#define AVR32_USBB_UPERR5_DATATGL_MASK 0x00000001\n#define AVR32_USBB_UPERR5_DATATGL_OFFSET 0\n#define AVR32_USBB_UPERR5_DATATGL_SIZE 1\n#define AVR32_USBB_UPERR5_PID 2\n#define AVR32_USBB_UPERR5_PID_MASK 0x00000004\n#define AVR32_USBB_UPERR5_PID_OFFSET 2\n#define AVR32_USBB_UPERR5_PID_SIZE 1\n#define AVR32_USBB_UPERR5_TIMEOUT 3\n#define AVR32_USBB_UPERR5_TIMEOUT_MASK 0x00000008\n#define AVR32_USBB_UPERR5_TIMEOUT_OFFSET 3\n#define AVR32_USBB_UPERR5_TIMEOUT_SIZE 1\n#define AVR32_USBB_UPERR6 0x00000698\n#define AVR32_USBB_UPERR6_COUNTER 5\n#define AVR32_USBB_UPERR6_COUNTER_MASK 0x00000060\n#define AVR32_USBB_UPERR6_COUNTER_OFFSET 5\n#define AVR32_USBB_UPERR6_COUNTER_SIZE 2\n#define AVR32_USBB_UPERR6_CRC16 4\n#define AVR32_USBB_UPERR6_CRC16_MASK 0x00000010\n#define AVR32_USBB_UPERR6_CRC16_OFFSET 4\n#define AVR32_USBB_UPERR6_CRC16_SIZE 1\n#define AVR32_USBB_UPERR6_DATAPID 1\n#define AVR32_USBB_UPERR6_DATAPID_MASK 0x00000002\n#define AVR32_USBB_UPERR6_DATAPID_OFFSET 1\n#define AVR32_USBB_UPERR6_DATAPID_SIZE 1\n#define AVR32_USBB_UPERR6_DATATGL 0\n#define AVR32_USBB_UPERR6_DATATGL_MASK 0x00000001\n#define AVR32_USBB_UPERR6_DATATGL_OFFSET 0\n#define AVR32_USBB_UPERR6_DATATGL_SIZE 1\n#define AVR32_USBB_UPERR6_PID 2\n#define AVR32_USBB_UPERR6_PID_MASK 0x00000004\n#define AVR32_USBB_UPERR6_PID_OFFSET 2\n#define AVR32_USBB_UPERR6_PID_SIZE 1\n#define AVR32_USBB_UPERR6_TIMEOUT 3\n#define AVR32_USBB_UPERR6_TIMEOUT_MASK 0x00000008\n#define AVR32_USBB_UPERR6_TIMEOUT_OFFSET 3\n#define AVR32_USBB_UPERR6_TIMEOUT_SIZE 1\n#define AVR32_USBB_UPINRQ0 0x00000650\n#define AVR32_USBB_UPINRQ0_INMODE 8\n#define AVR32_USBB_UPINRQ0_INMODE_MASK 0x00000100\n#define AVR32_USBB_UPINRQ0_INMODE_OFFSET 8\n#define AVR32_USBB_UPINRQ0_INMODE_SIZE 1\n#define AVR32_USBB_UPINRQ0_INRQ 0\n#define AVR32_USBB_UPINRQ0_INRQ_MASK 0x000000ff\n#define AVR32_USBB_UPINRQ0_INRQ_OFFSET 0\n#define AVR32_USBB_UPINRQ0_INRQ_SIZE 8\n#define AVR32_USBB_UPINRQ1 0x00000654\n#define AVR32_USBB_UPINRQ1_INMODE 8\n#define AVR32_USBB_UPINRQ1_INMODE_MASK 0x00000100\n#define AVR32_USBB_UPINRQ1_INMODE_OFFSET 8\n#define AVR32_USBB_UPINRQ1_INMODE_SIZE 1\n#define AVR32_USBB_UPINRQ1_INRQ 0\n#define AVR32_USBB_UPINRQ1_INRQ_MASK 0x000000ff\n#define AVR32_USBB_UPINRQ1_INRQ_OFFSET 0\n#define AVR32_USBB_UPINRQ1_INRQ_SIZE 8\n#define AVR32_USBB_UPINRQ2 0x00000658\n#define AVR32_USBB_UPINRQ2_INMODE 8\n#define AVR32_USBB_UPINRQ2_INMODE_MASK 0x00000100\n#define AVR32_USBB_UPINRQ2_INMODE_OFFSET 8\n#define AVR32_USBB_UPINRQ2_INMODE_SIZE 1\n#define AVR32_USBB_UPINRQ2_INRQ 0\n#define AVR32_USBB_UPINRQ2_INRQ_MASK 0x000000ff\n#define AVR32_USBB_UPINRQ2_INRQ_OFFSET 0\n#define AVR32_USBB_UPINRQ2_INRQ_SIZE 8\n#define AVR32_USBB_UPINRQ3 0x0000065c\n#define AVR32_USBB_UPINRQ3_INMODE 8\n#define AVR32_USBB_UPINRQ3_INMODE_MASK 0x00000100\n#define AVR32_USBB_UPINRQ3_INMODE_OFFSET 8\n#define AVR32_USBB_UPINRQ3_INMODE_SIZE 1\n#define AVR32_USBB_UPINRQ3_INRQ 0\n#define AVR32_USBB_UPINRQ3_INRQ_MASK 0x000000ff\n#define AVR32_USBB_UPINRQ3_INRQ_OFFSET 0\n#define AVR32_USBB_UPINRQ3_INRQ_SIZE 8\n#define AVR32_USBB_UPINRQ4 0x00000660\n#define AVR32_USBB_UPINRQ4_INMODE 8\n#define AVR32_USBB_UPINRQ4_INMODE_MASK 0x00000100\n#define AVR32_USBB_UPINRQ4_INMODE_OFFSET 8\n#define AVR32_USBB_UPINRQ4_INMODE_SIZE 1\n#define AVR32_USBB_UPINRQ4_INRQ 0\n#define AVR32_USBB_UPINRQ4_INRQ_MASK 0x000000ff\n#define AVR32_USBB_UPINRQ4_INRQ_OFFSET 0\n#define AVR32_USBB_UPINRQ4_INRQ_SIZE 8\n#define AVR32_USBB_UPINRQ5 0x00000664\n#define AVR32_USBB_UPINRQ5_INMODE 8\n#define AVR32_USBB_UPINRQ5_INMODE_MASK 0x00000100\n#define AVR32_USBB_UPINRQ5_INMODE_OFFSET 8\n#define AVR32_USBB_UPINRQ5_INMODE_SIZE 1\n#define AVR32_USBB_UPINRQ5_INRQ 0\n#define AVR32_USBB_UPINRQ5_INRQ_MASK 0x000000ff\n#define AVR32_USBB_UPINRQ5_INRQ_OFFSET 0\n#define AVR32_USBB_UPINRQ5_INRQ_SIZE 8\n#define AVR32_USBB_UPINRQ6 0x00000668\n#define AVR32_USBB_UPINRQ6_INMODE 8\n#define AVR32_USBB_UPINRQ6_INMODE_MASK 0x00000100\n#define AVR32_USBB_UPINRQ6_INMODE_OFFSET 8\n#define AVR32_USBB_UPINRQ6_INMODE_SIZE 1\n#define AVR32_USBB_UPINRQ6_INRQ 0\n#define AVR32_USBB_UPINRQ6_INRQ_MASK 0x000000ff\n#define AVR32_USBB_UPINRQ6_INRQ_OFFSET 0\n#define AVR32_USBB_UPINRQ6_INRQ_SIZE 8\n#define AVR32_USBB_UPRSM 6\n#define AVR32_USBB_UPRSMC 6\n#define AVR32_USBB_UPRSMC_MASK 0x00000040\n#define AVR32_USBB_UPRSMC_OFFSET 6\n#define AVR32_USBB_UPRSMC_SIZE 1\n#define AVR32_USBB_UPRSME 6\n#define AVR32_USBB_UPRSMEC 6\n#define AVR32_USBB_UPRSMEC_MASK 0x00000040\n#define AVR32_USBB_UPRSMEC_OFFSET 6\n#define AVR32_USBB_UPRSMEC_SIZE 1\n#define AVR32_USBB_UPRSMES 6\n#define AVR32_USBB_UPRSMES_MASK 0x00000040\n#define AVR32_USBB_UPRSMES_OFFSET 6\n#define AVR32_USBB_UPRSMES_SIZE 1\n#define AVR32_USBB_UPRSME_MASK 0x00000040\n#define AVR32_USBB_UPRSME_OFFSET 6\n#define AVR32_USBB_UPRSME_SIZE 1\n#define AVR32_USBB_UPRSMS 6\n#define AVR32_USBB_UPRSMS_MASK 0x00000040\n#define AVR32_USBB_UPRSMS_OFFSET 6\n#define AVR32_USBB_UPRSMS_SIZE 1\n#define AVR32_USBB_UPRSM_MASK 0x00000040\n#define AVR32_USBB_UPRSM_OFFSET 6\n#define AVR32_USBB_UPRSM_SIZE 1\n#define AVR32_USBB_UPRST 0x0000041c\n#define AVR32_USBB_UPRST_PEN0 0\n#define AVR32_USBB_UPRST_PEN0_MASK 0x00000001\n#define AVR32_USBB_UPRST_PEN0_OFFSET 0\n#define AVR32_USBB_UPRST_PEN0_SIZE 1\n#define AVR32_USBB_UPRST_PEN1 1\n#define AVR32_USBB_UPRST_PEN1_MASK 0x00000002\n#define AVR32_USBB_UPRST_PEN1_OFFSET 1\n#define AVR32_USBB_UPRST_PEN1_SIZE 1\n#define AVR32_USBB_UPRST_PEN2 2\n#define AVR32_USBB_UPRST_PEN2_MASK 0x00000004\n#define AVR32_USBB_UPRST_PEN2_OFFSET 2\n#define AVR32_USBB_UPRST_PEN2_SIZE 1\n#define AVR32_USBB_UPRST_PEN3 3\n#define AVR32_USBB_UPRST_PEN3_MASK 0x00000008\n#define AVR32_USBB_UPRST_PEN3_OFFSET 3\n#define AVR32_USBB_UPRST_PEN3_SIZE 1\n#define AVR32_USBB_UPRST_PEN4 4\n#define AVR32_USBB_UPRST_PEN4_MASK 0x00000010\n#define AVR32_USBB_UPRST_PEN4_OFFSET 4\n#define AVR32_USBB_UPRST_PEN4_SIZE 1\n#define AVR32_USBB_UPRST_PEN5 5\n#define AVR32_USBB_UPRST_PEN5_MASK 0x00000020\n#define AVR32_USBB_UPRST_PEN5_OFFSET 5\n#define AVR32_USBB_UPRST_PEN5_SIZE 1\n#define AVR32_USBB_UPRST_PEN6 6\n#define AVR32_USBB_UPRST_PEN6_MASK 0x00000040\n#define AVR32_USBB_UPRST_PEN6_OFFSET 6\n#define AVR32_USBB_UPRST_PEN6_SIZE 1\n#define AVR32_USBB_UPRST_PRST0 16\n#define AVR32_USBB_UPRST_PRST0_MASK 0x00010000\n#define AVR32_USBB_UPRST_PRST0_OFFSET 16\n#define AVR32_USBB_UPRST_PRST0_SIZE 1\n#define AVR32_USBB_UPRST_PRST1 17\n#define AVR32_USBB_UPRST_PRST1_MASK 0x00020000\n#define AVR32_USBB_UPRST_PRST1_OFFSET 17\n#define AVR32_USBB_UPRST_PRST1_SIZE 1\n#define AVR32_USBB_UPRST_PRST2 18\n#define AVR32_USBB_UPRST_PRST2_MASK 0x00040000\n#define AVR32_USBB_UPRST_PRST2_OFFSET 18\n#define AVR32_USBB_UPRST_PRST2_SIZE 1\n#define AVR32_USBB_UPRST_PRST3 19\n#define AVR32_USBB_UPRST_PRST3_MASK 0x00080000\n#define AVR32_USBB_UPRST_PRST3_OFFSET 19\n#define AVR32_USBB_UPRST_PRST3_SIZE 1\n#define AVR32_USBB_UPRST_PRST4 20\n#define AVR32_USBB_UPRST_PRST4_MASK 0x00100000\n#define AVR32_USBB_UPRST_PRST4_OFFSET 20\n#define AVR32_USBB_UPRST_PRST4_SIZE 1\n#define AVR32_USBB_UPRST_PRST5 21\n#define AVR32_USBB_UPRST_PRST5_MASK 0x00200000\n#define AVR32_USBB_UPRST_PRST5_OFFSET 21\n#define AVR32_USBB_UPRST_PRST5_SIZE 1\n#define AVR32_USBB_UPRST_PRST6 22\n#define AVR32_USBB_UPRST_PRST6_MASK 0x00400000\n#define AVR32_USBB_UPRST_PRST6_OFFSET 22\n#define AVR32_USBB_UPRST_PRST6_SIZE 1\n#define AVR32_USBB_UPSTA0 0x00000530\n#define AVR32_USBB_UPSTA0CLR 0x00000560\n#define AVR32_USBB_UPSTA0CLR_NAKEDIC 4\n#define AVR32_USBB_UPSTA0CLR_NAKEDIC_MASK 0x00000010\n#define AVR32_USBB_UPSTA0CLR_NAKEDIC_OFFSET 4\n#define AVR32_USBB_UPSTA0CLR_NAKEDIC_SIZE 1\n#define AVR32_USBB_UPSTA0CLR_OVERFIC 5\n#define AVR32_USBB_UPSTA0CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UPSTA0CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UPSTA0CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UPSTA0CLR_RXINIC 0\n#define AVR32_USBB_UPSTA0CLR_RXINIC_MASK 0x00000001\n#define AVR32_USBB_UPSTA0CLR_RXINIC_OFFSET 0\n#define AVR32_USBB_UPSTA0CLR_RXINIC_SIZE 1\n#define AVR32_USBB_UPSTA0CLR_RXSTALLDIC 6\n#define AVR32_USBB_UPSTA0CLR_RXSTALLDIC_MASK 0x00000040\n#define AVR32_USBB_UPSTA0CLR_RXSTALLDIC_OFFSET 6\n#define AVR32_USBB_UPSTA0CLR_RXSTALLDIC_SIZE 1\n#define AVR32_USBB_UPSTA0CLR_SHORTPACKETIC 7\n#define AVR32_USBB_UPSTA0CLR_SHORTPACKETIC_MASK 0x00000080\n#define AVR32_USBB_UPSTA0CLR_SHORTPACKETIC_OFFSET 7\n#define AVR32_USBB_UPSTA0CLR_SHORTPACKETIC_SIZE 1\n#define AVR32_USBB_UPSTA0CLR_TXOUTIC 1\n#define AVR32_USBB_UPSTA0CLR_TXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UPSTA0CLR_TXOUTIC_OFFSET 1\n#define AVR32_USBB_UPSTA0CLR_TXOUTIC_SIZE 1\n#define AVR32_USBB_UPSTA0CLR_TXSTPIC 2\n#define AVR32_USBB_UPSTA0CLR_TXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UPSTA0CLR_TXSTPIC_OFFSET 2\n#define AVR32_USBB_UPSTA0CLR_TXSTPIC_SIZE 1\n#define AVR32_USBB_UPSTA0SET 0x00000590\n#define AVR32_USBB_UPSTA0SET_NAKEDIS 4\n#define AVR32_USBB_UPSTA0SET_NAKEDIS_MASK 0x00000010\n#define AVR32_USBB_UPSTA0SET_NAKEDIS_OFFSET 4\n#define AVR32_USBB_UPSTA0SET_NAKEDIS_SIZE 1\n#define AVR32_USBB_UPSTA0SET_NBUSYBKS 12\n#define AVR32_USBB_UPSTA0SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UPSTA0SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UPSTA0SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UPSTA0SET_OVERFIS 5\n#define AVR32_USBB_UPSTA0SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UPSTA0SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UPSTA0SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UPSTA0SET_PERRIS 3\n#define AVR32_USBB_UPSTA0SET_PERRIS_MASK 0x00000008\n#define AVR32_USBB_UPSTA0SET_PERRIS_OFFSET 3\n#define AVR32_USBB_UPSTA0SET_PERRIS_SIZE 1\n#define AVR32_USBB_UPSTA0SET_RXINIS 0\n#define AVR32_USBB_UPSTA0SET_RXINIS_MASK 0x00000001\n#define AVR32_USBB_UPSTA0SET_RXINIS_OFFSET 0\n#define AVR32_USBB_UPSTA0SET_RXINIS_SIZE 1\n#define AVR32_USBB_UPSTA0SET_RXSTALLDIS 6\n#define AVR32_USBB_UPSTA0SET_RXSTALLDIS_MASK 0x00000040\n#define AVR32_USBB_UPSTA0SET_RXSTALLDIS_OFFSET 6\n#define AVR32_USBB_UPSTA0SET_RXSTALLDIS_SIZE 1\n#define AVR32_USBB_UPSTA0SET_SHORTPACKETIS 7\n#define AVR32_USBB_UPSTA0SET_SHORTPACKETIS_MASK 0x00000080\n#define AVR32_USBB_UPSTA0SET_SHORTPACKETIS_OFFSET 7\n#define AVR32_USBB_UPSTA0SET_SHORTPACKETIS_SIZE 1\n#define AVR32_USBB_UPSTA0SET_TXOUTIS 1\n#define AVR32_USBB_UPSTA0SET_TXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UPSTA0SET_TXOUTIS_OFFSET 1\n#define AVR32_USBB_UPSTA0SET_TXOUTIS_SIZE 1\n#define AVR32_USBB_UPSTA0SET_TXSTPIS 2\n#define AVR32_USBB_UPSTA0SET_TXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UPSTA0SET_TXSTPIS_OFFSET 2\n#define AVR32_USBB_UPSTA0SET_TXSTPIS_SIZE 1\n#define AVR32_USBB_UPSTA0_CFGOK 18\n#define AVR32_USBB_UPSTA0_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UPSTA0_CFGOK_OFFSET 18\n#define AVR32_USBB_UPSTA0_CFGOK_SIZE 1\n#define AVR32_USBB_UPSTA0_CURRBK 14\n#define AVR32_USBB_UPSTA0_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UPSTA0_CURRBK_OFFSET 14\n#define AVR32_USBB_UPSTA0_CURRBK_SIZE 2\n#define AVR32_USBB_UPSTA0_DTSEQ 8\n#define AVR32_USBB_UPSTA0_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UPSTA0_DTSEQ_OFFSET 8\n#define AVR32_USBB_UPSTA0_DTSEQ_SIZE 2\n#define AVR32_USBB_UPSTA0_NAKEDI 4\n#define AVR32_USBB_UPSTA0_NAKEDI_MASK 0x00000010\n#define AVR32_USBB_UPSTA0_NAKEDI_OFFSET 4\n#define AVR32_USBB_UPSTA0_NAKEDI_SIZE 1\n#define AVR32_USBB_UPSTA0_NBUSYBK 12\n#define AVR32_USBB_UPSTA0_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UPSTA0_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UPSTA0_NBUSYBK_SIZE 2\n#define AVR32_USBB_UPSTA0_OVERFI 5\n#define AVR32_USBB_UPSTA0_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UPSTA0_OVERFI_OFFSET 5\n#define AVR32_USBB_UPSTA0_OVERFI_SIZE 1\n#define AVR32_USBB_UPSTA0_PBYCT 20\n#define AVR32_USBB_UPSTA0_PBYCT_MASK 0x7ff00000\n#define AVR32_USBB_UPSTA0_PBYCT_OFFSET 20\n#define AVR32_USBB_UPSTA0_PBYCT_SIZE 11\n#define AVR32_USBB_UPSTA0_PERRI 3\n#define AVR32_USBB_UPSTA0_PERRI_MASK 0x00000008\n#define AVR32_USBB_UPSTA0_PERRI_OFFSET 3\n#define AVR32_USBB_UPSTA0_PERRI_SIZE 1\n#define AVR32_USBB_UPSTA0_RWALL 16\n#define AVR32_USBB_UPSTA0_RWALL_MASK 0x00010000\n#define AVR32_USBB_UPSTA0_RWALL_OFFSET 16\n#define AVR32_USBB_UPSTA0_RWALL_SIZE 1\n#define AVR32_USBB_UPSTA0_RXINI 0\n#define AVR32_USBB_UPSTA0_RXINI_MASK 0x00000001\n#define AVR32_USBB_UPSTA0_RXINI_OFFSET 0\n#define AVR32_USBB_UPSTA0_RXINI_SIZE 1\n#define AVR32_USBB_UPSTA0_RXSTALLDI 6\n#define AVR32_USBB_UPSTA0_RXSTALLDI_MASK 0x00000040\n#define AVR32_USBB_UPSTA0_RXSTALLDI_OFFSET 6\n#define AVR32_USBB_UPSTA0_RXSTALLDI_SIZE 1\n#define AVR32_USBB_UPSTA0_SHORTPACKETI 7\n#define AVR32_USBB_UPSTA0_SHORTPACKETI_MASK 0x00000080\n#define AVR32_USBB_UPSTA0_SHORTPACKETI_OFFSET 7\n#define AVR32_USBB_UPSTA0_SHORTPACKETI_SIZE 1\n#define AVR32_USBB_UPSTA0_TXOUTI 1\n#define AVR32_USBB_UPSTA0_TXOUTI_MASK 0x00000002\n#define AVR32_USBB_UPSTA0_TXOUTI_OFFSET 1\n#define AVR32_USBB_UPSTA0_TXOUTI_SIZE 1\n#define AVR32_USBB_UPSTA0_TXSTPI 2\n#define AVR32_USBB_UPSTA0_TXSTPI_MASK 0x00000004\n#define AVR32_USBB_UPSTA0_TXSTPI_OFFSET 2\n#define AVR32_USBB_UPSTA0_TXSTPI_SIZE 1\n#define AVR32_USBB_UPSTA1 0x00000534\n#define AVR32_USBB_UPSTA1CLR 0x00000564\n#define AVR32_USBB_UPSTA1CLR_NAKEDIC 4\n#define AVR32_USBB_UPSTA1CLR_NAKEDIC_MASK 0x00000010\n#define AVR32_USBB_UPSTA1CLR_NAKEDIC_OFFSET 4\n#define AVR32_USBB_UPSTA1CLR_NAKEDIC_SIZE 1\n#define AVR32_USBB_UPSTA1CLR_OVERFIC 5\n#define AVR32_USBB_UPSTA1CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UPSTA1CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UPSTA1CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UPSTA1CLR_RXINIC 0\n#define AVR32_USBB_UPSTA1CLR_RXINIC_MASK 0x00000001\n#define AVR32_USBB_UPSTA1CLR_RXINIC_OFFSET 0\n#define AVR32_USBB_UPSTA1CLR_RXINIC_SIZE 1\n#define AVR32_USBB_UPSTA1CLR_RXSTALLDIC 6\n#define AVR32_USBB_UPSTA1CLR_RXSTALLDIC_MASK 0x00000040\n#define AVR32_USBB_UPSTA1CLR_RXSTALLDIC_OFFSET 6\n#define AVR32_USBB_UPSTA1CLR_RXSTALLDIC_SIZE 1\n#define AVR32_USBB_UPSTA1CLR_SHORTPACKETIC 7\n#define AVR32_USBB_UPSTA1CLR_SHORTPACKETIC_MASK 0x00000080\n#define AVR32_USBB_UPSTA1CLR_SHORTPACKETIC_OFFSET 7\n#define AVR32_USBB_UPSTA1CLR_SHORTPACKETIC_SIZE 1\n#define AVR32_USBB_UPSTA1CLR_TXOUTIC 1\n#define AVR32_USBB_UPSTA1CLR_TXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UPSTA1CLR_TXOUTIC_OFFSET 1\n#define AVR32_USBB_UPSTA1CLR_TXOUTIC_SIZE 1\n#define AVR32_USBB_UPSTA1CLR_TXSTPIC 2\n#define AVR32_USBB_UPSTA1CLR_TXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UPSTA1CLR_TXSTPIC_OFFSET 2\n#define AVR32_USBB_UPSTA1CLR_TXSTPIC_SIZE 1\n#define AVR32_USBB_UPSTA1SET 0x00000594\n#define AVR32_USBB_UPSTA1SET_NAKEDIS 4\n#define AVR32_USBB_UPSTA1SET_NAKEDIS_MASK 0x00000010\n#define AVR32_USBB_UPSTA1SET_NAKEDIS_OFFSET 4\n#define AVR32_USBB_UPSTA1SET_NAKEDIS_SIZE 1\n#define AVR32_USBB_UPSTA1SET_NBUSYBKS 12\n#define AVR32_USBB_UPSTA1SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UPSTA1SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UPSTA1SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UPSTA1SET_OVERFIS 5\n#define AVR32_USBB_UPSTA1SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UPSTA1SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UPSTA1SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UPSTA1SET_PERRIS 3\n#define AVR32_USBB_UPSTA1SET_PERRIS_MASK 0x00000008\n#define AVR32_USBB_UPSTA1SET_PERRIS_OFFSET 3\n#define AVR32_USBB_UPSTA1SET_PERRIS_SIZE 1\n#define AVR32_USBB_UPSTA1SET_RXINIS 0\n#define AVR32_USBB_UPSTA1SET_RXINIS_MASK 0x00000001\n#define AVR32_USBB_UPSTA1SET_RXINIS_OFFSET 0\n#define AVR32_USBB_UPSTA1SET_RXINIS_SIZE 1\n#define AVR32_USBB_UPSTA1SET_RXSTALLDIS 6\n#define AVR32_USBB_UPSTA1SET_RXSTALLDIS_MASK 0x00000040\n#define AVR32_USBB_UPSTA1SET_RXSTALLDIS_OFFSET 6\n#define AVR32_USBB_UPSTA1SET_RXSTALLDIS_SIZE 1\n#define AVR32_USBB_UPSTA1SET_SHORTPACKETIS 7\n#define AVR32_USBB_UPSTA1SET_SHORTPACKETIS_MASK 0x00000080\n#define AVR32_USBB_UPSTA1SET_SHORTPACKETIS_OFFSET 7\n#define AVR32_USBB_UPSTA1SET_SHORTPACKETIS_SIZE 1\n#define AVR32_USBB_UPSTA1SET_TXOUTIS 1\n#define AVR32_USBB_UPSTA1SET_TXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UPSTA1SET_TXOUTIS_OFFSET 1\n#define AVR32_USBB_UPSTA1SET_TXOUTIS_SIZE 1\n#define AVR32_USBB_UPSTA1SET_TXSTPIS 2\n#define AVR32_USBB_UPSTA1SET_TXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UPSTA1SET_TXSTPIS_OFFSET 2\n#define AVR32_USBB_UPSTA1SET_TXSTPIS_SIZE 1\n#define AVR32_USBB_UPSTA1_CFGOK 18\n#define AVR32_USBB_UPSTA1_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UPSTA1_CFGOK_OFFSET 18\n#define AVR32_USBB_UPSTA1_CFGOK_SIZE 1\n#define AVR32_USBB_UPSTA1_CURRBK 14\n#define AVR32_USBB_UPSTA1_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UPSTA1_CURRBK_OFFSET 14\n#define AVR32_USBB_UPSTA1_CURRBK_SIZE 2\n#define AVR32_USBB_UPSTA1_DTSEQ 8\n#define AVR32_USBB_UPSTA1_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UPSTA1_DTSEQ_OFFSET 8\n#define AVR32_USBB_UPSTA1_DTSEQ_SIZE 2\n#define AVR32_USBB_UPSTA1_NAKEDI 4\n#define AVR32_USBB_UPSTA1_NAKEDI_MASK 0x00000010\n#define AVR32_USBB_UPSTA1_NAKEDI_OFFSET 4\n#define AVR32_USBB_UPSTA1_NAKEDI_SIZE 1\n#define AVR32_USBB_UPSTA1_NBUSYBK 12\n#define AVR32_USBB_UPSTA1_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UPSTA1_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UPSTA1_NBUSYBK_SIZE 2\n#define AVR32_USBB_UPSTA1_OVERFI 5\n#define AVR32_USBB_UPSTA1_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UPSTA1_OVERFI_OFFSET 5\n#define AVR32_USBB_UPSTA1_OVERFI_SIZE 1\n#define AVR32_USBB_UPSTA1_PBYCT 20\n#define AVR32_USBB_UPSTA1_PBYCT_MASK 0x7ff00000\n#define AVR32_USBB_UPSTA1_PBYCT_OFFSET 20\n#define AVR32_USBB_UPSTA1_PBYCT_SIZE 11\n#define AVR32_USBB_UPSTA1_PERRI 3\n#define AVR32_USBB_UPSTA1_PERRI_MASK 0x00000008\n#define AVR32_USBB_UPSTA1_PERRI_OFFSET 3\n#define AVR32_USBB_UPSTA1_PERRI_SIZE 1\n#define AVR32_USBB_UPSTA1_RWALL 16\n#define AVR32_USBB_UPSTA1_RWALL_MASK 0x00010000\n#define AVR32_USBB_UPSTA1_RWALL_OFFSET 16\n#define AVR32_USBB_UPSTA1_RWALL_SIZE 1\n#define AVR32_USBB_UPSTA1_RXINI 0\n#define AVR32_USBB_UPSTA1_RXINI_MASK 0x00000001\n#define AVR32_USBB_UPSTA1_RXINI_OFFSET 0\n#define AVR32_USBB_UPSTA1_RXINI_SIZE 1\n#define AVR32_USBB_UPSTA1_RXSTALLDI 6\n#define AVR32_USBB_UPSTA1_RXSTALLDI_MASK 0x00000040\n#define AVR32_USBB_UPSTA1_RXSTALLDI_OFFSET 6\n#define AVR32_USBB_UPSTA1_RXSTALLDI_SIZE 1\n#define AVR32_USBB_UPSTA1_SHORTPACKETI 7\n#define AVR32_USBB_UPSTA1_SHORTPACKETI_MASK 0x00000080\n#define AVR32_USBB_UPSTA1_SHORTPACKETI_OFFSET 7\n#define AVR32_USBB_UPSTA1_SHORTPACKETI_SIZE 1\n#define AVR32_USBB_UPSTA1_TXOUTI 1\n#define AVR32_USBB_UPSTA1_TXOUTI_MASK 0x00000002\n#define AVR32_USBB_UPSTA1_TXOUTI_OFFSET 1\n#define AVR32_USBB_UPSTA1_TXOUTI_SIZE 1\n#define AVR32_USBB_UPSTA1_TXSTPI 2\n#define AVR32_USBB_UPSTA1_TXSTPI_MASK 0x00000004\n#define AVR32_USBB_UPSTA1_TXSTPI_OFFSET 2\n#define AVR32_USBB_UPSTA1_TXSTPI_SIZE 1\n#define AVR32_USBB_UPSTA2 0x00000538\n#define AVR32_USBB_UPSTA2CLR 0x00000568\n#define AVR32_USBB_UPSTA2CLR_NAKEDIC 4\n#define AVR32_USBB_UPSTA2CLR_NAKEDIC_MASK 0x00000010\n#define AVR32_USBB_UPSTA2CLR_NAKEDIC_OFFSET 4\n#define AVR32_USBB_UPSTA2CLR_NAKEDIC_SIZE 1\n#define AVR32_USBB_UPSTA2CLR_OVERFIC 5\n#define AVR32_USBB_UPSTA2CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UPSTA2CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UPSTA2CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UPSTA2CLR_RXINIC 0\n#define AVR32_USBB_UPSTA2CLR_RXINIC_MASK 0x00000001\n#define AVR32_USBB_UPSTA2CLR_RXINIC_OFFSET 0\n#define AVR32_USBB_UPSTA2CLR_RXINIC_SIZE 1\n#define AVR32_USBB_UPSTA2CLR_RXSTALLDIC 6\n#define AVR32_USBB_UPSTA2CLR_RXSTALLDIC_MASK 0x00000040\n#define AVR32_USBB_UPSTA2CLR_RXSTALLDIC_OFFSET 6\n#define AVR32_USBB_UPSTA2CLR_RXSTALLDIC_SIZE 1\n#define AVR32_USBB_UPSTA2CLR_SHORTPACKETIC 7\n#define AVR32_USBB_UPSTA2CLR_SHORTPACKETIC_MASK 0x00000080\n#define AVR32_USBB_UPSTA2CLR_SHORTPACKETIC_OFFSET 7\n#define AVR32_USBB_UPSTA2CLR_SHORTPACKETIC_SIZE 1\n#define AVR32_USBB_UPSTA2CLR_TXOUTIC 1\n#define AVR32_USBB_UPSTA2CLR_TXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UPSTA2CLR_TXOUTIC_OFFSET 1\n#define AVR32_USBB_UPSTA2CLR_TXOUTIC_SIZE 1\n#define AVR32_USBB_UPSTA2CLR_TXSTPIC 2\n#define AVR32_USBB_UPSTA2CLR_TXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UPSTA2CLR_TXSTPIC_OFFSET 2\n#define AVR32_USBB_UPSTA2CLR_TXSTPIC_SIZE 1\n#define AVR32_USBB_UPSTA2SET 0x00000598\n#define AVR32_USBB_UPSTA2SET_NAKEDIS 4\n#define AVR32_USBB_UPSTA2SET_NAKEDIS_MASK 0x00000010\n#define AVR32_USBB_UPSTA2SET_NAKEDIS_OFFSET 4\n#define AVR32_USBB_UPSTA2SET_NAKEDIS_SIZE 1\n#define AVR32_USBB_UPSTA2SET_NBUSYBKS 12\n#define AVR32_USBB_UPSTA2SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UPSTA2SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UPSTA2SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UPSTA2SET_OVERFIS 5\n#define AVR32_USBB_UPSTA2SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UPSTA2SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UPSTA2SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UPSTA2SET_PERRIS 3\n#define AVR32_USBB_UPSTA2SET_PERRIS_MASK 0x00000008\n#define AVR32_USBB_UPSTA2SET_PERRIS_OFFSET 3\n#define AVR32_USBB_UPSTA2SET_PERRIS_SIZE 1\n#define AVR32_USBB_UPSTA2SET_RXINIS 0\n#define AVR32_USBB_UPSTA2SET_RXINIS_MASK 0x00000001\n#define AVR32_USBB_UPSTA2SET_RXINIS_OFFSET 0\n#define AVR32_USBB_UPSTA2SET_RXINIS_SIZE 1\n#define AVR32_USBB_UPSTA2SET_RXSTALLDIS 6\n#define AVR32_USBB_UPSTA2SET_RXSTALLDIS_MASK 0x00000040\n#define AVR32_USBB_UPSTA2SET_RXSTALLDIS_OFFSET 6\n#define AVR32_USBB_UPSTA2SET_RXSTALLDIS_SIZE 1\n#define AVR32_USBB_UPSTA2SET_SHORTPACKETIS 7\n#define AVR32_USBB_UPSTA2SET_SHORTPACKETIS_MASK 0x00000080\n#define AVR32_USBB_UPSTA2SET_SHORTPACKETIS_OFFSET 7\n#define AVR32_USBB_UPSTA2SET_SHORTPACKETIS_SIZE 1\n#define AVR32_USBB_UPSTA2SET_TXOUTIS 1\n#define AVR32_USBB_UPSTA2SET_TXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UPSTA2SET_TXOUTIS_OFFSET 1\n#define AVR32_USBB_UPSTA2SET_TXOUTIS_SIZE 1\n#define AVR32_USBB_UPSTA2SET_TXSTPIS 2\n#define AVR32_USBB_UPSTA2SET_TXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UPSTA2SET_TXSTPIS_OFFSET 2\n#define AVR32_USBB_UPSTA2SET_TXSTPIS_SIZE 1\n#define AVR32_USBB_UPSTA2_CFGOK 18\n#define AVR32_USBB_UPSTA2_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UPSTA2_CFGOK_OFFSET 18\n#define AVR32_USBB_UPSTA2_CFGOK_SIZE 1\n#define AVR32_USBB_UPSTA2_CURRBK 14\n#define AVR32_USBB_UPSTA2_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UPSTA2_CURRBK_OFFSET 14\n#define AVR32_USBB_UPSTA2_CURRBK_SIZE 2\n#define AVR32_USBB_UPSTA2_DTSEQ 8\n#define AVR32_USBB_UPSTA2_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UPSTA2_DTSEQ_OFFSET 8\n#define AVR32_USBB_UPSTA2_DTSEQ_SIZE 2\n#define AVR32_USBB_UPSTA2_NAKEDI 4\n#define AVR32_USBB_UPSTA2_NAKEDI_MASK 0x00000010\n#define AVR32_USBB_UPSTA2_NAKEDI_OFFSET 4\n#define AVR32_USBB_UPSTA2_NAKEDI_SIZE 1\n#define AVR32_USBB_UPSTA2_NBUSYBK 12\n#define AVR32_USBB_UPSTA2_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UPSTA2_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UPSTA2_NBUSYBK_SIZE 2\n#define AVR32_USBB_UPSTA2_OVERFI 5\n#define AVR32_USBB_UPSTA2_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UPSTA2_OVERFI_OFFSET 5\n#define AVR32_USBB_UPSTA2_OVERFI_SIZE 1\n#define AVR32_USBB_UPSTA2_PBYCT 20\n#define AVR32_USBB_UPSTA2_PBYCT_MASK 0x7ff00000\n#define AVR32_USBB_UPSTA2_PBYCT_OFFSET 20\n#define AVR32_USBB_UPSTA2_PBYCT_SIZE 11\n#define AVR32_USBB_UPSTA2_PERRI 3\n#define AVR32_USBB_UPSTA2_PERRI_MASK 0x00000008\n#define AVR32_USBB_UPSTA2_PERRI_OFFSET 3\n#define AVR32_USBB_UPSTA2_PERRI_SIZE 1\n#define AVR32_USBB_UPSTA2_RWALL 16\n#define AVR32_USBB_UPSTA2_RWALL_MASK 0x00010000\n#define AVR32_USBB_UPSTA2_RWALL_OFFSET 16\n#define AVR32_USBB_UPSTA2_RWALL_SIZE 1\n#define AVR32_USBB_UPSTA2_RXINI 0\n#define AVR32_USBB_UPSTA2_RXINI_MASK 0x00000001\n#define AVR32_USBB_UPSTA2_RXINI_OFFSET 0\n#define AVR32_USBB_UPSTA2_RXINI_SIZE 1\n#define AVR32_USBB_UPSTA2_RXSTALLDI 6\n#define AVR32_USBB_UPSTA2_RXSTALLDI_MASK 0x00000040\n#define AVR32_USBB_UPSTA2_RXSTALLDI_OFFSET 6\n#define AVR32_USBB_UPSTA2_RXSTALLDI_SIZE 1\n#define AVR32_USBB_UPSTA2_SHORTPACKETI 7\n#define AVR32_USBB_UPSTA2_SHORTPACKETI_MASK 0x00000080\n#define AVR32_USBB_UPSTA2_SHORTPACKETI_OFFSET 7\n#define AVR32_USBB_UPSTA2_SHORTPACKETI_SIZE 1\n#define AVR32_USBB_UPSTA2_TXOUTI 1\n#define AVR32_USBB_UPSTA2_TXOUTI_MASK 0x00000002\n#define AVR32_USBB_UPSTA2_TXOUTI_OFFSET 1\n#define AVR32_USBB_UPSTA2_TXOUTI_SIZE 1\n#define AVR32_USBB_UPSTA2_TXSTPI 2\n#define AVR32_USBB_UPSTA2_TXSTPI_MASK 0x00000004\n#define AVR32_USBB_UPSTA2_TXSTPI_OFFSET 2\n#define AVR32_USBB_UPSTA2_TXSTPI_SIZE 1\n#define AVR32_USBB_UPSTA3 0x0000053c\n#define AVR32_USBB_UPSTA3CLR 0x0000056c\n#define AVR32_USBB_UPSTA3CLR_NAKEDIC 4\n#define AVR32_USBB_UPSTA3CLR_NAKEDIC_MASK 0x00000010\n#define AVR32_USBB_UPSTA3CLR_NAKEDIC_OFFSET 4\n#define AVR32_USBB_UPSTA3CLR_NAKEDIC_SIZE 1\n#define AVR32_USBB_UPSTA3CLR_OVERFIC 5\n#define AVR32_USBB_UPSTA3CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UPSTA3CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UPSTA3CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UPSTA3CLR_RXINIC 0\n#define AVR32_USBB_UPSTA3CLR_RXINIC_MASK 0x00000001\n#define AVR32_USBB_UPSTA3CLR_RXINIC_OFFSET 0\n#define AVR32_USBB_UPSTA3CLR_RXINIC_SIZE 1\n#define AVR32_USBB_UPSTA3CLR_RXSTALLDIC 6\n#define AVR32_USBB_UPSTA3CLR_RXSTALLDIC_MASK 0x00000040\n#define AVR32_USBB_UPSTA3CLR_RXSTALLDIC_OFFSET 6\n#define AVR32_USBB_UPSTA3CLR_RXSTALLDIC_SIZE 1\n#define AVR32_USBB_UPSTA3CLR_SHORTPACKETIC 7\n#define AVR32_USBB_UPSTA3CLR_SHORTPACKETIC_MASK 0x00000080\n#define AVR32_USBB_UPSTA3CLR_SHORTPACKETIC_OFFSET 7\n#define AVR32_USBB_UPSTA3CLR_SHORTPACKETIC_SIZE 1\n#define AVR32_USBB_UPSTA3CLR_TXOUTIC 1\n#define AVR32_USBB_UPSTA3CLR_TXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UPSTA3CLR_TXOUTIC_OFFSET 1\n#define AVR32_USBB_UPSTA3CLR_TXOUTIC_SIZE 1\n#define AVR32_USBB_UPSTA3CLR_TXSTPIC 2\n#define AVR32_USBB_UPSTA3CLR_TXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UPSTA3CLR_TXSTPIC_OFFSET 2\n#define AVR32_USBB_UPSTA3CLR_TXSTPIC_SIZE 1\n#define AVR32_USBB_UPSTA3SET 0x0000059c\n#define AVR32_USBB_UPSTA3SET_NAKEDIS 4\n#define AVR32_USBB_UPSTA3SET_NAKEDIS_MASK 0x00000010\n#define AVR32_USBB_UPSTA3SET_NAKEDIS_OFFSET 4\n#define AVR32_USBB_UPSTA3SET_NAKEDIS_SIZE 1\n#define AVR32_USBB_UPSTA3SET_NBUSYBKS 12\n#define AVR32_USBB_UPSTA3SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UPSTA3SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UPSTA3SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UPSTA3SET_OVERFIS 5\n#define AVR32_USBB_UPSTA3SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UPSTA3SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UPSTA3SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UPSTA3SET_PERRIS 3\n#define AVR32_USBB_UPSTA3SET_PERRIS_MASK 0x00000008\n#define AVR32_USBB_UPSTA3SET_PERRIS_OFFSET 3\n#define AVR32_USBB_UPSTA3SET_PERRIS_SIZE 1\n#define AVR32_USBB_UPSTA3SET_RXINIS 0\n#define AVR32_USBB_UPSTA3SET_RXINIS_MASK 0x00000001\n#define AVR32_USBB_UPSTA3SET_RXINIS_OFFSET 0\n#define AVR32_USBB_UPSTA3SET_RXINIS_SIZE 1\n#define AVR32_USBB_UPSTA3SET_RXSTALLDIS 6\n#define AVR32_USBB_UPSTA3SET_RXSTALLDIS_MASK 0x00000040\n#define AVR32_USBB_UPSTA3SET_RXSTALLDIS_OFFSET 6\n#define AVR32_USBB_UPSTA3SET_RXSTALLDIS_SIZE 1\n#define AVR32_USBB_UPSTA3SET_SHORTPACKETIS 7\n#define AVR32_USBB_UPSTA3SET_SHORTPACKETIS_MASK 0x00000080\n#define AVR32_USBB_UPSTA3SET_SHORTPACKETIS_OFFSET 7\n#define AVR32_USBB_UPSTA3SET_SHORTPACKETIS_SIZE 1\n#define AVR32_USBB_UPSTA3SET_TXOUTIS 1\n#define AVR32_USBB_UPSTA3SET_TXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UPSTA3SET_TXOUTIS_OFFSET 1\n#define AVR32_USBB_UPSTA3SET_TXOUTIS_SIZE 1\n#define AVR32_USBB_UPSTA3SET_TXSTPIS 2\n#define AVR32_USBB_UPSTA3SET_TXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UPSTA3SET_TXSTPIS_OFFSET 2\n#define AVR32_USBB_UPSTA3SET_TXSTPIS_SIZE 1\n#define AVR32_USBB_UPSTA3_CFGOK 18\n#define AVR32_USBB_UPSTA3_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UPSTA3_CFGOK_OFFSET 18\n#define AVR32_USBB_UPSTA3_CFGOK_SIZE 1\n#define AVR32_USBB_UPSTA3_CURRBK 14\n#define AVR32_USBB_UPSTA3_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UPSTA3_CURRBK_OFFSET 14\n#define AVR32_USBB_UPSTA3_CURRBK_SIZE 2\n#define AVR32_USBB_UPSTA3_DTSEQ 8\n#define AVR32_USBB_UPSTA3_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UPSTA3_DTSEQ_OFFSET 8\n#define AVR32_USBB_UPSTA3_DTSEQ_SIZE 2\n#define AVR32_USBB_UPSTA3_NAKEDI 4\n#define AVR32_USBB_UPSTA3_NAKEDI_MASK 0x00000010\n#define AVR32_USBB_UPSTA3_NAKEDI_OFFSET 4\n#define AVR32_USBB_UPSTA3_NAKEDI_SIZE 1\n#define AVR32_USBB_UPSTA3_NBUSYBK 12\n#define AVR32_USBB_UPSTA3_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UPSTA3_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UPSTA3_NBUSYBK_SIZE 2\n#define AVR32_USBB_UPSTA3_OVERFI 5\n#define AVR32_USBB_UPSTA3_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UPSTA3_OVERFI_OFFSET 5\n#define AVR32_USBB_UPSTA3_OVERFI_SIZE 1\n#define AVR32_USBB_UPSTA3_PBYCT 20\n#define AVR32_USBB_UPSTA3_PBYCT_MASK 0x7ff00000\n#define AVR32_USBB_UPSTA3_PBYCT_OFFSET 20\n#define AVR32_USBB_UPSTA3_PBYCT_SIZE 11\n#define AVR32_USBB_UPSTA3_PERRI 3\n#define AVR32_USBB_UPSTA3_PERRI_MASK 0x00000008\n#define AVR32_USBB_UPSTA3_PERRI_OFFSET 3\n#define AVR32_USBB_UPSTA3_PERRI_SIZE 1\n#define AVR32_USBB_UPSTA3_RWALL 16\n#define AVR32_USBB_UPSTA3_RWALL_MASK 0x00010000\n#define AVR32_USBB_UPSTA3_RWALL_OFFSET 16\n#define AVR32_USBB_UPSTA3_RWALL_SIZE 1\n#define AVR32_USBB_UPSTA3_RXINI 0\n#define AVR32_USBB_UPSTA3_RXINI_MASK 0x00000001\n#define AVR32_USBB_UPSTA3_RXINI_OFFSET 0\n#define AVR32_USBB_UPSTA3_RXINI_SIZE 1\n#define AVR32_USBB_UPSTA3_RXSTALLDI 6\n#define AVR32_USBB_UPSTA3_RXSTALLDI_MASK 0x00000040\n#define AVR32_USBB_UPSTA3_RXSTALLDI_OFFSET 6\n#define AVR32_USBB_UPSTA3_RXSTALLDI_SIZE 1\n#define AVR32_USBB_UPSTA3_SHORTPACKETI 7\n#define AVR32_USBB_UPSTA3_SHORTPACKETI_MASK 0x00000080\n#define AVR32_USBB_UPSTA3_SHORTPACKETI_OFFSET 7\n#define AVR32_USBB_UPSTA3_SHORTPACKETI_SIZE 1\n#define AVR32_USBB_UPSTA3_TXOUTI 1\n#define AVR32_USBB_UPSTA3_TXOUTI_MASK 0x00000002\n#define AVR32_USBB_UPSTA3_TXOUTI_OFFSET 1\n#define AVR32_USBB_UPSTA3_TXOUTI_SIZE 1\n#define AVR32_USBB_UPSTA3_TXSTPI 2\n#define AVR32_USBB_UPSTA3_TXSTPI_MASK 0x00000004\n#define AVR32_USBB_UPSTA3_TXSTPI_OFFSET 2\n#define AVR32_USBB_UPSTA3_TXSTPI_SIZE 1\n#define AVR32_USBB_UPSTA4 0x00000540\n#define AVR32_USBB_UPSTA4CLR 0x00000570\n#define AVR32_USBB_UPSTA4CLR_NAKEDIC 4\n#define AVR32_USBB_UPSTA4CLR_NAKEDIC_MASK 0x00000010\n#define AVR32_USBB_UPSTA4CLR_NAKEDIC_OFFSET 4\n#define AVR32_USBB_UPSTA4CLR_NAKEDIC_SIZE 1\n#define AVR32_USBB_UPSTA4CLR_OVERFIC 5\n#define AVR32_USBB_UPSTA4CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UPSTA4CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UPSTA4CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UPSTA4CLR_RXINIC 0\n#define AVR32_USBB_UPSTA4CLR_RXINIC_MASK 0x00000001\n#define AVR32_USBB_UPSTA4CLR_RXINIC_OFFSET 0\n#define AVR32_USBB_UPSTA4CLR_RXINIC_SIZE 1\n#define AVR32_USBB_UPSTA4CLR_RXSTALLDIC 6\n#define AVR32_USBB_UPSTA4CLR_RXSTALLDIC_MASK 0x00000040\n#define AVR32_USBB_UPSTA4CLR_RXSTALLDIC_OFFSET 6\n#define AVR32_USBB_UPSTA4CLR_RXSTALLDIC_SIZE 1\n#define AVR32_USBB_UPSTA4CLR_SHORTPACKETIC 7\n#define AVR32_USBB_UPSTA4CLR_SHORTPACKETIC_MASK 0x00000080\n#define AVR32_USBB_UPSTA4CLR_SHORTPACKETIC_OFFSET 7\n#define AVR32_USBB_UPSTA4CLR_SHORTPACKETIC_SIZE 1\n#define AVR32_USBB_UPSTA4CLR_TXOUTIC 1\n#define AVR32_USBB_UPSTA4CLR_TXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UPSTA4CLR_TXOUTIC_OFFSET 1\n#define AVR32_USBB_UPSTA4CLR_TXOUTIC_SIZE 1\n#define AVR32_USBB_UPSTA4CLR_TXSTPIC 2\n#define AVR32_USBB_UPSTA4CLR_TXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UPSTA4CLR_TXSTPIC_OFFSET 2\n#define AVR32_USBB_UPSTA4CLR_TXSTPIC_SIZE 1\n#define AVR32_USBB_UPSTA4SET 0x000005a0\n#define AVR32_USBB_UPSTA4SET_NAKEDIS 4\n#define AVR32_USBB_UPSTA4SET_NAKEDIS_MASK 0x00000010\n#define AVR32_USBB_UPSTA4SET_NAKEDIS_OFFSET 4\n#define AVR32_USBB_UPSTA4SET_NAKEDIS_SIZE 1\n#define AVR32_USBB_UPSTA4SET_NBUSYBKS 12\n#define AVR32_USBB_UPSTA4SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UPSTA4SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UPSTA4SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UPSTA4SET_OVERFIS 5\n#define AVR32_USBB_UPSTA4SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UPSTA4SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UPSTA4SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UPSTA4SET_PERRIS 3\n#define AVR32_USBB_UPSTA4SET_PERRIS_MASK 0x00000008\n#define AVR32_USBB_UPSTA4SET_PERRIS_OFFSET 3\n#define AVR32_USBB_UPSTA4SET_PERRIS_SIZE 1\n#define AVR32_USBB_UPSTA4SET_RXINIS 0\n#define AVR32_USBB_UPSTA4SET_RXINIS_MASK 0x00000001\n#define AVR32_USBB_UPSTA4SET_RXINIS_OFFSET 0\n#define AVR32_USBB_UPSTA4SET_RXINIS_SIZE 1\n#define AVR32_USBB_UPSTA4SET_RXSTALLDIS 6\n#define AVR32_USBB_UPSTA4SET_RXSTALLDIS_MASK 0x00000040\n#define AVR32_USBB_UPSTA4SET_RXSTALLDIS_OFFSET 6\n#define AVR32_USBB_UPSTA4SET_RXSTALLDIS_SIZE 1\n#define AVR32_USBB_UPSTA4SET_SHORTPACKETIS 7\n#define AVR32_USBB_UPSTA4SET_SHORTPACKETIS_MASK 0x00000080\n#define AVR32_USBB_UPSTA4SET_SHORTPACKETIS_OFFSET 7\n#define AVR32_USBB_UPSTA4SET_SHORTPACKETIS_SIZE 1\n#define AVR32_USBB_UPSTA4SET_TXOUTIS 1\n#define AVR32_USBB_UPSTA4SET_TXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UPSTA4SET_TXOUTIS_OFFSET 1\n#define AVR32_USBB_UPSTA4SET_TXOUTIS_SIZE 1\n#define AVR32_USBB_UPSTA4SET_TXSTPIS 2\n#define AVR32_USBB_UPSTA4SET_TXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UPSTA4SET_TXSTPIS_OFFSET 2\n#define AVR32_USBB_UPSTA4SET_TXSTPIS_SIZE 1\n#define AVR32_USBB_UPSTA4_CFGOK 18\n#define AVR32_USBB_UPSTA4_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UPSTA4_CFGOK_OFFSET 18\n#define AVR32_USBB_UPSTA4_CFGOK_SIZE 1\n#define AVR32_USBB_UPSTA4_CURRBK 14\n#define AVR32_USBB_UPSTA4_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UPSTA4_CURRBK_OFFSET 14\n#define AVR32_USBB_UPSTA4_CURRBK_SIZE 2\n#define AVR32_USBB_UPSTA4_DTSEQ 8\n#define AVR32_USBB_UPSTA4_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UPSTA4_DTSEQ_OFFSET 8\n#define AVR32_USBB_UPSTA4_DTSEQ_SIZE 2\n#define AVR32_USBB_UPSTA4_NAKEDI 4\n#define AVR32_USBB_UPSTA4_NAKEDI_MASK 0x00000010\n#define AVR32_USBB_UPSTA4_NAKEDI_OFFSET 4\n#define AVR32_USBB_UPSTA4_NAKEDI_SIZE 1\n#define AVR32_USBB_UPSTA4_NBUSYBK 12\n#define AVR32_USBB_UPSTA4_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UPSTA4_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UPSTA4_NBUSYBK_SIZE 2\n#define AVR32_USBB_UPSTA4_OVERFI 5\n#define AVR32_USBB_UPSTA4_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UPSTA4_OVERFI_OFFSET 5\n#define AVR32_USBB_UPSTA4_OVERFI_SIZE 1\n#define AVR32_USBB_UPSTA4_PBYCT 20\n#define AVR32_USBB_UPSTA4_PBYCT_MASK 0x7ff00000\n#define AVR32_USBB_UPSTA4_PBYCT_OFFSET 20\n#define AVR32_USBB_UPSTA4_PBYCT_SIZE 11\n#define AVR32_USBB_UPSTA4_PERRI 3\n#define AVR32_USBB_UPSTA4_PERRI_MASK 0x00000008\n#define AVR32_USBB_UPSTA4_PERRI_OFFSET 3\n#define AVR32_USBB_UPSTA4_PERRI_SIZE 1\n#define AVR32_USBB_UPSTA4_RWALL 16\n#define AVR32_USBB_UPSTA4_RWALL_MASK 0x00010000\n#define AVR32_USBB_UPSTA4_RWALL_OFFSET 16\n#define AVR32_USBB_UPSTA4_RWALL_SIZE 1\n#define AVR32_USBB_UPSTA4_RXINI 0\n#define AVR32_USBB_UPSTA4_RXINI_MASK 0x00000001\n#define AVR32_USBB_UPSTA4_RXINI_OFFSET 0\n#define AVR32_USBB_UPSTA4_RXINI_SIZE 1\n#define AVR32_USBB_UPSTA4_RXSTALLDI 6\n#define AVR32_USBB_UPSTA4_RXSTALLDI_MASK 0x00000040\n#define AVR32_USBB_UPSTA4_RXSTALLDI_OFFSET 6\n#define AVR32_USBB_UPSTA4_RXSTALLDI_SIZE 1\n#define AVR32_USBB_UPSTA4_SHORTPACKETI 7\n#define AVR32_USBB_UPSTA4_SHORTPACKETI_MASK 0x00000080\n#define AVR32_USBB_UPSTA4_SHORTPACKETI_OFFSET 7\n#define AVR32_USBB_UPSTA4_SHORTPACKETI_SIZE 1\n#define AVR32_USBB_UPSTA4_TXOUTI 1\n#define AVR32_USBB_UPSTA4_TXOUTI_MASK 0x00000002\n#define AVR32_USBB_UPSTA4_TXOUTI_OFFSET 1\n#define AVR32_USBB_UPSTA4_TXOUTI_SIZE 1\n#define AVR32_USBB_UPSTA4_TXSTPI 2\n#define AVR32_USBB_UPSTA4_TXSTPI_MASK 0x00000004\n#define AVR32_USBB_UPSTA4_TXSTPI_OFFSET 2\n#define AVR32_USBB_UPSTA4_TXSTPI_SIZE 1\n#define AVR32_USBB_UPSTA5 0x00000544\n#define AVR32_USBB_UPSTA5CLR 0x00000574\n#define AVR32_USBB_UPSTA5CLR_NAKEDIC 4\n#define AVR32_USBB_UPSTA5CLR_NAKEDIC_MASK 0x00000010\n#define AVR32_USBB_UPSTA5CLR_NAKEDIC_OFFSET 4\n#define AVR32_USBB_UPSTA5CLR_NAKEDIC_SIZE 1\n#define AVR32_USBB_UPSTA5CLR_OVERFIC 5\n#define AVR32_USBB_UPSTA5CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UPSTA5CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UPSTA5CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UPSTA5CLR_RXINIC 0\n#define AVR32_USBB_UPSTA5CLR_RXINIC_MASK 0x00000001\n#define AVR32_USBB_UPSTA5CLR_RXINIC_OFFSET 0\n#define AVR32_USBB_UPSTA5CLR_RXINIC_SIZE 1\n#define AVR32_USBB_UPSTA5CLR_RXSTALLDIC 6\n#define AVR32_USBB_UPSTA5CLR_RXSTALLDIC_MASK 0x00000040\n#define AVR32_USBB_UPSTA5CLR_RXSTALLDIC_OFFSET 6\n#define AVR32_USBB_UPSTA5CLR_RXSTALLDIC_SIZE 1\n#define AVR32_USBB_UPSTA5CLR_SHORTPACKETIC 7\n#define AVR32_USBB_UPSTA5CLR_SHORTPACKETIC_MASK 0x00000080\n#define AVR32_USBB_UPSTA5CLR_SHORTPACKETIC_OFFSET 7\n#define AVR32_USBB_UPSTA5CLR_SHORTPACKETIC_SIZE 1\n#define AVR32_USBB_UPSTA5CLR_TXOUTIC 1\n#define AVR32_USBB_UPSTA5CLR_TXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UPSTA5CLR_TXOUTIC_OFFSET 1\n#define AVR32_USBB_UPSTA5CLR_TXOUTIC_SIZE 1\n#define AVR32_USBB_UPSTA5CLR_TXSTPIC 2\n#define AVR32_USBB_UPSTA5CLR_TXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UPSTA5CLR_TXSTPIC_OFFSET 2\n#define AVR32_USBB_UPSTA5CLR_TXSTPIC_SIZE 1\n#define AVR32_USBB_UPSTA5SET 0x000005a4\n#define AVR32_USBB_UPSTA5SET_NAKEDIS 4\n#define AVR32_USBB_UPSTA5SET_NAKEDIS_MASK 0x00000010\n#define AVR32_USBB_UPSTA5SET_NAKEDIS_OFFSET 4\n#define AVR32_USBB_UPSTA5SET_NAKEDIS_SIZE 1\n#define AVR32_USBB_UPSTA5SET_NBUSYBKS 12\n#define AVR32_USBB_UPSTA5SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UPSTA5SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UPSTA5SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UPSTA5SET_OVERFIS 5\n#define AVR32_USBB_UPSTA5SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UPSTA5SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UPSTA5SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UPSTA5SET_PERRIS 3\n#define AVR32_USBB_UPSTA5SET_PERRIS_MASK 0x00000008\n#define AVR32_USBB_UPSTA5SET_PERRIS_OFFSET 3\n#define AVR32_USBB_UPSTA5SET_PERRIS_SIZE 1\n#define AVR32_USBB_UPSTA5SET_RXINIS 0\n#define AVR32_USBB_UPSTA5SET_RXINIS_MASK 0x00000001\n#define AVR32_USBB_UPSTA5SET_RXINIS_OFFSET 0\n#define AVR32_USBB_UPSTA5SET_RXINIS_SIZE 1\n#define AVR32_USBB_UPSTA5SET_RXSTALLDIS 6\n#define AVR32_USBB_UPSTA5SET_RXSTALLDIS_MASK 0x00000040\n#define AVR32_USBB_UPSTA5SET_RXSTALLDIS_OFFSET 6\n#define AVR32_USBB_UPSTA5SET_RXSTALLDIS_SIZE 1\n#define AVR32_USBB_UPSTA5SET_SHORTPACKETIS 7\n#define AVR32_USBB_UPSTA5SET_SHORTPACKETIS_MASK 0x00000080\n#define AVR32_USBB_UPSTA5SET_SHORTPACKETIS_OFFSET 7\n#define AVR32_USBB_UPSTA5SET_SHORTPACKETIS_SIZE 1\n#define AVR32_USBB_UPSTA5SET_TXOUTIS 1\n#define AVR32_USBB_UPSTA5SET_TXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UPSTA5SET_TXOUTIS_OFFSET 1\n#define AVR32_USBB_UPSTA5SET_TXOUTIS_SIZE 1\n#define AVR32_USBB_UPSTA5SET_TXSTPIS 2\n#define AVR32_USBB_UPSTA5SET_TXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UPSTA5SET_TXSTPIS_OFFSET 2\n#define AVR32_USBB_UPSTA5SET_TXSTPIS_SIZE 1\n#define AVR32_USBB_UPSTA5_CFGOK 18\n#define AVR32_USBB_UPSTA5_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UPSTA5_CFGOK_OFFSET 18\n#define AVR32_USBB_UPSTA5_CFGOK_SIZE 1\n#define AVR32_USBB_UPSTA5_CURRBK 14\n#define AVR32_USBB_UPSTA5_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UPSTA5_CURRBK_OFFSET 14\n#define AVR32_USBB_UPSTA5_CURRBK_SIZE 2\n#define AVR32_USBB_UPSTA5_DTSEQ 8\n#define AVR32_USBB_UPSTA5_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UPSTA5_DTSEQ_OFFSET 8\n#define AVR32_USBB_UPSTA5_DTSEQ_SIZE 2\n#define AVR32_USBB_UPSTA5_NAKEDI 4\n#define AVR32_USBB_UPSTA5_NAKEDI_MASK 0x00000010\n#define AVR32_USBB_UPSTA5_NAKEDI_OFFSET 4\n#define AVR32_USBB_UPSTA5_NAKEDI_SIZE 1\n#define AVR32_USBB_UPSTA5_NBUSYBK 12\n#define AVR32_USBB_UPSTA5_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UPSTA5_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UPSTA5_NBUSYBK_SIZE 2\n#define AVR32_USBB_UPSTA5_OVERFI 5\n#define AVR32_USBB_UPSTA5_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UPSTA5_OVERFI_OFFSET 5\n#define AVR32_USBB_UPSTA5_OVERFI_SIZE 1\n#define AVR32_USBB_UPSTA5_PBYCT 20\n#define AVR32_USBB_UPSTA5_PBYCT_MASK 0x7ff00000\n#define AVR32_USBB_UPSTA5_PBYCT_OFFSET 20\n#define AVR32_USBB_UPSTA5_PBYCT_SIZE 11\n#define AVR32_USBB_UPSTA5_PERRI 3\n#define AVR32_USBB_UPSTA5_PERRI_MASK 0x00000008\n#define AVR32_USBB_UPSTA5_PERRI_OFFSET 3\n#define AVR32_USBB_UPSTA5_PERRI_SIZE 1\n#define AVR32_USBB_UPSTA5_RWALL 16\n#define AVR32_USBB_UPSTA5_RWALL_MASK 0x00010000\n#define AVR32_USBB_UPSTA5_RWALL_OFFSET 16\n#define AVR32_USBB_UPSTA5_RWALL_SIZE 1\n#define AVR32_USBB_UPSTA5_RXINI 0\n#define AVR32_USBB_UPSTA5_RXINI_MASK 0x00000001\n#define AVR32_USBB_UPSTA5_RXINI_OFFSET 0\n#define AVR32_USBB_UPSTA5_RXINI_SIZE 1\n#define AVR32_USBB_UPSTA5_RXSTALLDI 6\n#define AVR32_USBB_UPSTA5_RXSTALLDI_MASK 0x00000040\n#define AVR32_USBB_UPSTA5_RXSTALLDI_OFFSET 6\n#define AVR32_USBB_UPSTA5_RXSTALLDI_SIZE 1\n#define AVR32_USBB_UPSTA5_SHORTPACKETI 7\n#define AVR32_USBB_UPSTA5_SHORTPACKETI_MASK 0x00000080\n#define AVR32_USBB_UPSTA5_SHORTPACKETI_OFFSET 7\n#define AVR32_USBB_UPSTA5_SHORTPACKETI_SIZE 1\n#define AVR32_USBB_UPSTA5_TXOUTI 1\n#define AVR32_USBB_UPSTA5_TXOUTI_MASK 0x00000002\n#define AVR32_USBB_UPSTA5_TXOUTI_OFFSET 1\n#define AVR32_USBB_UPSTA5_TXOUTI_SIZE 1\n#define AVR32_USBB_UPSTA5_TXSTPI 2\n#define AVR32_USBB_UPSTA5_TXSTPI_MASK 0x00000004\n#define AVR32_USBB_UPSTA5_TXSTPI_OFFSET 2\n#define AVR32_USBB_UPSTA5_TXSTPI_SIZE 1\n#define AVR32_USBB_UPSTA6 0x00000548\n#define AVR32_USBB_UPSTA6CLR 0x00000578\n#define AVR32_USBB_UPSTA6CLR_NAKEDIC 4\n#define AVR32_USBB_UPSTA6CLR_NAKEDIC_MASK 0x00000010\n#define AVR32_USBB_UPSTA6CLR_NAKEDIC_OFFSET 4\n#define AVR32_USBB_UPSTA6CLR_NAKEDIC_SIZE 1\n#define AVR32_USBB_UPSTA6CLR_OVERFIC 5\n#define AVR32_USBB_UPSTA6CLR_OVERFIC_MASK 0x00000020\n#define AVR32_USBB_UPSTA6CLR_OVERFIC_OFFSET 5\n#define AVR32_USBB_UPSTA6CLR_OVERFIC_SIZE 1\n#define AVR32_USBB_UPSTA6CLR_RXINIC 0\n#define AVR32_USBB_UPSTA6CLR_RXINIC_MASK 0x00000001\n#define AVR32_USBB_UPSTA6CLR_RXINIC_OFFSET 0\n#define AVR32_USBB_UPSTA6CLR_RXINIC_SIZE 1\n#define AVR32_USBB_UPSTA6CLR_RXSTALLDIC 6\n#define AVR32_USBB_UPSTA6CLR_RXSTALLDIC_MASK 0x00000040\n#define AVR32_USBB_UPSTA6CLR_RXSTALLDIC_OFFSET 6\n#define AVR32_USBB_UPSTA6CLR_RXSTALLDIC_SIZE 1\n#define AVR32_USBB_UPSTA6CLR_SHORTPACKETIC 7\n#define AVR32_USBB_UPSTA6CLR_SHORTPACKETIC_MASK 0x00000080\n#define AVR32_USBB_UPSTA6CLR_SHORTPACKETIC_OFFSET 7\n#define AVR32_USBB_UPSTA6CLR_SHORTPACKETIC_SIZE 1\n#define AVR32_USBB_UPSTA6CLR_TXOUTIC 1\n#define AVR32_USBB_UPSTA6CLR_TXOUTIC_MASK 0x00000002\n#define AVR32_USBB_UPSTA6CLR_TXOUTIC_OFFSET 1\n#define AVR32_USBB_UPSTA6CLR_TXOUTIC_SIZE 1\n#define AVR32_USBB_UPSTA6CLR_TXSTPIC 2\n#define AVR32_USBB_UPSTA6CLR_TXSTPIC_MASK 0x00000004\n#define AVR32_USBB_UPSTA6CLR_TXSTPIC_OFFSET 2\n#define AVR32_USBB_UPSTA6CLR_TXSTPIC_SIZE 1\n#define AVR32_USBB_UPSTA6SET 0x000005a8\n#define AVR32_USBB_UPSTA6SET_NAKEDIS 4\n#define AVR32_USBB_UPSTA6SET_NAKEDIS_MASK 0x00000010\n#define AVR32_USBB_UPSTA6SET_NAKEDIS_OFFSET 4\n#define AVR32_USBB_UPSTA6SET_NAKEDIS_SIZE 1\n#define AVR32_USBB_UPSTA6SET_NBUSYBKS 12\n#define AVR32_USBB_UPSTA6SET_NBUSYBKS_MASK 0x00001000\n#define AVR32_USBB_UPSTA6SET_NBUSYBKS_OFFSET 12\n#define AVR32_USBB_UPSTA6SET_NBUSYBKS_SIZE 1\n#define AVR32_USBB_UPSTA6SET_OVERFIS 5\n#define AVR32_USBB_UPSTA6SET_OVERFIS_MASK 0x00000020\n#define AVR32_USBB_UPSTA6SET_OVERFIS_OFFSET 5\n#define AVR32_USBB_UPSTA6SET_OVERFIS_SIZE 1\n#define AVR32_USBB_UPSTA6SET_PERRIS 3\n#define AVR32_USBB_UPSTA6SET_PERRIS_MASK 0x00000008\n#define AVR32_USBB_UPSTA6SET_PERRIS_OFFSET 3\n#define AVR32_USBB_UPSTA6SET_PERRIS_SIZE 1\n#define AVR32_USBB_UPSTA6SET_RXINIS 0\n#define AVR32_USBB_UPSTA6SET_RXINIS_MASK 0x00000001\n#define AVR32_USBB_UPSTA6SET_RXINIS_OFFSET 0\n#define AVR32_USBB_UPSTA6SET_RXINIS_SIZE 1\n#define AVR32_USBB_UPSTA6SET_RXSTALLDIS 6\n#define AVR32_USBB_UPSTA6SET_RXSTALLDIS_MASK 0x00000040\n#define AVR32_USBB_UPSTA6SET_RXSTALLDIS_OFFSET 6\n#define AVR32_USBB_UPSTA6SET_RXSTALLDIS_SIZE 1\n#define AVR32_USBB_UPSTA6SET_SHORTPACKETIS 7\n#define AVR32_USBB_UPSTA6SET_SHORTPACKETIS_MASK 0x00000080\n#define AVR32_USBB_UPSTA6SET_SHORTPACKETIS_OFFSET 7\n#define AVR32_USBB_UPSTA6SET_SHORTPACKETIS_SIZE 1\n#define AVR32_USBB_UPSTA6SET_TXOUTIS 1\n#define AVR32_USBB_UPSTA6SET_TXOUTIS_MASK 0x00000002\n#define AVR32_USBB_UPSTA6SET_TXOUTIS_OFFSET 1\n#define AVR32_USBB_UPSTA6SET_TXOUTIS_SIZE 1\n#define AVR32_USBB_UPSTA6SET_TXSTPIS 2\n#define AVR32_USBB_UPSTA6SET_TXSTPIS_MASK 0x00000004\n#define AVR32_USBB_UPSTA6SET_TXSTPIS_OFFSET 2\n#define AVR32_USBB_UPSTA6SET_TXSTPIS_SIZE 1\n#define AVR32_USBB_UPSTA6_CFGOK 18\n#define AVR32_USBB_UPSTA6_CFGOK_MASK 0x00040000\n#define AVR32_USBB_UPSTA6_CFGOK_OFFSET 18\n#define AVR32_USBB_UPSTA6_CFGOK_SIZE 1\n#define AVR32_USBB_UPSTA6_CURRBK 14\n#define AVR32_USBB_UPSTA6_CURRBK_MASK 0x0000c000\n#define AVR32_USBB_UPSTA6_CURRBK_OFFSET 14\n#define AVR32_USBB_UPSTA6_CURRBK_SIZE 2\n#define AVR32_USBB_UPSTA6_DTSEQ 8\n#define AVR32_USBB_UPSTA6_DTSEQ_MASK 0x00000300\n#define AVR32_USBB_UPSTA6_DTSEQ_OFFSET 8\n#define AVR32_USBB_UPSTA6_DTSEQ_SIZE 2\n#define AVR32_USBB_UPSTA6_NAKEDI 4\n#define AVR32_USBB_UPSTA6_NAKEDI_MASK 0x00000010\n#define AVR32_USBB_UPSTA6_NAKEDI_OFFSET 4\n#define AVR32_USBB_UPSTA6_NAKEDI_SIZE 1\n#define AVR32_USBB_UPSTA6_NBUSYBK 12\n#define AVR32_USBB_UPSTA6_NBUSYBK_MASK 0x00003000\n#define AVR32_USBB_UPSTA6_NBUSYBK_OFFSET 12\n#define AVR32_USBB_UPSTA6_NBUSYBK_SIZE 2\n#define AVR32_USBB_UPSTA6_OVERFI 5\n#define AVR32_USBB_UPSTA6_OVERFI_MASK 0x00000020\n#define AVR32_USBB_UPSTA6_OVERFI_OFFSET 5\n#define AVR32_USBB_UPSTA6_OVERFI_SIZE 1\n#define AVR32_USBB_UPSTA6_PBYCT 20\n#define AVR32_USBB_UPSTA6_PBYCT_MASK 0x7ff00000\n#define AVR32_USBB_UPSTA6_PBYCT_OFFSET 20\n#define AVR32_USBB_UPSTA6_PBYCT_SIZE 11\n#define AVR32_USBB_UPSTA6_PERRI 3\n#define AVR32_USBB_UPSTA6_PERRI_MASK 0x00000008\n#define AVR32_USBB_UPSTA6_PERRI_OFFSET 3\n#define AVR32_USBB_UPSTA6_PERRI_SIZE 1\n#define AVR32_USBB_UPSTA6_RWALL 16\n#define AVR32_USBB_UPSTA6_RWALL_MASK 0x00010000\n#define AVR32_USBB_UPSTA6_RWALL_OFFSET 16\n#define AVR32_USBB_UPSTA6_RWALL_SIZE 1\n#define AVR32_USBB_UPSTA6_RXINI 0\n#define AVR32_USBB_UPSTA6_RXINI_MASK 0x00000001\n#define AVR32_USBB_UPSTA6_RXINI_OFFSET 0\n#define AVR32_USBB_UPSTA6_RXINI_SIZE 1\n#define AVR32_USBB_UPSTA6_RXSTALLDI 6\n#define AVR32_USBB_UPSTA6_RXSTALLDI_MASK 0x00000040\n#define AVR32_USBB_UPSTA6_RXSTALLDI_OFFSET 6\n#define AVR32_USBB_UPSTA6_RXSTALLDI_SIZE 1\n#define AVR32_USBB_UPSTA6_SHORTPACKETI 7\n#define AVR32_USBB_UPSTA6_SHORTPACKETI_MASK 0x00000080\n#define AVR32_USBB_UPSTA6_SHORTPACKETI_OFFSET 7\n#define AVR32_USBB_UPSTA6_SHORTPACKETI_SIZE 1\n#define AVR32_USBB_UPSTA6_TXOUTI 1\n#define AVR32_USBB_UPSTA6_TXOUTI_MASK 0x00000002\n#define AVR32_USBB_UPSTA6_TXOUTI_OFFSET 1\n#define AVR32_USBB_UPSTA6_TXOUTI_SIZE 1\n#define AVR32_USBB_UPSTA6_TXSTPI 2\n#define AVR32_USBB_UPSTA6_TXSTPI_MASK 0x00000004\n#define AVR32_USBB_UPSTA6_TXSTPI_OFFSET 2\n#define AVR32_USBB_UPSTA6_TXSTPI_SIZE 1\n#define AVR32_USBB_USBCON 0x00000800\n#define AVR32_USBB_USBCON_BCERRE 4\n#define AVR32_USBB_USBCON_BCERRE_MASK 0x00000010\n#define AVR32_USBB_USBCON_BCERRE_OFFSET 4\n#define AVR32_USBB_USBCON_BCERRE_SIZE 1\n#define AVR32_USBB_USBCON_FRZCLK 14\n#define AVR32_USBB_USBCON_FRZCLK_MASK 0x00004000\n#define AVR32_USBB_USBCON_FRZCLK_OFFSET 14\n#define AVR32_USBB_USBCON_FRZCLK_SIZE 1\n#define AVR32_USBB_USBCON_HNPERRE 6\n#define AVR32_USBB_USBCON_HNPERRE_MASK 0x00000040\n#define AVR32_USBB_USBCON_HNPERRE_OFFSET 6\n#define AVR32_USBB_USBCON_HNPERRE_SIZE 1\n#define AVR32_USBB_USBCON_HNPREQ 11\n#define AVR32_USBB_USBCON_HNPREQ_MASK 0x00000800\n#define AVR32_USBB_USBCON_HNPREQ_OFFSET 11\n#define AVR32_USBB_USBCON_HNPREQ_SIZE 1\n#define AVR32_USBB_USBCON_IDTE 0\n#define AVR32_USBB_USBCON_IDTE_MASK 0x00000001\n#define AVR32_USBB_USBCON_IDTE_OFFSET 0\n#define AVR32_USBB_USBCON_IDTE_SIZE 1\n#define AVR32_USBB_USBCON_OTGPADE 12\n#define AVR32_USBB_USBCON_OTGPADE_MASK 0x00001000\n#define AVR32_USBB_USBCON_OTGPADE_OFFSET 12\n#define AVR32_USBB_USBCON_OTGPADE_SIZE 1\n#define AVR32_USBB_USBCON_ROLEEXE 5\n#define AVR32_USBB_USBCON_ROLEEXE_MASK 0x00000020\n#define AVR32_USBB_USBCON_ROLEEXE_OFFSET 5\n#define AVR32_USBB_USBCON_ROLEEXE_SIZE 1\n#define AVR32_USBB_USBCON_SRPE 2\n#define AVR32_USBB_USBCON_SRPE_MASK 0x00000004\n#define AVR32_USBB_USBCON_SRPE_OFFSET 2\n#define AVR32_USBB_USBCON_SRPE_SIZE 1\n#define AVR32_USBB_USBCON_SRPREQ 10\n#define AVR32_USBB_USBCON_SRPREQ_MASK 0x00000400\n#define AVR32_USBB_USBCON_SRPREQ_OFFSET 10\n#define AVR32_USBB_USBCON_SRPREQ_SIZE 1\n#define AVR32_USBB_USBCON_SRPSEL 9\n#define AVR32_USBB_USBCON_SRPSEL_MASK 0x00000200\n#define AVR32_USBB_USBCON_SRPSEL_OFFSET 9\n#define AVR32_USBB_USBCON_SRPSEL_SIZE 1\n#define AVR32_USBB_USBCON_STOE 7\n#define AVR32_USBB_USBCON_STOE_MASK 0x00000080\n#define AVR32_USBB_USBCON_STOE_OFFSET 7\n#define AVR32_USBB_USBCON_STOE_SIZE 1\n#define AVR32_USBB_USBCON_TIMPAGE 20\n#define AVR32_USBB_USBCON_TIMPAGE_A_WAIT_VRISE 0x00000000\n#define AVR32_USBB_USBCON_TIMPAGE_MASK 0x00300000\n#define AVR32_USBB_USBCON_TIMPAGE_OFFSET 20\n#define AVR32_USBB_USBCON_TIMPAGE_PD_TMOUT_CNT 0x00000002\n#define AVR32_USBB_USBCON_TIMPAGE_SIZE 2\n#define AVR32_USBB_USBCON_TIMPAGE_SRP_DET_TMOUT 0x00000003\n#define AVR32_USBB_USBCON_TIMPAGE_VB_BUS_PULSING 0x00000001\n#define AVR32_USBB_USBCON_TIMVALUE 16\n#define AVR32_USBB_USBCON_TIMVALUE_A_WAIT_VRISE_100_MS 0x00000003\n#define AVR32_USBB_USBCON_TIMVALUE_A_WAIT_VRISE_20_MS 0x00000000\n#define AVR32_USBB_USBCON_TIMVALUE_A_WAIT_VRISE_50_MS 0x00000001\n#define AVR32_USBB_USBCON_TIMVALUE_A_WAIT_VRISE_70_MS 0x00000002\n#define AVR32_USBB_USBCON_TIMVALUE_MASK 0x00030000\n#define AVR32_USBB_USBCON_TIMVALUE_OFFSET 16\n#define AVR32_USBB_USBCON_TIMVALUE_PD_TMOUT_CNT_105_MS 0x00000001\n#define AVR32_USBB_USBCON_TIMVALUE_PD_TMOUT_CNT_118_MS 0x00000002\n#define AVR32_USBB_USBCON_TIMVALUE_PD_TMOUT_CNT_131_MS 0x00000003\n#define AVR32_USBB_USBCON_TIMVALUE_PD_TMOUT_CNT_93_MS 0x00000000\n#define AVR32_USBB_USBCON_TIMVALUE_SIZE 2\n#define AVR32_USBB_USBCON_TIMVALUE_SRP_DET_TMOUT_100_US 0x00000001\n#define AVR32_USBB_USBCON_TIMVALUE_SRP_DET_TMOUT_10_US 0x00000000\n#define AVR32_USBB_USBCON_TIMVALUE_SRP_DET_TMOUT_11_MS 0x00000003\n#define AVR32_USBB_USBCON_TIMVALUE_SRP_DET_TMOUT_1_MS 0x00000002\n#define AVR32_USBB_USBCON_TIMVALUE_VB_BUS_PULSING_15_MS 0x00000000\n#define AVR32_USBB_USBCON_TIMVALUE_VB_BUS_PULSING_23_MS 0x00000001\n#define AVR32_USBB_USBCON_TIMVALUE_VB_BUS_PULSING_31_MS 0x00000002\n#define AVR32_USBB_USBCON_TIMVALUE_VB_BUS_PULSING_40_MS 0x00000003\n#define AVR32_USBB_USBCON_UIDE 24\n#define AVR32_USBB_USBCON_UIDE_MASK 0x01000000\n#define AVR32_USBB_USBCON_UIDE_OFFSET 24\n#define AVR32_USBB_USBCON_UIDE_SIZE 1\n#define AVR32_USBB_USBCON_UIMOD 25\n#define AVR32_USBB_USBCON_UIMOD_MASK 0x02000000\n#define AVR32_USBB_USBCON_UIMOD_OFFSET 25\n#define AVR32_USBB_USBCON_UIMOD_SIZE 1\n#define AVR32_USBB_USBCON_UNLOCK 22\n#define AVR32_USBB_USBCON_UNLOCK_MASK 0x00400000\n#define AVR32_USBB_USBCON_UNLOCK_OFFSET 22\n#define AVR32_USBB_USBCON_UNLOCK_SIZE 1\n#define AVR32_USBB_USBCON_USBE 15\n#define AVR32_USBB_USBCON_USBE_MASK 0x00008000\n#define AVR32_USBB_USBCON_USBE_OFFSET 15\n#define AVR32_USBB_USBCON_USBE_SIZE 1\n#define AVR32_USBB_USBCON_VBERRE 3\n#define AVR32_USBB_USBCON_VBERRE_MASK 0x00000008\n#define AVR32_USBB_USBCON_VBERRE_OFFSET 3\n#define AVR32_USBB_USBCON_VBERRE_SIZE 1\n#define AVR32_USBB_USBCON_VBUSHWC 8\n#define AVR32_USBB_USBCON_VBUSHWC_MASK 0x00000100\n#define AVR32_USBB_USBCON_VBUSHWC_OFFSET 8\n#define AVR32_USBB_USBCON_VBUSHWC_SIZE 1\n#define AVR32_USBB_USBCON_VBUSPO 13\n#define AVR32_USBB_USBCON_VBUSPO_MASK 0x00002000\n#define AVR32_USBB_USBCON_VBUSPO_OFFSET 13\n#define AVR32_USBB_USBCON_VBUSPO_SIZE 1\n#define AVR32_USBB_USBCON_VBUSTE 1\n#define AVR32_USBB_USBCON_VBUSTE_MASK 0x00000002\n#define AVR32_USBB_USBCON_VBUSTE_OFFSET 1\n#define AVR32_USBB_USBCON_VBUSTE_SIZE 1\n#define AVR32_USBB_USBE_SIZE 1\n#define AVR32_USBB_USBFSM 0x0000082c\n#define AVR32_USBB_USBFSM_DRDSTATE 0\n#define AVR32_USBB_USBFSM_DRDSTATE_A_HOST 0x00000003\n#define AVR32_USBB_USBFSM_DRDSTATE_A_IDLE 0x00000000\n#define AVR32_USBB_USBFSM_DRDSTATE_A_PERIPHERAL 0x00000005\n#define AVR32_USBB_USBFSM_DRDSTATE_A_SUSPEND 0x00000004\n#define AVR32_USBB_USBFSM_DRDSTATE_A_VBUS_ERR 0x00000007\n#define AVR32_USBB_USBFSM_DRDSTATE_A_WAIT_BCON 0x00000002\n#define AVR32_USBB_USBFSM_DRDSTATE_A_WAIT_DISCHARGE 0x00000008\n#define AVR32_USBB_USBFSM_DRDSTATE_A_WAIT_VFALL 0x00000006\n#define AVR32_USBB_USBFSM_DRDSTATE_A_WAIT_VRISE 0x00000001\n#define AVR32_USBB_USBFSM_DRDSTATE_B_HOST 0x0000000e\n#define AVR32_USBB_USBFSM_DRDSTATE_B_IDLE 0x00000009\n#define AVR32_USBB_USBFSM_DRDSTATE_B_PERIPHERAL 0x0000000a\n#define AVR32_USBB_USBFSM_DRDSTATE_B_SRP_INIT 0x0000000f\n#define AVR32_USBB_USBFSM_DRDSTATE_B_WAIT_ACON 0x0000000d\n#define AVR32_USBB_USBFSM_DRDSTATE_B_WAIT_BEGIN_HNP 0x0000000b\n#define AVR32_USBB_USBFSM_DRDSTATE_B_WAIT_DISCHARGE 0x0000000c\n#define AVR32_USBB_USBFSM_DRDSTATE_MASK 0x0000000f\n#define AVR32_USBB_USBFSM_DRDSTATE_OFFSET 0\n#define AVR32_USBB_USBFSM_DRDSTATE_SIZE 4\n#define AVR32_USBB_USBSTA 0x00000804\n#define AVR32_USBB_USBSTACLR 0x00000808\n#define AVR32_USBB_USBSTACLR_BCERRIC 4\n#define AVR32_USBB_USBSTACLR_BCERRIC_MASK 0x00000010\n#define AVR32_USBB_USBSTACLR_BCERRIC_OFFSET 4\n#define AVR32_USBB_USBSTACLR_BCERRIC_SIZE 1\n#define AVR32_USBB_USBSTACLR_HNPERRIC 6\n#define AVR32_USBB_USBSTACLR_HNPERRIC_MASK 0x00000040\n#define AVR32_USBB_USBSTACLR_HNPERRIC_OFFSET 6\n#define AVR32_USBB_USBSTACLR_HNPERRIC_SIZE 1\n#define AVR32_USBB_USBSTACLR_IDTIC 0\n#define AVR32_USBB_USBSTACLR_IDTIC_MASK 0x00000001\n#define AVR32_USBB_USBSTACLR_IDTIC_OFFSET 0\n#define AVR32_USBB_USBSTACLR_IDTIC_SIZE 1\n#define AVR32_USBB_USBSTACLR_ROLEEXIC 5\n#define AVR32_USBB_USBSTACLR_ROLEEXIC_MASK 0x00000020\n#define AVR32_USBB_USBSTACLR_ROLEEXIC_OFFSET 5\n#define AVR32_USBB_USBSTACLR_ROLEEXIC_SIZE 1\n#define AVR32_USBB_USBSTACLR_SRPIC 2\n#define AVR32_USBB_USBSTACLR_SRPIC_MASK 0x00000004\n#define AVR32_USBB_USBSTACLR_SRPIC_OFFSET 2\n#define AVR32_USBB_USBSTACLR_SRPIC_SIZE 1\n#define AVR32_USBB_USBSTACLR_STOIC 7\n#define AVR32_USBB_USBSTACLR_STOIC_MASK 0x00000080\n#define AVR32_USBB_USBSTACLR_STOIC_OFFSET 7\n#define AVR32_USBB_USBSTACLR_STOIC_SIZE 1\n#define AVR32_USBB_USBSTACLR_VBERRIC 3\n#define AVR32_USBB_USBSTACLR_VBERRIC_MASK 0x00000008\n#define AVR32_USBB_USBSTACLR_VBERRIC_OFFSET 3\n#define AVR32_USBB_USBSTACLR_VBERRIC_SIZE 1\n#define AVR32_USBB_USBSTACLR_VBUSRQC 9\n#define AVR32_USBB_USBSTACLR_VBUSRQC_MASK 0x00000200\n#define AVR32_USBB_USBSTACLR_VBUSRQC_OFFSET 9\n#define AVR32_USBB_USBSTACLR_VBUSRQC_SIZE 1\n#define AVR32_USBB_USBSTACLR_VBUSTIC 1\n#define AVR32_USBB_USBSTACLR_VBUSTIC_MASK 0x00000002\n#define AVR32_USBB_USBSTACLR_VBUSTIC_OFFSET 1\n#define AVR32_USBB_USBSTACLR_VBUSTIC_SIZE 1\n#define AVR32_USBB_USBSTASET 0x0000080c\n#define AVR32_USBB_USBSTASET_BCERRIS 4\n#define AVR32_USBB_USBSTASET_BCERRIS_MASK 0x00000010\n#define AVR32_USBB_USBSTASET_BCERRIS_OFFSET 4\n#define AVR32_USBB_USBSTASET_BCERRIS_SIZE 1\n#define AVR32_USBB_USBSTASET_HNPERRIS 6\n#define AVR32_USBB_USBSTASET_HNPERRIS_MASK 0x00000040\n#define AVR32_USBB_USBSTASET_HNPERRIS_OFFSET 6\n#define AVR32_USBB_USBSTASET_HNPERRIS_SIZE 1\n#define AVR32_USBB_USBSTASET_IDTIS 0\n#define AVR32_USBB_USBSTASET_IDTIS_MASK 0x00000001\n#define AVR32_USBB_USBSTASET_IDTIS_OFFSET 0\n#define AVR32_USBB_USBSTASET_IDTIS_SIZE 1\n#define AVR32_USBB_USBSTASET_ROLEEXIS 5\n#define AVR32_USBB_USBSTASET_ROLEEXIS_MASK 0x00000020\n#define AVR32_USBB_USBSTASET_ROLEEXIS_OFFSET 5\n#define AVR32_USBB_USBSTASET_ROLEEXIS_SIZE 1\n#define AVR32_USBB_USBSTASET_SRPIS 2\n#define AVR32_USBB_USBSTASET_SRPIS_MASK 0x00000004\n#define AVR32_USBB_USBSTASET_SRPIS_OFFSET 2\n#define AVR32_USBB_USBSTASET_SRPIS_SIZE 1\n#define AVR32_USBB_USBSTASET_STOIS 7\n#define AVR32_USBB_USBSTASET_STOIS_MASK 0x00000080\n#define AVR32_USBB_USBSTASET_STOIS_OFFSET 7\n#define AVR32_USBB_USBSTASET_STOIS_SIZE 1\n#define AVR32_USBB_USBSTASET_VBERRIS 3\n#define AVR32_USBB_USBSTASET_VBERRIS_MASK 0x00000008\n#define AVR32_USBB_USBSTASET_VBERRIS_OFFSET 3\n#define AVR32_USBB_USBSTASET_VBERRIS_SIZE 1\n#define AVR32_USBB_USBSTASET_VBUSRQS 9\n#define AVR32_USBB_USBSTASET_VBUSRQS_MASK 0x00000200\n#define AVR32_USBB_USBSTASET_VBUSRQS_OFFSET 9\n#define AVR32_USBB_USBSTASET_VBUSRQS_SIZE 1\n#define AVR32_USBB_USBSTASET_VBUSTIS 1\n#define AVR32_USBB_USBSTASET_VBUSTIS_MASK 0x00000002\n#define AVR32_USBB_USBSTASET_VBUSTIS_OFFSET 1\n#define AVR32_USBB_USBSTASET_VBUSTIS_SIZE 1\n#define AVR32_USBB_USBSTA_BCERRI 4\n#define AVR32_USBB_USBSTA_BCERRI_MASK 0x00000010\n#define AVR32_USBB_USBSTA_BCERRI_OFFSET 4\n#define AVR32_USBB_USBSTA_BCERRI_SIZE 1\n#define AVR32_USBB_USBSTA_CLKUSABLE 14\n#define AVR32_USBB_USBSTA_CLKUSABLE_MASK 0x00004000\n#define AVR32_USBB_USBSTA_CLKUSABLE_OFFSET 14\n#define AVR32_USBB_USBSTA_CLKUSABLE_SIZE 1\n#define AVR32_USBB_USBSTA_HNPERRI 6\n#define AVR32_USBB_USBSTA_HNPERRI_MASK 0x00000040\n#define AVR32_USBB_USBSTA_HNPERRI_OFFSET 6\n#define AVR32_USBB_USBSTA_HNPERRI_SIZE 1\n#define AVR32_USBB_USBSTA_ID 10\n#define AVR32_USBB_USBSTA_IDTI 0\n#define AVR32_USBB_USBSTA_IDTI_MASK 0x00000001\n#define AVR32_USBB_USBSTA_IDTI_OFFSET 0\n#define AVR32_USBB_USBSTA_IDTI_SIZE 1\n#define AVR32_USBB_USBSTA_ID_MASK 0x00000400\n#define AVR32_USBB_USBSTA_ID_OFFSET 10\n#define AVR32_USBB_USBSTA_ID_SIZE 1\n#define AVR32_USBB_USBSTA_ROLEEXI 5\n#define AVR32_USBB_USBSTA_ROLEEXI_MASK 0x00000020\n#define AVR32_USBB_USBSTA_ROLEEXI_OFFSET 5\n#define AVR32_USBB_USBSTA_ROLEEXI_SIZE 1\n#define AVR32_USBB_USBSTA_SPEED 12\n#define AVR32_USBB_USBSTA_SPEED_FULL 0x00000000\n#define AVR32_USBB_USBSTA_SPEED_LOW 0x00000002\n#define AVR32_USBB_USBSTA_SPEED_MASK 0x00003000\n#define AVR32_USBB_USBSTA_SPEED_OFFSET 12\n#define AVR32_USBB_USBSTA_SPEED_SIZE 2\n#define AVR32_USBB_USBSTA_SRPI 2\n#define AVR32_USBB_USBSTA_SRPI_MASK 0x00000004\n#define AVR32_USBB_USBSTA_SRPI_OFFSET 2\n#define AVR32_USBB_USBSTA_SRPI_SIZE 1\n#define AVR32_USBB_USBSTA_STOI 7\n#define AVR32_USBB_USBSTA_STOI_MASK 0x00000080\n#define AVR32_USBB_USBSTA_STOI_OFFSET 7\n#define AVR32_USBB_USBSTA_STOI_SIZE 1\n#define AVR32_USBB_USBSTA_VBERRI 3\n#define AVR32_USBB_USBSTA_VBERRI_MASK 0x00000008\n#define AVR32_USBB_USBSTA_VBERRI_OFFSET 3\n#define AVR32_USBB_USBSTA_VBERRI_SIZE 1\n#define AVR32_USBB_USBSTA_VBUS 11\n#define AVR32_USBB_USBSTA_VBUSRQ 9\n#define AVR32_USBB_USBSTA_VBUSRQ_MASK 0x00000200\n#define AVR32_USBB_USBSTA_VBUSRQ_OFFSET 9\n#define AVR32_USBB_USBSTA_VBUSRQ_SIZE 1\n#define AVR32_USBB_USBSTA_VBUSTI 1\n#define AVR32_USBB_USBSTA_VBUSTI_MASK 0x00000002\n#define AVR32_USBB_USBSTA_VBUSTI_OFFSET 1\n#define AVR32_USBB_USBSTA_VBUSTI_SIZE 1\n#define AVR32_USBB_USBSTA_VBUS_MASK 0x00000800\n#define AVR32_USBB_USBSTA_VBUS_OFFSET 11\n#define AVR32_USBB_USBSTA_VBUS_SIZE 1\n#define AVR32_USBB_UTMIRESET 8\n#define AVR32_USBB_UTMIRESET_MASK 0x00000100\n#define AVR32_USBB_UTMIRESET_OFFSET 8\n#define AVR32_USBB_UTMIRESET_SIZE 1\n#define AVR32_USBB_UVERS 0x00000818\n#define AVR32_USBB_UVERS_METAL_FIX_NUM 16\n#define AVR32_USBB_UVERS_METAL_FIX_NUM_MASK 0x00070000\n#define AVR32_USBB_UVERS_METAL_FIX_NUM_OFFSET 16\n#define AVR32_USBB_UVERS_METAL_FIX_NUM_SIZE 3\n#define AVR32_USBB_UVERS_VERSION_NUM 0\n#define AVR32_USBB_UVERS_VERSION_NUM_MASK 0x0000ffff\n#define AVR32_USBB_UVERS_VERSION_NUM_OFFSET 0\n#define AVR32_USBB_UVERS_VERSION_NUM_SIZE 16\n#define AVR32_USBB_VBERRE 3\n#define AVR32_USBB_VBERRE_MASK 0x00000008\n#define AVR32_USBB_VBERRE_OFFSET 3\n#define AVR32_USBB_VBERRE_SIZE 1\n#define AVR32_USBB_VBERRI 3\n#define AVR32_USBB_VBERRIC 3\n#define AVR32_USBB_VBERRIC_MASK 0x00000008\n#define AVR32_USBB_VBERRIC_OFFSET 3\n#define AVR32_USBB_VBERRIC_SIZE 1\n#define AVR32_USBB_VBERRIS 3\n#define AVR32_USBB_VBERRIS_MASK 0x00000008\n#define AVR32_USBB_VBERRIS_OFFSET 3\n#define AVR32_USBB_VBERRIS_SIZE 1\n#define AVR32_USBB_VBERRI_MASK 0x00000008\n#define AVR32_USBB_VBERRI_OFFSET 3\n#define AVR32_USBB_VBERRI_SIZE 1\n#define AVR32_USBB_VBUSE 7\n#define AVR32_USBB_VBUSEC 7\n#define AVR32_USBB_VBUSEC_MASK 0x00000080\n#define AVR32_USBB_VBUSEC_OFFSET 7\n#define AVR32_USBB_VBUSEC_SIZE 1\n#define AVR32_USBB_VBUSES 7\n#define AVR32_USBB_VBUSES_MASK 0x00000080\n#define AVR32_USBB_VBUSES_OFFSET 7\n#define AVR32_USBB_VBUSES_SIZE 1\n#define AVR32_USBB_VBUSE_MASK 0x00000080\n#define AVR32_USBB_VBUSE_OFFSET 7\n#define AVR32_USBB_VBUSE_SIZE 1\n#define AVR32_USBB_VBUSHWC 8\n#define AVR32_USBB_VBUSHWC_MASK 0x00000100\n#define AVR32_USBB_VBUSHWC_OFFSET 8\n#define AVR32_USBB_VBUSHWC_SIZE 1\n#define AVR32_USBB_VBUSPO 13\n#define AVR32_USBB_VBUSPO_MASK 0x00002000\n#define AVR32_USBB_VBUSPO_OFFSET 13\n#define AVR32_USBB_VBUSPO_SIZE 1\n#define AVR32_USBB_VBUSRQ 9\n#define AVR32_USBB_VBUSRQC 9\n#define AVR32_USBB_VBUSRQC_MASK 0x00000200\n#define AVR32_USBB_VBUSRQC_OFFSET 9\n#define AVR32_USBB_VBUSRQC_SIZE 1\n#define AVR32_USBB_VBUSRQS 9\n#define AVR32_USBB_VBUSRQS_MASK 0x00000200\n#define AVR32_USBB_VBUSRQS_OFFSET 9\n#define AVR32_USBB_VBUSRQS_SIZE 1\n#define AVR32_USBB_VBUSRQ_MASK 0x00000200\n#define AVR32_USBB_VBUSRQ_OFFSET 9\n#define AVR32_USBB_VBUSRQ_SIZE 1\n#define AVR32_USBB_VBUSTE 1\n#define AVR32_USBB_VBUSTE_MASK 0x00000002\n#define AVR32_USBB_VBUSTE_OFFSET 1\n#define AVR32_USBB_VBUSTE_SIZE 1\n#define AVR32_USBB_VBUSTIC_SIZE 1\n#define AVR32_USBB_VBUSTIS_SIZE 1\n#define AVR32_USBB_VBUSTI_SIZE 1\n#define AVR32_USBB_VBUS_SIZE 1\n#define AVR32_USBB_VB_BUS_PULSING 0x00000001\n#define AVR32_USBB_VB_BUS_PULSING_15_MS 0x00000000\n#define AVR32_USBB_VB_BUS_PULSING_23_MS 0x00000001\n#define AVR32_USBB_VB_BUS_PULSING_31_MS 0x00000002\n#define AVR32_USBB_VB_BUS_PULSING_40_MS 0x00000003\n#define AVR32_USBB_VERSION_NUM 0\n#define AVR32_USBB_VERSION_NUM_MASK 0x0000ffff\n#define AVR32_USBB_VERSION_NUM_OFFSET 0\n#define AVR32_USBB_VERSION_NUM_SIZE 16\n#define AVR32_USBB_WAKEUP 4\n#define AVR32_USBB_WAKEUPC 4\n#define AVR32_USBB_WAKEUPC_MASK 0x00000010\n#define AVR32_USBB_WAKEUPC_OFFSET 4\n#define AVR32_USBB_WAKEUPC_SIZE 1\n#define AVR32_USBB_WAKEUPE 4\n#define AVR32_USBB_WAKEUPEC 4\n#define AVR32_USBB_WAKEUPEC_MASK 0x00000010\n#define AVR32_USBB_WAKEUPEC_OFFSET 4\n#define AVR32_USBB_WAKEUPEC_SIZE 1\n#define AVR32_USBB_WAKEUPES 4\n#define AVR32_USBB_WAKEUPES_MASK 0x00000010\n#define AVR32_USBB_WAKEUPES_OFFSET 4\n#define AVR32_USBB_WAKEUPES_SIZE 1\n#define AVR32_USBB_WAKEUPE_MASK 0x00000010\n#define AVR32_USBB_WAKEUPE_OFFSET 4\n#define AVR32_USBB_WAKEUPE_SIZE 1\n#define AVR32_USBB_WAKEUPS 4\n#define AVR32_USBB_WAKEUPS_MASK 0x00000010\n#define AVR32_USBB_WAKEUPS_OFFSET 4\n#define AVR32_USBB_WAKEUPS_SIZE 1\n#define AVR32_USBB_WAKEUP_MASK 0x00000010\n#define AVR32_USBB_WAKEUP_OFFSET 4\n#define AVR32_USBB_WAKEUP_SIZE 1\n\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_usbb_udcon_t {\n unsigned int :13;\n unsigned int frzclk : 1;\n unsigned int usbe : 1;\n unsigned int opmode2 : 1;\n unsigned int tstpckt : 1;\n unsigned int tstk : 1;\n unsigned int tstj : 1;\n unsigned int ls : 1;\n unsigned int spdconf : 2;\n unsigned int rmwkup : 1;\n unsigned int detach : 1;\n unsigned int adden : 1;\n unsigned int uadd : 7;\n} avr32_usbb_udcon_t;\n\n\n\ntypedef struct avr32_usbb_udint_t {\n unsigned int : 1;\n unsigned int dma6int : 1;\n unsigned int dma5int : 1;\n unsigned int dma4int : 1;\n unsigned int dma3int : 1;\n unsigned int dma2int : 1;\n unsigned int dma1int : 1;\n unsigned int : 6;\n unsigned int ep6int : 1;\n unsigned int ep5int : 1;\n unsigned int ep4int : 1;\n unsigned int ep3int : 1;\n unsigned int ep2int : 1;\n unsigned int ep1int : 1;\n unsigned int ep0int : 1;\n unsigned int : 1;\n unsigned int clkusable : 1;\n unsigned int speed : 1;\n unsigned int vbus : 1;\n unsigned int vbusti : 1;\n unsigned int uprsm : 1;\n unsigned int eorsm : 1;\n unsigned int wakeup : 1;\n unsigned int eorst : 1;\n unsigned int sof : 1;\n unsigned int msof : 1;\n unsigned int susp : 1;\n} avr32_usbb_udint_t;\n\n\n\ntypedef struct avr32_usbb_udintclr_t {\n unsigned int :24;\n unsigned int vbustic : 1;\n unsigned int uprsmc : 1;\n unsigned int eorsmc : 1;\n unsigned int wakeupc : 1;\n unsigned int eorstc : 1;\n unsigned int sofc : 1;\n unsigned int msofc : 1;\n unsigned int suspc : 1;\n} avr32_usbb_udintclr_t;\n\n\n\ntypedef struct avr32_usbb_udintset_t {\n unsigned int : 1;\n unsigned int dma6ints : 1;\n unsigned int dma5ints : 1;\n unsigned int dma4ints : 1;\n unsigned int dma3ints : 1;\n unsigned int dma2ints : 1;\n unsigned int dma1ints : 1;\n unsigned int :17;\n unsigned int vbustis : 1;\n unsigned int uprsms : 1;\n unsigned int eorsms : 1;\n unsigned int wakeups : 1;\n unsigned int eorsts : 1;\n unsigned int sofs : 1;\n unsigned int msofs : 1;\n unsigned int susps : 1;\n} avr32_usbb_udintset_t;\n\n\n\ntypedef struct avr32_usbb_udinte_t {\n unsigned int : 1;\n unsigned int dma6inte : 1;\n unsigned int dma5inte : 1;\n unsigned int dma4inte : 1;\n unsigned int dma3inte : 1;\n unsigned int dma2inte : 1;\n unsigned int dma1inte : 1;\n unsigned int : 6;\n unsigned int ep6inte : 1;\n unsigned int ep5inte : 1;\n unsigned int ep4inte : 1;\n unsigned int ep3inte : 1;\n unsigned int ep2inte : 1;\n unsigned int ep1inte : 1;\n unsigned int ep0inte : 1;\n unsigned int : 4;\n unsigned int vbuse : 1;\n unsigned int uprsme : 1;\n unsigned int eorsme : 1;\n unsigned int wakeupe : 1;\n unsigned int eorste : 1;\n unsigned int sofe : 1;\n unsigned int msofe : 1;\n unsigned int suspe : 1;\n} avr32_usbb_udinte_t;\n\n\n\ntypedef struct avr32_usbb_udinteclr_t {\n unsigned int : 1;\n unsigned int dam6intec : 1;\n unsigned int dma5intec : 1;\n unsigned int dma4intec : 1;\n unsigned int dma3intec : 1;\n unsigned int dma2intec : 1;\n unsigned int dma1intec : 1;\n unsigned int : 6;\n unsigned int ep6intec : 1;\n unsigned int ep5intec : 1;\n unsigned int ep4intec : 1;\n unsigned int ep3intec : 1;\n unsigned int ep2intec : 1;\n unsigned int ep1intec : 1;\n unsigned int ep0intec : 1;\n unsigned int : 4;\n unsigned int vbusec : 1;\n unsigned int uprsmec : 1;\n unsigned int eorsmec : 1;\n unsigned int wakeupec : 1;\n unsigned int eorstec : 1;\n unsigned int sofec : 1;\n unsigned int msofec : 1;\n unsigned int suspec : 1;\n} avr32_usbb_udinteclr_t;\n\n\n\ntypedef struct avr32_usbb_udinteset_t {\n unsigned int : 1;\n unsigned int dma6intes : 1;\n unsigned int dma5intes : 1;\n unsigned int dma4intes : 1;\n unsigned int dma3intes : 1;\n unsigned int dma2intes : 1;\n unsigned int dma1intes : 1;\n unsigned int : 6;\n unsigned int ep6intes : 1;\n unsigned int ep5intes : 1;\n unsigned int ep4intes : 1;\n unsigned int ep3intes : 1;\n unsigned int ep2intes : 1;\n unsigned int ep1intes : 1;\n unsigned int ep0intes : 1;\n unsigned int : 4;\n unsigned int vbuses : 1;\n unsigned int uprsmes : 1;\n unsigned int eorsmes : 1;\n unsigned int wakeupes : 1;\n unsigned int eorstes : 1;\n unsigned int sofes : 1;\n unsigned int msofes : 1;\n unsigned int suspes : 1;\n} avr32_usbb_udinteset_t;\n\n\n\ntypedef struct avr32_usbb_uerst_t {\n unsigned int : 9;\n unsigned int eprst6 : 1;\n unsigned int eprst5 : 1;\n unsigned int eprst4 : 1;\n unsigned int eprst3 : 1;\n unsigned int eprst2 : 1;\n unsigned int eprst1 : 1;\n unsigned int eprst0 : 1;\n unsigned int : 9;\n unsigned int epen6 : 1;\n unsigned int epen5 : 1;\n unsigned int epen4 : 1;\n unsigned int epen3 : 1;\n unsigned int epen2 : 1;\n unsigned int epen1 : 1;\n unsigned int epen0 : 1;\n} avr32_usbb_uerst_t;\n\n\n\ntypedef struct avr32_usbb_udfnum_t {\n unsigned int :16;\n unsigned int fncerr : 1;\n unsigned int : 1;\n unsigned int fnum :11;\n unsigned int mfnum : 3;\n} avr32_usbb_udfnum_t;\n\n\n\ntypedef struct avr32_usbb_udtst1_t {\n unsigned int loadsofcnt : 1;\n unsigned int sofcntmax : 7;\n unsigned int loadcntb : 1;\n unsigned int : 1;\n unsigned int counterb : 6;\n unsigned int loadcnta : 1;\n unsigned int countera :15;\n} avr32_usbb_udtst1_t;\n\n\n\ntypedef struct avr32_usbb_udtst2_t {\n unsigned int :25;\n unsigned int nothostdisconnect : 1;\n unsigned int bypassdpll : 1;\n unsigned int forcesuspendmto1 : 1;\n unsigned int disbalegatedclock : 1;\n unsigned int loopbackmode : 1;\n unsigned int hsserialmode : 1;\n unsigned int fulldetachen : 1;\n} avr32_usbb_udtst2_t;\n\n\n\ntypedef struct avr32_usbb_udfeatures_t {\n unsigned int en_high_bd_iso_ept_15 : 1;\n unsigned int en_high_bd_iso_ept_14 : 1;\n unsigned int en_high_bd_iso_ept_13 : 1;\n unsigned int en_high_bd_iso_ept_12 : 1;\n unsigned int en_high_bd_iso_ept_11 : 1;\n unsigned int en_high_bd_iso_ept_10 : 1;\n unsigned int en_high_bd_iso_ept_9 : 1;\n unsigned int en_high_bd_iso_ept_8 : 1;\n unsigned int en_high_bd_iso_ept_7 : 1;\n unsigned int en_high_bd_iso_ept_6 : 1;\n unsigned int en_high_bd_iso_ept_5 : 1;\n unsigned int en_high_bd_iso_ept_4 : 1;\n unsigned int en_high_bd_iso_ept_3 : 1;\n unsigned int en_high_bd_iso_ept_2 : 1;\n unsigned int en_high_bd_iso_ept_1 : 1;\n unsigned int data_bus_8_16 : 1;\n unsigned int byte_write_dpram : 1;\n unsigned int fifo_max_size : 3;\n unsigned int dma_fifo_word_depth : 4;\n unsigned int dma_buffer_size : 1;\n unsigned int dma_channel_nbr : 3;\n unsigned int ept_nbr_max : 4;\n} avr32_usbb_udfeatures_t;\n\n\n\ntypedef struct avr32_usbb_uecfg0_t {\n unsigned int datasizerdwr : 2;\n unsigned int :15;\n unsigned int nbtrans : 2;\n unsigned int eptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int epdir : 1;\n unsigned int : 1;\n unsigned int epsize : 3;\n unsigned int epbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_uecfg0_t;\n\n\n\ntypedef struct avr32_usbb_uecfg1_t {\n unsigned int datasizerdwr : 2;\n unsigned int :15;\n unsigned int nbtrans : 2;\n unsigned int eptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int epdir : 1;\n unsigned int : 1;\n unsigned int epsize : 3;\n unsigned int epbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_uecfg1_t;\n\n\n\ntypedef struct avr32_usbb_uecfg2_t {\n unsigned int datasizerdwr : 2;\n unsigned int :15;\n unsigned int nbtrans : 2;\n unsigned int eptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int epdir : 1;\n unsigned int : 1;\n unsigned int epsize : 3;\n unsigned int epbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_uecfg2_t;\n\n\n\ntypedef struct avr32_usbb_uecfg3_t {\n unsigned int datasizerdwr : 2;\n unsigned int :15;\n unsigned int nbtrans : 2;\n unsigned int eptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int epdir : 1;\n unsigned int : 1;\n unsigned int epsize : 3;\n unsigned int epbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_uecfg3_t;\n\n\n\ntypedef struct avr32_usbb_uecfg4_t {\n unsigned int datasizerdwr : 2;\n unsigned int :15;\n unsigned int nbtrans : 2;\n unsigned int eptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int epdir : 1;\n unsigned int : 1;\n unsigned int epsize : 3;\n unsigned int epbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_uecfg4_t;\n\n\n\ntypedef struct avr32_usbb_uecfg5_t {\n unsigned int datasizerdwr : 2;\n unsigned int :15;\n unsigned int nbtrans : 2;\n unsigned int eptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int epdir : 1;\n unsigned int : 1;\n unsigned int epsize : 3;\n unsigned int epbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_uecfg5_t;\n\n\n\ntypedef struct avr32_usbb_uecfg6_t {\n unsigned int datasizerdwr : 2;\n unsigned int :15;\n unsigned int nbtrans : 2;\n unsigned int eptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int epdir : 1;\n unsigned int : 1;\n unsigned int epsize : 3;\n unsigned int epbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_uecfg6_t;\n\n\n\ntypedef struct avr32_usbb_uesta0_t {\n unsigned int : 1;\n unsigned int byct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int ctrldir : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 1;\n unsigned int errortrans : 1;\n unsigned int dtseq : 2;\n unsigned int shortpacket : 1;\n unsigned int stalledi : 1;\n unsigned int overfi : 1;\n unsigned int nakini : 1;\n unsigned int nakouti : 1;\n unsigned int rxstpi : 1;\n unsigned int rxouti : 1;\n unsigned int txini : 1;\n} avr32_usbb_uesta0_t;\n\n\n\ntypedef struct avr32_usbb_uesta1_t {\n unsigned int : 1;\n unsigned int byct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int ctrldir : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 1;\n unsigned int errortrans : 1;\n unsigned int dtseq : 2;\n unsigned int shortpacket : 1;\n unsigned int stalledi : 1;\n unsigned int overfi : 1;\n unsigned int nakini : 1;\n unsigned int nakouti : 1;\n unsigned int rxstpi : 1;\n unsigned int rxouti : 1;\n unsigned int txini : 1;\n} avr32_usbb_uesta1_t;\n\n\n\ntypedef struct avr32_usbb_uesta2_t {\n unsigned int : 1;\n unsigned int byct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int ctrldir : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 1;\n unsigned int errortrans : 1;\n unsigned int dtseq : 2;\n unsigned int shortpacket : 1;\n unsigned int stalledi : 1;\n unsigned int overfi : 1;\n unsigned int nakini : 1;\n unsigned int nakouti : 1;\n unsigned int rxstpi : 1;\n unsigned int rxouti : 1;\n unsigned int txini : 1;\n} avr32_usbb_uesta2_t;\n\n\n\ntypedef struct avr32_usbb_uesta3_t {\n unsigned int : 1;\n unsigned int byct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int ctrldir : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 1;\n unsigned int errortrans : 1;\n unsigned int dtseq : 2;\n unsigned int shortpacket : 1;\n unsigned int stalledi : 1;\n unsigned int overfi : 1;\n unsigned int nakini : 1;\n unsigned int nakouti : 1;\n unsigned int rxstpi : 1;\n unsigned int rxouti : 1;\n unsigned int txini : 1;\n} avr32_usbb_uesta3_t;\n\n\n\ntypedef struct avr32_usbb_uesta4_t {\n unsigned int : 1;\n unsigned int byct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int ctrldir : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 1;\n unsigned int errortrans : 1;\n unsigned int dtseq : 2;\n unsigned int shortpacket : 1;\n unsigned int stalledi : 1;\n unsigned int overfi : 1;\n unsigned int nakini : 1;\n unsigned int nakouti : 1;\n unsigned int rxstpi : 1;\n unsigned int rxouti : 1;\n unsigned int txini : 1;\n} avr32_usbb_uesta4_t;\n\n\n\ntypedef struct avr32_usbb_uesta5_t {\n unsigned int : 1;\n unsigned int byct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int ctrldir : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 1;\n unsigned int errortrans : 1;\n unsigned int dtseq : 2;\n unsigned int shortpacket : 1;\n unsigned int stalledi : 1;\n unsigned int overfi : 1;\n unsigned int nakini : 1;\n unsigned int nakouti : 1;\n unsigned int rxstpi : 1;\n unsigned int rxouti : 1;\n unsigned int txini : 1;\n} avr32_usbb_uesta5_t;\n\n\n\ntypedef struct avr32_usbb_uesta6_t {\n unsigned int : 1;\n unsigned int byct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int ctrldir : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 1;\n unsigned int errortrans : 1;\n unsigned int dtseq : 2;\n unsigned int shortpacket : 1;\n unsigned int stalledi : 1;\n unsigned int overfi : 1;\n unsigned int nakini : 1;\n unsigned int nakouti : 1;\n unsigned int rxstpi : 1;\n unsigned int rxouti : 1;\n unsigned int txini : 1;\n} avr32_usbb_uesta6_t;\n\n\n\ntypedef struct avr32_usbb_uesta0clr_t {\n unsigned int :24;\n unsigned int shortpacketc : 1;\n unsigned int stalledic : 1;\n unsigned int overfic : 1;\n unsigned int nakinic : 1;\n unsigned int nakoutic : 1;\n unsigned int rxstpic : 1;\n unsigned int rxoutic : 1;\n unsigned int txinic : 1;\n} avr32_usbb_uesta0clr_t;\n\n\n\ntypedef struct avr32_usbb_uesta1clr_t {\n unsigned int :24;\n unsigned int shortpacketc : 1;\n unsigned int stalledic : 1;\n unsigned int overfic : 1;\n unsigned int nakinic : 1;\n unsigned int nakoutic : 1;\n unsigned int rxstpic : 1;\n unsigned int rxoutic : 1;\n unsigned int txinic : 1;\n} avr32_usbb_uesta1clr_t;\n\n\n\ntypedef struct avr32_usbb_uesta2clr_t {\n unsigned int :24;\n unsigned int shortpacketc : 1;\n unsigned int stalledic : 1;\n unsigned int overfic : 1;\n unsigned int nakinic : 1;\n unsigned int nakoutic : 1;\n unsigned int rxstpic : 1;\n unsigned int rxoutic : 1;\n unsigned int txinic : 1;\n} avr32_usbb_uesta2clr_t;\n\n\n\ntypedef struct avr32_usbb_uesta3clr_t {\n unsigned int :24;\n unsigned int shortpacketc : 1;\n unsigned int stalledic : 1;\n unsigned int overfic : 1;\n unsigned int nakinic : 1;\n unsigned int nakoutic : 1;\n unsigned int rxstpic : 1;\n unsigned int rxoutic : 1;\n unsigned int txinic : 1;\n} avr32_usbb_uesta3clr_t;\n\n\n\ntypedef struct avr32_usbb_uesta4clr_t {\n unsigned int :24;\n unsigned int shortpacketc : 1;\n unsigned int stalledic : 1;\n unsigned int overfic : 1;\n unsigned int nakinic : 1;\n unsigned int nakoutic : 1;\n unsigned int rxstpic : 1;\n unsigned int rxoutic : 1;\n unsigned int txinic : 1;\n} avr32_usbb_uesta4clr_t;\n\n\n\ntypedef struct avr32_usbb_uesta5clr_t {\n unsigned int :24;\n unsigned int shortpacketc : 1;\n unsigned int stalledic : 1;\n unsigned int overfic : 1;\n unsigned int nakinic : 1;\n unsigned int nakoutic : 1;\n unsigned int rxstpic : 1;\n unsigned int rxoutic : 1;\n unsigned int txinic : 1;\n} avr32_usbb_uesta5clr_t;\n\n\n\ntypedef struct avr32_usbb_uesta6clr_t {\n unsigned int :24;\n unsigned int shortpacketc : 1;\n unsigned int stalledic : 1;\n unsigned int overfic : 1;\n unsigned int nakinic : 1;\n unsigned int nakoutic : 1;\n unsigned int rxstpic : 1;\n unsigned int rxoutic : 1;\n unsigned int txinic : 1;\n} avr32_usbb_uesta6clr_t;\n\n\n\ntypedef struct avr32_usbb_uesta0set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 1;\n unsigned int errortranss : 1;\n unsigned int : 1;\n unsigned int setmdata : 1;\n unsigned int shortpackets : 1;\n unsigned int stalledis : 1;\n unsigned int overfis : 1;\n unsigned int nakinis : 1;\n unsigned int nakoutis : 1;\n unsigned int rxstpis : 1;\n unsigned int rxoutis : 1;\n unsigned int txinis : 1;\n} avr32_usbb_uesta0set_t;\n\n\n\ntypedef struct avr32_usbb_uesta1set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 1;\n unsigned int errortranss : 1;\n unsigned int : 1;\n unsigned int setmdata : 1;\n unsigned int shortpackets : 1;\n unsigned int stalledis : 1;\n unsigned int overfis : 1;\n unsigned int nakinis : 1;\n unsigned int nakoutis : 1;\n unsigned int rxstpis : 1;\n unsigned int rxoutis : 1;\n unsigned int txinis : 1;\n} avr32_usbb_uesta1set_t;\n\n\n\ntypedef struct avr32_usbb_uesta2set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 1;\n unsigned int errortranss : 1;\n unsigned int : 1;\n unsigned int setmdata : 1;\n unsigned int shortpackets : 1;\n unsigned int stalledis : 1;\n unsigned int overfis : 1;\n unsigned int nakinis : 1;\n unsigned int nakoutis : 1;\n unsigned int rxstpis : 1;\n unsigned int rxoutis : 1;\n unsigned int txinis : 1;\n} avr32_usbb_uesta2set_t;\n\n\n\ntypedef struct avr32_usbb_uesta3set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 1;\n unsigned int errortranss : 1;\n unsigned int : 1;\n unsigned int setmdata : 1;\n unsigned int shortpackets : 1;\n unsigned int stalledis : 1;\n unsigned int overfis : 1;\n unsigned int nakinis : 1;\n unsigned int nakoutis : 1;\n unsigned int rxstpis : 1;\n unsigned int rxoutis : 1;\n unsigned int txinis : 1;\n} avr32_usbb_uesta3set_t;\n\n\n\ntypedef struct avr32_usbb_uesta4set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 1;\n unsigned int errortranss : 1;\n unsigned int : 1;\n unsigned int setmdata : 1;\n unsigned int shortpackets : 1;\n unsigned int stalledis : 1;\n unsigned int overfis : 1;\n unsigned int nakinis : 1;\n unsigned int nakoutis : 1;\n unsigned int rxstpis : 1;\n unsigned int rxoutis : 1;\n unsigned int txinis : 1;\n} avr32_usbb_uesta4set_t;\n\n\n\ntypedef struct avr32_usbb_uesta5set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 1;\n unsigned int errortranss : 1;\n unsigned int : 1;\n unsigned int setmdata : 1;\n unsigned int shortpackets : 1;\n unsigned int stalledis : 1;\n unsigned int overfis : 1;\n unsigned int nakinis : 1;\n unsigned int nakoutis : 1;\n unsigned int rxstpis : 1;\n unsigned int rxoutis : 1;\n unsigned int txinis : 1;\n} avr32_usbb_uesta5set_t;\n\n\n\ntypedef struct avr32_usbb_uesta6set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 1;\n unsigned int errortranss : 1;\n unsigned int : 1;\n unsigned int setmdata : 1;\n unsigned int shortpackets : 1;\n unsigned int stalledis : 1;\n unsigned int overfis : 1;\n unsigned int nakinis : 1;\n unsigned int nakoutis : 1;\n unsigned int rxstpis : 1;\n unsigned int rxoutis : 1;\n unsigned int txinis : 1;\n} avr32_usbb_uesta6set_t;\n\n\n\ntypedef struct avr32_usbb_uecon0_t {\n unsigned int :12;\n unsigned int stallrq : 1;\n unsigned int rstdt : 1;\n unsigned int nyetdis : 1;\n unsigned int epdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int killbk : 1;\n unsigned int nbusybke : 1;\n unsigned int : 1;\n unsigned int errortranse : 1;\n unsigned int dataxe : 1;\n unsigned int mdatae : 1;\n unsigned int shortpackete : 1;\n unsigned int stallede : 1;\n unsigned int overfe : 1;\n unsigned int nakine : 1;\n unsigned int nakoute : 1;\n unsigned int rxstpe : 1;\n unsigned int rxoute : 1;\n unsigned int txine : 1;\n} avr32_usbb_uecon0_t;\n\n\n\ntypedef struct avr32_usbb_uecon1_t {\n unsigned int :12;\n unsigned int stallrq : 1;\n unsigned int rstdt : 1;\n unsigned int nyetdis : 1;\n unsigned int epdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int killbk : 1;\n unsigned int nbusybke : 1;\n unsigned int : 1;\n unsigned int errortranse : 1;\n unsigned int dataxe : 1;\n unsigned int mdatae : 1;\n unsigned int shortpackete : 1;\n unsigned int stallede : 1;\n unsigned int overfe : 1;\n unsigned int nakine : 1;\n unsigned int nakoute : 1;\n unsigned int rxstpe : 1;\n unsigned int rxoute : 1;\n unsigned int txine : 1;\n} avr32_usbb_uecon1_t;\n\n\n\ntypedef struct avr32_usbb_uecon2_t {\n unsigned int :12;\n unsigned int stallrq : 1;\n unsigned int rstdt : 1;\n unsigned int nyetdis : 1;\n unsigned int epdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int killbk : 1;\n unsigned int nbusybke : 1;\n unsigned int : 1;\n unsigned int errortranse : 1;\n unsigned int dataxe : 1;\n unsigned int mdatae : 1;\n unsigned int shortpackete : 1;\n unsigned int stallede : 1;\n unsigned int overfe : 1;\n unsigned int nakine : 1;\n unsigned int nakoute : 1;\n unsigned int rxstpe : 1;\n unsigned int rxoute : 1;\n unsigned int txine : 1;\n} avr32_usbb_uecon2_t;\n\n\n\ntypedef struct avr32_usbb_uecon3_t {\n unsigned int :12;\n unsigned int stallrq : 1;\n unsigned int rstdt : 1;\n unsigned int nyetdis : 1;\n unsigned int epdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int killbk : 1;\n unsigned int nbusybke : 1;\n unsigned int : 1;\n unsigned int errortranse : 1;\n unsigned int dataxe : 1;\n unsigned int mdatae : 1;\n unsigned int shortpackete : 1;\n unsigned int stallede : 1;\n unsigned int overfe : 1;\n unsigned int nakine : 1;\n unsigned int nakoute : 1;\n unsigned int rxstpe : 1;\n unsigned int rxoute : 1;\n unsigned int txine : 1;\n} avr32_usbb_uecon3_t;\n\n\n\ntypedef struct avr32_usbb_uecon4_t {\n unsigned int :12;\n unsigned int stallrq : 1;\n unsigned int rstdt : 1;\n unsigned int nyetdis : 1;\n unsigned int epdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int killbk : 1;\n unsigned int nbusybke : 1;\n unsigned int : 1;\n unsigned int errortranse : 1;\n unsigned int dataxe : 1;\n unsigned int mdatae : 1;\n unsigned int shortpackete : 1;\n unsigned int stallede : 1;\n unsigned int overfe : 1;\n unsigned int nakine : 1;\n unsigned int nakoute : 1;\n unsigned int rxstpe : 1;\n unsigned int rxoute : 1;\n unsigned int txine : 1;\n} avr32_usbb_uecon4_t;\n\n\n\ntypedef struct avr32_usbb_uecon5_t {\n unsigned int :12;\n unsigned int stallrq : 1;\n unsigned int rstdt : 1;\n unsigned int nyetdis : 1;\n unsigned int epdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int killbk : 1;\n unsigned int nbusybke : 1;\n unsigned int : 1;\n unsigned int errortranse : 1;\n unsigned int dataxe : 1;\n unsigned int mdatae : 1;\n unsigned int shortpackete : 1;\n unsigned int stallede : 1;\n unsigned int overfe : 1;\n unsigned int nakine : 1;\n unsigned int nakoute : 1;\n unsigned int rxstpe : 1;\n unsigned int rxoute : 1;\n unsigned int txine : 1;\n} avr32_usbb_uecon5_t;\n\n\n\ntypedef struct avr32_usbb_uecon6_t {\n unsigned int :12;\n unsigned int stallrq : 1;\n unsigned int rstdt : 1;\n unsigned int nyetdis : 1;\n unsigned int epdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int killbk : 1;\n unsigned int nbusybke : 1;\n unsigned int : 1;\n unsigned int errortranse : 1;\n unsigned int dataxe : 1;\n unsigned int mdatae : 1;\n unsigned int shortpackete : 1;\n unsigned int stallede : 1;\n unsigned int overfe : 1;\n unsigned int nakine : 1;\n unsigned int nakoute : 1;\n unsigned int rxstpe : 1;\n unsigned int rxoute : 1;\n unsigned int txine : 1;\n} avr32_usbb_uecon6_t;\n\n\n\ntypedef struct avr32_usbb_uecon0set_t {\n unsigned int :12;\n unsigned int stallrqs : 1;\n unsigned int rstdts : 1;\n unsigned int nyetdiss : 1;\n unsigned int epdishdmas : 1;\n unsigned int : 2;\n unsigned int killbks : 1;\n unsigned int nbusybkes : 1;\n unsigned int : 1;\n unsigned int errortranses : 1;\n unsigned int dataxes : 1;\n unsigned int mdataes : 1;\n unsigned int shortpacketes : 1;\n unsigned int stalledes : 1;\n unsigned int overfes : 1;\n unsigned int nakines : 1;\n unsigned int nakoutes : 1;\n unsigned int rxstpes : 1;\n unsigned int rxoutes : 1;\n unsigned int txines : 1;\n} avr32_usbb_uecon0set_t;\n\n\n\ntypedef struct avr32_usbb_uecon1set_t {\n unsigned int :12;\n unsigned int stallrqs : 1;\n unsigned int rstdts : 1;\n unsigned int nyetdiss : 1;\n unsigned int epdishdmas : 1;\n unsigned int : 2;\n unsigned int killbks : 1;\n unsigned int nbusybkes : 1;\n unsigned int : 1;\n unsigned int errortranses : 1;\n unsigned int dataxes : 1;\n unsigned int mdataes : 1;\n unsigned int shortpacketes : 1;\n unsigned int stalledes : 1;\n unsigned int overfes : 1;\n unsigned int nakines : 1;\n unsigned int nakoutes : 1;\n unsigned int rxstpes : 1;\n unsigned int rxoutes : 1;\n unsigned int txines : 1;\n} avr32_usbb_uecon1set_t;\n\n\n\ntypedef struct avr32_usbb_uecon2set_t {\n unsigned int :12;\n unsigned int stallrqs : 1;\n unsigned int rstdts : 1;\n unsigned int nyetdiss : 1;\n unsigned int epdishdmas : 1;\n unsigned int : 2;\n unsigned int killbks : 1;\n unsigned int nbusybkes : 1;\n unsigned int : 1;\n unsigned int errortranses : 1;\n unsigned int dataxes : 1;\n unsigned int mdataes : 1;\n unsigned int shortpacketes : 1;\n unsigned int stalledes : 1;\n unsigned int overfes : 1;\n unsigned int nakines : 1;\n unsigned int nakoutes : 1;\n unsigned int rxstpes : 1;\n unsigned int rxoutes : 1;\n unsigned int txines : 1;\n} avr32_usbb_uecon2set_t;\n\n\n\ntypedef struct avr32_usbb_uecon3set_t {\n unsigned int :12;\n unsigned int stallrqs : 1;\n unsigned int rstdts : 1;\n unsigned int nyetdiss : 1;\n unsigned int epdishdmas : 1;\n unsigned int : 2;\n unsigned int killbks : 1;\n unsigned int nbusybkes : 1;\n unsigned int : 1;\n unsigned int errortranses : 1;\n unsigned int dataxes : 1;\n unsigned int mdataes : 1;\n unsigned int shortpacketes : 1;\n unsigned int stalledes : 1;\n unsigned int overfes : 1;\n unsigned int nakines : 1;\n unsigned int nakoutes : 1;\n unsigned int rxstpes : 1;\n unsigned int rxoutes : 1;\n unsigned int txines : 1;\n} avr32_usbb_uecon3set_t;\n\n\n\ntypedef struct avr32_usbb_uecon4set_t {\n unsigned int :12;\n unsigned int stallrqs : 1;\n unsigned int rstdts : 1;\n unsigned int nyetdiss : 1;\n unsigned int epdishdmas : 1;\n unsigned int : 2;\n unsigned int killbks : 1;\n unsigned int nbusybkes : 1;\n unsigned int : 1;\n unsigned int errortranses : 1;\n unsigned int dataxes : 1;\n unsigned int mdataes : 1;\n unsigned int shortpacketes : 1;\n unsigned int stalledes : 1;\n unsigned int overfes : 1;\n unsigned int nakines : 1;\n unsigned int nakoutes : 1;\n unsigned int rxstpes : 1;\n unsigned int rxoutes : 1;\n unsigned int txines : 1;\n} avr32_usbb_uecon4set_t;\n\n\n\ntypedef struct avr32_usbb_uecon5set_t {\n unsigned int :12;\n unsigned int stallrqs : 1;\n unsigned int rstdts : 1;\n unsigned int nyetdiss : 1;\n unsigned int epdishdmas : 1;\n unsigned int : 2;\n unsigned int killbks : 1;\n unsigned int nbusybkes : 1;\n unsigned int : 1;\n unsigned int errortranses : 1;\n unsigned int dataxes : 1;\n unsigned int mdataes : 1;\n unsigned int shortpacketes : 1;\n unsigned int stalledes : 1;\n unsigned int overfes : 1;\n unsigned int nakines : 1;\n unsigned int nakoutes : 1;\n unsigned int rxstpes : 1;\n unsigned int rxoutes : 1;\n unsigned int txines : 1;\n} avr32_usbb_uecon5set_t;\n\n\n\ntypedef struct avr32_usbb_uecon6set_t {\n unsigned int :12;\n unsigned int stallrqs : 1;\n unsigned int rstdts : 1;\n unsigned int nyetdiss : 1;\n unsigned int epdishdmas : 1;\n unsigned int : 2;\n unsigned int killbks : 1;\n unsigned int nbusybkes : 1;\n unsigned int : 1;\n unsigned int errortranses : 1;\n unsigned int dataxes : 1;\n unsigned int mdataes : 1;\n unsigned int shortpacketes : 1;\n unsigned int stalledes : 1;\n unsigned int overfes : 1;\n unsigned int nakines : 1;\n unsigned int nakoutes : 1;\n unsigned int rxstpes : 1;\n unsigned int rxoutes : 1;\n unsigned int txines : 1;\n} avr32_usbb_uecon6set_t;\n\n\n\ntypedef struct avr32_usbb_uecon0clr_t {\n unsigned int :12;\n unsigned int stallrqc : 1;\n unsigned int : 1;\n unsigned int nyetdisc : 1;\n unsigned int epdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 1;\n unsigned int errortransec : 1;\n unsigned int dataxec : 1;\n unsigned int mdataec : 1;\n unsigned int shortpacketec : 1;\n unsigned int stalledec : 1;\n unsigned int overfec : 1;\n unsigned int nakinec : 1;\n unsigned int nakoutec : 1;\n unsigned int rxstpec : 1;\n unsigned int rxoutec : 1;\n unsigned int txinec : 1;\n} avr32_usbb_uecon0clr_t;\n\n\n\ntypedef struct avr32_usbb_uecon1clr_t {\n unsigned int :12;\n unsigned int stallrqc : 1;\n unsigned int : 1;\n unsigned int nyetdisc : 1;\n unsigned int epdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 1;\n unsigned int errortransec : 1;\n unsigned int dataxec : 1;\n unsigned int mdataec : 1;\n unsigned int shortpacketec : 1;\n unsigned int stalledec : 1;\n unsigned int overfec : 1;\n unsigned int nakinec : 1;\n unsigned int nakoutec : 1;\n unsigned int rxstpec : 1;\n unsigned int rxoutec : 1;\n unsigned int txinec : 1;\n} avr32_usbb_uecon1clr_t;\n\n\n\ntypedef struct avr32_usbb_uecon2clr_t {\n unsigned int :12;\n unsigned int stallrqc : 1;\n unsigned int : 1;\n unsigned int nyetdisc : 1;\n unsigned int epdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 1;\n unsigned int errortransec : 1;\n unsigned int dataxec : 1;\n unsigned int mdataec : 1;\n unsigned int shortpacketec : 1;\n unsigned int stalledec : 1;\n unsigned int overfec : 1;\n unsigned int nakinec : 1;\n unsigned int nakoutec : 1;\n unsigned int rxstpec : 1;\n unsigned int rxoutec : 1;\n unsigned int txinec : 1;\n} avr32_usbb_uecon2clr_t;\n\n\n\ntypedef struct avr32_usbb_uecon3clr_t {\n unsigned int :12;\n unsigned int stallrqc : 1;\n unsigned int : 1;\n unsigned int nyetdisc : 1;\n unsigned int epdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 1;\n unsigned int errortransec : 1;\n unsigned int dataxec : 1;\n unsigned int mdataec : 1;\n unsigned int shortpacketec : 1;\n unsigned int stalledec : 1;\n unsigned int overfec : 1;\n unsigned int nakinec : 1;\n unsigned int nakoutec : 1;\n unsigned int rxstpec : 1;\n unsigned int rxoutec : 1;\n unsigned int txinec : 1;\n} avr32_usbb_uecon3clr_t;\n\n\n\ntypedef struct avr32_usbb_uecon4clr_t {\n unsigned int :12;\n unsigned int stallrqc : 1;\n unsigned int : 1;\n unsigned int nyetdisc : 1;\n unsigned int epdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 1;\n unsigned int errortransec : 1;\n unsigned int dataxec : 1;\n unsigned int mdataec : 1;\n unsigned int shortpacketec : 1;\n unsigned int stalledec : 1;\n unsigned int overfec : 1;\n unsigned int nakinec : 1;\n unsigned int nakoutec : 1;\n unsigned int rxstpec : 1;\n unsigned int rxoutec : 1;\n unsigned int txinec : 1;\n} avr32_usbb_uecon4clr_t;\n\n\n\ntypedef struct avr32_usbb_uecon5clr_t {\n unsigned int :12;\n unsigned int stallrqc : 1;\n unsigned int : 1;\n unsigned int nyetdisc : 1;\n unsigned int epdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 1;\n unsigned int errortransec : 1;\n unsigned int dataxec : 1;\n unsigned int mdataec : 1;\n unsigned int shortpacketec : 1;\n unsigned int stalledec : 1;\n unsigned int overfec : 1;\n unsigned int nakinec : 1;\n unsigned int nakoutec : 1;\n unsigned int rxstpec : 1;\n unsigned int rxoutec : 1;\n unsigned int txinec : 1;\n} avr32_usbb_uecon5clr_t;\n\n\n\ntypedef struct avr32_usbb_uecon6clr_t {\n unsigned int :12;\n unsigned int stallrqc : 1;\n unsigned int : 1;\n unsigned int nyetdisc : 1;\n unsigned int epdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 1;\n unsigned int errortransec : 1;\n unsigned int dataxec : 1;\n unsigned int mdataec : 1;\n unsigned int shortpacketec : 1;\n unsigned int stalledec : 1;\n unsigned int overfec : 1;\n unsigned int nakinec : 1;\n unsigned int nakoutec : 1;\n unsigned int rxstpec : 1;\n unsigned int rxoutec : 1;\n unsigned int txinec : 1;\n} avr32_usbb_uecon6clr_t;\n\n\n\ntypedef struct avr32_usbb_uddma1_nextdesc_t {\n unsigned int nxt_desc_addr :28;\n unsigned int : 4;\n} avr32_usbb_uddma1_nextdesc_t;\n\n\n\ntypedef struct avr32_usbb_uddma1_control_t {\n unsigned int ch_byte_length :16;\n unsigned int : 8;\n unsigned int burst_lock_en : 1;\n unsigned int desc_ld_irq_en : 1;\n unsigned int eobuff_irq_en : 1;\n unsigned int eot_irq_en : 1;\n unsigned int dmaend_en : 1;\n unsigned int buff_close_in_en : 1;\n unsigned int ld_nxt_ch_desc_en : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uddma1_control_t;\n\n\n\ntypedef struct avr32_usbb_uddma1_status_t {\n unsigned int ch_byte_cnt :16;\n unsigned int : 9;\n unsigned int desc_ld_sta : 1;\n unsigned int eoch_buff_sta : 1;\n unsigned int eot_sta : 1;\n unsigned int : 2;\n unsigned int ch_active : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uddma1_status_t;\n\n\n\ntypedef struct avr32_usbb_uddma2_nextdesc_t {\n unsigned int nxt_desc_addr :28;\n unsigned int : 4;\n} avr32_usbb_uddma2_nextdesc_t;\n\n\n\ntypedef struct avr32_usbb_uddma2_control_t {\n unsigned int ch_byte_length :16;\n unsigned int : 8;\n unsigned int burst_lock_en : 1;\n unsigned int desc_ld_irq_en : 1;\n unsigned int eobuff_irq_en : 1;\n unsigned int eot_irq_en : 1;\n unsigned int dmaend_en : 1;\n unsigned int buff_close_in_en : 1;\n unsigned int ld_nxt_ch_desc_en : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uddma2_control_t;\n\n\n\ntypedef struct avr32_usbb_uddma2_status_t {\n unsigned int ch_byte_cnt :16;\n unsigned int : 9;\n unsigned int desc_ld_sta : 1;\n unsigned int eoch_buff_sta : 1;\n unsigned int eot_sta : 1;\n unsigned int : 2;\n unsigned int ch_active : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uddma2_status_t;\n\n\n\ntypedef struct avr32_usbb_uddma3_nextdesc_t {\n unsigned int nxt_desc_addr :28;\n unsigned int : 4;\n} avr32_usbb_uddma3_nextdesc_t;\n\n\n\ntypedef struct avr32_usbb_uddma3_control_t {\n unsigned int ch_byte_length :16;\n unsigned int : 8;\n unsigned int burst_lock_en : 1;\n unsigned int desc_ld_irq_en : 1;\n unsigned int eobuff_irq_en : 1;\n unsigned int eot_irq_en : 1;\n unsigned int dmaend_en : 1;\n unsigned int buff_close_in_en : 1;\n unsigned int ld_nxt_ch_desc_en : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uddma3_control_t;\n\n\n\ntypedef struct avr32_usbb_uddma3_status_t {\n unsigned int ch_byte_cnt :16;\n unsigned int : 9;\n unsigned int desc_ld_sta : 1;\n unsigned int eoch_buff_sta : 1;\n unsigned int eot_sta : 1;\n unsigned int : 2;\n unsigned int ch_active : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uddma3_status_t;\n\n\n\ntypedef struct avr32_usbb_uddma4_nextdesc_t {\n unsigned int nxt_desc_addr :28;\n unsigned int : 4;\n} avr32_usbb_uddma4_nextdesc_t;\n\n\n\ntypedef struct avr32_usbb_uddma4_control_t {\n unsigned int ch_byte_length :16;\n unsigned int : 8;\n unsigned int burst_lock_en : 1;\n unsigned int desc_ld_irq_en : 1;\n unsigned int eobuff_irq_en : 1;\n unsigned int eot_irq_en : 1;\n unsigned int dmaend_en : 1;\n unsigned int buff_close_in_en : 1;\n unsigned int ld_nxt_ch_desc_en : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uddma4_control_t;\n\n\n\ntypedef struct avr32_usbb_uddma4_status_t {\n unsigned int ch_byte_cnt :16;\n unsigned int : 9;\n unsigned int desc_ld_sta : 1;\n unsigned int eoch_buff_sta : 1;\n unsigned int eot_sta : 1;\n unsigned int : 2;\n unsigned int ch_active : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uddma4_status_t;\n\n\n\ntypedef struct avr32_usbb_uddma5_nextdesc_t {\n unsigned int nxt_desc_addr :28;\n unsigned int : 4;\n} avr32_usbb_uddma5_nextdesc_t;\n\n\n\ntypedef struct avr32_usbb_uddma5_control_t {\n unsigned int ch_byte_length :16;\n unsigned int : 8;\n unsigned int burst_lock_en : 1;\n unsigned int desc_ld_irq_en : 1;\n unsigned int eobuff_irq_en : 1;\n unsigned int eot_irq_en : 1;\n unsigned int dmaend_en : 1;\n unsigned int buff_close_in_en : 1;\n unsigned int ld_nxt_ch_desc_en : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uddma5_control_t;\n\n\n\ntypedef struct avr32_usbb_uddma5_status_t {\n unsigned int ch_byte_cnt :16;\n unsigned int : 9;\n unsigned int desc_ld_sta : 1;\n unsigned int eoch_buff_sta : 1;\n unsigned int eot_sta : 1;\n unsigned int : 2;\n unsigned int ch_active : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uddma5_status_t;\n\n\n\ntypedef struct avr32_usbb_uddma6_nextdesc_t {\n unsigned int nxt_desc_addr :28;\n unsigned int : 4;\n} avr32_usbb_uddma6_nextdesc_t;\n\n\n\ntypedef struct avr32_usbb_uddma6_control_t {\n unsigned int ch_byte_length :16;\n unsigned int : 8;\n unsigned int burst_lock_en : 1;\n unsigned int desc_ld_irq_en : 1;\n unsigned int eobuff_irq_en : 1;\n unsigned int eot_irq_en : 1;\n unsigned int dmaend_en : 1;\n unsigned int buff_close_in_en : 1;\n unsigned int ld_nxt_ch_desc_en : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uddma6_control_t;\n\n\n\ntypedef struct avr32_usbb_uddma6_status_t {\n unsigned int ch_byte_cnt :16;\n unsigned int : 9;\n unsigned int desc_ld_sta : 1;\n unsigned int eoch_buff_sta : 1;\n unsigned int eot_sta : 1;\n unsigned int : 2;\n unsigned int ch_active : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uddma6_status_t;\n\n\n\ntypedef struct avr32_usbb_uhcon_t {\n unsigned int :18;\n unsigned int spdconf : 2;\n unsigned int : 1;\n unsigned int resume : 1;\n unsigned int reset : 1;\n unsigned int sofe : 1;\n unsigned int : 8;\n} avr32_usbb_uhcon_t;\n\n\n\ntypedef struct avr32_usbb_uhint_t {\n unsigned int : 1;\n unsigned int dma6int : 1;\n unsigned int dma5int : 1;\n unsigned int dma4int : 1;\n unsigned int dma3int : 1;\n unsigned int dma2int : 1;\n unsigned int dma1int : 1;\n unsigned int :10;\n unsigned int p6int : 1;\n unsigned int p5int : 1;\n unsigned int p4int : 1;\n unsigned int p3int : 1;\n unsigned int p2int : 1;\n unsigned int p1int : 1;\n unsigned int p0int : 1;\n unsigned int : 1;\n unsigned int hwupi : 1;\n unsigned int hsofi : 1;\n unsigned int rxrsmi : 1;\n unsigned int rsmedi : 1;\n unsigned int rsti : 1;\n unsigned int ddisci : 1;\n unsigned int dconni : 1;\n} avr32_usbb_uhint_t;\n\n\n\ntypedef struct avr32_usbb_uhintclr_t {\n unsigned int :25;\n unsigned int hwupic : 1;\n unsigned int hsofic : 1;\n unsigned int rxrsmic : 1;\n unsigned int rsmedic : 1;\n unsigned int rstic : 1;\n unsigned int ddiscic : 1;\n unsigned int dconnic : 1;\n} avr32_usbb_uhintclr_t;\n\n\n\ntypedef struct avr32_usbb_uhintset_t {\n unsigned int : 1;\n unsigned int dma6ints : 1;\n unsigned int dma5ints : 1;\n unsigned int dma4ints : 1;\n unsigned int dma3ints : 1;\n unsigned int dma2ints : 1;\n unsigned int dma1ints : 1;\n unsigned int :18;\n unsigned int hwupis : 1;\n unsigned int hsofis : 1;\n unsigned int rxrsmis : 1;\n unsigned int rsmedis : 1;\n unsigned int rstis : 1;\n unsigned int ddiscis : 1;\n unsigned int dconnis : 1;\n} avr32_usbb_uhintset_t;\n\n\n\ntypedef struct avr32_usbb_uhinte_t {\n unsigned int : 1;\n unsigned int dma6inte : 1;\n unsigned int dma5inte : 1;\n unsigned int dma4inte : 1;\n unsigned int dma3inte : 1;\n unsigned int dma2inte : 1;\n unsigned int dma1inte : 1;\n unsigned int :10;\n unsigned int p6inte : 1;\n unsigned int p5inte : 1;\n unsigned int p4inte : 1;\n unsigned int p3inte : 1;\n unsigned int p2inte : 1;\n unsigned int p1inte : 1;\n unsigned int p0inte : 1;\n unsigned int : 1;\n unsigned int hwupie : 1;\n unsigned int hsofie : 1;\n unsigned int rxrsmie : 1;\n unsigned int rsmedie : 1;\n unsigned int rstie : 1;\n unsigned int ddiscie : 1;\n unsigned int dconnie : 1;\n} avr32_usbb_uhinte_t;\n\n\n\ntypedef struct avr32_usbb_uhinteclr_t {\n unsigned int : 1;\n unsigned int dma6intec : 1;\n unsigned int dma5intec : 1;\n unsigned int dma4intec : 1;\n unsigned int dma3intec : 1;\n unsigned int dma2intec : 1;\n unsigned int dma1intec : 1;\n unsigned int :10;\n unsigned int p6intec : 1;\n unsigned int p5intec : 1;\n unsigned int p4intec : 1;\n unsigned int p3intec : 1;\n unsigned int p2intec : 1;\n unsigned int p1intec : 1;\n unsigned int p0intec : 1;\n unsigned int : 1;\n unsigned int hwupiec : 1;\n unsigned int hsofiec : 1;\n unsigned int rxrsmiec : 1;\n unsigned int rsmediec : 1;\n unsigned int rstiec : 1;\n unsigned int ddisciec : 1;\n unsigned int dconniec : 1;\n} avr32_usbb_uhinteclr_t;\n\n\n\ntypedef struct avr32_usbb_uhinteset_t {\n unsigned int : 1;\n unsigned int dma6intes : 1;\n unsigned int dma5intes : 1;\n unsigned int dma4intes : 1;\n unsigned int dma3intes : 1;\n unsigned int dma2intes : 1;\n unsigned int dma1intes : 1;\n unsigned int :10;\n unsigned int p6intes : 1;\n unsigned int p5intes : 1;\n unsigned int p4intes : 1;\n unsigned int p3intes : 1;\n unsigned int p2intes : 1;\n unsigned int p1intes : 1;\n unsigned int p0intes : 1;\n unsigned int : 1;\n unsigned int hwupies : 1;\n unsigned int hsofies : 1;\n unsigned int rxrsmies : 1;\n unsigned int rsmedies : 1;\n unsigned int rsties : 1;\n unsigned int ddiscies : 1;\n unsigned int dconnies : 1;\n} avr32_usbb_uhinteset_t;\n\n\n\ntypedef struct avr32_usbb_uprst_t {\n unsigned int : 9;\n unsigned int prst6 : 1;\n unsigned int prst5 : 1;\n unsigned int prst4 : 1;\n unsigned int prst3 : 1;\n unsigned int prst2 : 1;\n unsigned int prst1 : 1;\n unsigned int prst0 : 1;\n unsigned int : 9;\n unsigned int pen6 : 1;\n unsigned int pen5 : 1;\n unsigned int pen4 : 1;\n unsigned int pen3 : 1;\n unsigned int pen2 : 1;\n unsigned int pen1 : 1;\n unsigned int pen0 : 1;\n} avr32_usbb_uprst_t;\n\n\n\ntypedef struct avr32_usbb_uhfnum_t {\n unsigned int : 8;\n unsigned int flenhigh : 8;\n unsigned int : 2;\n unsigned int fnum :11;\n unsigned int mfnum : 3;\n} avr32_usbb_uhfnum_t;\n\n\n\ntypedef struct avr32_usbb_uhaddr1_t {\n unsigned int : 1;\n unsigned int uhaddr_p3 : 7;\n unsigned int : 1;\n unsigned int uhaddr_p2 : 7;\n unsigned int : 1;\n unsigned int uhaddr_p1 : 7;\n unsigned int : 1;\n unsigned int uhaddr_p0 : 7;\n} avr32_usbb_uhaddr1_t;\n\n\n\ntypedef struct avr32_usbb_uhaddr2_t {\n unsigned int : 1;\n unsigned int uhaddr_p7 : 7;\n unsigned int : 1;\n unsigned int uhaddr_p6 : 7;\n unsigned int : 1;\n unsigned int uhaddr_p5 : 7;\n unsigned int : 1;\n unsigned int uhaddr_p4 : 7;\n} avr32_usbb_uhaddr2_t;\n\n\n\ntypedef struct avr32_usbb_uhaddr3_t {\n unsigned int : 1;\n unsigned int uhaddr_p11 : 7;\n unsigned int : 1;\n unsigned int uhaddr_p10 : 7;\n unsigned int : 1;\n unsigned int uhaddr_p9 : 7;\n unsigned int : 1;\n unsigned int uhaddr_p8 : 7;\n} avr32_usbb_uhaddr3_t;\n\n\n\ntypedef struct avr32_usbb_upcfg0_t {\n unsigned int intfrq : 8;\n unsigned int datasizerdwr : 2;\n unsigned int : 1;\n unsigned int pingen : 1;\n unsigned int pepnum : 4;\n unsigned int : 2;\n unsigned int ptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int ptoken : 2;\n unsigned int : 1;\n unsigned int psize : 3;\n unsigned int pbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_upcfg0_t;\n\n\n\ntypedef struct avr32_usbb_upcfg1_t {\n unsigned int intfrq : 8;\n unsigned int datasizerdwr : 2;\n unsigned int : 1;\n unsigned int pingen : 1;\n unsigned int pepnum : 4;\n unsigned int : 2;\n unsigned int ptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int ptoken : 2;\n unsigned int : 1;\n unsigned int psize : 3;\n unsigned int pbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_upcfg1_t;\n\n\n\ntypedef struct avr32_usbb_upcfg2_t {\n unsigned int intfrq : 8;\n unsigned int datasizerdwr : 2;\n unsigned int : 1;\n unsigned int pingen : 1;\n unsigned int pepnum : 4;\n unsigned int : 2;\n unsigned int ptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int ptoken : 2;\n unsigned int : 1;\n unsigned int psize : 3;\n unsigned int pbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_upcfg2_t;\n\n\n\ntypedef struct avr32_usbb_upcfg3_t {\n unsigned int intfrq : 8;\n unsigned int datasizerdwr : 2;\n unsigned int : 1;\n unsigned int pingen : 1;\n unsigned int pepnum : 4;\n unsigned int : 2;\n unsigned int ptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int ptoken : 2;\n unsigned int : 1;\n unsigned int psize : 3;\n unsigned int pbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_upcfg3_t;\n\n\n\ntypedef struct avr32_usbb_upcfg4_t {\n unsigned int intfrq : 8;\n unsigned int datasizerdwr : 2;\n unsigned int : 1;\n unsigned int pingen : 1;\n unsigned int pepnum : 4;\n unsigned int : 2;\n unsigned int ptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int ptoken : 2;\n unsigned int : 1;\n unsigned int psize : 3;\n unsigned int pbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_upcfg4_t;\n\n\n\ntypedef struct avr32_usbb_upcfg5_t {\n unsigned int intfrq : 8;\n unsigned int datasizerdwr : 2;\n unsigned int : 1;\n unsigned int pingen : 1;\n unsigned int pepnum : 4;\n unsigned int : 2;\n unsigned int ptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int ptoken : 2;\n unsigned int : 1;\n unsigned int psize : 3;\n unsigned int pbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_upcfg5_t;\n\n\n\ntypedef struct avr32_usbb_upcfg6_t {\n unsigned int intfrq : 8;\n unsigned int datasizerdwr : 2;\n unsigned int : 1;\n unsigned int pingen : 1;\n unsigned int pepnum : 4;\n unsigned int : 2;\n unsigned int ptype : 2;\n unsigned int : 1;\n unsigned int autosw : 1;\n unsigned int ptoken : 2;\n unsigned int : 1;\n unsigned int psize : 3;\n unsigned int pbk : 2;\n unsigned int alloc : 1;\n unsigned int : 1;\n} avr32_usbb_upcfg6_t;\n\n\n\ntypedef struct avr32_usbb_upsta0_t {\n unsigned int : 1;\n unsigned int pbyct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 2;\n unsigned int dtseq : 2;\n unsigned int shortpacketi : 1;\n unsigned int rxstalldi : 1;\n unsigned int overfi : 1;\n unsigned int nakedi : 1;\n unsigned int perri : 1;\n unsigned int txstpi : 1;\n unsigned int txouti : 1;\n unsigned int rxini : 1;\n} avr32_usbb_upsta0_t;\n\n\n\ntypedef struct avr32_usbb_upsta1_t {\n unsigned int : 1;\n unsigned int pbyct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 2;\n unsigned int dtseq : 2;\n unsigned int shortpacketi : 1;\n unsigned int rxstalldi : 1;\n unsigned int overfi : 1;\n unsigned int nakedi : 1;\n unsigned int perri : 1;\n unsigned int txstpi : 1;\n unsigned int txouti : 1;\n unsigned int rxini : 1;\n} avr32_usbb_upsta1_t;\n\n\n\ntypedef struct avr32_usbb_upsta2_t {\n unsigned int : 1;\n unsigned int pbyct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 2;\n unsigned int dtseq : 2;\n unsigned int shortpacketi : 1;\n unsigned int rxstalldi : 1;\n unsigned int overfi : 1;\n unsigned int nakedi : 1;\n unsigned int perri : 1;\n unsigned int txstpi : 1;\n unsigned int txouti : 1;\n unsigned int rxini : 1;\n} avr32_usbb_upsta2_t;\n\n\n\ntypedef struct avr32_usbb_upsta3_t {\n unsigned int : 1;\n unsigned int pbyct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 2;\n unsigned int dtseq : 2;\n unsigned int shortpacketi : 1;\n unsigned int rxstalldi : 1;\n unsigned int overfi : 1;\n unsigned int nakedi : 1;\n unsigned int perri : 1;\n unsigned int txstpi : 1;\n unsigned int txouti : 1;\n unsigned int rxini : 1;\n} avr32_usbb_upsta3_t;\n\n\n\ntypedef struct avr32_usbb_upsta4_t {\n unsigned int : 1;\n unsigned int pbyct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 2;\n unsigned int dtseq : 2;\n unsigned int shortpacketi : 1;\n unsigned int rxstalldi : 1;\n unsigned int overfi : 1;\n unsigned int nakedi : 1;\n unsigned int perri : 1;\n unsigned int txstpi : 1;\n unsigned int txouti : 1;\n unsigned int rxini : 1;\n} avr32_usbb_upsta4_t;\n\n\n\ntypedef struct avr32_usbb_upsta5_t {\n unsigned int : 1;\n unsigned int pbyct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 2;\n unsigned int dtseq : 2;\n unsigned int shortpacketi : 1;\n unsigned int rxstalldi : 1;\n unsigned int overfi : 1;\n unsigned int nakedi : 1;\n unsigned int perri : 1;\n unsigned int txstpi : 1;\n unsigned int txouti : 1;\n unsigned int rxini : 1;\n} avr32_usbb_upsta5_t;\n\n\n\ntypedef struct avr32_usbb_upsta6_t {\n unsigned int : 1;\n unsigned int pbyct :11;\n unsigned int : 1;\n unsigned int cfgok : 1;\n unsigned int : 1;\n unsigned int rwall : 1;\n unsigned int currbk : 2;\n unsigned int nbusybk : 2;\n unsigned int : 2;\n unsigned int dtseq : 2;\n unsigned int shortpacketi : 1;\n unsigned int rxstalldi : 1;\n unsigned int overfi : 1;\n unsigned int nakedi : 1;\n unsigned int perri : 1;\n unsigned int txstpi : 1;\n unsigned int txouti : 1;\n unsigned int rxini : 1;\n} avr32_usbb_upsta6_t;\n\n\n\ntypedef struct avr32_usbb_upsta0clr_t {\n unsigned int :24;\n unsigned int shortpacketic : 1;\n unsigned int rxstalldic : 1;\n unsigned int overfic : 1;\n unsigned int nakedic : 1;\n unsigned int : 1;\n unsigned int txstpic : 1;\n unsigned int txoutic : 1;\n unsigned int rxinic : 1;\n} avr32_usbb_upsta0clr_t;\n\n\n\ntypedef struct avr32_usbb_upsta1clr_t {\n unsigned int :24;\n unsigned int shortpacketic : 1;\n unsigned int rxstalldic : 1;\n unsigned int overfic : 1;\n unsigned int nakedic : 1;\n unsigned int : 1;\n unsigned int txstpic : 1;\n unsigned int txoutic : 1;\n unsigned int rxinic : 1;\n} avr32_usbb_upsta1clr_t;\n\n\n\ntypedef struct avr32_usbb_upsta2clr_t {\n unsigned int :24;\n unsigned int shortpacketic : 1;\n unsigned int rxstalldic : 1;\n unsigned int overfic : 1;\n unsigned int nakedic : 1;\n unsigned int : 1;\n unsigned int txstpic : 1;\n unsigned int txoutic : 1;\n unsigned int rxinic : 1;\n} avr32_usbb_upsta2clr_t;\n\n\n\ntypedef struct avr32_usbb_upsta3clr_t {\n unsigned int :24;\n unsigned int shortpacketic : 1;\n unsigned int rxstalldic : 1;\n unsigned int overfic : 1;\n unsigned int nakedic : 1;\n unsigned int : 1;\n unsigned int txstpic : 1;\n unsigned int txoutic : 1;\n unsigned int rxinic : 1;\n} avr32_usbb_upsta3clr_t;\n\n\n\ntypedef struct avr32_usbb_upsta4clr_t {\n unsigned int :24;\n unsigned int shortpacketic : 1;\n unsigned int rxstalldic : 1;\n unsigned int overfic : 1;\n unsigned int nakedic : 1;\n unsigned int : 1;\n unsigned int txstpic : 1;\n unsigned int txoutic : 1;\n unsigned int rxinic : 1;\n} avr32_usbb_upsta4clr_t;\n\n\n\ntypedef struct avr32_usbb_upsta5clr_t {\n unsigned int :24;\n unsigned int shortpacketic : 1;\n unsigned int rxstalldic : 1;\n unsigned int overfic : 1;\n unsigned int nakedic : 1;\n unsigned int : 1;\n unsigned int txstpic : 1;\n unsigned int txoutic : 1;\n unsigned int rxinic : 1;\n} avr32_usbb_upsta5clr_t;\n\n\n\ntypedef struct avr32_usbb_upsta6clr_t {\n unsigned int :24;\n unsigned int shortpacketic : 1;\n unsigned int rxstalldic : 1;\n unsigned int overfic : 1;\n unsigned int nakedic : 1;\n unsigned int : 1;\n unsigned int txstpic : 1;\n unsigned int txoutic : 1;\n unsigned int rxinic : 1;\n} avr32_usbb_upsta6clr_t;\n\n\n\ntypedef struct avr32_usbb_upsta0set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 4;\n unsigned int shortpacketis : 1;\n unsigned int rxstalldis : 1;\n unsigned int overfis : 1;\n unsigned int nakedis : 1;\n unsigned int perris : 1;\n unsigned int txstpis : 1;\n unsigned int txoutis : 1;\n unsigned int rxinis : 1;\n} avr32_usbb_upsta0set_t;\n\n\n\ntypedef struct avr32_usbb_upsta1set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 4;\n unsigned int shortpacketis : 1;\n unsigned int rxstalldis : 1;\n unsigned int overfis : 1;\n unsigned int nakedis : 1;\n unsigned int perris : 1;\n unsigned int txstpis : 1;\n unsigned int txoutis : 1;\n unsigned int rxinis : 1;\n} avr32_usbb_upsta1set_t;\n\n\n\ntypedef struct avr32_usbb_upsta2set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 4;\n unsigned int shortpacketis : 1;\n unsigned int rxstalldis : 1;\n unsigned int overfis : 1;\n unsigned int nakedis : 1;\n unsigned int perris : 1;\n unsigned int txstpis : 1;\n unsigned int txoutis : 1;\n unsigned int rxinis : 1;\n} avr32_usbb_upsta2set_t;\n\n\n\ntypedef struct avr32_usbb_upsta3set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 4;\n unsigned int shortpacketis : 1;\n unsigned int rxstalldis : 1;\n unsigned int overfis : 1;\n unsigned int nakedis : 1;\n unsigned int perris : 1;\n unsigned int txstpis : 1;\n unsigned int txoutis : 1;\n unsigned int rxinis : 1;\n} avr32_usbb_upsta3set_t;\n\n\n\ntypedef struct avr32_usbb_upsta4set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 4;\n unsigned int shortpacketis : 1;\n unsigned int rxstalldis : 1;\n unsigned int overfis : 1;\n unsigned int nakedis : 1;\n unsigned int perris : 1;\n unsigned int txstpis : 1;\n unsigned int txoutis : 1;\n unsigned int rxinis : 1;\n} avr32_usbb_upsta4set_t;\n\n\n\ntypedef struct avr32_usbb_upsta5set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 4;\n unsigned int shortpacketis : 1;\n unsigned int rxstalldis : 1;\n unsigned int overfis : 1;\n unsigned int nakedis : 1;\n unsigned int perris : 1;\n unsigned int txstpis : 1;\n unsigned int txoutis : 1;\n unsigned int rxinis : 1;\n} avr32_usbb_upsta5set_t;\n\n\n\ntypedef struct avr32_usbb_upsta6set_t {\n unsigned int :19;\n unsigned int nbusybks : 1;\n unsigned int : 4;\n unsigned int shortpacketis : 1;\n unsigned int rxstalldis : 1;\n unsigned int overfis : 1;\n unsigned int nakedis : 1;\n unsigned int perris : 1;\n unsigned int txstpis : 1;\n unsigned int txoutis : 1;\n unsigned int rxinis : 1;\n} avr32_usbb_upsta6set_t;\n\n\n\ntypedef struct avr32_usbb_upcon0_t {\n unsigned int :13;\n unsigned int rstdt : 1;\n unsigned int pfreeze : 1;\n unsigned int pdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int : 1;\n unsigned int nbusybke : 1;\n unsigned int : 4;\n unsigned int shortpacketie : 1;\n unsigned int rxstallde : 1;\n unsigned int overfie : 1;\n unsigned int nakede : 1;\n unsigned int perre : 1;\n unsigned int txstpe : 1;\n unsigned int txoute : 1;\n unsigned int rxine : 1;\n} avr32_usbb_upcon0_t;\n\n\n\ntypedef struct avr32_usbb_upcon1_t {\n unsigned int :13;\n unsigned int rstdt : 1;\n unsigned int pfreeze : 1;\n unsigned int pdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int : 1;\n unsigned int nbusybke : 1;\n unsigned int : 4;\n unsigned int shortpacketie : 1;\n unsigned int rxstallde : 1;\n unsigned int overfie : 1;\n unsigned int nakede : 1;\n unsigned int perre : 1;\n unsigned int txstpe : 1;\n unsigned int txoute : 1;\n unsigned int rxine : 1;\n} avr32_usbb_upcon1_t;\n\n\n\ntypedef struct avr32_usbb_upcon2_t {\n unsigned int :13;\n unsigned int rstdt : 1;\n unsigned int pfreeze : 1;\n unsigned int pdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int : 1;\n unsigned int nbusybke : 1;\n unsigned int : 4;\n unsigned int shortpacketie : 1;\n unsigned int rxstallde : 1;\n unsigned int overfie : 1;\n unsigned int nakede : 1;\n unsigned int perre : 1;\n unsigned int txstpe : 1;\n unsigned int txoute : 1;\n unsigned int rxine : 1;\n} avr32_usbb_upcon2_t;\n\n\n\ntypedef struct avr32_usbb_upcon3_t {\n unsigned int :13;\n unsigned int rstdt : 1;\n unsigned int pfreeze : 1;\n unsigned int pdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int : 1;\n unsigned int nbusybke : 1;\n unsigned int : 4;\n unsigned int shortpacketie : 1;\n unsigned int rxstallde : 1;\n unsigned int overfie : 1;\n unsigned int nakede : 1;\n unsigned int perre : 1;\n unsigned int txstpe : 1;\n unsigned int txoute : 1;\n unsigned int rxine : 1;\n} avr32_usbb_upcon3_t;\n\n\n\ntypedef struct avr32_usbb_upcon4_t {\n unsigned int :13;\n unsigned int rstdt : 1;\n unsigned int pfreeze : 1;\n unsigned int pdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int : 1;\n unsigned int nbusybke : 1;\n unsigned int : 4;\n unsigned int shortpacketie : 1;\n unsigned int rxstallde : 1;\n unsigned int overfie : 1;\n unsigned int nakede : 1;\n unsigned int perre : 1;\n unsigned int txstpe : 1;\n unsigned int txoute : 1;\n unsigned int rxine : 1;\n} avr32_usbb_upcon4_t;\n\n\n\ntypedef struct avr32_usbb_upcon5_t {\n unsigned int :13;\n unsigned int rstdt : 1;\n unsigned int pfreeze : 1;\n unsigned int pdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int : 1;\n unsigned int nbusybke : 1;\n unsigned int : 4;\n unsigned int shortpacketie : 1;\n unsigned int rxstallde : 1;\n unsigned int overfie : 1;\n unsigned int nakede : 1;\n unsigned int perre : 1;\n unsigned int txstpe : 1;\n unsigned int txoute : 1;\n unsigned int rxine : 1;\n} avr32_usbb_upcon5_t;\n\n\n\ntypedef struct avr32_usbb_upcon6_t {\n unsigned int :13;\n unsigned int rstdt : 1;\n unsigned int pfreeze : 1;\n unsigned int pdishdma : 1;\n unsigned int : 1;\n unsigned int fifocon : 1;\n unsigned int : 1;\n unsigned int nbusybke : 1;\n unsigned int : 4;\n unsigned int shortpacketie : 1;\n unsigned int rxstallde : 1;\n unsigned int overfie : 1;\n unsigned int nakede : 1;\n unsigned int perre : 1;\n unsigned int txstpe : 1;\n unsigned int txoute : 1;\n unsigned int rxine : 1;\n} avr32_usbb_upcon6_t;\n\n\n\ntypedef struct avr32_usbb_upcon0set_t {\n unsigned int :13;\n unsigned int rstdts : 1;\n unsigned int pfreezes : 1;\n unsigned int pdishdmas : 1;\n unsigned int : 3;\n unsigned int nbusybkes : 1;\n unsigned int : 4;\n unsigned int shortpacketies : 1;\n unsigned int rxstalldes : 1;\n unsigned int overfies : 1;\n unsigned int nakedes : 1;\n unsigned int perres : 1;\n unsigned int txstpes : 1;\n unsigned int txoutes : 1;\n unsigned int rxines : 1;\n} avr32_usbb_upcon0set_t;\n\n\n\ntypedef struct avr32_usbb_upcon1set_t {\n unsigned int :13;\n unsigned int rstdts : 1;\n unsigned int pfreezes : 1;\n unsigned int pdishdmas : 1;\n unsigned int : 3;\n unsigned int nbusybkes : 1;\n unsigned int : 4;\n unsigned int shortpacketies : 1;\n unsigned int rxstalldes : 1;\n unsigned int overfies : 1;\n unsigned int nakedes : 1;\n unsigned int perres : 1;\n unsigned int txstpes : 1;\n unsigned int txoutes : 1;\n unsigned int rxines : 1;\n} avr32_usbb_upcon1set_t;\n\n\n\ntypedef struct avr32_usbb_upcon2set_t {\n unsigned int :13;\n unsigned int rstdts : 1;\n unsigned int pfreezes : 1;\n unsigned int pdishdmas : 1;\n unsigned int : 3;\n unsigned int nbusybkes : 1;\n unsigned int : 4;\n unsigned int shortpacketies : 1;\n unsigned int rxstalldes : 1;\n unsigned int overfies : 1;\n unsigned int nakedes : 1;\n unsigned int perres : 1;\n unsigned int txstpes : 1;\n unsigned int txoutes : 1;\n unsigned int rxines : 1;\n} avr32_usbb_upcon2set_t;\n\n\n\ntypedef struct avr32_usbb_upcon3set_t {\n unsigned int :13;\n unsigned int rstdts : 1;\n unsigned int pfreezes : 1;\n unsigned int pdishdmas : 1;\n unsigned int : 3;\n unsigned int nbusybkes : 1;\n unsigned int : 4;\n unsigned int shortpacketies : 1;\n unsigned int rxstalldes : 1;\n unsigned int overfies : 1;\n unsigned int nakedes : 1;\n unsigned int perres : 1;\n unsigned int txstpes : 1;\n unsigned int txoutes : 1;\n unsigned int rxines : 1;\n} avr32_usbb_upcon3set_t;\n\n\n\ntypedef struct avr32_usbb_upcon4set_t {\n unsigned int :13;\n unsigned int rstdts : 1;\n unsigned int pfreezes : 1;\n unsigned int pdishdmas : 1;\n unsigned int : 3;\n unsigned int nbusybkes : 1;\n unsigned int : 4;\n unsigned int shortpacketies : 1;\n unsigned int rxstalldes : 1;\n unsigned int overfies : 1;\n unsigned int nakedes : 1;\n unsigned int perres : 1;\n unsigned int txstpes : 1;\n unsigned int txoutes : 1;\n unsigned int rxines : 1;\n} avr32_usbb_upcon4set_t;\n\n\n\ntypedef struct avr32_usbb_upcon5set_t {\n unsigned int :13;\n unsigned int rstdts : 1;\n unsigned int pfreezes : 1;\n unsigned int pdishdmas : 1;\n unsigned int : 3;\n unsigned int nbusybkes : 1;\n unsigned int : 4;\n unsigned int shortpacketies : 1;\n unsigned int rxstalldes : 1;\n unsigned int overfies : 1;\n unsigned int nakedes : 1;\n unsigned int perres : 1;\n unsigned int txstpes : 1;\n unsigned int txoutes : 1;\n unsigned int rxines : 1;\n} avr32_usbb_upcon5set_t;\n\n\n\ntypedef struct avr32_usbb_upcon6set_t {\n unsigned int :13;\n unsigned int rstdts : 1;\n unsigned int pfreezes : 1;\n unsigned int pdishdmas : 1;\n unsigned int : 3;\n unsigned int nbusybkes : 1;\n unsigned int : 4;\n unsigned int shortpacketies : 1;\n unsigned int rxstalldes : 1;\n unsigned int overfies : 1;\n unsigned int nakedes : 1;\n unsigned int perres : 1;\n unsigned int txstpes : 1;\n unsigned int txoutes : 1;\n unsigned int rxines : 1;\n} avr32_usbb_upcon6set_t;\n\n\n\ntypedef struct avr32_usbb_upcon0clr_t {\n unsigned int :14;\n unsigned int pfreezec : 1;\n unsigned int pdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 4;\n unsigned int shortpacketiec : 1;\n unsigned int rxstalldec : 1;\n unsigned int overfiec : 1;\n unsigned int nakedec : 1;\n unsigned int perrec : 1;\n unsigned int txstpec : 1;\n unsigned int txoutec : 1;\n unsigned int rxinec : 1;\n} avr32_usbb_upcon0clr_t;\n\n\n\ntypedef struct avr32_usbb_upcon1clr_t {\n unsigned int :14;\n unsigned int pfreezec : 1;\n unsigned int pdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 4;\n unsigned int shortpacketiec : 1;\n unsigned int rxstalldec : 1;\n unsigned int overfiec : 1;\n unsigned int nakedec : 1;\n unsigned int perrec : 1;\n unsigned int txstpec : 1;\n unsigned int txoutec : 1;\n unsigned int rxinec : 1;\n} avr32_usbb_upcon1clr_t;\n\n\n\ntypedef struct avr32_usbb_upcon2clr_t {\n unsigned int :14;\n unsigned int pfreezec : 1;\n unsigned int pdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 4;\n unsigned int shortpacketiec : 1;\n unsigned int rxstalldec : 1;\n unsigned int overfiec : 1;\n unsigned int nakedec : 1;\n unsigned int perrec : 1;\n unsigned int txstpec : 1;\n unsigned int txoutec : 1;\n unsigned int rxinec : 1;\n} avr32_usbb_upcon2clr_t;\n\n\n\ntypedef struct avr32_usbb_upcon3clr_t {\n unsigned int :14;\n unsigned int pfreezec : 1;\n unsigned int pdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 4;\n unsigned int shortpacketiec : 1;\n unsigned int rxstalldec : 1;\n unsigned int overfiec : 1;\n unsigned int nakedec : 1;\n unsigned int perrec : 1;\n unsigned int txstpec : 1;\n unsigned int txoutec : 1;\n unsigned int rxinec : 1;\n} avr32_usbb_upcon3clr_t;\n\n\n\ntypedef struct avr32_usbb_upcon4clr_t {\n unsigned int :14;\n unsigned int pfreezec : 1;\n unsigned int pdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 4;\n unsigned int shortpacketiec : 1;\n unsigned int rxstalldec : 1;\n unsigned int overfiec : 1;\n unsigned int nakedec : 1;\n unsigned int perrec : 1;\n unsigned int txstpec : 1;\n unsigned int txoutec : 1;\n unsigned int rxinec : 1;\n} avr32_usbb_upcon4clr_t;\n\n\n\ntypedef struct avr32_usbb_upcon5clr_t {\n unsigned int :14;\n unsigned int pfreezec : 1;\n unsigned int pdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 4;\n unsigned int shortpacketiec : 1;\n unsigned int rxstalldec : 1;\n unsigned int overfiec : 1;\n unsigned int nakedec : 1;\n unsigned int perrec : 1;\n unsigned int txstpec : 1;\n unsigned int txoutec : 1;\n unsigned int rxinec : 1;\n} avr32_usbb_upcon5clr_t;\n\n\n\ntypedef struct avr32_usbb_upcon6clr_t {\n unsigned int :14;\n unsigned int pfreezec : 1;\n unsigned int pdishdmac : 1;\n unsigned int : 1;\n unsigned int fifoconc : 1;\n unsigned int : 1;\n unsigned int nbusybkec : 1;\n unsigned int : 4;\n unsigned int shortpacketiec : 1;\n unsigned int rxstalldec : 1;\n unsigned int overfiec : 1;\n unsigned int nakedec : 1;\n unsigned int perrec : 1;\n unsigned int txstpec : 1;\n unsigned int txoutec : 1;\n unsigned int rxinec : 1;\n} avr32_usbb_upcon6clr_t;\n\n\n\ntypedef struct avr32_usbb_upinrq0_t {\n unsigned int :23;\n unsigned int inmode : 1;\n unsigned int inrq : 8;\n} avr32_usbb_upinrq0_t;\n\n\n\ntypedef struct avr32_usbb_upinrq1_t {\n unsigned int :23;\n unsigned int inmode : 1;\n unsigned int inrq : 8;\n} avr32_usbb_upinrq1_t;\n\n\n\ntypedef struct avr32_usbb_upinrq2_t {\n unsigned int :23;\n unsigned int inmode : 1;\n unsigned int inrq : 8;\n} avr32_usbb_upinrq2_t;\n\n\n\ntypedef struct avr32_usbb_upinrq3_t {\n unsigned int :23;\n unsigned int inmode : 1;\n unsigned int inrq : 8;\n} avr32_usbb_upinrq3_t;\n\n\n\ntypedef struct avr32_usbb_upinrq4_t {\n unsigned int :23;\n unsigned int inmode : 1;\n unsigned int inrq : 8;\n} avr32_usbb_upinrq4_t;\n\n\n\ntypedef struct avr32_usbb_upinrq5_t {\n unsigned int :23;\n unsigned int inmode : 1;\n unsigned int inrq : 8;\n} avr32_usbb_upinrq5_t;\n\n\n\ntypedef struct avr32_usbb_upinrq6_t {\n unsigned int :23;\n unsigned int inmode : 1;\n unsigned int inrq : 8;\n} avr32_usbb_upinrq6_t;\n\n\n\ntypedef struct avr32_usbb_uperr0_t {\n unsigned int :25;\n unsigned int counter : 2;\n unsigned int crc16 : 1;\n unsigned int timeout : 1;\n unsigned int pid : 1;\n unsigned int datapid : 1;\n unsigned int datatgl : 1;\n} avr32_usbb_uperr0_t;\n\n\n\ntypedef struct avr32_usbb_uperr1_t {\n unsigned int :25;\n unsigned int counter : 2;\n unsigned int crc16 : 1;\n unsigned int timeout : 1;\n unsigned int pid : 1;\n unsigned int datapid : 1;\n unsigned int datatgl : 1;\n} avr32_usbb_uperr1_t;\n\n\n\ntypedef struct avr32_usbb_uperr2_t {\n unsigned int :25;\n unsigned int counter : 2;\n unsigned int crc16 : 1;\n unsigned int timeout : 1;\n unsigned int pid : 1;\n unsigned int datapid : 1;\n unsigned int datatgl : 1;\n} avr32_usbb_uperr2_t;\n\n\n\ntypedef struct avr32_usbb_uperr3_t {\n unsigned int :25;\n unsigned int counter : 2;\n unsigned int crc16 : 1;\n unsigned int timeout : 1;\n unsigned int pid : 1;\n unsigned int datapid : 1;\n unsigned int datatgl : 1;\n} avr32_usbb_uperr3_t;\n\n\n\ntypedef struct avr32_usbb_uperr4_t {\n unsigned int :25;\n unsigned int counter : 2;\n unsigned int crc16 : 1;\n unsigned int timeout : 1;\n unsigned int pid : 1;\n unsigned int datapid : 1;\n unsigned int datatgl : 1;\n} avr32_usbb_uperr4_t;\n\n\n\ntypedef struct avr32_usbb_uperr5_t {\n unsigned int :25;\n unsigned int counter : 2;\n unsigned int crc16 : 1;\n unsigned int timeout : 1;\n unsigned int pid : 1;\n unsigned int datapid : 1;\n unsigned int datatgl : 1;\n} avr32_usbb_uperr5_t;\n\n\n\ntypedef struct avr32_usbb_uperr6_t {\n unsigned int :25;\n unsigned int counter : 2;\n unsigned int crc16 : 1;\n unsigned int timeout : 1;\n unsigned int pid : 1;\n unsigned int datapid : 1;\n unsigned int datatgl : 1;\n} avr32_usbb_uperr6_t;\n\n\n\ntypedef struct avr32_usbb_uhdma1_nextdesc_t {\n unsigned int nxt_desc_addr :28;\n unsigned int : 4;\n} avr32_usbb_uhdma1_nextdesc_t;\n\n\n\ntypedef struct avr32_usbb_uhdma1_control_t {\n unsigned int ch_byte_length :16;\n unsigned int : 8;\n unsigned int burst_lock_en : 1;\n unsigned int desc_ld_irq_en : 1;\n unsigned int eobuff_irq_en : 1;\n unsigned int eot_irq_en : 1;\n unsigned int dmaend_en : 1;\n unsigned int buff_close_in_en : 1;\n unsigned int ld_nxt_ch_desc_en : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uhdma1_control_t;\n\n\n\ntypedef struct avr32_usbb_uhdma1_status_t {\n unsigned int ch_byte_cnt :16;\n unsigned int : 9;\n unsigned int desc_ld_sta : 1;\n unsigned int eoch_buff_sta : 1;\n unsigned int eot_sta : 1;\n unsigned int : 2;\n unsigned int ch_active : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uhdma1_status_t;\n\n\n\ntypedef struct avr32_usbb_uhdma2_nextdesc_t {\n unsigned int nxt_desc_addr :28;\n unsigned int : 4;\n} avr32_usbb_uhdma2_nextdesc_t;\n\n\n\ntypedef struct avr32_usbb_uhdma2_control_t {\n unsigned int ch_byte_length :16;\n unsigned int : 8;\n unsigned int burst_lock_en : 1;\n unsigned int desc_ld_irq_en : 1;\n unsigned int eobuff_irq_en : 1;\n unsigned int eot_irq_en : 1;\n unsigned int dmaend_en : 1;\n unsigned int buff_close_in_en : 1;\n unsigned int ld_nxt_ch_desc_en : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uhdma2_control_t;\n\n\n\ntypedef struct avr32_usbb_uhdma2_status_t {\n unsigned int ch_byte_cnt :16;\n unsigned int : 9;\n unsigned int desc_ld_sta : 1;\n unsigned int eoch_buff_sta : 1;\n unsigned int eot_sta : 1;\n unsigned int : 2;\n unsigned int ch_active : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uhdma2_status_t;\n\n\n\ntypedef struct avr32_usbb_uhdma3_nextdesc_t {\n unsigned int nxt_desc_addr :28;\n unsigned int : 4;\n} avr32_usbb_uhdma3_nextdesc_t;\n\n\n\ntypedef struct avr32_usbb_uhdma3_control_t {\n unsigned int ch_byte_length :16;\n unsigned int : 8;\n unsigned int burst_lock_en : 1;\n unsigned int desc_ld_irq_en : 1;\n unsigned int eobuff_irq_en : 1;\n unsigned int eot_irq_en : 1;\n unsigned int dmaend_en : 1;\n unsigned int buff_close_in_en : 1;\n unsigned int ld_nxt_ch_desc_en : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uhdma3_control_t;\n\n\n\ntypedef struct avr32_usbb_uhdma3_status_t {\n unsigned int ch_byte_cnt :16;\n unsigned int : 9;\n unsigned int desc_ld_sta : 1;\n unsigned int eoch_buff_sta : 1;\n unsigned int eot_sta : 1;\n unsigned int : 2;\n unsigned int ch_active : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uhdma3_status_t;\n\n\n\ntypedef struct avr32_usbb_uhdma4_nextdesc_t {\n unsigned int nxt_desc_addr :28;\n unsigned int : 4;\n} avr32_usbb_uhdma4_nextdesc_t;\n\n\n\ntypedef struct avr32_usbb_uhdma4_control_t {\n unsigned int ch_byte_length :16;\n unsigned int : 8;\n unsigned int burst_lock_en : 1;\n unsigned int desc_ld_irq_en : 1;\n unsigned int eobuff_irq_en : 1;\n unsigned int eot_irq_en : 1;\n unsigned int dmaend_en : 1;\n unsigned int buff_close_in_en : 1;\n unsigned int ld_nxt_ch_desc_en : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uhdma4_control_t;\n\n\n\ntypedef struct avr32_usbb_uhdma4_status_t {\n unsigned int ch_byte_cnt :16;\n unsigned int : 9;\n unsigned int desc_ld_sta : 1;\n unsigned int eoch_buff_sta : 1;\n unsigned int eot_sta : 1;\n unsigned int : 2;\n unsigned int ch_active : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uhdma4_status_t;\n\n\n\ntypedef struct avr32_usbb_uhdma5_nextdesc_t {\n unsigned int nxt_desc_addr :28;\n unsigned int : 4;\n} avr32_usbb_uhdma5_nextdesc_t;\n\n\n\ntypedef struct avr32_usbb_uhdma5_control_t {\n unsigned int ch_byte_length :16;\n unsigned int : 8;\n unsigned int burst_lock_en : 1;\n unsigned int desc_ld_irq_en : 1;\n unsigned int eobuff_irq_en : 1;\n unsigned int eot_irq_en : 1;\n unsigned int dmaend_en : 1;\n unsigned int buff_close_in_en : 1;\n unsigned int ld_nxt_ch_desc_en : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uhdma5_control_t;\n\n\n\ntypedef struct avr32_usbb_uhdma5_status_t {\n unsigned int ch_byte_cnt :16;\n unsigned int : 9;\n unsigned int desc_ld_sta : 1;\n unsigned int eoch_buff_sta : 1;\n unsigned int eot_sta : 1;\n unsigned int : 2;\n unsigned int ch_active : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uhdma5_status_t;\n\n\n\ntypedef struct avr32_usbb_uhdma6_nextdesc_t {\n unsigned int nxt_desc_addr :28;\n unsigned int : 4;\n} avr32_usbb_uhdma6_nextdesc_t;\n\n\n\ntypedef struct avr32_usbb_uhdma6_control_t {\n unsigned int ch_byte_length :16;\n unsigned int : 8;\n unsigned int burst_lock_en : 1;\n unsigned int desc_ld_irq_en : 1;\n unsigned int eobuff_irq_en : 1;\n unsigned int eot_irq_en : 1;\n unsigned int dmaend_en : 1;\n unsigned int buff_close_in_en : 1;\n unsigned int ld_nxt_ch_desc_en : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uhdma6_control_t;\n\n\n\ntypedef struct avr32_usbb_uhdma6_status_t {\n unsigned int ch_byte_cnt :16;\n unsigned int : 9;\n unsigned int desc_ld_sta : 1;\n unsigned int eoch_buff_sta : 1;\n unsigned int eot_sta : 1;\n unsigned int : 2;\n unsigned int ch_active : 1;\n unsigned int ch_en : 1;\n} avr32_usbb_uhdma6_status_t;\n\n\n\ntypedef struct avr32_usbb_usbcon_t {\n unsigned int : 6;\n unsigned int uimod : 1;\n unsigned int uide : 1;\n unsigned int : 1;\n unsigned int unlock : 1;\n unsigned int timpage : 2;\n unsigned int : 2;\n unsigned int timvalue : 2;\n unsigned int usbe : 1;\n unsigned int frzclk : 1;\n unsigned int vbuspo : 1;\n unsigned int otgpade : 1;\n unsigned int hnpreq : 1;\n unsigned int srpreq : 1;\n unsigned int srpsel : 1;\n unsigned int vbushwc : 1;\n unsigned int stoe : 1;\n unsigned int hnperre : 1;\n unsigned int roleexe : 1;\n unsigned int bcerre : 1;\n unsigned int vberre : 1;\n unsigned int srpe : 1;\n unsigned int vbuste : 1;\n unsigned int idte : 1;\n} avr32_usbb_usbcon_t;\n\n\n\ntypedef struct avr32_usbb_usbsta_t {\n unsigned int :17;\n unsigned int clkusable : 1;\n unsigned int speed : 2;\n unsigned int vbus : 1;\n unsigned int id : 1;\n unsigned int vbusrq : 1;\n unsigned int : 1;\n unsigned int stoi : 1;\n unsigned int hnperri : 1;\n unsigned int roleexi : 1;\n unsigned int bcerri : 1;\n unsigned int vberri : 1;\n unsigned int srpi : 1;\n unsigned int vbusti : 1;\n unsigned int idti : 1;\n} avr32_usbb_usbsta_t;\n\n\n\ntypedef struct avr32_usbb_usbstaclr_t {\n unsigned int :22;\n unsigned int vbusrqc : 1;\n unsigned int : 1;\n unsigned int stoic : 1;\n unsigned int hnperric : 1;\n unsigned int roleexic : 1;\n unsigned int bcerric : 1;\n unsigned int vberric : 1;\n unsigned int srpic : 1;\n unsigned int vbustic : 1;\n unsigned int idtic : 1;\n} avr32_usbb_usbstaclr_t;\n\n\n\ntypedef struct avr32_usbb_usbstaset_t {\n unsigned int :22;\n unsigned int vbusrqs : 1;\n unsigned int : 1;\n unsigned int stois : 1;\n unsigned int hnperris : 1;\n unsigned int roleexis : 1;\n unsigned int bcerris : 1;\n unsigned int vberris : 1;\n unsigned int srpis : 1;\n unsigned int vbustis : 1;\n unsigned int idtis : 1;\n} avr32_usbb_usbstaset_t;\n\n\n\ntypedef struct avr32_usbb_uatst1_t {\n unsigned int loadsofcnt : 1;\n unsigned int sofcntmax : 7;\n unsigned int loadcntb : 1;\n unsigned int : 1;\n unsigned int counterb : 6;\n unsigned int loadcnta : 1;\n unsigned int countera :15;\n} avr32_usbb_uatst1_t;\n\n\n\ntypedef struct avr32_usbb_uatst2_t {\n unsigned int :23;\n unsigned int utmireset : 1;\n unsigned int forcehsresetto50ms : 1;\n unsigned int hosthsdisconnectdisable : 1;\n unsigned int bypassdpll : 1;\n unsigned int forcesuspendmto1 : 1;\n unsigned int disbalegatedclock : 1;\n unsigned int loopbackmode : 1;\n unsigned int hsserialmode : 1;\n unsigned int fulldetachen : 1;\n} avr32_usbb_uatst2_t;\n\n\n\ntypedef struct avr32_usbb_uvers_t {\n unsigned int :13;\n unsigned int metal_fix_num : 3;\n unsigned int version_num :16;\n} avr32_usbb_uvers_t;\n\n\n\ntypedef struct avr32_usbb_ufeatures_t {\n unsigned int en_high_bd_iso_ept_15 : 1;\n unsigned int en_high_bd_iso_ept_14 : 1;\n unsigned int en_high_bd_iso_ept_13 : 1;\n unsigned int en_high_bd_iso_ept_12 : 1;\n unsigned int en_high_bd_iso_ept_11 : 1;\n unsigned int en_high_bd_iso_ept_10 : 1;\n unsigned int en_high_bd_iso_ept_9 : 1;\n unsigned int en_high_bd_iso_ept_8 : 1;\n unsigned int en_high_bd_iso_ept_7 : 1;\n unsigned int en_high_bd_iso_ept_6 : 1;\n unsigned int en_high_bd_iso_ept_5 : 1;\n unsigned int en_high_bd_iso_ept_4 : 1;\n unsigned int en_high_bd_iso_ept_3 : 1;\n unsigned int en_high_bd_iso_ept_2 : 1;\n unsigned int en_high_bd_iso_ept_1 : 1;\n unsigned int data_bus_8_16 : 1;\n unsigned int byte_write_dpram : 1;\n unsigned int fifo_max_size : 3;\n unsigned int dma_fifo_word_depth : 4;\n unsigned int dma_buffer_size : 1;\n unsigned int dma_channel_nbr : 3;\n unsigned int ept_nbr_max : 4;\n} avr32_usbb_ufeatures_t;\n\n\n\ntypedef struct avr32_usbb_usbfsm_t {\n unsigned int :28;\n unsigned int drdstate : 4;\n} avr32_usbb_usbfsm_t;\n\n\n\ntypedef struct avr32_usbb_t {\n union {\n unsigned long udcon ;//0x0000\n avr32_usbb_udcon_t UDCON ;\n };\n union {\n const unsigned long udint ;//0x0004\n const avr32_usbb_udint_t UDINT ;\n };\n union {\n unsigned long udintclr ;//0x0008\n avr32_usbb_udintclr_t UDINTCLR ;\n };\n union {\n unsigned long udintset ;//0x000c\n avr32_usbb_udintset_t UDINTSET ;\n };\n union {\n const unsigned long udinte ;//0x0010\n const avr32_usbb_udinte_t UDINTE ;\n };\n union {\n unsigned long udinteclr ;//0x0014\n avr32_usbb_udinteclr_t UDINTECLR ;\n };\n union {\n unsigned long udinteset ;//0x0018\n avr32_usbb_udinteset_t UDINTESET ;\n };\n union {\n unsigned long uerst ;//0x001c\n avr32_usbb_uerst_t UERST ;\n };\n union {\n const unsigned long udfnum ;//0x0020\n const avr32_usbb_udfnum_t UDFNUM ;\n };\n union {\n unsigned long udtst1 ;//0x0024\n avr32_usbb_udtst1_t UDTST1 ;\n };\n union {\n unsigned long udtst2 ;//0x0028\n avr32_usbb_udtst2_t UDTST2 ;\n };\n const unsigned long udvers ;//0x002c\n union {\n const unsigned long udfeatures;//0x0030\n const avr32_usbb_udfeatures_t UDFEATURES;\n };\n const unsigned long udaddrsize;//0x0034\n const unsigned long udname1 ;//0x0038\n const unsigned long udname2 ;//0x003c\n unsigned int :32 ;//0x0040\n unsigned int :32 ;//0x0044\n unsigned int :32 ;//0x0048\n unsigned int :32 ;//0x004c\n unsigned int :32 ;//0x0050\n unsigned int :32 ;//0x0054\n unsigned int :32 ;//0x0058\n unsigned int :32 ;//0x005c\n unsigned int :32 ;//0x0060\n unsigned int :32 ;//0x0064\n unsigned int :32 ;//0x0068\n unsigned int :32 ;//0x006c\n unsigned int :32 ;//0x0070\n unsigned int :32 ;//0x0074\n unsigned int :32 ;//0x0078\n unsigned int :32 ;//0x007c\n unsigned int :32 ;//0x0080\n unsigned int :32 ;//0x0084\n unsigned int :32 ;//0x0088\n unsigned int :32 ;//0x008c\n unsigned int :32 ;//0x0090\n unsigned int :32 ;//0x0094\n unsigned int :32 ;//0x0098\n unsigned int :32 ;//0x009c\n unsigned int :32 ;//0x00a0\n unsigned int :32 ;//0x00a4\n unsigned int :32 ;//0x00a8\n unsigned int :32 ;//0x00ac\n unsigned int :32 ;//0x00b0\n unsigned int :32 ;//0x00b4\n unsigned int :32 ;//0x00b8\n unsigned int :32 ;//0x00bc\n unsigned int :32 ;//0x00c0\n unsigned int :32 ;//0x00c4\n unsigned int :32 ;//0x00c8\n unsigned int :32 ;//0x00cc\n unsigned int :32 ;//0x00d0\n unsigned int :32 ;//0x00d4\n unsigned int :32 ;//0x00d8\n unsigned int :32 ;//0x00dc\n unsigned int :32 ;//0x00e0\n unsigned int :32 ;//0x00e4\n unsigned int :32 ;//0x00e8\n unsigned int :32 ;//0x00ec\n unsigned int :32 ;//0x00f0\n unsigned int :32 ;//0x00f4\n unsigned int :32 ;//0x00f8\n unsigned int :32 ;//0x00fc\n union {\n unsigned long uecfg0 ;//0x0100\n avr32_usbb_uecfg0_t UECFG0 ;\n };\n union {\n unsigned long uecfg1 ;//0x0104\n avr32_usbb_uecfg1_t UECFG1 ;\n };\n union {\n unsigned long uecfg2 ;//0x0108\n avr32_usbb_uecfg2_t UECFG2 ;\n };\n union {\n unsigned long uecfg3 ;//0x010c\n avr32_usbb_uecfg3_t UECFG3 ;\n };\n union {\n unsigned long uecfg4 ;//0x0110\n avr32_usbb_uecfg4_t UECFG4 ;\n };\n union {\n unsigned long uecfg5 ;//0x0114\n avr32_usbb_uecfg5_t UECFG5 ;\n };\n union {\n unsigned long uecfg6 ;//0x0118\n avr32_usbb_uecfg6_t UECFG6 ;\n };\n unsigned int :32 ;//0x011c\n unsigned int :32 ;//0x0120\n unsigned int :32 ;//0x0124\n unsigned int :32 ;//0x0128\n unsigned int :32 ;//0x012c\n union {\n const unsigned long uesta0 ;//0x0130\n const avr32_usbb_uesta0_t UESTA0 ;\n };\n union {\n const unsigned long uesta1 ;//0x0134\n const avr32_usbb_uesta1_t UESTA1 ;\n };\n union {\n const unsigned long uesta2 ;//0x0138\n const avr32_usbb_uesta2_t UESTA2 ;\n };\n union {\n const unsigned long uesta3 ;//0x013c\n const avr32_usbb_uesta3_t UESTA3 ;\n };\n union {\n const unsigned long uesta4 ;//0x0140\n const avr32_usbb_uesta4_t UESTA4 ;\n };\n union {\n const unsigned long uesta5 ;//0x0144\n const avr32_usbb_uesta5_t UESTA5 ;\n };\n union {\n const unsigned long uesta6 ;//0x0148\n const avr32_usbb_uesta6_t UESTA6 ;\n };\n unsigned int :32 ;//0x014c\n unsigned int :32 ;//0x0150\n unsigned int :32 ;//0x0154\n unsigned int :32 ;//0x0158\n unsigned int :32 ;//0x015c\n union {\n unsigned long uesta0clr ;//0x0160\n avr32_usbb_uesta0clr_t UESTA0CLR ;\n };\n union {\n unsigned long uesta1clr ;//0x0164\n avr32_usbb_uesta1clr_t UESTA1CLR ;\n };\n union {\n unsigned long uesta2clr ;//0x0168\n avr32_usbb_uesta2clr_t UESTA2CLR ;\n };\n union {\n unsigned long uesta3clr ;//0x016c\n avr32_usbb_uesta3clr_t UESTA3CLR ;\n };\n union {\n unsigned long uesta4clr ;//0x0170\n avr32_usbb_uesta4clr_t UESTA4CLR ;\n };\n union {\n unsigned long uesta5clr ;//0x0174\n avr32_usbb_uesta5clr_t UESTA5CLR ;\n };\n union {\n unsigned long uesta6clr ;//0x0178\n avr32_usbb_uesta6clr_t UESTA6CLR ;\n };\n unsigned int :32 ;//0x017c\n unsigned int :32 ;//0x0180\n unsigned int :32 ;//0x0184\n unsigned int :32 ;//0x0188\n unsigned int :32 ;//0x018c\n union {\n unsigned long uesta0set ;//0x0190\n avr32_usbb_uesta0set_t UESTA0SET ;\n };\n union {\n unsigned long uesta1set ;//0x0194\n avr32_usbb_uesta1set_t UESTA1SET ;\n };\n union {\n unsigned long uesta2set ;//0x0198\n avr32_usbb_uesta2set_t UESTA2SET ;\n };\n union {\n unsigned long uesta3set ;//0x019c\n avr32_usbb_uesta3set_t UESTA3SET ;\n };\n union {\n unsigned long uesta4set ;//0x01a0\n avr32_usbb_uesta4set_t UESTA4SET ;\n };\n union {\n unsigned long uesta5set ;//0x01a4\n avr32_usbb_uesta5set_t UESTA5SET ;\n };\n union {\n unsigned long uesta6set ;//0x01a8\n avr32_usbb_uesta6set_t UESTA6SET ;\n };\n unsigned int :32 ;//0x01ac\n unsigned int :32 ;//0x01b0\n unsigned int :32 ;//0x01b4\n unsigned int :32 ;//0x01b8\n unsigned int :32 ;//0x01bc\n union {\n const unsigned long uecon0 ;//0x01c0\n const avr32_usbb_uecon0_t UECON0 ;\n };\n union {\n const unsigned long uecon1 ;//0x01c4\n const avr32_usbb_uecon1_t UECON1 ;\n };\n union {\n const unsigned long uecon2 ;//0x01c8\n const avr32_usbb_uecon2_t UECON2 ;\n };\n union {\n const unsigned long uecon3 ;//0x01cc\n const avr32_usbb_uecon3_t UECON3 ;\n };\n union {\n const unsigned long uecon4 ;//0x01d0\n const avr32_usbb_uecon4_t UECON4 ;\n };\n union {\n const unsigned long uecon5 ;//0x01d4\n const avr32_usbb_uecon5_t UECON5 ;\n };\n union {\n const unsigned long uecon6 ;//0x01d8\n const avr32_usbb_uecon6_t UECON6 ;\n };\n unsigned int :32 ;//0x01dc\n unsigned int :32 ;//0x01e0\n unsigned int :32 ;//0x01e4\n unsigned int :32 ;//0x01e8\n unsigned int :32 ;//0x01ec\n union {\n unsigned long uecon0set ;//0x01f0\n avr32_usbb_uecon0set_t UECON0SET ;\n };\n union {\n unsigned long uecon1set ;//0x01f4\n avr32_usbb_uecon1set_t UECON1SET ;\n };\n union {\n unsigned long uecon2set ;//0x01f8\n avr32_usbb_uecon2set_t UECON2SET ;\n };\n union {\n unsigned long uecon3set ;//0x01fc\n avr32_usbb_uecon3set_t UECON3SET ;\n };\n union {\n unsigned long uecon4set ;//0x0200\n avr32_usbb_uecon4set_t UECON4SET ;\n };\n union {\n unsigned long uecon5set ;//0x0204\n avr32_usbb_uecon5set_t UECON5SET ;\n };\n union {\n unsigned long uecon6set ;//0x0208\n avr32_usbb_uecon6set_t UECON6SET ;\n };\n unsigned int :32 ;//0x020c\n unsigned int :32 ;//0x0210\n unsigned int :32 ;//0x0214\n unsigned int :32 ;//0x0218\n unsigned int :32 ;//0x021c\n union {\n unsigned long uecon0clr ;//0x0220\n avr32_usbb_uecon0clr_t UECON0CLR ;\n };\n union {\n unsigned long uecon1clr ;//0x0224\n avr32_usbb_uecon1clr_t UECON1CLR ;\n };\n union {\n unsigned long uecon2clr ;//0x0228\n avr32_usbb_uecon2clr_t UECON2CLR ;\n };\n union {\n unsigned long uecon3clr ;//0x022c\n avr32_usbb_uecon3clr_t UECON3CLR ;\n };\n union {\n unsigned long uecon4clr ;//0x0230\n avr32_usbb_uecon4clr_t UECON4CLR ;\n };\n union {\n unsigned long uecon5clr ;//0x0234\n avr32_usbb_uecon5clr_t UECON5CLR ;\n };\n union {\n unsigned long uecon6clr ;//0x0238\n avr32_usbb_uecon6clr_t UECON6CLR ;\n };\n unsigned int :32 ;//0x023c\n unsigned int :32 ;//0x0240\n unsigned int :32 ;//0x0244\n unsigned int :32 ;//0x0248\n unsigned int :32 ;//0x024c\n unsigned long uedat0 ;//0x0250\n unsigned long uedat1 ;//0x0254\n unsigned long uedat2 ;//0x0258\n unsigned long uedat3 ;//0x025c\n unsigned long uedat4 ;//0x0260\n unsigned long uedat5 ;//0x0264\n unsigned long uedat6 ;//0x0268\n unsigned int :32 ;//0x026c\n unsigned int :32 ;//0x0270\n unsigned int :32 ;//0x0274\n unsigned int :32 ;//0x0278\n unsigned int :32 ;//0x027c\n unsigned int :32 ;//0x0280\n unsigned int :32 ;//0x0284\n unsigned int :32 ;//0x0288\n unsigned int :32 ;//0x028c\n unsigned int :32 ;//0x0290\n unsigned int :32 ;//0x0294\n unsigned int :32 ;//0x0298\n unsigned int :32 ;//0x029c\n unsigned int :32 ;//0x02a0\n unsigned int :32 ;//0x02a4\n unsigned int :32 ;//0x02a8\n unsigned int :32 ;//0x02ac\n unsigned int :32 ;//0x02b0\n unsigned int :32 ;//0x02b4\n unsigned int :32 ;//0x02b8\n unsigned int :32 ;//0x02bc\n unsigned int :32 ;//0x02c0\n unsigned int :32 ;//0x02c4\n unsigned int :32 ;//0x02c8\n unsigned int :32 ;//0x02cc\n unsigned int :32 ;//0x02d0\n unsigned int :32 ;//0x02d4\n unsigned int :32 ;//0x02d8\n unsigned int :32 ;//0x02dc\n unsigned int :32 ;//0x02e0\n unsigned int :32 ;//0x02e4\n unsigned int :32 ;//0x02e8\n unsigned int :32 ;//0x02ec\n unsigned int :32 ;//0x02f0\n unsigned int :32 ;//0x02f4\n unsigned int :32 ;//0x02f8\n unsigned int :32 ;//0x02fc\n unsigned int :32 ;//0x0300\n unsigned int :32 ;//0x0304\n unsigned int :32 ;//0x0308\n unsigned int :32 ;//0x030c\n union {\n unsigned long uddma1_nextdesc;//0x0310\n avr32_usbb_uddma1_nextdesc_t UDDMA1_NEXTDESC;\n };\n unsigned long uddma1_addr;//0x0314\n union {\n unsigned long uddma1_control;//0x0318\n avr32_usbb_uddma1_control_t UDDMA1_CONTROL;\n };\n union {\n unsigned long uddma1_status;//0x031c\n avr32_usbb_uddma1_status_t UDDMA1_STATUS;\n };\n union {\n unsigned long uddma2_nextdesc;//0x0320\n avr32_usbb_uddma2_nextdesc_t UDDMA2_NEXTDESC;\n };\n unsigned long uddma2_addr;//0x0324\n union {\n unsigned long uddma2_control;//0x0328\n avr32_usbb_uddma2_control_t UDDMA2_CONTROL;\n };\n union {\n unsigned long uddma2_status;//0x032c\n avr32_usbb_uddma2_status_t UDDMA2_STATUS;\n };\n union {\n unsigned long uddma3_nextdesc;//0x0330\n avr32_usbb_uddma3_nextdesc_t UDDMA3_NEXTDESC;\n };\n unsigned long uddma3_addr;//0x0334\n union {\n unsigned long uddma3_control;//0x0338\n avr32_usbb_uddma3_control_t UDDMA3_CONTROL;\n };\n union {\n unsigned long uddma3_status;//0x033c\n avr32_usbb_uddma3_status_t UDDMA3_STATUS;\n };\n union {\n unsigned long uddma4_nextdesc;//0x0340\n avr32_usbb_uddma4_nextdesc_t UDDMA4_NEXTDESC;\n };\n unsigned long uddma4_addr;//0x0344\n union {\n unsigned long uddma4_control;//0x0348\n avr32_usbb_uddma4_control_t UDDMA4_CONTROL;\n };\n union {\n unsigned long uddma4_status;//0x034c\n avr32_usbb_uddma4_status_t UDDMA4_STATUS;\n };\n union {\n unsigned long uddma5_nextdesc;//0x0350\n avr32_usbb_uddma5_nextdesc_t UDDMA5_NEXTDESC;\n };\n unsigned long uddma5_addr;//0x0354\n union {\n unsigned long uddma5_control;//0x0358\n avr32_usbb_uddma5_control_t UDDMA5_CONTROL;\n };\n union {\n unsigned long uddma5_status;//0x035c\n avr32_usbb_uddma5_status_t UDDMA5_STATUS;\n };\n union {\n unsigned long uddma6_nextdesc;//0x0360\n avr32_usbb_uddma6_nextdesc_t UDDMA6_NEXTDESC;\n };\n unsigned long uddma6_addr;//0x0364\n union {\n unsigned long uddma6_control;//0x0368\n avr32_usbb_uddma6_control_t UDDMA6_CONTROL;\n };\n union {\n unsigned long uddma6_status;//0x036c\n avr32_usbb_uddma6_status_t UDDMA6_STATUS;\n };\n unsigned int :32 ;//0x0370\n unsigned int :32 ;//0x0374\n unsigned int :32 ;//0x0378\n unsigned int :32 ;//0x037c\n unsigned int :32 ;//0x0380\n unsigned int :32 ;//0x0384\n unsigned int :32 ;//0x0388\n unsigned int :32 ;//0x038c\n unsigned int :32 ;//0x0390\n unsigned int :32 ;//0x0394\n unsigned int :32 ;//0x0398\n unsigned int :32 ;//0x039c\n unsigned int :32 ;//0x03a0\n unsigned int :32 ;//0x03a4\n unsigned int :32 ;//0x03a8\n unsigned int :32 ;//0x03ac\n unsigned int :32 ;//0x03b0\n unsigned int :32 ;//0x03b4\n unsigned int :32 ;//0x03b8\n unsigned int :32 ;//0x03bc\n unsigned int :32 ;//0x03c0\n unsigned int :32 ;//0x03c4\n unsigned int :32 ;//0x03c8\n unsigned int :32 ;//0x03cc\n unsigned int :32 ;//0x03d0\n unsigned int :32 ;//0x03d4\n unsigned int :32 ;//0x03d8\n unsigned int :32 ;//0x03dc\n unsigned int :32 ;//0x03e0\n unsigned int :32 ;//0x03e4\n unsigned int :32 ;//0x03e8\n unsigned int :32 ;//0x03ec\n unsigned int :32 ;//0x03f0\n unsigned int :32 ;//0x03f4\n unsigned int :32 ;//0x03f8\n unsigned int :32 ;//0x03fc\n union {\n unsigned long uhcon ;//0x0400\n avr32_usbb_uhcon_t UHCON ;\n };\n union {\n const unsigned long uhint ;//0x0404\n const avr32_usbb_uhint_t UHINT ;\n };\n union {\n unsigned long uhintclr ;//0x0408\n avr32_usbb_uhintclr_t UHINTCLR ;\n };\n union {\n unsigned long uhintset ;//0x040c\n avr32_usbb_uhintset_t UHINTSET ;\n };\n union {\n const unsigned long uhinte ;//0x0410\n const avr32_usbb_uhinte_t UHINTE ;\n };\n union {\n unsigned long uhinteclr ;//0x0414\n avr32_usbb_uhinteclr_t UHINTECLR ;\n };\n union {\n unsigned long uhinteset ;//0x0418\n avr32_usbb_uhinteset_t UHINTESET ;\n };\n union {\n unsigned long uprst ;//0x041c\n avr32_usbb_uprst_t UPRST ;\n };\n union {\n unsigned long uhfnum ;//0x0420\n avr32_usbb_uhfnum_t UHFNUM ;\n };\n union {\n unsigned long uhaddr1 ;//0x0424\n avr32_usbb_uhaddr1_t UHADDR1 ;\n };\n union {\n unsigned long uhaddr2 ;//0x0428\n avr32_usbb_uhaddr2_t UHADDR2 ;\n };\n union {\n unsigned long uhaddr3 ;//0x042c\n avr32_usbb_uhaddr3_t UHADDR3 ;\n };\n unsigned int :32 ;//0x0430\n unsigned int :32 ;//0x0434\n unsigned int :32 ;//0x0438\n unsigned int :32 ;//0x043c\n unsigned int :32 ;//0x0440\n unsigned int :32 ;//0x0444\n unsigned int :32 ;//0x0448\n unsigned int :32 ;//0x044c\n unsigned int :32 ;//0x0450\n unsigned int :32 ;//0x0454\n unsigned int :32 ;//0x0458\n unsigned int :32 ;//0x045c\n unsigned int :32 ;//0x0460\n unsigned int :32 ;//0x0464\n unsigned int :32 ;//0x0468\n unsigned int :32 ;//0x046c\n unsigned int :32 ;//0x0470\n unsigned int :32 ;//0x0474\n unsigned int :32 ;//0x0478\n unsigned int :32 ;//0x047c\n unsigned int :32 ;//0x0480\n unsigned int :32 ;//0x0484\n unsigned int :32 ;//0x0488\n unsigned int :32 ;//0x048c\n unsigned int :32 ;//0x0490\n unsigned int :32 ;//0x0494\n unsigned int :32 ;//0x0498\n unsigned int :32 ;//0x049c\n unsigned int :32 ;//0x04a0\n unsigned int :32 ;//0x04a4\n unsigned int :32 ;//0x04a8\n unsigned int :32 ;//0x04ac\n unsigned int :32 ;//0x04b0\n unsigned int :32 ;//0x04b4\n unsigned int :32 ;//0x04b8\n unsigned int :32 ;//0x04bc\n unsigned int :32 ;//0x04c0\n unsigned int :32 ;//0x04c4\n unsigned int :32 ;//0x04c8\n unsigned int :32 ;//0x04cc\n unsigned int :32 ;//0x04d0\n unsigned int :32 ;//0x04d4\n unsigned int :32 ;//0x04d8\n unsigned int :32 ;//0x04dc\n unsigned int :32 ;//0x04e0\n unsigned int :32 ;//0x04e4\n unsigned int :32 ;//0x04e8\n unsigned int :32 ;//0x04ec\n unsigned int :32 ;//0x04f0\n unsigned int :32 ;//0x04f4\n unsigned int :32 ;//0x04f8\n unsigned int :32 ;//0x04fc\n union {\n unsigned long upcfg0 ;//0x0500\n avr32_usbb_upcfg0_t UPCFG0 ;\n };\n union {\n unsigned long upcfg1 ;//0x0504\n avr32_usbb_upcfg1_t UPCFG1 ;\n };\n union {\n unsigned long upcfg2 ;//0x0508\n avr32_usbb_upcfg2_t UPCFG2 ;\n };\n union {\n unsigned long upcfg3 ;//0x050c\n avr32_usbb_upcfg3_t UPCFG3 ;\n };\n union {\n unsigned long upcfg4 ;//0x0510\n avr32_usbb_upcfg4_t UPCFG4 ;\n };\n union {\n unsigned long upcfg5 ;//0x0514\n avr32_usbb_upcfg5_t UPCFG5 ;\n };\n union {\n unsigned long upcfg6 ;//0x0518\n avr32_usbb_upcfg6_t UPCFG6 ;\n };\n unsigned int :32 ;//0x051c\n unsigned int :32 ;//0x0520\n unsigned int :32 ;//0x0524\n unsigned int :32 ;//0x0528\n unsigned int :32 ;//0x052c\n union {\n const unsigned long upsta0 ;//0x0530\n const avr32_usbb_upsta0_t UPSTA0 ;\n };\n union {\n const unsigned long upsta1 ;//0x0534\n const avr32_usbb_upsta1_t UPSTA1 ;\n };\n union {\n const unsigned long upsta2 ;//0x0538\n const avr32_usbb_upsta2_t UPSTA2 ;\n };\n union {\n const unsigned long upsta3 ;//0x053c\n const avr32_usbb_upsta3_t UPSTA3 ;\n };\n union {\n const unsigned long upsta4 ;//0x0540\n const avr32_usbb_upsta4_t UPSTA4 ;\n };\n union {\n const unsigned long upsta5 ;//0x0544\n const avr32_usbb_upsta5_t UPSTA5 ;\n };\n union {\n const unsigned long upsta6 ;//0x0548\n const avr32_usbb_upsta6_t UPSTA6 ;\n };\n unsigned int :32 ;//0x054c\n unsigned int :32 ;//0x0550\n unsigned int :32 ;//0x0554\n unsigned int :32 ;//0x0558\n unsigned int :32 ;//0x055c\n union {\n unsigned long upsta0clr ;//0x0560\n avr32_usbb_upsta0clr_t UPSTA0CLR ;\n };\n union {\n unsigned long upsta1clr ;//0x0564\n avr32_usbb_upsta1clr_t UPSTA1CLR ;\n };\n union {\n unsigned long upsta2clr ;//0x0568\n avr32_usbb_upsta2clr_t UPSTA2CLR ;\n };\n union {\n unsigned long upsta3clr ;//0x056c\n avr32_usbb_upsta3clr_t UPSTA3CLR ;\n };\n union {\n unsigned long upsta4clr ;//0x0570\n avr32_usbb_upsta4clr_t UPSTA4CLR ;\n };\n union {\n unsigned long upsta5clr ;//0x0574\n avr32_usbb_upsta5clr_t UPSTA5CLR ;\n };\n union {\n unsigned long upsta6clr ;//0x0578\n avr32_usbb_upsta6clr_t UPSTA6CLR ;\n };\n unsigned int :32 ;//0x057c\n unsigned int :32 ;//0x0580\n unsigned int :32 ;//0x0584\n unsigned int :32 ;//0x0588\n unsigned int :32 ;//0x058c\n union {\n unsigned long upsta0set ;//0x0590\n avr32_usbb_upsta0set_t UPSTA0SET ;\n };\n union {\n unsigned long upsta1set ;//0x0594\n avr32_usbb_upsta1set_t UPSTA1SET ;\n };\n union {\n unsigned long upsta2set ;//0x0598\n avr32_usbb_upsta2set_t UPSTA2SET ;\n };\n union {\n unsigned long upsta3set ;//0x059c\n avr32_usbb_upsta3set_t UPSTA3SET ;\n };\n union {\n unsigned long upsta4set ;//0x05a0\n avr32_usbb_upsta4set_t UPSTA4SET ;\n };\n union {\n unsigned long upsta5set ;//0x05a4\n avr32_usbb_upsta5set_t UPSTA5SET ;\n };\n union {\n unsigned long upsta6set ;//0x05a8\n avr32_usbb_upsta6set_t UPSTA6SET ;\n };\n unsigned int :32 ;//0x05ac\n unsigned int :32 ;//0x05b0\n unsigned int :32 ;//0x05b4\n unsigned int :32 ;//0x05b8\n unsigned int :32 ;//0x05bc\n union {\n const unsigned long upcon0 ;//0x05c0\n const avr32_usbb_upcon0_t UPCON0 ;\n };\n union {\n const unsigned long upcon1 ;//0x05c4\n const avr32_usbb_upcon1_t UPCON1 ;\n };\n union {\n const unsigned long upcon2 ;//0x05c8\n const avr32_usbb_upcon2_t UPCON2 ;\n };\n union {\n const unsigned long upcon3 ;//0x05cc\n const avr32_usbb_upcon3_t UPCON3 ;\n };\n union {\n const unsigned long upcon4 ;//0x05d0\n const avr32_usbb_upcon4_t UPCON4 ;\n };\n union {\n const unsigned long upcon5 ;//0x05d4\n const avr32_usbb_upcon5_t UPCON5 ;\n };\n union {\n const unsigned long upcon6 ;//0x05d8\n const avr32_usbb_upcon6_t UPCON6 ;\n };\n unsigned int :32 ;//0x05dc\n unsigned int :32 ;//0x05e0\n unsigned int :32 ;//0x05e4\n unsigned int :32 ;//0x05e8\n unsigned int :32 ;//0x05ec\n union {\n unsigned long upcon0set ;//0x05f0\n avr32_usbb_upcon0set_t UPCON0SET ;\n };\n union {\n unsigned long upcon1set ;//0x05f4\n avr32_usbb_upcon1set_t UPCON1SET ;\n };\n union {\n unsigned long upcon2set ;//0x05f8\n avr32_usbb_upcon2set_t UPCON2SET ;\n };\n union {\n unsigned long upcon3set ;//0x05fc\n avr32_usbb_upcon3set_t UPCON3SET ;\n };\n union {\n unsigned long upcon4set ;//0x0600\n avr32_usbb_upcon4set_t UPCON4SET ;\n };\n union {\n unsigned long upcon5set ;//0x0604\n avr32_usbb_upcon5set_t UPCON5SET ;\n };\n union {\n unsigned long upcon6set ;//0x0608\n avr32_usbb_upcon6set_t UPCON6SET ;\n };\n unsigned int :32 ;//0x060c\n unsigned int :32 ;//0x0610\n unsigned int :32 ;//0x0614\n unsigned int :32 ;//0x0618\n unsigned int :32 ;//0x061c\n union {\n unsigned long upcon0clr ;//0x0620\n avr32_usbb_upcon0clr_t UPCON0CLR ;\n };\n union {\n unsigned long upcon1clr ;//0x0624\n avr32_usbb_upcon1clr_t UPCON1CLR ;\n };\n union {\n unsigned long upcon2clr ;//0x0628\n avr32_usbb_upcon2clr_t UPCON2CLR ;\n };\n union {\n unsigned long upcon3clr ;//0x062c\n avr32_usbb_upcon3clr_t UPCON3CLR ;\n };\n union {\n unsigned long upcon4clr ;//0x0630\n avr32_usbb_upcon4clr_t UPCON4CLR ;\n };\n union {\n unsigned long upcon5clr ;//0x0634\n avr32_usbb_upcon5clr_t UPCON5CLR ;\n };\n union {\n unsigned long upcon6clr ;//0x0638\n avr32_usbb_upcon6clr_t UPCON6CLR ;\n };\n unsigned int :32 ;//0x063c\n unsigned int :32 ;//0x0640\n unsigned int :32 ;//0x0644\n unsigned int :32 ;//0x0648\n unsigned int :32 ;//0x064c\n union {\n unsigned long upinrq0 ;//0x0650\n avr32_usbb_upinrq0_t UPINRQ0 ;\n };\n union {\n unsigned long upinrq1 ;//0x0654\n avr32_usbb_upinrq1_t UPINRQ1 ;\n };\n union {\n unsigned long upinrq2 ;//0x0658\n avr32_usbb_upinrq2_t UPINRQ2 ;\n };\n union {\n unsigned long upinrq3 ;//0x065c\n avr32_usbb_upinrq3_t UPINRQ3 ;\n };\n union {\n unsigned long upinrq4 ;//0x0660\n avr32_usbb_upinrq4_t UPINRQ4 ;\n };\n union {\n unsigned long upinrq5 ;//0x0664\n avr32_usbb_upinrq5_t UPINRQ5 ;\n };\n union {\n unsigned long upinrq6 ;//0x0668\n avr32_usbb_upinrq6_t UPINRQ6 ;\n };\n unsigned int :32 ;//0x066c\n unsigned int :32 ;//0x0670\n unsigned int :32 ;//0x0674\n unsigned int :32 ;//0x0678\n unsigned int :32 ;//0x067c\n union {\n unsigned long uperr0 ;//0x0680\n avr32_usbb_uperr0_t UPERR0 ;\n };\n union {\n unsigned long uperr1 ;//0x0684\n avr32_usbb_uperr1_t UPERR1 ;\n };\n union {\n unsigned long uperr2 ;//0x0688\n avr32_usbb_uperr2_t UPERR2 ;\n };\n union {\n unsigned long uperr3 ;//0x068c\n avr32_usbb_uperr3_t UPERR3 ;\n };\n union {\n unsigned long uperr4 ;//0x0690\n avr32_usbb_uperr4_t UPERR4 ;\n };\n union {\n unsigned long uperr5 ;//0x0694\n avr32_usbb_uperr5_t UPERR5 ;\n };\n union {\n unsigned long uperr6 ;//0x0698\n avr32_usbb_uperr6_t UPERR6 ;\n };\n unsigned int :32 ;//0x069c\n unsigned int :32 ;//0x06a0\n unsigned int :32 ;//0x06a4\n unsigned int :32 ;//0x06a8\n unsigned int :32 ;//0x06ac\n unsigned long updat0 ;//0x06b0\n unsigned long updat1 ;//0x06b4\n unsigned long updat2 ;//0x06b8\n unsigned long updat3 ;//0x06bc\n unsigned long updat4 ;//0x06c0\n unsigned long updat5 ;//0x06c4\n unsigned long updat6 ;//0x06c8\n unsigned int :32 ;//0x06cc\n unsigned int :32 ;//0x06d0\n unsigned int :32 ;//0x06d4\n unsigned int :32 ;//0x06d8\n unsigned int :32 ;//0x06dc\n unsigned int :32 ;//0x06e0\n unsigned int :32 ;//0x06e4\n unsigned int :32 ;//0x06e8\n unsigned int :32 ;//0x06ec\n unsigned int :32 ;//0x06f0\n unsigned int :32 ;//0x06f4\n unsigned int :32 ;//0x06f8\n unsigned int :32 ;//0x06fc\n unsigned int :32 ;//0x0700\n unsigned int :32 ;//0x0704\n unsigned int :32 ;//0x0708\n unsigned int :32 ;//0x070c\n union {\n unsigned long uhdma1_nextdesc;//0x0710\n avr32_usbb_uhdma1_nextdesc_t UHDMA1_NEXTDESC;\n };\n unsigned long uhdma1_addr;//0x0714\n union {\n unsigned long uhdma1_control;//0x0718\n avr32_usbb_uhdma1_control_t UHDMA1_CONTROL;\n };\n union {\n unsigned long uhdma1_status;//0x071c\n avr32_usbb_uhdma1_status_t UHDMA1_STATUS;\n };\n union {\n unsigned long uhdma2_nextdesc;//0x0720\n avr32_usbb_uhdma2_nextdesc_t UHDMA2_NEXTDESC;\n };\n unsigned long uhdma2_addr;//0x0724\n union {\n unsigned long uhdma2_control;//0x0728\n avr32_usbb_uhdma2_control_t UHDMA2_CONTROL;\n };\n union {\n unsigned long uhdma2_status;//0x072c\n avr32_usbb_uhdma2_status_t UHDMA2_STATUS;\n };\n union {\n unsigned long uhdma3_nextdesc;//0x0730\n avr32_usbb_uhdma3_nextdesc_t UHDMA3_NEXTDESC;\n };\n unsigned long uhdma3_addr;//0x0734\n union {\n unsigned long uhdma3_control;//0x0738\n avr32_usbb_uhdma3_control_t UHDMA3_CONTROL;\n };\n union {\n unsigned long uhdma3_status;//0x073c\n avr32_usbb_uhdma3_status_t UHDMA3_STATUS;\n };\n union {\n unsigned long uhdma4_nextdesc;//0x0740\n avr32_usbb_uhdma4_nextdesc_t UHDMA4_NEXTDESC;\n };\n unsigned long uhdma4_addr;//0x0744\n union {\n unsigned long uhdma4_control;//0x0748\n avr32_usbb_uhdma4_control_t UHDMA4_CONTROL;\n };\n union {\n unsigned long uhdma4_status;//0x074c\n avr32_usbb_uhdma4_status_t UHDMA4_STATUS;\n };\n union {\n unsigned long uhdma5_nextdesc;//0x0750\n avr32_usbb_uhdma5_nextdesc_t UHDMA5_NEXTDESC;\n };\n unsigned long uhdma5_addr;//0x0754\n union {\n unsigned long uhdma5_control;//0x0758\n avr32_usbb_uhdma5_control_t UHDMA5_CONTROL;\n };\n union {\n unsigned long uhdma5_status;//0x075c\n avr32_usbb_uhdma5_status_t UHDMA5_STATUS;\n };\n union {\n unsigned long uhdma6_nextdesc;//0x0760\n avr32_usbb_uhdma6_nextdesc_t UHDMA6_NEXTDESC;\n };\n unsigned long uhdma6_addr;//0x0764\n union {\n unsigned long uhdma6_control;//0x0768\n avr32_usbb_uhdma6_control_t UHDMA6_CONTROL;\n };\n union {\n unsigned long uhdma6_status;//0x076c\n avr32_usbb_uhdma6_status_t UHDMA6_STATUS;\n };\n unsigned int :32 ;//0x0770\n unsigned int :32 ;//0x0774\n unsigned int :32 ;//0x0778\n unsigned int :32 ;//0x077c\n unsigned int :32 ;//0x0780\n unsigned int :32 ;//0x0784\n unsigned int :32 ;//0x0788\n unsigned int :32 ;//0x078c\n unsigned int :32 ;//0x0790\n unsigned int :32 ;//0x0794\n unsigned int :32 ;//0x0798\n unsigned int :32 ;//0x079c\n unsigned int :32 ;//0x07a0\n unsigned int :32 ;//0x07a4\n unsigned int :32 ;//0x07a8\n unsigned int :32 ;//0x07ac\n unsigned int :32 ;//0x07b0\n unsigned int :32 ;//0x07b4\n unsigned int :32 ;//0x07b8\n unsigned int :32 ;//0x07bc\n unsigned int :32 ;//0x07c0\n unsigned int :32 ;//0x07c4\n unsigned int :32 ;//0x07c8\n unsigned int :32 ;//0x07cc\n unsigned int :32 ;//0x07d0\n unsigned int :32 ;//0x07d4\n unsigned int :32 ;//0x07d8\n unsigned int :32 ;//0x07dc\n unsigned int :32 ;//0x07e0\n unsigned int :32 ;//0x07e4\n unsigned int :32 ;//0x07e8\n unsigned int :32 ;//0x07ec\n unsigned int :32 ;//0x07f0\n unsigned int :32 ;//0x07f4\n unsigned int :32 ;//0x07f8\n unsigned int :32 ;//0x07fc\n union {\n unsigned long usbcon ;//0x0800\n avr32_usbb_usbcon_t USBCON ;\n };\n union {\n const unsigned long usbsta ;//0x0804\n const avr32_usbb_usbsta_t USBSTA ;\n };\n union {\n unsigned long usbstaclr ;//0x0808\n avr32_usbb_usbstaclr_t USBSTACLR ;\n };\n union {\n unsigned long usbstaset ;//0x080c\n avr32_usbb_usbstaset_t USBSTASET ;\n };\n union {\n unsigned long uatst1 ;//0x0810\n avr32_usbb_uatst1_t UATST1 ;\n };\n union {\n unsigned long uatst2 ;//0x0814\n avr32_usbb_uatst2_t UATST2 ;\n };\n union {\n const unsigned long uvers ;//0x0818\n const avr32_usbb_uvers_t UVERS ;\n };\n union {\n const unsigned long ufeatures ;//0x081c\n const avr32_usbb_ufeatures_t UFEATURES ;\n };\n const unsigned long uaddrsize ;//0x0820\n const unsigned long uname1 ;//0x0824\n const unsigned long uname2 ;//0x0828\n union {\n const unsigned long usbfsm ;//0x082c\n const avr32_usbb_usbfsm_t USBFSM ;\n };\n} avr32_usbb_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n/*#ifdef AVR32_USBB_310_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/avr32/wdt_230.h", "content": "/*****************************************************************************\n *\n * Copyright (C) 2008-2010 Atmel Corporation\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * * Neither the name of the copyright holders nor the names of\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n * \n * Model : UC3000\n * Revision : $Revision: 74772 $\n * Checkin Date : $Date: 2010-05-14 06:51:12 +0200 (Fri, 14 May 2010) $ \n *\n ****************************************************************************/\n#ifndef AVR32_WDT_230_H_INCLUDED\n#define AVR32_WDT_230_H_INCLUDED\n\n#define AVR32_WDT_H_VERSION 230\n\n#include \"avr32/abi.h\"\n\n\n/*\n Note to user:\n\n The following defines are always generated:\n - Register offset: AVR32_WDT_\n - Bitfield mask: AVR32_WDT__\n - Bitfield offset: AVR32_WDT___OFFSET\n - Bitfield size: AVR32_WDT___SIZE\n - Bitfield values: AVR32_WDT___\n\n The following defines are generated if they don't cause ambiguities,\n i.e. the name is unique, or all values with that name are the same.\n - Bitfield mask: AVR32_WDT_\n - Bitfield offset: AVR32_WDT__OFFSET\n - Bitfield size: AVR32_WDT__SIZE\n - Bitfield values: AVR32_WDT__\n - Bitfield values: AVR32_WDT_\n\n All defines are sorted alphabetically.\n*/\n\n\n#define AVR32_WDT_CLR 0x00000004\n#define AVR32_WDT_CTRL 0x00000000\n#define AVR32_WDT_CTRL_EN 0\n#define AVR32_WDT_CTRL_EN_MASK 0x00000001\n#define AVR32_WDT_CTRL_EN_OFFSET 0\n#define AVR32_WDT_CTRL_EN_SIZE 1\n#define AVR32_WDT_CTRL_KEY 24\n#define AVR32_WDT_CTRL_KEY_MASK 0xff000000\n#define AVR32_WDT_CTRL_KEY_OFFSET 24\n#define AVR32_WDT_CTRL_KEY_SIZE 8\n#define AVR32_WDT_CTRL_PSEL 8\n#define AVR32_WDT_CTRL_PSEL_MASK 0x00001f00\n#define AVR32_WDT_CTRL_PSEL_OFFSET 8\n#define AVR32_WDT_CTRL_PSEL_SIZE 5\n#define AVR32_WDT_EN 0\n#define AVR32_WDT_EN_MASK 0x00000001\n#define AVR32_WDT_EN_OFFSET 0\n#define AVR32_WDT_EN_SIZE 1\n#define AVR32_WDT_KEY 24\n#define AVR32_WDT_KEY_MASK 0xff000000\n#define AVR32_WDT_KEY_OFFSET 24\n#define AVR32_WDT_KEY_SIZE 8\n#define AVR32_WDT_PSEL 8\n#define AVR32_WDT_PSEL_MASK 0x00001f00\n#define AVR32_WDT_PSEL_OFFSET 8\n#define AVR32_WDT_PSEL_SIZE 5\n\n#define AVR32_WDT_KEY_VALUE 0x00000055\n\n\n\n#ifdef __AVR32_ABI_COMPILER__\n\n\ntypedef struct avr32_wdt_ctrl_t {\n unsigned int key : 8;\n unsigned int :11;\n unsigned int psel : 5;\n unsigned int : 7;\n unsigned int en : 1;\n} avr32_wdt_ctrl_t;\n\n\n\ntypedef struct avr32_wdt_t {\n union {\n unsigned long ctrl ;//0x0000\n avr32_wdt_ctrl_t CTRL ;\n };\n unsigned long clr ;//0x0004\n} avr32_wdt_t;\n\n\n\n/*#ifdef __AVR32_ABI_COMPILER__*/\n#endif\n\n/*#ifdef AVR32_WDT_230_H_INCLUDED*/\n#endif\n\n" }, { "path": "firmware/mock_hardware/include/board.h", "content": "#include \"conf_board.h\"\n" }, { "path": "firmware/mock_hardware/include/compiler.h", "content": "#include \n#include \n#include \n#include \n\n#include \"avr32/io.h\"\n\n#ifndef _COMPILER_AVR32_H_\n#define _COMPILER_AVR32_H_\n\n#define COMPILER_PRAGMA(arg) \n#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))\n#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())\n#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))\n\n#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))\n\ntypedef int8_t S8; //!< 8-bit signed integer.\ntypedef uint8_t U8; //!< 8-bit unsigned integer.\ntypedef int16_t S16; //!< 16-bit signed integer.\ntypedef uint16_t U16; //!< 16-bit unsigned integer.\ntypedef uint16_t le16_t;\ntypedef uint16_t be16_t;\ntypedef int32_t S32; //!< 32-bit signed integer.\ntypedef uint32_t U32; //!< 32-bit unsigned integer.\ntypedef uint32_t le32_t;\ntypedef uint32_t be32_t;\ntypedef signed long long int S64; //!< 64-bit signed integer.\ntypedef unsigned long long int U64; //!< 64-bit unsigned integer.\ntypedef float F32; //!< 32-bit floating-point number.\ntypedef double F64; //!< 64-bit floating-point number.\ntypedef uint32_t iram_size_t;\n//! @}\n\n/*! \\name Status Types\n */\n//! @{\ntypedef bool Status_bool_t; //!< Boolean status.\ntypedef U8 Status_t; //!< 8-bit-coded status.\n//! @}\n\n/*! \\name Aliasing Aggregate Types\n */\n//! @{\n\n//! 16-bit union.\ntypedef union\n{\n S16 s16;\n U16 u16;\n S8 s8[2];\n U8 u8[2];\n} Union16;\n\n//! 32-bit union.\ntypedef union\n{\n S32 s32;\n U32 u32;\n S16 s16[2];\n U16 u16[2];\n S8 s8[4];\n U8 u8[4];\n} Union32;\n\n//! 64-bit union.\ntypedef union\n{\n S64 s64;\n U64 u64;\n S32 s32[2];\n U32 u32[2];\n S16 s16[4];\n U16 u16[4];\n S8 s8[8];\n U8 u8[8];\n} Union64;\n\n//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\ntypedef union\n{\n S64* s64ptr;\n U64* u64ptr;\n S32* s32ptr;\n U32* u32ptr;\n S16* s16ptr;\n U16* u16ptr;\n S8* s8ptr;\n U8* u8ptr;\n} UnionPtr;\n\n//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\ntypedef union\n{\n volatile S64* s64ptr;\n volatile U64* u64ptr;\n volatile S32* s32ptr;\n volatile U32* u32ptr;\n volatile S16* s16ptr;\n volatile U16* u16ptr;\n volatile S8* s8ptr;\n volatile U8* u8ptr;\n} UnionVPtr;\n\n//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\ntypedef union\n{\n const S64* s64ptr;\n const U64* u64ptr;\n const S32* s32ptr;\n const U32* u32ptr;\n const S16* s16ptr;\n const U16* u16ptr;\n const S8* s8ptr;\n const U8* u8ptr;\n} UnionCPtr;\n\n//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\ntypedef union\n{\n const volatile S64* s64ptr;\n const volatile U64* u64ptr;\n const volatile S32* s32ptr;\n const volatile U32* u32ptr;\n const volatile S16* s16ptr;\n const volatile U16* u16ptr;\n const volatile S8* s8ptr;\n const volatile U8* u8ptr;\n} UnionCVPtr;\n\n//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\ntypedef struct\n{\n S64* s64ptr;\n U64* u64ptr;\n S32* s32ptr;\n U32* u32ptr;\n S16* s16ptr;\n U16* u16ptr;\n S8* s8ptr;\n U8* u8ptr;\n} StructPtr;\n\n//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\ntypedef struct\n{\n volatile S64* s64ptr;\n volatile U64* u64ptr;\n volatile S32* s32ptr;\n volatile U32* u32ptr;\n volatile S16* s16ptr;\n volatile U16* u16ptr;\n volatile S8* s8ptr;\n volatile U8* u8ptr;\n} StructVPtr;\n\n//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\ntypedef struct\n{\n const S64* s64ptr;\n const U64* u64ptr;\n const S32* s32ptr;\n const U32* u32ptr;\n const S16* s16ptr;\n const U16* u16ptr;\n const S8* s8ptr;\n const U8* u8ptr;\n} StructCPtr;\n\n//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\ntypedef struct\n{\n const volatile S64* s64ptr;\n const volatile U64* u64ptr;\n const volatile S32* s32ptr;\n const volatile U32* u32ptr;\n const volatile S16* s16ptr;\n const volatile U16* u16ptr;\n const volatile S8* s8ptr;\n const volatile U8* u8ptr;\n} StructCVPtr;\n\n\n/*! \\name Usual Constants\n */\n//! @{\n#define DISABLE 0\n#define ENABLE 1\n#ifndef __cplusplus\n#if !defined(__bool_true_false_are_defined)\n#define false 0\n#define true 1\n#endif\n#endif\n#define PASS 0\n#define FAIL 1\n#define LOW 0\n#define HIGH 1\n//! @}\n\n\n/*! \\name Mathematics\n *\n * The same considerations as for clz and ctz apply here but AVR32-GCC does not\n * provide built-in functions to access the assembly instructions abs, min and\n * max and it does not produce them by itself in most cases, so two sets of\n * macros are defined here:\n * - Abs, Min and Max to apply to constant expressions (values known at\n * compile time);\n * - abs, min and max to apply to non-constant expressions (values unknown at\n * compile time).\n */\n//! @{\n\n/*! \\brief Takes the absolute value of \\a a.\n *\n * \\param a Input value.\n *\n * \\return Absolute value of \\a a.\n *\n * \\note More optimized if only used with values known at compile time.\n */\n#define Abs(a) (((a) < 0) ? -(a) : (a))\n\n/*! \\brief Takes the minimal value of \\a a and \\a b.\n *\n * \\param a Input value.\n * \\param b Input value.\n *\n * \\return Minimal value of \\a a and \\a b.\n *\n * \\note More optimized if only used with values known at compile time.\n */\n#define Min(a, b) (((a) < (b)) ? (a) : (b))\n\n/*! \\brief Takes the maximal value of \\a a and \\a b.\n *\n * \\param a Input value.\n * \\param b Input value.\n *\n * \\return Maximal value of \\a a and \\a b.\n *\n * \\note More optimized if only used with values known at compile time.\n */\n#define Max(a, b) (((a) > (b)) ? (a) : (b))\n\n#define abs(a) Abs(a)\n#define min(a, b) Min(a, b)\n#define max(a, b) Max(a, b)\n\n#endif" }, { "path": "firmware/mock_hardware/include/conf_usb_host.h", "content": "#include \"compiler.h\"" }, { "path": "firmware/mock_hardware/include/delay.h", "content": "#define delay_ms(delay)\n#define delay_us(delay)" }, { "path": "firmware/mock_hardware/include/flashc.h", "content": "#include \n#include \"conf_board.h\"\n\nvoid hardware_declareNVRAM(const void* ptr, uint32_t bytes);\nvoid hardware_declareVRAM(const void* ptr, uint32_t bytes);\n\n#define DECLARE_NVRAM(ptr, bytes) \\\n void declare_nvram_constructor(void) __attribute__((constructor)); \\\n void declare_nvram_constructor(void) \\\n { \\\n hardware_declareNVRAM(ptr, bytes); \\\n }\n\n#define DECLARE_VRAM(ptr, bytes) \\\n void declare_vram_constructor(void) __attribute__((constructor)); \\\n void declare_vram_constructor(void) \\\n { \\\n hardware_declareVRAM(ptr, bytes); \\\n }\n\nvoid* flashc_memset8(void* dst, uint8_t src, size_t nbytes, bool erase);\nvoid* flashc_memset16(void* dst, uint16_t src, size_t nbytes, bool erase);\nvoid* flashc_memset32(void* dst, uint32_t src, size_t nbytes, bool erase);\nvoid* flashc_memset64(void* dst, uint64_t src, size_t nbytes, bool erase);\nvoid* flashc_memcpy(void* dst, const void* src, size_t nbytes, bool erase);\n" }, { "path": "firmware/mock_hardware/include/fs_com.h", "content": "" }, { "path": "firmware/mock_hardware/include/ftdi.h", "content": "#include \"types.h\"\n#include \"uhc.h\"\n\n#pragma once\n\n#define FTDI_RX_BUF_SIZE 64\n#define FTDI_STATUS_BYTES 2\n\nvoid ftdi_read(void);\nvoid ftdi_write(u8* data, u32 bytes);\n\nvoid ftdi_change(uhc_device_t* dev, u8 plug);\nvoid ftdi_setup(void);\n\nu8* ftdi_rx_buf(void);\nvolatile u8 ftdi_rx_bytes(void);\nvolatile u8 ftdi_rx_busy(void);\nvolatile u8 ftdi_tx_busy(void);\nu8 ftdi_connected(void);\n" }, { "path": "firmware/mock_hardware/include/gpio.h", "content": "#include \"compiler.h\"\n\nbool gpio_get_pin_value(uint32_t pin);\nvoid gpio_set_gpio_pin(uint32_t pin);\nvoid gpio_clr_gpio_pin(uint32_t pin);\nvoid gpio_set_pin_high(uint32_t pin);\nvoid gpio_set_pin_low(uint32_t pin);\n" }, { "path": "firmware/mock_hardware/include/intc.h", "content": "" }, { "path": "firmware/mock_hardware/include/interrupt.h", "content": "#define cpu_irq_enable_level(level) \n#define cpu_irq_disable_level(level) \n#define cpu_irq_enable() \n#define irq_initialize_vectors()\n#define Disable_global_interrupt()\n#define Enable_global_interrupt()\n" }, { "path": "firmware/mock_hardware/include/parts.h", "content": "" }, { "path": "firmware/mock_hardware/include/pm.h", "content": "" }, { "path": "firmware/mock_hardware/include/preprocessor.h", "content": "" }, { "path": "firmware/mock_hardware/include/print_funcs.h", "content": "\n#include \"compiler.h\"\n#include \n#include \n\nextern void init_dbg_rs232(long pba_hz);\n\n#ifdef FIRMWARE_DEBUG_OUTPUT\nstatic inline void print_dbg(const char* str) { fprintf(stderr, \"%s\", str); }\nstatic inline void print_dbg_char(int c) { fprintf(stderr, \"%d\", c); }\nstatic inline void print_dbg_ulong(unsigned long n) { fprintf(stderr, \"%ld\", n); }\nstatic inline void print_dbg_char_hex(unsigned char n) { fprintf(stderr, \"%x\", n); }\nstatic inline void print_dbg_short_hex(unsigned short n) { fprintf(stderr, \"%d\", n); }\nstatic inline void print_dbg_hex(unsigned long n) { fprintf(stderr, \"%lx\", n); }\n#else\nstatic inline void print_dbg(const char* str) { }\nstatic inline void print_dbg_char(int c) { }\nstatic inline void print_dbg_ulong(unsigned long n) { }\nstatic inline void print_dbg_char_hex(unsigned char n) { }\nstatic inline void print_dbg_short_hex(unsigned short n) { }\nstatic inline void print_dbg_hex(unsigned long n) { }\n#endif" }, { "path": "firmware/mock_hardware/include/spi.h", "content": "typedef enum {\n SPI_ERROR = -1,\n SPI_OK = 0,\n SPI_ERROR_TIMEOUT = 1,\n SPI_ERROR_ARGUMENT,\n SPI_ERROR_OVERRUN,\n SPI_ERROR_MODE_FAULT,\n SPI_ERROR_OVERRUN_AND_MODE_FAULT\n} spi_status_t;\n\nspi_status_t spi_selectChip(volatile void *spi, uint8_t chip);\nspi_status_t spi_unselectChip(volatile void *spi, uint8_t chip);\nspi_status_t spi_write(volatile void *spi, uint16_t data);" }, { "path": "firmware/mock_hardware/include/sysclk.h", "content": "void sysclk_init(void);\n" }, { "path": "firmware/mock_hardware/include/tc.h", "content": "" }, { "path": "firmware/mock_hardware/include/twi.h", "content": "" }, { "path": "firmware/mock_hardware/include/usart.h", "content": "" }, { "path": "firmware/mock_hardware/include/usb_protocol.h", "content": "/**\n * \\file\n *\n * \\brief USB protocol definitions.\n *\n * This file contains the USB definitions and data structures provided by the\n * USB 2.0 specification.\n *\n * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.\n *\n * \\asf_license_start\n *\n * \\page License\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n *\n * 3. The name of Atmel may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * 4. This software may only be redistributed and used in connection with an\n * Atmel microcontroller product.\n *\n * THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR IMPLIED\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n * \\asf_license_stop\n *\n */\n/*\n * Support and FAQ: visit Atmel Support\n */\n\n#ifndef _USB_PROTOCOL_H_\n#define _USB_PROTOCOL_H_\n\n#include \"usb_atmel.h\"\n#include \"compiler.h\"\n\n/**\n * \\ingroup usb_group\n * \\defgroup usb_protocol_group USB Protocol Definitions\n *\n * This module defines constants and data structures provided by the USB\n * 2.0 specification.\n *\n * @{\n */\n\n//! Value for field bcdUSB\n#define USB_V2_0 0x0200 //!< USB Specification version 2.00\n#define USB_V2_1 0x0201 //!< USB Specification version 2.01\n\n/*! \\name Generic definitions (Class, subclass and protocol)\n */\n//! @{\n#define NO_CLASS 0x00\n#define CLASS_VENDOR_SPECIFIC 0xFF\n#define NO_SUBCLASS 0x00\n#define NO_PROTOCOL 0x00\n//! @}\n\n//! \\name IAD (Interface Association Descriptor) constants\n//! @{\n#define CLASS_IAD 0xEF\n#define SUB_CLASS_IAD 0x02\n#define PROTOCOL_IAD 0x01\n//! @}\n\n/**\n * \\brief USB request data transfer direction (bmRequestType)\n */\n#define USB_REQ_DIR_OUT (0 << 7) //!< Host to device\n#define USB_REQ_DIR_IN (1 << 7) //!< Device to host\n#define USB_REQ_DIR_MASK (1 << 7) //!< Mask\n\n/**\n * \\brief USB request types (bmRequestType)\n */\n#define USB_REQ_TYPE_STANDARD (0 << 5) //!< Standard request\n#define USB_REQ_TYPE_CLASS (1 << 5) //!< Class-specific request\n#define USB_REQ_TYPE_VENDOR (2 << 5) //!< Vendor-specific request\n#define USB_REQ_TYPE_MASK (3 << 5) //!< Mask\n\n/**\n * \\brief USB recipient codes (bmRequestType)\n */\n#define USB_REQ_RECIP_DEVICE (0 << 0) //!< Recipient device\n#define USB_REQ_RECIP_INTERFACE (1 << 0) //!< Recipient interface\n#define USB_REQ_RECIP_ENDPOINT (2 << 0) //!< Recipient endpoint\n#define USB_REQ_RECIP_OTHER (3 << 0) //!< Recipient other\n#define USB_REQ_RECIP_MASK (0x1F) //!< Mask\n\n/**\n * \\brief Standard USB requests (bRequest)\n */\nenum usb_reqid\n{\n USB_REQ_GET_STATUS = 0,\n USB_REQ_CLEAR_FEATURE = 1,\n USB_REQ_SET_FEATURE = 3,\n USB_REQ_SET_ADDRESS = 5,\n USB_REQ_GET_DESCRIPTOR = 6,\n USB_REQ_SET_DESCRIPTOR = 7,\n USB_REQ_GET_CONFIGURATION = 8,\n USB_REQ_SET_CONFIGURATION = 9,\n USB_REQ_GET_INTERFACE = 10,\n USB_REQ_SET_INTERFACE = 11,\n USB_REQ_SYNCH_FRAME = 12,\n};\n\n/**\n * \\brief Standard USB device status flags\n *\n */\nenum usb_device_status\n{\n USB_DEV_STATUS_BUS_POWERED = 0,\n USB_DEV_STATUS_SELF_POWERED = 1,\n USB_DEV_STATUS_REMOTEWAKEUP = 2\n};\n\n/**\n * \\brief Standard USB Interface status flags\n *\n */\nenum usb_interface_status\n{\n USB_IFACE_STATUS_RESERVED = 0\n};\n\n/**\n * \\brief Standard USB endpoint status flags\n *\n */\nenum usb_endpoint_status\n{\n USB_EP_STATUS_HALTED = 1,\n};\n\n/**\n * \\brief Standard USB device feature flags\n *\n * \\note valid for SetFeature request.\n */\nenum usb_device_feature\n{\n USB_DEV_FEATURE_REMOTE_WAKEUP = 1, //!< Remote wakeup enabled\n USB_DEV_FEATURE_TEST_MODE = 2, //!< USB test mode\n USB_DEV_FEATURE_OTG_B_HNP_ENABLE = 3,\n USB_DEV_FEATURE_OTG_A_HNP_SUPPORT = 4,\n USB_DEV_FEATURE_OTG_A_ALT_HNP_SUPPORT = 5\n};\n\n/**\n * \\brief Test Mode possible on HS USB device\n *\n * \\note valid for USB_DEV_FEATURE_TEST_MODE request.\n */\nenum usb_device_hs_test_mode\n{\n USB_DEV_TEST_MODE_J = 1,\n USB_DEV_TEST_MODE_K = 2,\n USB_DEV_TEST_MODE_SE0_NAK = 3,\n USB_DEV_TEST_MODE_PACKET = 4,\n USB_DEV_TEST_MODE_FORCE_ENABLE = 5,\n};\n\n/**\n * \\brief Standard USB endpoint feature/status flags\n */\nenum usb_endpoint_feature\n{\n USB_EP_FEATURE_HALT = 0,\n};\n\n/**\n * \\brief Standard USB Test Mode Selectors\n */\nenum usb_test_mode_selector\n{\n USB_TEST_J = 0x01,\n USB_TEST_K = 0x02,\n USB_TEST_SE0_NAK = 0x03,\n USB_TEST_PACKET = 0x04,\n USB_TEST_FORCE_ENABLE = 0x05,\n};\n\n/**\n * \\brief Standard USB descriptor types\n */\nenum usb_descriptor_type\n{\n USB_DT_DEVICE = 1,\n USB_DT_CONFIGURATION = 2,\n USB_DT_STRING = 3,\n USB_DT_INTERFACE = 4,\n USB_DT_ENDPOINT = 5,\n USB_DT_DEVICE_QUALIFIER = 6,\n USB_DT_OTHER_SPEED_CONFIGURATION = 7,\n USB_DT_INTERFACE_POWER = 8,\n USB_DT_OTG = 9,\n USB_DT_IAD = 0x0B,\n USB_DT_BOS = 0x0F,\n USB_DT_DEVICE_CAPABILITY = 0x10,\n};\n\n/**\n * \\brief USB Device Capability types\n */\nenum usb_capability_type\n{\n USB_DC_USB20_EXTENSION = 0x02,\n};\n\n/**\n * \\brief USB Device Capability - USB 2.0 Extension\n * To fill bmAttributes field of usb_capa_ext_desc_t structure.\n */\nenum usb_capability_extension_attr\n{\n USB_DC_EXT_LPM = 0x00000002,\n};\n\n#define HIRD_50_US 0\n#define HIRD_125_US 1\n#define HIRD_200_US 2\n#define HIRD_275_US 3\n#define HIRD_350_US 4\n#define HIRD_425_US 5\n#define HIRD_500_US 6\n#define HIRD_575_US 7\n#define HIRD_650_US 8\n#define HIRD_725_US 9\n#define HIRD_800_US 10\n#define HIRD_875_US 11\n#define HIRD_950_US 12\n#define HIRD_1025_US 13\n#define HIRD_1100_US 14\n#define HIRD_1175_US 15\n\n/** Fields definition from a LPM TOKEN */\n#define USB_LPM_ATTRIBUT_BLINKSTATE_MASK (0xF << 0)\n#define USB_LPM_ATTRIBUT_FIRD_MASK (0xF << 4)\n#define USB_LPM_ATTRIBUT_REMOTEWAKE_MASK (1 << 8)\n#define USB_LPM_ATTRIBUT_BLINKSTATE(value) ((value & 0xF) << 0)\n#define USB_LPM_ATTRIBUT_FIRD(value) ((value & 0xF) << 4)\n#define USB_LPM_ATTRIBUT_REMOTEWAKE(value) ((value & 1) << 8)\n#define USB_LPM_ATTRIBUT_BLINKSTATE_L1 USB_LPM_ATTRIBUT_BLINKSTATE(1)\n\n/**\n * \\brief Standard USB endpoint transfer types\n */\nenum usb_ep_type\n{\n USB_EP_TYPE_CONTROL = 0x00,\n USB_EP_TYPE_ISOCHRONOUS = 0x01,\n USB_EP_TYPE_BULK = 0x02,\n USB_EP_TYPE_INTERRUPT = 0x03,\n USB_EP_TYPE_MASK = 0x03,\n};\n\n/**\n * \\brief Standard USB language IDs for string descriptors\n */\nenum usb_langid\n{\n USB_LANGID_EN_US = 0x0409, //!< English (United States)\n};\n\n/**\n * \\brief Mask selecting the index part of an endpoint address\n */\n#define USB_EP_ADDR_MASK 0x0f\n\n//! \\brief USB address identifier\ntypedef uint8_t usb_add_t;\n\n/**\n * \\brief Endpoint transfer direction is IN\n */\n#define USB_EP_DIR_IN 0x80\n\n/**\n * \\brief Endpoint transfer direction is OUT\n */\n#define USB_EP_DIR_OUT 0x00\n\n//! \\brief Endpoint identifier\ntypedef uint8_t usb_ep_t;\n\n/**\n * \\brief Maximum length in bytes of a USB descriptor\n *\n * The maximum length of a USB descriptor is limited by the 8-bit\n * bLength field.\n */\n#define USB_MAX_DESC_LEN 255\n\n/*\n * 2-byte alignment requested for all USB structures.\n */\n//COMPILER_PACK_SET(1)\n\n/**\n * \\brief A USB Device SETUP request\n *\n * The data payload of SETUP packets always follows this structure.\n */\ntypedef struct\n{\n uint8_t bmRequestType;\n uint8_t bRequest;\n le16_t wValue;\n le16_t wIndex;\n le16_t wLength;\n} usb_setup_req_t;\n\n/**\n * \\brief Standard USB device descriptor structure\n */\ntypedef struct\n{\n uint8_t bLength;\n uint8_t bDescriptorType;\n le16_t bcdUSB;\n uint8_t bDeviceClass;\n uint8_t bDeviceSubClass;\n uint8_t bDeviceProtocol;\n uint8_t bMaxPacketSize0;\n le16_t idVendor;\n le16_t idProduct;\n le16_t bcdDevice;\n uint8_t iManufacturer;\n uint8_t iProduct;\n uint8_t iSerialNumber;\n uint8_t bNumConfigurations;\n} usb_dev_desc_t;\n\n/**\n * \\brief Standard USB device qualifier descriptor structure\n *\n * This descriptor contains information about the device when running at\n * the \"other\" speed (i.e. if the device is currently operating at high\n * speed, this descriptor can be used to determine what would change if\n * the device was operating at full speed.)\n */\ntypedef struct\n{\n uint8_t bLength;\n uint8_t bDescriptorType;\n le16_t bcdUSB;\n uint8_t bDeviceClass;\n uint8_t bDeviceSubClass;\n uint8_t bDeviceProtocol;\n uint8_t bMaxPacketSize0;\n uint8_t bNumConfigurations;\n uint8_t bReserved;\n} usb_dev_qual_desc_t;\n\n/**\n * \\brief USB Device BOS descriptor structure\n *\n * The BOS descriptor (Binary device Object Store) defines a root\n * descriptor that is similar to the configuration descriptor, and is\n * the base descriptor for accessing a family of related descriptors.\n * A host can read a BOS descriptor and learn from the wTotalLength field\n * the entire size of the device-level descriptor set, or it can read in\n * the entire BOS descriptor set of device capabilities.\n * The host accesses this descriptor using the GetDescriptor() request.\n * The descriptor type in the GetDescriptor() request is set to BOS.\n */\ntypedef struct\n{\n uint8_t bLength;\n uint8_t bDescriptorType;\n le16_t wTotalLength;\n uint8_t bNumDeviceCaps;\n} usb_dev_bos_desc_t;\n\n/**\n * \\brief USB Device Capabilities - USB 2.0 Extension Descriptor structure\n *\n * Defines the set of USB 1.1-specific device level capabilities.\n */\ntypedef struct\n{\n uint8_t bLength;\n uint8_t bDescriptorType;\n uint8_t bDevCapabilityType;\n le32_t bmAttributes;\n} usb_dev_capa_ext_desc_t;\n\n/**\n * \\brief USB Device LPM Descriptor structure\n *\n * The BOS descriptor and capabilities descriptors for LPM.\n */\ntypedef struct\n{\n usb_dev_bos_desc_t bos;\n usb_dev_capa_ext_desc_t capa_ext;\n} usb_dev_lpm_desc_t;\n\n/**\n * \\brief Standard USB Interface Association Descriptor structure\n */\ntypedef struct\n{\n uint8_t bLength; //!< size of this descriptor in bytes\n uint8_t bDescriptorType; //!< INTERFACE descriptor type\n uint8_t bFirstInterface; //!< Number of interface\n uint8_t bInterfaceCount; //!< value to select alternate setting\n uint8_t bFunctionClass; //!< Class code assigned by the USB\n uint8_t bFunctionSubClass; //!< Sub-class code assigned by the USB\n uint8_t bFunctionProtocol; //!< Protocol code assigned by the USB\n uint8_t iFunction; //!< Index of string descriptor\n} usb_association_desc_t;\n\n/**\n * \\brief Standard USB configuration descriptor structure\n */\ntypedef struct\n{\n uint8_t bLength;\n uint8_t bDescriptorType;\n le16_t wTotalLength;\n uint8_t bNumInterfaces;\n uint8_t bConfigurationValue;\n uint8_t iConfiguration;\n uint8_t bmAttributes;\n uint8_t bMaxPower;\n} usb_conf_desc_t;\n\n#define USB_CONFIG_ATTR_MUST_SET (1 << 7) //!< Must always be set\n#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) //!< Bus-powered\n#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) //!< Self-powered\n#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) //!< remote wakeup supported\n\n#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) //!< Max power in mA\n\n/**\n * \\brief Standard USB association descriptor structure\n */\ntypedef struct\n{\n uint8_t bLength; //!< Size of this descriptor in bytes\n uint8_t bDescriptorType; //!< Interface descriptor type\n uint8_t bFirstInterface; //!< Number of interface\n uint8_t bInterfaceCount; //!< value to select alternate setting\n uint8_t bFunctionClass; //!< Class code assigned by the USB\n uint8_t bFunctionSubClass; //!< Sub-class code assigned by the USB\n uint8_t bFunctionProtocol; //!< Protocol code assigned by the USB\n uint8_t iFunction; //!< Index of string descriptor\n} usb_iad_desc_t;\n\n/**\n * \\brief Standard USB interface descriptor structure\n */\ntypedef struct\n{\n uint8_t bLength;\n uint8_t bDescriptorType;\n uint8_t bInterfaceNumber;\n uint8_t bAlternateSetting;\n uint8_t bNumEndpoints;\n uint8_t bInterfaceClass;\n uint8_t bInterfaceSubClass;\n uint8_t bInterfaceProtocol;\n uint8_t iInterface;\n} usb_iface_desc_t;\n\n/**\n * \\brief Standard USB endpoint descriptor structure\n */\ntypedef struct\n{\n uint8_t bLength;\n uint8_t bDescriptorType;\n uint8_t bEndpointAddress;\n uint8_t bmAttributes;\n le16_t wMaxPacketSize;\n uint8_t bInterval;\n} usb_ep_desc_t;\n\n/**\n * \\brief A standard USB string descriptor structure\n */\ntypedef struct\n{\n uint8_t bLength;\n uint8_t bDescriptorType;\n} usb_str_desc_t;\n\ntypedef struct\n{\n usb_str_desc_t desc;\n le16_t string[1];\n} usb_str_lgid_desc_t;\n\n//COMPILER_PACK_RESET()\n\n//! @}\n\n#endif /* _USB_PROTOCOL_H_ */\n" }, { "path": "firmware/mock_hardware/mock_hardware_api.c", "content": "#include \"mock_hardware_api.h\"\n#include \"mock_hardware_api_private.h\"\n#include \"mock_serial.h\"\n#include \"mock_interrupt.h\"\n\n#include \"events.h\"\n#include \"hid.h\"\n\n#include \"cbbq.h\"\n//#include \"test/cbbq_utils.h\"\n\n#include \n#include \n\n\n#define GPIO_NUM_PINS 50\nbool gpioBlock[GPIO_NUM_PINS];\n\nuint16_t adcBlock[4];\nuint16_t dacBlock[4];\n\n#define VSERIAL_IN_BUFFER_SIZE 512\n#define VSERIAL_OUT_BUFFER_SIZE 512\n\ncbbq serial_in_queue;\ncbbq serial_out_queue;\n\nvoid* nvram_ptr = NULL;\nvoid* vram_ptr = NULL;\nuint32_t nvram_size = 0;\nuint32_t vram_size = 0;\n\nuint8_t* screenBuffer = NULL;\n#define SCREEN_WIDTH 128\n#define SCREEN_HEIGHT 64\n\n// main interface points to module code -- the two halves of main() in the original source\nextern void initialize_module(void);\nextern void check_events(void);\n\n// this *could* be simulated as an event, but key press/hold has already been calculated in glfw,\n// and getting module timing assumptions right is tricky, so just let's just skip to the handler\nextern void process_keypress(uint8_t key, uint8_t mod_key, bool is_held_key, bool is_release);\n\n\nvoid hardware_hidMessage(uint8_t key, uint8_t mod, bool held, bool release)\n{\n process_keypress(key, mod, held, release);\n}\n\nvoid hardware_hidConnect()\n{\n event_t ev;\n ev.type = kEventHidConnect;\n event_post(&ev);\n}\n\nvoid hardware_hidDisconnect()\n{\n event_t ev;\n ev.type = kEventHidDisconnect;\n event_post(&ev);\n}\n\nvoid initialize_serial()\n{\n queue_init(&serial_in_queue, VSERIAL_IN_BUFFER_SIZE);\n queue_init(&serial_out_queue, VSERIAL_OUT_BUFFER_SIZE);\n}\n\nvoid hardware_init()\n{\n initialize_serial();\n initialize_module();\n hardware_afterInit();\n}\n\nvoid hardware_step()\n{\n check_events();\n hardware_afterStep();\n}\n\nvoid hardware_triggerInterrupt(int interrupt)\n{\n mock_interrupt(interrupt);\n}\n\nbool hardware_getGPIO(uint32_t pin)\n{\n if (pin >= 0 && pin < GPIO_NUM_PINS)\n {\n return gpioBlock[pin];\n }\n return false;\n}\n\nvoid hardware_setGPIO(uint32_t pin, bool value)\n{\n if (pin >= 0 && pin < GPIO_NUM_PINS)\n {\n // Check for interrupt on pins A00-A07\n bool changed = false;\n if (pin < 8 && gpioBlock[pin] != value)\n {\n changed = true;\n }\n\n gpioBlock[pin] = value;\n\n // Trigger interrupt only on rising edge\n if (changed && value)\n {\n mock_gpio_interrupt(pin);\n }\n }\n}\n\nuint16_t hardware_getADC(int channel)\n{\n return adcBlock[channel];\n}\n\nvoid hardware_setADC(int channel, uint16_t value)\n{\n adcBlock[channel] = value;\n}\n\nuint16_t hardware_getDAC(int channel)\n{\n return dacBlock[channel];\n}\n\nvoid hardware_setDAC(int channel, uint16_t value)\n{\n dacBlock[channel] = value;\n}\n\nvoid hardware_postEvent(uint32_t type, uint32_t data)\n{\n event_t e;\n e.type = type;\n e.data = data;\n event_post(&e);\n}\n\nvoid hardware_serialConnectionChange(bool connected, uint8_t type, uint8_t protocol, uint8_t width, uint8_t height)\n{\n mock_monome_serial_setup(connected, type, protocol, width, height);\n}\n\nint hardware_readSerial(uint8_t** pbuf, uint8_t* pcount)\n{\n int ret = queue_read(&serial_out_queue, pbuf, pcount);\n // queue_display(&serial_out_queue);\n // printf(\"hardware_readSerial queue_read returned: %d\\n\", ret);\n return ret;\n}\n\nint hardware_writeSerial_internal(uint8_t* buf, uint8_t byteCount)\n{\n int ret = queue_write(&serial_out_queue, buf, byteCount);\n // queue_display(&serial_out_queue);\n // printf(\"hardware_writeSerial_internal queue_write returned: %d\\n\", ret);\n return ret;\n}\n\nint hardware_readSerial_internal(uint8_t** pbuf, uint8_t* pcount)\n{\n int ret = queue_read(&serial_in_queue, pbuf, pcount);\n // queue_display(&serial_in_queue);\n // printf(\"hardware_readSerial_internal queue_read returned: %d\\n\", ret);\n return ret;\n}\n\nint hardware_writeSerial(uint8_t* buf, uint8_t byteCount)\n{\n int ret = queue_write(&serial_in_queue, buf, byteCount);\n // queue_display(&serial_in_queue);\n // printf(\"hardware_writeSerial queue_write returned: %d\\n\", ret);\n return ret;\n}\n\nvoid hardware_declareNVRAM(void* ptr, uint32_t size)\n{\n nvram_ptr = ptr;\n nvram_size = size;\n}\n\nvoid hardware_readNVRAM(void** ptr, uint32_t* size)\n{\n *ptr = nvram_ptr;\n *size = nvram_size;\n}\n\nvoid hardware_writeNVRAM(const void* src, uint32_t size)\n{\n memcpy(nvram_ptr, src, nvram_size >= size ? size : nvram_size);\n}\n\nvoid hardware_declareVRAM(void* ptr, uint32_t size)\n{\n vram_ptr = ptr;\n vram_size = size;\n}\n\nvoid hardware_readVRAM(void** ptr, uint32_t* size)\n{\n hardware_beforeReadVRAM(vram_ptr, vram_size);\n\n if (ptr)\n {\n *ptr = vram_ptr;\n }\n if (size)\n {\n *size = vram_size;\n }\n}\n\nvoid hardware_writeVRAM(const void* src, uint32_t size)\n{\n memcpy(vram_ptr, src, vram_size >= size ? size : vram_size);\n hardware_afterWriteVRAM(vram_ptr, vram_size);\n}\n\nvoid hardware_getScreenBuffer(uint8_t** ptr, uint16_t* width, uint16_t* height)\n{\n if (ptr) *ptr = screenBuffer;\n if (width)\n *width = 128;\n if (height)\n *height = 64;\n}\n\nvoid hardware_setScreenBuffer(uint8_t* buf)\n{\n screenBuffer = buf;\n}\n\n// TODO: make this generic to support more follower types\nuint16_t faderbank[64];\n\nvoid hardware_iiUpdateFollowerData(uint8_t device, uint8_t param, uint16_t data)\n{\n // For now, only support 16 params each on devices 0x34-0x37\n uint8_t offset = device - 0x34;\n if (offset < 4 && param < 16)\n {\n uint8_t index = offset * 16 + param;\n faderbank[index] = data;\n }\n}\n\nuint16_t hardware_iiGetFollowerData(uint8_t device, uint8_t param)\n{\n // For now, only support 16 params each on devices 0x34-0x37\n uint8_t offset = device - 0x34;\n if (offset < 4 && param < 16)\n {\n uint8_t index = offset * 16 + param;\n return faderbank[index];\n }\n return 0;\n}\n\n#define II_MAX_DATA 8\n#define II_MAX_MESSAGES 32\n\ntypedef struct \n{\n uint8_t addr;\n uint8_t data[II_MAX_DATA];\n uint8_t length;\n} iiMessage;\n\niiMessage iiMessageBuffer[II_MAX_MESSAGES];\nsize_t iiMessageBufferIndex = 0;\n\nbool hardware_iiPushMessage(uint8_t addr, uint8_t* data, uint8_t length)\n{\n if (iiMessageBufferIndex < II_MAX_MESSAGES && length <= II_MAX_DATA) {\n iiMessageBuffer[iiMessageBufferIndex].addr = addr;\n iiMessageBuffer[iiMessageBufferIndex].length = length;\n memcpy(iiMessageBuffer[iiMessageBufferIndex].data, data, length);\n iiMessageBufferIndex++;\n return true;\n }\n return false;\n}\n\nbool hardware_iiPopMessage(uint8_t* addr, uint8_t* data, uint8_t* length)\n{\n if (iiMessageBufferIndex > 0)\n {\n if (addr) {\n *addr = iiMessageBuffer[iiMessageBufferIndex].addr;\n }\n if (length) {\n *length = iiMessageBuffer[iiMessageBufferIndex].length;\n }\n if (data && *length <= II_MAX_DATA) {\n memcpy(data, iiMessageBuffer[iiMessageBufferIndex].data, *length);\n }\n iiMessageBufferIndex--;\n return true;\n }\n return false;\n}\n" }, { "path": "firmware/mock_hardware/mock_hardware_api.h", "content": "#ifndef MOCK_API_SKIP_TYPES\n#include \"../teletype4/src/serializer.h\"\n#include \n#include \n#endif\n\n#ifndef MOCK_API\n#ifdef ARCH_WIN\n#define MOCK_API(returntype, name, argslist) __declspec(dllexport) \\\nreturntype hardware_##name argslist\n#elif ARCH_MAC\n#define MOCK_API(returntype, name, argslist) __attribute__((visibility(\"default\"))) \\\nreturntype hardware_##name argslist\n#elif ARCH_LIN\n#define MOCK_API(returntype, name, argslist) __attribute__((visibility(\"default\"))) \\\nreturntype hardware_##name argslist\n#endif\n#endif\n\nMOCK_API(void, init, ());\nMOCK_API(void, step, ());\n\nMOCK_API(void, triggerInterrupt, (int interrupt));\n\nMOCK_API(bool, getGPIO, (uint32_t pin));\nMOCK_API(void, setGPIO, (uint32_t pin, bool value));\n\nMOCK_API(uint16_t, getADC, (int channel));\nMOCK_API(void, setADC, (int channel, uint16_t value));\n\nMOCK_API(uint16_t, getDAC, (int channel));\nMOCK_API(void, setDAC, (int channel, uint16_t value));\n\nMOCK_API(void, postEvent, (uint32_t type, uint32_t data));\n\nMOCK_API(void, serialConnectionChange, (bool connected, uint8_t type, uint8_t protocol, uint8_t width, uint8_t height));\n\nMOCK_API(int, readSerial, (uint8_t** pbuf, uint8_t* pcount));\nMOCK_API(int, writeSerial, (uint8_t* buf, uint8_t byteCount));\n\nMOCK_API(void, readNVRAM, (void** ptr, uint32_t* size));\nMOCK_API(void, writeNVRAM, (const void* src, uint32_t size));\n\nMOCK_API(void, readVRAM, (void** ptr, uint32_t* size));\nMOCK_API(void, writeVRAM, (const void* src, uint32_t size));\n\nMOCK_API(void, setScreenBuffer, (uint8_t *ptr));\n\nMOCK_API(void, hidConnect, ());\nMOCK_API(void, hidDisconnect, ());\nMOCK_API(void, hidMessage, (uint8_t key, uint8_t mod, bool held, bool release));\n\nMOCK_API(void, iiUpdateFollowerData, (uint8_t device, uint8_t param, uint16_t data));\nMOCK_API(uint16_t, iiGetFollowerData, (uint8_t device, uint8_t param));\nMOCK_API(bool, iiPushMessage, (uint8_t addr, uint8_t* data, uint8_t length));\nMOCK_API(bool, iiPopMessage, (uint8_t* addr, uint8_t* data, uint8_t* length));\n\nMOCK_API(void, serializePreset, (tt_serializer_t* stream, uint8_t preset_num));\nMOCK_API(void, deserializePreset, (tt_deserializer_t* stream, uint8_t preset_num, bool clearExisting));\n\nMOCK_API(void, getVersion, (char* buffer));\nMOCK_API(double, getClockPeriod, ());\n" }, { "path": "firmware/mock_hardware/mock_hardware_api_private.h", "content": "// Functions that are only intended to be called internally\n\nextern int hardware_readSerial_internal(uint8_t** pbuf, uint8_t* pcount);\nextern int hardware_writeSerial_internal(uint8_t* buf, uint8_t byteCount);\n\nextern void hardware_afterInit();\nextern void hardware_afterStep();\n\nextern void hardware_beforeReadVRAM(void* ptr, uint32_t size);\nextern void hardware_afterWriteVRAM(void* ptr, uint32_t size);\n\nextern void hardware_getScreenBuffer(uint8_t **ptr, uint16_t* width, uint16_t* height);\n" }, { "path": "firmware/mock_hardware/mock_interrupt.c", "content": "#include \"mock_hardware_api.h\"\n\n// libavr32 headers\n#include \"types.h\"\n#include \"events.h\"\n#include \"timers.h\"\n\n\n#define B08 40\n#define B09 41\n#define NMI 13\n\n// state variables from module init_*.c\nvolatile u64 tcTicks = 0;\nvolatile u8 tcOverflow = 0;\nstatic const u64 tcMax = (u64)0x7fffffff;\nstatic const u64 tcMaxInv = (u64)0x10000000;\n\n\n// reimplement function from module init_*.c\nu64 get_ticks(void)\n{\n return tcTicks;\n}\n\nvoid simulate_tc_interrupt()\n{\n tcTicks++;\n // overflow control\n if (tcTicks > tcMax)\n {\n tcTicks = 0;\n tcOverflow = 1;\n }\n else\n {\n tcOverflow = 0;\n }\n process_timers();\n}\n\nvoid simulate_clock_normal_interrupt()\n{\n event_t e;\n e.type = kEventClockNormal;\n e.data = !hardware_getGPIO(B09);\n event_post(&e);\n}\n\nvoid simulate_external_clock_interrupt()\n{\n event_t e;\n e.type = kEventClockExt;\n e.data = hardware_getGPIO(B08);\n event_post(&e);\n}\n\nvoid simulate_front_button_interrupt()\n{\n event_t e;\n e.type = kEventFront;\n e.data = hardware_getGPIO(NMI);\n event_post(&e);\n}\n\nvoid mock_gpio_interrupt(int pin)\n{\n event_t e;\n e.type = kEventTrigger;\n e.data = pin;\n event_post(&e);\n}\n\nvoid simulate_ansible_tr_interrupt(int pin, int offset)\n{\n event_t e;\n e.type = kEventTr;\n e.data = hardware_getGPIO(pin) + offset;\n event_post(&e);\n}\n\n\nvoid mock_interrupt(int interrupt)\n{\n switch (interrupt)\n {\n // todo: make an enum for this\n case 0: // system clock\n simulate_tc_interrupt();\n break;\n case 1: // clock jack normal\n simulate_clock_normal_interrupt();\n break;\n case 2: // external clock rising edge\n simulate_external_clock_interrupt();\n break;\n case 3: // front button state change\n simulate_front_button_interrupt();\n break;\n case 6: // ansible input 1 change\n simulate_ansible_tr_interrupt(40, 0);\n break;\n case 7: // ansible input 2 change\n simulate_ansible_tr_interrupt(41, 2);\n break;\n }\n}" }, { "path": "firmware/mock_hardware/mock_interrupt.h", "content": "void mock_interrupt(int interrupt);\nvoid mock_gpio_interrupt(int pin);" }, { "path": "firmware/mock_hardware/mock_serial.c", "content": "// libavr32 headers\n#include \"monome.h\"\n#include \"mock_hardware_api_private.h\"\n\n#include \n#include \n\n// types and declarations private to monome.c not in monome.h\n\n// protocol enumeration\ntypedef enum\n{\n eProtocol40h, /// 40h and arduinome protocol (pre-2007)\n eProtocolSeries, /// series protocol (2007-2011)\n eProtocolMext, /// extended protocol (2011 - ? ), arcs + grids\n eProtocolNumProtocols // dummy and count\n} eMonomeProtocol;\n\n// device descriptor\ntypedef struct e_monomeDesc\n{\n eMonomeProtocol protocol;\n eMonomeDevice device;\n u8 cols; // number of columns\n u8 rows; // number of rows\n u8 encs; // number of encoders\n u8 tilt; // has tilt (??)\n u8 vari; // is variable brightness, true/false\n} monomeDesc;\n\nextern monomeDesc mdesc;\n\nextern void set_funcs();\n\n\n// end types and declarations from monome.c\n\nu8* mock_serial_current_message_buffer;\nu8 mock_serial_current_message_length;\nbool mock_serial_isconnected = false;\n\nu8 mock_serial_connected() \n{\n return mock_serial_isconnected ? 1 : 0;\n}\n\nvoid mock_serial_read(void)\n{\n while (hardware_readSerial_internal(&mock_serial_current_message_buffer, &mock_serial_current_message_length) > 0)\n {\n (*monome_read_serial)();\n }\n}\n\nvoid mock_serial_write(u8* data, u32 bytes)\n{\n hardware_writeSerial_internal(data, bytes);\n}\n\nvolatile u8 mock_serial_tx_busy()\n{\n return 0;\n}\n\nvolatile u8 mock_serial_rx_busy()\n{\n return 0;\n}\n\nu8* mock_serial_rx_buf(void)\n{\n return mock_serial_current_message_buffer;\n}\n\nvolatile u8 mock_serial_rx_bytes(void)\n{\n return mock_serial_current_message_length;\n}\n\nvoid setup_mock_serial()\n{\n serial_read = &mock_serial_read;\n serial_write = &mock_serial_write;\n tx_busy = &mock_serial_tx_busy;\n rx_busy = &mock_serial_rx_busy;\n rx_buf = &mock_serial_rx_buf;\n rx_bytes = &mock_serial_rx_bytes;\n serial_connected = &mock_serial_connected;\n}\n\nvoid mock_monome_serial_setup(bool connected, uint8_t type, uint8_t protocol, uint8_t width, uint8_t height)\n{\n if (connected)\n {\n // fill out the global mdesc structure\n mdesc.protocol = (eMonomeProtocol)protocol;\n mdesc.vari = mdesc.protocol == eProtocolMext;\n if (type == 0) {\n mdesc.device = eDeviceGrid;\n mdesc.rows = height;\n mdesc.cols = width;\n mdesc.tilt = 1;\n } else {\n mdesc.device = eDeviceArc;\n mdesc.tilt = 1;\n mdesc.encs = width;\n }\n\n // set device-specific event handlers based on the global mdesc\n set_funcs();\n setup_mock_serial();\n\n // push a connection event\n event_t ev;\n ev.type = kEventMonomeConnect;\n u8* data = (u8*)(&(ev.data));\n *data++ = (u8)(mdesc.device);\n *data++ = type? mdesc.encs : mdesc.cols;\n *data++ = mdesc.rows;\n event_post(&ev);\n\n mock_serial_isconnected = true;\n }\n else\n {\n // push a disconnect event\n event_t ev;\n // kEventFtdiDisconnect is the low-level disconnect event for both FTDI and CDC devices\n ev.type = kEventFtdiDisconnect;\n event_post(&ev);\n\n mock_serial_isconnected = false;\n }\n}\n\n" }, { "path": "firmware/mock_hardware/mock_serial.h", "content": "#include \n#include \n\nvoid mock_monome_serial_setup(bool connected, uint8_t type, uint8_t protocol, uint8_t width, uint8_t height);\n" }, { "path": "firmware/mock_hardware/modules/ansible/adapter_ansible.c", "content": "#include \"gitversion.h\"\n#include \"types.h\"\n\n#include \"mock_hardware_api.h\"\n#include \"mock_hardware_api_private.h\"\n\n#include \n\n#include \"main.h\"\n#include \"flashc.h\"\n\nvoid hid_parse_frame(u8* data, u8 sz)\n{\n}\n\nvoid process_keypress(uint8_t key, uint8_t mod_key, bool is_held_key)\n{\n}\n\nvoid hardware_serializePreset(tt_serializer_t* stream, uint8_t preset_num)\n{\n}\n\nvoid hardware_deserializePreset(tt_deserializer_t* stream, uint8_t preset_num, bool clearExisting)\n{\n}\n\nnvram_data_t ansible_vram;\nDECLARE_VRAM(&ansible_vram, sizeof(nvram_data_t))\n\nvoid hardware_beforeReadVRAM(void* ptr, uint32_t size)\n{\n save_tuning(&ansible_vram);\n save_levels(&ansible_vram);\n save_cycles(&ansible_vram);\n save_kria(&ansible_vram);\n save_mp(&ansible_vram);\n save_es(&ansible_vram);\n}\n\nvoid hardware_afterWriteVRAM(void* ptr, uint32_t size)\n{\n init_tuning(&ansible_vram);\n init_levels(&ansible_vram);\n init_cycles(&ansible_vram);\n init_kria(&ansible_vram);\n init_mp(&ansible_vram);\n init_es(&ansible_vram);\n}\n\nvoid hardware_afterInit()\n{\n}\n\nvoid hardware_afterStep()\n{\n}\n\nvoid hardware_getVersion(char* buffer)\n{\n strcpy(buffer, git_version);\n}\n\ndouble hardware_getClockPeriod()\n{\n return 0.001;\n}\n" }, { "path": "firmware/mock_hardware/modules/ansible/ansible_usb_disk.c", "content": "#include \"init_common.h\"\n#include \"main.h\"\n#include \"monome.h\"\n#include \"print_funcs.h\"\n\n#include \"ansible_preset_docdef.h\"\n#include \"ansible_usb_disk.h\"\n\ntypedef char * FS_STRING;\n\n#define DEBUG_ANSIBLE_USB_DISK 0\n#define DISK_BLINK_INTERVAL 250\n\nstatic void handler_UsbDiskKey(int32_t data);\nstatic void handler_UsbDiskFront(int32_t data);\n\nstatic bool usb_disk_mount_drive(void);\nstatic bool usb_disk_backup_binary(FS_STRING fname);\nstatic bool usb_disk_restore_backup(FS_STRING fname);\nstatic bool usb_disk_load_flash(FS_STRING fname);\nstatic bool usb_disk_save_flash(FS_STRING fname);\nstatic void flush(void);\nstatic void blink_read(void* o);\nstatic void blink_write(void* o);\n\nstatic char ansible_usb_disk_textbuf[ANSIBLE_USBDISK_TXTBUF_LEN] = { 0 };\nstatic uint8_t usb_disk_buffer[ANSIBLE_USBDISK_BLOCKSIZE] = { 0 };\nstatic jsmntok_t ansible_usb_disk_tokbuf[ANSIBLE_USBDISK_TOKBUF_LEN];\n\nstatic volatile bool usb_disk_locked = false;\n\nstatic bool usb_disk_lock(void)\n{\n if (!usb_disk_locked)\n {\n usb_disk_locked = true;\n print_dbg(\"\\r\\n\\r\\n> usb disk locked\");\n return true;\n }\n return false;\n}\n\nstatic void usb_disk_unlock(void)\n{\n usb_disk_locked = false;\n print_dbg(\"\\r\\n> usb disk unlocked\\r\\n\");\n}\n\nstatic volatile bool load_armed = false, save_armed = false;\nstatic bool blink = false;\n\nstatic void handler_UsbDiskKey(int32_t data)\n{\n}\n\nstatic void handler_UsbDiskFront(s32 data)\n{\n}\n\nstatic void blink_read(void* o)\n{\n}\n\nstatic void blink_write(void* o)\n{\n}\n\nvoid set_mode_usb_disk(void)\n{\n}\n\nbool usb_disk_enter()\n{\n}\n\nvoid usb_disk_exit()\n{\n}\n\nvoid usb_disk_skip_apps(bool skip)\n{\n}\n\nvoid usb_disk_select_app(ansible_mode_t mode)\n{\n}\n\nsize_t gets_chunks(char* dst, size_t len)\n{\n return 0;\n}\n\nstatic void copy_chunks(char* dst, const char* src, size_t len)\n{\n}\n\nstatic uint16_t buf_pos = 0;\nsize_t total_written = 0;\n\nstatic void flush(void)\n{\n}\n\nvoid puts_buffered(const char* src, size_t len)\n{\n}\n\nstatic bool usb_disk_mount_drive(void)\n{\n}\n\nstatic bool usb_disk_backup_binary(FS_STRING fname)\n{\n}\n\nstatic bool usb_disk_restore_backup(FS_STRING fname)\n{\n}\n\nstatic bool usb_disk_load_flash(FS_STRING fname)\n{\n}\n\nstatic bool usb_disk_save_flash(FS_STRING fname)\n{\n}\n" }, { "path": "firmware/mock_hardware/modules/teletype/adapter_teletype.c", "content": "#include \"mock_hardware_api.h\"\n#include \"mock_hardware_api_private.h\"\n#include \"flashc.h\"\n\n#include \"module/edit_mode.h\"\n#include \"module/flash.h\"\n#include \"module/gitversion.h\"\n#include \"module/globals.h\"\n#include \"module/live_mode.h\"\n#include \"module/preset_w_mode.h\"\n#include \"src/scene_serialization.h\"\n#include \"src/teletype_io.h\"\n#include \"types.h\"\n\nextern nvram_data_t f;\nextern scene_state_t scene_state;\n\n#ifdef DECLARE_NVRAM\nDECLARE_NVRAM(&f, sizeof(nvram_data_t))\n#endif\n#ifdef DECLARE_VRAM\nDECLARE_VRAM(&scene_state, sizeof(scene_state))\n#endif\n\nvoid clock_null(uint8_t phase) { }\ntypedef void (*clock_pulse_t)(uint8_t phase);\nvolatile uint8_t clock_external;\nvolatile clock_pulse_t clock_pulse = &clock_null;\n\nvoid tele_usb_disk() { }\n\nextern u8 get_revision(void)\n{\n return 0;\n}\n\nvoid hardware_serializePreset(tt_serializer_t* stream, uint8_t preset_num)\n{\n if (preset_num == 255) {\n // save from active scene state and text\n serialize_scene(stream, &scene_state, &scene_text);\n }\n else\n {\n // save from flash\n scene_state_t scene;\n ss_init(&scene);\n\n char text[SCENE_TEXT_LINES][SCENE_TEXT_CHARS];\n memset(text, 0, SCENE_TEXT_LINES * SCENE_TEXT_CHARS);\n \n flash_read(preset_num, &scene, &text, 1, 1, 1);\n serialize_scene(stream, &scene, &text);\n }\n}\n\n\n// copied and modified from module/flash.c\nvoid fake_flash_read(scene_state_t* src_scene, scene_state_t* dest_scene,\n char (*src_text)[SCENE_TEXT_LINES][SCENE_TEXT_CHARS], char (*dest_text)[SCENE_TEXT_LINES][SCENE_TEXT_CHARS],\n uint8_t init_pattern, uint8_t init_grid,\n uint8_t init_i2c_op_address)\n{\n memcpy(ss_scripts_ptr(dest_scene), ss_scripts_ptr(src_scene),\n\n// handle difference in macros between TT 5 and 4\n#ifdef EDITABLE_SCRIPT_COUNT\n ss_scripts_size(EDITABLE_SCRIPT_COUNT)\n#else\n // Exclude size of TEMP script as above\n ss_scripts_size() - sizeof(scene_script_t)\n#endif\n\n );\n\n if (init_pattern)\n {\n memcpy(ss_patterns_ptr(dest_scene), ss_patterns_ptr(src_scene),\n ss_patterns_size());\n }\n if (init_grid)\n {\n memcpy(&dest_scene->grid, &src_scene->grid, sizeof(scene_grid_t));\n }\n memcpy(dest_text, src_text, SCENE_TEXT_LINES * SCENE_TEXT_CHARS);\n // need to reset timestamps\n uint32_t ticks = tele_get_ticks();\n\n// handle difference in macros between TT 5 and 4\n#ifdef TOTAL_SCRIPT_COUNT\n for (size_t i = 0; i < TOTAL_SCRIPT_COUNT; i++)\n#else\n for (size_t i = 0; i < TEMP_SCRIPT; i++)\n#endif\n dest_scene->scripts[i].last_time = ticks;\n dest_scene->variables.time = 0;\n\n if (init_i2c_op_address)\n dest_scene->i2c_op_address = -1;\n ss_midi_init(dest_scene);\n}\n\n// copied and modified from module/flash.c\nvoid fake_do_preset_read(scene_state_t* src_scene, scene_state_t* dest_scene,\n char (*src_text)[SCENE_TEXT_LINES][SCENE_TEXT_CHARS], char (*dest_text)[SCENE_TEXT_LINES][SCENE_TEXT_CHARS],\n uint8_t init_pattern, uint8_t init_grid,\n uint8_t init_i2c_op_address, uint8_t run_init)\n{\n ss_grid_init(dest_scene);\n fake_flash_read(src_scene, dest_scene, src_text, dest_text, init_pattern, init_grid, init_i2c_op_address);\n\n set_dash_updated();\n if (run_init) {\n scene_state.initializing = true;\n run_script(&scene_state, INIT_SCRIPT);\n scene_state.initializing = false;\n }\n}\n\nvoid hardware_deserializePreset(tt_deserializer_t* stream, uint8_t preset_num, bool clearExisting)\n{\n if (preset_num == 255)\n {\n scene_state_t scene;\n ss_init(&scene);\n\n char text[SCENE_TEXT_LINES][SCENE_TEXT_CHARS];\n memset(text, 0, SCENE_TEXT_LINES * SCENE_TEXT_CHARS);\n\n if (!clearExisting) {\n memcpy(&scene, &scene_state, sizeof(scene_state_t));\n memcpy(text, scene_text, SCENE_TEXT_LINES * SCENE_TEXT_CHARS);\n }\n deserialize_scene(stream, &scene, &text);\n\n // load into active scene state and text\n fake_do_preset_read(&scene, &scene_state, &text, &scene_text, 1, 1, 1, clearExisting ? 1 : 0);\n\n // refresh some obvious things that might have been affected by the load\n set_preset_w_mode();\n set_edit_mode_script(get_edit_script());\n tele_pattern_updated();\n scene_state.grid.grid_dirty = 1;\n }\n else\n {\n // load into flash\n scene_state_t scene;\n ss_init(&scene);\n\n char text[SCENE_TEXT_LINES][SCENE_TEXT_CHARS];\n memset(text, 0, SCENE_TEXT_LINES * SCENE_TEXT_CHARS);\n\n deserialize_scene(stream, &scene, &text);\n flash_write(preset_num, &scene, &text);\n }\n}\n\nvoid calibrate_adc()\n{\n // set PARAM and IN calibration to cover 0-16383\n ss_set_in_min(&scene_state, 0);\n ss_set_in_max(&scene_state, 16380);\n ss_set_param_min(&scene_state, 0);\n ss_set_param_max(&scene_state, 16380);\n}\n\nvoid hardware_beforeReadVRAM(void* ptr, uint32_t size)\n{\n\n}\n\nvoid hardware_afterWriteVRAM(void* ptr, uint32_t size)\n{\n tele_metro_updated();\n tele_vars_updated();\n set_preset_w_mode();\n set_edit_mode_script(get_edit_script());\n tele_pattern_updated();\n scene_state.grid.grid_dirty = 1;\n\n calibrate_adc();\n}\n\nvoid hardware_afterInit()\n{\n calibrate_adc();\n}\n\nint ss_defeat_counter = 0;\nextern void process_keypress(uint8_t key, uint8_t mod_key, bool is_held_key, bool is_release);\n\nvoid hardware_afterStep()\n{\n if (++ss_defeat_counter > 48000)\n {\n // send a fake keypress to reset screensaver timer\n process_keypress(0xFF, 0, false, true);\n ss_defeat_counter = 0;\n }\n}\n\nvoid hardware_getVersion(char* buffer)\n{\n strcpy(buffer, git_version);\n}\n\ndouble hardware_getClockPeriod()\n{\n return 0.001;\n}\n" }, { "path": "firmware/mock_hardware/modules/teletype/usb_disk_mode.c", "content": "#include \n\nvoid handler_usb_PollADC(int32_t data) {\n}\n\nvoid handler_usb_Front(int32_t data) {\n}\n\nvoid handler_usb_ScreenRefresh(int32_t data) {\n}" }, { "path": "firmware/mock_hardware/modules/trilogy/adapter_trilogy.c", "content": "#include \"mock_hardware_api.h\"\n#include \"mock_hardware_api_private.h\"\n\n#include \"types.h\"\n\n#include \n\nvoid clock_null(uint8_t phase) { }\ntypedef void (*clock_pulse_t)(uint8_t phase);\nvolatile uint8_t clock_external;\nvolatile clock_pulse_t clock_pulse = &clock_null;\n\nvoid hid_parse_frame(u8* data, u8 sz)\n{\n}\n\nvoid process_keypress(uint8_t key, uint8_t mod_key, bool is_held_key)\n{\n}\n\nvoid hardware_serializePreset(tt_serializer_t* stream, uint8_t preset_num)\n{\n}\n\nvoid hardware_deserializePreset(tt_deserializer_t* stream, uint8_t preset_num, bool clearExisting)\n{\n}\n\nvoid hardware_beforeReadVRAM(void* ptr, uint32_t size)\n{\n}\n\nvoid hardware_afterWriteVRAM(void* ptr, uint32_t size)\n{\n}\n\nvoid hardware_afterInit()\n{\n}\n\nvoid hardware_afterStep()\n{\n}\n\n#ifndef GIT_VERSION\n#define GIT_VERSION \"?\"\n#endif\n\nvoid hardware_getVersion(char* buffer)\n{\n strcpy(buffer, GIT_VERSION);\n}\n\ndouble hardware_getClockPeriod()\n{\n return 0.001;\n}\n" }, { "path": "firmware/teletype.mk", "content": "FLAGS += \\\n\t-D__AVR32_UC3B0512__ \\\n\t-Imock_hardware \\\n\t-Imock_hardware/include \\\n\t-I$(TARGET_NAME)/libavr32/src \\\n\t-I$(TARGET_NAME)/libavr32/src/usb/midi \\\n\t-I$(TARGET_NAME)/libavr32/src/usb/hid \\\n\t-I$(TARGET_NAME)/libavr32/src/usb/cdc \\\n\t-I$(TARGET_NAME)/libavr32/src/usb/ftdi \\\n\t-I$(TARGET_NAME)/libavr32/conf \\\n\t-I$(TARGET_NAME)/libavr32/conf/teletype \\\n\t-I$(TARGET_NAME)/libavr32/asf/common/services/usb \\\n\t-I$(TARGET_NAME)/libavr32/asf/common/services/usb/uhc \\\n\t-I$(TARGET_NAME)/libavr32/asf/common/services/usb/class/hid \\\n\t-I$(TARGET_NAME)/src \\\n\t-I$(TARGET_NAME)/src/ops \\\n\t-I$(TARGET_NAME)/ \\\n\nSOURCES = \\\n\t$(wildcard $(TARGET_NAME)/src/*.c) \\\n\t$(TARGET_NAME)/src/scanner.c \\\n\t$(TARGET_NAME)/src/match_token.c \\\n\t$(TARGET_NAME)/module/gitversion.c \\\n\t$(wildcard $(TARGET_NAME)/src/ops/*.c) \\\n\t$(wildcard $(TARGET_NAME)/module/*.c) \\\n\t$(TARGET_NAME)/libavr32/src/events.c \\\n\t$(TARGET_NAME)/libavr32/src/timers.c \\\n\t$(TARGET_NAME)/libavr32/src/util.c \\\n\t$(TARGET_NAME)/libavr32/src/font.c \\\n\t$(TARGET_NAME)/libavr32/src/kbd.c \\\n\t$(TARGET_NAME)/libavr32/src/region.c \\\n\t$(TARGET_NAME)/libavr32/src/random.c \\\n\t$(TARGET_NAME)/libavr32/src/usb/hid/hid.c \\\n\t$(TARGET_NAME)/libavr32/src/music.c \\\n\t$(TARGET_NAME)/libavr32/src/midi_common.c \\\n\t$(wildcard $(TARGET_NAME)/libavr32/src/euclidean/*.c) \\\n\t$(wildcard mock_hardware/*.c) \\\n\t$(wildcard mock_hardware/common/*.c) \\\n\t$(wildcard mock_hardware/modules/teletype/*.c) \\\n\nSOURCES := $(filter-out $(TARGET_NAME)/module/usb_disk_mode.c, $(SOURCES))\n\nRAGEL ?= ragel\n\n# Add a rule to build match_token.c from match_token.rl\n$(TARGET_NAME)/src/match_token.c: $(TARGET_NAME)/src/match_token.rl\n\t$(RAGEL) -C -G2 $(TARGET_NAME)/src/match_token.rl -o $(TARGET_NAME)/src/match_token.c\n\n# Add a rule to build scanner.c from scanner.rl\n$(TARGET_NAME)/src/scanner.c: $(TARGET_NAME)/src/scanner.rl\n\t$(RAGEL) -C -G2 $(TARGET_NAME)/src/scanner.rl -o $(TARGET_NAME)/src/scanner.c\n\n# Add the git commit id to a file for use when printing out the version\n$(TARGET_NAME)/module/gitversion.c: $(TARGET_NAME)\n\techo \"const char *git_version = \\\"$(GIT_VERSION)\\\";\" > $@\n\ninclude common.mk\n" }, { "path": "firmware/whitewhale.mk", "content": "FLAGS += \\\n\t-D__AVR32_UC3B0256__ \\\n\t-Imock_hardware \\\n\t-Imock_hardware/include \\\n\t-I$(TARGET_NAME)/libavr32/src \\\n\t-I$(TARGET_NAME)/libavr32/src/usb/midi \\\n\t-I$(TARGET_NAME)/libavr32/src/usb/hid \\\n\t-I$(TARGET_NAME)/libavr32/src/usb/cdc \\\n\t-I$(TARGET_NAME)/libavr32/asf/common/services/usb \\\n\t-I$(TARGET_NAME)/libavr32/asf/common/services/usb/uhc \\\n\t-I$(TARGET_NAME)/libavr32/conf \\\n\t-I$(TARGET_NAME)/libavr32/conf/trilogy \\\n\t\nSOURCES = \\\n\t$(TARGET_NAME)/src/main.c \\\n\t$(TARGET_NAME)/libavr32/src/events.c \\\n\t$(TARGET_NAME)/libavr32/src/timers.c \\\n\t$(TARGET_NAME)/libavr32/src/util.c \\\n\t$(wildcard mock_hardware/*.c) \\\n\t$(wildcard mock_hardware/common/*.c) \\\n\t$(wildcard mock_hardware/modules/trilogy/*.c) \\\n\nFLAGS += -DGIT_VERSION=\"\\\"$(GIT_VERSION)\\\"\"\n\ninclude common.mk\n" }, { "path": "lib/base64/LICENSE", "content": "Copyright © 2004-2017 by René Nyffenegger\n\nThis source code is provided 'as-is', without any express or implied\nwarranty. In no event will the author be held liable for any damages\narising from the use of this software.\n \nPermission is granted to anyone to use this software for any purpose,\nincluding commercial applications, and to alter it and redistribute it\nfreely, subject to the following restrictions:\n \n1. The origin of this source code must not be misrepresented; you must not\n claim that you wrote the original source code. If you use this source code\n in a product, an acknowledgment in the product documentation would be\n appreciated but is not required.\n \n2. Altered source versions must be plainly marked as such, and must not be\n misrepresented as being the original source code.\n \n3. This notice may not be removed or altered from any source distribution." }, { "path": "lib/base64/README.md", "content": "cpp-base64 by René Nyffenegger\n\nhttps://github.com/ReneNyffenegger/cpp-base64" }, { "path": "lib/base64/base64.cpp", "content": "/* \n base64.cpp and base64.h\n\n base64 encoding and decoding with C++.\n\n Version: 1.01.00\n\n Copyright (C) 2004-2017 René Nyffenegger\n\n This source code is provided 'as-is', without any express or implied\n warranty. In no event will the author be held liable for any damages\n arising from the use of this software.\n\n Permission is granted to anyone to use this software for any purpose,\n including commercial applications, and to alter it and redistribute it\n freely, subject to the following restrictions:\n\n 1. The origin of this source code must not be misrepresented; you must not\n claim that you wrote the original source code. If you use this source code\n in a product, an acknowledgment in the product documentation would be\n appreciated but is not required.\n\n 2. Altered source versions must be plainly marked as such, and must not be\n misrepresented as being the original source code.\n\n 3. This notice may not be removed or altered from any source distribution.\n\n René Nyffenegger rene.nyffenegger@adp-gmbh.ch\n\n*/\n\n#include \"base64.h\"\n#include \n\nstatic const std::string base64_chars = \n \"ABCDEFGHIJKLMNOPQRSTUVWXYZ\"\n \"abcdefghijklmnopqrstuvwxyz\"\n \"0123456789+/\";\n\n\nstatic inline bool is_base64(unsigned char c) {\n return (isalnum(c) || (c == '+') || (c == '/'));\n}\n\nstd::string base64_encode(unsigned char const* bytes_to_encode, unsigned int in_len) {\n std::string ret;\n int i = 0;\n int j = 0;\n unsigned char char_array_3[3];\n unsigned char char_array_4[4];\n\n while (in_len--) {\n char_array_3[i++] = *(bytes_to_encode++);\n if (i == 3) {\n char_array_4[0] = (char_array_3[0] & 0xfc) >> 2;\n char_array_4[1] = ((char_array_3[0] & 0x03) << 4) + ((char_array_3[1] & 0xf0) >> 4);\n char_array_4[2] = ((char_array_3[1] & 0x0f) << 2) + ((char_array_3[2] & 0xc0) >> 6);\n char_array_4[3] = char_array_3[2] & 0x3f;\n\n for(i = 0; (i <4) ; i++)\n ret += base64_chars[char_array_4[i]];\n i = 0;\n }\n }\n\n if (i)\n {\n for(j = i; j < 3; j++)\n char_array_3[j] = '\\0';\n\n char_array_4[0] = ( char_array_3[0] & 0xfc) >> 2;\n char_array_4[1] = ((char_array_3[0] & 0x03) << 4) + ((char_array_3[1] & 0xf0) >> 4);\n char_array_4[2] = ((char_array_3[1] & 0x0f) << 2) + ((char_array_3[2] & 0xc0) >> 6);\n\n for (j = 0; (j < i + 1); j++)\n ret += base64_chars[char_array_4[j]];\n\n while((i++ < 3))\n ret += '=';\n\n }\n\n return ret;\n\n}\n\nstd::string base64_decode(std::string const& encoded_string) {\n int in_len = encoded_string.size();\n int i = 0;\n int j = 0;\n int in_ = 0;\n unsigned char char_array_4[4], char_array_3[3];\n std::string ret;\n\n while (in_len-- && ( encoded_string[in_] != '=') && is_base64(encoded_string[in_])) {\n char_array_4[i++] = encoded_string[in_]; in_++;\n if (i ==4) {\n for (i = 0; i <4; i++)\n char_array_4[i] = base64_chars.find(char_array_4[i]);\n\n char_array_3[0] = ( char_array_4[0] << 2 ) + ((char_array_4[1] & 0x30) >> 4);\n char_array_3[1] = ((char_array_4[1] & 0xf) << 4) + ((char_array_4[2] & 0x3c) >> 2);\n char_array_3[2] = ((char_array_4[2] & 0x3) << 6) + char_array_4[3];\n\n for (i = 0; (i < 3); i++)\n ret += char_array_3[i];\n i = 0;\n }\n }\n\n if (i) {\n for (j = 0; j < i; j++)\n char_array_4[j] = base64_chars.find(char_array_4[j]);\n\n char_array_3[0] = (char_array_4[0] << 2) + ((char_array_4[1] & 0x30) >> 4);\n char_array_3[1] = ((char_array_4[1] & 0xf) << 4) + ((char_array_4[2] & 0x3c) >> 2);\n\n for (j = 0; (j < i - 1); j++) ret += char_array_3[j];\n }\n\n return ret;\n}\n" }, { "path": "lib/base64/base64.h", "content": "//\n// base64 encoding and decoding with C++.\n// Version: 1.01.00\n//\n\n#ifndef BASE64_H_C0CE2A47_D10E_42C9_A27C_C883944E704A\n#define BASE64_H_C0CE2A47_D10E_42C9_A27C_C883944E704A\n\n#include \n\nstd::string base64_encode(unsigned char const* , unsigned int len);\nstd::string base64_decode(std::string const& s);\n\n#endif /* BASE64_H_C0CE2A47_D10E_42C9_A27C_C883944E704A */\n" }, { "path": "lib/cbbq/LICENSE.md", "content": "License: MIT\n\nCopyright © 2021 Michael Dewberry\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the “Software”), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is \nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, \nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n" }, { "path": "lib/cbbq/README.md", "content": "cbbq\n====\n\nHeader-only C library implementing a lock-free, thread-safe, \nsingle-producer/single-consumer circular message queue for \nshort variable-length byte-sequence messages.\n\nSee [the library](cbbq.h) for documentation.\n\nLicense: [MIT](LICENSE.md)" }, { "path": "lib/cbbq/cbbq.h", "content": "/*\n\ncbbq.h\n\nC implementation of a lock-free, thread-safe, single-producer/single-consumer \ncircular message queue for short variable-length byte-sequence messages\n\nby Michael Dewberry \nhttp://dewb.org\nhttps://github.com/dewb\n\nbased directly on the \"bbqueue\" design by Andrea Lattuada and James Munns\nhttps://ferrous-systems.com/blog/lock-free-ring-buffer/\nhttps://github.com/jamesmunns/bbqueue\n\n me: \"C is terrible and nobody should write it, we should use languages with memory safety\"\n also me: \n\nRequirements/notes\n\n* [TODO] C11 and support for recommended\n * if your MCU is too simple to reorder instructions, you might be okay without it (???)\n* Only one thread reads, only one thread writes\n* Individual message length 255 bytes or less\n* Queue size up to 2^32-1 bytes\n* [TODO] support multi-producer/single-consumer with an optional lock function on write? \n\n\nLicense: MIT\n\nCopyright © 2021 Michael Dewberry\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the “Software”), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is \nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, \nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n\n*/\n\n#ifdef CBBQ_DEBUG\n#include \n#define ASSERT(expr) assert(expr);\n\n#define CHECK_INVARIANTS(q) \\\n ASSERT(q->read <= q->watermark); \\\n ASSERT(q->write <= q->watermark); \\\n ASSERT(q->read <= q->size); \\\n ASSERT(q->write <= q->size); \\\n ASSERT(q->watermark <= q->size); \n#else\n#define ASSERT(expr)\n#define CHECK_INVARIANTS(expr)\n#endif\n\n#include \n#include \n#include \n#include \n\ntypedef struct\n{\n uint8_t* buf;\n uint32_t size;\n uint32_t read;\n uint32_t write;\n uint32_t watermark;\n} cbbq;\n\nvoid queue_init(cbbq* q, uint32_t size) \n{\n if (!q) \n {\n return;\n }\n\n q->buf = (uint8_t*)malloc(size);\n q->size = size;\n q->read = 0;\n q->write = 0;\n q->watermark = 0;\n}\n\nvoid queue_free(cbbq* q)\n{\n if (q)\n {\n free(q->buf);\n }\n}\n\ntypedef enum\n{\n Success = 1,\n NoMessagesAvailable = 0,\n MessageTooLarge = -1,\n QueueFull = -2,\n} QueueResult;\n\n// Write a message into the queue.\n// queue_write should only be called by the producer thread.\nQueueResult\nqueue_write(cbbq* q, uint8_t* msg_bytes, uint8_t msg_length)\n{\n CHECK_INVARIANTS(q)\n\n // total amount to write is the length byte plus the message contents\n uint32_t write_length = 1 + msg_length;\n if (write_length > q->size)\n {\n return MessageTooLarge;\n }\n\n // can we fit this message in the remaining area?\n if (q->size - q->write >= write_length)\n {\n if (q->read > q->write && q->read <= q->write + write_length)\n {\n // can't overtake read pointer\n return QueueFull; \n }\n\n // record the message length into the buffer\n *(q->buf + q->write) = msg_length;\n // copy the message bytes into the buffer\n memcpy(q->buf + q->write + 1, msg_bytes, msg_length);\n\n // move the write pointer ahead\n q->write = q->write + write_length;\n\n // if we're in the non-flipped case, update watermark\n if (q->read < q->write) {\n q->watermark = q->write;\n }\n }\n else // we have to wrap around\n {\n if (q->read <= write_length) {\n // can't overtake read pointer\n return QueueFull; \n }\n\n // set the high water mark at the previous write pointer\n q->watermark = q->write;\n\n // write pointer is now implicitly 0\n // record the message length into the buffer\n *(q->buf) = msg_length;\n // copy the message bytes into the buffer\n memcpy(q->buf + 1, msg_bytes, msg_length);\n\n // update the write pointer\n q->write = write_length;\n }\n\n return Success;\n}\n\n// Read a message from the queue.\n// The contents of the pointer written to read_bytes is only valid until the next\n// call to queue_read.\n// queue_read should only be called by the consumer thread.\nQueueResult\nqueue_read(cbbq* q, uint8_t** read_bytes, uint8_t* read_length)\n{\n CHECK_INVARIANTS(q)\n\n // are there messages left to read?\n if (q->read == q->write)\n {\n if (read_bytes)\n {\n *read_bytes = NULL;\n }\n if (read_length)\n {\n *read_length = 0;\n }\n return NoMessagesAvailable;\n }\n\n // if we are flipped and the read pointer reaches the watermark, next read starts at 0\n if (q->read > q->write && q->read >= q->watermark)\n {\n q->read = 0;\n }\n\n // get the message length from the buffer\n uint8_t msg_length = *(q->buf + q->read);\n\n // give the consumer a pointer to the message\n if (read_bytes) \n {\n *read_bytes = q->buf + q->read + 1;\n }\n\n // give the consumer the message length\n if (read_length)\n {\n *read_length = msg_length;\n }\n\n // move the read pointer to the next message\n q->read = (q->read + msg_length + 1);\n\n return Success;\n}" }, { "path": "lib/cbbq/test/.gitignore", "content": "bin\na.out\n" }, { "path": "lib/cbbq/test/cbbq_test.c", "content": "#define CBBQ_DEBUG\n\n#include \"cbbq.h\"\n#include \"cbbq_utils.h\"\n#include \n#include \n\n#define ASSERT(expr) assert(expr);\n#define QASSERT(expr) \\\n { \\\n bool tb = expr; \\\n printf(\"[%d] size: %d, read: %d, write: %d, watermark: %d, flipped: %s\\n\", \\\n __LINE__, q.size, q.read, q.write, q.watermark, q.read > q.write ? \"true\" : \"false\"); \\\n queue_display(&q); \\\n if (!tb) \\\n printf(\"FAIL: %s\\n\", #expr); \\\n assert(tb); \\\n }\n\n\nint main(void)\n{\n printf(\"\\nTesting...\\n\\n\");\n\n cbbq q;\n queue_init(&q, 21);\n QASSERT(q.size == 21);\n\n uint8_t* rbuf;\n uint8_t rlen;\n\n // start with no messages\n QASSERT(NoMessagesAvailable == queue_read(&q, &rbuf, &rlen));\n\n // quick write and immediate read\n QASSERT(queue_write(&q, (uint8_t[]) { 0xAA }, 1));\n QASSERT(queue_read(&q, &rbuf, &rlen));\n ASSERT(rlen == 1);\n ASSERT(rbuf[0] == 0xAA);\n ASSERT(q.write == 2);\n ASSERT(q.read == 2);\n QASSERT(NoMessagesAvailable == queue_read(&q, &rbuf, &rlen));\n\n // fill the buffer with messages\n QASSERT(queue_write(&q, (uint8_t[]) { 0x01, 0x02, 0x03 }, 3));\n QASSERT(queue_write(&q, (uint8_t[]) { 0x04, 0x05, 0x06, 0x07, 0x08 }, 5));\n QASSERT(queue_write(&q, (uint8_t[]) { 0xFF, 0xFF }, 2));\n QASSERT(queue_write(&q, (uint8_t[]) { 0xDE, 0xAD, 0xBE, 0xEF, 0xFF }, 5));\n\n // try to insert a message that won't fit\n QASSERT(QueueFull == queue_write(&q, (uint8_t[]) { 0xDD, 0xDD, 0xDD }, 3));\n\n // read the first message\n QASSERT(queue_read(&q, &rbuf, &rlen));\n ASSERT(rlen == 3);\n ASSERT(rbuf[0] == 0x01);\n ASSERT(rbuf[1] == 0x02);\n ASSERT(rbuf[2] == 0x03);\n\n // read the second message\n QASSERT(queue_read(&q, &rbuf, &rlen));\n ASSERT(rlen == 5);\n ASSERT(rbuf[0] == 0x04);\n ASSERT(rbuf[1] == 0x05);\n ASSERT(rbuf[2] == 0x06);\n ASSERT(rbuf[3] == 0x07);\n ASSERT(rbuf[4] == 0x08);\n\n // read the third message\n QASSERT(queue_read(&q, &rbuf, &rlen));\n ASSERT(rlen == 2);\n ASSERT(rbuf[0] == 0xFF);\n ASSERT(rbuf[1] == 0xFF);\n\n // write a new message that wraps\n QASSERT(queue_write(&q, (uint8_t[]) { 0xAA, 0xBB, 0xCC, 0xDD }, 4));\n ASSERT(q.write == 5);\n ASSERT(q.watermark == 21);\n\n // read the fourth message\n QASSERT(queue_read(&q, &rbuf, &rlen));\n ASSERT(rlen == 5);\n ASSERT(rbuf[0] == 0xDE);\n ASSERT(rbuf[1] == 0xAD);\n ASSERT(rbuf[2] == 0xBE);\n ASSERT(rbuf[3] == 0xEF);\n ASSERT(rbuf[4] == 0xFF);\n\n // read the fifth message\n QASSERT(queue_read(&q, &rbuf, &rlen));\n ASSERT(rlen == 4);\n ASSERT(rbuf[0] == 0xAA);\n ASSERT(rbuf[1] == 0xBB);\n ASSERT(rbuf[2] == 0xCC);\n ASSERT(rbuf[3] == 0xDD);\n\n // should be no more messages\n QASSERT(NoMessagesAvailable == queue_read(&q, &rbuf, &rlen));\n\n // write more messages\n QASSERT(queue_write(&q, (uint8_t[]) { 0x01, 0x02, 0x03 }, 3));\n QASSERT(queue_write(&q, (uint8_t[]) { 0x01, 0x02, 0x03 }, 3));\n QASSERT(queue_write(&q, (uint8_t[]) { 0x01, 0x02, 0x03 }, 3));\n\n // read the sixth message\n QASSERT(queue_read(&q, &rbuf, &rlen));\n ASSERT(rlen == 3);\n ASSERT(rbuf[0] == 0x01);\n ASSERT(rbuf[1] == 0x02);\n ASSERT(rbuf[2] == 0x03);\n\n // this should wrap\n QASSERT(queue_write(&q, (uint8_t[]) { 0xAA, 0xAA, 0xAA, 0xAA, 0xAA }, 5));\n ASSERT(q.write == 6);\n\n // this should barely fit in the remaining space before the read pointer\n QASSERT(queue_write(&q, (uint8_t[]) { 0x11 }, 1));\n \n // this should fail because writing it would overtake read\n QASSERT(QueueFull == queue_write(&q, (uint8_t[]) { 0x11 }, 1));\n\n // this should fail because it's larger than q.size\n QASSERT(MessageTooLarge == queue_write(&q, (uint8_t[]) { 0x11 }, 22));\n\n printf(\"Tests passed.\\n\\n\");\n return 0;\n}" }, { "path": "lib/cbbq/test/cbbq_utils.h", "content": "#pragma once\n\n#include \n\n// debugging utilities for cbbq\n\nvoid queue_display(cbbq* q)\n{\n for (int i = 0; i < q->size; i++)\n printf(\"%02X \", q->buf[i]);\n printf(\"\\n\");\n uint8_t i1, i2, i3;\n char c1, c2, c3;\n if (q->read <= q->write && q->read <= q->watermark)\n {\n i1 = q->read;\n c1 = 'r';\n if (q->write <= q->watermark)\n {\n i2 = q->write;\n c2 = 'w';\n i3 = q->watermark;\n c3 = 'm';\n }\n else\n {\n i3 = q->write;\n c3 = 'w';\n i2 = q->watermark;\n c2 = 'm';\n }\n }\n else if (q->write <= q->read && q->write <= q->watermark)\n {\n i1 = q->write;\n c1 = 'w';\n if (q->read <= q->watermark)\n {\n i2 = q->read;\n c2 = 'r';\n i3 = q->watermark;\n c3 = 'm';\n }\n else\n {\n i3 = q->read;\n c3 = 'r';\n i2 = q->watermark;\n c2 = 'm';\n }\n }\n else\n {\n i1 = q->watermark;\n c1 = 'm';\n if (q->read <= q->write)\n {\n i2 = q->read;\n c2 = 'r';\n i3 = q->write;\n c3 = 'w';\n }\n else\n {\n i3 = q->read;\n c3 = 'r';\n i2 = q->write;\n c2 = 'w';\n }\n }\n\n for (int x = 0; x < i1; x++)\n {\n printf(\" \");\n }\n printf(\"%c\", c1);\n\n if (i2 == i1)\n {\n printf(\"%c\", c2);\n }\n else\n {\n printf(\" \");\n for (int x = 0; x < i2 - i1 - 1; x++)\n {\n printf(\" \");\n }\n printf(\"%c\", c2);\n }\n\n if (i3 == i2)\n {\n printf(\"%c\\n\\n\", c3);\n }\n else\n {\n printf(i2 == i1 ? \" \" : \" \");\n for (int x = 0; x < i3 - i2 - 1; x++)\n {\n printf(\" \");\n }\n printf(\"%c\\n\\n\", c3);\n }\n}" }, { "path": "lib/cbbq/test/test.sh", "content": "mkdir -p bin\ncc cbbq_test.c -I.. -o bin/cbbq_test && bin/cbbq_test\n" }, { "path": "lib/oscpack/LICENSE", "content": "Oscpack is distributed under the MIT open source license:\n```\nCopyright © 2004-2013 Ross Bencina\nPermission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the “Software”), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:\nThe above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.\nTHE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\nThe text above constitutes the entire oscpack license; however, \tthe oscpack developer(s) also make the following non-binding requests: Any person wishing to distribute modifications to the Software is requested to send the modifications to the original developer so that\tthey can be incorporated into the canonical version. It is also \trequested that these non-binding requests be included whenever the\tabove license is reproduced.\n```\nAll feedback welcome. Please feel free to email comments to Ross at rossb@audiomulch.com" }, { "path": "lib/oscpack/README.md", "content": "oscpack 1.1.0 by Ross Bencina\n\nhttp://www.rossbencina.com/code/oscpack\n" }, { "path": "lib/oscpack/ip/IpEndpointName.cpp", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#include \"IpEndpointName.h\"\n\n#include \n\n#include \"NetworkingUtils.h\"\n\n\nunsigned long IpEndpointName::GetHostByName( const char *s )\n{\n\treturn ::GetHostByName(s);\n}\n\n\nvoid IpEndpointName::AddressAsString( char *s ) const\n{\n\tif( address == ANY_ADDRESS ){\n\t\tstd::sprintf( s, \"\" );\n\t}else{\n\t\tstd::sprintf( s, \"%d.%d.%d.%d\",\n\t\t\t\t(int)((address >> 24) & 0xFF),\n\t\t\t\t(int)((address >> 16) & 0xFF),\n\t\t\t\t(int)((address >> 8) & 0xFF),\n\t\t\t\t(int)(address & 0xFF) );\n\t}\n}\n\n\nvoid IpEndpointName::AddressAndPortAsString( char *s ) const\n{\n\tif( port == ANY_PORT ){\n\t\tif( address == ANY_ADDRESS ){\n\t\t\tstd::sprintf( s, \":\" );\n\t\t}else{\n\t\t\tstd::sprintf( s, \"%d.%d.%d.%d:\",\n\t\t\t\t(int)((address >> 24) & 0xFF),\n\t\t\t\t(int)((address >> 16) & 0xFF),\n\t\t\t\t(int)((address >> 8) & 0xFF),\n\t\t\t\t(int)(address & 0xFF) );\n\t\t}\n\t}else{\n\t\tif( address == ANY_ADDRESS ){\n\t\t\tstd::sprintf( s, \":%d\", port );\n\t\t}else{\n\t\t\tstd::sprintf( s, \"%d.%d.%d.%d:%d\",\n\t\t\t\t(int)((address >> 24) & 0xFF),\n\t\t\t\t(int)((address >> 16) & 0xFF),\n\t\t\t\t(int)((address >> 8) & 0xFF),\n\t\t\t\t(int)(address & 0xFF),\n\t\t\t\t(int)port );\n\t\t}\n\t}\t\n}\n" }, { "path": "lib/oscpack/ip/IpEndpointName.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_IPENDPOINTNAME_H\n#define INCLUDED_OSCPACK_IPENDPOINTNAME_H\n\n\nclass IpEndpointName{\n static unsigned long GetHostByName( const char *s );\npublic:\n static const unsigned long ANY_ADDRESS = 0xFFFFFFFF;\n static const int ANY_PORT = -1;\n\n IpEndpointName()\n\t\t: address( ANY_ADDRESS ), port( ANY_PORT ) {}\n IpEndpointName( int port_ ) \n\t\t: address( ANY_ADDRESS ), port( port_ ) {}\n IpEndpointName( unsigned long ipAddress_, int port_ ) \n\t\t: address( ipAddress_ ), port( port_ ) {}\n IpEndpointName( const char *addressName, int port_=ANY_PORT )\n\t\t: address( GetHostByName( addressName ) )\n\t\t, port( port_ ) {}\n IpEndpointName( int addressA, int addressB, int addressC, int addressD, int port_=ANY_PORT )\n\t\t: address( ( (addressA << 24) | (addressB << 16) | (addressC << 8) | addressD ) )\n\t\t, port( port_ ) {}\n\n\t// address and port are maintained in host byte order here\n unsigned long address;\n int port;\n\n bool IsMulticastAddress() const { return ((address >> 24) & 0xFF) >= 224 && ((address >> 24) & 0xFF) <= 239; }\n\n\tenum { ADDRESS_STRING_LENGTH=17 };\n\tvoid AddressAsString( char *s ) const;\n\n\tenum { ADDRESS_AND_PORT_STRING_LENGTH=23};\n\tvoid AddressAndPortAsString( char *s ) const;\n};\n\ninline bool operator==( const IpEndpointName& lhs, const IpEndpointName& rhs )\n{\t\n\treturn (lhs.address == rhs.address && lhs.port == rhs.port );\n}\n\ninline bool operator!=( const IpEndpointName& lhs, const IpEndpointName& rhs )\n{\n\treturn !(lhs == rhs);\n}\n\n#endif /* INCLUDED_OSCPACK_IPENDPOINTNAME_H */\n" }, { "path": "lib/oscpack/ip/NetworkingUtils.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_NETWORKINGUTILS_H\n#define INCLUDED_OSCPACK_NETWORKINGUTILS_H\n\n\n// in general NetworkInitializer is only used internally, but if you're \n// application creates multiple sockets from different threads at runtime you\n// should instantiate one of these in main just to make sure the networking\n// layer is initialized.\nclass NetworkInitializer{\npublic:\n NetworkInitializer();\n ~NetworkInitializer();\n};\n\n\n// return ip address of host name in host byte order\nunsigned long GetHostByName( const char *name );\n\n\n#endif /* INCLUDED_OSCPACK_NETWORKINGUTILS_H */\n" }, { "path": "lib/oscpack/ip/PacketListener.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_PACKETLISTENER_H\n#define INCLUDED_OSCPACK_PACKETLISTENER_H\n\n\nclass IpEndpointName;\n\nclass PacketListener{\npublic:\n virtual ~PacketListener() {}\n virtual void ProcessPacket( const char *data, int size, \n\t\t\tconst IpEndpointName& remoteEndpoint ) = 0;\n};\n\n#endif /* INCLUDED_OSCPACK_PACKETLISTENER_H */\n" }, { "path": "lib/oscpack/ip/TimerListener.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_TIMERLISTENER_H\n#define INCLUDED_OSCPACK_TIMERLISTENER_H\n\n\nclass TimerListener{\npublic:\n virtual ~TimerListener() {}\n virtual void TimerExpired() = 0;\n};\n\n#endif /* INCLUDED_OSCPACK_TIMERLISTENER_H */\n" }, { "path": "lib/oscpack/ip/UdpSocket.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_UDPSOCKET_H\n#define INCLUDED_OSCPACK_UDPSOCKET_H\n\n#include // size_t\n\n#include \"NetworkingUtils.h\"\n#include \"IpEndpointName.h\"\n\n\nclass PacketListener;\nclass TimerListener;\n\nclass UdpSocket;\n\nclass SocketReceiveMultiplexer{\n class Implementation;\n Implementation *impl_;\n\n\tfriend class UdpSocket;\n\npublic:\n SocketReceiveMultiplexer();\n ~SocketReceiveMultiplexer();\n\n\t// only call the attach/detach methods _before_ calling Run\n\n // only one listener per socket, each socket at most once\n void AttachSocketListener( UdpSocket *socket, PacketListener *listener );\n void DetachSocketListener( UdpSocket *socket, PacketListener *listener );\n\n void AttachPeriodicTimerListener( int periodMilliseconds, TimerListener *listener );\n\tvoid AttachPeriodicTimerListener(\n int initialDelayMilliseconds, int periodMilliseconds, TimerListener *listener );\n void DetachPeriodicTimerListener( TimerListener *listener ); \n\n void Run(); // loop and block processing messages indefinitely\n\tvoid RunUntilSigInt();\n void Break(); // call this from a listener to exit once the listener returns\n void AsynchronousBreak(); // call this from another thread or signal handler to exit the Run() state\n};\n\n\nclass UdpSocket{\n class Implementation;\n Implementation *impl_;\n \n\tfriend class SocketReceiveMultiplexer::Implementation;\n \npublic:\n\n\t// Ctor throws std::runtime_error if there's a problem\n\t// initializing the socket.\n\tUdpSocket();\n\tvirtual ~UdpSocket();\n\n\t// Enable broadcast addresses (e.g. x.x.x.255)\n\t// Sets SO_BROADCAST socket option.\n\tvoid SetEnableBroadcast( bool enableBroadcast );\n\n\t// Enable multiple listeners for a single port on same \n\t// network interface*\n\t// Sets SO_REUSEADDR (also SO_REUSEPORT on OS X).\n\t// [*] The exact behavior of SO_REUSEADDR and \n\t// SO_REUSEPORT is undefined for some common cases \n\t// and may have drastically different behavior on different\n\t// operating systems.\n\tvoid SetAllowReuse( bool allowReuse );\n\n\n\t// The socket is created in an unbound, unconnected state\n\t// such a socket can only be used to send to an arbitrary\n\t// address using SendTo(). To use Send() you need to first\n\t// connect to a remote endpoint using Connect(). To use\n\t// ReceiveFrom you need to first bind to a local endpoint\n\t// using Bind().\n\n\t// Retrieve the local endpoint name when sending to 'to'\n\tIpEndpointName LocalEndpointFor( const IpEndpointName& remoteEndpoint ) const;\n\n\t// Connect to a remote endpoint which is used as the target\n\t// for calls to Send()\n\tvoid Connect( const IpEndpointName& remoteEndpoint );\t\n\tvoid Send( const char *data, std::size_t size );\n void SendTo( const IpEndpointName& remoteEndpoint, const char *data, std::size_t size );\n\n\n\t// Bind a local endpoint to receive incoming data. Endpoint\n\t// can be 'any' for the system to choose an endpoint\n\tvoid Bind( const IpEndpointName& localEndpoint );\n\tbool IsBound() const;\n\n std::size_t ReceiveFrom( IpEndpointName& remoteEndpoint, char *data, std::size_t size );\n};\n\n\n// convenience classes for transmitting and receiving\n// they just call Connect and/or Bind in the ctor.\n// note that you can still use a receive socket\n// for transmitting etc\n\nclass UdpTransmitSocket : public UdpSocket{\npublic:\n\tUdpTransmitSocket( const IpEndpointName& remoteEndpoint )\n\t\t{ Connect( remoteEndpoint ); }\n};\n\n\nclass UdpReceiveSocket : public UdpSocket{\npublic:\n\tUdpReceiveSocket( const IpEndpointName& localEndpoint )\n\t\t{ Bind( localEndpoint ); }\n};\n\n\n// UdpListeningReceiveSocket provides a simple way to bind one listener\n// to a single socket without having to manually set up a SocketReceiveMultiplexer\n\nclass UdpListeningReceiveSocket : public UdpSocket{\n SocketReceiveMultiplexer mux_;\n PacketListener *listener_;\npublic:\n\tUdpListeningReceiveSocket( const IpEndpointName& localEndpoint, PacketListener *listener )\n : listener_( listener )\n {\n Bind( localEndpoint );\n mux_.AttachSocketListener( this, listener_ );\n }\n\n ~UdpListeningReceiveSocket()\n { mux_.DetachSocketListener( this, listener_ ); }\n\n // see SocketReceiveMultiplexer above for the behaviour of these methods...\n void Run() { mux_.Run(); }\n\tvoid RunUntilSigInt() { mux_.RunUntilSigInt(); }\n void Break() { mux_.Break(); }\n void AsynchronousBreak() { mux_.AsynchronousBreak(); }\n};\n\n\n#endif /* INCLUDED_OSCPACK_UDPSOCKET_H */\n" }, { "path": "lib/oscpack/ip/posix/NetworkingUtils.cpp", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n\thttp://www.rossbencina.com/code/oscpack\n\n\tCopyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#include \"ip/NetworkingUtils.h\"\n\n#include \n#include \n#include \n\n#include \n\n\n\nNetworkInitializer::NetworkInitializer() {}\n\nNetworkInitializer::~NetworkInitializer() {}\n\n\nunsigned long GetHostByName( const char *name )\n{\n unsigned long result = 0;\n\n struct hostent *h = gethostbyname( name );\n if( h ){\n struct in_addr a;\n std::memcpy( &a, h->h_addr_list[0], h->h_length );\n result = ntohl(a.s_addr);\n }\n\n return result;\n}\n" }, { "path": "lib/oscpack/ip/posix/UdpSocket.cpp", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n\thttp://www.rossbencina.com/code/oscpack\n\n\tCopyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#include \"ip/UdpSocket.h\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include // for sockaddr_in\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include // for memset\n#include \n#include \n\n#include \"ip/PacketListener.h\"\n#include \"ip/TimerListener.h\"\n\n\n#if defined(__APPLE__) && !defined(_SOCKLEN_T)\n// pre system 10.3 didn't have socklen_t\ntypedef ssize_t socklen_t;\n#endif\n\n\nstatic void SockaddrFromIpEndpointName( struct sockaddr_in& sockAddr, const IpEndpointName& endpoint )\n{\n std::memset( (char *)&sockAddr, 0, sizeof(sockAddr ) );\n sockAddr.sin_family = AF_INET;\n\n\tsockAddr.sin_addr.s_addr = \n\t\t(endpoint.address == IpEndpointName::ANY_ADDRESS)\n\t\t? INADDR_ANY\n\t\t: htonl( endpoint.address );\n\n\tsockAddr.sin_port =\n\t\t(endpoint.port == IpEndpointName::ANY_PORT)\n\t\t? 0\n\t\t: htons( endpoint.port );\n}\n\n\nstatic IpEndpointName IpEndpointNameFromSockaddr( const struct sockaddr_in& sockAddr )\n{\n\treturn IpEndpointName( \n\t\t(sockAddr.sin_addr.s_addr == INADDR_ANY) \n\t\t\t? IpEndpointName::ANY_ADDRESS \n\t\t\t: ntohl( sockAddr.sin_addr.s_addr ),\n\t\t(sockAddr.sin_port == 0)\n\t\t\t? IpEndpointName::ANY_PORT\n\t\t\t: ntohs( sockAddr.sin_port )\n\t\t);\n}\n\n\nclass UdpSocket::Implementation{\n\tbool isBound_;\n\tbool isConnected_;\n\n\tint socket_;\n\tstruct sockaddr_in connectedAddr_;\n\tstruct sockaddr_in sendToAddr_;\n\npublic:\n\n\tImplementation()\n\t\t: isBound_( false )\n\t\t, isConnected_( false )\n\t\t, socket_( -1 )\n\t{\n\t\tif( (socket_ = socket( AF_INET, SOCK_DGRAM, 0 )) == -1 ){\n throw std::runtime_error(\"unable to create udp socket\\n\");\n }\n\n\t\tstd::memset( &sendToAddr_, 0, sizeof(sendToAddr_) );\n sendToAddr_.sin_family = AF_INET;\n\t}\n\n\t~Implementation()\n\t{\n\t\tif (socket_ != -1) close(socket_);\n\t}\n\n\tvoid SetEnableBroadcast( bool enableBroadcast )\n\t{\n\t\tint broadcast = (enableBroadcast) ? 1 : 0; // int on posix\n\t\tsetsockopt(socket_, SOL_SOCKET, SO_BROADCAST, &broadcast, sizeof(broadcast));\n\t}\n\n\tvoid SetAllowReuse( bool allowReuse )\n\t{\n\t\tint reuseAddr = (allowReuse) ? 1 : 0; // int on posix\n\t\tsetsockopt(socket_, SOL_SOCKET, SO_REUSEADDR, &reuseAddr, sizeof(reuseAddr));\n\n#ifdef __APPLE__\n\t\t// needed also for OS X - enable multiple listeners for a single port on same network interface\n\t\tint reusePort = (allowReuse) ? 1 : 0; // int on posix\n\t\tsetsockopt(socket_, SOL_SOCKET, SO_REUSEPORT, &reusePort, sizeof(reusePort));\n#endif\n\t}\n\n\tIpEndpointName LocalEndpointFor( const IpEndpointName& remoteEndpoint ) const\n\t{\n\t\tassert( isBound_ );\n\n\t\t// first connect the socket to the remote server\n \n struct sockaddr_in connectSockAddr;\n\t\tSockaddrFromIpEndpointName( connectSockAddr, remoteEndpoint );\n \n if (connect(socket_, (struct sockaddr *)&connectSockAddr, sizeof(connectSockAddr)) < 0) {\n throw std::runtime_error(\"unable to connect udp socket\\n\");\n }\n\n // get the address\n\n struct sockaddr_in sockAddr;\n std::memset( (char *)&sockAddr, 0, sizeof(sockAddr ) );\n socklen_t length = sizeof(sockAddr);\n if (getsockname(socket_, (struct sockaddr *)&sockAddr, &length) < 0) {\n throw std::runtime_error(\"unable to getsockname\\n\");\n }\n \n\t\tif( isConnected_ ){\n\t\t\t// reconnect to the connected address\n\t\t\t\n\t\t\tif (connect(socket_, (struct sockaddr *)&connectedAddr_, sizeof(connectedAddr_)) < 0) {\n\t\t\t\tthrow std::runtime_error(\"unable to connect udp socket\\n\");\n\t\t\t}\n\n\t\t}else{\n\t\t\t// unconnect from the remote address\n\t\t\n\t\t\tstruct sockaddr_in unconnectSockAddr;\n\t\t\tstd::memset( (char *)&unconnectSockAddr, 0, sizeof(unconnectSockAddr ) );\n\t\t\tunconnectSockAddr.sin_family = AF_UNSPEC;\n\t\t\t// address fields are zero\n\t\t\tint connectResult = connect(socket_, (struct sockaddr *)&unconnectSockAddr, sizeof(unconnectSockAddr));\n\t\t\tif ( connectResult < 0 && errno != EAFNOSUPPORT ) {\n\t\t\t\tthrow std::runtime_error(\"unable to un-connect udp socket\\n\");\n\t\t\t}\n\t\t}\n\n\t\treturn IpEndpointNameFromSockaddr( sockAddr );\n\t}\n\n\tvoid Connect( const IpEndpointName& remoteEndpoint )\n\t{\n\t\tSockaddrFromIpEndpointName( connectedAddr_, remoteEndpoint );\n \n if (connect(socket_, (struct sockaddr *)&connectedAddr_, sizeof(connectedAddr_)) < 0) {\n throw std::runtime_error(\"unable to connect udp socket\\n\");\n }\n\n\t\tisConnected_ = true;\n\t}\n\n\tvoid Send( const char *data, std::size_t size )\n\t{\n\t\tassert( isConnected_ );\n\n send( socket_, data, size, 0 );\n\t}\n\n void SendTo( const IpEndpointName& remoteEndpoint, const char *data, std::size_t size )\n\t{\n\t\tsendToAddr_.sin_addr.s_addr = htonl( remoteEndpoint.address );\n sendToAddr_.sin_port = htons( remoteEndpoint.port );\n\n sendto( socket_, data, size, 0, (sockaddr*)&sendToAddr_, sizeof(sendToAddr_) );\n\t}\n\n\tvoid Bind( const IpEndpointName& localEndpoint )\n\t{\n\t\tstruct sockaddr_in bindSockAddr;\n\t\tSockaddrFromIpEndpointName( bindSockAddr, localEndpoint );\n\n if (bind(socket_, (struct sockaddr *)&bindSockAddr, sizeof(bindSockAddr)) < 0) {\n throw std::runtime_error(\"unable to bind udp socket\\n\");\n }\n\n\t\tisBound_ = true;\n\t}\n\n\tbool IsBound() const { return isBound_; }\n\n std::size_t ReceiveFrom( IpEndpointName& remoteEndpoint, char *data, std::size_t size )\n\t{\n\t\tassert( isBound_ );\n\n\t\tstruct sockaddr_in fromAddr;\n socklen_t fromAddrLen = sizeof(fromAddr);\n \t \n ssize_t result = recvfrom(socket_, data, size, 0,\n (struct sockaddr *) &fromAddr, (socklen_t*)&fromAddrLen);\n\t\tif( result < 0 )\n\t\t\treturn 0;\n\n\t\tremoteEndpoint.address = ntohl(fromAddr.sin_addr.s_addr);\n\t\tremoteEndpoint.port = ntohs(fromAddr.sin_port);\n\n\t\treturn (std::size_t)result;\n\t}\n\n\tint Socket() { return socket_; }\n};\n\nUdpSocket::UdpSocket()\n{\n\timpl_ = new Implementation();\n}\n\nUdpSocket::~UdpSocket()\n{\n\tdelete impl_;\n}\n\nvoid UdpSocket::SetEnableBroadcast( bool enableBroadcast )\n{\n impl_->SetEnableBroadcast( enableBroadcast );\n}\n\nvoid UdpSocket::SetAllowReuse( bool allowReuse )\n{\n impl_->SetAllowReuse( allowReuse );\n}\n\nIpEndpointName UdpSocket::LocalEndpointFor( const IpEndpointName& remoteEndpoint ) const\n{\n\treturn impl_->LocalEndpointFor( remoteEndpoint );\n}\n\nvoid UdpSocket::Connect( const IpEndpointName& remoteEndpoint )\n{\n\timpl_->Connect( remoteEndpoint );\n}\n\nvoid UdpSocket::Send( const char *data, std::size_t size )\n{\n\timpl_->Send( data, size );\n}\n\nvoid UdpSocket::SendTo( const IpEndpointName& remoteEndpoint, const char *data, std::size_t size )\n{\n\timpl_->SendTo( remoteEndpoint, data, size );\n}\n\nvoid UdpSocket::Bind( const IpEndpointName& localEndpoint )\n{\n\timpl_->Bind( localEndpoint );\n}\n\nbool UdpSocket::IsBound() const\n{\n\treturn impl_->IsBound();\n}\n\nstd::size_t UdpSocket::ReceiveFrom( IpEndpointName& remoteEndpoint, char *data, std::size_t size )\n{\n\treturn impl_->ReceiveFrom( remoteEndpoint, data, size );\n}\n\n\nstruct AttachedTimerListener{\n\tAttachedTimerListener( int id, int p, TimerListener *tl )\n\t\t: initialDelayMs( id )\n\t\t, periodMs( p )\n\t\t, listener( tl ) {}\n\tint initialDelayMs;\n\tint periodMs;\n\tTimerListener *listener;\n};\n\n\nstatic bool CompareScheduledTimerCalls( \n\t\tconst std::pair< double, AttachedTimerListener > & lhs, const std::pair< double, AttachedTimerListener > & rhs )\n{\n\treturn lhs.first < rhs.first;\n}\n\n\nSocketReceiveMultiplexer *multiplexerInstanceToAbortWithSigInt_ = 0;\n\nextern \"C\" /*static*/ void InterruptSignalHandler( int );\n/*static*/ void InterruptSignalHandler( int )\n{\n\tmultiplexerInstanceToAbortWithSigInt_->AsynchronousBreak();\n\tsignal( SIGINT, SIG_DFL );\n}\n\n\nclass SocketReceiveMultiplexer::Implementation{\n\tstd::vector< std::pair< PacketListener*, UdpSocket* > > socketListeners_;\n\tstd::vector< AttachedTimerListener > timerListeners_;\n\n\tvolatile bool break_;\n\tint breakPipe_[2]; // [0] is the reader descriptor and [1] the writer\n\n\tdouble GetCurrentTimeMs() const\n\t{\n\t\tstruct timeval t;\n\n\t\tgettimeofday( &t, 0 );\n\n\t\treturn ((double)t.tv_sec*1000.) + ((double)t.tv_usec / 1000.);\n\t}\n\npublic:\n Implementation()\n\t{\n\t\tif( pipe(breakPipe_) != 0 )\n\t\t\tthrow std::runtime_error( \"creation of asynchronous break pipes failed\\n\" );\n\t}\n\n ~Implementation()\n\t{\n\t\tclose( breakPipe_[0] );\n\t\tclose( breakPipe_[1] );\n\t}\n\n void AttachSocketListener( UdpSocket *socket, PacketListener *listener )\n\t{\n\t\tassert( std::find( socketListeners_.begin(), socketListeners_.end(), std::make_pair(listener, socket) ) == socketListeners_.end() );\n\t\t// we don't check that the same socket has been added multiple times, even though this is an error\n\t\tsocketListeners_.push_back( std::make_pair( listener, socket ) );\n\t}\n\n void DetachSocketListener( UdpSocket *socket, PacketListener *listener )\n\t{\n\t\tstd::vector< std::pair< PacketListener*, UdpSocket* > >::iterator i = \n\t\t\t\tstd::find( socketListeners_.begin(), socketListeners_.end(), std::make_pair(listener, socket) );\n\t\tassert( i != socketListeners_.end() );\n\n\t\tsocketListeners_.erase( i );\n\t}\n\n void AttachPeriodicTimerListener( int periodMilliseconds, TimerListener *listener )\n\t{\n\t\ttimerListeners_.push_back( AttachedTimerListener( periodMilliseconds, periodMilliseconds, listener ) );\n\t}\n\n\tvoid AttachPeriodicTimerListener( int initialDelayMilliseconds, int periodMilliseconds, TimerListener *listener )\n\t{\n\t\ttimerListeners_.push_back( AttachedTimerListener( initialDelayMilliseconds, periodMilliseconds, listener ) );\n\t}\n\n void DetachPeriodicTimerListener( TimerListener *listener )\n\t{\n\t\tstd::vector< AttachedTimerListener >::iterator i = timerListeners_.begin();\n\t\twhile( i != timerListeners_.end() ){\n\t\t\tif( i->listener == listener )\n\t\t\t\tbreak;\n\t\t\t++i;\n\t\t}\n\n\t\tassert( i != timerListeners_.end() );\n\n\t\ttimerListeners_.erase( i );\n\t}\n\n void Run()\n\t{\n\t\tbreak_ = false;\n char *data = 0;\n \n try{\n \n // configure the master fd_set for select()\n\n fd_set masterfds, tempfds;\n FD_ZERO( &masterfds );\n FD_ZERO( &tempfds );\n \n // in addition to listening to the inbound sockets we\n // also listen to the asynchronous break pipe, so that AsynchronousBreak()\n // can break us out of select() from another thread.\n FD_SET( breakPipe_[0], &masterfds );\n int fdmax = breakPipe_[0];\t\t\n\n for( std::vector< std::pair< PacketListener*, UdpSocket* > >::iterator i = socketListeners_.begin();\n i != socketListeners_.end(); ++i ){\n\n if( fdmax < i->second->impl_->Socket() )\n fdmax = i->second->impl_->Socket();\n FD_SET( i->second->impl_->Socket(), &masterfds );\n }\n\n\n // configure the timer queue\n double currentTimeMs = GetCurrentTimeMs();\n\n // expiry time ms, listener\n std::vector< std::pair< double, AttachedTimerListener > > timerQueue_;\n for( std::vector< AttachedTimerListener >::iterator i = timerListeners_.begin();\n i != timerListeners_.end(); ++i )\n timerQueue_.push_back( std::make_pair( currentTimeMs + i->initialDelayMs, *i ) );\n std::sort( timerQueue_.begin(), timerQueue_.end(), CompareScheduledTimerCalls );\n\n const int MAX_BUFFER_SIZE = 4098;\n data = new char[ MAX_BUFFER_SIZE ];\n IpEndpointName remoteEndpoint;\n\n struct timeval timeout;\n\n while( !break_ ){\n tempfds = masterfds;\n\n struct timeval *timeoutPtr = 0;\n if( !timerQueue_.empty() ){\n double timeoutMs = timerQueue_.front().first - GetCurrentTimeMs();\n if( timeoutMs < 0 )\n timeoutMs = 0;\n \n long timoutSecondsPart = (long)(timeoutMs * .001);\n timeout.tv_sec = (time_t)timoutSecondsPart;\n // 1000000 microseconds in a second\n timeout.tv_usec = (suseconds_t)((timeoutMs - (timoutSecondsPart * 1000)) * 1000);\n timeoutPtr = &timeout;\n }\n\n if( select( fdmax + 1, &tempfds, 0, 0, timeoutPtr ) < 0 ){\n if( break_ ){\n break;\n }else if( errno == EINTR ){\n // on returning an error, select() doesn't clear tempfds.\n // so tempfds would remain all set, which would cause read( breakPipe_[0]...\n // below to block indefinitely. therefore if select returns EINTR we restart\n // the while() loop instead of continuing on to below.\n continue;\n }else{\n throw std::runtime_error(\"select failed\\n\");\n }\n }\n\n if( FD_ISSET( breakPipe_[0], &tempfds ) ){\n // clear pending data from the asynchronous break pipe\n char c;\n read( breakPipe_[0], &c, 1 );\n }\n \n if( break_ )\n break;\n\n for( std::vector< std::pair< PacketListener*, UdpSocket* > >::iterator i = socketListeners_.begin();\n i != socketListeners_.end(); ++i ){\n\n if( FD_ISSET( i->second->impl_->Socket(), &tempfds ) ){\n\n std::size_t size = i->second->ReceiveFrom( remoteEndpoint, data, MAX_BUFFER_SIZE );\n if( size > 0 ){\n i->first->ProcessPacket( data, (int)size, remoteEndpoint );\n if( break_ )\n break;\n }\n }\n }\n\n // execute any expired timers\n currentTimeMs = GetCurrentTimeMs();\n bool resort = false;\n for( std::vector< std::pair< double, AttachedTimerListener > >::iterator i = timerQueue_.begin();\n i != timerQueue_.end() && i->first <= currentTimeMs; ++i ){\n\n i->second.listener->TimerExpired();\n if( break_ )\n break;\n\n i->first += i->second.periodMs;\n resort = true;\n }\n if( resort )\n std::sort( timerQueue_.begin(), timerQueue_.end(), CompareScheduledTimerCalls );\n }\n\n delete [] data;\n }catch(...){\n if( data )\n delete [] data;\n throw;\n }\n\t}\n\n void Break()\n\t{\n\t\tbreak_ = true;\n\t}\n\n void AsynchronousBreak()\n\t{\n\t\tbreak_ = true;\n\n\t\t// Send a termination message to the asynchronous break pipe, so select() will return\n\t\twrite( breakPipe_[1], \"!\", 1 );\n\t}\n};\n\n\n\nSocketReceiveMultiplexer::SocketReceiveMultiplexer()\n{\n\timpl_ = new Implementation();\n}\n\nSocketReceiveMultiplexer::~SocketReceiveMultiplexer()\n{\t\n\tdelete impl_;\n}\n\nvoid SocketReceiveMultiplexer::AttachSocketListener( UdpSocket *socket, PacketListener *listener )\n{\n\timpl_->AttachSocketListener( socket, listener );\n}\n\nvoid SocketReceiveMultiplexer::DetachSocketListener( UdpSocket *socket, PacketListener *listener )\n{\n\timpl_->DetachSocketListener( socket, listener );\n}\n\nvoid SocketReceiveMultiplexer::AttachPeriodicTimerListener( int periodMilliseconds, TimerListener *listener )\n{\n\timpl_->AttachPeriodicTimerListener( periodMilliseconds, listener );\n}\n\nvoid SocketReceiveMultiplexer::AttachPeriodicTimerListener( int initialDelayMilliseconds, int periodMilliseconds, TimerListener *listener )\n{\n\timpl_->AttachPeriodicTimerListener( initialDelayMilliseconds, periodMilliseconds, listener );\n}\n\nvoid SocketReceiveMultiplexer::DetachPeriodicTimerListener( TimerListener *listener )\n{\n\timpl_->DetachPeriodicTimerListener( listener );\n}\n\nvoid SocketReceiveMultiplexer::Run()\n{\n\timpl_->Run();\n}\n\nvoid SocketReceiveMultiplexer::RunUntilSigInt()\n{\n\tassert( multiplexerInstanceToAbortWithSigInt_ == 0 ); /* at present we support only one multiplexer instance running until sig int */\n\tmultiplexerInstanceToAbortWithSigInt_ = this;\n\tsignal( SIGINT, InterruptSignalHandler );\n\timpl_->Run();\n\tsignal( SIGINT, SIG_DFL );\n\tmultiplexerInstanceToAbortWithSigInt_ = 0;\n}\n\nvoid SocketReceiveMultiplexer::Break()\n{\n\timpl_->Break();\n}\n\nvoid SocketReceiveMultiplexer::AsynchronousBreak()\n{\n\timpl_->AsynchronousBreak();\n}\n\n" }, { "path": "lib/oscpack/ip/win32/NetworkingUtils.cpp", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#include \"ip/NetworkingUtils.h\"\n\n#include // this must come first to prevent errors with MSVC7\n#include \n\n#include \n\n\nstatic LONG initCount_ = 0;\nstatic bool winsockInitialized_ = false;\n\nNetworkInitializer::NetworkInitializer()\n{\n if( InterlockedIncrement( &initCount_ ) == 1 ){\n // there is a race condition here if one thread tries to access\n // the library while another is still initializing it. \n // i can't think of an easy way to fix it so i'm telling you here\n // incase you need to init the library from two threads at once.\n // this is why the header file advises to instantiate one of these \n // in main() so that the initialization happens globally\n\n // initialize winsock\n\t WSAData wsaData;\n\t int nCode = WSAStartup(MAKEWORD(1, 1), &wsaData);\n\t if( nCode != 0 ){\n\t //std::cout << \"WSAStartup() failed with error code \" << nCode << \"\\n\";\n }else{\n winsockInitialized_ = true;\n }\n }\n}\n\n\nNetworkInitializer::~NetworkInitializer()\n{\n if( InterlockedDecrement( &initCount_ ) == 0 ){\n if( winsockInitialized_ ){\n WSACleanup();\n winsockInitialized_ = false;\n }\n }\n}\n\n\nunsigned long GetHostByName( const char *name )\n{\n NetworkInitializer networkInitializer;\n\n unsigned long result = 0;\n\n struct hostent *h = gethostbyname( name );\n if( h ){\n struct in_addr a;\n std::memcpy( &a, h->h_addr_list[0], h->h_length );\n result = ntohl(a.s_addr);\n }\n\n return result;\n}\n" }, { "path": "lib/oscpack/ip/win32/UdpSocket.cpp", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n\n#include // this must come first to prevent errors with MSVC7\n#include \n#include // for timeGetTime()\n\n#ifndef WINCE\n#include \n#endif\n\n#include \n#include \n#include // for memset\n#include \n#include \n\n#include \"ip/UdpSocket.h\" // usually I'd include the module header first\n // but this is causing conflicts with BCB4 due to\n // std::size_t usage.\n\n#include \"ip/NetworkingUtils.h\"\n#include \"ip/PacketListener.h\"\n#include \"ip/TimerListener.h\"\n\n\ntypedef int socklen_t;\n\n\nstatic void SockaddrFromIpEndpointName( struct sockaddr_in& sockAddr, const IpEndpointName& endpoint )\n{\n std::memset( (char *)&sockAddr, 0, sizeof(sockAddr ) );\n sockAddr.sin_family = AF_INET;\n\n\tsockAddr.sin_addr.s_addr = \n\t\t(endpoint.address == IpEndpointName::ANY_ADDRESS)\n\t\t? INADDR_ANY\n\t\t: htonl( endpoint.address );\n\n\tsockAddr.sin_port =\n\t\t(endpoint.port == IpEndpointName::ANY_PORT)\n\t\t? (short)0\n\t\t: htons( (short)endpoint.port );\n}\n\n\nstatic IpEndpointName IpEndpointNameFromSockaddr( const struct sockaddr_in& sockAddr )\n{\n\treturn IpEndpointName( \n\t\t(sockAddr.sin_addr.s_addr == INADDR_ANY) \n\t\t\t? IpEndpointName::ANY_ADDRESS \n\t\t\t: ntohl( sockAddr.sin_addr.s_addr ),\n\t\t(sockAddr.sin_port == 0)\n\t\t\t? IpEndpointName::ANY_PORT\n\t\t\t: ntohs( sockAddr.sin_port )\n\t\t);\n}\n\n\nclass UdpSocket::Implementation{\n NetworkInitializer networkInitializer_;\n\n\tbool isBound_;\n\tbool isConnected_;\n\n\tSOCKET socket_;\n\tstruct sockaddr_in connectedAddr_;\n\tstruct sockaddr_in sendToAddr_;\n\npublic:\n\n\tImplementation()\n\t\t: isBound_( false )\n\t\t, isConnected_( false )\n\t\t, socket_( INVALID_SOCKET )\n\t{\n\t\tif( (socket_ = socket( AF_INET, SOCK_DGRAM, 0 )) == INVALID_SOCKET ){\n throw std::runtime_error(\"unable to create udp socket\\n\");\n }\n\n\t\tstd::memset( &sendToAddr_, 0, sizeof(sendToAddr_) );\n sendToAddr_.sin_family = AF_INET;\n\t}\n\n\t~Implementation()\n\t{\n\t\tif (socket_ != INVALID_SOCKET) closesocket(socket_);\n\t}\n\n\tvoid SetEnableBroadcast( bool enableBroadcast )\n\t{\n\t\tchar broadcast = (char)((enableBroadcast) ? 1 : 0); // char on win32\n\t\tsetsockopt(socket_, SOL_SOCKET, SO_BROADCAST, &broadcast, sizeof(broadcast));\n\t}\n\n\tvoid SetAllowReuse( bool allowReuse )\n\t{\n\t\t// Note: SO_REUSEADDR is non-deterministic for listening sockets on Win32. See MSDN article:\n\t\t// \"Using SO_REUSEADDR and SO_EXCLUSIVEADDRUSE\"\n\t\t// http://msdn.microsoft.com/en-us/library/ms740621%28VS.85%29.aspx\n\n\t\tchar reuseAddr = (char)((allowReuse) ? 1 : 0); // char on win32\n\t\tsetsockopt(socket_, SOL_SOCKET, SO_REUSEADDR, &reuseAddr, sizeof(reuseAddr));\n\t}\n\n\tIpEndpointName LocalEndpointFor( const IpEndpointName& remoteEndpoint ) const\n\t{\n\t\tassert( isBound_ );\n\n\t\t// first connect the socket to the remote server\n \n struct sockaddr_in connectSockAddr;\n\t\tSockaddrFromIpEndpointName( connectSockAddr, remoteEndpoint );\n \n if (connect(socket_, (struct sockaddr *)&connectSockAddr, sizeof(connectSockAddr)) < 0) {\n throw std::runtime_error(\"unable to connect udp socket\\n\");\n }\n\n // get the address\n\n struct sockaddr_in sockAddr;\n std::memset( (char *)&sockAddr, 0, sizeof(sockAddr ) );\n socklen_t length = sizeof(sockAddr);\n if (getsockname(socket_, (struct sockaddr *)&sockAddr, &length) < 0) {\n throw std::runtime_error(\"unable to getsockname\\n\");\n }\n \n\t\tif( isConnected_ ){\n\t\t\t// reconnect to the connected address\n\t\t\t\n\t\t\tif (connect(socket_, (struct sockaddr *)&connectedAddr_, sizeof(connectedAddr_)) < 0) {\n\t\t\t\tthrow std::runtime_error(\"unable to connect udp socket\\n\");\n\t\t\t}\n\n\t\t}else{\n\t\t\t// unconnect from the remote address\n\t\t\n\t\t\tstruct sockaddr_in unconnectSockAddr;\n\t\t\tSockaddrFromIpEndpointName( unconnectSockAddr, IpEndpointName() );\n\n\t\t\tif( connect(socket_, (struct sockaddr *)&unconnectSockAddr, sizeof(unconnectSockAddr)) < 0 \n\t\t\t\t\t&& WSAGetLastError() != WSAEADDRNOTAVAIL ){\n\t\t\t\tthrow std::runtime_error(\"unable to un-connect udp socket\\n\");\n\t\t\t}\n\t\t}\n\n\t\treturn IpEndpointNameFromSockaddr( sockAddr );\n\t}\n\n\tvoid Connect( const IpEndpointName& remoteEndpoint )\n\t{\n\t\tSockaddrFromIpEndpointName( connectedAddr_, remoteEndpoint );\n \n if (connect(socket_, (struct sockaddr *)&connectedAddr_, sizeof(connectedAddr_)) < 0) {\n throw std::runtime_error(\"unable to connect udp socket\\n\");\n }\n\n\t\tisConnected_ = true;\n\t}\n\n\tvoid Send( const char *data, std::size_t size )\n\t{\n\t\tassert( isConnected_ );\n\n send( socket_, data, (int)size, 0 );\n\t}\n\n void SendTo( const IpEndpointName& remoteEndpoint, const char *data, std::size_t size )\n\t{\n\t\tsendToAddr_.sin_addr.s_addr = htonl( remoteEndpoint.address );\n sendToAddr_.sin_port = htons( (short)remoteEndpoint.port );\n\n sendto( socket_, data, (int)size, 0, (sockaddr*)&sendToAddr_, sizeof(sendToAddr_) );\n\t}\n\n\tvoid Bind( const IpEndpointName& localEndpoint )\n\t{\n\t\tstruct sockaddr_in bindSockAddr;\n\t\tSockaddrFromIpEndpointName( bindSockAddr, localEndpoint );\n\n if (bind(socket_, (struct sockaddr *)&bindSockAddr, sizeof(bindSockAddr)) < 0) {\n throw std::runtime_error(\"unable to bind udp socket\\n\");\n }\n\n\t\tisBound_ = true;\n\t}\n\n\tbool IsBound() const { return isBound_; }\n\n std::size_t ReceiveFrom( IpEndpointName& remoteEndpoint, char *data, std::size_t size )\n\t{\n\t\tassert( isBound_ );\n\n\t\tstruct sockaddr_in fromAddr;\n socklen_t fromAddrLen = sizeof(fromAddr);\n \t \n int result = recvfrom(socket_, data, (int)size, 0,\n (struct sockaddr *) &fromAddr, (socklen_t*)&fromAddrLen);\n\t\tif( result < 0 )\n\t\t\treturn 0;\n\n\t\tremoteEndpoint.address = ntohl(fromAddr.sin_addr.s_addr);\n\t\tremoteEndpoint.port = ntohs(fromAddr.sin_port);\n\n\t\treturn result;\n\t}\n\n\tSOCKET& Socket() { return socket_; }\n};\n\nUdpSocket::UdpSocket()\n{\n\timpl_ = new Implementation();\n}\n\nUdpSocket::~UdpSocket()\n{\n\tdelete impl_;\n}\n\nvoid UdpSocket::SetEnableBroadcast( bool enableBroadcast )\n{\n impl_->SetEnableBroadcast( enableBroadcast );\n}\n\nvoid UdpSocket::SetAllowReuse( bool allowReuse )\n{\n impl_->SetAllowReuse( allowReuse );\n}\n\nIpEndpointName UdpSocket::LocalEndpointFor( const IpEndpointName& remoteEndpoint ) const\n{\n\treturn impl_->LocalEndpointFor( remoteEndpoint );\n}\n\nvoid UdpSocket::Connect( const IpEndpointName& remoteEndpoint )\n{\n\timpl_->Connect( remoteEndpoint );\n}\n\nvoid UdpSocket::Send( const char *data, std::size_t size )\n{\n\timpl_->Send( data, size );\n}\n\nvoid UdpSocket::SendTo( const IpEndpointName& remoteEndpoint, const char *data, std::size_t size )\n{\n\timpl_->SendTo( remoteEndpoint, data, size );\n}\n\nvoid UdpSocket::Bind( const IpEndpointName& localEndpoint )\n{\n\timpl_->Bind( localEndpoint );\n}\n\nbool UdpSocket::IsBound() const\n{\n\treturn impl_->IsBound();\n}\n\nstd::size_t UdpSocket::ReceiveFrom( IpEndpointName& remoteEndpoint, char *data, std::size_t size )\n{\n\treturn impl_->ReceiveFrom( remoteEndpoint, data, size );\n}\n\n\nstruct AttachedTimerListener{\n\tAttachedTimerListener( int id, int p, TimerListener *tl )\n\t\t: initialDelayMs( id )\n\t\t, periodMs( p )\n\t\t, listener( tl ) {}\n\tint initialDelayMs;\n\tint periodMs;\n\tTimerListener *listener;\n};\n\n\nstatic bool CompareScheduledTimerCalls( \n\t\tconst std::pair< double, AttachedTimerListener > & lhs, const std::pair< double, AttachedTimerListener > & rhs )\n{\n\treturn lhs.first < rhs.first;\n}\n\n\nSocketReceiveMultiplexer *multiplexerInstanceToAbortWithSigInt_ = 0;\n\nextern \"C\" /*static*/ void InterruptSignalHandler( int );\n/*static*/ void InterruptSignalHandler( int )\n{\n\tmultiplexerInstanceToAbortWithSigInt_->AsynchronousBreak();\n#ifndef WINCE\n signal( SIGINT, SIG_DFL );\n#endif\n}\n\n\nclass SocketReceiveMultiplexer::Implementation{\n NetworkInitializer networkInitializer_;\n\n\tstd::vector< std::pair< PacketListener*, UdpSocket* > > socketListeners_;\n\tstd::vector< AttachedTimerListener > timerListeners_;\n\n\tvolatile bool break_;\n\tHANDLE breakEvent_;\n\n\tdouble GetCurrentTimeMs() const\n\t{\n#ifndef WINCE\n\t\treturn timeGetTime(); // FIXME: bad choice if you want to run for more than 40 days\n#else\n return 0;\n#endif\n }\n\npublic:\n Implementation()\n\t{\n\t\tbreakEvent_ = CreateEvent( NULL, FALSE, FALSE, NULL );\n\t}\n\n ~Implementation()\n\t{\n\t\tCloseHandle( breakEvent_ );\n\t}\n\n void AttachSocketListener( UdpSocket *socket, PacketListener *listener )\n\t{\n\t\tassert( std::find( socketListeners_.begin(), socketListeners_.end(), std::make_pair(listener, socket) ) == socketListeners_.end() );\n\t\t// we don't check that the same socket has been added multiple times, even though this is an error\n\t\tsocketListeners_.push_back( std::make_pair( listener, socket ) );\n\t}\n\n void DetachSocketListener( UdpSocket *socket, PacketListener *listener )\n\t{\n\t\tstd::vector< std::pair< PacketListener*, UdpSocket* > >::iterator i = \n\t\t\t\tstd::find( socketListeners_.begin(), socketListeners_.end(), std::make_pair(listener, socket) );\n\t\tassert( i != socketListeners_.end() );\n\n\t\tsocketListeners_.erase( i );\n\t}\n\n void AttachPeriodicTimerListener( int periodMilliseconds, TimerListener *listener )\n\t{\n\t\ttimerListeners_.push_back( AttachedTimerListener( periodMilliseconds, periodMilliseconds, listener ) );\n\t}\n\n\tvoid AttachPeriodicTimerListener( int initialDelayMilliseconds, int periodMilliseconds, TimerListener *listener )\n\t{\n\t\ttimerListeners_.push_back( AttachedTimerListener( initialDelayMilliseconds, periodMilliseconds, listener ) );\n\t}\n\n void DetachPeriodicTimerListener( TimerListener *listener )\n\t{\n\t\tstd::vector< AttachedTimerListener >::iterator i = timerListeners_.begin();\n\t\twhile( i != timerListeners_.end() ){\n\t\t\tif( i->listener == listener )\n\t\t\t\tbreak;\n\t\t\t++i;\n\t\t}\n\n\t\tassert( i != timerListeners_.end() );\n\n\t\ttimerListeners_.erase( i );\n\t}\n\n void Run()\n\t{\n\t\tbreak_ = false;\n\n\t\t// prepare the window events which we use to wake up on incoming data\n\t\t// we use this instead of select() primarily to support the AsyncBreak() \n\t\t// mechanism.\n\n\t\tstd::vector events( socketListeners_.size() + 1, 0 );\n\t\tint j=0;\n\t\tfor( std::vector< std::pair< PacketListener*, UdpSocket* > >::iterator i = socketListeners_.begin();\n\t\t\t\ti != socketListeners_.end(); ++i, ++j ){\n\n\t\t\tHANDLE event = CreateEvent( NULL, FALSE, FALSE, NULL );\n\t\t\tWSAEventSelect( i->second->impl_->Socket(), event, FD_READ ); // note that this makes the socket non-blocking which is why we can safely call RecieveFrom() on all sockets below\n\t\t\tevents[j] = event;\n\t\t}\n\n\n\t\tevents[ socketListeners_.size() ] = breakEvent_; // last event in the collection is the break event\n\n\t\t\n\t\t// configure the timer queue\n\t\tdouble currentTimeMs = GetCurrentTimeMs();\n\n\t\t// expiry time ms, listener\n\t\tstd::vector< std::pair< double, AttachedTimerListener > > timerQueue_;\n\t\tfor( std::vector< AttachedTimerListener >::iterator i = timerListeners_.begin();\n\t\t\t\ti != timerListeners_.end(); ++i )\n\t\t\ttimerQueue_.push_back( std::make_pair( currentTimeMs + i->initialDelayMs, *i ) );\n\t\tstd::sort( timerQueue_.begin(), timerQueue_.end(), CompareScheduledTimerCalls );\n\n\t\tconst int MAX_BUFFER_SIZE = 4098;\n\t\tchar *data = new char[ MAX_BUFFER_SIZE ];\n\t\tIpEndpointName remoteEndpoint;\n\n\t\twhile( !break_ ){\n\n\t\t\tdouble currentTimeMs = GetCurrentTimeMs();\n\n DWORD waitTime = INFINITE;\n if( !timerQueue_.empty() ){\n\n waitTime = (DWORD)( timerQueue_.front().first >= currentTimeMs\n ? timerQueue_.front().first - currentTimeMs\n : 0 );\n }\n\n\t\t\tDWORD waitResult = WaitForMultipleObjects( (DWORD)socketListeners_.size() + 1, &events[0], FALSE, waitTime );\n\t\t\tif( break_ )\n\t\t\t\tbreak;\n\n\t\t\tif( waitResult != WAIT_TIMEOUT ){\n\t\t\t\tfor( int i = waitResult - WAIT_OBJECT_0; i < (int)socketListeners_.size(); ++i ){\n\t\t\t\t\tstd::size_t size = socketListeners_[i].second->ReceiveFrom( remoteEndpoint, data, MAX_BUFFER_SIZE );\n\t\t\t\t\tif( size > 0 ){\n\t\t\t\t\t\tsocketListeners_[i].first->ProcessPacket( data, (int)size, remoteEndpoint );\n\t\t\t\t\t\tif( break_ )\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t// execute any expired timers\n\t\t\tcurrentTimeMs = GetCurrentTimeMs();\n\t\t\tbool resort = false;\n\t\t\tfor( std::vector< std::pair< double, AttachedTimerListener > >::iterator i = timerQueue_.begin();\n\t\t\t\t\ti != timerQueue_.end() && i->first <= currentTimeMs; ++i ){\n\n\t\t\t\ti->second.listener->TimerExpired();\n\t\t\t\tif( break_ )\n\t\t\t\t\tbreak;\n\n\t\t\t\ti->first += i->second.periodMs;\n\t\t\t\tresort = true;\n\t\t\t}\n\t\t\tif( resort )\n\t\t\t\tstd::sort( timerQueue_.begin(), timerQueue_.end(), CompareScheduledTimerCalls );\n\t\t}\n\n\t\tdelete [] data;\n\n\t\t// free events\n\t\tj = 0;\n\t\tfor( std::vector< std::pair< PacketListener*, UdpSocket* > >::iterator i = socketListeners_.begin();\n\t\t\t\ti != socketListeners_.end(); ++i, ++j ){\n\n\t\t\tWSAEventSelect( i->second->impl_->Socket(), events[j], 0 ); // remove association between socket and event\n\t\t\tCloseHandle( events[j] );\n\t\t\tunsigned long enableNonblocking = 0;\n\t\t\tioctlsocket( i->second->impl_->Socket(), FIONBIO, &enableNonblocking ); // make the socket blocking again\n\t\t}\n\t}\n\n void Break()\n\t{\n\t\tbreak_ = true;\n\t}\n\n void AsynchronousBreak()\n\t{\n\t\tbreak_ = true;\n\t\tSetEvent( breakEvent_ );\n\t}\n};\n\n\n\nSocketReceiveMultiplexer::SocketReceiveMultiplexer()\n{\n\timpl_ = new Implementation();\n}\n\nSocketReceiveMultiplexer::~SocketReceiveMultiplexer()\n{\t\n\tdelete impl_;\n}\n\nvoid SocketReceiveMultiplexer::AttachSocketListener( UdpSocket *socket, PacketListener *listener )\n{\n\timpl_->AttachSocketListener( socket, listener );\n}\n\nvoid SocketReceiveMultiplexer::DetachSocketListener( UdpSocket *socket, PacketListener *listener )\n{\n\timpl_->DetachSocketListener( socket, listener );\n}\n\nvoid SocketReceiveMultiplexer::AttachPeriodicTimerListener( int periodMilliseconds, TimerListener *listener )\n{\n\timpl_->AttachPeriodicTimerListener( periodMilliseconds, listener );\n}\n\nvoid SocketReceiveMultiplexer::AttachPeriodicTimerListener( int initialDelayMilliseconds, int periodMilliseconds, TimerListener *listener )\n{\n\timpl_->AttachPeriodicTimerListener( initialDelayMilliseconds, periodMilliseconds, listener );\n}\n\nvoid SocketReceiveMultiplexer::DetachPeriodicTimerListener( TimerListener *listener )\n{\n\timpl_->DetachPeriodicTimerListener( listener );\n}\n\nvoid SocketReceiveMultiplexer::Run()\n{\n\timpl_->Run();\n}\n\nvoid SocketReceiveMultiplexer::RunUntilSigInt()\n{\n\tassert( multiplexerInstanceToAbortWithSigInt_ == 0 ); /* at present we support only one multiplexer instance running until sig int */\n\tmultiplexerInstanceToAbortWithSigInt_ = this;\n#ifndef WINCE\n signal( SIGINT, InterruptSignalHandler );\n#endif\n\timpl_->Run();\n#ifndef WINCE\n\tsignal( SIGINT, SIG_DFL );\n#endif\n\tmultiplexerInstanceToAbortWithSigInt_ = 0;\n}\n\nvoid SocketReceiveMultiplexer::Break()\n{\n\timpl_->Break();\n}\n\nvoid SocketReceiveMultiplexer::AsynchronousBreak()\n{\n\timpl_->AsynchronousBreak();\n}\n\n" }, { "path": "lib/oscpack/osc/MessageMappingOscPacketListener.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_MESSAGEMAPPINGOSCPACKETLISTENER_H\n#define INCLUDED_OSCPACK_MESSAGEMAPPINGOSCPACKETLISTENER_H\n\n#include \n#include \n\n#include \"OscPacketListener.h\"\n\n\n\nnamespace osc{\n\ntemplate< class T >\nclass MessageMappingOscPacketListener : public OscPacketListener{\npublic:\n typedef void (T::*function_type)(const osc::ReceivedMessage&, const IpEndpointName&);\n\nprotected:\n void RegisterMessageFunction( const char *addressPattern, function_type f )\n {\n functions_.insert( std::make_pair( addressPattern, f ) );\n }\n\n virtual void ProcessMessage( const osc::ReceivedMessage& m,\n\t\tconst IpEndpointName& remoteEndpoint )\n {\n typename function_map_type::iterator i = functions_.find( m.AddressPattern() );\n if( i != functions_.end() )\n (dynamic_cast(this)->*(i->second))( m, remoteEndpoint );\n }\n \nprivate:\n struct cstr_compare{\n bool operator()( const char *lhs, const char *rhs ) const\n { return std::strcmp( lhs, rhs ) < 0; }\n };\n\n typedef std::map function_map_type;\n function_map_type functions_;\n};\n\n} // namespace osc\n\n#endif /* INCLUDED_OSCPACK_MESSAGEMAPPINGOSCPACKETLISTENER_H */" }, { "path": "lib/oscpack/osc/OscException.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_OSCEXCEPTION_H\n#define INCLUDED_OSCPACK_OSCEXCEPTION_H\n\n#include \n\nnamespace osc\n{\n\nclass Exception : public std::exception\n{\n const char* what_;\n\npublic:\n Exception() throw() {}\n Exception(const Exception& src) throw()\n : std::exception(src)\n , what_(src.what_)\n {\n }\n Exception(const char* w) throw()\n : what_(w)\n {\n }\n Exception& operator=(const Exception& src) throw()\n {\n what_ = src.what_;\n return *this;\n }\n virtual ~Exception() throw() {}\n const char* what() const throw() override { return what_; }\n};\n\n} // namespace osc\n\n#endif /* INCLUDED_OSCPACK_OSCEXCEPTION_H */\n" }, { "path": "lib/oscpack/osc/OscHostEndianness.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_OSCHOSTENDIANNESS_H\n#define INCLUDED_OSCPACK_OSCHOSTENDIANNESS_H\n\n/*\n Make sure either OSC_HOST_LITTLE_ENDIAN or OSC_HOST_BIG_ENDIAN is defined\n\n We try to use preprocessor symbols to deduce the host endianness.\n\n Alternatively you can define one of the above symbols from the command line.\n Usually you do this with the -D flag to the compiler. e.g.:\n\n $ g++ -DOSC_HOST_LITTLE_ENDIAN ...\n*/\n\n#if defined(OSC_HOST_LITTLE_ENDIAN) || defined(OSC_HOST_BIG_ENDIAN)\n\n// endianness defined on the command line. nothing to do here.\n\n#elif defined(__WIN32__) || defined(WIN32) || defined(WINCE)\n\n// assume that __WIN32__ is only defined on little endian systems\n\n#define OSC_HOST_LITTLE_ENDIAN 1\n#undef OSC_HOST_BIG_ENDIAN\n\n#elif defined(__APPLE__)\n\n#if defined(__LITTLE_ENDIAN__)\n\n#define OSC_HOST_LITTLE_ENDIAN 1\n#undef OSC_HOST_BIG_ENDIAN\n\n#elif defined(__BIG_ENDIAN__)\n\n#define OSC_HOST_BIG_ENDIAN 1\n#undef OSC_HOST_LITTLE_ENDIAN\n\n#endif\n\n#elif defined(__BYTE_ORDER__) && defined(__ORDER_LITTLE_ENDIAN__) && defined(__ORDER_BIG_ENDIAN__)\n\n// should cover gcc and clang\n\n#if (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)\n\n#define OSC_HOST_LITTLE_ENDIAN 1\n#undef OSC_HOST_BIG_ENDIAN\n\n#elif (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)\n\n#define OSC_HOST_BIG_ENDIAN 1\n#undef OSC_HOST_LITTLE_ENDIAN\n\n#endif\n\n#else\n\n// gcc defines __LITTLE_ENDIAN__ and __BIG_ENDIAN__\n// for others used here see http://sourceforge.net/p/predef/wiki/Endianness/\n#if (defined(__LITTLE_ENDIAN__) && !defined(__BIG_ENDIAN__)) \\\n || (defined(__ARMEL__) && !defined(__ARMEB__)) \\\n || (defined(__AARCH64EL__) && !defined(__AARCH64EB__)) \\\n || (defined(_MIPSEL) && !defined(_MIPSEB)) \\\n || (defined(__MIPSEL) && !defined(__MIPSEB)) \\\n || (defined(__MIPSEL__) && !defined(__MIPSEB__))\n\n#define OSC_HOST_LITTLE_ENDIAN 1\n#undef OSC_HOST_BIG_ENDIAN\n\n#elif (defined(__BIG_ENDIAN__) && !defined(__LITTLE_ENDIAN__)) \\\n || (defined(__ARMEB__) && !defined(__ARMEL__)) \\\n || (defined(__AARCH64EB__) && !defined(__AARCH64EL__)) \\\n || (defined(_MIPSEB) && !defined(_MIPSEL)) \\\n || (defined(__MIPSEB) && !defined(__MIPSEL)) \\\n || (defined(__MIPSEB__) && !defined(__MIPSEL__))\n\n#define OSC_HOST_BIG_ENDIAN 1\n#undef OSC_HOST_LITTLE_ENDIAN\n\n#endif\n\n#endif\n\n#if !defined(OSC_HOST_LITTLE_ENDIAN) && !defined(OSC_HOST_BIG_ENDIAN)\n\n#error please edit OSCHostEndianness.h or define one of {OSC_HOST_LITTLE_ENDIAN, OSC_HOST_BIG_ENDIAN} to configure endianness\n\n#endif\n\n#endif /* INCLUDED_OSCPACK_OSCHOSTENDIANNESS_H */\n\n" }, { "path": "lib/oscpack/osc/OscOutboundPacketStream.cpp", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#include \"OscOutboundPacketStream.h\"\n\n#if defined(__WIN32__) || defined(WIN32) || defined(_WIN32)\n#include // for alloca\n#else\n//#include // alloca on Linux (also OSX)\n#include // alloca on OSX and FreeBSD (and Linux?)\n#endif\n\n#include \n#include // memcpy, memmove, strcpy, strlen\n#include // ptrdiff_t\n\n#include \"OscHostEndianness.h\"\n\n#if defined(__BORLANDC__) // workaround for BCB4 release build intrinsics bug\nnamespace std {\nusing ::__strcpy__; // avoid error: E2316 '__strcpy__' is not a member of 'std'.\n}\n#endif\n\nnamespace osc{\n\nstatic void FromInt32( char *p, int32 x )\n{\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union{\n osc::int32 i;\n char c[4];\n } u;\n\n u.i = x;\n\n p[3] = u.c[0];\n p[2] = u.c[1];\n p[1] = u.c[2];\n p[0] = u.c[3];\n#else\n *reinterpret_cast(p) = x;\n#endif\n}\n\n\nstatic void FromUInt32( char *p, uint32 x )\n{\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union{\n osc::uint32 i;\n char c[4];\n } u;\n\n u.i = x;\n\n p[3] = u.c[0];\n p[2] = u.c[1];\n p[1] = u.c[2];\n p[0] = u.c[3];\n#else\n *reinterpret_cast(p) = x;\n#endif\n}\n\n\nstatic void FromInt64( char *p, int64 x )\n{\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union{\n osc::int64 i;\n char c[8];\n } u;\n\n u.i = x;\n\n p[7] = u.c[0];\n p[6] = u.c[1];\n p[5] = u.c[2];\n p[4] = u.c[3];\n p[3] = u.c[4];\n p[2] = u.c[5];\n p[1] = u.c[6];\n p[0] = u.c[7];\n#else\n *reinterpret_cast(p) = x;\n#endif\n}\n\n\nstatic void FromUInt64( char *p, uint64 x )\n{\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union{\n osc::uint64 i;\n char c[8];\n } u;\n\n u.i = x;\n\n p[7] = u.c[0];\n p[6] = u.c[1];\n p[5] = u.c[2];\n p[4] = u.c[3];\n p[3] = u.c[4];\n p[2] = u.c[5];\n p[1] = u.c[6];\n p[0] = u.c[7];\n#else\n *reinterpret_cast(p) = x;\n#endif\n}\n\n\n// round up to the next highest multiple of 4. unless x is already a multiple of 4\nstatic inline std::size_t RoundUp4( std::size_t x ) \n{\n return (x + 3) & ~((std::size_t)0x03);\n}\n\n\nOutboundPacketStream::OutboundPacketStream( char *buffer, std::size_t capacity )\n : data_( buffer )\n , end_( data_ + capacity )\n , typeTagsCurrent_( end_ )\n , messageCursor_( data_ )\n , argumentCurrent_( data_ )\n , elementSizePtr_( 0 )\n , messageIsInProgress_( false )\n{\n // sanity check integer types declared in OscTypes.h \n // you'll need to fix OscTypes.h if any of these asserts fail\n assert( sizeof(osc::int32) == 4 );\n assert( sizeof(osc::uint32) == 4 );\n assert( sizeof(osc::int64) == 8 );\n assert( sizeof(osc::uint64) == 8 );\n}\n\n\nOutboundPacketStream::~OutboundPacketStream()\n{\n\n}\n\n\nchar *OutboundPacketStream::BeginElement( char *beginPtr )\n{\n if( elementSizePtr_ == 0 ){\n\n elementSizePtr_ = reinterpret_cast(data_);\n\n return beginPtr;\n\n }else{\n // store an offset to the old element size ptr in the element size slot\n // we store an offset rather than the actual pointer to be 64 bit clean.\n *reinterpret_cast(beginPtr) =\n (uint32)(reinterpret_cast(elementSizePtr_) - data_);\n\n elementSizePtr_ = reinterpret_cast(beginPtr);\n\n return beginPtr + 4;\n }\n}\n\n\nvoid OutboundPacketStream::EndElement( char *endPtr )\n{\n assert( elementSizePtr_ != 0 );\n\n if( elementSizePtr_ == reinterpret_cast(data_) ){\n\n elementSizePtr_ = 0;\n\n }else{\n // while building an element, an offset to the containing element's\n // size slot is stored in the elements size slot (or a ptr to data_\n // if there is no containing element). We retrieve that here\n uint32 *previousElementSizePtr =\n reinterpret_cast(data_ + *elementSizePtr_);\n\n // then we store the element size in the slot. note that the element\n // size does not include the size slot, hence the - 4 below.\n\n std::ptrdiff_t d = endPtr - reinterpret_cast(elementSizePtr_);\n // assert( d >= 4 && d <= 0x7FFFFFFF ); // assume packets smaller than 2Gb\n\n uint32 elementSize = static_cast(d - 4);\n FromUInt32( reinterpret_cast(elementSizePtr_), elementSize );\n\n // finally, we reset the element size ptr to the containing element\n elementSizePtr_ = previousElementSizePtr;\n }\n}\n\n\nbool OutboundPacketStream::ElementSizeSlotRequired() const\n{\n return (elementSizePtr_ != 0);\n}\n\n\nvoid OutboundPacketStream::CheckForAvailableBundleSpace()\n{\n std::size_t required = Size() + ((ElementSizeSlotRequired())?4:0) + 16;\n\n if( required > Capacity() )\n throw OutOfBufferMemoryException();\n}\n\n\nvoid OutboundPacketStream::CheckForAvailableMessageSpace( const char *addressPattern )\n{\n // plus 4 for at least four bytes of type tag\n std::size_t required = Size() + ((ElementSizeSlotRequired())?4:0)\n + RoundUp4(std::strlen(addressPattern) + 1) + 4;\n\n if( required > Capacity() )\n throw OutOfBufferMemoryException();\n}\n\n\nvoid OutboundPacketStream::CheckForAvailableArgumentSpace( std::size_t argumentLength )\n{\n // plus three for extra type tag, comma and null terminator\n std::size_t required = (argumentCurrent_ - data_) + argumentLength\n + RoundUp4( (end_ - typeTagsCurrent_) + 3 );\n\n if( required > Capacity() )\n throw OutOfBufferMemoryException();\n}\n\n\nvoid OutboundPacketStream::Clear()\n{\n typeTagsCurrent_ = end_;\n messageCursor_ = data_;\n argumentCurrent_ = data_;\n elementSizePtr_ = 0;\n messageIsInProgress_ = false;\n}\n\n\nstd::size_t OutboundPacketStream::Capacity() const\n{\n return end_ - data_;\n}\n\n\nstd::size_t OutboundPacketStream::Size() const\n{\n std::size_t result = argumentCurrent_ - data_;\n if( IsMessageInProgress() ){\n // account for the length of the type tag string. the total type tag\n // includes an initial comma, plus at least one terminating \\0\n result += RoundUp4( (end_ - typeTagsCurrent_) + 2 );\n }\n\n return result;\n}\n\n\nconst char *OutboundPacketStream::Data() const\n{\n return data_;\n}\n\n\nbool OutboundPacketStream::IsReady() const\n{\n return (!IsMessageInProgress() && !IsBundleInProgress());\n}\n\n\nbool OutboundPacketStream::IsMessageInProgress() const\n{\n return messageIsInProgress_;\n}\n\n\nbool OutboundPacketStream::IsBundleInProgress() const\n{\n return (elementSizePtr_ != 0);\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const BundleInitiator& rhs )\n{\n if( IsMessageInProgress() )\n throw MessageInProgressException();\n\n CheckForAvailableBundleSpace();\n\n messageCursor_ = BeginElement( messageCursor_ );\n\n std::memcpy( messageCursor_, \"#bundle\\0\", 8 );\n FromUInt64( messageCursor_ + 8, rhs.timeTag );\n\n messageCursor_ += 16;\n argumentCurrent_ = messageCursor_;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const BundleTerminator& rhs )\n{\n (void) rhs;\n\n if( !IsBundleInProgress() )\n throw BundleNotInProgressException();\n if( IsMessageInProgress() )\n throw MessageInProgressException();\n\n EndElement( messageCursor_ );\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const BeginMessage& rhs )\n{\n if( IsMessageInProgress() )\n throw MessageInProgressException();\n\n CheckForAvailableMessageSpace( rhs.addressPattern );\n\n messageCursor_ = BeginElement( messageCursor_ );\n\n std::strcpy( messageCursor_, rhs.addressPattern );\n std::size_t rhsLength = std::strlen(rhs.addressPattern);\n messageCursor_ += rhsLength + 1;\n\n // zero pad to 4-byte boundary\n std::size_t i = rhsLength + 1;\n while( i & 0x3 ){\n *messageCursor_++ = '\\0';\n ++i;\n }\n\n argumentCurrent_ = messageCursor_;\n typeTagsCurrent_ = end_;\n\n messageIsInProgress_ = true;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const MessageTerminator& rhs )\n{\n (void) rhs;\n\n if( !IsMessageInProgress() )\n throw MessageNotInProgressException();\n\n std::size_t typeTagsCount = end_ - typeTagsCurrent_;\n\n if( typeTagsCount ){\n\n char *tempTypeTags = (char*)alloca(typeTagsCount);\n std::memcpy( tempTypeTags, typeTagsCurrent_, typeTagsCount );\n\n // slot size includes comma and null terminator\n std::size_t typeTagSlotSize = RoundUp4( typeTagsCount + 2 );\n\n std::size_t argumentsSize = argumentCurrent_ - messageCursor_;\n\n std::memmove( messageCursor_ + typeTagSlotSize, messageCursor_, argumentsSize );\n\n messageCursor_[0] = ',';\n // copy type tags in reverse (really forward) order\n for( std::size_t i=0; i < typeTagsCount; ++i )\n messageCursor_[i+1] = tempTypeTags[ (typeTagsCount-1) - i ];\n\n char *p = messageCursor_ + 1 + typeTagsCount;\n for( std::size_t i=0; i < (typeTagSlotSize - (typeTagsCount + 1)); ++i )\n *p++ = '\\0';\n\n typeTagsCurrent_ = end_;\n\n // advance messageCursor_ for next message\n messageCursor_ += typeTagSlotSize + argumentsSize;\n\n }else{\n // send an empty type tags string\n std::memcpy( messageCursor_, \",\\0\\0\\0\", 4 );\n\n // advance messageCursor_ for next message\n messageCursor_ += 4;\n }\n\n argumentCurrent_ = messageCursor_;\n\n EndElement( messageCursor_ );\n\n messageIsInProgress_ = false;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( bool rhs )\n{\n CheckForAvailableArgumentSpace(0);\n\n *(--typeTagsCurrent_) = (char)((rhs) ? TRUE_TYPE_TAG : FALSE_TYPE_TAG);\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const NilType& rhs )\n{\n (void) rhs;\n CheckForAvailableArgumentSpace(0);\n\n *(--typeTagsCurrent_) = NIL_TYPE_TAG;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const InfinitumType& rhs )\n{\n (void) rhs;\n CheckForAvailableArgumentSpace(0);\n\n *(--typeTagsCurrent_) = INFINITUM_TYPE_TAG;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( int32 rhs )\n{\n CheckForAvailableArgumentSpace(4);\n\n *(--typeTagsCurrent_) = INT32_TYPE_TAG;\n FromInt32( argumentCurrent_, rhs );\n argumentCurrent_ += 4;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( float rhs )\n{\n CheckForAvailableArgumentSpace(4);\n\n *(--typeTagsCurrent_) = FLOAT_TYPE_TAG;\n\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union{\n float f;\n char c[4];\n } u;\n\n u.f = rhs;\n\n argumentCurrent_[3] = u.c[0];\n argumentCurrent_[2] = u.c[1];\n argumentCurrent_[1] = u.c[2];\n argumentCurrent_[0] = u.c[3];\n#else\n *reinterpret_cast(argumentCurrent_) = rhs;\n#endif\n\n argumentCurrent_ += 4;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( char rhs )\n{\n CheckForAvailableArgumentSpace(4);\n\n *(--typeTagsCurrent_) = CHAR_TYPE_TAG;\n FromInt32( argumentCurrent_, rhs );\n argumentCurrent_ += 4;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const RgbaColor& rhs )\n{\n CheckForAvailableArgumentSpace(4);\n\n *(--typeTagsCurrent_) = RGBA_COLOR_TYPE_TAG;\n FromUInt32( argumentCurrent_, rhs );\n argumentCurrent_ += 4;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const MidiMessage& rhs )\n{\n CheckForAvailableArgumentSpace(4);\n\n *(--typeTagsCurrent_) = MIDI_MESSAGE_TYPE_TAG;\n FromUInt32( argumentCurrent_, rhs );\n argumentCurrent_ += 4;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( int64 rhs )\n{\n CheckForAvailableArgumentSpace(8);\n\n *(--typeTagsCurrent_) = INT64_TYPE_TAG;\n FromInt64( argumentCurrent_, rhs );\n argumentCurrent_ += 8;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const TimeTag& rhs )\n{\n CheckForAvailableArgumentSpace(8);\n\n *(--typeTagsCurrent_) = TIME_TAG_TYPE_TAG;\n FromUInt64( argumentCurrent_, rhs );\n argumentCurrent_ += 8;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( double rhs )\n{\n CheckForAvailableArgumentSpace(8);\n\n *(--typeTagsCurrent_) = DOUBLE_TYPE_TAG;\n\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union{\n double f;\n char c[8];\n } u;\n\n u.f = rhs;\n\n argumentCurrent_[7] = u.c[0];\n argumentCurrent_[6] = u.c[1];\n argumentCurrent_[5] = u.c[2];\n argumentCurrent_[4] = u.c[3];\n argumentCurrent_[3] = u.c[4];\n argumentCurrent_[2] = u.c[5];\n argumentCurrent_[1] = u.c[6];\n argumentCurrent_[0] = u.c[7];\n#else\n *reinterpret_cast(argumentCurrent_) = rhs;\n#endif\n\n argumentCurrent_ += 8;\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const char *rhs )\n{\n CheckForAvailableArgumentSpace( RoundUp4(std::strlen(rhs) + 1) );\n\n *(--typeTagsCurrent_) = STRING_TYPE_TAG;\n std::strcpy( argumentCurrent_, rhs );\n std::size_t rhsLength = std::strlen(rhs);\n argumentCurrent_ += rhsLength + 1;\n\n // zero pad to 4-byte boundary\n std::size_t i = rhsLength + 1;\n while( i & 0x3 ){\n *argumentCurrent_++ = '\\0';\n ++i;\n }\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const Symbol& rhs )\n{\n CheckForAvailableArgumentSpace( RoundUp4(std::strlen(rhs) + 1) );\n\n *(--typeTagsCurrent_) = SYMBOL_TYPE_TAG;\n std::strcpy( argumentCurrent_, rhs );\n std::size_t rhsLength = std::strlen(rhs);\n argumentCurrent_ += rhsLength + 1;\n\n // zero pad to 4-byte boundary\n std::size_t i = rhsLength + 1;\n while( i & 0x3 ){\n *argumentCurrent_++ = '\\0';\n ++i;\n }\n\n return *this;\n}\n\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const Blob& rhs )\n{\n CheckForAvailableArgumentSpace( 4 + RoundUp4(rhs.size) );\n\n *(--typeTagsCurrent_) = BLOB_TYPE_TAG;\n FromUInt32( argumentCurrent_, rhs.size );\n argumentCurrent_ += 4;\n \n std::memcpy( argumentCurrent_, rhs.data, rhs.size );\n argumentCurrent_ += rhs.size;\n\n // zero pad to 4-byte boundary\n unsigned long i = rhs.size;\n while( i & 0x3 ){\n *argumentCurrent_++ = '\\0';\n ++i;\n }\n\n return *this;\n}\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const ArrayInitiator& rhs )\n{\n (void) rhs;\n CheckForAvailableArgumentSpace(0);\n\n *(--typeTagsCurrent_) = ARRAY_BEGIN_TYPE_TAG;\n\n return *this;\n}\n\nOutboundPacketStream& OutboundPacketStream::operator<<( const ArrayTerminator& rhs )\n{\n (void) rhs;\n CheckForAvailableArgumentSpace(0);\n\n *(--typeTagsCurrent_) = ARRAY_END_TYPE_TAG;\n\n return *this;\n}\n\n} // namespace osc\n\n\n" }, { "path": "lib/oscpack/osc/OscOutboundPacketStream.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_OSCOUTBOUNDPACKETSTREAM_H\n#define INCLUDED_OSCPACK_OSCOUTBOUNDPACKETSTREAM_H\n\n#include // size_t\n\n#include \"OscTypes.h\"\n#include \"OscException.h\"\n\n\nnamespace osc{\n\nclass OutOfBufferMemoryException : public Exception{\npublic:\n OutOfBufferMemoryException( const char *w=\"out of buffer memory\" )\n : Exception( w ) {}\n};\n\nclass BundleNotInProgressException : public Exception{\npublic:\n BundleNotInProgressException(\n const char *w=\"call to EndBundle when bundle is not in progress\" )\n : Exception( w ) {}\n};\n\nclass MessageInProgressException : public Exception{\npublic:\n MessageInProgressException(\n const char *w=\"opening or closing bundle or message while message is in progress\" )\n : Exception( w ) {}\n};\n\nclass MessageNotInProgressException : public Exception{\npublic:\n MessageNotInProgressException(\n const char *w=\"call to EndMessage when message is not in progress\" )\n : Exception( w ) {}\n};\n\n\nclass OutboundPacketStream{\npublic:\n\tOutboundPacketStream( char *buffer, std::size_t capacity );\n\t~OutboundPacketStream();\n\n void Clear();\n\n std::size_t Capacity() const;\n\n // invariant: size() is valid even while building a message.\n std::size_t Size() const;\n\n const char *Data() const;\n\n // indicates that all messages have been closed with a matching EndMessage\n // and all bundles have been closed with a matching EndBundle\n bool IsReady() const;\n\n bool IsMessageInProgress() const;\n bool IsBundleInProgress() const;\n\n OutboundPacketStream& operator<<( const BundleInitiator& rhs );\n OutboundPacketStream& operator<<( const BundleTerminator& rhs );\n \n OutboundPacketStream& operator<<( const BeginMessage& rhs );\n OutboundPacketStream& operator<<( const MessageTerminator& rhs );\n\n OutboundPacketStream& operator<<( bool rhs );\n OutboundPacketStream& operator<<( const NilType& rhs );\n OutboundPacketStream& operator<<( const InfinitumType& rhs );\n OutboundPacketStream& operator<<( int32 rhs );\n\n#if !(defined(__x86_64__) || defined(_M_X64) || defined(_LP64))\n OutboundPacketStream& operator<<( int rhs )\n { *this << (int32)rhs; return *this; }\n#endif\n\n OutboundPacketStream& operator<<( float rhs );\n OutboundPacketStream& operator<<( char rhs );\n OutboundPacketStream& operator<<( const RgbaColor& rhs );\n OutboundPacketStream& operator<<( const MidiMessage& rhs );\n OutboundPacketStream& operator<<( int64 rhs );\n OutboundPacketStream& operator<<( const TimeTag& rhs );\n OutboundPacketStream& operator<<( double rhs );\n OutboundPacketStream& operator<<( const char* rhs );\n OutboundPacketStream& operator<<( const Symbol& rhs );\n OutboundPacketStream& operator<<( const Blob& rhs );\n\n OutboundPacketStream& operator<<( const ArrayInitiator& rhs );\n OutboundPacketStream& operator<<( const ArrayTerminator& rhs );\n\nprivate:\n\n char *BeginElement( char *beginPtr );\n void EndElement( char *endPtr );\n\n bool ElementSizeSlotRequired() const;\n void CheckForAvailableBundleSpace();\n void CheckForAvailableMessageSpace( const char *addressPattern );\n void CheckForAvailableArgumentSpace( std::size_t argumentLength );\n\n char *data_;\n char *end_;\n\n char *typeTagsCurrent_; // stored in reverse order\n char *messageCursor_;\n char *argumentCurrent_;\n\n // elementSizePtr_ has two special values: 0 indicates that a bundle\n // isn't open, and elementSizePtr_==data_ indicates that a bundle is\n // open but that it doesn't have a size slot (ie the outermost bundle)\n uint32 *elementSizePtr_;\n\n bool messageIsInProgress_;\n};\n\n} // namespace osc\n\n#endif /* INCLUDED_OSCPACK_OSCOUTBOUNDPACKETSTREAM_H */\n" }, { "path": "lib/oscpack/osc/OscPacketListener.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_OSCPACKETLISTENER_H\n#define INCLUDED_OSCPACK_OSCPACKETLISTENER_H\n\n#include \"../ip/PacketListener.h\"\n#include \"OscReceivedElements.h\"\n\nnamespace osc\n{\n\nclass OscPacketListener : public PacketListener\n{\nprotected:\n virtual void ProcessBundle(const osc::ReceivedBundle& b,\n const IpEndpointName& remoteEndpoint)\n {\n // ignore bundle time tag for now\n\n for (ReceivedBundle::const_iterator i = b.ElementsBegin();\n i != b.ElementsEnd(); ++i)\n {\n if (i->IsBundle())\n ProcessBundle(ReceivedBundle(*i), remoteEndpoint);\n else\n ProcessMessage(ReceivedMessage(*i), remoteEndpoint);\n }\n }\n\n virtual void ProcessMessage(const osc::ReceivedMessage& m,\n const IpEndpointName& remoteEndpoint)\n = 0;\n\npublic:\n void ProcessPacket(const char* data, int size,\n const IpEndpointName& remoteEndpoint) override\n {\n osc::ReceivedPacket p(data, size);\n if (p.IsBundle())\n ProcessBundle(ReceivedBundle(p), remoteEndpoint);\n else\n ProcessMessage(ReceivedMessage(p), remoteEndpoint);\n }\n};\n\n} // namespace osc\n\n#endif /* INCLUDED_OSCPACK_OSCPACKETLISTENER_H */\n" }, { "path": "lib/oscpack/osc/OscPrintReceivedElements.cpp", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#include \"OscPrintReceivedElements.h\"\n\n#include \n#include \n#include \n#include \n\n#if defined(__BORLANDC__) // workaround for BCB4 release build intrinsics bug\nnamespace std {\nusing ::__strcpy__; // avoid error: E2316 '__strcpy__' is not a member of 'std'.\n}\n#endif\n\nnamespace osc{\n\n\nstd::ostream& operator<<( std::ostream & os,\n const ReceivedMessageArgument& arg )\n{\n switch( arg.TypeTag() ){\n case TRUE_TYPE_TAG:\n os << \"bool:true\";\n break;\n \n case FALSE_TYPE_TAG:\n os << \"bool:false\";\n break;\n\n case NIL_TYPE_TAG:\n os << \"(Nil)\";\n break;\n\n case INFINITUM_TYPE_TAG:\n os << \"(Infinitum)\";\n break;\n\n case INT32_TYPE_TAG:\n os << \"int32:\" << arg.AsInt32Unchecked();\n break;\n\n case FLOAT_TYPE_TAG:\n os << \"float32:\" << arg.AsFloatUnchecked();\n break;\n\n case CHAR_TYPE_TAG:\n {\n char s[2] = {0};\n s[0] = arg.AsCharUnchecked();\n os << \"char:'\" << s << \"'\";\n }\n break;\n\n case RGBA_COLOR_TYPE_TAG:\n {\n uint32 color = arg.AsRgbaColorUnchecked();\n \n os << \"RGBA:0x\"\n << std::hex << std::setfill('0')\n << std::setw(2) << (int)((color>>24) & 0xFF)\n << std::setw(2) << (int)((color>>16) & 0xFF)\n << std::setw(2) << (int)((color>>8) & 0xFF)\n << std::setw(2) << (int)(color & 0xFF)\n << std::setfill(' ');\n os.unsetf(std::ios::basefield);\n }\n break;\n\n case MIDI_MESSAGE_TYPE_TAG:\n {\n uint32 m = arg.AsMidiMessageUnchecked();\n os << \"midi (port, status, data1, data2):<<\"\n << std::hex << std::setfill('0')\n << \"0x\" << std::setw(2) << (int)((m>>24) & 0xFF)\n << \" 0x\" << std::setw(2) << (int)((m>>16) & 0xFF)\n << \" 0x\" << std::setw(2) << (int)((m>>8) & 0xFF)\n << \" 0x\" << std::setw(2) << (int)(m & 0xFF)\n << std::setfill(' ') << \">>\";\n os.unsetf(std::ios::basefield);\n }\n break;\n\t\t\t\t\n case INT64_TYPE_TAG:\n os << \"int64:\" << arg.AsInt64Unchecked();\n break;\n\n case TIME_TAG_TYPE_TAG:\n {\n os << \"OSC-timetag:\" << arg.AsTimeTagUnchecked() << \" \";\n\n std::time_t t =\n (unsigned long)( arg.AsTimeTagUnchecked() >> 32 );\n\n const char *timeString = std::ctime( &t );\n size_t len = std::strlen( timeString );\n\n // -1 to omit trailing newline from string returned by ctime()\n if( len > 1 )\n os.write( timeString, len - 1 );\n }\n break;\n \n case DOUBLE_TYPE_TAG:\n os << \"double:\" << arg.AsDoubleUnchecked();\n break;\n\n case STRING_TYPE_TAG:\n os << \"OSC-string:`\" << arg.AsStringUnchecked() << \"'\";\n break;\n \n case SYMBOL_TYPE_TAG: \n os << \"OSC-string (symbol):`\" << arg.AsSymbolUnchecked() << \"'\";\n break;\n\n case BLOB_TYPE_TAG:\n {\n const void *data;\n osc_bundle_element_size_t size;\n arg.AsBlobUnchecked( data, size );\n os << \"OSC-blob:<<\" << std::hex << std::setfill('0');\n unsigned char *p = (unsigned char*)data;\n for( osc_bundle_element_size_t i = 0; i < size; ++i ){\n os << \"0x\" << std::setw(2) << int(p[i]);\n if( i != size-1 )\n os << ' ';\n }\n os.unsetf(std::ios::basefield);\n os << \">>\" << std::setfill(' ');\n }\n break;\n\n case ARRAY_BEGIN_TYPE_TAG:\n os << \"[\";\n break;\n\n case ARRAY_END_TYPE_TAG:\n os << \"]\";\n break;\n\n default:\n os << \"unknown\";\n }\n\n return os;\n}\n\n\nstd::ostream& operator<<( std::ostream & os, const ReceivedMessage& m )\n{\n os << \"[\";\n if( m.AddressPatternIsUInt32() )\n os << m.AddressPatternAsUInt32();\n else\n os << m.AddressPattern();\n \n bool first = true;\n for( ReceivedMessage::const_iterator i = m.ArgumentsBegin();\n i != m.ArgumentsEnd(); ++i ){\n if( first ){\n os << \" \";\n first = false;\n }else{\n os << \", \";\n }\n\n os << *i;\n }\n\n os << \"]\";\n\n return os;\n}\n\n\nstd::ostream& operator<<( std::ostream & os, const ReceivedBundle& b )\n{\n static int indent = 0;\n\n for( int j=0; j < indent; ++j )\n os << \" \";\n os << \"{ ( \";\n if( b.TimeTag() == 1 )\n os << \"immediate\";\n else\n os << b.TimeTag();\n os << \" )\\n\";\n\n ++indent;\n \n for( ReceivedBundle::const_iterator i = b.ElementsBegin();\n i != b.ElementsEnd(); ++i ){\n if( i->IsBundle() ){\n ReceivedBundle b(*i);\n os << b << \"\\n\";\n }else{\n ReceivedMessage m(*i);\n for( int j=0; j < indent; ++j )\n os << \" \";\n os << m << \"\\n\";\n }\n }\n\n --indent;\n\n for( int j=0; j < indent; ++j )\n os << \" \";\n os << \"}\";\n\n return os;\n}\n\n\nstd::ostream& operator<<( std::ostream & os, const ReceivedPacket& p )\n{\n if( p.IsBundle() ){\n ReceivedBundle b(p);\n os << b << \"\\n\";\n }else{\n ReceivedMessage m(p);\n os << m << \"\\n\";\n }\n\n return os;\n}\n\n} // namespace osc\n" }, { "path": "lib/oscpack/osc/OscPrintReceivedElements.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_OSCPRINTRECEIVEDELEMENTS_H\n#define INCLUDED_OSCPACK_OSCPRINTRECEIVEDELEMENTS_H\n\n#include \n\n#include \"OscReceivedElements.h\"\n\n\nnamespace osc{\n\nstd::ostream& operator<<( std::ostream & os, const ReceivedPacket& p );\nstd::ostream& operator<<( std::ostream & os, const ReceivedMessageArgument& arg );\nstd::ostream& operator<<( std::ostream & os, const ReceivedMessage& m );\nstd::ostream& operator<<( std::ostream & os, const ReceivedBundle& b );\n\n} // namespace osc\n\n#endif /* INCLUDED_OSCPACK_OSCPRINTRECEIVEDELEMENTS_H */\n" }, { "path": "lib/oscpack/osc/OscReceivedElements.cpp", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#include \"OscReceivedElements.h\"\n\n#include \"OscHostEndianness.h\"\n\n#include // ptrdiff_t\n\nnamespace osc\n{\n\n// return the first 4 byte boundary after the end of a str4\n// be careful about calling this version if you don't know whether\n// the string is terminated correctly.\nstatic inline const char* FindStr4End(const char* p)\n{\n if (p[0] == '\\0') // special case for SuperCollider integer address pattern\n return p + 4;\n\n p += 3;\n\n while (*p)\n p += 4;\n\n return p + 1;\n}\n\n// return the first 4 byte boundary after the end of a str4\n// returns 0 if p == end or if the string is unterminated\nstatic inline const char* FindStr4End(const char* p, const char* end)\n{\n if (p >= end)\n return 0;\n\n if (p[0] == '\\0') // special case for SuperCollider integer address pattern\n return p + 4;\n\n p += 3;\n end -= 1;\n\n while (p < end && *p)\n p += 4;\n\n if (*p)\n return 0;\n else\n return p + 1;\n}\n\n// round up to the next highest multiple of 4. unless x is already a multiple of 4\nstatic inline uint32 RoundUp4(uint32 x)\n{\n return (x + 3) & ~((uint32)0x03);\n}\n\nstatic inline int32 ToInt32(const char* p)\n{\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union {\n osc::int32 i;\n char c[4];\n } u;\n\n u.c[0] = p[3];\n u.c[1] = p[2];\n u.c[2] = p[1];\n u.c[3] = p[0];\n\n return u.i;\n#else\n return *(int32*)p;\n#endif\n}\n\nstatic inline uint32 ToUInt32(const char* p)\n{\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union {\n osc::uint32 i;\n char c[4];\n } u;\n\n u.c[0] = p[3];\n u.c[1] = p[2];\n u.c[2] = p[1];\n u.c[3] = p[0];\n\n return u.i;\n#else\n return *(uint32*)p;\n#endif\n}\n\nstatic inline int64 ToInt64(const char* p)\n{\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union {\n osc::int64 i;\n char c[8];\n } u;\n\n u.c[0] = p[7];\n u.c[1] = p[6];\n u.c[2] = p[5];\n u.c[3] = p[4];\n u.c[4] = p[3];\n u.c[5] = p[2];\n u.c[6] = p[1];\n u.c[7] = p[0];\n\n return u.i;\n#else\n return *(int64*)p;\n#endif\n}\n\nstatic inline uint64 ToUInt64(const char* p)\n{\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union {\n osc::uint64 i;\n char c[8];\n } u;\n\n u.c[0] = p[7];\n u.c[1] = p[6];\n u.c[2] = p[5];\n u.c[3] = p[4];\n u.c[4] = p[3];\n u.c[5] = p[2];\n u.c[6] = p[1];\n u.c[7] = p[0];\n\n return u.i;\n#else\n return *(uint64*)p;\n#endif\n}\n\n//------------------------------------------------------------------------------\n\nbool ReceivedPacket::IsBundle() const\n{\n return (Size() > 0 && Contents()[0] == '#');\n}\n\n//------------------------------------------------------------------------------\n\nbool ReceivedBundleElement::IsBundle() const\n{\n return (Size() > 0 && Contents()[0] == '#');\n}\n\nosc_bundle_element_size_t ReceivedBundleElement::Size() const\n{\n return ToInt32(sizePtr_);\n}\n\n//------------------------------------------------------------------------------\n\nbool ReceivedMessageArgument::AsBool() const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == TRUE_TYPE_TAG)\n return true;\n else if (*typeTagPtr_ == FALSE_TYPE_TAG)\n return false;\n else\n throw WrongArgumentTypeException();\n}\n\nbool ReceivedMessageArgument::AsBoolUnchecked() const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == TRUE_TYPE_TAG)\n return true;\n else\n return false;\n}\n\nint32 ReceivedMessageArgument::AsInt32() const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == INT32_TYPE_TAG)\n return AsInt32Unchecked();\n else\n throw WrongArgumentTypeException();\n}\n\nint32 ReceivedMessageArgument::AsInt32Unchecked() const\n{\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union {\n osc::int32 i;\n char c[4];\n } u;\n\n u.c[0] = argumentPtr_[3];\n u.c[1] = argumentPtr_[2];\n u.c[2] = argumentPtr_[1];\n u.c[3] = argumentPtr_[0];\n\n return u.i;\n#else\n return *(int32*)argument_;\n#endif\n}\n\nfloat ReceivedMessageArgument::AsFloat() const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == FLOAT_TYPE_TAG)\n return AsFloatUnchecked();\n else\n throw WrongArgumentTypeException();\n}\n\nfloat ReceivedMessageArgument::AsFloatUnchecked() const\n{\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union {\n float f;\n char c[4];\n } u;\n\n u.c[0] = argumentPtr_[3];\n u.c[1] = argumentPtr_[2];\n u.c[2] = argumentPtr_[1];\n u.c[3] = argumentPtr_[0];\n\n return u.f;\n#else\n return *(float*)argument_;\n#endif\n}\n\nchar ReceivedMessageArgument::AsChar() const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == CHAR_TYPE_TAG)\n return AsCharUnchecked();\n else\n throw WrongArgumentTypeException();\n}\n\nchar ReceivedMessageArgument::AsCharUnchecked() const\n{\n return (char)ToInt32(argumentPtr_);\n}\n\nuint32 ReceivedMessageArgument::AsRgbaColor() const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == RGBA_COLOR_TYPE_TAG)\n return AsRgbaColorUnchecked();\n else\n throw WrongArgumentTypeException();\n}\n\nuint32 ReceivedMessageArgument::AsRgbaColorUnchecked() const\n{\n return ToUInt32(argumentPtr_);\n}\n\nuint32 ReceivedMessageArgument::AsMidiMessage() const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == MIDI_MESSAGE_TYPE_TAG)\n return AsMidiMessageUnchecked();\n else\n throw WrongArgumentTypeException();\n}\n\nuint32 ReceivedMessageArgument::AsMidiMessageUnchecked() const\n{\n return ToUInt32(argumentPtr_);\n}\n\nint64 ReceivedMessageArgument::AsInt64() const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == INT64_TYPE_TAG)\n return AsInt64Unchecked();\n else\n throw WrongArgumentTypeException();\n}\n\nint64 ReceivedMessageArgument::AsInt64Unchecked() const\n{\n return ToInt64(argumentPtr_);\n}\n\nuint64 ReceivedMessageArgument::AsTimeTag() const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == TIME_TAG_TYPE_TAG)\n return AsTimeTagUnchecked();\n else\n throw WrongArgumentTypeException();\n}\n\nuint64 ReceivedMessageArgument::AsTimeTagUnchecked() const\n{\n return ToUInt64(argumentPtr_);\n}\n\ndouble ReceivedMessageArgument::AsDouble() const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == DOUBLE_TYPE_TAG)\n return AsDoubleUnchecked();\n else\n throw WrongArgumentTypeException();\n}\n\ndouble ReceivedMessageArgument::AsDoubleUnchecked() const\n{\n#ifdef OSC_HOST_LITTLE_ENDIAN\n union {\n double d;\n char c[8];\n } u;\n\n u.c[0] = argumentPtr_[7];\n u.c[1] = argumentPtr_[6];\n u.c[2] = argumentPtr_[5];\n u.c[3] = argumentPtr_[4];\n u.c[4] = argumentPtr_[3];\n u.c[5] = argumentPtr_[2];\n u.c[6] = argumentPtr_[1];\n u.c[7] = argumentPtr_[0];\n\n return u.d;\n#else\n return *(double*)argument_;\n#endif\n}\n\nconst char* ReceivedMessageArgument::AsString() const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == STRING_TYPE_TAG)\n return argumentPtr_;\n else\n throw WrongArgumentTypeException();\n}\n\nconst char* ReceivedMessageArgument::AsSymbol() const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == SYMBOL_TYPE_TAG)\n return argumentPtr_;\n else\n throw WrongArgumentTypeException();\n}\n\nvoid ReceivedMessageArgument::AsBlob(const void*& data, osc_bundle_element_size_t& size) const\n{\n if (!typeTagPtr_)\n throw MissingArgumentException();\n else if (*typeTagPtr_ == BLOB_TYPE_TAG)\n AsBlobUnchecked(data, size);\n else\n throw WrongArgumentTypeException();\n}\n\nvoid ReceivedMessageArgument::AsBlobUnchecked(const void*& data, osc_bundle_element_size_t& size) const\n{\n // read blob size as an unsigned int then validate\n osc_bundle_element_size_t sizeResult = (osc_bundle_element_size_t)ToUInt32(argumentPtr_);\n if (!IsValidElementSizeValue(sizeResult))\n throw MalformedMessageException(\"invalid blob size\");\n\n size = sizeResult;\n data = (void*)(argumentPtr_ + osc::OSC_SIZEOF_INT32);\n}\n\nstd::size_t ReceivedMessageArgument::ComputeArrayItemCount() const\n{\n // it is only valid to call ComputeArrayItemCount when the argument is the array start marker\n if (!IsArrayBegin())\n throw WrongArgumentTypeException();\n\n std::size_t result = 0;\n unsigned int level = 0;\n const char* typeTag = typeTagPtr_ + 1;\n\n // iterate through all type tags. note that ReceivedMessage::Init\n // has already checked that the message is well formed.\n while (*typeTag)\n {\n switch (*typeTag++)\n {\n case ARRAY_BEGIN_TYPE_TAG:\n level += 1;\n break;\n\n case ARRAY_END_TYPE_TAG:\n if (level == 0)\n return result;\n level -= 1;\n break;\n\n default:\n if (level == 0) // only count items at level 0\n ++result;\n }\n }\n\n return result;\n}\n\n//------------------------------------------------------------------------------\n\nvoid ReceivedMessageArgumentIterator::Advance()\n{\n if (!value_.typeTagPtr_)\n return;\n\n switch (*value_.typeTagPtr_++)\n {\n case '\\0':\n // don't advance past end\n --value_.typeTagPtr_;\n break;\n\n case TRUE_TYPE_TAG:\n case FALSE_TYPE_TAG:\n case NIL_TYPE_TAG:\n case INFINITUM_TYPE_TAG:\n\n // zero length\n break;\n\n case INT32_TYPE_TAG:\n case FLOAT_TYPE_TAG:\n case CHAR_TYPE_TAG:\n case RGBA_COLOR_TYPE_TAG:\n case MIDI_MESSAGE_TYPE_TAG:\n\n value_.argumentPtr_ += 4;\n break;\n\n case INT64_TYPE_TAG:\n case TIME_TAG_TYPE_TAG:\n case DOUBLE_TYPE_TAG:\n\n value_.argumentPtr_ += 8;\n break;\n\n case STRING_TYPE_TAG:\n case SYMBOL_TYPE_TAG:\n\n // we use the unsafe function FindStr4End(char*) here because all of\n // the arguments have already been validated in\n // ReceivedMessage::Init() below.\n\n value_.argumentPtr_ = FindStr4End(value_.argumentPtr_);\n break;\n\n case BLOB_TYPE_TAG:\n {\n // treat blob size as an unsigned int for the purposes of this calculation\n uint32 blobSize = ToUInt32(value_.argumentPtr_);\n value_.argumentPtr_ = value_.argumentPtr_ + osc::OSC_SIZEOF_INT32 + RoundUp4(blobSize);\n }\n break;\n\n case ARRAY_BEGIN_TYPE_TAG:\n case ARRAY_END_TYPE_TAG:\n\n // [ Indicates the beginning of an array. The tags following are for\n // data in the Array until a close brace tag is reached.\n // ] Indicates the end of an array.\n\n // zero length, don't advance argument ptr\n break;\n\n default: // unknown type tag\n // don't advance\n --value_.typeTagPtr_;\n break;\n }\n}\n\n//------------------------------------------------------------------------------\n\nReceivedMessage::ReceivedMessage(const ReceivedPacket& packet)\n : addressPattern_(packet.Contents())\n{\n Init(packet.Contents(), packet.Size());\n}\n\nReceivedMessage::ReceivedMessage(const ReceivedBundleElement& bundleElement)\n : addressPattern_(bundleElement.Contents())\n{\n Init(bundleElement.Contents(), bundleElement.Size());\n}\n\nbool ReceivedMessage::AddressPatternIsUInt32() const\n{\n return (addressPattern_[0] == '\\0');\n}\n\nuint32 ReceivedMessage::AddressPatternAsUInt32() const\n{\n return ToUInt32(addressPattern_);\n}\n\nvoid ReceivedMessage::Init(const char* message, osc_bundle_element_size_t size)\n{\n if (!IsValidElementSizeValue(size))\n throw MalformedMessageException(\"invalid message size\");\n\n if (size == 0)\n throw MalformedMessageException(\"zero length messages not permitted\");\n\n if (!IsMultipleOf4(size))\n throw MalformedMessageException(\"message size must be multiple of four\");\n\n const char* end = message + size;\n\n typeTagsBegin_ = FindStr4End(addressPattern_, end);\n if (typeTagsBegin_ == 0)\n {\n // address pattern was not terminated before end\n throw MalformedMessageException(\"unterminated address pattern\");\n }\n\n if (typeTagsBegin_ == end)\n {\n // message consists of only the address pattern - no arguments or type tags.\n typeTagsBegin_ = 0;\n typeTagsEnd_ = 0;\n arguments_ = 0;\n }\n else\n {\n if (*typeTagsBegin_ != ',')\n throw MalformedMessageException(\"type tags not present\");\n\n if (*(typeTagsBegin_ + 1) == '\\0')\n {\n // zero length type tags\n typeTagsBegin_ = 0;\n typeTagsEnd_ = 0;\n arguments_ = 0;\n }\n else\n {\n // check that all arguments are present and well formed\n\n arguments_ = FindStr4End(typeTagsBegin_, end);\n if (arguments_ == 0)\n {\n throw MalformedMessageException(\"type tags were not terminated before end of message\");\n }\n\n ++typeTagsBegin_; // advance past initial ','\n\n const char* typeTag = typeTagsBegin_;\n const char* argument = arguments_;\n unsigned int arrayLevel = 0;\n\n do\n {\n switch (*typeTag)\n {\n case TRUE_TYPE_TAG:\n case FALSE_TYPE_TAG:\n case NIL_TYPE_TAG:\n case INFINITUM_TYPE_TAG:\n // zero length\n break;\n\n // [ Indicates the beginning of an array. The tags following are for\n // data in the Array until a close brace tag is reached.\n // ] Indicates the end of an array.\n case ARRAY_BEGIN_TYPE_TAG:\n ++arrayLevel;\n // (zero length argument data)\n break;\n\n case ARRAY_END_TYPE_TAG:\n --arrayLevel;\n // (zero length argument data)\n break;\n\n case INT32_TYPE_TAG:\n case FLOAT_TYPE_TAG:\n case CHAR_TYPE_TAG:\n case RGBA_COLOR_TYPE_TAG:\n case MIDI_MESSAGE_TYPE_TAG:\n\n if (argument == end)\n throw MalformedMessageException(\"arguments exceed message size\");\n argument += 4;\n if (argument > end)\n throw MalformedMessageException(\"arguments exceed message size\");\n break;\n\n case INT64_TYPE_TAG:\n case TIME_TAG_TYPE_TAG:\n case DOUBLE_TYPE_TAG:\n\n if (argument == end)\n throw MalformedMessageException(\"arguments exceed message size\");\n argument += 8;\n if (argument > end)\n throw MalformedMessageException(\"arguments exceed message size\");\n break;\n\n case STRING_TYPE_TAG:\n case SYMBOL_TYPE_TAG:\n\n if (argument == end)\n throw MalformedMessageException(\"arguments exceed message size\");\n argument = FindStr4End(argument, end);\n if (argument == 0)\n throw MalformedMessageException(\"unterminated string argument\");\n break;\n\n case BLOB_TYPE_TAG:\n {\n if (argument + osc::OSC_SIZEOF_INT32 > end)\n MalformedMessageException(\"arguments exceed message size\");\n\n // treat blob size as an unsigned int for the purposes of this calculation\n uint32 blobSize = ToUInt32(argument);\n argument = argument + osc::OSC_SIZEOF_INT32 + RoundUp4(blobSize);\n if (argument > end)\n MalformedMessageException(\"arguments exceed message size\");\n }\n break;\n\n default:\n throw MalformedMessageException(\"unknown type tag\");\n }\n\n } while (*++typeTag != '\\0');\n typeTagsEnd_ = typeTag;\n\n if (arrayLevel != 0)\n throw MalformedMessageException(\"array was not terminated before end of message (expected ']' end of array tag)\");\n }\n\n // These invariants should be guaranteed by the above code.\n // we depend on them in the implementation of ArgumentCount()\n#ifndef NDEBUG\n std::ptrdiff_t argumentCount = typeTagsEnd_ - typeTagsBegin_;\n assert(argumentCount >= 0);\n assert(argumentCount <= OSC_INT32_MAX);\n#endif\n }\n}\n\n//------------------------------------------------------------------------------\n\nReceivedBundle::ReceivedBundle(const ReceivedPacket& packet)\n : elementCount_(0)\n{\n Init(packet.Contents(), packet.Size());\n}\n\nReceivedBundle::ReceivedBundle(const ReceivedBundleElement& bundleElement)\n : elementCount_(0)\n{\n Init(bundleElement.Contents(), bundleElement.Size());\n}\n\nvoid ReceivedBundle::Init(const char* bundle, osc_bundle_element_size_t size)\n{\n\n if (!IsValidElementSizeValue(size))\n throw MalformedBundleException(\"invalid bundle size\");\n\n if (size < 16)\n throw MalformedBundleException(\"packet too short for bundle\");\n\n if (!IsMultipleOf4(size))\n throw MalformedBundleException(\"bundle size must be multiple of four\");\n\n if (bundle[0] != '#'\n || bundle[1] != 'b'\n || bundle[2] != 'u'\n || bundle[3] != 'n'\n || bundle[4] != 'd'\n || bundle[5] != 'l'\n || bundle[6] != 'e'\n || bundle[7] != '\\0')\n throw MalformedBundleException(\"bad bundle address pattern\");\n\n end_ = bundle + size;\n\n timeTag_ = bundle + 8;\n\n const char* p = timeTag_ + 8;\n\n while (p < end_)\n {\n if (p + osc::OSC_SIZEOF_INT32 > end_)\n throw MalformedBundleException(\"packet too short for elementSize\");\n\n // treat element size as an unsigned int for the purposes of this calculation\n uint32 elementSize = ToUInt32(p);\n if ((elementSize & ((uint32)0x03)) != 0)\n throw MalformedBundleException(\"bundle element size must be multiple of four\");\n\n p += osc::OSC_SIZEOF_INT32 + elementSize;\n if (p > end_)\n throw MalformedBundleException(\"packet too short for bundle element\");\n\n ++elementCount_;\n }\n\n if (p != end_)\n throw MalformedBundleException(\"bundle contents \");\n}\n\nuint64 ReceivedBundle::TimeTag() const\n{\n return ToUInt64(timeTag_);\n}\n\n} // namespace osc\n" }, { "path": "lib/oscpack/osc/OscReceivedElements.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_OSCRECEIVEDELEMENTS_H\n#define INCLUDED_OSCPACK_OSCRECEIVEDELEMENTS_H\n\n#include \n#include \n#include // size_t\n\n#include \"OscTypes.h\"\n#include \"OscException.h\"\n\n\nnamespace osc{\n\n\nclass MalformedPacketException : public Exception{\npublic:\n MalformedPacketException( const char *w=\"malformed packet\" )\n : Exception( w ) {}\n};\n\nclass MalformedMessageException : public Exception{\npublic:\n MalformedMessageException( const char *w=\"malformed message\" )\n : Exception( w ) {}\n};\n\nclass MalformedBundleException : public Exception{\npublic:\n MalformedBundleException( const char *w=\"malformed bundle\" )\n : Exception( w ) {}\n};\n\nclass WrongArgumentTypeException : public Exception{\npublic:\n WrongArgumentTypeException( const char *w=\"wrong argument type\" )\n : Exception( w ) {}\n};\n\nclass MissingArgumentException : public Exception{\npublic:\n MissingArgumentException( const char *w=\"missing argument\" )\n : Exception( w ) {}\n};\n\nclass ExcessArgumentException : public Exception{\npublic:\n ExcessArgumentException( const char *w=\"too many arguments\" )\n : Exception( w ) {}\n};\n\n\nclass ReceivedPacket{\npublic:\n // Although the OSC spec is not entirely clear on this, we only support\n // packets up to 0x7FFFFFFC bytes long (the maximum 4-byte aligned value\n // representable by an int32). An exception will be raised if you pass a \n // larger value to the ReceivedPacket() constructor.\n\n ReceivedPacket( const char *contents, osc_bundle_element_size_t size )\n : contents_( contents )\n , size_( ValidateSize(size) ) {}\n\n ReceivedPacket( const char *contents, std::size_t size )\n : contents_( contents )\n , size_( ValidateSize( (osc_bundle_element_size_t)size ) ) {}\n\n#if !(defined(__x86_64__) || defined(_M_X64) || defined(_LP64))\n ReceivedPacket( const char *contents, int size )\n : contents_( contents )\n , size_( ValidateSize( (osc_bundle_element_size_t)size ) ) {}\n#endif\n\n bool IsMessage() const { return !IsBundle(); }\n bool IsBundle() const;\n\n osc_bundle_element_size_t Size() const { return size_; }\n const char *Contents() const { return contents_; }\n\nprivate:\n const char *contents_;\n osc_bundle_element_size_t size_;\n\n static osc_bundle_element_size_t ValidateSize( osc_bundle_element_size_t size )\n {\n // sanity check integer types declared in OscTypes.h \n // you'll need to fix OscTypes.h if any of these asserts fail\n assert( sizeof(osc::int32) == 4 );\n assert( sizeof(osc::uint32) == 4 );\n assert( sizeof(osc::int64) == 8 );\n assert( sizeof(osc::uint64) == 8 );\n\n if( !IsValidElementSizeValue(size) )\n throw MalformedPacketException( \"invalid packet size\" );\n\n if( size == 0 )\n throw MalformedPacketException( \"zero length elements not permitted\" );\n\n if( !IsMultipleOf4(size) )\n throw MalformedPacketException( \"element size must be multiple of four\" );\n\n return size;\n }\n};\n\n\nclass ReceivedBundleElement{\npublic:\n ReceivedBundleElement( const char *sizePtr )\n : sizePtr_( sizePtr ) {}\n\n friend class ReceivedBundleElementIterator;\n\n bool IsMessage() const { return !IsBundle(); }\n bool IsBundle() const;\n\n osc_bundle_element_size_t Size() const;\n const char *Contents() const { return sizePtr_ + osc::OSC_SIZEOF_INT32; }\n\nprivate:\n const char *sizePtr_;\n};\n\n\nclass ReceivedBundleElementIterator{\npublic:\n\tReceivedBundleElementIterator( const char *sizePtr )\n : value_( sizePtr ) {}\n\n\tReceivedBundleElementIterator operator++()\n\t{\n Advance();\n return *this;\n\t}\n\n ReceivedBundleElementIterator operator++(int)\n {\n ReceivedBundleElementIterator old( *this );\n Advance();\n return old;\n }\n\n\tconst ReceivedBundleElement& operator*() const { return value_; }\n\n const ReceivedBundleElement* operator->() const { return &value_; }\n\n\tfriend bool operator==(const ReceivedBundleElementIterator& lhs,\n const ReceivedBundleElementIterator& rhs );\n\nprivate:\n\tReceivedBundleElement value_;\n\n\tvoid Advance() { value_.sizePtr_ = value_.Contents() + value_.Size(); }\n\n bool IsEqualTo( const ReceivedBundleElementIterator& rhs ) const\n {\n return value_.sizePtr_ == rhs.value_.sizePtr_;\n }\n};\n\ninline bool operator==(const ReceivedBundleElementIterator& lhs,\n const ReceivedBundleElementIterator& rhs )\n{\t\n\treturn lhs.IsEqualTo( rhs );\n}\n\ninline bool operator!=(const ReceivedBundleElementIterator& lhs,\n const ReceivedBundleElementIterator& rhs )\n{\n\treturn !( lhs == rhs );\n}\n\n\nclass ReceivedMessageArgument{\npublic:\n\tReceivedMessageArgument( const char *typeTagPtr, const char *argumentPtr )\n\t\t: typeTagPtr_( typeTagPtr )\n\t\t, argumentPtr_( argumentPtr ) {}\n\n friend class ReceivedMessageArgumentIterator;\n \n\tchar TypeTag() const { return *typeTagPtr_; }\n\n // the unchecked methods below don't check whether the argument actually\n // is of the specified type. they should only be used if you've already\n // checked the type tag or the associated IsType() method.\n\n bool IsBool() const\n { return *typeTagPtr_ == TRUE_TYPE_TAG || *typeTagPtr_ == FALSE_TYPE_TAG; }\n bool AsBool() const;\n bool AsBoolUnchecked() const;\n\n bool IsNil() const { return *typeTagPtr_ == NIL_TYPE_TAG; }\n bool IsInfinitum() const { return *typeTagPtr_ == INFINITUM_TYPE_TAG; }\n\n bool IsInt32() const { return *typeTagPtr_ == INT32_TYPE_TAG; }\n int32 AsInt32() const;\n int32 AsInt32Unchecked() const;\n\n bool IsFloat() const { return *typeTagPtr_ == FLOAT_TYPE_TAG; }\n float AsFloat() const;\n float AsFloatUnchecked() const;\n\n bool IsChar() const { return *typeTagPtr_ == CHAR_TYPE_TAG; }\n char AsChar() const;\n char AsCharUnchecked() const;\n\n bool IsRgbaColor() const { return *typeTagPtr_ == RGBA_COLOR_TYPE_TAG; }\n uint32 AsRgbaColor() const;\n uint32 AsRgbaColorUnchecked() const;\n\n bool IsMidiMessage() const { return *typeTagPtr_ == MIDI_MESSAGE_TYPE_TAG; }\n uint32 AsMidiMessage() const;\n uint32 AsMidiMessageUnchecked() const;\n\n bool IsInt64() const { return *typeTagPtr_ == INT64_TYPE_TAG; }\n int64 AsInt64() const;\n int64 AsInt64Unchecked() const;\n\n bool IsTimeTag() const { return *typeTagPtr_ == TIME_TAG_TYPE_TAG; }\n uint64 AsTimeTag() const;\n uint64 AsTimeTagUnchecked() const;\n\n bool IsDouble() const { return *typeTagPtr_ == DOUBLE_TYPE_TAG; }\n double AsDouble() const;\n double AsDoubleUnchecked() const;\n\n bool IsString() const { return *typeTagPtr_ == STRING_TYPE_TAG; }\n const char* AsString() const;\n const char* AsStringUnchecked() const { return argumentPtr_; }\n\n bool IsSymbol() const { return *typeTagPtr_ == SYMBOL_TYPE_TAG; }\n const char* AsSymbol() const;\n const char* AsSymbolUnchecked() const { return argumentPtr_; }\n\n bool IsBlob() const { return *typeTagPtr_ == BLOB_TYPE_TAG; }\n void AsBlob( const void*& data, osc_bundle_element_size_t& size ) const;\n void AsBlobUnchecked( const void*& data, osc_bundle_element_size_t& size ) const;\n \n bool IsArrayBegin() const { return *typeTagPtr_ == ARRAY_BEGIN_TYPE_TAG; }\n bool IsArrayEnd() const { return *typeTagPtr_ == ARRAY_END_TYPE_TAG; }\n // Calculate the number of top-level items in the array. Nested arrays count as one item.\n // Only valid at array start. Will throw an exception if IsArrayStart() == false.\n std::size_t ComputeArrayItemCount() const;\n\nprivate:\n\tconst char *typeTagPtr_;\n\tconst char *argumentPtr_;\n};\n\n\nclass ReceivedMessageArgumentIterator{\npublic:\n\tReceivedMessageArgumentIterator( const char *typeTags, const char *arguments )\n : value_( typeTags, arguments ) {}\n\n\tReceivedMessageArgumentIterator operator++()\n\t{\n Advance();\n return *this;\n\t}\n\n ReceivedMessageArgumentIterator operator++(int)\n {\n ReceivedMessageArgumentIterator old( *this );\n Advance();\n return old;\n }\n\n\tconst ReceivedMessageArgument& operator*() const { return value_; }\n\n const ReceivedMessageArgument* operator->() const { return &value_; }\n\n\tfriend bool operator==(const ReceivedMessageArgumentIterator& lhs,\n const ReceivedMessageArgumentIterator& rhs );\n\nprivate:\n\tReceivedMessageArgument value_;\n\n\tvoid Advance();\n\n bool IsEqualTo( const ReceivedMessageArgumentIterator& rhs ) const\n {\n return value_.typeTagPtr_ == rhs.value_.typeTagPtr_;\n }\n};\n\ninline bool operator==(const ReceivedMessageArgumentIterator& lhs,\n const ReceivedMessageArgumentIterator& rhs )\n{\t\n\treturn lhs.IsEqualTo( rhs );\n}\n\ninline bool operator!=(const ReceivedMessageArgumentIterator& lhs,\n const ReceivedMessageArgumentIterator& rhs )\n{\t\n\treturn !( lhs == rhs );\n}\n\n\nclass ReceivedMessageArgumentStream{\n friend class ReceivedMessage;\n ReceivedMessageArgumentStream( const ReceivedMessageArgumentIterator& begin,\n const ReceivedMessageArgumentIterator& end )\n : p_( begin )\n , end_( end ) {}\n\n ReceivedMessageArgumentIterator p_, end_;\n \npublic:\n\n // end of stream\n bool Eos() const { return p_ == end_; }\n\n ReceivedMessageArgumentStream& operator>>( bool& rhs )\n {\n if( Eos() )\n throw MissingArgumentException();\n\n rhs = (*p_++).AsBool();\n return *this;\n }\n\n // not sure if it would be useful to stream Nil and Infinitum\n // for now it's not possible\n // same goes for array boundaries\n\n ReceivedMessageArgumentStream& operator>>( int32& rhs )\n {\n if( Eos() )\n throw MissingArgumentException();\n\n rhs = (*p_++).AsInt32();\n return *this;\n } \n\n ReceivedMessageArgumentStream& operator>>( float& rhs )\n {\n if( Eos() )\n throw MissingArgumentException();\n\n rhs = (*p_++).AsFloat();\n return *this;\n }\n\n ReceivedMessageArgumentStream& operator>>( char& rhs )\n {\n if( Eos() )\n throw MissingArgumentException();\n\n rhs = (*p_++).AsChar();\n return *this;\n }\n\n ReceivedMessageArgumentStream& operator>>( RgbaColor& rhs )\n {\n if( Eos() )\n throw MissingArgumentException();\n\n rhs.value = (*p_++).AsRgbaColor();\n return *this;\n }\n\n ReceivedMessageArgumentStream& operator>>( MidiMessage& rhs )\n {\n if( Eos() )\n throw MissingArgumentException();\n\n rhs.value = (*p_++).AsMidiMessage();\n return *this;\n }\n\n ReceivedMessageArgumentStream& operator>>( int64& rhs )\n {\n if( Eos() )\n throw MissingArgumentException();\n\n rhs = (*p_++).AsInt64();\n return *this;\n }\n \n ReceivedMessageArgumentStream& operator>>( TimeTag& rhs )\n {\n if( Eos() )\n throw MissingArgumentException();\n\n rhs.value = (*p_++).AsTimeTag();\n return *this;\n }\n\n ReceivedMessageArgumentStream& operator>>( double& rhs )\n {\n if( Eos() )\n throw MissingArgumentException();\n\n rhs = (*p_++).AsDouble();\n return *this;\n }\n\n ReceivedMessageArgumentStream& operator>>( Blob& rhs )\n {\n if( Eos() )\n throw MissingArgumentException();\n\n (*p_++).AsBlob( rhs.data, rhs.size );\n return *this;\n }\n \n ReceivedMessageArgumentStream& operator>>( const char*& rhs )\n {\n if( Eos() )\n throw MissingArgumentException();\n\n rhs = (*p_++).AsString();\n return *this;\n }\n \n ReceivedMessageArgumentStream& operator>>( Symbol& rhs )\n {\n if( Eos() )\n throw MissingArgumentException();\n\n rhs.value = (*p_++).AsSymbol();\n return *this;\n }\n\n ReceivedMessageArgumentStream& operator>>( MessageTerminator& rhs )\n {\n (void) rhs; // suppress unused parameter warning\n\n if( !Eos() )\n throw ExcessArgumentException();\n\n return *this;\n }\n};\n\n\nclass ReceivedMessage{\n void Init( const char *bundle, osc_bundle_element_size_t size );\npublic:\n explicit ReceivedMessage( const ReceivedPacket& packet );\n explicit ReceivedMessage( const ReceivedBundleElement& bundleElement );\n\n\tconst char *AddressPattern() const { return addressPattern_; }\n\n\t// Support for non-standard SuperCollider integer address patterns:\n\tbool AddressPatternIsUInt32() const;\n\tuint32 AddressPatternAsUInt32() const;\n\n\tuint32 ArgumentCount() const { return static_cast(typeTagsEnd_ - typeTagsBegin_); }\n\n const char *TypeTags() const { return typeTagsBegin_; }\n\n\n typedef ReceivedMessageArgumentIterator const_iterator;\n \n\tReceivedMessageArgumentIterator ArgumentsBegin() const\n {\n return ReceivedMessageArgumentIterator( typeTagsBegin_, arguments_ );\n }\n \n\tReceivedMessageArgumentIterator ArgumentsEnd() const\n {\n return ReceivedMessageArgumentIterator( typeTagsEnd_, 0 );\n }\n\n ReceivedMessageArgumentStream ArgumentStream() const\n {\n return ReceivedMessageArgumentStream( ArgumentsBegin(), ArgumentsEnd() );\n }\n\nprivate:\n\tconst char *addressPattern_;\n\tconst char *typeTagsBegin_;\n\tconst char *typeTagsEnd_;\n const char *arguments_;\n};\n\n\nclass ReceivedBundle{\n void Init( const char *message, osc_bundle_element_size_t size );\npublic:\n explicit ReceivedBundle( const ReceivedPacket& packet );\n explicit ReceivedBundle( const ReceivedBundleElement& bundleElement );\n\n uint64 TimeTag() const;\n\n uint32 ElementCount() const { return elementCount_; }\n\n typedef ReceivedBundleElementIterator const_iterator;\n \n\tReceivedBundleElementIterator ElementsBegin() const\n {\n return ReceivedBundleElementIterator( timeTag_ + 8 );\n }\n \n\tReceivedBundleElementIterator ElementsEnd() const\n {\n return ReceivedBundleElementIterator( end_ );\n }\n\nprivate:\n const char *timeTag_;\n const char *end_;\n uint32 elementCount_;\n};\n\n\n} // namespace osc\n\n\n#endif /* INCLUDED_OSCPACK_OSCRECEIVEDELEMENTS_H */\n" }, { "path": "lib/oscpack/osc/OscTypes.cpp", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#include \"OscTypes.h\"\n\nnamespace osc{\n\nBundleInitiator BeginBundleImmediate(1);\nBundleTerminator EndBundle;\nMessageTerminator EndMessage;\nNilType OscNil;\n#ifndef _OBJC_OBJC_H_\nNilType Nil; // Objective-C defines Nil. so our Nil is deprecated. use OscNil instead\n#endif\nInfinitumType Infinitum;\nArrayInitiator BeginArray;\nArrayTerminator EndArray;\n\n} // namespace osc\n" }, { "path": "lib/oscpack/osc/OscTypes.h", "content": "/*\n\toscpack -- Open Sound Control (OSC) packet manipulation library\n http://www.rossbencina.com/code/oscpack\n\n Copyright (c) 2004-2013 Ross Bencina \n\n\tPermission is hereby granted, free of charge, to any person obtaining\n\ta copy of this software and associated documentation files\n\t(the \"Software\"), to deal in the Software without restriction,\n\tincluding without limitation the rights to use, copy, modify, merge,\n\tpublish, distribute, sublicense, and/or sell copies of the Software,\n\tand to permit persons to whom the Software is furnished to do so,\n\tsubject to the following conditions:\n\n\tThe above copyright notice and this permission notice shall be\n\tincluded in all copies or substantial portions of the Software.\n\n\tTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n\tEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n\tMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n\tIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\n\tANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n\tCONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n\tWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n*/\n\n/*\n\tThe text above constitutes the entire oscpack license; however, \n\tthe oscpack developer(s) also make the following non-binding requests:\n\n\tAny person wishing to distribute modifications to the Software is\n\trequested to send the modifications to the original developer so that\n\tthey can be incorporated into the canonical version. It is also \n\trequested that these non-binding requests be included whenever the\n\tabove license is reproduced.\n*/\n#ifndef INCLUDED_OSCPACK_OSCTYPES_H\n#define INCLUDED_OSCPACK_OSCTYPES_H\n\n#include \n\nnamespace osc\n{\n\n// basic types\n\n#if defined(__BORLANDC__) || defined(_MSC_VER)\n\ntypedef __int64 int64;\ntypedef unsigned __int64 uint64;\n\n#elif defined(__x86_64__) || defined(_M_X64) || defined(_LP64)\n\ntypedef int64_t int64;\ntypedef uint64_t uint64;\n\n#else\n\ntypedef long long int64;\ntypedef unsigned long long uint64;\n\n#endif\n\n#if defined(__x86_64__) || defined(_M_X64) || defined(_LP64)\n\ntypedef signed int int32;\ntypedef unsigned int uint32;\n\n#else\n\ntypedef signed long int32;\ntypedef unsigned long uint32;\n\n#endif\n\nenum ValueTypeSizes\n{\n OSC_SIZEOF_INT32 = 4,\n OSC_SIZEOF_UINT32 = 4,\n OSC_SIZEOF_INT64 = 8,\n OSC_SIZEOF_UINT64 = 8,\n};\n\n// osc_bundle_element_size_t is used for the size of bundle elements and blobs\n// the OSC spec specifies these as int32 (signed) but we ensure that they\n// are always positive since negative field sizes make no sense.\n\ntypedef int32 osc_bundle_element_size_t;\n\nenum\n{\n OSC_INT32_MAX = 0x7FFFFFFF,\n\n // Element sizes are specified to be int32, and are always rounded up to nearest\n // multiple of 4. Therefore their values can't be greater than 0x7FFFFFFC.\n OSC_BUNDLE_ELEMENT_SIZE_MAX = 0x7FFFFFFC\n};\n\ninline bool IsValidElementSizeValue(osc_bundle_element_size_t x)\n{\n // sizes may not be negative or exceed OSC_BUNDLE_ELEMENT_SIZE_MAX\n return x >= 0 && x <= OSC_BUNDLE_ELEMENT_SIZE_MAX;\n}\n\ninline bool IsMultipleOf4(osc_bundle_element_size_t x)\n{\n return (x & ((osc_bundle_element_size_t)0x03)) == 0;\n}\n\nenum TypeTagValues\n{\n TRUE_TYPE_TAG = 'T',\n FALSE_TYPE_TAG = 'F',\n NIL_TYPE_TAG = 'N',\n INFINITUM_TYPE_TAG = 'I',\n INT32_TYPE_TAG = 'i',\n FLOAT_TYPE_TAG = 'f',\n CHAR_TYPE_TAG = 'c',\n RGBA_COLOR_TYPE_TAG = 'r',\n MIDI_MESSAGE_TYPE_TAG = 'm',\n INT64_TYPE_TAG = 'h',\n TIME_TAG_TYPE_TAG = 't',\n DOUBLE_TYPE_TAG = 'd',\n STRING_TYPE_TAG = 's',\n SYMBOL_TYPE_TAG = 'S',\n BLOB_TYPE_TAG = 'b',\n ARRAY_BEGIN_TYPE_TAG = '[',\n ARRAY_END_TYPE_TAG = ']'\n};\n\n// i/o manipulators used for streaming interfaces\n\nstruct BundleInitiator\n{\n explicit BundleInitiator(uint64 timeTag_)\n : timeTag(timeTag_)\n {\n }\n uint64 timeTag;\n};\n\nextern BundleInitiator BeginBundleImmediate;\n\ninline BundleInitiator BeginBundle(uint64 timeTag = 1)\n{\n return BundleInitiator(timeTag);\n}\n\nstruct BundleTerminator\n{\n};\n\nextern BundleTerminator EndBundle;\n\nstruct BeginMessage\n{\n explicit BeginMessage(const char* addressPattern_)\n : addressPattern(addressPattern_)\n {\n }\n const char* addressPattern;\n};\n\nstruct MessageTerminator\n{\n};\n\nextern MessageTerminator EndMessage;\n\n// osc specific types. they are defined as structs so they can be used\n// as separately identifiable types with the streaming operators.\n\nstruct NilType\n{\n};\n\nextern NilType OscNil;\n\n#ifndef _OBJC_OBJC_H_\nextern NilType Nil; // Objective-C defines Nil. so our Nil is deprecated. use OscNil instead\n#endif\n\nstruct InfinitumType\n{\n};\n\nextern InfinitumType Infinitum;\n\nstruct RgbaColor\n{\n RgbaColor() {}\n explicit RgbaColor(uint32 value_)\n : value(value_)\n {\n }\n uint32 value;\n\n operator uint32() const { return value; }\n};\n\nstruct MidiMessage\n{\n MidiMessage() {}\n explicit MidiMessage(uint32 value_)\n : value(value_)\n {\n }\n uint32 value;\n\n operator uint32() const { return value; }\n};\n\nstruct TimeTag\n{\n TimeTag() {}\n explicit TimeTag(uint64 value_)\n : value(value_)\n {\n }\n uint64 value;\n\n operator uint64() const { return value; }\n};\n\nstruct Symbol\n{\n Symbol() {}\n explicit Symbol(const char* value_)\n : value(value_)\n {\n }\n const char* value;\n\n operator const char*() const { return value; }\n};\n\nstruct Blob\n{\n Blob() {}\n explicit Blob(const void* data_, osc_bundle_element_size_t size_)\n : data(data_)\n , size(size_)\n {\n }\n const void* data;\n osc_bundle_element_size_t size;\n};\n\nstruct ArrayInitiator\n{\n};\n\nextern ArrayInitiator BeginArray;\n\nstruct ArrayTerminator\n{\n};\n\nextern ArrayTerminator EndArray;\n\n} // namespace osc\n\n#endif /* INCLUDED_OSCPACK_OSCTYPES_H */\n" }, { "path": "lib/serialosc/MonomeDevice.h", "content": "#ifndef __MONOMEDEVICE_H__\n#define __MONOMEDEVICE_H__\n\n#include \n\ntypedef enum {\n PROTOCOL_40H,\n PROTOCOL_SERIES,\n PROTOCOL_MEXT\n} MonomeProtocol;\n\nstruct MonomeDevice\n{\n std::string id;\n std::string type;\n std::string prefix;\n int port;\n int width;\n int height;\n int rotation;\n MonomeProtocol protocol;\n bool varibright;\n};\n\n#endif //__MONOMEDEVICE_H__" }, { "path": "lib/serialosc/README.md", "content": "C++ serialosc example by Daniel-Bytes\n(with modifications by @dewb for varibright grid messages)\n\nhttp://daniel-bytes.github.io/serialosc_example/\n\nhttps://github.com/daniel-bytes/serialosc_example\n" }, { "path": "lib/serialosc/SerialOsc.cpp", "content": "#include \"SerialOsc.h\"\n#include \"osc/OscOutboundPacketStream.h\"\n#include \n#include \n#include \n\n#define OSC_BUFFER_SIZE 1024\n\nSerialOsc::SerialOsc(std::string devicePrefix, int defaultPort, int maxPortsToScan)\n : listenSocket(nullptr)\n , listener(nullptr)\n , devicePrefix(devicePrefix)\n , listenPort(defaultPort)\n , portsToScan(maxPortsToScan < 1 ? 1 : maxPortsToScan)\n , serviceDetected(false)\n{\n}\n\nSerialOsc::~SerialOsc(void)\n{\n if (listenSocket != nullptr)\n {\n stop();\n delete listenSocket;\n }\n\n for (auto it = devices.begin(); it != devices.end(); ++it)\n {\n delete *it;\n }\n}\n\nvoid SerialOsc::start(Listener* listener)\n{\n this->listener = listener;\n\n if (listener == nullptr || listenSocket != nullptr)\n {\n return;\n }\n\n for (int i = 0; i < portsToScan; i++)\n {\n int tempPort = listenPort + i;\n\n try\n {\n listenSocket = new UdpListeningReceiveSocket(\n IpEndpointName(\"localhost\", tempPort),\n this);\n\n listenPort = tempPort;\n std::cout << \"Binding to port \" << tempPort << \".\" << std::endl;\n break;\n }\n catch (std::runtime_error& ex)\n {\n // try next port\n listenSocket = nullptr;\n std::cerr << \"Failed to bind to port \" << tempPort << \". \" << ex.what() << std::endl;\n }\n }\n\n if (listenSocket != nullptr)\n {\n thread = std::thread(&SerialOsc::runThread, this);\n\n sendStatusMessage();\n sendVersionMessage();\n sendDeviceQueryMessage();\n sendDeviceNotifyMessage();\n }\n}\n\nvoid SerialOsc::stop(void)\n{\n if (listenSocket != nullptr)\n {\n listenSocket->AsynchronousBreak();\n thread.join();\n listenSocket = nullptr;\n }\n}\n\nbool SerialOsc::isServiceDetected(void) const\n{\n return serviceDetected;\n}\n\nstd::string SerialOsc::getVersionString(void) const\n{\n return versionString;\n}\n\nvoid SerialOsc::runThread(void)\n{\n if (listenSocket != nullptr)\n {\n listenSocket->Run();\n }\n}\n\nvoid SerialOsc::sendStatusMessage(void)\n{\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, SERIALOSC_PORT));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(\"/serialosc/status\")\n << SERIALOSC_ADDRESS\n << listenPort\n << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::sendVersionMessage(void)\n{\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, SERIALOSC_PORT));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(\"/serialosc/version\")\n << SERIALOSC_ADDRESS\n << listenPort\n << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::sendDeviceQueryMessage(void)\n{\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, SERIALOSC_PORT));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(\"/serialosc/list\")\n << SERIALOSC_ADDRESS\n << listenPort\n << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::sendDeviceNotifyMessage(void)\n{\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, SERIALOSC_PORT));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(\"/serialosc/notify\")\n << SERIALOSC_ADDRESS\n << listenPort\n << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::sendDeviceInfoMessage(int port)\n{\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, port));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(\"/sys/info\")\n << listenPort\n << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::sendDevicePortMessage(int port)\n{\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, port));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(\"/sys/port\")\n << listenPort\n << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::sendDevicePrefixMessage(int port)\n{\n std::string prefix = devicePrefix;\n\n if (prefix.find(\"/\") == 0)\n {\n prefix = prefix.substr(1);\n }\n\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, port));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(\"/sys/prefix\")\n << prefix.c_str()\n << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::sendDeviceLedCommand(const MonomeDevice* const device, int x, int y, bool state)\n{\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, device->port));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n std::string address = (device->prefix + \"/grid/led/set\");\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(address.c_str())\n << x\n << y\n << (state ? 1 : 0)\n << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::sendDeviceLedAllCommand(const MonomeDevice* const device, bool state)\n{\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, device->port));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n std::string address = (device->prefix + \"/grid/led/all\");\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(address.c_str())\n << (state ? 1 : 0)\n << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::sendDeviceLedRowCommand(const MonomeDevice* const device, int x_offset, int y, uint8_t stateBits)\n{\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, device->port));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n std::string address = (device->prefix + \"/grid/led/row\");\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(address.c_str())\n << x_offset\n << y\n << stateBits\n << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::sendDeviceLedMapCommand(const MonomeDevice* const device, int x, int y, uint8_t* stateMap)\n{\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, device->port));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n std::string address = (device->prefix + \"/grid/led/map\");\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(address.c_str())\n << x\n << y;\n\n for (int i = 0; i < 8; i++)\n {\n p << stateMap[i];\n }\n\n p << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::sendDeviceLedLevelMapCommand(const MonomeDevice* const device, int x, int y, uint8_t* stateMap)\n{\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, device->port));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n std::string address = (device->prefix + \"/grid/led/level/map\");\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(address.c_str())\n << x\n << y;\n\n for (int i = 0; i < 64; i++)\n {\n p << stateMap[i];\n }\n\n p << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::sendDeviceRingMapCommand(const MonomeDevice* const device, int n, uint8_t leds[64])\n{\n UdpTransmitSocket transmitSocket(IpEndpointName(SERIALOSC_ADDRESS, device->port));\n char buffer[OSC_BUFFER_SIZE];\n osc::OutboundPacketStream p(buffer, OSC_BUFFER_SIZE);\n std::string address = (device->prefix + \"/ring/map\");\n\n p << osc::BeginBundleImmediate\n << osc::BeginMessage(address.c_str())\n << n;\n\n for (int i = 0; i < 64; i++)\n {\n p << leds[i];\n }\n\n p << osc::EndMessage\n << osc::EndBundle;\n\n transmitSocket.Send(p.Data(), p.Size());\n}\n\nvoid SerialOsc::ProcessMessage(const osc::ReceivedMessage& m, const IpEndpointName& remoteEndpoint)\n{\n std::string address = m.AddressPattern();\n auto iter = m.ArgumentsBegin();\n\n try\n {\n if (address == \"/serialosc/status\")\n {\n int state = (iter++)->AsInt32();\n if (state == 1)\n {\n serviceDetected = true;\n }\n }\n else if (address == \"/serialosc/version\")\n {\n std::string version = (iter++)->AsString();\n std::string commit = (iter++)->AsString();\n\n versionString = version + \" (\" + commit + \")\";\n }\n else if (address == \"/serialosc/device\" || address == \"/serialosc/add\")\n {\n std::string id = (iter++)->AsString();\n std::string type = (iter++)->AsString();\n int port = (iter++)->AsInt32();\n MonomeDevice* device = nullptr;\n\n auto deviceIterator = std::find_if(devices.begin(), devices.end(), [id](const MonomeDevice* x) { return x->id == id; });\n\n if (deviceIterator == devices.end())\n {\n device = new MonomeDevice;\n devices.push_back(device);\n\n if (address == \"/serialosc/add\")\n {\n sendDeviceNotifyMessage();\n }\n }\n else\n {\n device = *deviceIterator;\n }\n\n device->id = id;\n const char* idstr = device->id.c_str();\n\n if (strncmp(idstr, \"m40h\", 4) == 0 || strncmp(idstr, \"a40h\", 4) == 0)\n {\n device->protocol = PROTOCOL_40H;\n device->varibright = false;\n }\n else if (strncmp(idstr, \"m64-\", 4) == 0 || strncmp(idstr, \"m128-\", 5) == 0 || strncmp(idstr, \"m256-\", 5) == 0)\n {\n device->protocol = PROTOCOL_SERIES;\n device->varibright = false;\n }\n else\n {\n device->protocol = PROTOCOL_MEXT;\n device->varibright = true;\n }\n\n device->type = type;\n device->port = port;\n device->prefix = devicePrefix;\n\n if (device->prefix.find(\"/\") != 0)\n {\n device->prefix = \"/\" + device->prefix;\n }\n\n // wait until after size message recieved -MD\n // listener->deviceFound(device);\n sendDeviceInfoMessage(device->port);\n }\n else if (address == \"/serialosc/remove\")\n {\n std::string id = (iter++)->AsString();\n\n auto deviceIterator = std::find_if(devices.begin(), devices.end(), [id](const MonomeDevice* x) { return x->id == id; });\n\n if (deviceIterator != devices.end())\n {\n std::remove(devices.begin(), devices.end(), *deviceIterator);\n delete *deviceIterator;\n devices.erase(deviceIterator);\n\n listener->deviceRemoved(id);\n\n sendDeviceNotifyMessage();\n }\n }\n else if (address == \"/sys/id\")\n {\n currentDeviceID = (iter++)->AsString();\n }\n else if (address == \"/sys/size\")\n {\n auto deviceIterator = std::find_if(devices.begin(), devices.end(), [=](const MonomeDevice* x) { return x->id == currentDeviceID; });\n\n if (deviceIterator != devices.end())\n {\n auto device = *deviceIterator;\n device->width = (iter++)->AsInt32();\n device->height = (iter++)->AsInt32();\n\n // wait to notify listeners here, after size is known -MD\n listener->deviceFound(device);\n }\n }\n else if (address == \"/sys/rotation\")\n {\n auto deviceIterator = std::find_if(devices.begin(), devices.end(), [=](const MonomeDevice* x) { return x->id == currentDeviceID; });\n\n if (deviceIterator != devices.end())\n {\n auto device = *deviceIterator;\n device->rotation = (iter++)->AsInt32();\n }\n }\n else if (address == (\"/\" + devicePrefix + \"/grid/key\"))\n {\n auto deviceIterator = std::find_if(devices.begin(), devices.end(), [=](const MonomeDevice* x) { return x->port == remoteEndpoint.port; });\n\n int x = (iter++)->AsInt32();\n int y = (iter++)->AsInt32();\n bool state = (iter++)->AsInt32() > 0;\n\n listener->buttonPressMessageReceived(*deviceIterator, x, y, state);\n }\n else if (address == (\"/\" + devicePrefix + \"/enc/delta\"))\n {\n auto deviceIterator = std::find_if(devices.begin(), devices.end(), [=](const MonomeDevice* x) { return x->port == remoteEndpoint.port; });\n\n int n = (iter++)->AsInt32();\n int d = (iter++)->AsInt32();\n\n listener->encDeltaMessageReceived(*deviceIterator, n, d);\n }\n // TODO : Handle other incoming device commands\n }\n catch (osc::WrongArgumentTypeException& exc)\n {\n printf(\"WrongArgumentTypeException: %s\", exc.what());\n }\n}" }, { "path": "lib/serialosc/SerialOsc.h", "content": "#ifndef __SERIALOSC_H__\n#define __SERIALOSC_H__\n\n#include \"MonomeDevice.h\"\n#include \"ip/UdpSocket.h\"\n#include \"osc/OscPacketListener.h\"\n#include \n#include \n#include \n\n#define SERIALOSC_ADDRESS \"127.0.0.1\"\n#define SERIALOSC_PORT 12002\n\nclass UdpListeningReceiveSocket;\n\nclass SerialOsc\n : protected osc::OscPacketListener\n{\npublic:\n struct Listener\n {\n virtual void deviceFound(const MonomeDevice* const device) {}\n virtual void deviceRemoved(const std::string& id) {}\n virtual void buttonPressMessageReceived(MonomeDevice* device, int x, int y, bool state) = 0;\n virtual void encDeltaMessageReceived(MonomeDevice* device, int n, int delta) = 0;\n };\n\n typedef std::vector MonomeDeviceCollection;\n typedef std::vector::iterator MonomeDeviceCollectionIterator;\n\npublic:\n SerialOsc(std::string devicePrefix, int defaultPort, int maxPortsToScan = 1000);\n virtual ~SerialOsc(void);\n\n void start(Listener* listener);\n void stop(void);\n\n bool isServiceDetected() const;\n std::string getVersionString() const;\n\n int getListenPort(void) const { return listenPort; }\n int getDeviceCount(void) const { return devices.size(); }\n const MonomeDeviceCollection& getDevices(void) const { return devices; }\n\npublic:\n // Serialosc messages\n void sendStatusMessage(void);\n void sendVersionMessage(void);\n void sendDeviceQueryMessage(void);\n void sendDeviceNotifyMessage(void);\n void sendDeviceInfoMessage(int port);\n void sendDevicePortMessage(int port);\n void sendDevicePrefixMessage(int port);\n\n // Device messages\n void sendDeviceLedCommand(const MonomeDevice* const device, int x, int y, bool state);\n void sendDeviceLedAllCommand(const MonomeDevice* const device, bool state);\n void sendDeviceLedRowCommand(const MonomeDevice* const device, int x_offset, int y, uint8_t stateBits);\n void sendDeviceLedMapCommand(const MonomeDevice* const device, int x, int y, uint8_t* stateMap);\n void sendDeviceLedLevelMapCommand(const MonomeDevice* const device, int x, int y, uint8_t* stateMap);\n void sendDeviceRingMapCommand(const MonomeDevice* const device, int n, uint8_t leds[64]);\n\nprotected:\n void runThread(void);\n void ProcessMessage(const osc::ReceivedMessage& m, const IpEndpointName& remoteEndpoint) override;\n\nprotected:\n UdpListeningReceiveSocket* listenSocket;\n Listener* listener;\n MonomeDeviceCollection devices;\n std::string currentDeviceID;\n std::string devicePrefix;\n int listenPort;\n int portsToScan;\n std::thread thread;\n bool serviceDetected;\n std::string versionString;\n};\n\n#endif //_SERIALOSC_H__" }, { "path": "lib/simple-svg/CMakeLists.txt", "content": "project (simple-svg)\ncmake_minimum_required(VERSION 2.8)\n\nadd_executable(simple_svg main_1.0.0.cpp simple_svg_1.0.0.hpp)\n\nset_property(TARGET simple_svg PROPERTY CXX_STANDARD 11)\n\n \nif(MSVC)\n add_definitions(/D_CRT_SECURE_NO_WARNINGS)\n add_definitions(/D_SCL_SECURE_NO_WARNINGS)\n add_definitions(/DNOMINMAX)\nendif(MSVC)\n" }, { "path": "lib/simple-svg/LICENSE", "content": "Copyright (c) 2015, adishavit\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n* Redistributions of source code must retain the above copyright notice, this\n list of conditions and the following disclaimer.\n\n* Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n* Neither the name of simple-svg nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\nFOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\nDAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\nSERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\nCAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\nOR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\nOF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n" }, { "path": "lib/simple-svg/README.md", "content": "# simple-svg\nEasy to use SVG library for C++ (fork)\n\nThis library is a single file header-only C++ library for creating SVG files.\n\nSimple-SVG was written to provide an easy API to allow beginners to become more accustomed to C++ by easily creating graphics.\n\nThis project creates files that can then be viewed by a sister project [File Monitor](http://code.google.com/p/file-monitor). As you make changes to your SVG document, you will automatically see an updated image in File Monitor.\n\n\nThis is a fork/clone of the original code [here](https://code.google.com/p/simple-svg/).\n" }, { "path": "lib/simple-svg/main_1.0.0.cpp", "content": "\n/*******************************************************************************\n* The \"New BSD License\" : http://www.opensource.org/licenses/bsd-license.php *\n********************************************************************************\n\nCopyright (c) 2010, Mark Turney\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n * Neither the name of the nor the\n names of its contributors may be used to endorse or promote products\n derived from this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\nANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n******************************************************************************/\n\n#include \"simple_svg_1.0.0.hpp\"\n\nusing namespace svg;\n\n// Demo page shows sample usage of the Simple SVG library.\n\nint main()\n{\n Dimensions dimensions(100, 100);\n Document doc(\"my_svg.svg\", Layout(dimensions, Layout::BottomLeft));\n\n // Red image border.\n Polygon border(Stroke(1, Color::Red));\n border << Point(0, 0) << Point(dimensions.width, 0)\n << Point(dimensions.width, dimensions.height) << Point(0, dimensions.height);\n doc << border;\n\n // Long notation. Local variable is created, children are added to varaible.\n LineChart chart(5.0);\n Polyline polyline_a(Stroke(.5, Color::Blue));\n Polyline polyline_b(Stroke(.5, Color::Aqua));\n Polyline polyline_c(Stroke(.5, Color::Fuchsia));\n polyline_a << Point(0, 0) << Point(10, 30)\n << Point(20, 40) << Point(30, 45) << Point(40, 44);\n polyline_b << Point(0, 10) << Point(10, 22)\n << Point(20, 30) << Point(30, 32) << Point(40, 30);\n polyline_c << Point(0, 12) << Point(10, 15)\n << Point(20, 14) << Point(30, 10) << Point(40, 2);\n chart << polyline_a << polyline_b << polyline_c;\n doc << chart;\n\n // Condensed notation, parenthesis isolate temporaries that are inserted into parents.\n doc << (LineChart(Dimensions(65, 5))\n << (Polyline(Stroke(.5, Color::Blue)) << Point(0, 0) << Point(10, 8) << Point(20, 13))\n << (Polyline(Stroke(.5, Color::Orange)) << Point(0, 10) << Point(10, 16) << Point(20, 20))\n << (Polyline(Stroke(.5, Color::Cyan)) << Point(0, 5) << Point(10, 13) << Point(20, 16)));\n\n doc << Circle(Point(80, 80), 20, Fill(Color(100, 200, 120)), Stroke(1, Color(200, 250, 150)));\n\n doc << Text(Point(5, 77), \"Simple SVG\", Color::Silver, Font(10, \"Verdana\"));\n\n doc << (Polygon(Color(200, 160, 220), Stroke(.5, Color(150, 160, 200))) << Point(20, 70)\n << Point(25, 72) << Point(33, 70) << Point(35, 60) << Point(25, 55) << Point(18, 63));\n\n doc << Rectangle(Point(70, 55), 20, 15, Color::Yellow);\n\n doc.save();\n}\n" }, { "path": "lib/simple-svg/simple_svg_1.0.0.hpp", "content": "/*******************************************************************************\n* The \"New BSD License\" : http://www.opensource.org/licenses/bsd-license.php *\n********************************************************************************\n\nCopyright (c) 2010, Mark Turney\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n * Neither the name of the nor the\n names of its contributors may be used to endorse or promote products\n derived from this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\nANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n******************************************************************************/\n\n#ifndef SIMPLE_SVG_HPP\n#define SIMPLE_SVG_HPP\n\n#include \n#include \n#include \n#include \n\n#include \n\nnamespace svg\n{\n // Utility XML/String Functions.\n template \n inline std::string attribute(std::string const & attribute_name,\n T const & value, std::string const & unit = \"\")\n {\n std::stringstream ss;\n ss << attribute_name << \"=\\\"\" << value << unit << \"\\\" \";\n return ss.str();\n }\n inline std::string elemStart(std::string const & element_name)\n {\n return \"\\t<\" + element_name + \" \";\n }\n inline std::string elemEnd(std::string const & element_name)\n {\n return \"\\n\";\n }\n inline std::string emptyElemEnd()\n {\n return \"/>\\n\";\n }\n\n // Quick optional return type. This allows functions to return an invalid\n // value if no good return is possible. The user checks for validity\n // before using the returned value.\n template \n class optional\n {\n public:\n optional(T const & type)\n : valid(true), type(type) { }\n optional() : valid(false), type(T()) { }\n T * operator->()\n {\n // If we try to access an invalid value, an exception is thrown.\n if (!valid)\n throw std::exception();\n\n return &type;\n }\n // Test for validity.\n bool operator!() const { return !valid; }\n private:\n bool valid;\n T type;\n };\n\n struct Dimensions\n {\n Dimensions(double width, double height) : width(width), height(height) { }\n Dimensions(double combined = 0) : width(combined), height(combined) { }\n double width;\n double height;\n };\n\n struct Point\n {\n Point(double x = 0, double y = 0) : x(x), y(y) { }\n double x;\n double y;\n };\n inline optional getMinPoint(std::vector const & points)\n {\n if (points.empty())\n return optional();\n\n Point min = points[0];\n for (unsigned i = 0; i < points.size(); ++i) {\n if (points[i].x < min.x)\n min.x = points[i].x;\n if (points[i].y < min.y)\n min.y = points[i].y;\n }\n return optional(min);\n }\n inline optional getMaxPoint(std::vector const & points)\n {\n if (points.empty())\n return optional();\n\n Point max = points[0];\n for (unsigned i = 0; i < points.size(); ++i) {\n if (points[i].x > max.x)\n max.x = points[i].x;\n if (points[i].y > max.y)\n max.y = points[i].y;\n }\n return optional(max);\n }\n\n // Defines the dimensions, scale, origin, and origin offset of the document.\n struct Layout\n {\n enum Origin { TopLeft, BottomLeft, TopRight, BottomRight };\n\n Layout(Dimensions const & dimensions = Dimensions(400, 300), Origin origin = BottomLeft,\n double scale = 1, Point const & origin_offset = Point(0, 0))\n : dimensions(dimensions), scale(scale), origin(origin), origin_offset(origin_offset) { }\n Dimensions dimensions;\n double scale;\n Origin origin;\n Point origin_offset;\n };\n\n // Convert coordinates in user space to SVG native space.\n inline double translateX(double x, Layout const & layout)\n {\n if (layout.origin == Layout::BottomRight || layout.origin == Layout::TopRight)\n return layout.dimensions.width - ((x + layout.origin_offset.x) * layout.scale);\n else\n return (layout.origin_offset.x + x) * layout.scale;\n }\n\n inline double translateY(double y, Layout const & layout)\n {\n if (layout.origin == Layout::BottomLeft || layout.origin == Layout::BottomRight)\n return layout.dimensions.height - ((y + layout.origin_offset.y) * layout.scale);\n else\n return (layout.origin_offset.y + y) * layout.scale;\n }\n inline double translateScale(double dimension, Layout const & layout)\n {\n return dimension * layout.scale;\n }\n\n class Serializeable\n {\n public:\n Serializeable() { }\n virtual ~Serializeable() { };\n virtual std::string toString(Layout const & layout) const = 0;\n };\n\n class Color : public Serializeable\n {\n public:\n enum Defaults { Transparent = -1, Aqua, Black, Blue, Brown, Cyan, Fuchsia,\n Green, Lime, Magenta, Orange, Purple, Red, Silver, White, Yellow };\n\n Color(int r, int g, int b) : transparent(false), red(r), green(g), blue(b) { }\n Color(Defaults color)\n : transparent(false), red(0), green(0), blue(0)\n {\n switch (color)\n {\n case Aqua: assign(0, 255, 255); break;\n case Black: assign(0, 0, 0); break;\n case Blue: assign(0, 0, 255); break;\n case Brown: assign(165, 42, 42); break;\n case Cyan: assign(0, 255, 255); break;\n case Fuchsia: assign(255, 0, 255); break;\n case Green: assign(0, 128, 0); break;\n case Lime: assign(0, 255, 0); break;\n case Magenta: assign(255, 0, 255); break;\n case Orange: assign(255, 165, 0); break;\n case Purple: assign(128, 0, 128); break;\n case Red: assign(255, 0, 0); break;\n case Silver: assign(192, 192, 192); break;\n case White: assign(255, 255, 255); break;\n case Yellow: assign(255, 255, 0); break;\n default: transparent = true; break;\n }\n }\n virtual ~Color() { }\n std::string toString(Layout const &) const\n {\n std::stringstream ss;\n if (transparent)\n ss << \"none\";\n else\n ss << \"rgb(\" << red << \",\" << green << \",\" << blue << \")\";\n return ss.str();\n }\n private:\n bool transparent;\n int red;\n int green;\n int blue;\n\n void assign(int r, int g, int b)\n {\n red = r;\n green = g;\n blue = b;\n }\n };\n\n class Fill : public Serializeable\n {\n public:\n Fill(Color::Defaults color) : color(color) { }\n Fill(Color color = Color::Transparent)\n : color(color) { }\n std::string toString(Layout const & layout) const\n {\n std::stringstream ss;\n ss << attribute(\"fill\", color.toString(layout));\n return ss.str();\n }\n private:\n Color color;\n };\n\n class Stroke : public Serializeable\n {\n public:\n Stroke(double width = -1, Color color = Color::Transparent, bool nonScalingStroke = false)\n : width(width), color(color), nonScaling(nonScalingStroke) { }\n std::string toString(Layout const & layout) const\n {\n // If stroke width is invalid.\n if (width < 0)\n return std::string();\n\n std::stringstream ss;\n ss << attribute(\"stroke-width\", translateScale(width, layout)) << attribute(\"stroke\", color.toString(layout));\n if (nonScaling)\n ss << attribute(\"vector-effect\", \"non-scaling-stroke\");\n return ss.str();\n }\n private:\n double width;\n Color color;\n bool nonScaling;\n };\n\n class Font : public Serializeable\n {\n public:\n Font(double size = 12, std::string const & family = \"Verdana\") : size(size), family(family) { }\n std::string toString(Layout const & layout) const\n {\n std::stringstream ss;\n ss << attribute(\"font-size\", translateScale(size, layout)) << attribute(\"font-family\", family);\n return ss.str();\n }\n private:\n double size;\n std::string family;\n };\n\n class Shape : public Serializeable\n {\n public:\n Shape(Fill const & fill = Fill(), Stroke const & stroke = Stroke())\n : fill(fill), stroke(stroke) { }\n virtual ~Shape() { }\n virtual std::string toString(Layout const & layout) const = 0;\n virtual void offset(Point const & offset) = 0;\n protected:\n Fill fill;\n Stroke stroke;\n };\n template \n inline std::string vectorToString(std::vector collection, Layout const & layout)\n {\n std::string combination_str;\n for (unsigned i = 0; i < collection.size(); ++i)\n combination_str += collection[i].toString(layout);\n\n return combination_str;\n }\n\n class Circle : public Shape\n {\n public:\n Circle(Point const & center, double diameter, Fill const & fill,\n Stroke const & stroke = Stroke())\n : Shape(fill, stroke), center(center), radius(diameter / 2) { }\n std::string toString(Layout const & layout) const\n {\n std::stringstream ss;\n ss << elemStart(\"circle\") << attribute(\"cx\", translateX(center.x, layout))\n << attribute(\"cy\", translateY(center.y, layout))\n << attribute(\"r\", translateScale(radius, layout)) << fill.toString(layout)\n << stroke.toString(layout) << emptyElemEnd();\n return ss.str();\n }\n void offset(Point const & offset)\n {\n center.x += offset.x;\n center.y += offset.y;\n }\n private:\n Point center;\n double radius;\n };\n\n class Elipse : public Shape\n {\n public:\n Elipse(Point const & center, double width, double height,\n Fill const & fill = Fill(), Stroke const & stroke = Stroke())\n : Shape(fill, stroke), center(center), radius_width(width / 2),\n radius_height(height / 2) { }\n std::string toString(Layout const & layout) const\n {\n std::stringstream ss;\n ss << elemStart(\"ellipse\") << attribute(\"cx\", translateX(center.x, layout))\n << attribute(\"cy\", translateY(center.y, layout))\n << attribute(\"rx\", translateScale(radius_width, layout))\n << attribute(\"ry\", translateScale(radius_height, layout))\n << fill.toString(layout) << stroke.toString(layout) << emptyElemEnd();\n return ss.str();\n }\n void offset(Point const & offset)\n {\n center.x += offset.x;\n center.y += offset.y;\n }\n private:\n Point center;\n double radius_width;\n double radius_height;\n };\n\n class Rectangle : public Shape\n {\n public:\n Rectangle(Point const & edge, double width, double height,\n Fill const & fill = Fill(), Stroke const & stroke = Stroke())\n : Shape(fill, stroke), edge(edge), width(width),\n height(height) { }\n std::string toString(Layout const & layout) const\n {\n std::stringstream ss;\n ss << elemStart(\"rect\") << attribute(\"x\", translateX(edge.x, layout))\n << attribute(\"y\", translateY(edge.y, layout))\n << attribute(\"width\", translateScale(width, layout))\n << attribute(\"height\", translateScale(height, layout))\n << fill.toString(layout) << stroke.toString(layout) << emptyElemEnd();\n return ss.str();\n }\n void offset(Point const & offset)\n {\n edge.x += offset.x;\n edge.y += offset.y;\n }\n private:\n Point edge;\n double width;\n double height;\n };\n\n class Line : public Shape\n {\n public:\n Line(Point const & start_point, Point const & end_point,\n Stroke const & stroke = Stroke())\n : Shape(Fill(), stroke), start_point(start_point),\n end_point(end_point) { }\n std::string toString(Layout const & layout) const\n {\n std::stringstream ss;\n ss << elemStart(\"line\") << attribute(\"x1\", translateX(start_point.x, layout))\n << attribute(\"y1\", translateY(start_point.y, layout))\n << attribute(\"x2\", translateX(end_point.x, layout))\n << attribute(\"y2\", translateY(end_point.y, layout))\n << stroke.toString(layout) << emptyElemEnd();\n return ss.str();\n }\n void offset(Point const & offset)\n {\n start_point.x += offset.x;\n start_point.y += offset.y;\n\n end_point.x += offset.x;\n end_point.y += offset.y;\n }\n private:\n Point start_point;\n Point end_point;\n };\n\n class Polygon : public Shape\n {\n public:\n Polygon(Fill const & fill = Fill(), Stroke const & stroke = Stroke())\n : Shape(fill, stroke) { }\n Polygon(Stroke const & stroke = Stroke()) : Shape(Color::Transparent, stroke) { }\n Polygon & operator<<(Point const & point)\n {\n points.push_back(point);\n return *this;\n }\n std::string toString(Layout const & layout) const\n {\n std::stringstream ss;\n ss << elemStart(\"polygon\");\n\n ss << \"points=\\\"\";\n for (unsigned i = 0; i < points.size(); ++i)\n ss << translateX(points[i].x, layout) << \",\" << translateY(points[i].y, layout) << \" \";\n ss << \"\\\" \";\n\n ss << fill.toString(layout) << stroke.toString(layout) << emptyElemEnd();\n return ss.str();\n }\n void offset(Point const & offset)\n {\n for (unsigned i = 0; i < points.size(); ++i) {\n points[i].x += offset.x;\n points[i].y += offset.y;\n }\n }\n private:\n std::vector points;\n };\n\n class Path : public Shape\n {\n public:\n Path(Fill const & fill = Fill(), Stroke const & stroke = Stroke())\n : Shape(fill, stroke) \n { startNewSubPath(); }\n Path(Stroke const & stroke = Stroke()) : Shape(Color::Transparent, stroke) \n { startNewSubPath(); }\n Path & operator<<(Point const & point)\n {\n paths.back().push_back(point);\n return *this;\n }\n\n void startNewSubPath()\n {\n if (paths.empty() || 0 < paths.back().size())\n paths.emplace_back();\n }\n\n std::string toString(Layout const & layout) const\n {\n std::stringstream ss;\n ss << elemStart(\"path\");\n\n ss << \"d=\\\"\";\n for (auto const& subpath: paths)\n {\n if (subpath.empty())\n continue;\n\n ss << \"M\";\n for (auto const& point: subpath)\n ss << translateX(point.x, layout) << \",\" << translateY(point.y, layout) << \" \";\n ss << \"z \";\n }\n ss << \"\\\" \";\n ss << \"fill-rule=\\\"evenodd\\\" \";\n\n ss << fill.toString(layout) << stroke.toString(layout) << emptyElemEnd();\n return ss.str();\n }\n\n void offset(Point const & offset)\n {\n for (auto& subpath : paths)\n for (auto& point : subpath)\n {\n point.x += offset.x;\n point.y += offset.y;\n }\n }\n private:\n std::vector> paths;\n };\n\n class Polyline : public Shape\n {\n public:\n Polyline(Fill const & fill = Fill(), Stroke const & stroke = Stroke())\n : Shape(fill, stroke) { }\n Polyline(Stroke const & stroke = Stroke()) : Shape(Color::Transparent, stroke) { }\n Polyline(std::vector const & points,\n Fill const & fill = Fill(), Stroke const & stroke = Stroke())\n : Shape(fill, stroke), points(points) { }\n Polyline & operator<<(Point const & point)\n {\n points.push_back(point);\n return *this;\n }\n std::string toString(Layout const & layout) const\n {\n std::stringstream ss;\n ss << elemStart(\"polyline\");\n\n ss << \"points=\\\"\";\n for (unsigned i = 0; i < points.size(); ++i)\n ss << translateX(points[i].x, layout) << \",\" << translateY(points[i].y, layout) << \" \";\n ss << \"\\\" \";\n\n ss << fill.toString(layout) << stroke.toString(layout) << emptyElemEnd();\n return ss.str();\n }\n void offset(Point const & offset)\n {\n for (unsigned i = 0; i < points.size(); ++i) {\n points[i].x += offset.x;\n points[i].y += offset.y;\n }\n }\n std::vector points;\n };\n\n class Text : public Shape\n {\n public:\n Text(Point const & origin, std::string const & content, Fill const & fill = Fill(),\n Font const & font = Font(), Stroke const & stroke = Stroke())\n : Shape(fill, stroke), origin(origin), content(content), font(font) { }\n std::string toString(Layout const & layout) const\n {\n std::stringstream ss;\n ss << elemStart(\"text\") << attribute(\"x\", translateX(origin.x, layout))\n << attribute(\"y\", translateY(origin.y, layout))\n << fill.toString(layout) << stroke.toString(layout) << font.toString(layout)\n << \">\" << content << elemEnd(\"text\");\n return ss.str();\n }\n void offset(Point const & offset)\n {\n origin.x += offset.x;\n origin.y += offset.y;\n }\n private:\n Point origin;\n std::string content;\n Font font;\n };\n\n // Sample charting class.\n class LineChart : public Shape\n {\n public:\n LineChart(Dimensions margin = Dimensions(), double scale = 1,\n Stroke const & axis_stroke = Stroke(.5, Color::Purple))\n : axis_stroke(axis_stroke), margin(margin), scale(scale) { }\n LineChart & operator<<(Polyline const & polyline)\n {\n if (polyline.points.empty())\n return *this;\n\n polylines.push_back(polyline);\n return *this;\n }\n std::string toString(Layout const & layout) const\n {\n if (polylines.empty())\n return \"\";\n\n std::string ret;\n for (unsigned i = 0; i < polylines.size(); ++i)\n ret += polylineToString(polylines[i], layout);\n\n return ret + axisString(layout);\n }\n void offset(Point const & offset)\n {\n for (unsigned i = 0; i < polylines.size(); ++i)\n polylines[i].offset(offset);\n }\n private:\n Stroke axis_stroke;\n Dimensions margin;\n\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wunused-private-field\"\n double scale;\n#pragma GCC diagnostic pop\n\n std::vector polylines;\n\n optional getDimensions() const\n {\n if (polylines.empty())\n return optional();\n\n optional min = getMinPoint(polylines[0].points);\n optional max = getMaxPoint(polylines[0].points);\n for (unsigned i = 0; i < polylines.size(); ++i) {\n if (getMinPoint(polylines[i].points)->x < min->x)\n min->x = getMinPoint(polylines[i].points)->x;\n if (getMinPoint(polylines[i].points)->y < min->y)\n min->y = getMinPoint(polylines[i].points)->y;\n if (getMaxPoint(polylines[i].points)->x > max->x)\n max->x = getMaxPoint(polylines[i].points)->x;\n if (getMaxPoint(polylines[i].points)->y > max->y)\n max->y = getMaxPoint(polylines[i].points)->y;\n }\n\n return optional(Dimensions(max->x - min->x, max->y - min->y));\n }\n std::string axisString(Layout const & layout) const\n {\n optional dimensions = getDimensions();\n if (!dimensions)\n return \"\";\n\n // Make the axis 10% wider and higher than the data points.\n double width = dimensions->width * 1.1;\n double height = dimensions->height * 1.1;\n\n // Draw the axis.\n Polyline axis(Color::Transparent, axis_stroke);\n axis << Point(margin.width, margin.height + height) << Point(margin.width, margin.height)\n << Point(margin.width + width, margin.height);\n\n return axis.toString(layout);\n }\n std::string polylineToString(Polyline const & polyline, Layout const & layout) const\n {\n Polyline shifted_polyline = polyline;\n shifted_polyline.offset(Point(margin.width, margin.height));\n\n std::vector vertices;\n for (unsigned i = 0; i < shifted_polyline.points.size(); ++i)\n vertices.push_back(Circle(shifted_polyline.points[i], getDimensions()->height / 30.0, Color::Black));\n\n return shifted_polyline.toString(layout) + vectorToString(vertices, layout);\n }\n };\n\n class Document\n {\n public:\n Document() {};\n Document(std::string const & file_name, Layout layout = Layout())\n : file_name(file_name), layout(layout) { }\n\n Document & operator<<(Shape const & shape)\n {\n body_nodes_str_list.push_back(shape.toString(layout));\n return *this;\n }\n std::string toString() const\n {\n std::stringstream ss;\n writeToStream(ss);\n return ss.str();\n }\n bool save() const\n {\n std::ofstream ofs(file_name.c_str());\n if (!ofs.good())\n return false;\n\n writeToStream(ofs);\n ofs.close();\n return true;\n }\n private:\n void writeToStream(std::ostream& str) const\n {\n str << \"\\n\\n\\n\";\n for (const auto& body_node_str : body_nodes_str_list) {\n str << body_node_str;\n }\n str << elemEnd(\"svg\");\n }\n\n private:\n std::string file_name;\n Layout layout;\n\n std::vector body_nodes_str_list;\n };\n}\n\n#endif\n" }, { "path": "mkdocs.yml", "content": "site_name: monome for VCV Rack\nsite_url: https://dewb.github.io/monome-rack\nrepo_url: https://github.com/Dewb/monome-rack\nnav:\n - Manual: 'index.md'\n - 'General Info':\n - Introduction: 'general/intro.md'\n - 'Connecting Devices': 'general/connections.md'\n - 'Voltage Standards': 'general/voltage.md'\n - 'Credits & License': \"general/credits.md\"\n - 'Core Modules':\n - Ansible: 'modules/ansible.md'\n - Earthsea: 'modules/earthsea.md'\n - Meadowphysics: 'modules/meadowphysics.md'\n - Teletype: 'modules/teletype.md'\n - 'White Whale': 'modules/whitewhale.md'\n - 'Accessory Modules':\n - 'Virtual Grids': 'modules/grids.md'\n - 'Faderbank': 'modules/faderbank.md'\n - 'Getting Help':\n - Index: 'help.md'\n - 'Releases↗': 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J D: G.BTN.SW G.BTNI\\nIF D: PN 2 K * J 3; $ 3\\n\\n#M\\nJ == + PRT 7 1 8; R * + IN 2 3\\nIF J: PRT 8 PRM; PRT 9 IN; BRK\\nPRT 7 O; J PRT 7; X + J 10\\nD + * J 7 16; K + D 56; P.N 3\\nG.GBX X K 0 J 1 1 1 0 8 7 1\\nG.GBX J D 9 J 1 1 1 0 8 7 1\\n\\n#I\\nINIT.DATA; Q.GRW 1\\nPARAM.SCALE 0 8; IN.SCALE 0 17\\nPRT 7 0; M 25; M.ACT 1\\nG.GBX 8 0 7 0 1 1 0 5 6 1 8\\nG.GBX 9 8 8 0 1 1 0 5 6 1 8\\nLIVE.DASH 1; $ 5\\n\\n#P\\n1\\t1\\t8\\t8\\n1\\t1\\t1\\t1\\n0\\t0\\t0\\t0\\n7\\t7\\t7\\t7\\n\\n1\\t6\\t3\\t0\\n1\\t6\\t3\\t0\\n1\\t6\\t3\\t1\\n1\\t6\\t3\\t1\\n1\\t6\\t3\\t1\\n1\\t6\\t3\\t1\\n1\\t6\\t3\\t1\\n1\\t6\\t3\\t1\\n0\\t0\\t0\\t-1\\n0\\t0\\t0\\t-1\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t1\\n0\\t0\\t0\\t1\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\n\\n#G\\n0000000000000000\\n0000001000000100\\n0000100000010000\\n0010000001000000\\n1000000110000001\\n0000001000000100\\n0000100000010000\\n0010000001000000\\n0000000000000000\\n0000000000000000\\n0000000000000000\\n0000000000000000\\n0000000000000000\\n0000000000000000\\n0000000000000000\\n0000000000000000\\n\\n1\\t2\\t4\\t4\\t1\\t2\\t4\\t5\\t1\\t1\\t1\\t1\\t1\\t1\\t1\\t1\\n5\\t7\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\n7\\t3\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\n0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\t0\\n\"\n }\n }\n}" }, { "path": "res/keymaps/README.md", "content": "## Teletype Keyboard Layouts\n\nThese JSON files define keyboard layouts for Teletype, selectable from the right-click menu. Keyboard layout choice is global for all Teletype modules, and is saved with the Rack settings, not the patch. \n\n### Why does Teletype need custom keyboard layouts?\n\nThe Teletype module firmware code operates directly on HID scancodes sent in USB packets. It acts more like a videogame input mapping system than a text entry system. Rack's GLFW input processing does attempt to do international layout translation, but this text-only mapping is not sufficient for Teletype to understand which keys are being pressed. Even on US keyboards, we have to remap from GLFW scancodes back to HID scancodes.\n\n### How do I use this to improve support for my keyboard?\n\nCopy one of the existing layouts and change the values of `\"output\"` to match the HID codes that Teletype should receive for a given GLFW keycode. \n\nFor example, in the US Dvorak layout, the A key is still A, but the scancodes for B, C, and D should now produce X, J, and E.\n\n```json\n{\n \"name\": \"US Dvorak\",\n \"keymap\": [\n ...\n { \"input\": \"GLFW_KEY_A\", \"output\": \"HID_A\" },\n { \"input\": \"GLFW_KEY_B\", \"output\": \"HID_X\" },\n { \"input\": \"GLFW_KEY_C\", \"output\": \"HID_J\" },\n { \"input\": \"GLFW_KEY_D\", \"output\": \"HID_E\" },\n ...\n ]\n}\n```\n\nBy default, the entire key will be translated regardless which modifier keys are pressed, and the modifier state will be passed along to Teletype as is. \n\nIf you need to map a character that is accessible via the shift key in your layout to a completely different key than its non-shifted character, you can add `\"input_shift\": true` to only remap the shifted character. If you need to customize the behavior so an input key produces a character that requires a shift key in the default US HID layout, you can add `\"output_shift\": true` to send a synthetic shift modifier to Teletype.\n\nFor example, one of the differences between US and UK keyboards is that the \" and @ characters swap positions as shifted characters on the ' and 2 keys. \n\n```json\n{\n \"name\": \"UK\",\n \"keymap\": [\n ...\n { \"input\": \"GLFW_KEY_APOSTROPHE\", \"output\": \"HID_QUOTE\" },\n { \"input\": \"GLFW_KEY_APOSTROPHE\", \"input_shift\": true, \"output\": \"HID_2\", \"output_shift\": true },\n ...\n { \"input\": \"GLFW_KEY_2\", \"output\": \"HID_2\" },\n { \"input\": \"GLFW_KEY_2\", \"input_shift\": true, \"output\": \"HID_QUOTE\", \"output_shift\": true },\n ...\n ]\n}\n```\n\nRemapping of other modifiers is not currently supported, and Alt/Control/Meta are passed to Teletype unchanged. If you need the ability to remap other modifiers in order to properly map your keyboard, please [open an issue](https://github.com/Dewb/monome-rack/issues/new/choose).\n\n### What are the GLFW and HID scancode names?\n\n#### GLFW:\n* GLFW documentation: https://www.glfw.org/docs/3.3/group__keys.html\n\n#### HID:\n* Atmel ASF USB HID header: https://github.com/avrxml/asf/blob/master/common/services/usb/class/hid/usb_protocol_hid.h\n\nTeletype may add additional constants to cover gaps in ASF support, see\n[TeletypeKeyboard.cpp](https://github.com/Dewb/monome-rack/tree/main/src/teletype/TeletypeKeyboard.cpp)\nfor a definitive list.\n" }, { "path": "res/keymaps/uk.json", "content": "{\n \"name\": \"UK\",\n \"keymap\": [\n { \"input\": \"GLFW_KEY_SPACE\", \"output\": \"HID_SPACEBAR\" },\n { \"input\": \"GLFW_KEY_APOSTROPHE\", \"output\": \"HID_QUOTE\" },\n { \"input\": \"GLFW_KEY_APOSTROPHE\", \"input_shift\": true, \"output\": \"HID_2\", \"output_shift\": true },\n { \"input\": \"GLFW_KEY_COMMA\", \"output\": \"HID_COMMA\" },\n { \"input\": \"GLFW_KEY_MINUS\", \"output\": \"HID_UNDERSCORE\" },\n { \"input\": \"GLFW_KEY_PERIOD\", \"output\": \"HID_DOT\" },\n { \"input\": \"GLFW_KEY_SLASH\", \"output\": \"HID_SLASH\" },\n { \"input\": \"GLFW_KEY_0\", \"output\": \"HID_0\" },\n { \"input\": \"GLFW_KEY_1\", \"output\": \"HID_1\" },\n { \"input\": \"GLFW_KEY_2\", \"output\": \"HID_2\" },\n { \"input\": \"GLFW_KEY_2\", \"input_shift\": true, \"output\": \"HID_QUOTE\", \"output_shift\": true },\n { \"input\": \"GLFW_KEY_3\", \"output\": \"HID_3\" },\n { \"input\": \"GLFW_KEY_3\", \"input_shift\": true, \"output\": \"HID_TILDE\" },\n { \"input\": \"GLFW_KEY_4\", \"output\": \"HID_4\" },\n { \"input\": \"GLFW_KEY_5\", \"output\": \"HID_5\" },\n { \"input\": \"GLFW_KEY_6\", \"output\": \"HID_6\" },\n { \"input\": \"GLFW_KEY_7\", \"output\": \"HID_7\" },\n { \"input\": \"GLFW_KEY_8\", \"output\": \"HID_8\" },\n { \"input\": \"GLFW_KEY_9\", \"output\": \"HID_9\" },\n { \"input\": \"GLFW_KEY_SEMICOLON\", \"output\": \"HID_COLON\" },\n { \"input\": \"GLFW_KEY_EQUAL\", \"output\": \"HID_PLUS\" },\n { \"input\": \"GLFW_KEY_A\", \"output\": \"HID_A\" },\n { \"input\": \"GLFW_KEY_B\", \"output\": \"HID_B\" },\n { \"input\": \"GLFW_KEY_C\", \"output\": \"HID_C\" },\n { \"input\": \"GLFW_KEY_D\", \"output\": \"HID_D\" },\n { \"input\": \"GLFW_KEY_E\", \"output\": \"HID_E\" },\n { \"input\": \"GLFW_KEY_F\", \"output\": \"HID_F\" },\n { \"input\": \"GLFW_KEY_G\", \"output\": \"HID_G\" },\n { \"input\": \"GLFW_KEY_H\", \"output\": \"HID_H\" },\n { \"input\": \"GLFW_KEY_I\", \"output\": \"HID_I\" },\n { \"input\": \"GLFW_KEY_J\", \"output\": \"HID_J\" },\n { \"input\": \"GLFW_KEY_K\", \"output\": \"HID_K\" },\n { \"input\": \"GLFW_KEY_L\", \"output\": \"HID_L\" },\n { \"input\": \"GLFW_KEY_M\", \"output\": \"HID_M\" },\n { \"input\": \"GLFW_KEY_N\", \"output\": \"HID_N\" },\n { \"input\": \"GLFW_KEY_O\", \"output\": \"HID_O\" },\n { \"input\": \"GLFW_KEY_P\", \"output\": \"HID_P\" },\n { \"input\": \"GLFW_KEY_Q\", \"output\": \"HID_Q\" },\n { \"input\": \"GLFW_KEY_R\", \"output\": \"HID_R\" },\n { \"input\": \"GLFW_KEY_S\", \"output\": \"HID_S\" },\n { \"input\": \"GLFW_KEY_T\", \"output\": \"HID_T\" },\n { \"input\": \"GLFW_KEY_U\", \"output\": \"HID_U\" },\n { \"input\": \"GLFW_KEY_V\", \"output\": \"HID_V\" },\n { \"input\": \"GLFW_KEY_W\", \"output\": \"HID_W\" },\n { \"input\": \"GLFW_KEY_X\", \"output\": \"HID_X\" },\n { \"input\": \"GLFW_KEY_Y\", \"output\": \"HID_Y\" },\n { \"input\": \"GLFW_KEY_Z\", \"output\": \"HID_Z\" },\n { \"input\": \"GLFW_KEY_LEFT_BRACKET\", \"output\": \"HID_OPEN_BRACKET\" },\n { \"input\": \"GLFW_KEY_BACKSLASH\", \"output\": \"HID_3\", \"output_shift\": true },\n { \"input\": \"GLFW_KEY_BACKSLASH\", \"input_shift\": true, \"output\": \"HID_TILDE\", \"output_shift\": true },\n { \"input\": \"GLFW_KEY_RIGHT_BRACKET\", \"output\": \"HID_CLOSE_BRACKET\" },\n { \"input\": \"GLFW_KEY_GRAVE_ACCENT\", \"output\": \"HID_TILDE\" },\n { \"input\": \"GLFW_KEY_WORLD_1\", \"output\": \"\" },\n { \"input\": \"GLFW_KEY_WORLD_2\", \"output\": \"\" },\n { \"input\": \"GLFW_KEY_ESCAPE\", \"output\": \"HID_ESCAPE\" },\n { \"input\": \"GLFW_KEY_ENTER\", \"output\": \"HID_ENTER\" },\n { \"input\": \"GLFW_KEY_TAB\", \"output\": \"HID_TAB\" },\n { \"input\": \"GLFW_KEY_BACKSPACE\", \"output\": \"HID_BACKSPACE\" },\n { \"input\": \"GLFW_KEY_INSERT\", \"output\": \"HID_INSERT\" },\n { \"input\": \"GLFW_KEY_DELETE\", \"output\": \"HID_DELETE\" },\n { \"input\": \"GLFW_KEY_RIGHT\", \"output\": \"HID_RIGHT\" },\n { \"input\": \"GLFW_KEY_LEFT\", \"output\": \"HID_LEFT\" },\n { \"input\": \"GLFW_KEY_DOWN\", \"output\": \"HID_DOWN\" },\n { \"input\": \"GLFW_KEY_UP\", \"output\": \"HID_UP\" },\n { \"input\": \"GLFW_KEY_PAGE_UP\", \"output\": \"HID_PAGEUP\" },\n { \"input\": \"GLFW_KEY_PAGE_DOWN\", \"output\": \"HID_PAGEDOWN\" },\n { \"input\": \"GLFW_KEY_HOME\", \"output\": \"HID_HOME\" },\n { \"input\": \"GLFW_KEY_END\", \"output\": \"HID_END\" },\n { \"input\": \"GLFW_KEY_CAPS_LOCK\", \"output\": \"HID_CAPS_LOCK\" },\n { \"input\": \"GLFW_KEY_SCROLL_LOCK\", \"output\": \"HID_SCROLL_LOCK\" },\n { \"input\": \"GLFW_KEY_NUM_LOCK\", \"output\": \"HID_KEYPAD_NUM_LOCK\" },\n { \"input\": \"GLFW_KEY_PRINT_SCREEN\", \"output\": \"HID_PRINTSCREEN\" },\n { \"input\": \"GLFW_KEY_PAUSE\", \"output\": \"HID_PAUSE\" },\n { \"input\": \"GLFW_KEY_F1\", \"output\": \"HID_F1\" },\n { \"input\": \"GLFW_KEY_F2\", \"output\": \"HID_F2\" },\n { \"input\": \"GLFW_KEY_F3\", \"output\": \"HID_F3\" },\n { \"input\": \"GLFW_KEY_F4\", \"output\": \"HID_F4\" },\n { \"input\": \"GLFW_KEY_F5\", \"output\": \"HID_F5\" },\n { \"input\": \"GLFW_KEY_F6\", \"output\": \"HID_F6\" },\n { \"input\": \"GLFW_KEY_F7\", \"output\": \"HID_F7\" },\n { \"input\": \"GLFW_KEY_F8\", \"output\": \"HID_F8\" },\n { \"input\": \"GLFW_KEY_F9\", \"output\": \"HID_F9\" },\n { \"input\": \"GLFW_KEY_F10\", \"output\": \"HID_F10\" },\n { \"input\": \"GLFW_KEY_F11\", \"output\": \"HID_F11\" },\n { \"input\": \"GLFW_KEY_F12\", \"output\": \"HID_F12\" },\n { \"input\": \"GLFW_KEY_F13\", \"output\": \"HID_F13\" },\n { \"input\": \"GLFW_KEY_F14\", \"output\": \"HID_F14\" },\n { \"input\": \"GLFW_KEY_F15\", \"output\": \"HID_F15\" },\n { \"input\": \"GLFW_KEY_F16\", \"output\": \"HID_F16\" },\n { \"input\": \"GLFW_KEY_F17\", \"output\": \"HID_F17\" },\n { \"input\": \"GLFW_KEY_F18\", \"output\": \"HID_F18\" },\n { \"input\": \"GLFW_KEY_F19\", \"output\": \"HID_F19\" },\n { \"input\": \"GLFW_KEY_F20\", \"output\": \"HID_F20\" },\n { \"input\": \"GLFW_KEY_F21\", \"output\": \"HID_F21\" },\n { \"input\": \"GLFW_KEY_F22\", \"output\": \"HID_F22\" },\n { \"input\": \"GLFW_KEY_F23\", \"output\": \"HID_F23\" },\n { \"input\": \"GLFW_KEY_F24\", \"output\": \"HID_F24\" },\n { \"input\": \"GLFW_KEY_KP_0\", \"output\": \"HID_KEYPAD_0\" },\n { \"input\": \"GLFW_KEY_KP_1\", \"output\": \"HID_KEYPAD_1\" },\n { \"input\": \"GLFW_KEY_KP_2\", \"output\": \"HID_KEYPAD_2\" },\n { \"input\": \"GLFW_KEY_KP_3\", \"output\": \"HID_KEYPAD_3\" },\n { \"input\": \"GLFW_KEY_KP_4\", \"output\": \"HID_KEYPAD_4\" },\n { \"input\": \"GLFW_KEY_KP_5\", \"output\": \"HID_KEYPAD_5\" },\n { \"input\": \"GLFW_KEY_KP_6\", \"output\": \"HID_KEYPAD_6\" },\n { \"input\": \"GLFW_KEY_KP_7\", \"output\": \"HID_KEYPAD_7\" },\n { \"input\": \"GLFW_KEY_KP_8\", \"output\": \"HID_KEYPAD_8\" },\n { \"input\": \"GLFW_KEY_KP_9\", \"output\": \"HID_KEYPAD_9\" },\n { \"input\": \"GLFW_KEY_KP_DECIMAL\", \"output\": \"HID_KEYPAD_DECIMAL\" },\n { \"input\": \"GLFW_KEY_KP_DIVIDE\", \"output\": \"HID_KEYPAD_DIVIDE\" },\n { \"input\": \"GLFW_KEY_KP_MULTIPLY\", \"output\": \"HID_KEYPAD_MULTIPLY\" },\n { \"input\": \"GLFW_KEY_KP_SUBTRACT\", \"output\": \"HID_KEYPAD_MINUS\" },\n { \"input\": \"GLFW_KEY_KP_ADD\", \"output\": \"HID_KEYPAD_PLUS\" },\n { \"input\": \"GLFW_KEY_KP_ENTER\", \"output\": \"HID_KEYPAD_ENTER\" },\n { \"input\": \"GLFW_KEY_KP_EQUAL\", \"output\": \"\" }\n ]\n}" }, { "path": "res/keymaps/us-dvorak.json", "content": "{\n \"name\": \"US Dvorak\",\n \"keymap\": [\n { \"input\": \"GLFW_KEY_SPACE\", \"output\": \"HID_SPACEBAR\" },\n { \"input\": \"GLFW_KEY_APOSTROPHE\", \"output\": \"HID_UNDERSCORE\" },\n { \"input\": \"GLFW_KEY_COMMA\", \"output\": \"HID_W\" },\n { \"input\": \"GLFW_KEY_MINUS\", \"output\": \"HID_OPEN_BRACKET\" },\n { \"input\": \"GLFW_KEY_PERIOD\", \"output\": \"HID_V\" },\n { \"input\": \"GLFW_KEY_SLASH\", \"output\": \"HID_Z\" },\n { \"input\": \"GLFW_KEY_0\", \"output\": \"HID_0\" },\n { \"input\": \"GLFW_KEY_1\", \"output\": \"HID_1\" },\n { \"input\": \"GLFW_KEY_2\", \"output\": \"HID_2\" },\n { \"input\": \"GLFW_KEY_3\", \"output\": \"HID_3\" },\n { \"input\": \"GLFW_KEY_4\", \"output\": \"HID_4\" },\n { \"input\": \"GLFW_KEY_5\", \"output\": \"HID_5\" },\n { \"input\": \"GLFW_KEY_6\", \"output\": \"HID_6\" },\n { \"input\": \"GLFW_KEY_7\", \"output\": \"HID_7\" },\n { \"input\": \"GLFW_KEY_8\", \"output\": \"HID_8\" },\n { \"input\": \"GLFW_KEY_9\", \"output\": \"HID_9\" },\n { \"input\": \"GLFW_KEY_SEMICOLON\", \"output\": \"HID_S\" },\n { \"input\": \"GLFW_KEY_EQUAL\", \"output\": \"HID_CLOSE_BRACKET\" },\n { \"input\": \"GLFW_KEY_A\", \"output\": \"HID_A\" },\n { \"input\": \"GLFW_KEY_B\", \"output\": \"HID_X\" },\n { \"input\": \"GLFW_KEY_C\", \"output\": \"HID_J\" },\n { \"input\": \"GLFW_KEY_D\", \"output\": \"HID_E\" },\n { \"input\": \"GLFW_KEY_E\", \"output\": \"HID_DOT\" },\n { \"input\": \"GLFW_KEY_F\", \"output\": \"HID_U\" },\n { \"input\": \"GLFW_KEY_G\", \"output\": \"HID_I\" },\n { \"input\": \"GLFW_KEY_H\", \"output\": \"HID_D\" },\n { \"input\": \"GLFW_KEY_I\", \"output\": \"HID_C\" },\n { \"input\": \"GLFW_KEY_J\", \"output\": \"HID_H\" },\n { \"input\": \"GLFW_KEY_K\", \"output\": \"HID_T\" },\n { \"input\": \"GLFW_KEY_L\", \"output\": \"HID_N\" },\n { \"input\": \"GLFW_KEY_M\", \"output\": \"HID_M\" },\n { \"input\": \"GLFW_KEY_N\", \"output\": \"HID_B\" },\n { \"input\": \"GLFW_KEY_O\", \"output\": \"HID_R\" },\n { \"input\": \"GLFW_KEY_P\", \"output\": \"HID_L\" },\n { \"input\": \"GLFW_KEY_Q\", \"output\": \"HID_QUOTE\" },\n { \"input\": \"GLFW_KEY_R\", \"output\": \"HID_P\" },\n { \"input\": \"GLFW_KEY_S\", \"output\": \"HID_O\" },\n { \"input\": \"GLFW_KEY_T\", \"output\": \"HID_Y\" },\n { \"input\": \"GLFW_KEY_U\", \"output\": \"HID_G\" },\n { \"input\": \"GLFW_KEY_V\", \"output\": \"HID_K\" },\n { \"input\": \"GLFW_KEY_W\", \"output\": \"HID_COMMA\" },\n { \"input\": \"GLFW_KEY_X\", \"output\": \"HID_Q\" },\n { \"input\": \"GLFW_KEY_Y\", \"output\": \"HID_F\" },\n { \"input\": \"GLFW_KEY_Z\", \"output\": \"HID_COLON\" },\n { \"input\": \"GLFW_KEY_LEFT_BRACKET\", \"output\": \"HID_SLASH\" },\n { \"input\": \"GLFW_KEY_BACKSLASH\", \"output\": \"HID_BACKSLASH\" },\n { \"input\": \"GLFW_KEY_RIGHT_BRACKET\", \"output\": \"HID_PLUS\" },\n { \"input\": \"GLFW_KEY_GRAVE_ACCENT\", \"output\": \"HID_TILDE\" },\n { \"input\": \"GLFW_KEY_WORLD_1\", \"output\": \"\" },\n { \"input\": \"GLFW_KEY_WORLD_2\", \"output\": \"\" },\n { \"input\": \"GLFW_KEY_ESCAPE\", \"output\": \"HID_ESCAPE\" },\n { \"input\": \"GLFW_KEY_ENTER\", \"output\": \"HID_ENTER\" },\n { \"input\": \"GLFW_KEY_TAB\", \"output\": \"HID_TAB\" },\n { \"input\": \"GLFW_KEY_BACKSPACE\", \"output\": \"HID_BACKSPACE\" },\n { \"input\": \"GLFW_KEY_INSERT\", \"output\": \"HID_INSERT\" },\n { \"input\": \"GLFW_KEY_DELETE\", \"output\": \"HID_DELETE\" },\n { \"input\": \"GLFW_KEY_RIGHT\", \"output\": \"HID_RIGHT\" },\n { \"input\": \"GLFW_KEY_LEFT\", \"output\": \"HID_LEFT\" },\n { \"input\": \"GLFW_KEY_DOWN\", \"output\": \"HID_DOWN\" },\n { \"input\": \"GLFW_KEY_UP\", \"output\": \"HID_UP\" },\n { \"input\": \"GLFW_KEY_PAGE_UP\", \"output\": \"HID_PAGEUP\" },\n { \"input\": \"GLFW_KEY_PAGE_DOWN\", \"output\": \"HID_PAGEDOWN\" },\n { \"input\": \"GLFW_KEY_HOME\", \"output\": \"HID_HOME\" },\n { \"input\": \"GLFW_KEY_END\", \"output\": \"HID_END\" },\n { \"input\": \"GLFW_KEY_CAPS_LOCK\", \"output\": \"HID_CAPS_LOCK\" },\n { \"input\": \"GLFW_KEY_SCROLL_LOCK\", \"output\": \"HID_SCROLL_LOCK\" },\n { \"input\": \"GLFW_KEY_NUM_LOCK\", \"output\": \"HID_KEYPAD_NUM_LOCK\" },\n { \"input\": \"GLFW_KEY_PRINT_SCREEN\", \"output\": \"HID_PRINTSCREEN\" },\n { \"input\": \"GLFW_KEY_PAUSE\", \"output\": \"HID_PAUSE\" },\n { \"input\": \"GLFW_KEY_F1\", \"output\": \"HID_F1\" },\n { \"input\": \"GLFW_KEY_F2\", \"output\": \"HID_F2\" },\n { \"input\": \"GLFW_KEY_F3\", \"output\": \"HID_F3\" },\n { \"input\": \"GLFW_KEY_F4\", \"output\": \"HID_F4\" },\n { \"input\": \"GLFW_KEY_F5\", \"output\": \"HID_F5\" },\n { \"input\": \"GLFW_KEY_F6\", \"output\": \"HID_F6\" },\n { \"input\": \"GLFW_KEY_F7\", \"output\": \"HID_F7\" },\n { \"input\": \"GLFW_KEY_F8\", \"output\": \"HID_F8\" },\n { \"input\": \"GLFW_KEY_F9\", \"output\": \"HID_F9\" },\n { \"input\": \"GLFW_KEY_F10\", \"output\": \"HID_F10\" },\n { \"input\": \"GLFW_KEY_F11\", \"output\": \"HID_F11\" },\n { \"input\": \"GLFW_KEY_F12\", \"output\": \"HID_F12\" },\n { \"input\": \"GLFW_KEY_F13\", \"output\": \"HID_F13\" },\n { \"input\": \"GLFW_KEY_F14\", \"output\": \"HID_F14\" },\n { \"input\": \"GLFW_KEY_F15\", \"output\": \"HID_F15\" },\n { \"input\": \"GLFW_KEY_F16\", \"output\": \"HID_F16\" },\n { \"input\": \"GLFW_KEY_F17\", \"output\": \"HID_F17\" },\n { \"input\": \"GLFW_KEY_F18\", \"output\": \"HID_F18\" },\n { \"input\": \"GLFW_KEY_F19\", \"output\": \"HID_F19\" },\n { \"input\": \"GLFW_KEY_F20\", \"output\": \"HID_F20\" },\n { \"input\": \"GLFW_KEY_F21\", \"output\": \"HID_F21\" },\n { \"input\": \"GLFW_KEY_F22\", \"output\": \"HID_F22\" },\n { \"input\": \"GLFW_KEY_F23\", \"output\": \"HID_F23\" },\n { \"input\": \"GLFW_KEY_F24\", \"output\": \"HID_F24\" },\n { \"input\": \"GLFW_KEY_KP_0\", \"output\": \"HID_KEYPAD_0\" },\n { \"input\": \"GLFW_KEY_KP_1\", \"output\": \"HID_KEYPAD_1\" },\n { \"input\": \"GLFW_KEY_KP_2\", \"output\": \"HID_KEYPAD_2\" },\n { \"input\": \"GLFW_KEY_KP_3\", \"output\": \"HID_KEYPAD_3\" },\n { \"input\": \"GLFW_KEY_KP_4\", \"output\": \"HID_KEYPAD_4\" },\n { \"input\": \"GLFW_KEY_KP_5\", \"output\": \"HID_KEYPAD_5\" },\n { \"input\": \"GLFW_KEY_KP_6\", \"output\": \"HID_KEYPAD_6\" },\n { \"input\": \"GLFW_KEY_KP_7\", \"output\": \"HID_KEYPAD_7\" },\n { \"input\": \"GLFW_KEY_KP_8\", \"output\": \"HID_KEYPAD_8\" },\n { \"input\": \"GLFW_KEY_KP_9\", \"output\": \"HID_KEYPAD_9\" },\n { \"input\": \"GLFW_KEY_KP_DECIMAL\", \"output\": \"HID_KEYPAD_DECIMAL\" },\n { \"input\": \"GLFW_KEY_KP_DIVIDE\", \"output\": \"HID_KEYPAD_DIVIDE\" },\n { \"input\": \"GLFW_KEY_KP_MULTIPLY\", \"output\": \"HID_KEYPAD_MULTIPLY\" },\n { \"input\": \"GLFW_KEY_KP_SUBTRACT\", \"output\": \"HID_KEYPAD_MINUS\" },\n { \"input\": \"GLFW_KEY_KP_ADD\", \"output\": \"HID_KEYPAD_PLUS\" },\n { \"input\": \"GLFW_KEY_KP_ENTER\", \"output\": \"HID_KEYPAD_ENTER\" },\n { \"input\": \"GLFW_KEY_KP_EQUAL\", \"output\": \"\" }\n ]\n}" }, { "path": "res/keymaps/us-qwerty.json", "content": "{\n \"name\": \"US Qwerty\",\n \"keymap\": [\n { \"input\": \"GLFW_KEY_SPACE\", \"output\": \"HID_SPACEBAR\" },\n { \"input\": \"GLFW_KEY_APOSTROPHE\", \"output\": \"HID_QUOTE\" },\n { \"input\": \"GLFW_KEY_COMMA\", \"output\": \"HID_COMMA\" },\n { \"input\": \"GLFW_KEY_MINUS\", \"output\": \"HID_UNDERSCORE\" },\n { \"input\": \"GLFW_KEY_PERIOD\", \"output\": \"HID_DOT\" },\n { \"input\": \"GLFW_KEY_SLASH\", \"output\": \"HID_SLASH\" },\n { \"input\": \"GLFW_KEY_0\", \"output\": \"HID_0\" },\n { \"input\": \"GLFW_KEY_1\", \"output\": \"HID_1\" },\n { \"input\": \"GLFW_KEY_2\", \"output\": \"HID_2\" },\n { \"input\": \"GLFW_KEY_3\", \"output\": \"HID_3\" },\n { \"input\": \"GLFW_KEY_4\", \"output\": \"HID_4\" },\n { \"input\": \"GLFW_KEY_5\", \"output\": \"HID_5\" },\n { \"input\": \"GLFW_KEY_6\", \"output\": \"HID_6\" },\n { \"input\": \"GLFW_KEY_7\", \"output\": \"HID_7\" },\n { \"input\": \"GLFW_KEY_8\", \"output\": \"HID_8\" },\n { \"input\": \"GLFW_KEY_9\", \"output\": \"HID_9\" },\n { \"input\": \"GLFW_KEY_SEMICOLON\", \"output\": \"HID_COLON\" },\n { \"input\": \"GLFW_KEY_EQUAL\", \"output\": \"HID_PLUS\" },\n { \"input\": \"GLFW_KEY_A\", \"output\": \"HID_A\" },\n { \"input\": \"GLFW_KEY_B\", \"output\": \"HID_B\" },\n { \"input\": \"GLFW_KEY_C\", \"output\": \"HID_C\" },\n { \"input\": \"GLFW_KEY_D\", \"output\": \"HID_D\" },\n { \"input\": \"GLFW_KEY_E\", \"output\": \"HID_E\" },\n { \"input\": \"GLFW_KEY_F\", \"output\": \"HID_F\" },\n { \"input\": \"GLFW_KEY_G\", \"output\": \"HID_G\" },\n { \"input\": \"GLFW_KEY_H\", \"output\": \"HID_H\" },\n { \"input\": \"GLFW_KEY_I\", \"output\": \"HID_I\" },\n { \"input\": \"GLFW_KEY_J\", \"output\": \"HID_J\" },\n { \"input\": \"GLFW_KEY_K\", \"output\": \"HID_K\" },\n { \"input\": \"GLFW_KEY_L\", \"output\": \"HID_L\" },\n { \"input\": \"GLFW_KEY_M\", \"output\": \"HID_M\" },\n { \"input\": \"GLFW_KEY_N\", \"output\": \"HID_N\" },\n { \"input\": \"GLFW_KEY_O\", \"output\": \"HID_O\" },\n { \"input\": \"GLFW_KEY_P\", \"output\": \"HID_P\" },\n { \"input\": \"GLFW_KEY_Q\", \"output\": \"HID_Q\" },\n { \"input\": \"GLFW_KEY_R\", \"output\": \"HID_R\" },\n { \"input\": \"GLFW_KEY_S\", \"output\": \"HID_S\" },\n { \"input\": \"GLFW_KEY_T\", \"output\": \"HID_T\" },\n { \"input\": \"GLFW_KEY_U\", \"output\": \"HID_U\" },\n { \"input\": \"GLFW_KEY_V\", \"output\": \"HID_V\" },\n { \"input\": \"GLFW_KEY_W\", \"output\": \"HID_W\" },\n { \"input\": \"GLFW_KEY_X\", \"output\": \"HID_X\" },\n { \"input\": \"GLFW_KEY_Y\", \"output\": \"HID_Y\" },\n { \"input\": \"GLFW_KEY_Z\", \"output\": \"HID_Z\" },\n { \"input\": \"GLFW_KEY_LEFT_BRACKET\", \"output\": \"HID_OPEN_BRACKET\" },\n { \"input\": \"GLFW_KEY_BACKSLASH\", \"output\": \"HID_BACKSLASH\" },\n { \"input\": \"GLFW_KEY_RIGHT_BRACKET\", \"output\": \"HID_CLOSE_BRACKET\" },\n { \"input\": \"GLFW_KEY_GRAVE_ACCENT\", \"output\": \"HID_TILDE\" },\n { \"input\": \"GLFW_KEY_WORLD_1\", \"output\": \"\" },\n { \"input\": \"GLFW_KEY_WORLD_2\", \"output\": \"\" },\n { \"input\": \"GLFW_KEY_ESCAPE\", \"output\": \"HID_ESCAPE\" },\n { \"input\": \"GLFW_KEY_ENTER\", \"output\": \"HID_ENTER\" },\n { \"input\": \"GLFW_KEY_TAB\", \"output\": \"HID_TAB\" },\n { \"input\": \"GLFW_KEY_BACKSPACE\", \"output\": \"HID_BACKSPACE\" },\n { \"input\": \"GLFW_KEY_INSERT\", \"output\": \"HID_INSERT\" },\n { \"input\": \"GLFW_KEY_DELETE\", \"output\": \"HID_DELETE\" },\n { \"input\": \"GLFW_KEY_RIGHT\", \"output\": \"HID_RIGHT\" },\n { \"input\": \"GLFW_KEY_LEFT\", \"output\": \"HID_LEFT\" },\n { \"input\": \"GLFW_KEY_DOWN\", \"output\": \"HID_DOWN\" },\n { \"input\": \"GLFW_KEY_UP\", \"output\": \"HID_UP\" },\n { \"input\": \"GLFW_KEY_PAGE_UP\", \"output\": \"HID_PAGEUP\" },\n { \"input\": \"GLFW_KEY_PAGE_DOWN\", \"output\": \"HID_PAGEDOWN\" },\n { \"input\": \"GLFW_KEY_HOME\", \"output\": \"HID_HOME\" },\n { \"input\": \"GLFW_KEY_END\", \"output\": \"HID_END\" },\n { \"input\": \"GLFW_KEY_CAPS_LOCK\", \"output\": \"HID_CAPS_LOCK\" },\n { \"input\": \"GLFW_KEY_SCROLL_LOCK\", \"output\": \"HID_SCROLL_LOCK\" },\n { \"input\": \"GLFW_KEY_NUM_LOCK\", \"output\": \"HID_KEYPAD_NUM_LOCK\" },\n { \"input\": \"GLFW_KEY_PRINT_SCREEN\", \"output\": \"HID_PRINTSCREEN\" },\n { \"input\": \"GLFW_KEY_PAUSE\", \"output\": \"HID_PAUSE\" },\n { \"input\": \"GLFW_KEY_F1\", \"output\": \"HID_F1\" },\n { \"input\": \"GLFW_KEY_F2\", \"output\": \"HID_F2\" },\n { \"input\": \"GLFW_KEY_F3\", \"output\": \"HID_F3\" },\n { \"input\": \"GLFW_KEY_F4\", \"output\": \"HID_F4\" },\n { \"input\": \"GLFW_KEY_F5\", \"output\": \"HID_F5\" },\n { \"input\": \"GLFW_KEY_F6\", \"output\": \"HID_F6\" },\n { \"input\": \"GLFW_KEY_F7\", \"output\": \"HID_F7\" },\n { \"input\": \"GLFW_KEY_F8\", \"output\": \"HID_F8\" },\n { \"input\": \"GLFW_KEY_F9\", \"output\": \"HID_F9\" },\n { \"input\": \"GLFW_KEY_F10\", \"output\": \"HID_F10\" },\n { \"input\": \"GLFW_KEY_F11\", \"output\": \"HID_F11\" },\n { \"input\": \"GLFW_KEY_F12\", \"output\": \"HID_F12\" },\n { \"input\": \"GLFW_KEY_F13\", \"output\": \"HID_F13\" },\n { \"input\": \"GLFW_KEY_F14\", \"output\": \"HID_F14\" },\n { \"input\": \"GLFW_KEY_F15\", \"output\": \"HID_F15\" },\n { \"input\": \"GLFW_KEY_F16\", \"output\": \"HID_F16\" },\n { \"input\": \"GLFW_KEY_F17\", \"output\": \"HID_F17\" },\n { \"input\": \"GLFW_KEY_F18\", \"output\": \"HID_F18\" },\n { \"input\": \"GLFW_KEY_F19\", \"output\": \"HID_F19\" },\n { \"input\": \"GLFW_KEY_F20\", \"output\": \"HID_F20\" },\n { \"input\": \"GLFW_KEY_F21\", \"output\": \"HID_F21\" },\n { \"input\": \"GLFW_KEY_F22\", \"output\": \"HID_F22\" },\n { \"input\": \"GLFW_KEY_F23\", \"output\": \"HID_F23\" },\n { \"input\": \"GLFW_KEY_F24\", \"output\": \"HID_F24\" },\n { \"input\": \"GLFW_KEY_KP_0\", \"output\": \"HID_KEYPAD_0\" },\n { \"input\": \"GLFW_KEY_KP_1\", \"output\": \"HID_KEYPAD_1\" },\n { \"input\": \"GLFW_KEY_KP_2\", \"output\": \"HID_KEYPAD_2\" },\n { \"input\": \"GLFW_KEY_KP_3\", \"output\": \"HID_KEYPAD_3\" },\n { \"input\": \"GLFW_KEY_KP_4\", \"output\": \"HID_KEYPAD_4\" },\n { \"input\": \"GLFW_KEY_KP_5\", \"output\": \"HID_KEYPAD_5\" },\n { \"input\": \"GLFW_KEY_KP_6\", \"output\": \"HID_KEYPAD_6\" },\n { \"input\": \"GLFW_KEY_KP_7\", \"output\": \"HID_KEYPAD_7\" },\n { \"input\": \"GLFW_KEY_KP_8\", \"output\": \"HID_KEYPAD_8\" },\n { \"input\": \"GLFW_KEY_KP_9\", \"output\": \"HID_KEYPAD_9\" },\n { \"input\": \"GLFW_KEY_KP_DECIMAL\", \"output\": \"HID_KEYPAD_DECIMAL\" },\n { \"input\": \"GLFW_KEY_KP_DIVIDE\", \"output\": \"HID_KEYPAD_DIVIDE\" },\n { \"input\": \"GLFW_KEY_KP_MULTIPLY\", \"output\": \"HID_KEYPAD_MULTIPLY\" },\n { \"input\": \"GLFW_KEY_KP_SUBTRACT\", \"output\": \"HID_KEYPAD_MINUS\" },\n { \"input\": \"GLFW_KEY_KP_ADD\", \"output\": \"HID_KEYPAD_PLUS\" },\n { \"input\": \"GLFW_KEY_KP_ENTER\", \"output\": \"HID_KEYPAD_ENTER\" },\n { \"input\": \"GLFW_KEY_KP_EQUAL\", \"output\": \"\" }\n ]\n}" }, { "path": "src/ansible/AnsibleModule.hpp", "content": "#pragma once\n\n#include \"LibAVR32Module.hpp\"\n#include \"AnsibleModule.hpp\"\n\nusing namespace rack;\n\nstruct AnsibleModule : LibAVR32Module\n{\n enum ParamIds\n {\n KEY1_PARAM,\n KEY2_PARAM,\n MODE_PARAM,\n USB_PARAM,\n NUM_PARAMS\n };\n\n enum InputIds\n {\n IN1_INPUT,\n IN2_INPUT,\n NUM_INPUTS\n };\n\n enum OutputIds\n {\n TR1_OUTPUT,\n TR2_OUTPUT,\n TR3_OUTPUT,\n TR4_OUTPUT,\n CV1_OUTPUT,\n CV2_OUTPUT,\n CV3_OUTPUT,\n CV4_OUTPUT,\n NUM_OUTPUTS\n };\n\n enum LightIds\n {\n MODE_YELLOW_LIGHT,\n MODE_WHITE_LIGHT,\n TR1_LIGHT,\n TR2_LIGHT,\n TR3_LIGHT,\n TR4_LIGHT,\n CV1_LIGHT,\n CV2_LIGHT,\n CV3_LIGHT,\n CV4_LIGHT,\n NUM_LIGHTS\n };\n\n rack::dsp::SchmittTrigger inputTriggers[2];\n\n AnsibleModule()\n : LibAVR32Module(\"ansible\", \"ansible\")\n {\n config(NUM_PARAMS, NUM_INPUTS, NUM_OUTPUTS, NUM_LIGHTS);\n configButton(KEY1_PARAM, \"KEY 1\");\n configButton(KEY2_PARAM, \"KEY 2\");\n configButton(MODE_PARAM, \"MODE\");\n configInput(IN1_INPUT, \"IN 1\");\n configInput(IN2_INPUT, \"IN 2\");\n configOutput(TR1_OUTPUT, \"TR 1\");\n configOutput(TR2_OUTPUT, \"TR 2\");\n configOutput(TR3_OUTPUT, \"TR 3\");\n configOutput(TR4_OUTPUT, \"TR 4\");\n configOutput(CV1_OUTPUT, \"CV 1\");\n configOutput(CV2_OUTPUT, \"CV 2\");\n configOutput(CV3_OUTPUT, \"CV 3\");\n configOutput(CV4_OUTPUT, \"CV 4\");\n configButton(USB_PARAM, \"USB Device Port\");\n\n setDeviceConnectionParam(USB_PARAM);\n }\n\n void processInputs(const ProcessArgs& args) override\n {\n bool in1Normal = !inputs[IN1_INPUT].isConnected();\n if (in1Normal != firmware.getGPIO(B10))\n {\n firmware.setGPIO(B10, in1Normal);\n firmware.triggerInterrupt(1);\n }\n\n for (int i = 0; i < 2; i++)\n {\n inputTriggers[i].process(\n inputs[IN1_INPUT + i].getVoltage(),\n triggerLowThreshold,\n triggerHighThreshold);\n\n if (inputTriggers[i].isHigh() != firmware.getGPIO(B08 + i))\n {\n firmware.setGPIO(B08 + i, inputTriggers[i].isHigh());\n firmware.triggerInterrupt(6 + i);\n }\n }\n\n bool key1Button = params[KEY1_PARAM].getValue() == 0;\n if (key1Button != firmware.getGPIO(B07))\n {\n firmware.setGPIO(B07, key1Button);\n }\n\n bool key2Button = params[KEY2_PARAM].getValue() == 0;\n if (key2Button != firmware.getGPIO(B06))\n {\n firmware.setGPIO(B06, key2Button);\n }\n\n bool modeButton = params[MODE_PARAM].getValue() == 0;\n if (modeButton != firmware.getGPIO(NMI))\n {\n firmware.setGPIO(NMI, modeButton);\n }\n }\n\n void processOutputs(const ProcessArgs& args) override\n {\n float cv1 = dacToVolts(firmware.getDAC(2));\n float cv2 = dacToVolts(firmware.getDAC(3));\n float cv3 = dacToVolts(firmware.getDAC(0));\n float cv4 = dacToVolts(firmware.getDAC(1));\n\n bool tr1 = firmware.getGPIO(B02);\n bool tr2 = firmware.getGPIO(B03);\n bool tr3 = firmware.getGPIO(B04);\n bool tr4 = firmware.getGPIO(B05);\n\n // Update bicolor mode light from B00/B01\n lights[MODE_YELLOW_LIGHT].setSmoothBrightness(firmware.getGPIO(B00) * 0.7, args.sampleTime);\n lights[MODE_WHITE_LIGHT].setSmoothBrightness(firmware.getGPIO(B01) * 0.4, args.sampleTime);\n\n // Update normal lights\n lights[TR1_LIGHT].setSmoothBrightness(tr1, args.sampleTime);\n lights[TR2_LIGHT].setSmoothBrightness(tr2, args.sampleTime);\n lights[TR3_LIGHT].setSmoothBrightness(tr3, args.sampleTime);\n lights[TR4_LIGHT].setSmoothBrightness(tr4, args.sampleTime);\n lights[CV1_LIGHT].setSmoothBrightness(cv1 / 10.0, args.sampleTime);\n lights[CV2_LIGHT].setSmoothBrightness(cv2 / 10.0, args.sampleTime);\n lights[CV3_LIGHT].setSmoothBrightness(cv3 / 10.0, args.sampleTime);\n lights[CV4_LIGHT].setSmoothBrightness(cv4 / 10.0, args.sampleTime);\n\n // Update output jacks from GPIO & DAC\n outputs[TR1_OUTPUT].setVoltage(tr1 * 8.0);\n outputs[TR2_OUTPUT].setVoltage(tr2 * 8.0);\n outputs[TR3_OUTPUT].setVoltage(tr3 * 8.0);\n outputs[TR4_OUTPUT].setVoltage(tr4 * 8.0);\n outputs[CV1_OUTPUT].setVoltage(cv1);\n outputs[CV2_OUTPUT].setVoltage(cv2);\n outputs[CV3_OUTPUT].setVoltage(cv3);\n outputs[CV4_OUTPUT].setVoltage(cv4);\n }\n};\n" }, { "path": "src/ansible/AnsibleWidget.hpp", "content": "#pragma once\n\n#include \"AnsibleModule.hpp\"\n#include \"HoldableButton.hpp\"\n#include \"LibAVR32ModuleWidget.hpp\"\n#include \"USBAJack.hpp\"\n#include \"YellowWhiteLight.hpp\"\n\nusing namespace rack;\n\nstruct AnsibleWidget : LibAVR32ModuleWidget\n{\n AnsibleWidget(AnsibleModule* module)\n {\n setModule(module);\n\n box.size = Vec(15 * 6, 380);\n\n {\n auto panel = new ThemedSvgPanel();\n panel->setBackground(\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/ansible.svg\")),\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/ansible-dark.svg\")));\n panel->box.size = box.size;\n addChild(panel);\n }\n\n addChild(createWidget(Vec(RACK_GRID_WIDTH / 2, 0)));\n addChild(createWidget(Vec(RACK_GRID_WIDTH / 2, RACK_GRID_HEIGHT - RACK_GRID_WIDTH)));\n\n addParam(createParam(Vec(7, 333), module, AnsibleModule::USB_PARAM));\n addParam(createParam(Vec(62, 336), module, AnsibleModule::MODE_PARAM));\n addParam(createParam(Vec(19, 256), module, AnsibleModule::KEY1_PARAM));\n addParam(createParam(Vec(54, 256), module, AnsibleModule::KEY2_PARAM));\n\n addOutput(createOutput(Vec(15, 54), module, AnsibleModule::TR1_OUTPUT));\n addOutput(createOutput(Vec(50, 75), module, AnsibleModule::CV1_OUTPUT));\n addOutput(createOutput(Vec(15, 92), module, AnsibleModule::TR2_OUTPUT));\n addOutput(createOutput(Vec(50, 111), module, AnsibleModule::CV2_OUTPUT));\n addOutput(createOutput(Vec(15, 130), module, AnsibleModule::TR3_OUTPUT));\n addOutput(createOutput(Vec(50, 149), module, AnsibleModule::CV3_OUTPUT));\n addOutput(createOutput(Vec(15, 168), module, AnsibleModule::TR4_OUTPUT));\n addOutput(createOutput(Vec(50, 187), module, AnsibleModule::CV4_OUTPUT));\n\n addInput(createInput(Vec(15, 286), module, AnsibleModule::IN1_INPUT));\n addInput(createInput(Vec(50, 286), module, AnsibleModule::IN2_INPUT));\n\n addChild(createLight>(Vec(3, 72), module, AnsibleModule::TR1_LIGHT));\n addChild(createLight>(Vec(77, 72), module, AnsibleModule::CV1_LIGHT));\n addChild(createLight>(Vec(3, 110), module, AnsibleModule::TR2_LIGHT));\n addChild(createLight>(Vec(77, 110), module, AnsibleModule::CV2_LIGHT));\n addChild(createLight>(Vec(3, 148), module, AnsibleModule::TR3_LIGHT));\n addChild(createLight>(Vec(77, 148), module, AnsibleModule::CV3_LIGHT));\n addChild(createLight>(Vec(3, 186), module, AnsibleModule::TR4_LIGHT));\n addChild(createLight>(Vec(77, 186), module, AnsibleModule::CV4_LIGHT));\n addChild(createLight>(Vec(77, 326), module, AnsibleModule::MODE_YELLOW_LIGHT));\n }\n};\n" }, { "path": "src/common/core/ActionQueue.hpp", "content": "#pragma once\n\n#include \"rack.hpp\"\n#include \n\ntypedef std::function Action;\ntypedef rack::dsp::RingBuffer ActionQueue;" }, { "path": "src/common/core/FirmwareManager.cpp", "content": "#include \"FirmwareManager.hpp\"\n#include \"rack.hpp\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n\nnamespace fs = ghc::filesystem;\n\nextern rack::Plugin* pluginInstance;\n\n#if ARCH_LIN\n#define LIB_EXTENSION \".so\"\n#define PATH_SEPARATOR '/'\n#define MODULE_HANDLE_TYPE void*\n#elif ARCH_WIN\n#define LIB_EXTENSION \".dll\"\n#define PATH_SEPARATOR '\\\\'\n#define MODULE_HANDLE_TYPE HINSTANCE\n#elif ARCH_MAC\n#define LIB_EXTENSION \".dylib\"\n#define PATH_SEPARATOR '/'\n#define MODULE_HANDLE_TYPE void*\n#endif\n\n#if ARCH_WIN\n\n#include \n#include \n\n#define GET_PROC_ADDRESS(returntype, name, argslist) \\\n fw_fn_hardware_##name = reinterpret_cast( \\\n reinterpret_cast( \\\n GetProcAddress(handle, \"hardware_\" #name))); \\\n if (!fw_fn_hardware_##name) \\\n { \\\n WARN(\"Failed to find symbol 'hardware\" #name \"'\"); \\\n return false; \\\n }\n\n#elif ARCH_LIN || ARCH_MAC\n\n#include \n#include \n#include \n\n#define GET_PROC_ADDRESS(returntype, name, argslist) \\\n fw_fn_hardware_##name = reinterpret_cast( \\\n reinterpret_cast( \\\n dlsym(handle, \"hardware_\" #name))); \\\n if (!fw_fn_hardware_##name) \\\n { \\\n WARN(\"Failed to find symbol 'hardware_\" #name \"'\"); \\\n return false; \\\n }\n\n#endif\n\n#define DECLARE_PROC(returntype, name, argslist) \\\n typedef returntype(*fw_fn_hardware_##name##_t) argslist; \\\n fw_fn_hardware_##name##_t fw_fn_hardware_##name;\n\nstruct FirmwareManagerImpl\n{\n#ifdef MOCK_API\n#undef MOCK_API\n#endif\n#define MOCK_API DECLARE_PROC\n#include \"mock_hardware_api.h\"\n\n double clockPeriod;\n double clockPhase;\n\n std::string tempLibraryFolder;\n std::string tempLibraryFile;\n\n MODULE_HANDLE_TYPE handle;\n\n static std::unordered_set alreadyLoadedPaths;\n\n FirmwareManagerImpl()\n {\n clockPhase = 0.0;\n clockPeriod = 0.001;\n }\n\n ~FirmwareManagerImpl()\n {\n#if ARCH_WIN\n FreeLibrary(handle);\n#elif ARCH_LIN || ARCH_MAC\n dlclose(handle);\n#endif\n\n if (!tempLibraryFile.empty())\n {\n unlink(tempLibraryFile.c_str());\n }\n if (!tempLibraryFolder.empty())\n {\n rmdir(tempLibraryFolder.c_str());\n }\n }\n\n bool load(std::string firmwareName)\n {\n using namespace rack;\n\n std::string librarySource;\n librarySource = rack::asset::plugin(pluginInstance, \"res/firmware/\" + firmwareName + LIB_EXTENSION);\n\n std::error_code ec;\n if (!fs::is_regular_file(fs::status(librarySource, ec)))\n {\n WARN(\"Requested firmware not found or invalid\");\n return false;\n }\n\n std::string libraryToLoad = librarySource;\n\n // If we have already loaded this firmware at least once, create a temp copy so it will have its own address space\n if (alreadyLoadedPaths.find(libraryToLoad) != alreadyLoadedPaths.end())\n {\n bool success = false;\n\n#if ARCH_WIN\n char* tempdir = 0;\n (tempdir = getenv(\"TMPDIR\")) || (tempdir = getenv(\"TMP\")) || (tempdir = getenv(\"TEMP\")) || (tempdir = getenv(\"TEMPDIR\")) || (tempdir = getenv(\"LOCALAPPDATA\"));\n\n if (tempdir != 0)\n {\n char* name = tmpnam(NULL);\n if (name != 0)\n {\n tempLibraryFolder = tempdir;\n if (tempLibraryFolder.back() != PATH_SEPARATOR && name[0] != PATH_SEPARATOR)\n {\n tempLibraryFolder += PATH_SEPARATOR;\n }\n tempLibraryFolder += std::string(name);\n\n if (mkdir(tempLibraryFolder.c_str()) == 0)\n {\n success = true;\n }\n }\n }\n\n#elif ARCH_LIN || ARCH_MAC\n\n char* name = tmpnam(NULL);\n if (name != 0)\n {\n tempLibraryFolder = name;\n\n if (mkdir(tempLibraryFolder.c_str(), 0777) == 0)\n {\n success = true;\n }\n }\n\n#endif\n\n if (!success)\n {\n WARN(\"Could not create temporary folder for firmware\");\n return false;\n }\n\n tempLibraryFile = tempLibraryFolder + PATH_SEPARATOR + \"monome_vcvrack_firmware\" + LIB_EXTENSION;\n\n // DEBUG(\"Creating new temporary firmware instance at %s\", tempLibraryFile.c_str());\n\n {\n std::ifstream src(librarySource, std::ios::binary);\n std::ofstream dst(tempLibraryFile, std::ios::binary);\n dst << src.rdbuf();\n }\n\n libraryToLoad = tempLibraryFile;\n }\n else\n {\n // first time load, record it.\n alreadyLoadedPaths.insert(libraryToLoad);\n }\n\n INFO(\"Loading module firmware from %s\", libraryToLoad.c_str());\n\n#if ARCH_WIN\n\n int wideLength = MultiByteToWideChar(CP_UTF8, 0, libraryToLoad.c_str(), -1, nullptr, 0);\n if (wideLength > 0)\n {\n std::vector wideLibName(wideLength);\n wideLength = MultiByteToWideChar(CP_UTF8, 0, libraryToLoad.c_str(), -1, wideLibName.data(), wideLength);\n if (wideLength > 0)\n {\n SetErrorMode(SEM_NOOPENFILEERRORBOX | SEM_FAILCRITICALERRORS);\n handle = LoadLibraryW(wideLibName.data());\n SetErrorMode(0);\n }\n }\n\n if (!handle)\n {\n int error = GetLastError();\n WARN(\"Failed to load library %s: %d\", libraryToLoad.c_str(), error);\n return false;\n }\n\n#elif ARCH_LIN || ARCH_MAC\n\n handle = dlopen(libraryToLoad.c_str(), RTLD_NOW | RTLD_LOCAL);\n if (!handle)\n {\n WARN(\"Failed to load library %s: %s\", libraryToLoad.c_str(), dlerror());\n return false;\n }\n\n#endif\n\n#ifdef MOCK_API\n#undef MOCK_API\n#endif\n#define MOCK_API GET_PROC_ADDRESS\n#include \"mock_hardware_api.h\"\n\n // cache this so we don't have to call it constantly\n clockPeriod = fw_fn_hardware_getClockPeriod();\n\n return true;\n }\n};\n\nstd::unordered_set FirmwareManagerImpl::alreadyLoadedPaths;\n\nFirmwareManager::FirmwareManager()\n : impl(nullptr)\n{\n}\n\nFirmwareManager::~FirmwareManager()\n{\n delete impl;\n}\n\nconst std::string FirmwareManager::getLibExtension()\n{\n return LIB_EXTENSION;\n}\n\nbool FirmwareManager::load(std::string firmwareName)\n{\n delete impl;\n impl = new FirmwareManagerImpl();\n if (!impl->load(firmwareName))\n {\n delete impl;\n impl = nullptr;\n WARN(\"Could not load firmware %s\", firmwareName.c_str());\n return false;\n }\n loadedName = firmwareName;\n return true;\n}\n\nvoid FirmwareManager::init()\n{\n if (impl)\n {\n impl->fw_fn_hardware_init();\n }\n}\n\nvoid FirmwareManager::step()\n{\n if (impl)\n {\n impl->fw_fn_hardware_step();\n }\n}\n\nbool FirmwareManager::getGPIO(uint32_t pin)\n{\n if (impl)\n {\n return impl->fw_fn_hardware_getGPIO(pin);\n }\n else\n {\n return false;\n }\n}\n\nvoid FirmwareManager::setGPIO(uint32_t pin, bool value)\n{\n if (impl)\n {\n impl->fw_fn_hardware_setGPIO(pin, value);\n }\n}\n\nuint16_t FirmwareManager::getDAC(int channel)\n{\n if (impl)\n {\n return impl->fw_fn_hardware_getDAC(channel);\n }\n else\n {\n return 0;\n }\n}\n\nvoid FirmwareManager::setADC(int channel, uint16_t value)\n{\n if (impl)\n {\n impl->fw_fn_hardware_setADC(channel, value);\n }\n}\n\nvoid FirmwareManager::postEvent(uint32_t type, uint32_t data)\n{\n if (impl)\n {\n impl->fw_fn_hardware_postEvent(type, data);\n }\n}\n\nvoid FirmwareManager::serialConnectionChange(bool connected, uint8_t type, uint8_t protocol, uint8_t width, uint8_t height)\n{\n if (impl)\n {\n return impl->fw_fn_hardware_serialConnectionChange(connected, type, protocol, width, height);\n }\n}\n\nint FirmwareManager::readSerial(uint8_t** pbuf, uint8_t* pcount)\n{\n if (impl)\n {\n return impl->fw_fn_hardware_readSerial(pbuf, pcount);\n }\n else\n {\n *pbuf = NULL;\n *pcount = 0;\n return -1;\n }\n}\n\nint FirmwareManager::writeSerial(uint8_t* buf, uint8_t byteCount)\n{\n if (impl)\n {\n return impl->fw_fn_hardware_writeSerial(buf, byteCount);\n }\n else \n {\n return -1;\n }\n}\n\nvoid FirmwareManager::triggerInterrupt(int interrupt)\n{\n if (impl)\n {\n impl->fw_fn_hardware_triggerInterrupt(interrupt);\n }\n}\n\nvoid FirmwareManager::setClockPeriod(float seconds)\n{\n if (impl)\n {\n impl->clockPeriod = seconds;\n }\n}\n\nvoid FirmwareManager::advanceClock(float seconds)\n{\n if (impl)\n {\n impl->clockPhase += seconds;\n if (impl->clockPhase > impl->clockPeriod)\n {\n impl->clockPhase -= impl->clockPeriod;\n impl->fw_fn_hardware_triggerInterrupt(0);\n }\n }\n}\n\nvoid FirmwareManager::readNVRAM(void** ptr, uint32_t* size)\n{\n if (impl)\n {\n impl->fw_fn_hardware_readNVRAM(ptr, size);\n }\n}\n\nvoid FirmwareManager::writeNVRAM(const void* ptr, uint32_t size)\n{\n if (impl)\n {\n impl->fw_fn_hardware_writeNVRAM(ptr, size);\n }\n}\n\nvoid FirmwareManager::readVRAM(void** ptr, uint32_t* size)\n{\n if (impl)\n {\n impl->fw_fn_hardware_readVRAM(ptr, size);\n }\n}\n\nvoid FirmwareManager::writeVRAM(const void* ptr, uint32_t size)\n{\n if (impl)\n {\n impl->fw_fn_hardware_writeVRAM(ptr, size);\n }\n}\n\nvoid FirmwareManager::setScreenBuffer(uint8_t* ptr)\n{\n if (impl)\n {\n impl->fw_fn_hardware_setScreenBuffer(ptr);\n }\n}\n\nvoid FirmwareManager::hidConnect()\n{\n if (impl)\n {\n impl->fw_fn_hardware_hidConnect();\n }\n}\n\nvoid FirmwareManager::hidDisconnect()\n{\n if (impl)\n {\n impl->fw_fn_hardware_hidDisconnect();\n }\n}\n\nvoid FirmwareManager::hidMessage(uint8_t key, uint8_t mod, bool held, bool release)\n{\n if (impl)\n {\n impl->fw_fn_hardware_hidMessage(key, mod, held, release);\n }\n}\n\nvoid FirmwareManager::iiUpdateFollowerData(uint8_t device, uint8_t param, uint16_t value)\n{\n if (impl)\n {\n impl->fw_fn_hardware_iiUpdateFollowerData(device, param, value);\n }\n}\n\nbool FirmwareManager::iiPopMessage(uint8_t* addr, uint8_t* data, uint8_t* length)\n{\n if (impl)\n {\n return impl->fw_fn_hardware_iiPopMessage(addr, data, length);\n }\n return false;\n}\n\nvoid FirmwareManager::serializePreset(tt_serializer_t* stream, uint8_t preset_num)\n{\n if (impl)\n {\n return impl->fw_fn_hardware_serializePreset(stream, preset_num);\n }\n}\n\nvoid FirmwareManager::deserializePreset(tt_deserializer_t* stream, uint8_t preset_num, bool clearExisting)\n{\n if (impl)\n {\n return impl->fw_fn_hardware_deserializePreset(stream, preset_num, clearExisting);\n }\n}\n\nvoid FirmwareManager::getVersion(char* buffer)\n{\n if (impl)\n {\n return impl->fw_fn_hardware_getVersion(buffer);\n }\n}\n\ndouble FirmwareManager::getClockPeriod()\n{\n if (impl)\n {\n return impl->fw_fn_hardware_getClockPeriod();\n }\n else\n {\n return 0.001;\n }\n}\n" }, { "path": "src/common/core/FirmwareManager.hpp", "content": "#include \n#include \n\n\n#pragma once\n\n#ifdef MOCK_API\n#undef MOCK_API\n#endif\n#define MOCK_API(RET, METHODNAME, ARGS)\n#include \"mock_hardware_api.h\"\n#define MOCK_API_SKIP_TYPES\n\nstruct FirmwareManager\n{\n FirmwareManager();\n ~FirmwareManager();\n\n const std::string getLibExtension();\n\n bool load(std::string firmwareName);\n void unload();\n\n const std::string& getLoadedName() const { return loadedName; }\n\n void setClockPeriod(float seconds);\n void advanceClock(float seconds);\n\n#ifdef MOCK_API\n#undef MOCK_API\n#endif\n#define MOCK_API(RET, METHODNAME, ARGS) RET METHODNAME ARGS\n\n#include \"mock_hardware_api.h\"\n\n struct FirmwareManagerImpl* impl;\nprotected:\n std::string loadedName;\n};" }, { "path": "src/common/core/GridConnection/GridConnection.cpp", "content": "#include \"GridConnection.hpp\"\n#include \"SerialOscInterface.hpp\"\n\nvoid GridConnectionManager::registerGrid(Grid* grid)\n{\n grids.insert(grid);\n\n // Check if there's a consumer with a saved connection looking for this grid\n IGridConsumer* consumerToConnect = nullptr;\n for (auto consumer : consumers)\n {\n if (!isConnected(consumer) && grid->getDevice().id == consumer->gridGetLastDeviceId(true))\n {\n consumerToConnect = consumer;\n break;\n }\n }\n\n if (consumerToConnect != nullptr)\n {\n connect(grid, consumerToConnect);\n }\n}\n\nvoid GridConnectionManager::registerGridConsumer(IGridConsumer* consumer)\n{\n consumers.insert(consumer);\n\n // Check if this consumer had a saved connection to an already-registered grid\n Grid* gridToConnect = nullptr;\n for (auto grid : grids)\n {\n if (!isConnected(grid->getDevice().id) && consumer->gridGetLastDeviceId(true) == grid->getDevice().id)\n {\n gridToConnect = grid;\n break;\n }\n }\n\n if (gridToConnect != nullptr)\n {\n connect(gridToConnect, consumer);\n }\n}\n\nvoid GridConnectionManager::deregisterGrid(std::string id, bool deleteGrid)\n{\n for (Grid* grid : grids)\n {\n if (grid->getDevice().id == id)\n {\n disconnect(grid);\n grids.erase(grid);\n\n // Connection manager owns the pointer, so deleteGrid should always be true,\n // unless this is being called from the Grid destructor\n if (deleteGrid)\n {\n delete grid;\n }\n return;\n }\n }\n}\n\nvoid GridConnectionManager::deregisterGridConsumer(IGridConsumer* consumer)\n{\n disconnect(consumer);\n consumers.erase(consumer);\n}\n\nvoid GridConnectionManager::connect(Grid* grid, IGridConsumer* consumer)\n{\n disconnect(consumer, true);\n disconnect(grid, true);\n\n consumerToGridMap[consumer] = grid;\n idToConsumerMap[grid->getDevice().id] = consumer;\n consumer->gridConnected(grid);\n\n // If serialosc is managing the grid (e.g. it's a hardware grid), inform serialosc about new grid owner\n auto port = grid->getDevice().port;\n auto so = SerialOscInterface::get();\n if (port > 0 && so != nullptr && so->driver != nullptr)\n {\n so->driver->sendDevicePrefixMessage(port);\n so->driver->sendDevicePortMessage(port);\n }\n}\n\nbool GridConnectionManager::isConnected(IGridConsumer* consumer)\n{\n return consumerToGridMap.find(consumer) != consumerToGridMap.end();\n}\n\nbool GridConnectionManager::isConnected(std::string id)\n{\n return idToConsumerMap.find(id) != idToConsumerMap.end();\n}\n\nvoid GridConnectionManager::disconnect(Grid* grid, bool ownerChanged)\n{\n if (grid)\n {\n grid->clearAll();\n auto iter = idToConsumerMap.find(grid->getDevice().id);\n if (iter != idToConsumerMap.end())\n {\n auto consumer = iter->second;\n consumer->gridDisconnected(ownerChanged);\n idToConsumerMap.erase(grid->getDevice().id);\n consumerToGridMap.erase(consumer);\n }\n }\n}\n\nvoid GridConnectionManager::disconnect(IGridConsumer* consumer, bool ownerChanged)\n{\n if (consumer)\n {\n auto iter = consumerToGridMap.find(consumer);\n if (iter != consumerToGridMap.end())\n {\n Grid* grid = iter->second;\n if (grid)\n {\n grid->clearAll();\n consumer->gridDisconnected(ownerChanged);\n consumerToGridMap.erase(consumer);\n idToConsumerMap.erase(grid->getDevice().id);\n }\n }\n }\n}\n\nvoid GridConnectionManager::toggleConnection(Grid* grid, IGridConsumer* consumer)\n{\n if (consumer && consumer->gridGetDevice() == grid)\n {\n disconnect(consumer, true);\n consumer->setLastDeviceId(\"\");\n }\n else\n {\n connect(grid, consumer);\n }\n}\n\nvoid GridConnectionManager::dispatchButtonMessage(MonomeDevice* device, int x, int y, bool state)\n{\n auto iter = idToConsumerMap.find(device->id);\n if (iter != idToConsumerMap.end())\n {\n iter->second->gridButtonEvent(x, y, state);\n }\n}\n\nvoid GridConnectionManager::dispatchEncDeltaMessage(MonomeDevice* device, int n, int d)\n{\n auto iter = idToConsumerMap.find(device->id);\n if (iter != idToConsumerMap.end())\n {\n iter->second->encDeltaEvent(n, d);\n }\n}\n\nconst std::set& GridConnectionManager::getGrids()\n{\n return grids;\n}\n\nGridConnectionManager& GridConnectionManager::get()\n{\n static GridConnectionManager instance;\n return instance;\n}\n" }, { "path": "src/common/core/GridConnection/GridConnection.hpp", "content": "#pragma once\n\n#include \"MonomeDevice.h\"\n#include \n#include \n#include \n\nstruct SerialOscInterface;\n\nstruct Grid\n{\n virtual ~Grid() {}\n virtual const MonomeDevice& getDevice() = 0;\n virtual void updateRow(int x_offset, int y, uint8_t bitfield) = 0;\n virtual void updateQuadrant(int x, int y, uint8_t* leds) = 0;\n virtual void updateRing(int n, uint8_t leds[64]) = 0;\n virtual void clearAll() = 0;\n virtual bool isHardware() = 0;\n};\n\nstruct IGridConsumer\n{\n virtual ~IGridConsumer() {}\n virtual void gridConnected(Grid* grid) = 0;\n virtual void gridDisconnected(bool ownerChanged) = 0;\n virtual std::string gridGetCurrentDeviceId() = 0;\n virtual std::string gridGetLastDeviceId(bool owned) = 0;\n virtual void setLastDeviceId(std::string id) = 0;\n virtual void gridButtonEvent(int x, int y, bool state) = 0;\n virtual void encDeltaEvent(int n, int d) = 0;\n virtual Grid* gridGetDevice() = 0;\n};\n\nstruct GridConnectionManager final\n{\n // Only call these from the UI thread\n void registerGrid(Grid* grid);\n void registerGridConsumer(IGridConsumer* consumer);\n void deregisterGrid(std::string id, bool deleteGrid = false);\n void deregisterGridConsumer(IGridConsumer* consumer);\n\n void connect(Grid* grid, IGridConsumer* consumer);\n bool isConnected(IGridConsumer* consumer);\n bool isConnected(std::string id);\n void disconnect(Grid* grid, bool ownerChanged = false);\n void disconnect(IGridConsumer* consumer, bool ownerChanged = false);\n void toggleConnection(Grid* grid, IGridConsumer* consumer);\n\n void dispatchButtonMessage(MonomeDevice* device, int x, int y, bool state);\n void dispatchEncDeltaMessage(MonomeDevice* device, int n, int d);\n const std::set& getGrids();\n\n static GridConnectionManager& get();\n\nprivate:\n GridConnectionManager() = default;\n ~GridConnectionManager() = default;\n GridConnectionManager(const GridConnectionManager&) = delete;\n GridConnectionManager& operator=(const GridConnectionManager&) = delete;\n GridConnectionManager(GridConnectionManager&&) = delete;\n GridConnectionManager&& operator=(const GridConnectionManager&&) = delete;\n\n std::set consumers;\n std::set grids;\n std::map idToConsumerMap;\n std::map consumerToGridMap;\n};" }, { "path": "src/common/core/GridConnection/GridConnectionMenu.cpp", "content": "#include \"GridConnectionMenu.hpp\"\n#include \"SerialOscInterface.hpp\"\n\nusing namespace rack;\n\nstruct ConnectGridItem : rack::ui::MenuItem\n{\n Grid* grid;\n IGridConsumer* consumer;\n ActionQueue* actionQueue;\n\n void onAction(const rack::event::Action& e) override\n {\n if (actionQueue)\n {\n auto thisGrid = grid;\n auto thisConsumer = consumer;\n\n actionQueue->push([thisGrid, thisConsumer]() {\n GridConnectionManager::get().toggleConnection(thisGrid, thisConsumer);\n });\n }\n }\n};\n\nvoid menuUserReacquireGrid(IGridConsumer* consumer, std::string lastDeviceId, ActionQueue* actionQueue)\n{\n for (Grid* grid : GridConnectionManager::get().getGrids())\n {\n if (lastDeviceId == grid->getDevice().id)\n {\n if (actionQueue)\n {\n actionQueue->push([grid, consumer]() {\n GridConnectionManager::get().connect(grid, consumer);\n });\n }\n return;\n }\n }\n}\n\nvoid appendDeviceConnectionMenu(rack::Menu* menu, IGridConsumer* consumer, ActionQueue* actionQueue, bool hardwareOnly)\n{\n std::string currentConnectedDeviceId = consumer->gridGetCurrentDeviceId();\n std::string lastConnectedDeviceId = consumer->gridGetLastDeviceId(false);\n\n menu->addChild(construct(&MenuLabel::text, \"Device Connection\"));\n\n if (SerialOscInterface::get()->isServiceDetected())\n {\n menu->addChild(\n construct(\n &MenuLabel::text,\n \"serialosc version \" + SerialOscInterface::get()->getServiceVersion()));\n }\n else\n {\n menu->addChild(\n createMenuItem(\"└ serialosc service not detected, click here to install\", \"\",\n [=]()\n {\n system::openBrowser(\"https://monome.org/docs/serialosc/setup/\");\n }));\n }\n\n // enumerate registered grid devices\n int deviceCount = 0;\n bool preferredDeviceFound = false;\n for (Grid* grid : GridConnectionManager::get().getGrids())\n {\n if (hardwareOnly && !grid->isHardware())\n {\n continue;\n }\n\n auto connectItem = new ConnectGridItem();\n connectItem->text = \"└ \" + grid->getDevice().type + \" (\" + grid->getDevice().id + \") \";\n\n auto rightText = \"\";\n if (currentConnectedDeviceId == grid->getDevice().id)\n {\n rightText = \"✔\";\n preferredDeviceFound = true;\n }\n else if (currentConnectedDeviceId == \"\" && lastConnectedDeviceId == grid->getDevice().id)\n {\n rightText = \"⋯\";\n preferredDeviceFound = true;\n }\n\n connectItem->rightText = rightText;\n connectItem->grid = grid;\n connectItem->actionQueue = actionQueue;\n connectItem->consumer = consumer;\n\n menu->addChild(connectItem);\n deviceCount++;\n }\n\n if (deviceCount == 0)\n {\n std::string message = hardwareOnly ? \"no hardware devices found\" : \"no hardware or virtual devices found\";\n menu->addChild(construct(&MenuLabel::text, \" (\" + message + \")\"));\n }\n\n if (currentConnectedDeviceId == \"\" && lastConnectedDeviceId != \"\")\n {\n if (preferredDeviceFound)\n {\n menu->addChild(createMenuItem(\"Reacquire grid\", \"\", [=]()\n {\n if (lastConnectedDeviceId != \"\")\n {\n menuUserReacquireGrid(consumer, lastConnectedDeviceId, actionQueue);\n }\n }\n ));\n }\n else\n {\n menu->addChild(construct(&MenuLabel::text, \"Can't reacquire grid (\" + lastConnectedDeviceId + \" not found)\"));\n }\n }\n}" }, { "path": "src/common/core/GridConnection/GridConnectionMenu.hpp", "content": "#pragma once\n\n#include \"rack.hpp\"\n#include \"GridConnection.hpp\"\n#include \"ActionQueue.hpp\"\n\nvoid appendDeviceConnectionMenu(rack::Menu* menu, IGridConsumer* consumer, ActionQueue* queue, bool hardwareOnly = false);" }, { "path": "src/common/core/GridConnection/GridConsumerBase.cpp", "content": "#include \"GridConsumerBase.hpp\"\n\nGridConsumerBase::GridConsumerBase()\n : lastConnectedDeviceId(\"\")\n , currentConnectedDeviceId(\"\")\n , gridConnection(nullptr)\n{\n\n}\n\nvoid GridConsumerBase::gridConnected(Grid* newConnection)\n{\n gridConnection = newConnection;\n if (gridConnection)\n {\n std::string id = gridConnection->getDevice().id;\n lastConnectedDeviceId = id;\n currentConnectedDeviceId = id;\n connectionOwned = true;\n }\n}\n\nvoid GridConsumerBase::gridDisconnected(bool ownerChanged)\n{\n gridConnection = nullptr;\n currentConnectedDeviceId = \"\";\n \n if (ownerChanged)\n {\n connectionOwned = false;\n }\n}\n\nstd::string GridConsumerBase::gridGetCurrentDeviceId()\n{\n return currentConnectedDeviceId;\n}\n\nstd::string GridConsumerBase::gridGetLastDeviceId(bool owned)\n{\n if (owned && !connectionOwned)\n {\n return \"\";\n }\n\n return lastConnectedDeviceId;\n}\n\nvoid GridConsumerBase::setLastDeviceId(std::string id)\n{\n lastConnectedDeviceId = id;\n}\n\nGrid* GridConsumerBase::gridGetDevice()\n{\n return gridConnection;\n}\n\nvoid GridConsumerBase::userReacquireGrid()\n{\n if (lastConnectedDeviceId != \"\" && gridConnection == nullptr)\n {\n for (Grid* grid : GridConnectionManager::get().getGrids())\n {\n if (gridGetLastDeviceId(false) == grid->getDevice().id)\n {\n GridConnectionManager::get().connect(grid, this);\n return;\n }\n }\n }\n}\n\nvoid GridConsumerBase::saveGridConnectionToJson(json_t* rootJ)\n{\n std::string deviceId = lastConnectedDeviceId;\n if (gridConnection)\n {\n deviceId = gridConnection->getDevice().id;\n }\n json_object_set_new(rootJ, \"connectedDeviceId\", json_string(deviceId.c_str()));\n json_object_set_new(rootJ, \"connectionOwned\", json_boolean(connectionOwned));\n}\n\nvoid GridConsumerBase::loadGridConnectionFromJson(json_t* rootJ)\n{\n json_t* id = json_object_get(rootJ, \"connectedDeviceId\");\n if (id)\n {\n lastConnectedDeviceId = json_string_value(id);\n }\n\n json_t* owned = json_object_get(rootJ, \"connectionOwned\");\n if (owned)\n {\n connectionOwned = json_boolean_value(owned);\n }\n}" }, { "path": "src/common/core/GridConnection/GridConsumerBase.hpp", "content": "#pragma once\n\n#include \"GridConnection.hpp\"\n#include \"rack.hpp\"\n\nstruct GridConsumerBase : public IGridConsumer\n{\n // IGridConsumer partial implementation; child classes implement gridButtonEvent/encDeltaEvent\n void gridConnected(Grid* grid) override;\n void gridDisconnected(bool ownerChanged) override;\n std::string gridGetCurrentDeviceId() override;\n std::string gridGetLastDeviceId(bool owned) override;\n virtual void setLastDeviceId(std::string id) override;\n Grid* gridGetDevice() override;\n\n GridConsumerBase();\n virtual ~GridConsumerBase() {};\n\n void userReacquireGrid();\n\n void saveGridConnectionToJson(json_t* rootJ);\n void loadGridConnectionFromJson(json_t* rootJ);\n\n std::string lastConnectedDeviceId;\n std::string currentConnectedDeviceId;\n bool connectionOwned;\n\nprotected:\n Grid* gridConnection;\n};" }, { "path": "src/common/core/GridConnection/SerialOscGrid.cpp", "content": "#include \"SerialOscGrid.hpp\"\n#include \"SerialOscInterface.hpp\"\n\nSerialOscGrid::SerialOscGrid(const MonomeDevice* const _device)\n : device(*_device)\n{\n}\n\nconst MonomeDevice& SerialOscGrid::getDevice()\n{\n return device;\n}\n\nvoid SerialOscGrid::updateRow(int x_offset, int y, uint8_t bitfield)\n{\n SerialOscInterface::get()->driver->sendDeviceLedRowCommand(&device, x_offset, y, bitfield);\n}\n\nvoid SerialOscGrid::updateQuadrant(int x, int y, uint8_t* leds)\n{\n if (device.protocol == PROTOCOL_40H)\n {\n uint8_t* p = leds;\n for (int i = 0; i < 8; i++)\n {\n uint8_t bits = 0;\n for (int j = 0; j < 8; j++)\n {\n if (*p++)\n {\n bits |= 1 << j;\n }\n }\n SerialOscInterface::get()->driver->sendDeviceLedRowCommand(&device, 0, i, bits);\n }\n }\n else if (device.protocol == PROTOCOL_SERIES)\n {\n uint8_t* p = leds;\n uint8_t map[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };\n for (int i = 0; i < 8; i++)\n {\n for (int j = 0; j < 8; j++)\n {\n if (*p++)\n {\n map[i] |= 1 << j;\n }\n }\n }\n SerialOscInterface::get()->driver->sendDeviceLedMapCommand(&device, x, y, map);\n }\n else\n {\n SerialOscInterface::get()->driver->sendDeviceLedLevelMapCommand(&device, x, y, leds);\n }\n}\n\nvoid SerialOscGrid::updateRing(int n, uint8_t leds[64])\n{\n SerialOscInterface::get()->driver->sendDeviceRingMapCommand(&device, n, leds);\n}\n\nvoid SerialOscGrid::clearAll()\n{\n SerialOscInterface::get()->driver->sendDeviceLedAllCommand(&device, false);\n}\n" }, { "path": "src/common/core/GridConnection/SerialOscGrid.hpp", "content": "#pragma once\n\n#include \"GridConnection.hpp\"\n#include \"MonomeDevice.h\"\n\nstruct SerialOscGrid : Grid\n{\n SerialOscGrid(const MonomeDevice* const device);\n MonomeDevice device;\n\n const MonomeDevice& getDevice() override;\n void updateRow(int x_offset, int y, uint8_t bitfield) override;\n void updateQuadrant(int x, int y, uint8_t* leds) override;\n void updateRing(int n, uint8_t leds[64]) override;\n void clearAll() override;\n bool isHardware() override { return true; }\n};" }, { "path": "src/common/core/GridConnection/SerialOscInterface.cpp", "content": "#include \"SerialOscInterface.hpp\"\n#include \"SerialOscGrid.hpp\"\n\nSerialOscInterface::SerialOscInterface()\n{\n driver = new SerialOsc(\"rack\", 13000);\n driver->start(this);\n}\n\nSerialOscInterface::~SerialOscInterface()\n{\n driver->stop();\n delete driver;\n}\n\nbool SerialOscInterface::isServiceDetected() const\n{\n return driver->isServiceDetected();\n}\n\nstd::string SerialOscInterface::getServiceVersion() const\n{\n return driver->getVersionString();\n}\n\nvoid SerialOscInterface::deviceFound(const MonomeDevice* const device)\n{\n if (!device)\n {\n return;\n }\n\n // don't register the same device id twice\n for (auto grid : GridConnectionManager::get().getGrids())\n {\n if (grid->getDevice().id == device->id)\n {\n return;\n }\n }\n\n GridConnectionManager::get().registerGrid(new SerialOscGrid(device));\n}\n\nvoid SerialOscInterface::deviceRemoved(const std::string& id)\n{\n GridConnectionManager::get().deregisterGrid(id, true);\n}\n\nvoid SerialOscInterface::buttonPressMessageReceived(MonomeDevice* device, int x, int y, bool state)\n{\n GridConnectionManager::get().dispatchButtonMessage(device, x, y, state);\n}\n\nvoid SerialOscInterface::encDeltaMessageReceived(MonomeDevice* device, int n, int d)\n{\n GridConnectionManager::get().dispatchEncDeltaMessage(device, n, d);\n}\n\nSerialOscInterface* SerialOscInterface::get()\n{\n static SerialOscInterface* instance = new SerialOscInterface();\n return instance;\n}" }, { "path": "src/common/core/GridConnection/SerialOscInterface.hpp", "content": "#include \"SerialOsc.h\"\n\nstruct SerialOscInterface final : public SerialOsc::Listener\n{\n // constructor is private\n ~SerialOscInterface();\n\n bool isServiceDetected() const;\n std::string getServiceVersion() const;\n\n // SerialOsc::Listener methods\n void deviceFound(const MonomeDevice* const device) override;\n void deviceRemoved(const std::string& id) override;\n void buttonPressMessageReceived(MonomeDevice* device, int x, int y, bool state) override;\n void encDeltaMessageReceived(MonomeDevice* device, int n, int delta) override;\n\n SerialOsc* driver;\n\n static SerialOscInterface* get();\n\nprivate:\n SerialOscInterface();\n SerialOscInterface(const SerialOscInterface&) = delete;\n SerialOscInterface& operator=(const SerialOscInterface&) = delete;\n SerialOscInterface(SerialOscInterface&&) = delete;\n SerialOscInterface&& operator=(const SerialOscInterface&&) = delete;\n};\n" }, { "path": "src/common/core/IIBus.cpp", "content": "#include \"IIBus.h\"\n#include \"LibAVR32Module.hpp\"\n\n#define FADERBANK_II_MAX_VALUE 16383\n\nextern rack::plugin::Model* modelFaderbank;\n\nIIBus::IIBus(LibAVR32Module* leader)\n : leader(leader)\n{\n}\n\nbool IIBus::isFollower(rack::Module* module)\n{\n // Only faderbanks participate in II right now\n return module != nullptr && module->model == modelFaderbank;\n}\n\nvoid IIBus::step()\n{\n if (leader == nullptr)\n {\n return;\n }\n\n // let's tentatively define a bus as an unbroken chain of II-supporting\n // modules directly attached to either the left or right of the leader.\n\n // scan the \"bus\" for eligible modules, starting to the leader's left\n std::vector followers;\n auto module = leader->getLeftExpander().module;\n while (isFollower(module))\n {\n followers.push_back(module);\n module = module->getLeftExpander().module;\n }\n\n // flip the order, so we can prioritize left-to-right\n if (followers.size() > 1)\n {\n std::reverse(followers.begin(), followers.end());\n }\n\n // scan to the leader's right\n module = leader->getRightExpander().module;\n while (isFollower(module))\n {\n followers.push_back(module);\n module = module->getRightExpander().module;\n }\n\n // gather params from all followers\n for (size_t follower = 0; follower < std::min(static_cast(4), followers.size()); follower++)\n {\n for (uint8_t fader = 0; fader < std::min(16, followers[follower]->getNumParams()); fader++)\n {\n auto param = followers[follower]->getParamQuantity(fader);\n if (param)\n {\n uint16_t value = static_cast(param->getScaledValue() * FADERBANK_II_MAX_VALUE);\n leader->firmware.iiUpdateFollowerData(follower + 0x34, fader, value);\n }\n }\n }\n}\n" }, { "path": "src/common/core/IIBus.h", "content": "#pragma once\n\n#include \"rack.hpp\"\n\n#include \n#include \n#include \n\nstruct LibAVR32Module;\n\n// Notes on the work-in-progress implementation of II (monome ecosystem i2c):\n//\n// An i2c module cannot wait for a response to messages. Even if the Rack engine is\n// using multiple threads, a leader and follower may be executing on the same thread.\n//\n// Since the leader will block waiting on a request for data from a follower, we need to\n// have the data ready in advance. Therefore the bus must continuously maintain a data\n// structure accessible to the leader with all data the leader could possibly request.\n\nstruct IIBus\n{\n IIBus(LibAVR32Module* leader);\n bool isFollower(rack::Module* module);\n\n void step();\n\nprotected:\n LibAVR32Module* leader;\n};\n" }, { "path": "src/common/core/LibAVR32Module.cpp", "content": "#include \"LibAVR32Module.hpp\"\n#include \"SerialOscInterface.hpp\"\n#include \"base64.h\"\n#include \n\nLibAVR32Module::LibAVR32Module(std::string firmwarePrefix, std::string defaultFirmwareName)\n : firmwarePrefix(firmwarePrefix)\n , firmwareName(defaultFirmwareName)\n , defaultFirmwareName(defaultFirmwareName)\n , theme(GridTheme::Yellow)\n , usbParamId(-1)\n{\n // make sure serialosc is fully initialized by the time\n // the user needs to interact with it\n SerialOscInterface::get();\n\n dacOffsetVolts = 0.0007;\n triggerHighThreshold = 2.21;\n triggerLowThreshold = 0.8;\n\n inputRate = 2;\n outputRate = 4;\n\n firmware.load(firmwareName);\n firmware.init();\n\n firmware.advanceClock(0.02);\n firmware.step();\n}\n\nLibAVR32Module::~LibAVR32Module()\n{\n GridConnectionManager::get().deregisterGridConsumer(this);\n}\n\nvoid LibAVR32Module::gridConnected(Grid* newConnection)\n{\n if (gridConnection != nullptr)\n {\n firmware.serialConnectionChange(false, 0, 0, 0, 0);\n }\n\n GridConsumerBase::gridConnected(newConnection);\n\n if (gridConnection)\n {\n auto d = gridConnection->getDevice();\n if (d.type == \"monome arc 2\")\n {\n firmware.serialConnectionChange(true, 1, d.protocol, 2, 1);\n }\n else if (d.type.compare(0, 10, \"monome arc\") == 0)\n {\n firmware.serialConnectionChange(true, 1, d.protocol, 4, 1);\n }\n else\n {\n firmware.serialConnectionChange(true, 0, d.protocol, d.width, d.height);\n }\n\n if (usbParamId >= 0)\n {\n params[usbParamId].setValue(1.0);\n }\n }\n}\n\nvoid LibAVR32Module::gridDisconnected(bool ownerChanged)\n{\n GridConsumerBase::gridDisconnected(ownerChanged);\n\n firmware.serialConnectionChange(false, 0, 0, 0, 0);\n\n if (usbParamId >= 0)\n {\n params[usbParamId].setValue(0.0);\n }\n}\n\nvoid LibAVR32Module::gridButtonEvent(int x, int y, bool state)\n{\n // send grid press as serial event\n if (gridConnection)\n {\n switch (gridConnection->getDevice().protocol)\n {\n case PROTOCOL_40H:\n {\n uint8_t msg[2] = {\n (uint8_t)(state ? 0x01 : 0x00),\n (uint8_t)(((0x0F & x) << 4) | (0x0F & y))\n };\n firmware.writeSerial(msg, 2);\n }\n break;\n\n case PROTOCOL_SERIES:\n {\n uint8_t msg[2] = {\n (uint8_t)(state ? 0x00 : 0x10),\n (uint8_t)(((0x0F & x) << 4) | (0x0F & y))\n };\n firmware.writeSerial(msg, 2);\n }\n break;\n\n case PROTOCOL_MEXT:\n {\n uint8_t msg[3] = {\n (uint8_t)(state ? 0x21 : 0x20),\n (uint8_t)x,\n (uint8_t)y\n };\n firmware.writeSerial(msg, 3);\n }\n break;\n\n default:\n break;\n }\n }\n\n // alternative: send grid press directly to event queue\n // performance is surprisingly much worse!\n // uint32_t data = (0xF & x) | ((0xF & y) << 8) | ((state ? 0 : 1) << 16);\n // firmware.postEvent(16 /* kEventMonomeGridKey */, data);\n}\n\nvoid LibAVR32Module::encDeltaEvent(int n, int d)\n{\n if (gridConnection)\n {\n uint8_t msg[3] = {\n (uint8_t)0x50,\n (uint8_t)n,\n (uint8_t)d\n };\n firmware.writeSerial(msg, 3);\n }\n}\n\nvoid LibAVR32Module::readSerialMessages()\n{\n uint8_t* msg;\n uint8_t count;\n\n if (firmware.readSerial(&msg, &count) > 0)\n {\n if ((msg[0] & 0xF0) == 0x70)\n {\n while ((msg[0] & 0xF0) == 0x70 && count >= 2)\n {\n // 40h protocol row update\n uint8_t y = msg[0] & 0x0F;\n uint8_t bitfield = msg[1];\n\n if (gridConnection)\n {\n gridConnection->updateRow(0, y, bitfield);\n }\n\n if (count > 2) // there are more 0x7x two-byte commands in this serial message\n {\n msg += 2;\n count -= 2;\n }\n else\n {\n break;\n }\n }\n }\n else if (msg[0] == 0x1A && count >= 35)\n {\n // mext protocol quadrant update\n uint8_t x = msg[1];\n uint8_t y = msg[2];\n uint8_t leds[64];\n for (int i = 0; i < 32; i++)\n {\n leds[2 * i + 0] = msg[3 + i] >> 4;\n leds[2 * i + 1] = msg[3 + i] & 0xF;\n }\n\n if (gridConnection)\n {\n gridConnection->updateQuadrant(x, y, leds);\n }\n }\n else if ((msg[0] & 0xF0) == 0x80 && count >= 9)\n {\n // series protocol quadrant update\n int x = (msg[0] & 0x1) * 8;\n int y = (msg[0] & 0x2) * 8;\n uint8_t leds[64];\n for (int j = 0; j < 8; j++)\n {\n for (int i = 0; i < 8; i++)\n {\n leds[i + 8 * j] = (msg[1 + j] & (0x1 << i)) ? 15 : 0;\n }\n }\n\n if (gridConnection)\n {\n gridConnection->updateQuadrant(x, y, leds);\n }\n }\n else if (msg[0] == 0x92 && count >= 32)\n {\n if (gridConnection)\n {\n uint8_t leds[64];\n for (int i = 0; i < 32; i++) {\n leds[i * 2] = msg[2 + i] >> 4;\n leds[i * 2 + 1] = msg[2 + i] & 0x0F;\n }\n gridConnection->updateRing(msg[1], leds);\n }\n }\n }\n}\n\nvoid LibAVR32Module::requestReloadFirmware(bool preserveVRAM, bool preserveNVRAM, const std::string& firmwareName)\n{\n audioThreadActions.push([this, preserveVRAM, preserveNVRAM, firmwareName]()\n { this->reloadFirmware(preserveVRAM, preserveNVRAM, firmwareName); });\n}\n\nvoid LibAVR32Module::reloadFirmware(bool preserveVRAM, bool preserveNVRAM, const std::string& newName)\n{\n void *data, *nvram_copy, *vram_copy = 0;\n uint32_t nvram_size, vram_size = 0;\n\n firmwareName = newName.empty() ? firmware.getLoadedName() : newName;\n if (firmwareName != firmware.getLoadedName()) {\n preserveVRAM = false;\n preserveNVRAM = false;\n }\n\n if (preserveNVRAM)\n {\n firmware.readNVRAM(&data, &nvram_size);\n nvram_copy = malloc(nvram_size);\n memcpy(nvram_copy, data, nvram_size);\n }\n\n if (preserveVRAM)\n {\n firmware.readVRAM(&data, &vram_size);\n vram_copy = malloc(vram_size);\n memcpy(vram_copy, data, vram_size);\n }\n\n firmware.load(firmwareName);\n firmware.init();\n firmware.setScreenBuffer(getScreenBuffer());\n\n if (preserveNVRAM)\n {\n firmware.writeNVRAM(nvram_copy, nvram_size);\n free(nvram_copy);\n }\n\n if (preserveVRAM)\n {\n firmware.writeVRAM(vram_copy, vram_size);\n free(vram_copy);\n }\n\n gridConnected(gridConnection);\n}\n\nvoid LibAVR32Module::process(const ProcessArgs& args)\n{\n while (audioThreadActions.size())\n {\n audioThreadActions.shift()();\n }\n\n // Run inputs at 1/2 audio rate by default, configurable in right-click menu\n if (args.frame % inputRate == 0)\n {\n // Module-specific code to bind Rack inputs to GPIO/ADC\n processInputs(args);\n }\n\n // Advance hardware timers\n firmware.advanceClock(args.sampleTime);\n\n // Pump hardware event loop\n firmware.step();\n\n // Run outputs at 1/4 audio rate by default, configurable in right-click menu\n if (args.frame % outputRate == 0)\n {\n // Module-specific code to bind GPIO/DAC to Rack outputs & lights\n processOutputs(args);\n }\n\n // Act on serial output from module to the outside world (grid LEDs, etc.)\n readSerialMessages();\n\n // Keep USB param state in sync with device connection state\n processDeviceConnectionParam();\n}\n\njson_t* LibAVR32Module::dataToJson()\n{\n json_t* rootJ = json_object();\n json_object_set_new(rootJ, \"firmwareName\", json_string(firmwareName.c_str()));\n json_object_set_new(rootJ, \"inputRate\", json_integer(inputRate));\n json_object_set_new(rootJ, \"outputRate\", json_integer(outputRate));\n\n saveGridConnectionToJson(rootJ);\n\n void* data = 0;\n uint32_t size = 0;\n\n firmware.readNVRAM(&data, &size);\n if (data && size > 0)\n {\n json_object_set_new(rootJ, \"nvram\", json_string(base64_encode((unsigned char*)data, size).c_str()));\n }\n\n firmware.readVRAM(&data, &size);\n if (data && size > 0)\n {\n json_object_set_new(rootJ, \"vram\", json_string(base64_encode((unsigned char*)data, size).c_str()));\n }\n\n return rootJ;\n}\n\nvoid LibAVR32Module::dataFromJson(json_t* rootJ)\n{\n loadGridConnectionFromJson(rootJ);\n\n json_t* jsonFirmwareName = json_object_get(rootJ, \"firmwareName\");\n std::string newFirmwareName = jsonFirmwareName ? json_string_value(jsonFirmwareName) : defaultFirmwareName;\n\n if (newFirmwareName != firmwareName)\n {\n reloadFirmware(false, false, newFirmwareName);\n }\n\n void* data = 0;\n uint32_t size = 0;\n json_t* jd;\n\n jd = json_object_get(rootJ, \"nvram\");\n if (jd)\n {\n std::string decoded = base64_decode(json_string_value(jd));\n\n firmware.readNVRAM(&data, &size);\n if (data && size == decoded.length())\n {\n firmware.writeNVRAM((void*)decoded.c_str(), size);\n }\n }\n\n jd = json_object_get(rootJ, \"vram\");\n if (jd)\n {\n std::string decoded = base64_decode(json_string_value(jd));\n\n firmware.readVRAM(&data, &size);\n if (data && size == decoded.length())\n {\n firmware.writeVRAM((void*)decoded.c_str(), size);\n }\n }\n\n jd = json_object_get(rootJ, \"inputRate\");\n if (jd)\n {\n int value = json_integer_value(jd);\n if (value == 1 || value == 2 || value == 4 || value == 8 || value == 16)\n {\n inputRate = value;\n }\n }\n\n jd = json_object_get(rootJ, \"outputRate\");\n if (jd)\n {\n int value = json_integer_value(jd);\n if (value == 1 || value == 2 || value == 4 || value == 8 || value == 16)\n {\n outputRate = value;\n }\n }\n\n GridConnectionManager::get().registerGridConsumer(this);\n}\n\nvoid LibAVR32Module::onReset() {\n rack::engine::Module::onReset();\n reloadFirmware(false);\n}\n\nvoid LibAVR32Module::processDeviceConnectionParam()\n{\n if (usbParamId >= 0)\n {\n float usbParamState = params[usbParamId].getValue();\n if (usbParamState > 0 && gridConnection == nullptr)\n {\n userReacquireGrid();\n }\n\n params[usbParamId].setValue(gridConnection != nullptr ? 1.0 : 0.0);\n }\n}" }, { "path": "src/common/core/LibAVR32Module.hpp", "content": "#include \"FirmwareManager.hpp\"\n#include \"GridConnection.hpp\"\n#include \"GridConsumerBase.hpp\"\n#include \"VirtualGridTheme.hpp\"\n#include \"rack.hpp\"\n#include \"ActionQueue.hpp\"\n\n#pragma once\n\n#define A00 0\n#define A01 1\n#define A02 2\n#define A03 3\n#define A04 4\n#define A05 5\n#define A06 6\n#define A07 7\n#define B00 32\n#define B01 33\n#define B02 34\n#define B03 35\n#define B04 36\n#define B05 37\n#define B06 38\n#define B07 39\n#define B08 40\n#define B09 41\n#define B10 42\n#define B11 43\n#define NMI 13\n\nstruct GridConnection;\n\nstruct LibAVR32Module : rack::engine::Module, GridConsumerBase\n{\n FirmwareManager firmware;\n\n LibAVR32Module(std::string firmwarePrefix, std::string defaultFirmwareName);\n ~LibAVR32Module();\n\n // Rack module methods\n void process(const ProcessArgs& args) override;\n json_t* dataToJson() override;\n void dataFromJson(json_t* rootJ) override;\n void onReset() override;\n\n // MonomeModuleBase virtual methods\n virtual void processInputs(const ProcessArgs& args) = 0;\n virtual void processOutputs(const ProcessArgs& args) = 0;\n\n // Override IGridConsumer methods implemented by GridConsumerBase (and call base impl)\n // TODO: replace this with an event hook system\n virtual void gridConnected(Grid* newConnection) override;\n virtual void gridDisconnected(bool ownerChanged) override;\n // Implement remaining IGridConsumer methods\n virtual void gridButtonEvent(int x, int y, bool state) override;\n virtual void encDeltaEvent(int n, int d) override;\n\n virtual void readSerialMessages();\n void requestReloadFirmware(bool preserveVRAM, bool preserveNVRAM, const std::string& firmwareName = \"\");\n\n float dacToVolts(uint16_t adc);\n uint16_t voltsToAdc(float volts);\n\n std::string firmwarePrefix;\n std::string firmwareName;\n std::string defaultFirmwareName;\n\n int inputRate;\n int outputRate;\n\n GridTheme theme;\n\n virtual uint8_t* getScreenBuffer() { return 0; }\n\nprotected:\n void reloadFirmware(bool preserveVRAM, bool preserveNVRAM = true, const std::string& newFirmware = \"\");\n\n int usbParamId;\n void setDeviceConnectionParam(int paramId) { usbParamId = paramId; }\n void processDeviceConnectionParam();\n\n float dacOffsetVolts;\n float triggerHighThreshold;\n float triggerLowThreshold;\n\n // Thread-safe for single-producer, single-consumer\n friend struct TeletypeSceneIO;\n friend struct LibAVR32ModuleWidget;\n friend struct USBAJack;\n ActionQueue audioThreadActions;\n};\n\ninline float LibAVR32Module::dacToVolts(uint16_t dac)\n{\n // special case 0 so CV outs used as gates hit true zero (see issue #187)\n if (dac == 0) {\n return 0;\n }\n\n // 12 bits of information left aligned in a 16-bit word, add a small offset to get the 12-bit data closer to true\n return (10.0 * dac / (0xFFFF * 1.0)) + dacOffsetVolts;\n}\n\ninline uint16_t LibAVR32Module::voltsToAdc(float volts)\n{\n // Scale to 12-bit ADC, right-aligned in 16-bit word\n return (uint16_t)(rack::math::clamp(volts, 0.0, 10.0) * 0.1 * 0xFFF);\n}\n\n" }, { "path": "src/common/core/LibAVR32ModuleWidget.cpp", "content": "#include \"LibAVR32ModuleWidget.hpp\"\n#include \"LibAVR32Module.hpp\"\n#include \"GridConnectionMenu.hpp\"\n#include \"VirtualGridModule.hpp\"\n#include \"VirtualGridWidget.hpp\"\n#include \"SerialOscInterface.hpp\"\n#include \"Screenshot.hpp\"\n\n#include \n\nnamespace fs = ghc::filesystem;\n\nusing namespace rack;\n\n\nstruct ReloadFirmwareItem : rack::ui::MenuItem\n{\n LibAVR32Module* module;\n bool preserveVRAM;\n bool preserveNVRAM;\n\n void onAction(const rack::event::Action& e) override\n {\n if (module) {\n module->requestReloadFirmware(preserveVRAM, preserveNVRAM);\n }\n }\n};\n\nstruct SwitchFirmwareItem : rack::ui::MenuItem\n{\n LibAVR32Module* module;\n\n ui::Menu* createChildMenu() override\n {\n // duplicate filenames that may be left in res folder by prior versions\n std::vector ignoreList = {\"teletype\", \"ansible 2\", \"earthsea 2\", \"meadowphysics 2\", \"teletype 2\", \"whitewhale 2\"};\n std::vector fwNames = {};\n\n const fs::path fwPath{rack::asset::plugin(pluginInstance, \"res/firmware\")};\n for (auto const& file : fs::directory_iterator{fwPath})\n {\n auto name = file.path().stem().string();\n auto extension = file.path().extension().string();\n if (extension == module->firmware.getLibExtension() &&\n name.substr(0, module->firmwarePrefix.size()) == module->firmwarePrefix &&\n std::find(std::begin(ignoreList), std::end(ignoreList), name) == std::end(ignoreList))\n {\n fwNames.push_back(name);\n }\n }\n\n bool currentMissing = false;\n if (std::find(std::begin(fwNames), std::end(fwNames), module->firmwareName) == std::end(fwNames))\n {\n fwNames.push_back(module->firmwareName);\n currentMissing = true;\n }\n\n ui::Menu* menu = new ui::Menu;\n\n for (auto const& name : fwNames)\n {\n menu->addChild(createCheckMenuItem(\n name,\n (currentMissing && (module->firmwareName == name)) ? \"(missing)\" : \"\",\n [=]()\n { return module->firmwareName == name; },\n [=]()\n { module->requestReloadFirmware(false, false, name); }\n ));\n }\n\n return menu;\n }\n};\n\nstruct ioRateItem : rack::ui::MenuItem\n{\n int* target = nullptr;\n int defaultValue = 0;\n\n ui::Menu* createChildMenu() override\n {\n ui::Menu* menu = new ui::Menu;\n\n std::string names[] = { \"1x\", \"/2\", \"/4\", \"/8\", \"/16\" };\n std::string right[] = { \"(audio rate)\", \"\", \"\", \"\", \"(lowest CPU)\" };\n\n for (int i = 0; i < 5; i++)\n {\n int value = 1 << i;\n menu->addChild(createCheckMenuItem(\n names[i],\n (value == defaultValue) ? \"(default)\" : right[i],\n [=]()\n { return *target == value; },\n [=]()\n { *target = value; }));\n }\n\n return menu;\n }\n};\n\nstruct FirmwareSubmenuItem : MenuItem\n{\n LibAVR32Module* module;\n LibAVR32ModuleWidget* widget;\n\n Menu* createChildMenu() override\n {\n Menu* menu = new Menu;\n\n char versionbuf[512];\n module->firmware.getVersion(versionbuf);\n menu->addChild(construct(&MenuLabel::text, module->firmwareName));\n menu->addChild(construct(&MenuLabel::text, versionbuf));\n\n menu->addChild(construct(\n &MenuItem::text, \"Input rate\", &MenuItem::rightText, RIGHT_ARROW,\n &ioRateItem::defaultValue, 2, &ioRateItem::target, &module->inputRate));\n\n menu->addChild(construct(\n &MenuItem::text, \"Output rate\", &MenuItem::rightText, RIGHT_ARROW,\n &ioRateItem::defaultValue, 4, &ioRateItem::target, &module->outputRate));\n\n menu->addChild(new MenuSeparator());\n\n menu->addChild(createMenuItem(\"Save PNG screenshot\", \"\", [this]()\n { screenshotModulePNG(widget, widget->model->slug + \"-screenshot.png\"); }));\n\n menu->addChild(new MenuSeparator());\n\n menu->addChild(construct(\n &MenuItem::text, \"Switch Firmware\", &MenuItem::rightText, RIGHT_ARROW,\n &SwitchFirmwareItem::module, module));\n\n auto hotReloadItem = new ReloadFirmwareItem();\n hotReloadItem->text = \"Hot Reload\";\n hotReloadItem->module = module;\n hotReloadItem->preserveVRAM = true;\n hotReloadItem->preserveNVRAM = true;\n menu->addChild(hotReloadItem);\n\n auto reloadItem = new ReloadFirmwareItem();\n reloadItem->text = \"Reload & Restart\";\n reloadItem->module = module;\n reloadItem->preserveVRAM = false;\n reloadItem->preserveNVRAM = true;\n menu->addChild(reloadItem);\n\n auto clearItem = new ReloadFirmwareItem();\n clearItem->text = \"Clear NVRAM\";\n clearItem->module = module;\n clearItem->preserveVRAM = true;\n clearItem->preserveNVRAM = false;\n menu->addChild(clearItem);\n\n return menu;\n }\n};\n\nLibAVR32ModuleWidget::LibAVR32ModuleWidget()\n{\n}\n\nvoid LibAVR32ModuleWidget::appendContextMenu(rack::Menu* menu)\n{\n LibAVR32Module* m = dynamic_cast(module);\n assert(m);\n\n menu->addChild(new MenuSeparator());\n\n auto firmwareMenu = new FirmwareSubmenuItem();\n firmwareMenu->text = \"Firmware Tools\";\n firmwareMenu->module = m;\n firmwareMenu->widget = this;\n firmwareMenu->rightText = \"▸\";\n menu->addChild(firmwareMenu);\n\n menu->addChild(new MenuSeparator());\n appendDeviceConnectionMenu(menu, m, &m->audioThreadActions);\n}\n" }, { "path": "src/common/core/LibAVR32ModuleWidget.hpp", "content": "#include \"LibAVR32Module.hpp\"\n#include \"rack.hpp\"\n\n#pragma once\n\nextern rack::Plugin* pluginInstance;\n\nstruct LibAVR32ModuleWidget : rack::app::ModuleWidget\n{\n LibAVR32ModuleWidget();\n\n virtual void appendContextMenu(rack::ui::Menu* menu) override;\n};" }, { "path": "src/common/util/Clock12BitParam.hpp", "content": "#pragma once\n\n#include \n\ntemplate\nstruct Clock12BitParam : rack::engine::ParamQuantity\n{\n std::string divisorLabels[9] = {\n \"1/16\", \"1/8\", \"1/4\", \"1/2\", \"1\", \"2\", \"4\", \"8\", \"16\"\n };\n\n bool isDividerMode()\n {\n return\n DividerModeWhenInputPatched >= 0 &&\n module &&\n module->inputs[DividerModeWhenInputPatched].isConnected();\n }\n\n std::string getDisplayValueString() override\n {\n float v = getDisplayValue();\n if (std::isnan(v))\n return \"NaN\";\n\n uint16_t word = ((((uint16_t)(v * 1638.3) >> 4)) & 0xFFF);\n\n if (isDividerMode())\n {\n int div = rack::math::clamp((word << 2) / 455, 0, 8);\n unit = \"x\";\n return divisorLabels[div];\n }\n else\n {\n uint16_t period = 2 * (Multiplier * 12500) / (word + 25);\n unit = \"ms\";\n return rack::string::f(\"%d\", period);\n }\n }\n\n void setDisplayValueString(std::string s) override\n {\n if (isDividerMode())\n {\n // remove any whitespace\n s.erase(std::remove_if(s.begin(), s.end(), isspace), s.end());\n s = s == \"1/1\" ? \"1\" : s;\n\n for (int i = 0; i < 9; i++)\n {\n if (s == divisorLabels[i])\n {\n uint16_t word = (i * 455 + 227) << 2;\n setImmediateValue(word * (10.0 / 16383.0) + 0.0007);\n return;\n }\n }\n }\n else\n {\n ParamQuantity::setDisplayValueString(s);\n }\n }\n\n void setDisplayValue(float dv) override\n {\n uint16_t period = rack::math::clamp((int)floor(dv), 22 * Multiplier, 1000 * Multiplier);\n uint16_t word = (Multiplier * 12500 / (period / 2) - 25) << 4;\n setImmediateValue(word * (10.0 / 16383.0) + 0.0007);\n }\n};" }, { "path": "src/common/util/Screenshot.cpp", "content": "#include \"Screenshot.hpp\"\n#include \"osdialog.h\"\n#include \"stb_image_write.h\"\n\n#if SCREENSHOT_SVG\n\n#include \n#include \n#include \n\nstruct SVGcontext\n{\n svg::Document doc;\n int width;\n int height;\n};\n\nint svg__renderCreate(void* uptr, void* otherUptr)\n{\n return 1;\n}\n\nint svg__renderCreateTexture(void* uptr, int type, int w, int h, int imageFlags, const unsigned char* data)\n{\n return 1;\n}\n\nint svg__renderDeleteTexture(void* uptr, int image)\n{\n return 1;\n}\n\nint svg__renderUpdateTexture(void* uptr, int image, int x, int y, int w, int h, const unsigned char* data)\n{\n return 1;\n}\n\nint svg__renderGetTextureSize(void* uptr, int image, int* w, int* h)\n{\n return 1;\n}\n\nvoid svg__renderViewport(void* uptr, float width, float height, float devicePixelRatio)\n{\n \n}\n\nvoid svg__renderFlush(void* uptr)\n{\n\n}\n\nsvg::Point vertToPoint(SVGcontext* ctx, NVGvertex v)\n{\n return svg::Point(v.x, ctx->height - v.y);\n}\n\nvoid svg__renderFill(void* uptr, NVGpaint* paint, NVGcompositeOperationState compositeOperation, NVGscissor* scissor, float fringe, const float* bounds, const NVGpath* paths, int npaths)\n{\n SVGcontext* svgContext = reinterpret_cast(uptr);\n if (svgContext == nullptr)\n {\n return;\n }\n\n for (int i = 0; i < npaths; i++)\n {\n auto c = paint->innerColor;\n svg::Color fillColor(c.r, c.g, c.b);\n svg::Polygon svgPolygon((svg::Fill(svg::Color::White), svg::Stroke(1, svg::Color::Black)));\n\n const NVGpath* path = &paths[i];\n for (int v = 0; v < path->nstroke; v++)\n {\n svgPolygon << vertToPoint(svgContext, path->stroke[v]);\n }\n\n svgContext->doc << svgPolygon;\n }\n}\n\nvoid svg__renderStroke(void* uptr, NVGpaint* paint, NVGcompositeOperationState compositeOperation, NVGscissor* scissor, float fringe, float strokeWidth, const NVGpath* paths, int npaths)\n{\n SVGcontext* svgContext = reinterpret_cast(uptr);\n if (svgContext == nullptr)\n {\n return;\n }\n\n for (int i = 0; i < npaths; i++)\n {\n svg::Polyline svgPolyline(svg::Stroke(strokeWidth, svg::Color::Black));\n\n const NVGpath* path = &paths[i];\n for (int v = 0; v < path->nstroke; v++)\n {\n svgPolyline << vertToPoint(svgContext, path->stroke[v]);\n }\n\n svgContext->doc << svgPolyline;\n }\n}\n\nvoid svg__renderTriangles(void* uptr, NVGpaint* paint, NVGcompositeOperationState compositeOperation, NVGscissor* scissor, const NVGvertex* verts, int nverts, float fringe)\n{\n\n}\n\nvoid svg__renderDelete(void* uptr)\n{\n SVGcontext* svgContext = reinterpret_cast(uptr);\n if (svgContext == nullptr)\n {\n return;\n }\n\n svgContext->doc.save();\n\n delete svgContext;\n}\n\nstruct NVGcontext* nvgCreateSVGRenderer(std::string svgPath, int width, int height, NVGcontext* other)\n{\n struct NVGparams params;\n struct NVGcontext* ctx = NULL;\n struct SVGcontext* userData = new SVGcontext();\n\n svg::Dimensions dimensions(width, height);\n svg::Document doc(svgPath, svg::Layout(dimensions, svg::Layout::BottomLeft));\n\n svg::Polygon border(svg::Stroke(1, svg::Color::Red));\n border << svg::Point(0, 0) << svg::Point(dimensions.width, 0)\n << svg::Point(dimensions.width, dimensions.height) << svg::Point(0, dimensions.height);\n doc << border;\n //doc.save();\n\n userData->doc = doc;\n userData->width = width;\n userData->height = height;\n\n memset(¶ms, 0, sizeof(params));\n params.renderCreate = svg__renderCreate;\n params.renderCreateTexture = svg__renderCreateTexture;\n params.renderDeleteTexture = svg__renderDeleteTexture;\n params.renderUpdateTexture = svg__renderUpdateTexture;\n params.renderGetTextureSize = svg__renderGetTextureSize;\n params.renderViewport = svg__renderViewport;\n params.renderFlush = svg__renderFlush;\n params.renderFill = svg__renderFill;\n params.renderStroke = svg__renderStroke;\n params.renderTriangles = svg__renderTriangles;\n params.renderDelete = svg__renderDelete;\n params.userPtr = userData;\n params.edgeAntiAlias = 1;\n\n ctx = nvgCreateInternal(¶ms, other);\n return ctx;\n}\n\nvoid nvgDestroySVGRenderer(NVGcontext* ctx)\n{\n nvgDeleteInternal(ctx);\n}\n\nvoid screenshotModuleSVG(rack::app::ModuleWidget* moduleWidget, std::string svgPath)\n{\n auto size = moduleWidget->box.size;\n auto ctx = nvgCreateSVGRenderer(svgPath, size.x, size.y, nullptr);\n\n rack::widget::Widget::DrawArgs args;\n args.vg = ctx;\n args.fb = nullptr;\n args.clipBox = rack::math::Rect(0, 0, size.x, size.y);\n\n moduleWidget->draw(args);\n\n nvgDestroySVGRenderer(ctx);\n}\n\n#endif\n\nvoid screenshotModulePNG(rack::app::ModuleWidget* moduleWidget, std::string defaultFileName)\n{\n // adapted from rack::Window::screenshotModules()\n // https://github.com/VCVRack/Rack/blob/a811a9c78a4876824a2f721d91bdebced6a1a387/src/window/Window.cpp#L564\n\n float zoom = 2.0;\n\n auto fbw = new rack::widget::FramebufferWidget;\n fbw->oversample = 1;\n\n struct ModuleWidgetContainer : rack::widget::Widget\n {\n void draw(const DrawArgs& args) override\n {\n Widget::draw(args);\n Widget::drawLayer(args, 1);\n }\n };\n ModuleWidgetContainer* mwc = new ModuleWidgetContainer;\n fbw->addChild(mwc);\n\n rack::app::ModuleWidget* mw = moduleWidget->model->createModuleWidget(moduleWidget->module);\n mwc->box.size = mw->box.size;\n fbw->box.size = mw->box.size;\n mwc->addChild(mw);\n\n fbw->step();\n fbw->render(rack::math::Vec(zoom, zoom));\n\n char* path_result = osdialog_file(\n OSDIALOG_SAVE,\n NULL,\n defaultFileName.c_str(),\n NULL);\n\n if (!path_result)\n return;\n\n nvgluBindFramebuffer(fbw->getFramebuffer());\n int width, height;\n int depth = 4;\n\n nvgImageSize(APP->window->vg, fbw->getImageHandle(), &width, &height);\n uint8_t* pixels = new uint8_t[height * width * depth];\n glReadPixels(0, 0, width, height, GL_RGBA, GL_UNSIGNED_BYTE, pixels);\n\n for (int y = 0; y < height / 2; y++)\n {\n int flipY = height - y - 1;\n uint8_t tmp[width * depth];\n std::memcpy(tmp, &pixels[y * width * depth], width * depth);\n std::memcpy(&pixels[y * width * depth], &pixels[flipY * width * depth], width * depth);\n std::memcpy(&pixels[flipY * width * depth], tmp, width * depth);\n }\n\n stbi_write_png(path_result, width, height, depth, pixels, width * depth);\n\n delete[] pixels;\n nvgluBindFramebuffer(NULL);\n\n mw->module = nullptr;\n delete fbw;\n\n INFO(\"Screenshot saved to %s\", path_result);\n std::free(path_result);\n}" }, { "path": "src/common/util/Screenshot.hpp", "content": "#pragma once\n\n#include \n#include \"rack.hpp\"\n\n#define SCREENSHOT_SVG 0\n\n#if SCREENSHOT_SVG\nvoid screenshotModuleSVG(rack::app::ModuleWidget* moduleWidget, std::string svgPath);\n#endif\n\nvoid screenshotModulePNG(rack::app::ModuleWidget* moduleWidget, std::string pngPath);\n\n" }, { "path": "src/common/widgets/CustomMenuTemplates.hpp", "content": "#pragma once\n\n#include \"rack.hpp\"\nusing namespace rack;\n\ntemplate \nTMenuItem* createUnconsumingIndexSubmenuItem(std::string text, std::vector labels, std::function getter, std::function setter, bool disabled = false)\n{\n struct IndexItem : ui::MenuItem\n {\n std::function getter;\n std::function setter;\n size_t index;\n\n void step() override\n {\n size_t currIndex = getter();\n this->rightText = CHECKMARK(currIndex == index);\n MenuItem::step();\n }\n void onAction(const event::Action& e) override\n {\n setter(index);\n e.unconsume();\n }\n };\n\n struct Item : TMenuItem\n {\n std::function getter;\n std::function setter;\n std::vector labels;\n\n void step() override\n {\n size_t currIndex = getter();\n std::string label = (currIndex < labels.size()) ? labels[currIndex] : \"\";\n this->rightText = label + \" \" + RIGHT_ARROW;\n TMenuItem::step();\n }\n ui::Menu* createChildMenu() override\n {\n ui::Menu* menu = new ui::Menu;\n for (size_t i = 0; i < labels.size(); i++)\n {\n IndexItem* item = createMenuItem(labels[i]);\n item->getter = getter;\n item->setter = setter;\n item->index = i;\n menu->addChild(item);\n }\n return menu;\n }\n };\n\n Item* item = createMenuItem(text);\n item->getter = getter;\n item->setter = setter;\n item->labels = labels;\n item->disabled = disabled;\n return item;\n}\n\ntemplate \nTMenuItem* createUnconsumingIndexSubmenuItemWithDynamicLabels(std::string text, std::function()> getLabels, std::function getter, std::function setter, bool disabled = false)\n{\n struct IndexItem : ui::MenuItem\n {\n std::function getter;\n std::function setter;\n size_t index;\n\n void step() override\n {\n size_t currIndex = getter();\n this->rightText = CHECKMARK(currIndex == index);\n MenuItem::step();\n }\n void onAction(const event::Action& e) override\n {\n setter(index);\n e.unconsume();\n }\n };\n\n struct Item : TMenuItem\n {\n std::function()> getLabels;\n std::function getter;\n std::function setter;\n\n void step() override\n {\n size_t currIndex = getter();\n auto labels = getLabels();\n std::string label = (currIndex < labels.size()) ? labels[currIndex] : \"\";\n this->rightText = label + \" \" + RIGHT_ARROW;\n TMenuItem::step();\n }\n ui::Menu* createChildMenu() override\n {\n ui::Menu* menu = new ui::Menu;\n auto labels = getLabels();\n for (size_t i = 0; i < labels.size(); i++)\n {\n IndexItem* item = createMenuItem(labels[i]);\n item->getter = getter;\n item->setter = setter;\n item->index = i;\n menu->addChild(item);\n }\n return menu;\n }\n };\n\n Item* item = createMenuItem(text);\n item->getter = getter;\n item->setter = setter;\n item->getLabels = getLabels;\n item->disabled = disabled;\n return item;\n}\n\ntemplate \nTMenuItem* createSubmenuItemWithDynamicRightText(std::string text, std::function getRightText, std::function createMenu, bool disabled = false)\n{\n struct Item : TMenuItem\n {\n std::function getRightText;\n std::function createMenu;\n\n void step() override\n {\n this->rightText = getRightText() + \" \" + RIGHT_ARROW;\n TMenuItem::step();\n }\n\n ui::Menu* createChildMenu() override\n {\n ui::Menu* menu = new ui::Menu;\n createMenu(menu);\n return menu;\n }\n };\n\n Item* item = createMenuItem(text, getRightText() + \" \" + RIGHT_ARROW);\n item->getRightText = getRightText;\n item->createMenu = createMenu;\n item->disabled = disabled;\n return item;\n}" }, { "path": "src/common/widgets/HoldableButton.hpp", "content": "#include \"rack.hpp\"\n\nstruct HoldableButton : rack::TL1105\n{\n bool heldThisGesture;\n\n HoldableButton() : rack::TL1105()\n {\n heldThisGesture = false;\n }\n\n void onButton(const rack::widget::Widget::ButtonEvent& e) override\n {\n // Shift from momentary to toggle if we're control-clicked, to enable a \"hold\" state\n if (momentary &&\n e.action == GLFW_PRESS && e.button == GLFW_MOUSE_BUTTON_LEFT &&\n (e.mods & RACK_MOD_CTRL) == RACK_MOD_CTRL)\n {\n momentary = false;\n heldThisGesture = true;\n }\n // don't cancel the hold on the very first release event\n else if (e.action == GLFW_RELEASE && heldThisGesture)\n {\n heldThisGesture = false;\n }\n else\n {\n momentary = true;\n heldThisGesture = false;\n }\n TL1105::onButton(e);\n }\n\n void draw(const DrawArgs& args) override\n {\n if (!momentary) {\n nvgBeginPath(args.vg);\n nvgCircle(args.vg, box.size.x / 2, box.size.y / 2, box.size.x / 2 + 2);\n nvgStrokeColor(args.vg, nvgRGB(190, 180, 0));\n nvgStrokeWidth(args.vg, 4);\n nvgStroke(args.vg);\n }\n TL1105::draw(args);\n }\n};" }, { "path": "src/common/widgets/SifamTPM.hpp", "content": "#pragma once\n\n#include \n\nstruct Sifam : rack::app::SvgKnob\n{\n rack::widget::SvgWidget* bg;\n rack::widget::SvgWidget* fg;\n rack::widget::SvgWidget* indicator;\n rack::widget::TransformWidget* indicatorTransform;\n\n Sifam()\n {\n minAngle = -0.83 * M_PI;\n maxAngle = 0.83 * M_PI;\n\n bg = new rack::widget::SvgWidget;\n fb->addChildBelow(bg, tw);\n\n fg = new rack::widget::SvgWidget;\n fb->addChildAbove(fg, tw);\n\n indicatorTransform = new rack::widget::TransformWidget;\n indicator = new rack::widget::SvgWidget;\n indicatorTransform->addChild(indicator);\n fb->addChildAbove(indicatorTransform, fg);\n }\n\n void onChange(const ChangeEvent& e) override\n {\n SvgKnob::onChange(e);\n for (int i = 0; i < 6; i++) \n {\n indicatorTransform->transform[i] = tw->transform[i];\n }\n }\n};\n\nstruct SifamTPN111GrayBlackStripe : Sifam\n{\n SifamTPN111GrayBlackStripe()\n {\n setSvg(rack::window::Svg::load(rack::asset::plugin(pluginInstance, \"res/SifamTPN111.svg\")));\n bg->setSvg(rack::window::Svg::load(rack::asset::plugin(pluginInstance, \"res/SifamTPN111-bg.svg\")));\n fg->setSvg(rack::window::Svg::load(rack::asset::plugin(pluginInstance, \"res/SifamTPN111-gray-fg.svg\")));\n indicator->setSvg(rack::window::Svg::load(rack::asset::plugin(pluginInstance, \"res/SifamTPN111-blackstripe.svg\")));\n indicatorTransform->box.size = indicator->box.size;\n }\n};" }, { "path": "src/common/widgets/USBAJack.hpp", "content": "#pragma once\n\n#include \"rack.hpp\"\n#include \"LibAVR32Module.hpp\"\n#include \"GridConnectionMenu.hpp\"\n\n\nstruct USBAJack : rack::Switch\n{\n USBAJack()\n {\n box.size = rack::Vec(44, 23.75);\n }\n\n void draw(const DrawArgs& args) override\n {\n auto vg = args.vg;\n auto m = dynamic_cast(module);\n\n float w = box.size.x;\n float h = box.size.y;\n float z = 4.75;\n\n rack::engine::ParamQuantity* pq = getParamQuantity();\n if (pq && pq->getValue() >= 1.0)\n {\n // draw shadow\n nvgBeginPath(vg);\n nvgRoundedRect(vg, 0, z - 1, w, h - z + 1, 4.5);\n nvgFillColor(vg, nvgRGB(165, 165, 165));\n nvgFill(vg);\n\n // draw face\n nvgBeginPath(vg);\n nvgRoundedRect(vg, 0, 0, w, h - z + 1, 3.5);\n nvgFillColor(vg, nvgRGB(200, 200, 200));\n nvgFill(vg);\n\n // draw 3D highlight\n nvgBeginPath(vg);\n nvgRoundedRect(vg, 2, 1, w - 4, h - z - 1, 3);\n nvgFillPaint(vg, nvgBoxGradient(vg, 2, 1, w - 4, 18, 2, 5, nvgRGB(225, 225, 225), nvgRGB(190, 190, 190)));\n nvgFill(vg);\n\n // draw embossed text label\n std::string label = m->currentConnectedDeviceId.substr(0, 11);\n nvgFontSize(vg, 6.0);\n nvgTextAlign(vg, NVG_ALIGN_RIGHT | NVG_ALIGN_BOTTOM);\n nvgFillColor(vg, nvgRGB(250, 250, 250));\n nvgText(vg, w - 4.1, z + 12.4, label.c_str(), 0);\n nvgFillColor(vg, nvgRGB(150, 150, 150));\n nvgText(vg, w - 4.5, z + 12, label.c_str(), 0);\n }\n else\n {\n // draw port background\n nvgBeginPath(vg);\n nvgRoundedRect(vg, 3, z, w - 6, h - z - 5, 1.5);\n nvgFillColor(vg, nvgRGB(0, 0, 0));\n nvgFill(vg);\n\n // draw connector base\n nvgBeginPath(vg);\n nvgRect(vg, 7, 4 + z, w - 14, 6);\n nvgFillColor(vg, nvgRGB(50, 50, 50));\n nvgFill(vg);\n\n // draw contacts\n float p = (w - 14) / 8.5;\n nvgBeginPath(vg);\n nvgRoundedRect(vg, 7 + 1 * p, z + 5, p, 4, 1.5);\n nvgRoundedRect(vg, 7 + 2.9 * p, z + 5, p, 3.5, 1.5);\n nvgRoundedRect(vg, 7 + 4.6 * p, z + 5, p, 3.5, 1.5);\n nvgRoundedRect(vg, 7 + 6.5 * p, z + 5, p, 4, 1.5);\n nvgFillColor(vg, nvgRGB(77, 75, 0));\n nvgFill(vg);\n\n // draw connector prong\n nvgBeginPath(vg);\n nvgRect(vg, 7, 4 + z, 30, 3);\n nvgFillColor(vg, nvgRGB(120, 120, 120));\n nvgFill(vg);\n }\n }\n\n void appendContextMenu(rack::ui::Menu* menu) override\n {\n auto mw = dynamic_cast(parent);\n if (mw)\n {\n auto m = dynamic_cast(mw->module);\n if (mw)\n {\n menu->addChild(new rack::MenuSeparator());\n appendDeviceConnectionMenu(menu, m, &m->audioThreadActions);\n }\n }\n }\n};\n" }, { "path": "src/common/widgets/YellowWhiteLight.hpp", "content": "#pragma once\n\n#include \"rack.hpp\"\n\nstruct YellowWhiteLight : rack::componentlibrary::GrayModuleLightWidget\n{\n YellowWhiteLight() {\n this->addBaseColor(rack::SCHEME_YELLOW);\n this->addBaseColor(rack::SCHEME_WHITE);\n }\n};" }, { "path": "src/earthsea/EarthseaModule.hpp", "content": "#include \"LibAVR32Module.hpp\"\n\n#pragma once\n\nstruct EarthseaModule : LibAVR32Module\n{\n enum ParamIds\n {\n CV1_PARAM,\n CV2_PARAM,\n CV3_PARAM,\n BUTTON_PARAM,\n USB_PARAM,\n NUM_PARAMS\n };\n\n enum InputIds\n {\n NUM_INPUTS\n };\n\n enum OutputIds\n {\n CV1_OUTPUT,\n CV2_OUTPUT,\n CV3_OUTPUT,\n POS_OUTPUT,\n EDGE_OUTPUT,\n NUM_OUTPUTS\n };\n\n enum LightIds\n {\n CV1_LIGHT,\n CV2_LIGHT,\n CV3_LIGHT,\n POS_LIGHT,\n EDGE_LIGHT,\n NUM_LIGHTS\n };\n\n EarthseaModule()\n : LibAVR32Module(\"earthsea\", \"earthsea\")\n {\n config(NUM_PARAMS, NUM_INPUTS, NUM_OUTPUTS, NUM_LIGHTS);\n\n configButton(BUTTON_PARAM, \"PRESET\");\n configParam(CV1_PARAM, 0, 10.0, 0.0, \"SHAPE 1\", \"V\");\n configParam(CV2_PARAM, 0, 10.0, 0.0, \"SHAPE 2\", \"V\");\n configParam(CV3_PARAM, 0, 10.0, 0.0, \"SHAPE 3\", \"V\");\n configOutput(CV1_OUTPUT, \"SHAPE 1\");\n configOutput(CV2_OUTPUT, \"SHAPE 2\");\n configOutput(CV3_OUTPUT, \"SHAPE 3\");\n configOutput(EDGE_OUTPUT, \"EDGE\");\n configOutput(POS_OUTPUT, \"POS\");\n configButton(USB_PARAM, \"USB Device Port\");\n\n setDeviceConnectionParam(USB_PARAM);\n }\n\n void processInputs(const ProcessArgs& args) override\n {\n bool frontButton = params[BUTTON_PARAM].getValue() == 0;\n if (frontButton != firmware.getGPIO(NMI))\n {\n firmware.setGPIO(NMI, frontButton);\n firmware.triggerInterrupt(3);\n }\n\n // Convert knob float parameters to 12-bit ADC values\n firmware.setADC(0, voltsToAdc(params[CV1_PARAM].getValue()));\n firmware.setADC(1, voltsToAdc(params[CV2_PARAM].getValue()));\n firmware.setADC(2, voltsToAdc(params[CV3_PARAM].getValue()));\n }\n\n void processOutputs(const ProcessArgs& args) override\n {\n float cv1 = dacToVolts(firmware.getDAC(2));\n float cv2 = dacToVolts(firmware.getDAC(3));\n float cv3 = dacToVolts(firmware.getDAC(0));\n float pos = dacToVolts(firmware.getDAC(1));\n bool edge = firmware.getGPIO(B00);\n\n // Update lights from DAC and GPIO\n lights[CV1_LIGHT].setSmoothBrightness(cv1 / 10.0, args.sampleTime);\n lights[CV2_LIGHT].setSmoothBrightness(cv2 / 10.0, args.sampleTime);\n lights[CV3_LIGHT].setSmoothBrightness(cv3 / 10.0, args.sampleTime);\n lights[POS_LIGHT].setSmoothBrightness(pos / 10.0, args.sampleTime);\n lights[EDGE_LIGHT].setSmoothBrightness(edge, args.sampleTime);\n\n // Update output jacks from GPIO & DAC\n outputs[CV1_OUTPUT].setVoltage(cv1);\n outputs[CV2_OUTPUT].setVoltage(cv2);\n outputs[CV3_OUTPUT].setVoltage(cv3);\n outputs[POS_OUTPUT].setVoltage(pos);\n outputs[EDGE_OUTPUT].setVoltage(edge * 8.0);\n }\n};" }, { "path": "src/earthsea/EarthseaWidget.hpp", "content": "#pragma once\n\n#include \"EarthseaModule.hpp\"\n#include \"LibAVR32ModuleWidget.hpp\"\n#include \"SifamTPM.hpp\"\n#include \"USBAJack.hpp\"\n\nusing namespace rack;\n\nstruct EarthseaWidget : LibAVR32ModuleWidget\n{\n EarthseaWidget(EarthseaModule* module)\n {\n setModule(module);\n\n box.size = Vec(15 * 6, 380);\n\n {\n auto panel = new ThemedSvgPanel();\n panel->setBackground(\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/earthsea.svg\")),\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/earthsea-dark.svg\")));\n panel->box.size = box.size;\n addChild(panel);\n }\n\n // Screws positioned for sliding nuts :)\n addChild(createWidget(Vec(RACK_GRID_WIDTH / 2, 0)));\n addChild(createWidget(Vec(RACK_GRID_WIDTH / 2, RACK_GRID_HEIGHT - RACK_GRID_WIDTH)));\n\n addParam(createParam(Vec(7, 333), module, EarthseaModule::USB_PARAM));\n addParam(createParam(Vec(62, 336), module, EarthseaModule::BUTTON_PARAM));\n addParam(createParam(Vec(12.5, 30), module, EarthseaModule::CV1_PARAM));\n addParam(createParam(Vec(12.5, 116), module, EarthseaModule::CV2_PARAM));\n addParam(createParam(Vec(12.5, 202), module, EarthseaModule::CV3_PARAM));\n\n addOutput(createOutput(Vec(50, 82), module, EarthseaModule::CV1_OUTPUT));\n addOutput(createOutput(Vec(50, 166), module, EarthseaModule::CV2_OUTPUT));\n addOutput(createOutput(Vec(50, 248), module, EarthseaModule::CV3_OUTPUT));\n addOutput(createOutput(Vec(50, 286), module, EarthseaModule::POS_OUTPUT));\n addOutput(createOutput(Vec(15, 265), module, EarthseaModule::EDGE_OUTPUT));\n\n addChild(createLight>(Vec(77, 78), module, EarthseaModule::CV1_LIGHT));\n addChild(createLight>(Vec(77, 162), module, EarthseaModule::CV2_LIGHT));\n addChild(createLight>(Vec(77, 244), module, EarthseaModule::CV3_LIGHT));\n addChild(createLight>(Vec(77, 282), module, EarthseaModule::POS_LIGHT));\n addChild(createLight>(Vec(2, 282), module, EarthseaModule::EDGE_LIGHT));\n }\n};\n" }, { "path": "src/faderbank/FaderbankModule.cpp", "content": "#include \"FaderbankModule.hpp\"\n\n\nFaderbankModule::FaderbankModule()\n{\n config(NUM_FADERS, 0, NUM_FADERS, 0);\n\n for (unsigned i = 0; i < NUM_FADERS; i++)\n {\n configParam(i, 0.0, 10.0, 0.0, rack::string::f(\"Fader %d\", i + 1), \" V\");\n }\n\n resetConfig();\n}\n\nFaderbankModule::~FaderbankModule()\n{\n}\n\nvoid FaderbankModule::process(const ProcessArgs& args)\n{\n processMIDIMessages(args);\n\n for (unsigned i = 0; i < NUM_FADERS; i++)\n {\n outputs[i].setVoltage(params[i].getValue());\n }\n\n if (polyphonicMode)\n {\n outputs[NUM_FADERS - 1].setChannels(16);\n for (unsigned i = 0; i < NUM_FADERS; i++)\n {\n outputs[NUM_FADERS - 1].setVoltage(params[i].getValue(), i);\n }\n }\n else\n {\n outputs[NUM_FADERS - 1].setChannels(1);\n }\n}\n\nvoid FaderbankModule::processMIDIMessages(const ProcessArgs& args)\n{\n int min14bitInterval = floor(args.sampleRate * 0.004);\n\n rack::midi::Message msg;\n while (midiInput.tryPop(&msg, args.frame))\n {\n DEBUG(\"MIDI: %lld %s\", msg.getFrame(), msg.toString().c_str());\n\n switch (msg.getStatus())\n {\n case 0xb: // Continuous Controller\n {\n // Combine channel and CC number into a lookup key\n uint8_t ccNum = msg.getNote();\n uint16_t key = (msg.getChannel() << 8) | ccNum;\n\n auto iter = inputMap.find(key);\n if (iter != inputMap.end())\n {\n auto faderDestinations = iter->second;\n for (auto index : faderDestinations) {\n if (index < NUM_FADERS)\n {\n records[index].highValue = msg.getValue();\n records[index].lastHighValue = msg.getValue();\n records[index].lastHighValueFrame = args.frame;\n }\n }\n }\n\n if (ccNum >= 32)\n {\n // look for potential LSB CC of 14-bit CC\n key = (msg.getChannel() << 8) | (ccNum - 32);\n iter = inputMap.find(key);\n if (iter != inputMap.end())\n {\n auto faderDestinations = iter->second;\n for (auto index : faderDestinations)\n {\n if (index < NUM_FADERS && records[index].faderMode == FaderMode14bitCC)\n {\n records[index].lowValue = msg.getValue();\n records[index].lastLowValueFrame = args.frame;\n }\n }\n }\n }\n }\n break;\n case 0xF: // System Exclusive\n {\n if (msg.bytes[1] == 0x7d && // 16n manufacturer ID\n msg.bytes[2] == 0x00 &&\n msg.bytes[3] == 0x00 &&\n msg.bytes[4] == 0x0F && // sysex config response ID\n msg.bytes.size() >= (9 + 80))\n {\n for (int i = 0; i < NUM_FADERS; i++)\n {\n uint8_t channel = ((msg.bytes[9 + 16 + i]) & 0xF) - 1;\n uint8_t ccNum = msg.bytes[9 + 48 + i] & 0x7F;\n records[i].ccNum = ccNum;\n records[i].channel = channel;\n if (msg.bytes.size() >= 9 + 83)\n {\n uint16_t ccMode = (msg.bytes[9 + 80] & 0x7F) | ((msg.bytes[9 + 81] & 0x7F) << 7) | ((msg.bytes[9 + 82] & 0x03) << 14);\n records[i].faderMode = (ccMode & (1 << i)) == 0 ? FaderModeCC : FaderMode14bitCC;\n }\n }\n updateInputMap();\n }\n }\n break;\n default:\n break;\n }\n }\n\n for (int i = 0; i < NUM_FADERS; i++)\n {\n uint16_t value;\n bool updateable = false;\n bool expect14bit = records[i].faderMode == FaderMode14bitCC && records[i].ccNum < 96;\n\n if (records[i].highValue != 0xFF)\n {\n if (expect14bit)\n {\n if (records[i].lowValue != 0xFF)\n {\n value = ((records[i].highValue & 0x7F) << 7) + (records[i].lowValue & 0x7F);\n updateable = true;\n }\n else if ((args.frame - records[i].lastHighValueFrame) > min14bitInterval)\n {\n // give up waiting for a low value\n value = (records[i].highValue & 0x7F) << 7;\n updateable = true;\n }\n }\n else\n {\n value = records[i].highValue & 0x7F;\n updateable = true;\n }\n }\n else if (expect14bit && records[i].lowValue != 0xFF && (args.frame - records[i].lastLowValueFrame) > min14bitInterval)\n {\n // give up waiting for a high value\n value = ((records[i].lastHighValue & 0x7F) << 7) + (records[i].lowValue & 0x7F);\n updateable = true;\n }\n\n if (updateable)\n {\n auto param = getParamQuantity(i);\n if (param)\n {\n param->setScaledValue((value * 1.0f) / ((expect14bit ? 0x3FFF : 0x7F) * 1.0f));\n }\n\n records[i].highValue = 0xFF;\n records[i].lowValue = 0xFF;\n }\n }\n}\n\nvoid FaderbankModule::resetConfig()\n{\n for (int i = 0; i < NUM_FADERS; i++)\n {\n // by default, assign CC faders starting with 32, all on channel 1\n records[i].ccNum = 32 + i;\n records[i].channel = 0;\n records[i].faderMode = FaderModeCC;\n }\n\n updateInputMap();\n}\n\nvoid FaderbankModule::updateInputMap()\n{\n inputMap.clear();\n\n for (int i = 0; i < NUM_FADERS; i++)\n {\n uint16_t key = (records[i].channel << 8) | records[i].ccNum;\n if (inputMap.find(key) == inputMap.end())\n {\n inputMap.insert(make_pair(key, std::vector()));\n }\n\n inputMap[key].push_back(i);\n }\n}\n\nvoid FaderbankModule::updateFaderRanges()\n{\n for (int i = 0; i < NUM_FADERS; i++)\n {\n auto param = getParamQuantity(i);\n if (param != nullptr)\n {\n float orig = param->getValue();\n switch (faderRange)\n {\n case FaderRange10V:\n {\n param->minValue = 0.0;\n param->maxValue = 10.0;\n }\n break;\n case FaderRange5V:\n {\n param->minValue = 0.0;\n param->maxValue = 5.0;\n }\n break;\n case FaderRangeBipolar:\n {\n param->minValue = -5.0;\n param->maxValue = 5.0;\n }\n break;\n default:\n break;\n }\n param->setValue(orig);\n }\n }\n}\n\nvoid FaderbankModule::autodetectConfig()\n{\n resetConfig();\n\n midiInput.setDriverId(rack::midi::getDriverIds()[0]);\n if (midiInput.deviceId == -1)\n {\n for (int deviceId : midiInput.getDeviceIds())\n {\n if (midiInput.getDeviceName(deviceId).substr(0, 3).find(\"16n\") != std::string::npos)\n {\n midiInput.setDeviceId(deviceId);\n break;\n }\n }\n }\n\n midiOutput.setDriverId(rack::midi::getDriverIds()[0]);\n if (midiOutput.deviceId == -1)\n {\n for (int deviceId : midiOutput.getDeviceIds())\n {\n if (midiOutput.getDeviceName(deviceId).find(\"16n\") != std::string::npos)\n {\n midiOutput.setDeviceId(deviceId);\n break;\n }\n }\n }\n\n // Send a sysex message to request device channel/CC config.\n if (midiOutput.deviceId != -1)\n {\n rack::midi::Message msg;\n msg.setSize(6);\n msg.bytes = { 0xF0, 0x7d, 0x00, 0x00, 0x1F, 0xF7 };\n\n midiOutput.sendMessage(msg);\n }\n}\n\nvoid FaderbankModule::writeConfigSysex()\n{\n if (midiOutput.deviceId != -1)\n {\n rack::midi::Message msg;\n msg.setSize(41);\n\n uint8_t header[] = { 0xF0, 0x7d, 0x00, 0x00, 0x0C };\n for (int i = 0; i < 5; i++)\n {\n msg.bytes[i] = header[i];\n }\n\n uint16_t modeBits = 0x0000;\n for (int i = 0; i < NUM_FADERS; i++)\n {\n msg.bytes[5 + i] = (records[i].channel + 1) & 0x1F;\n msg.bytes[21 + i] = records[i].ccNum & 0x7F;\n if (records[i].faderMode == FaderMode14bitCC)\n {\n modeBits |= (1 << i);\n }\n }\n msg.bytes[37] = modeBits & 0x7F;\n msg.bytes[38] = (modeBits >> 7) & 0x7F;\n msg.bytes[39] = (modeBits >> 14) & 0x03;\n msg.bytes[40] = 0xF7;\n\n midiOutput.sendMessage(msg);\n }\n}\n\njson_t* FaderbankModule::dataToJson()\n{\n json_t* rootJ = json_object();\n\n json_object_set_new(rootJ, \"faderRange\", json_integer(faderRange));\n json_object_set_new(rootJ, \"faderSize\", json_integer(faderSize));\n json_object_set_new(rootJ, \"polyphonicMode\", json_boolean(polyphonicMode));\n\n json_object_set_new(rootJ, \"midi\", midiInput.toJson());\n json_object_set_new(rootJ, \"midiOutput\", midiOutput.toJson());\n\n json_t* configJ = json_array();\n for (auto& entry : records)\n {\n json_t* faderRecord = json_object();\n json_object_set_new(faderRecord, \"channel\", json_integer(entry.channel));\n json_object_set_new(faderRecord, \"faderMode\", json_integer(entry.faderMode));\n json_object_set_new(faderRecord, \"ccNum\", json_integer(entry.ccNum));\n\n json_array_append(configJ, faderRecord);\n }\n json_object_set_new(rootJ, \"fader_config\", configJ);\n\n return rootJ;\n}\n\nvoid FaderbankModule::dataFromJson(json_t* rootJ)\n{\n json_t* faderRangeJ = json_object_get(rootJ, \"faderRange\");\n if (faderRangeJ)\n faderRange = static_cast(json_integer_value(faderRangeJ));\n\n updateFaderRanges();\n\n json_t* faderSizeJ = json_object_get(rootJ, \"faderSize\");\n if (faderSizeJ)\n faderSize = static_cast(json_integer_value(faderSizeJ));\n\n json_t* polyphonicModeJ = json_object_get(rootJ, \"polyphonicMode\");\n if (polyphonicModeJ)\n polyphonicMode = json_boolean_value(polyphonicModeJ);\n\n json_t* midiJ = json_object_get(rootJ, \"midi\");\n if (midiJ)\n midiInput.fromJson(midiJ);\n\n json_t* midiOutputJ = json_object_get(rootJ, \"midiOutput\");\n if (midiOutputJ)\n midiOutput.fromJson(midiOutputJ);\n\n // backwards compatibility for patches with older config structure\n json_t* oldConfigJ = json_object_get(rootJ, \"16n_config\");\n if (oldConfigJ)\n {\n json_t* dataJ;\n const char* key;\n json_object_foreach(oldConfigJ, key, dataJ)\n {\n int16_t val = std::stoi(key);\n int8_t fader = json_integer_value(dataJ);\n records[fader].ccNum = val & 0x7F;\n records[fader].channel = val >> 8;\n }\n }\n\n // current format for config\n json_t* configJ = json_object_get(rootJ, \"fader_config\");\n if (configJ)\n {\n json_t* dataJ;\n size_t key;\n json_array_foreach(configJ, key, dataJ)\n {\n if (key < NUM_FADERS)\n {\n json_t* channelJ = json_object_get(dataJ, \"channel\");\n if (channelJ)\n {\n records[key].channel = json_integer_value(channelJ) & 0xF;\n }\n json_t* modeJ = json_object_get(dataJ, \"faderMode\");\n if (modeJ)\n {\n records[key].faderMode = static_cast(json_integer_value(modeJ));\n }\n json_t* ccJ = json_object_get(dataJ, \"ccNum\");\n if (ccJ)\n {\n records[key].ccNum = json_integer_value(ccJ) & 0x7F;\n }\n }\n }\n }\n\n updateInputMap();\n}\n\nvoid FaderbankModule::fromJson(json_t* rootJ)\n{\n // deserialize data before params, so voltage range option is set correctly\n json_t* dataJ = json_object_get(rootJ, \"data\");\n if (dataJ)\n dataFromJson(dataJ);\n\n Module::fromJson(rootJ);\n}\n\nFaderbankModule::ControllerRecord::ControllerRecord()\n{\n highValue = 0xFF;\n lowValue = 0xFF;\n lastHighValue = 0;\n channel = 0;\n ccNum = 0;\n faderMode = FaderModeCC;\n}" }, { "path": "src/faderbank/FaderbankModule.hpp", "content": "#pragma once\n#include \"rack.hpp\"\n\n#include \n\n#define NUM_FADERS 16\n\n\nstruct FaderbankModule : rack::Module\n{\n FaderbankModule();\n ~FaderbankModule();\n\n void process(const ProcessArgs& args) override;\n\n void processMIDIMessages(const ProcessArgs& args);\n void resetConfig();\n void updateInputMap();\n void updateFaderRanges();\n void autodetectConfig();\n void writeConfigSysex();\n\n json_t* dataToJson() override;\n void dataFromJson(json_t* rootJ) override;\n // override fromJson to deserialize data before params\n void fromJson(json_t* rootJ) override;\n\n std::map > inputMap;\n\n rack::midi::InputQueue midiInput;\n rack::midi::Output midiOutput;\n\n typedef enum\n {\n FaderSize90mm,\n FaderSize60mm\n } FaderSize;\n\n typedef enum\n {\n FaderRange10V,\n FaderRange5V,\n FaderRangeBipolar\n } FaderRange;\n\n typedef enum\n {\n FaderModeCC,\n FaderMode14bitCC\n } FaderMode;\n\n struct ControllerRecord\n {\n uint8_t highValue;\n uint8_t lowValue;\n uint8_t lastHighValue;\n int64_t lastHighValueFrame;\n int64_t lastLowValueFrame;\n uint8_t ccNum;\n uint8_t channel;\n FaderMode faderMode;\n\n ControllerRecord();\n };\n\n FaderSize faderSize = FaderSize90mm;\n FaderRange faderRange = FaderRange10V;\n bool polyphonicMode = false;\n\n ControllerRecord records[NUM_FADERS];\n};\n" }, { "path": "src/faderbank/FaderbankWidget.cpp", "content": "#include \"FaderbankWidget.hpp\"\n#include \"FaderbankModule.hpp\"\n#include \"CustomMenuTemplates.hpp\"\n\nextern rack::Plugin* pluginInstance;\n\nusing namespace rack;\n\nstruct ThemedSvgSlider : app::SvgSlider\n{\n std::vector> lightThemedBackgrounds;\n std::vector> darkThemedBackgrounds;\n\n unsigned int *theme = 0;\n\n void updateGraphics()\n {\n int t = theme == nullptr ? 0 : *theme;\n SvgSlider::setBackgroundSvg(\n settings::preferDarkPanels ?\n darkThemedBackgrounds[t % darkThemedBackgrounds.size()] :\n lightThemedBackgrounds[t % lightThemedBackgrounds.size()]\n );\n }\n\n void step() override\n {\n updateGraphics();\n SvgSlider::step();\n }\n};\n\nstruct FaderbankSlider : ThemedSvgSlider\n{\n FaderbankSlider()\n {\n lightThemedBackgrounds.push_back(Svg::load(asset::plugin(pluginInstance, \"res/FaderBackground90mm.svg\")));\n lightThemedBackgrounds.push_back(Svg::load(asset::plugin(pluginInstance, \"res/FaderBackground60mm.svg\")));\n darkThemedBackgrounds.push_back(Svg::load(asset::plugin(pluginInstance, \"res/FaderBackground90mm-dark.svg\")));\n darkThemedBackgrounds.push_back(Svg::load(asset::plugin(pluginInstance, \"res/FaderBackground60mm-dark.svg\")));\n\n setHandleSvg(Svg::load(asset::plugin(pluginInstance, \"res/FaderHandle.svg\")));\n updateGraphics();\n\n maxHandlePos = rack::window::mm2px(math::Vec(0.738, 1.8));\n minHandlePos = rack::window::mm2px(math::Vec(0.738, 87.3));\n\n box.grow(math::Vec(3, 1));\n }\n\n void step() override\n {\n minHandlePos = rack::window::mm2px(math::Vec(0.738, (theme == nullptr || *theme == 0) ? 87.3 : 59.8));\n ThemedSvgSlider::step();\n }\n};\n\nstruct WideYellowLight : YellowLight\n{\n // custom draw function to make glow look better on a\n // rectangular light that is much wider than it is tall\n void drawHalo(const DrawArgs& args) override\n {\n if (args.fb)\n return;\n\n const float halo = settings::haloBrightness;\n if (halo == 0.f)\n return;\n\n if (color.r == 0.f && color.g == 0.f && color.b == 0.f)\n return;\n\n math::Vec c = box.size.div(2);\n\n float xoradius = c.x + std::min(c.x * 1.55f, 15.f);\n float yoradius = c.y + std::min(c.y * 1.85f, 15.f);\n\n nvgBeginPath(args.vg);\n nvgRect(args.vg, c.x - xoradius, c.y - yoradius, 2 * xoradius, 3 * yoradius);\n\n NVGcolor icol = color::mult(color, halo);\n NVGcolor ocol = nvgRGBA(0, 0, 0, 0);\n nvgSave(args.vg);\n nvgScale(args.vg, 1.0f, 1.85f * c.y / c.x);\n NVGpaint paint = nvgRadialGradient(args.vg, c.x, c.y, c.x * 0.46, xoradius * 0.8, icol, ocol);\n nvgFillPaint(args.vg, paint);\n nvgFill(args.vg);\n nvgRestore(args.vg);\n }\n};\n\ntemplate \nstruct FaderbankSliderLight : RectangleLight>\n{\n FaderbankSliderLight()\n {\n this->setSvg(Svg::load(asset::plugin(pluginInstance, \"res/FaderSliderLight.svg\")));\n }\n};\n\nstruct FaderbankSliderYellow : LightSlider>\n{\n FaderbankSliderYellow()\n {\n getLight()->box.size.x = getLight()->box.size.x * 6;\n getLight()->box.size.y = getLight()->box.size.y * 0.4;\n }\n};\n\nFaderbankWidget::FaderbankWidget(FaderbankModule* module)\n{\n setModule(module);\n\n box.size = Vec(735, 380);\n\n {\n auto panel = new ThemedSvgPanel();\n panel->setBackground(\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/grid.svg\")),\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/grid-dark.svg\")));\n panel->box.size = box.size;\n addChild(panel);\n }\n\n // dummy opaque widget to prevent accidentally dragging the module when clicking between faders\n // TODO: increase hitboxes of faders instead\n auto dummy = new OpaqueWidget();\n dummy->box.size = Vec(735 - 29, 300);\n dummy->setPosition(Vec(14.5, 60));\n addChild(dummy);\n\n for (int i = 0; i < NUM_FADERS; i++)\n {\n addOutput(createOutput(Vec(17 + 45 * i, 20), module, i));\n auto slider = createParam(Vec(14.5 + 45 * i, 60), module, i);\n if (module != nullptr)\n {\n slider->theme = (unsigned int*)&module->faderSize;\n }\n else\n {\n // set the handles on a diagonal in the library\n slider->handle->box.pos = slider->minHandlePos.crossfade(slider->maxHandlePos, i/(NUM_FADERS * 1.0));\n }\n addParam(slider);\n }\n}\n\nvoid appendFaderConfigMenu(FaderbankModule* fb, ::Menu* menu, int faderIndex)\n{\n if (fb == nullptr || menu == nullptr || faderIndex < 0 || faderIndex > NUM_FADERS)\n {\n return;\n }\n\n std::vector modeNames { \"CC\", \"CC (14-bit)\" };\n\n std::vector channelNames;\n for (auto i = 0; i < 16; i++)\n {\n std::ostringstream ss;\n ss << (i + 1);\n channelNames.push_back(ss.str());\n }\n\n std::ostringstream faderName;\n faderName << faderIndex + 1;\n\n menu->addChild(createSubmenuItemWithDynamicRightText(faderName.str(),\n [=]()\n {\n FaderbankModule::ControllerRecord record = fb->records[faderIndex];\n std::ostringstream faderDesc;\n faderDesc << \"Ch \" << (int)(record.channel + 1) << \" \" << modeNames[record.faderMode] << \" \";\n if (record.faderMode == FaderbankModule::FaderModeCC)\n {\n faderDesc << (int)record.ccNum;\n }\n else if (record.faderMode == FaderbankModule::FaderMode14bitCC)\n {\n faderDesc << (int)record.ccNum << \"/\" << (int)(record.ccNum + 32);\n }\n return faderDesc.str();\n },\n [=](Menu* childMenu)\n {\n childMenu->addChild(createUnconsumingIndexSubmenuItem(\"Channel\", channelNames,\n [=]()\n {\n return fb->records[faderIndex].channel;\n },\n [=](int index)\n {\n fb->records[faderIndex].channel = index & 0xF;\n fb->updateInputMap();\n }\n ));\n\n childMenu->addChild(createUnconsumingIndexSubmenuItem(\"Mode\", modeNames,\n [=]()\n {\n return fb->records[faderIndex].faderMode;\n },\n [=](int index)\n {\n fb->records[faderIndex].faderMode = static_cast(index);\n fb->updateInputMap();\n }\n ));\n\n childMenu->addChild(createUnconsumingIndexSubmenuItemWithDynamicLabels(\"CC Number\",\n [=]()\n {\n FaderbankModule::ControllerRecord record = fb->records[faderIndex];\n uint8_t ccMax = record.faderMode == FaderbankModule::FaderMode14bitCC ? 31 : 127;\n\n std::vector ccNames;\n for (auto i = 0; i < ccMax + 1; i++)\n {\n std::ostringstream ss;\n ss << i;\n ccNames.push_back(ss.str());\n }\n return ccNames;\n },\n [=]()\n {\n return fb->records[faderIndex].ccNum;\n },\n [=](int index)\n {\n fb->records[faderIndex].ccNum = index & 0x7F;\n fb->updateInputMap();\n }\n ));\n }\n ));\n}\n\nvoid FaderbankWidget::appendContextMenu(Menu* menu)\n{\n auto fb = dynamic_cast(module);\n if (!fb)\n {\n return;\n }\n\n menu->addChild(new MenuSeparator());\n\n menu->addChild(createUnconsumingIndexSubmenuItem(\"Fader voltage range\", { \"0-10V\", \"0-5V\", \"+/-5V\" },\n [=]() {\n return fb->faderRange;\n },\n [=](int index) {\n fb->faderRange = static_cast(index);\n fb->updateFaderRanges();\n // update all the slider handle positions\n for (widget::Widget* child : children)\n {\n child->step();\n ChangeEvent eChange;\n child->onChange(eChange);\n }\n }));\n\n menu->addChild(createUnconsumingIndexSubmenuItem(\"Fader size\", { \"90mm\", \"60mm\" },\n [=]() {\n return fb->faderSize;\n },\n [=](int index) {\n fb->faderSize = static_cast(index);\n // update all the slider handle positions\n for (widget::Widget* child : children)\n {\n child->step();\n ChangeEvent eChange;\n child->onChange(eChange);\n }\n }\n ));\n\n menu->addChild(createCheckMenuItem(\n \"Polyphonic mode\", \"\",\n [=]() {\n return fb->polyphonicMode;\n },\n [=]() {\n fb->polyphonicMode = !fb->polyphonicMode;\n }));\n\n menu->addChild(new MenuSeparator());\n\n menu->addChild(createMenuItem(\"Autodetect 16n hardware\", \"\",\n [=]()\n {\n fb->autodetectConfig();\n }));\n\n menu->addChild(createSubmenuItem(\"MIDI Configuration\", \"\",\n [=](Menu* configMenu)\n {\n configMenu->addChild(createSubmenuItem(\"Input device\", fb->midiInput.getDeviceName(fb->midiInput.getDeviceId()),\n [=](Menu* childMenu)\n {\n appendMidiMenu(childMenu, &fb->midiInput);\n // remove channel selection\n auto last = childMenu->children.back();\n childMenu->removeChild(last);\n delete last;\n // and separator\n last = childMenu->children.back();\n childMenu->removeChild(last);\n delete last;\n }));\n\n configMenu->addChild(createSubmenuItem(\"Output device\", fb->midiOutput.getDeviceName(fb->midiOutput.getDeviceId()),\n [=](Menu* childMenu)\n {\n appendMidiMenu(childMenu, &fb->midiOutput);\n // remove channel selection\n auto last = childMenu->children.back();\n childMenu->removeChild(last);\n delete last;\n // and separator\n last = childMenu->children.back();\n childMenu->removeChild(last);\n delete last;\n }));\n\n configMenu->addChild(createSubmenuItem(\"Fader settings\", \"\",\n [=](Menu* childMenu)\n {\n for (int i = 0; i < NUM_FADERS; i++)\n {\n appendFaderConfigMenu(fb, childMenu, i);\n }\n }));\n\n configMenu->addChild(new MenuSeparator());\n\n configMenu->addChild(createMenuItem(\"Write configuration to 16n hardware\", \"\",\n [=]()\n {\n fb->writeConfigSysex();\n }\n ));\n }\n ));\n}\n\n" }, { "path": "src/faderbank/FaderbankWidget.hpp", "content": "#include \"rack.hpp\"\n\n#pragma once\n\nstruct FaderbankModule;\n\nstruct FaderbankWidget : rack::app::ModuleWidget\n{\n FaderbankWidget(FaderbankModule* module);\n\n void appendContextMenu(rack::ui::Menu* menu) override;\n};\n" }, { "path": "src/meadowphysics/MeadowphysicsModule.hpp", "content": "#include \"Clock12BitParam.hpp\"\n#include \"LibAVR32Module.hpp\"\n\n#pragma once\n\nstruct MeadowphysicsModule : LibAVR32Module\n{\n enum ParamIds\n {\n CLOCK_PARAM,\n BUTTON_PARAM,\n USB_PARAM,\n NUM_PARAMS\n };\n\n enum InputIds\n {\n CLOCK_INPUT,\n NUM_INPUTS\n };\n\n enum OutputIds\n {\n CLOCK_OUTPUT,\n TR1_OUTPUT,\n TR2_OUTPUT,\n TR3_OUTPUT,\n TR4_OUTPUT,\n TR5_OUTPUT,\n TR6_OUTPUT,\n TR7_OUTPUT,\n TR8_OUTPUT,\n NUM_OUTPUTS\n };\n\n enum LightIds\n {\n CLOCK_LIGHT,\n TR1_LIGHT,\n TR2_LIGHT,\n TR3_LIGHT,\n TR4_LIGHT,\n TR5_LIGHT,\n TR6_LIGHT,\n TR7_LIGHT,\n TR8_LIGHT,\n NUM_LIGHTS\n };\n\n rack::dsp::SchmittTrigger clockTrigger;\n\n MeadowphysicsModule()\n : LibAVR32Module(\"meadowphysics\", \"meadowphysics\")\n {\n config(NUM_PARAMS, NUM_INPUTS, NUM_OUTPUTS, NUM_LIGHTS);\n configButton(BUTTON_PARAM, \"PRESET\");\n configParam>(CLOCK_PARAM, 0.0, 10.0, 5.0, \"CLOCK\", \"ms\");\n configInput(CLOCK_INPUT, \"CLOCK\");\n configOutput(CLOCK_OUTPUT, \"CLOCK\");\n configOutput(TR1_OUTPUT, \"TR 1\");\n configOutput(TR2_OUTPUT, \"TR 2\");\n configOutput(TR3_OUTPUT, \"TR 3\");\n configOutput(TR4_OUTPUT, \"TR 4\");\n configOutput(TR5_OUTPUT, \"TR 5\");\n configOutput(TR6_OUTPUT, \"TR 6\");\n configOutput(TR7_OUTPUT, \"TR 7\");\n configOutput(TR8_OUTPUT, \"TR 8\");\n configButton(USB_PARAM, \"USB Device Port\");\n\n setDeviceConnectionParam(USB_PARAM);\n }\n\n void processInputs(const ProcessArgs& args) override\n {\n // Convert clock input jack to GPIO signals for normal connection and value\n bool clockNormal = !inputs[CLOCK_INPUT].isConnected();\n if (clockNormal != firmware.getGPIO(B09))\n {\n firmware.setGPIO(B09, clockNormal);\n firmware.triggerInterrupt(1);\n }\n\n clockTrigger.process(inputs[CLOCK_INPUT].getVoltage(), triggerLowThreshold, triggerHighThreshold);\n bool externalClock = clockTrigger.isHigh();\n if (externalClock != firmware.getGPIO(B08))\n {\n firmware.setGPIO(B08, externalClock);\n firmware.triggerInterrupt(2);\n }\n\n bool frontButton = params[BUTTON_PARAM].getValue() == 0;\n if (frontButton != firmware.getGPIO(NMI))\n {\n firmware.setGPIO(NMI, frontButton);\n firmware.triggerInterrupt(3);\n }\n\n // Convert knob float parameters to 12-bit ADC values\n firmware.setADC(0, voltsToAdc(params[CLOCK_PARAM].getValue()));\n }\n\n void processOutputs(const ProcessArgs& args) override\n {\n // Update lights from GPIO\n lights[CLOCK_LIGHT].setSmoothBrightness(firmware.getGPIO(B10), args.sampleTime);\n lights[TR1_LIGHT].setSmoothBrightness(firmware.getGPIO(B00), args.sampleTime);\n lights[TR2_LIGHT].setSmoothBrightness(firmware.getGPIO(B01), args.sampleTime);\n lights[TR3_LIGHT].setSmoothBrightness(firmware.getGPIO(B02), args.sampleTime);\n lights[TR4_LIGHT].setSmoothBrightness(firmware.getGPIO(B03), args.sampleTime);\n lights[TR5_LIGHT].setSmoothBrightness(firmware.getGPIO(B04), args.sampleTime);\n lights[TR6_LIGHT].setSmoothBrightness(firmware.getGPIO(B05), args.sampleTime);\n lights[TR7_LIGHT].setSmoothBrightness(firmware.getGPIO(B06), args.sampleTime);\n lights[TR8_LIGHT].setSmoothBrightness(firmware.getGPIO(B07), args.sampleTime);\n\n // Update output jacks from GPIO\n outputs[CLOCK_OUTPUT].setVoltage(firmware.getGPIO(B10) * 8.0);\n outputs[TR1_OUTPUT].setVoltage(firmware.getGPIO(B00) * 8.0);\n outputs[TR2_OUTPUT].setVoltage(firmware.getGPIO(B01) * 8.0);\n outputs[TR3_OUTPUT].setVoltage(firmware.getGPIO(B02) * 8.0);\n outputs[TR4_OUTPUT].setVoltage(firmware.getGPIO(B03) * 8.0);\n outputs[TR5_OUTPUT].setVoltage(firmware.getGPIO(B04) * 8.0);\n outputs[TR6_OUTPUT].setVoltage(firmware.getGPIO(B05) * 8.0);\n outputs[TR7_OUTPUT].setVoltage(firmware.getGPIO(B06) * 8.0);\n outputs[TR8_OUTPUT].setVoltage(firmware.getGPIO(B07) * 8.0);\n }\n};\n" }, { "path": "src/meadowphysics/MeadowphysicsWidget.hpp", "content": "#pragma once\n\n#include \"LibAVR32ModuleWidget.hpp\"\n#include \"SifamTPM.hpp\"\n#include \"USBAJack.hpp\"\n\nusing namespace rack;\n\nstruct MeadowphysicsWidget : LibAVR32ModuleWidget\n{\n MeadowphysicsWidget(MeadowphysicsModule* module)\n {\n setModule(module);\n\n box.size = Vec(15 * 6, 380);\n\n {\n auto panel = new ThemedSvgPanel();\n panel->setBackground(\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/meadowphysics.svg\")),\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/meadowphysics-dark.svg\")));\n panel->box.size = box.size;\n addChild(panel);\n }\n\n // Screws positioned for sliding nuts :)\n addChild(createWidget(Vec(RACK_GRID_WIDTH / 2, 0)));\n addChild(createWidget(Vec(RACK_GRID_WIDTH / 2, RACK_GRID_HEIGHT - RACK_GRID_WIDTH)));\n\n addParam(createParam(Vec(7, 333), module, MeadowphysicsModule::USB_PARAM));\n addParam(createParam(Vec(62, 336), module, MeadowphysicsModule::BUTTON_PARAM));\n addParam(createParam(Vec(12, 232), module, MeadowphysicsModule::CLOCK_PARAM));\n\n addOutput(createOutput(Vec(15, 54), module, MeadowphysicsModule::TR1_OUTPUT));\n addOutput(createOutput(Vec(50, 75), module, MeadowphysicsModule::TR2_OUTPUT));\n addOutput(createOutput(Vec(15, 92), module, MeadowphysicsModule::TR3_OUTPUT));\n addOutput(createOutput(Vec(50, 113), module, MeadowphysicsModule::TR4_OUTPUT));\n addOutput(createOutput(Vec(15, 130), module, MeadowphysicsModule::TR5_OUTPUT));\n addOutput(createOutput(Vec(50, 151), module, MeadowphysicsModule::TR6_OUTPUT));\n addOutput(createOutput(Vec(15, 168), module, MeadowphysicsModule::TR7_OUTPUT));\n addOutput(createOutput(Vec(50, 189), module, MeadowphysicsModule::TR8_OUTPUT));\n addInput(createInput(Vec(15, 286), module, MeadowphysicsModule::CLOCK_INPUT));\n addOutput(createOutput(Vec(50, 286), module, MeadowphysicsModule::CLOCK_OUTPUT));\n\n addChild(createLight>(Vec(3, 71), module, MeadowphysicsModule::TR1_LIGHT));\n addChild(createLight>(Vec(77, 71), module, MeadowphysicsModule::TR2_LIGHT));\n addChild(createLight>(Vec(3, 109), module, MeadowphysicsModule::TR3_LIGHT));\n addChild(createLight>(Vec(77, 109), module, MeadowphysicsModule::TR4_LIGHT));\n addChild(createLight>(Vec(3, 147), module, MeadowphysicsModule::TR5_LIGHT));\n addChild(createLight>(Vec(77, 147), module, MeadowphysicsModule::TR6_LIGHT));\n addChild(createLight>(Vec(3, 185), module, MeadowphysicsModule::TR7_LIGHT));\n addChild(createLight>(Vec(77, 185), module, MeadowphysicsModule::TR8_LIGHT));\n addChild(createLight>(Vec(77, 282), module, MeadowphysicsModule::CLOCK_LIGHT));\n }\n};\n" }, { "path": "src/plugin.cpp", "content": "#include \"AnsibleModule.hpp\"\n#include \"AnsibleWidget.hpp\"\n#include \"EarthseaModule.hpp\"\n#include \"EarthseaWidget.hpp\"\n#include \"FaderbankModule.hpp\"\n#include \"FaderbankWidget.hpp\"\n#include \"MeadowphysicsModule.hpp\"\n#include \"MeadowphysicsWidget.hpp\"\n#include \"SerialOscInterface.hpp\"\n#include \"TeletypeModule.hpp\"\n#include \"TeletypeWidget.hpp\"\n#include \"VirtualGridModule.hpp\"\n#include \"VirtualGridWidget.hpp\"\n#include \"WhiteWhaleModule.hpp\"\n#include \"WhiteWhaleWidget.hpp\"\n#include \"TeletypeKeyboard.hpp\"\n\nusing namespace rack;\n\nPlugin* pluginInstance;\nModel* modelFaderbank;\n\nvoid init(Plugin* p)\n{\n pluginInstance = p;\n\n Model* modelWhiteWhale = createModel(\"whitewhale\");\n Model* modelMeadowphysics = createModel(\"meadowphysics\");\n Model* modelEarthsea = createModel(\"earthsea\");\n\n Model* modelTeletype = createModel(\"teletype\");\n Model* modelAnsible = createModel(\"ansible\");\n\n Model* modelGrid128 = createModel, VirtualGridWidgetTemplate<16, 8>>(\"grid128\");\n Model* modelGrid64 = createModel, VirtualGridWidgetTemplate<8, 8>>(\"grid64\");\n Model* modelGrid256 = createModel, VirtualGridWidgetTemplate<16, 16>>(\"grid256\");\n\n modelFaderbank = createModel(\"faderbank\");\n\n p->addModel(modelWhiteWhale);\n p->addModel(modelMeadowphysics);\n p->addModel(modelEarthsea);\n \n p->addModel(modelTeletype);\n p->addModel(modelAnsible);\n\n p->addModel(modelGrid128);\n p->addModel(modelGrid64);\n p->addModel(modelGrid256);\n\n p->addModel(modelFaderbank);\n\n initThemes();\n}\n\njson_t* settingsToJson()\n{\n json_t* rootJ = json_object();\n json_object_set_new(rootJ, \"keyboardLayout\", json_string(TeletypeKeyboard::getCurrentLayout().c_str()));\n return rootJ;\n}\n\nvoid settingsFromJson(json_t* rootJ)\n{\n json_t* themeJ = json_object_get(rootJ, \"keyboardLayout\");\n if (themeJ)\n TeletypeKeyboard::setCurrentLayout(json_string_value(themeJ));\n}" }, { "path": "src/teletype/TeletypeKeyboard.cpp", "content": "#include \"TeletypeKeyboard.hpp\"\n\n#include \"osdialog.h\"\n#include \n\nusing namespace rack;\n\nextern rack::Plugin* pluginInstance;\n\nTeletypeKeyboard::KeycodeMap TeletypeKeyboard::keycodeMap;\nbool TeletypeKeyboard::initialized = false;\nstd::string TeletypeKeyboard::currentLayout = \"us-qwerty\";\n\nvoid TeletypeKeyboard::init()\n{\n if (!initialized)\n {\n loadMap();\n initialized = true;\n }\n}\n\nvoid TeletypeKeyboard::setCurrentLayout(std::string layoutName)\n{\n if (currentLayout != layoutName)\n {\n currentLayout = layoutName;\n initialized = false;\n }\n}\n\nconst std::string& TeletypeKeyboard::getCurrentLayout()\n{\n return currentLayout;\n}\n\nvoid TeletypeKeyboard::loadMap()\n{\n auto path = rack::asset::plugin(pluginInstance, \"res/keymaps/\" + currentLayout + \".json\");\n\n FILE* file = std::fopen(path.c_str(), \"r\");\n if (!file)\n return;\n DEFER({ std::fclose(file); });\n\n json_error_t error;\n json_t* rootJ = json_loadf(file, 0, &error);\n if (!rootJ)\n {\n std::string message = rack::string::f(\n \"Teletype keymap file %s has invalid JSON at line %d, column %d.\\n\\nError text: %s\",\n path.c_str(),\n error.line,\n error.column,\n error.text\n );\n osdialog_message(OSDIALOG_WARNING, OSDIALOG_OK, message.c_str());\n return;\n }\n\n DEFER({ json_decref(rootJ); });\n\n keycodeMap.clear();\n\n json_t* mapArrayJ = json_object_get(rootJ, \"keymap\");\n if (mapArrayJ)\n {\n size_t i;\n json_t* mapEntryJ;\n json_array_foreach(mapArrayJ, i, mapEntryJ)\n {\n json_t* inputJ = json_object_get(mapEntryJ, \"input\");\n json_t* outputJ = json_object_get(mapEntryJ, \"output\");\n if (inputJ && outputJ)\n {\n int inputCode = stringToGLFWCode(std::string(json_string_value(inputJ)));\n uint8_t outputCode = stringToHIDCode(std::string(json_string_value(outputJ)));\n if (inputCode != GLFW_KEY_UNKNOWN && outputCode != 0)\n {\n int inputMod = 0;\n uint8_t outputMod = 0;\n\n json_t* inputShift = json_object_get(mapEntryJ, \"input_shift\");\n json_t* outputShift = json_object_get(mapEntryJ, \"output_shift\");\n\n if (inputShift && json_boolean_value(inputShift))\n {\n inputMod |= GLFW_MOD_SHIFT;\n }\n\n if (outputShift && json_boolean_value(outputShift))\n {\n outputMod |= 0x02;\n }\n\n keycodeMap.insert(std::make_pair(std::make_pair(inputCode, inputMod), std::make_pair(outputCode, outputMod)));\n }\n }\n }\n }\n}\n\nbool TeletypeKeyboard::process(const rack::event::SelectKey& e, uint8_t* pKey, uint8_t* pMod)\n{\n init();\n\n uint8_t key = 0;\n uint8_t mod = 0;\n\n bool found = false;\n bool shiftConsumed = false;\n\n // Look for a mapping with shift explicitly set\n if (e.mods & GLFW_MOD_SHIFT)\n {\n auto result = keycodeMap.find(std::make_pair(e.key, GLFW_MOD_SHIFT));\n if (result != keycodeMap.end())\n {\n key = result->second.first;\n mod = result->second.second;\n found = true;\n shiftConsumed = true;\n }\n }\n\n // Look for a mapping of the keycode with no modifiers\n if (!found)\n {\n auto result = keycodeMap.find(std::make_pair(e.key, 0));\n if (result != keycodeMap.end())\n {\n key = result->second.first;\n mod = result->second.second;\n found = true;\n }\n }\n\n if (e.mods & GLFW_MOD_CONTROL)\n {\n mod |= 0x1;\n }\n if ((e.mods & GLFW_MOD_SHIFT) && !shiftConsumed)\n {\n mod |= 0x2;\n }\n if (e.mods & GLFW_MOD_ALT)\n {\n mod |= 0x4;\n }\n if (e.mods & GLFW_MOD_SUPER)\n {\n mod |= 0x8;\n }\n\n if (found)\n {\n if (pKey)\n {\n *pKey = key;\n }\n\n if (pMod)\n {\n *pMod = mod;\n }\n }\n\n return found;\n}\n\nint TeletypeKeyboard::stringToGLFWCode(std::string s)\n{\n // Defines from glfw3.h\n if (s == \"GLFW_KEY_UNKNOWN\")\n return GLFW_KEY_UNKNOWN;\n else if (s == \"GLFW_KEY_SPACE\")\n return GLFW_KEY_SPACE;\n else if (s == \"GLFW_KEY_APOSTROPHE\")\n return GLFW_KEY_APOSTROPHE;\n else if (s == \"GLFW_KEY_COMMA\")\n return GLFW_KEY_COMMA;\n else if (s == \"GLFW_KEY_MINUS\")\n return GLFW_KEY_MINUS;\n else if (s == \"GLFW_KEY_PERIOD\")\n return GLFW_KEY_PERIOD;\n else if (s == \"GLFW_KEY_SLASH\")\n return GLFW_KEY_SLASH;\n else if (s == \"GLFW_KEY_0\")\n return GLFW_KEY_0;\n else if (s == \"GLFW_KEY_1\")\n return GLFW_KEY_1;\n else if (s == \"GLFW_KEY_2\")\n return GLFW_KEY_2;\n else if (s == \"GLFW_KEY_3\")\n return GLFW_KEY_3;\n else if (s == \"GLFW_KEY_4\")\n return GLFW_KEY_4;\n else if (s == \"GLFW_KEY_5\")\n return GLFW_KEY_5;\n else if (s == \"GLFW_KEY_6\")\n return GLFW_KEY_6;\n else if (s == \"GLFW_KEY_7\")\n return GLFW_KEY_7;\n else if (s == \"GLFW_KEY_8\")\n return GLFW_KEY_8;\n else if (s == \"GLFW_KEY_9\")\n return GLFW_KEY_9;\n else if (s == \"GLFW_KEY_SEMICOLON\")\n return GLFW_KEY_SEMICOLON;\n else if (s == \"GLFW_KEY_EQUAL\")\n return GLFW_KEY_EQUAL;\n else if (s == \"GLFW_KEY_A\")\n return GLFW_KEY_A;\n else if (s == \"GLFW_KEY_B\")\n return GLFW_KEY_B;\n else if (s == \"GLFW_KEY_C\")\n return GLFW_KEY_C;\n else if (s == \"GLFW_KEY_D\")\n return GLFW_KEY_D;\n else if (s == \"GLFW_KEY_E\")\n return GLFW_KEY_E;\n else if (s == \"GLFW_KEY_F\")\n return GLFW_KEY_F;\n else if (s == \"GLFW_KEY_G\")\n return GLFW_KEY_G;\n else if (s == \"GLFW_KEY_H\")\n return GLFW_KEY_H;\n else if (s == \"GLFW_KEY_I\")\n return GLFW_KEY_I;\n else if (s == \"GLFW_KEY_J\")\n return GLFW_KEY_J;\n else if (s == \"GLFW_KEY_K\")\n return GLFW_KEY_K;\n else if (s == \"GLFW_KEY_L\")\n return GLFW_KEY_L;\n else if (s == \"GLFW_KEY_M\")\n return GLFW_KEY_M;\n else if (s == \"GLFW_KEY_N\")\n return GLFW_KEY_N;\n else if (s == \"GLFW_KEY_O\")\n return GLFW_KEY_O;\n else if (s == \"GLFW_KEY_P\")\n return GLFW_KEY_P;\n else if (s == \"GLFW_KEY_Q\")\n return GLFW_KEY_Q;\n else if (s == \"GLFW_KEY_R\")\n return GLFW_KEY_R;\n else if (s == \"GLFW_KEY_S\")\n return GLFW_KEY_S;\n else if (s == \"GLFW_KEY_T\")\n return GLFW_KEY_T;\n else if (s == \"GLFW_KEY_U\")\n return GLFW_KEY_U;\n else if (s == \"GLFW_KEY_V\")\n return GLFW_KEY_V;\n else if (s == \"GLFW_KEY_W\")\n return GLFW_KEY_W;\n else if (s == \"GLFW_KEY_X\")\n return GLFW_KEY_X;\n else if (s == \"GLFW_KEY_Y\")\n return GLFW_KEY_Y;\n else if (s == \"GLFW_KEY_Z\")\n return GLFW_KEY_Z;\n else if (s == \"GLFW_KEY_LEFT_BRACKET\")\n return GLFW_KEY_LEFT_BRACKET;\n else if (s == \"GLFW_KEY_BACKSLASH\")\n return GLFW_KEY_BACKSLASH;\n else if (s == \"GLFW_KEY_RIGHT_BRACKET\")\n return GLFW_KEY_RIGHT_BRACKET;\n else if (s == \"GLFW_KEY_GRAVE_ACCENT\")\n return GLFW_KEY_GRAVE_ACCENT;\n else if (s == \"GLFW_KEY_WORLD_1\")\n return GLFW_KEY_WORLD_1;\n else if (s == \"GLFW_KEY_WORLD_2\")\n return GLFW_KEY_WORLD_2;\n else if (s == \"GLFW_KEY_ESCAPE\")\n return GLFW_KEY_ESCAPE;\n else if (s == \"GLFW_KEY_ENTER\")\n return GLFW_KEY_ENTER;\n else if (s == \"GLFW_KEY_TAB\")\n return GLFW_KEY_TAB;\n else if (s == \"GLFW_KEY_BACKSPACE\")\n return GLFW_KEY_BACKSPACE;\n else if (s == \"GLFW_KEY_INSERT\")\n return GLFW_KEY_INSERT;\n else if (s == \"GLFW_KEY_DELETE\")\n return GLFW_KEY_DELETE;\n else if (s == \"GLFW_KEY_RIGHT\")\n return GLFW_KEY_RIGHT;\n else if (s == \"GLFW_KEY_LEFT\")\n return GLFW_KEY_LEFT;\n else if (s == \"GLFW_KEY_DOWN\")\n return GLFW_KEY_DOWN;\n else if (s == \"GLFW_KEY_UP\")\n return GLFW_KEY_UP;\n else if (s == \"GLFW_KEY_PAGE_UP\")\n return GLFW_KEY_PAGE_UP;\n else if (s == \"GLFW_KEY_PAGE_DOWN\")\n return GLFW_KEY_PAGE_DOWN;\n else if (s == \"GLFW_KEY_HOME\")\n return GLFW_KEY_HOME;\n else if (s == \"GLFW_KEY_END\")\n return GLFW_KEY_END;\n else if (s == \"GLFW_KEY_CAPS_LOCK\")\n return GLFW_KEY_CAPS_LOCK;\n else if (s == \"GLFW_KEY_SCROLL_LOCK\")\n return GLFW_KEY_SCROLL_LOCK;\n else if (s == \"GLFW_KEY_NUM_LOCK\")\n return GLFW_KEY_NUM_LOCK;\n else if (s == \"GLFW_KEY_PRINT_SCREEN\")\n return GLFW_KEY_PRINT_SCREEN;\n else if (s == \"GLFW_KEY_PAUSE\")\n return GLFW_KEY_PAUSE;\n else if (s == \"GLFW_KEY_F1\")\n return GLFW_KEY_F1;\n else if (s == \"GLFW_KEY_F2\")\n return GLFW_KEY_F2;\n else if (s == \"GLFW_KEY_F3\")\n return GLFW_KEY_F3;\n else if (s == \"GLFW_KEY_F4\")\n return GLFW_KEY_F4;\n else if (s == \"GLFW_KEY_F5\")\n return GLFW_KEY_F5;\n else if (s == \"GLFW_KEY_F6\")\n return GLFW_KEY_F6;\n else if (s == \"GLFW_KEY_F7\")\n return GLFW_KEY_F7;\n else if (s == \"GLFW_KEY_F8\")\n return GLFW_KEY_F8;\n else if (s == \"GLFW_KEY_F9\")\n return GLFW_KEY_F9;\n else if (s == \"GLFW_KEY_F10\")\n return GLFW_KEY_F10;\n else if (s == \"GLFW_KEY_F11\")\n return GLFW_KEY_F11;\n else if (s == \"GLFW_KEY_F12\")\n return GLFW_KEY_F12;\n else if (s == \"GLFW_KEY_F13\")\n return GLFW_KEY_F13;\n else if (s == \"GLFW_KEY_F14\")\n return GLFW_KEY_F14;\n else if (s == \"GLFW_KEY_F15\")\n return GLFW_KEY_F15;\n else if (s == \"GLFW_KEY_F16\")\n return GLFW_KEY_F16;\n else if (s == \"GLFW_KEY_F17\")\n return GLFW_KEY_F17;\n else if (s == \"GLFW_KEY_F18\")\n return GLFW_KEY_F18;\n else if (s == \"GLFW_KEY_F19\")\n return GLFW_KEY_F19;\n else if (s == \"GLFW_KEY_F20\")\n return GLFW_KEY_F20;\n else if (s == \"GLFW_KEY_F21\")\n return GLFW_KEY_F21;\n else if (s == \"GLFW_KEY_F22\")\n return GLFW_KEY_F22;\n else if (s == \"GLFW_KEY_F23\")\n return GLFW_KEY_F23;\n else if (s == \"GLFW_KEY_F24\")\n return GLFW_KEY_F24;\n else if (s == \"GLFW_KEY_F25\")\n return GLFW_KEY_F25;\n else if (s == \"GLFW_KEY_KP_0\")\n return GLFW_KEY_KP_0;\n else if (s == \"GLFW_KEY_KP_1\")\n return GLFW_KEY_KP_1;\n else if (s == \"GLFW_KEY_KP_2\")\n return GLFW_KEY_KP_2;\n else if (s == \"GLFW_KEY_KP_3\")\n return GLFW_KEY_KP_3;\n else if (s == \"GLFW_KEY_KP_4\")\n return GLFW_KEY_KP_4;\n else if (s == \"GLFW_KEY_KP_5\")\n return GLFW_KEY_KP_5;\n else if (s == \"GLFW_KEY_KP_6\")\n return GLFW_KEY_KP_6;\n else if (s == \"GLFW_KEY_KP_7\")\n return GLFW_KEY_KP_7;\n else if (s == \"GLFW_KEY_KP_8\")\n return GLFW_KEY_KP_8;\n else if (s == \"GLFW_KEY_KP_9\")\n return GLFW_KEY_KP_9;\n else if (s == \"GLFW_KEY_KP_DECIMAL\")\n return GLFW_KEY_KP_DECIMAL;\n else if (s == \"GLFW_KEY_KP_DIVIDE\")\n return GLFW_KEY_KP_DIVIDE;\n else if (s == \"GLFW_KEY_KP_MULTIPLY\")\n return GLFW_KEY_KP_MULTIPLY;\n else if (s == \"GLFW_KEY_KP_SUBTRACT\")\n return GLFW_KEY_KP_SUBTRACT;\n else if (s == \"GLFW_KEY_KP_ADD\")\n return GLFW_KEY_KP_ADD;\n else if (s == \"GLFW_KEY_KP_ENTER\")\n return GLFW_KEY_KP_ENTER;\n else if (s == \"GLFW_KEY_KP_EQUAL\")\n return GLFW_KEY_KP_EQUAL;\n\n return GLFW_KEY_UNKNOWN;\n}\n\nuint8_t TeletypeKeyboard::stringToHIDCode(std::string s)\n{\n // HID #defines from Atmel ASF usb_protocol_hid.h\n if (s == \"HID_A\")\n return 0x04;\n else if (s == \"HID_B\")\n return 0x05;\n else if (s == \"HID_C\")\n return 0x06;\n else if (s == \"HID_D\")\n return 0x07;\n else if (s == \"HID_E\")\n return 0x08;\n else if (s == \"HID_F\")\n return 0x09;\n else if (s == \"HID_G\")\n return 0x0A;\n else if (s == \"HID_H\")\n return 0x0B;\n else if (s == \"HID_I\")\n return 0x0C;\n else if (s == \"HID_J\")\n return 0x0D;\n else if (s == \"HID_K\")\n return 0x0E;\n else if (s == \"HID_L\")\n return 0x0F;\n else if (s == \"HID_M\")\n return 0x10;\n else if (s == \"HID_N\")\n return 0x11;\n else if (s == \"HID_O\")\n return 0x12;\n else if (s == \"HID_P\")\n return 0x13;\n else if (s == \"HID_Q\")\n return 0x14;\n else if (s == \"HID_R\")\n return 0x15;\n else if (s == \"HID_S\")\n return 0x16;\n else if (s == \"HID_T\")\n return 0x17;\n else if (s == \"HID_U\")\n return 0x18;\n else if (s == \"HID_V\")\n return 0x19;\n else if (s == \"HID_W\")\n return 0x1A;\n else if (s == \"HID_X\")\n return 0x1B;\n else if (s == \"HID_Y\")\n return 0x1C;\n else if (s == \"HID_Z\")\n return 0x1D;\n else if (s == \"HID_1\")\n return 30;\n else if (s == \"HID_2\")\n return 31;\n else if (s == \"HID_3\")\n return 32;\n else if (s == \"HID_4\")\n return 33;\n else if (s == \"HID_5\")\n return 34;\n else if (s == \"HID_6\")\n return 35;\n else if (s == \"HID_7\")\n return 36;\n else if (s == \"HID_8\")\n return 37;\n else if (s == \"HID_9\")\n return 38;\n else if (s == \"HID_0\")\n return 39;\n else if (s == \"HID_ENTER\")\n return 40;\n else if (s == \"HID_ESCAPE\")\n return 41;\n else if (s == \"HID_BACKSPACE\")\n return 42;\n else if (s == \"HID_TAB\")\n return 43;\n else if (s == \"HID_SPACEBAR\")\n return 44;\n else if (s == \"HID_UNDERSCORE\")\n return 45;\n else if (s == \"HID_PLUS\")\n return 46;\n else if (s == \"HID_OPEN_BRACKET\")\n return 47;\n else if (s == \"HID_CLOSE_BRACKET\")\n return 48;\n else if (s == \"HID_BACKSLASH\")\n return 49;\n else if (s == \"HID_ASH\")\n return 50;\n else if (s == \"HID_COLON\")\n return 51;\n else if (s == \"HID_QUOTE\")\n return 52;\n else if (s == \"HID_TILDE\")\n return 53;\n else if (s == \"HID_COMMA\")\n return 54;\n else if (s == \"HID_DOT\")\n return 55;\n else if (s == \"HID_SLASH\")\n return 56;\n else if (s == \"HID_CAPS_LOCK\")\n return 57;\n else if (s == \"HID_F1\")\n return 58;\n else if (s == \"HID_F2\")\n return 59;\n else if (s == \"HID_F3\")\n return 60;\n else if (s == \"HID_F4\")\n return 61;\n else if (s == \"HID_F5\")\n return 62;\n else if (s == \"HID_F6\")\n return 63;\n else if (s == \"HID_F7\")\n return 64;\n else if (s == \"HID_F8\")\n return 65;\n else if (s == \"HID_F9\")\n return 66;\n else if (s == \"HID_F10\")\n return 67;\n else if (s == \"HID_F11\")\n return 68;\n else if (s == \"HID_F12\")\n return 69;\n else if (s == \"HID_PRINTSCREEN\")\n return 70;\n else if (s == \"HID_SCROLL_LOCK\")\n return 71;\n else if (s == \"HID_PAUSE\")\n return 72;\n else if (s == \"HID_INSERT\")\n return 73;\n else if (s == \"HID_HOME\")\n return 74;\n else if (s == \"HID_PAGEUP\")\n return 75;\n else if (s == \"HID_DELETE\")\n return 76;\n else if (s == \"HID_END\")\n return 77;\n else if (s == \"HID_PAGEDOWN\")\n return 78;\n else if (s == \"HID_RIGHT\")\n return 79;\n else if (s == \"HID_LEFT\")\n return 80;\n else if (s == \"HID_DOWN\")\n return 81;\n else if (s == \"HID_UP\")\n return 82;\n else if (s == \"HID_KEYPAD_NUM_LOCK\")\n return 83;\n else if (s == \"HID_KEYPAD_DIVIDE\")\n return 84;\n else if (s == \"HID_KEYPAD_AT\")\n return 85;\n else if (s == \"HID_KEYPAD_MULTIPLY\")\n return 85;\n else if (s == \"HID_KEYPAD_MINUS\")\n return 86;\n else if (s == \"HID_KEYPAD_PLUS\")\n return 87;\n else if (s == \"HID_KEYPAD_ENTER\")\n return 88;\n else if (s == \"HID_KEYPAD_1\")\n return 89;\n else if (s == \"HID_KEYPAD_2\")\n return 90;\n else if (s == \"HID_KEYPAD_3\")\n return 91;\n else if (s == \"HID_KEYPAD_4\")\n return 92;\n else if (s == \"HID_KEYPAD_5\")\n return 93;\n else if (s == \"HID_KEYPAD_6\")\n return 94;\n else if (s == \"HID_KEYPAD_7\")\n return 95;\n else if (s == \"HID_KEYPAD_8\")\n return 96;\n else if (s == \"HID_KEYPAD_9\")\n return 97;\n else if (s == \"HID_KEYPAD_0\")\n return 98;\n else if (s == \"HID_KEYPAD_DECIMAL\") // not in usb_protocol_hid.h or used in TT code, but previously supported\n return 99;\n\n return 0;\n}\n" }, { "path": "src/teletype/TeletypeKeyboard.hpp", "content": "#pragma once\n#include \"rack.hpp\"\n#include \n\n\n\nstruct TeletypeKeyboard\n{\n static void init();\n static void setCurrentLayout(std::string layoutName);\n static const std::string& getCurrentLayout();\n static bool process(const rack::event::SelectKey& e, uint8_t* pkey, uint8_t* pmod);\n\n static int stringToGLFWCode(std::string s);\n static uint8_t stringToHIDCode(std::string s);\n\nprotected:\n static void loadMap();\n typedef std::map, std::pair> KeycodeMap;\n static KeycodeMap keycodeMap;\n static bool initialized;\n static std::string currentLayout;\n};" }, { "path": "src/teletype/TeletypeModule.cpp", "content": "#include \"TeletypeModule.hpp\"\n#include \"scene/TeletypeSceneIO.hpp\"\n#include \"screen/EngineStoppedScreen.hpp\"\n\n#include \n\n#define TO_Q15(x) ((x) << 15)\n#define FROM_Q15(x) ((((x) >> 14) + 1) >> 1)\n\nstruct TTParamQuantity : rack::engine::ParamQuantity\n{\n std::string getDisplayValueString() override\n {\n float v = getDisplayValue();\n if (std::isnan(v))\n return \"NaN\";\n\n // Calculate the same value that the TT firmware will calculate from this voltage.\n // 0-10V 12-bit ADC, shifted left 2 bits (to 0-16380), then scaled to 0-16383 in Q15 fixed-point\n uint16_t rawval = ((uint16_t)(v * 0.1f * 4095.0f) & 0xFFF) << 2;\n return rack::string::f(\"%d\", FROM_Q15(TO_Q15(16383) / 16380 * rawval));\n }\n\n void setDisplayValue(float dv) override\n {\n // Reverse the above calc to set the float voltage that the ADC will turn into the given value\n uint16_t val = rack::math::clamp((int)floor(dv), 0, 16383);\n uint16_t rawval = FROM_Q15(TO_Q15(16380) / 16383 * val);\n // Add the same 12-bit sampling error correction offset here\n setImmediateValue(rawval * (10.0 / 16380.0) + 0.0007);\n }\n};\n\nTeletypeModule::TeletypeModule()\n: LibAVR32Module(\"teletype\", \"teletype5\")\n, iiBus(this)\n, screenBuffer{}\n{\n // initialize screen with \"engine stopped\" message\n memcpy(screenBuffer, engineStoppedScreen, 128 * 40 * sizeof(uint8_t));\n\n firmware.setScreenBuffer(getScreenBuffer());\n\n config(NUM_PARAMS, NUM_INPUTS, NUM_OUTPUTS, NUM_LIGHTS);\n configParam(PARAM_PARAM, 0.0, 10.0, 5.0, \"PARAM\", \"\");\n configButton(BUTTON_PARAM, \"SCENE\");\n configInput(IN_INPUT, \"IN\");\n configInput(TRIG1_INPUT, \"TRIGGER 1\");\n configInput(TRIG2_INPUT, \"TRIGGER 2\");\n configInput(TRIG3_INPUT, \"TRIGGER 3\");\n configInput(TRIG4_INPUT, \"TRIGGER 4\");\n configInput(TRIG5_INPUT, \"TRIGGER 5\");\n configInput(TRIG6_INPUT, \"TRIGGER 6\");\n configInput(TRIG7_INPUT, \"TRIGGER 7\");\n configInput(TRIG8_INPUT, \"TRIGGER 8\");\n configOutput(TR1_OUTPUT, \"TR 1\");\n configOutput(TR2_OUTPUT, \"TR 2\");\n configOutput(TR3_OUTPUT, \"TR 3\");\n configOutput(TR4_OUTPUT, \"TR 4\");\n configOutput(CV1_OUTPUT, \"CV 1\");\n configOutput(CV2_OUTPUT, \"CV 2\");\n configOutput(CV3_OUTPUT, \"CV 3\");\n configOutput(CV4_OUTPUT, \"CV 4\");\n configButton(USB_PARAM, \"USB Device Port\");\n\n setDeviceConnectionParam(USB_PARAM);\n}\n\nvoid TeletypeModule::processInputs(const ProcessArgs& args)\n{\n bool frontButton = params[BUTTON_PARAM].getValue() == 0;\n if (frontButton != firmware.getGPIO(NMI))\n {\n firmware.setGPIO(NMI, frontButton);\n firmware.triggerInterrupt(3);\n }\n\n // Convert knob float parameters to 12-bit ADC values\n firmware.setADC(1, voltsToAdc(params[PARAM_PARAM].getValue()));\n firmware.setADC(0, voltsToAdc(inputs[IN_INPUT].getVoltage()));\n\n for (int i = 0; i < 8; i++)\n {\n inputTriggers[i].process(\n inputs[TRIG1_INPUT + i].getVoltage(),\n triggerLowThreshold,\n triggerHighThreshold);\n\n firmware.setGPIO(A00 + i, inputTriggers[i].isHigh());\n }\n\n // process II follower-to-leader input\n // no support for leader-to-follower commands right now\n iiBus.step();\n}\n\nvoid TeletypeModule::processOutputs(const ProcessArgs& args)\n{\n float cv1 = dacToVolts(firmware.getDAC(2));\n float cv2 = dacToVolts(firmware.getDAC(3));\n float cv3 = dacToVolts(firmware.getDAC(0));\n float cv4 = dacToVolts(firmware.getDAC(1));\n\n bool tr1 = firmware.getGPIO(B08);\n bool tr2 = firmware.getGPIO(B09);\n bool tr3 = firmware.getGPIO(B10);\n bool tr4 = firmware.getGPIO(B11);\n\n // Update lights\n lights[TR1_LIGHT].setSmoothBrightness(tr1, args.sampleTime);\n lights[TR2_LIGHT].setSmoothBrightness(tr2, args.sampleTime);\n lights[TR3_LIGHT].setSmoothBrightness(tr3, args.sampleTime);\n lights[TR4_LIGHT].setSmoothBrightness(tr4, args.sampleTime);\n lights[CV1_LIGHT].setSmoothBrightness(cv1 / 10.0, args.sampleTime);\n lights[CV2_LIGHT].setSmoothBrightness(cv2 / 10.0, args.sampleTime);\n lights[CV3_LIGHT].setSmoothBrightness(cv3 / 10.0, args.sampleTime);\n lights[CV4_LIGHT].setSmoothBrightness(cv4 / 10.0, args.sampleTime);\n\n // Update TR outs from GPIO (8V)\n outputs[TR1_OUTPUT].setVoltage(tr1 * 8.0);\n outputs[TR2_OUTPUT].setVoltage(tr2 * 8.0);\n outputs[TR3_OUTPUT].setVoltage(tr3 * 8.0);\n outputs[TR4_OUTPUT].setVoltage(tr4 * 8.0);\n\n // Update CV outs from DAC\n outputs[CV1_OUTPUT].setVoltage(cv1);\n outputs[CV2_OUTPUT].setVoltage(cv2);\n outputs[CV3_OUTPUT].setVoltage(cv3);\n outputs[CV4_OUTPUT].setVoltage(cv4);\n}\n\njson_t* TeletypeModule::dataToJson()\n{\n json_t* rootJ = LibAVR32Module::dataToJson();\n\n json_object_set_new(rootJ, \"theme\", json_integer(theme));\n\n return rootJ;\n}\n\nvoid TeletypeModule::dataFromJson(json_t* rootJ)\n{\n LibAVR32Module::dataFromJson(rootJ);\n\n auto json_theme = json_object_get(rootJ, \"theme\");\n if (json_theme)\n {\n theme = static_cast(json_integer_value(json_theme));\n }\n\n // Special json key only in factory presets, not saved in dataToJson\n json_t* jd = json_object_get(rootJ, \"loadScript\");\n if (jd)\n {\n json_t* scriptDataJson = json_object_get(jd, \"data\");\n json_t* jsonActive = json_object_get(jd, \"active\");\n json_t* jsonFlash = json_object_get(jd, \"flash\");\n\n bool loadActive = jsonActive && json_is_true(jsonActive);\n bool loadFlash = jsonFlash && json_is_number(jsonFlash);\n\n if ((loadActive || loadFlash) && scriptDataJson && json_is_string(scriptDataJson))\n {\n std::string script = json_string_value(scriptDataJson);\n reloadFirmware(false);\n\n if (loadActive)\n {\n TeletypeSceneIO::presetImportString(this, script, 255, true);\n }\n\n if (loadFlash)\n {\n int num = json_integer_value(jsonFlash);\n if (num >= 0 && num < 32)\n {\n TeletypeSceneIO::presetImportString(this, script, num, true);\n }\n }\n\n // send an ESC press/release to open preset description\n firmware.hidMessage(0x29, 0, false, false);\n firmware.hidMessage(0x29, 0, false, true);\n }\n }\n}" }, { "path": "src/teletype/TeletypeModule.hpp", "content": "#include \"LibAVR32Module.hpp\"\n#include \"IIBus.h\"\n\n#include \"rack.hpp\"\n\n\nstruct TeletypeModule : LibAVR32Module\n{\n enum ParamIds\n {\n PARAM_PARAM,\n BUTTON_PARAM,\n USB_PARAM,\n NUM_PARAMS\n };\n enum InputIds\n {\n TRIG1_INPUT,\n TRIG2_INPUT,\n TRIG3_INPUT,\n TRIG4_INPUT,\n TRIG5_INPUT,\n TRIG6_INPUT,\n TRIG7_INPUT,\n TRIG8_INPUT,\n IN_INPUT,\n NUM_INPUTS\n };\n enum OutputIds\n {\n TR1_OUTPUT,\n TR2_OUTPUT,\n TR3_OUTPUT,\n TR4_OUTPUT,\n CV1_OUTPUT,\n CV2_OUTPUT,\n CV3_OUTPUT,\n CV4_OUTPUT,\n NUM_OUTPUTS\n };\n enum LightIds\n {\n TR1_LIGHT,\n TR2_LIGHT,\n TR3_LIGHT,\n TR4_LIGHT,\n CV1_LIGHT,\n CV2_LIGHT,\n CV3_LIGHT,\n CV4_LIGHT,\n NUM_LIGHTS\n };\n\n TeletypeModule();\n\n void processInputs(const ProcessArgs& args) override;\n void processOutputs(const ProcessArgs& args) override;\n\n json_t* dataToJson() override;\n void dataFromJson(json_t* rootJ) override;\n\n rack::dsp::SchmittTrigger inputTriggers[8];\n\n virtual uint8_t* getScreenBuffer() override { return screenBuffer; }\n\nprotected:\n IIBus iiBus;\n\n uint8_t screenBuffer[128 * 64];\n};\n" }, { "path": "src/teletype/TeletypeWidget.cpp", "content": "#include \"TeletypeWidget.hpp\"\n#include \"SifamTPM.hpp\"\n#include \"TeletypeKeyboard.hpp\"\n#include \"TeletypeModule.hpp\"\n#include \"USBAJack.hpp\"\n#include \"scene/TeletypeSceneIOMenu.hpp\"\n#include \"screen/TeletypeScreenWidget.hpp\"\n#include \n\nnamespace fs = ghc::filesystem;\n\nTeletypeWidget::TeletypeWidget(TeletypeModule* module)\n{\n setModule(module);\n\n box.size = Vec(15 * 18, 380);\n\n {\n auto panel = new ThemedSvgPanel();\n panel->setBackground(\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/teletype.svg\")),\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/teletype-dark.svg\")));\n panel->box.size = box.size;\n addChild(panel);\n }\n\n addChild(createWidget(Vec(RACK_GRID_WIDTH, 0)));\n addChild(createWidget(Vec(box.size.x - 2 * RACK_GRID_WIDTH, 0)));\n addChild(createWidget(Vec(RACK_GRID_WIDTH, RACK_GRID_HEIGHT - RACK_GRID_WIDTH)));\n addChild(createWidget(Vec(box.size.x - 2 * RACK_GRID_WIDTH, RACK_GRID_HEIGHT - RACK_GRID_WIDTH)));\n\n addParam(createParam(Vec(7, 333), module, TeletypeModule::USB_PARAM));\n addParam(createParam(Vec(62, 337), module, TeletypeModule::BUTTON_PARAM));\n\n screen = new TeletypeScreenWidget(module);\n screen->box.pos = Vec(30, 200);\n screen->box.size = Vec(210, 112);\n addChild(screen);\n\n addParam(createParam(Vec(211, 47.5), module, TeletypeModule::PARAM_PARAM));\n\n addInput(createInput(Vec(11, 38.5), module, TeletypeModule::TRIG1_INPUT));\n addInput(createInput(Vec(50.5, 38.5), module, TeletypeModule::TRIG3_INPUT));\n addInput(createInput(Vec(90, 38.5), module, TeletypeModule::TRIG5_INPUT));\n addInput(createInput(Vec(130, 38.5), module, TeletypeModule::TRIG7_INPUT));\n addInput(createInput(Vec(30, 77.5), module, TeletypeModule::TRIG2_INPUT));\n addInput(createInput(Vec(69.5, 77.5), module, TeletypeModule::TRIG4_INPUT));\n addInput(createInput(Vec(109, 77.5), module, TeletypeModule::TRIG6_INPUT));\n addInput(createInput(Vec(148.5, 77.5), module, TeletypeModule::TRIG8_INPUT));\n\n addInput(createInput(Vec(169, 38.5), module, TeletypeModule::IN_INPUT));\n\n addOutput(createOutput(Vec(90, 117.5), module, TeletypeModule::TR1_OUTPUT));\n addOutput(createOutput(Vec(129.5, 117.5), module, TeletypeModule::TR2_OUTPUT));\n addOutput(createOutput(Vec(169, 117.5), module, TeletypeModule::TR3_OUTPUT));\n addOutput(createOutput(Vec(208.5, 117.5), module, TeletypeModule::TR4_OUTPUT));\n addOutput(createOutput(Vec(109, 157.5), module, TeletypeModule::CV1_OUTPUT));\n addOutput(createOutput(Vec(148.5, 157.5), module, TeletypeModule::CV2_OUTPUT));\n addOutput(createOutput(Vec(188, 157.5), module, TeletypeModule::CV3_OUTPUT));\n addOutput(createOutput(Vec(227.5, 157.5), module, TeletypeModule::CV4_OUTPUT));\n\n addChild(createLight>(Vec(117, 112), module, TeletypeModule::TR1_LIGHT));\n addChild(createLight>(Vec(156.5, 112), module, TeletypeModule::TR2_LIGHT));\n addChild(createLight>(Vec(196, 112), module, TeletypeModule::TR3_LIGHT));\n addChild(createLight>(Vec(235.5, 112), module, TeletypeModule::TR4_LIGHT));\n addChild(createLight>(Vec(136, 152), module, TeletypeModule::CV1_LIGHT));\n addChild(createLight>(Vec(175.5, 152), module, TeletypeModule::CV2_LIGHT));\n addChild(createLight>(Vec(215, 152), module, TeletypeModule::CV3_LIGHT));\n addChild(createLight>(Vec(254.5, 152), module, TeletypeModule::CV4_LIGHT));\n}\n\nstruct TeletypeKeyboardLayoutItem : rack::ui::MenuItem\n{\n LibAVR32Module* module;\n\n TeletypeKeyboardLayoutItem()\n {\n text = \"Keyboard Layout\";\n rightText = TeletypeKeyboard::getCurrentLayout() + \" \" + RIGHT_ARROW;\n }\n\n ui::Menu* createChildMenu() override\n {\n std::vector layoutNames = {};\n\n const fs::path mapPath { rack::asset::plugin(pluginInstance, \"res/keymaps\") };\n for (auto const& file : fs::directory_iterator { mapPath })\n {\n auto name = file.path().stem().string();\n auto extension = file.path().extension().string();\n if (extension == \".json\")\n {\n layoutNames.push_back(name);\n }\n }\n\n ui::Menu* menu = new ui::Menu;\n\n for (auto const& name : layoutNames)\n {\n menu->addChild(createCheckMenuItem(\n name,\n \"\",\n [=]()\n {\n return name == TeletypeKeyboard::getCurrentLayout();\n },\n [=]()\n {\n TeletypeKeyboard::setCurrentLayout(name);\n TeletypeKeyboard::init();\n }\n ));\n }\n\n return menu;\n }\n};\n\nstruct TeletypeKeystrokeItem : rack::ui::MenuItem\n{\n TeletypeModule* module;\n rack::widget::Widget* screen;\n uint8_t key;\n uint8_t mod;\n\n TeletypeKeystrokeItem(TeletypeModule* module, rack::widget::Widget* screen, uint8_t key, uint8_t mod, std::string _text, std::string _rightText = \"\")\n : module(module)\n , screen(screen)\n , key(key)\n , mod(mod)\n {\n text = _text;\n rightText = _rightText;\n }\n\n void onAction(const rack::event::Action& e) override\n {\n if (module)\n {\n module->firmware.hidMessage(key, mod, false, false);\n module->firmware.hidMessage(key, mod, false, true);\n\n if (screen) {\n APP->event->setSelectedWidget(screen);\n }\n }\n }\n};\n\nvoid TeletypeWidget::appendContextMenu(rack::Menu* menu)\n{\n LibAVR32ModuleWidget::appendContextMenu(menu);\n\n TeletypeModule* m = dynamic_cast(module);\n assert(m);\n\n menu->addChild(new MenuSeparator());\n\n menu->addChild(createIndexPtrSubmenuItem(\"Theme\", { \"Red\", \"Orange\", \"Yellow\", \"White\" }, &m->theme));\n menu->addChild(new TeletypeKeyboardLayoutItem());\n\n menu->addChild(new MenuSeparator());\n\n menu->addChild(new InternalPresetSubmenu(m, \"Import scenes\", Load));\n menu->addChild(new InternalPresetSubmenu(m, \"Export scenes\", Save));\n\n menu->addChild(new MenuSeparator());\n\n menu->addChild(construct(&MenuLabel::text, \"Shortcuts\"));\n\n menu->addChild(new TeletypeKeystrokeItem(m, screen, 0x45, 0, \"LIVE mode\", \"F12\"));\n menu->addChild(new TeletypeKeystrokeItem(m, screen, 0x3a, 4, \"EDIT mode\", \"Alt+F1\"));\n menu->addChild(new TeletypeKeystrokeItem(m, screen, 0x44, 0, \"TRACKER mode\", \"F11\"));\n menu->addChild(new TeletypeKeystrokeItem(m, screen, 0x2b, 0, \"Cycle LIVE/EDIT/TRACKER\", \"Tab\"));\n menu->addChild(new TeletypeKeystrokeItem(m, screen, 0x29, 0, \"SCENE READ mode\", \"Esc\"));\n menu->addChild(new TeletypeKeystrokeItem(m, screen, 0x29, 4, \"SCENE WRITE mode\", \"Alt+Esc\"));\n //menu->addChild(new TeletypeKeystrokeItem(m, screen, 0x0a, 4, \"GRID visualizer mode\", \"Alt+G\"));\n //menu->addChild(new TeletypeKeystrokeItem(m, screen, 0x35, 0, \"Toggle system variables display\", \"~\"));\n menu->addChild(new TeletypeKeystrokeItem(m, screen, 0x2f, 0, \"Previous script/page/value/scene\", \"[\"));\n menu->addChild(new TeletypeKeystrokeItem(m, screen, 0x30, 0, \"Next script/page/value/scene\", \"]\"));\n menu->addChild(new TeletypeKeystrokeItem(m, screen, 0x0b, 4, \"HELP mode\", \"Alt+H\"));\n}" }, { "path": "src/teletype/TeletypeWidget.hpp", "content": "#include \"LibAVR32ModuleWidget.hpp\"\n\n#pragma once\n\nstruct TeletypeModule;\n\nstruct TeletypeWidget : LibAVR32ModuleWidget\n{\n TeletypeWidget(TeletypeModule* module);\n\n virtual void appendContextMenu(rack::ui::Menu* menu) override;\n rack::widget::Widget* screen;\n};" }, { "path": "src/teletype/scene/TeletypeSceneIO.cpp", "content": "#include \"TeletypeSceneIO.hpp\"\n#include \"LibAVR32Module.hpp\"\n\n#include \"osdialog.h\"\n#include \n#include \n\n#include \"rack.hpp\"\n\nvoid TeletypeSceneIO::presetImportExportFileOperation(LibAVR32Module* module, SceneOperation operation, int preset_num, std::string fileName)\n{\n if (!module)\n {\n return;\n }\n\n if (operation == Save)\n {\n FILE* file = std::fopen(fileName.c_str(), \"w+\");\n if (!file)\n {\n std::string message = rack::string::f(\"Couldn't write to %s. Error: %d\", fileName.c_str(), errno);\n osdialog_message(OSDIALOG_WARNING, OSDIALOG_OK, message.c_str());\n return;\n }\n DEFER({\n std::fclose(file);\n });\n\n tt_serializer_t stream {\n .write_buffer = [](void* user_data, uint8_t* buffer, uint16_t size)\n { std::fwrite(buffer, 1, size, static_cast(user_data)); },\n .write_char = [](void* user_data, uint8_t c)\n { std::fputc(c, static_cast(user_data)); },\n .print_dbg = [](const char* c) {},\n .data = (void*)file,\n };\n\n module->firmware.serializePreset(&stream, preset_num);\n }\n else\n {\n std::ifstream ifs(fileName);\n std::string scene(\n (std::istreambuf_iterator(ifs)),\n (std::istreambuf_iterator())\n );\n\n TeletypeSceneIO::presetImportString(module, scene, preset_num, true);\n }\n}\n\nvoid TeletypeSceneIO::presetImportExportClipboardOperation(LibAVR32Module* module, SceneOperation operation, int preset_num, bool clearExisting)\n{\n if (!module)\n {\n return;\n }\n\n if (operation == Save)\n {\n std::stringstream clip;\n\n tt_serializer_t stream {\n .write_buffer = [](void* user_data, uint8_t* buffer, uint16_t size)\n { *static_cast(user_data) << std::string(buffer, buffer + size); },\n .write_char = [](void* user_data, uint8_t c)\n { *static_cast(user_data) << c; },\n .print_dbg = [](const char* c) {},\n .data = (void*)&clip,\n };\n\n module->firmware.serializePreset(&stream, preset_num);\n\n glfwSetClipboardString(APP->window->win, clip.str().c_str());\n }\n else\n {\n std::string rawclip(glfwGetClipboardString(APP->window->win));\n\n TeletypeSceneIO::presetImportString(module, rawclip, preset_num, clearExisting);\n }\n}\n\nvoid TeletypeSceneIO::presetImportString(LibAVR32Module* module, std::string scene, int preset_num, bool clearExisting)\n{\n // Remove any linefeeds\n scene.erase(std::remove(scene.begin(), scene.end(), '\\r'), scene.end());\n\n // Tabs in pattern/grid sections may have been turned into spaces. Turn them back\n auto patStart = scene.find(\"#P\");\n auto gridStart = scene.find(\"#G\");\n if (patStart != std::string::npos || gridStart != std::string::npos)\n {\n auto start =\n patStart == std::string::npos\n ? gridStart\n : gridStart == std::string::npos\n ? patStart\n : std::min(patStart, gridStart);\n\n std::regex r(\" +\");\n std::string tab(\"\\t\");\n std::string result = scene.substr(0, start);\n std::regex_replace(std::back_inserter(result), scene.begin() + start, scene.end(), r, tab);\n scene = result;\n }\n\n // Add a final newline, since a selection in discord/browser probably won't include it\n scene += \"\\n\";\n\n module->audioThreadActions.push([=]() {\n std::stringstream clip(scene);\n\n tt_deserializer_t stream {\n .read_char = [](void* user_data)\n { return static_cast(static_cast(user_data)->get()); },\n .eof = [](void* user_data)\n { return static_cast(user_data)->eof(); },\n .print_dbg = [](const char* c) {},\n .data = (void*)&clip,\n };\n\n module->firmware.deserializePreset(&stream, preset_num, clearExisting);\n });\n}\n" }, { "path": "src/teletype/scene/TeletypeSceneIO.hpp", "content": "#include \n\nstruct LibAVR32Module;\n\ntypedef enum\n{\n Load = 0,\n Save\n} SceneOperation;\n\nstruct TeletypeSceneIO\n{\n static void presetImportString(LibAVR32Module* module, std::string scene, int preset_num, bool clearExisting);\n\n static void presetImportExportFileOperation(LibAVR32Module* module, SceneOperation operation, int preset_num, std::string fileName);\n static void presetImportExportClipboardOperation(LibAVR32Module* module, SceneOperation operation, int preset_num, bool clearExisting);\n};" }, { "path": "src/teletype/scene/TeletypeSceneIOMenu.cpp", "content": "#include \"TeletypeSceneIOMenu.hpp\"\n\n#include \"osdialog.h\"\n#include \"rack.hpp\"\n#include \n\n#ifdef ARCH_WIN\n#define PATH_SEPARATOR '\\\\'\n#else\n#define PATH_SEPARATOR '/'\n#endif\n\nstruct InternalPresetItem : rack::ui::MenuItem\n{\n LibAVR32Module* module;\n int preset_num;\n SceneOperation operation;\n\n InternalPresetItem(LibAVR32Module* module, int preset_num, SceneOperation operation)\n : module(module)\n , preset_num(preset_num)\n , operation(operation)\n {\n if (preset_num == -1)\n {\n text = (operation == Load ? \"Import from file\" : \"Export to file\");\n } else {\n text = (operation == Load ? \".txt → \" : \"\") + std::to_string(preset_num) + (operation == Save ? \" → .txt\" : \"\");\n }\n }\n\n void onAction(const rack::event::Action& e) override\n {\n osdialog_filters* filters = osdialog_filters_parse(\"Teletype Scene Files (*.txt):txt\");\n\n std::stringstream defaultFileName;\n if (preset_num < 0)\n {\n defaultFileName << \"tt_active\" << (operation == Save ? \"_s.txt\" : \".txt\");\n }\n else\n {\n defaultFileName\n << \"tt\"\n << std::setw(2) << std::setfill('0') << preset_num\n << (operation == Save ? \"s.txt\" : \".txt\");\n }\n\n char* path_result = osdialog_file(\n operation == Save ? OSDIALOG_SAVE : OSDIALOG_OPEN,\n NULL,\n defaultFileName.str().c_str(),\n filters);\n\n osdialog_filters_free(filters);\n\n if (!path_result)\n return;\n\n std::string path(path_result);\n std::free(path_result);\n\n TeletypeSceneIO::presetImportExportFileOperation(module, operation, preset_num, path);\n }\n};\n\nstruct InternalPresetClipboardItem : rack::ui::MenuItem\n{\n LibAVR32Module* module;\n int preset_num;\n SceneOperation operation;\n bool clearExisting;\n\n InternalPresetClipboardItem(LibAVR32Module* module, int preset_num, SceneOperation operation, bool clearExisting = true)\n : module(module)\n , preset_num(preset_num)\n , operation(operation)\n , clearExisting(clearExisting)\n {\n text = (operation == Save ?\n \"Copy to clipboard\" :\n (clearExisting ? \"Paste and init new scene from clipboard\" : \"Paste and merge clipboard into current scene\"));\n }\n\n void onAction(const rack::event::Action& e) override\n {\n TeletypeSceneIO::presetImportExportClipboardOperation(module, operation, preset_num, clearExisting);\n }\n};\n\nstruct InternalPresetBulkItem : rack::ui::MenuItem\n{\n LibAVR32Module* module;\n SceneOperation operation;\n std::string suffix;\n\n InternalPresetBulkItem(LibAVR32Module* module, SceneOperation operation, std::string suffix)\n : module(module)\n , operation(operation)\n , suffix(suffix)\n {\n text = operation == Load\n ? (\"tt##\" + suffix + \".txt → All\")\n : (\"All → tt##\" + suffix + \".txt\");\n }\n\n void onAction(const rack::event::Action& e) override\n {\n char* path_result = osdialog_file(\n OSDIALOG_OPEN_DIR,\n NULL,\n NULL,\n NULL);\n\n if (!path_result)\n return;\n\n std::string path(path_result);\n std::free(path_result);\n\n for (int i = 0; i < 32; i++)\n {\n std::stringstream fileName;\n fileName\n << path\n << PATH_SEPARATOR\n << \"tt\"\n << std::setfill('0') << std::setw(2) << i\n << suffix\n << \".txt\";\n TeletypeSceneIO::presetImportExportFileOperation(module, operation, i, fileName.str());\n }\n }\n};\n\nstruct InternalPresetActiveSubmenu : rack::ui::MenuItem\n{\n LibAVR32Module* module;\n SceneOperation operation;\n\n InternalPresetActiveSubmenu(LibAVR32Module* module, SceneOperation operation)\n : module(module)\n , operation(operation)\n {\n text = \"Active scene\";\n rightText = \"▸\";\n }\n\n rack::ui::Menu* createChildMenu() override\n {\n LibAVR32Module* m = dynamic_cast(module);\n assert(m);\n\n auto menu = new rack::ui::Menu();\n\n menu->addChild(new InternalPresetItem(module, -1, operation));\n menu->addChild(new InternalPresetClipboardItem(module, -1, operation));\n if (operation == Load) {\n menu->addChild(new InternalPresetClipboardItem(module, -1, operation, false)); // paste and merge\n }\n\n return menu;\n }\n};\n\nstruct InternalPresetGroupSubmenu : rack::ui::MenuItem\n{\n LibAVR32Module* module;\n SceneOperation operation;\n int first;\n int last;\n\n InternalPresetGroupSubmenu(LibAVR32Module* module, int first, int last, SceneOperation operation)\n : module(module)\n , operation(operation)\n , first(first)\n , last(last)\n {\n text = std::to_string(first) + \" - \" + std::to_string(last);\n rightText = \"▸\";\n }\n\n rack::ui::Menu* createChildMenu() override\n {\n LibAVR32Module* m = dynamic_cast(module);\n assert(m);\n\n auto menu = new rack::ui::Menu();\n\n for (int i = first; i <= last; i++)\n {\n menu->addChild(new InternalPresetItem(module, i, operation));\n }\n return menu;\n }\n};\n\nInternalPresetSubmenu::InternalPresetSubmenu(LibAVR32Module* module, std::string _text, SceneOperation operation)\n : module(module)\n , operation(operation)\n{\n text = _text;\n rightText = \"▸\";\n}\n\nrack::ui::Menu* InternalPresetSubmenu::createChildMenu()\n{\n LibAVR32Module* m = dynamic_cast(module);\n assert(m);\n\n auto menu = new rack::ui::Menu();\n\n menu->addChild(new InternalPresetActiveSubmenu(module, operation));\n\n for (int i = 0; i < 4; i++)\n {\n menu->addChild(new InternalPresetGroupSubmenu(module, i * 8, i * 8 + 7, operation));\n }\n menu->addChild(new InternalPresetBulkItem(module, operation, \"\"));\n menu->addChild(new InternalPresetBulkItem(module, operation, \"s\"));\n return menu;\n}\n" }, { "path": "src/teletype/scene/TeletypeSceneIOMenu.hpp", "content": "#include \"TeletypeSceneIO.hpp\"\n#include \n\nstruct InternalPresetSubmenu : rack::ui::MenuItem\n{\n LibAVR32Module* module;\n SceneOperation operation;\n\n InternalPresetSubmenu(LibAVR32Module* module, std::string _text, SceneOperation operation);\n rack::ui::Menu* createChildMenu() override;\n};" }, { "path": "src/teletype/screen/EngineStoppedScreen.hpp", "content": "\nunsigned char engineStoppedScreen[128 * 40] = {\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 0x0,\n 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}\n}\n\nvoid TeletypeScreenWidget::onSelect(const event::Select& e)\n{\n}\n\nvoid TeletypeScreenWidget::onDeselect(const event::Deselect& e)\n{\n}\n\nvoid TeletypeScreenWidget::onSelectKey(const event::SelectKey& e)\n{\n uint8_t key = 0;\n uint8_t mod = 0;\n\n if (TeletypeKeyboard::process(e, &key, &mod))\n {\n if (module)\n {\n if (e.action == GLFW_PRESS)\n {\n module->firmware.hidMessage(key, mod, false, false);\n }\n else if (e.action == GLFW_REPEAT)\n {\n module->firmware.hidMessage(key, mod, true, false);\n }\n else if (e.action == GLFW_RELEASE)\n {\n module->firmware.hidMessage(key, mod, false, true);\n }\n }\n }\n\n e.consume(this);\n}\n\nvoid TeletypeScreenWidget::draw(const DrawArgs& args)\n{\n drawFrame(args.vg);\n}\n\nvoid TeletypeScreenWidget::drawLayer(const DrawArgs& args, int layer)\n{\n if (layer == 1)\n {\n if (this == APP->event->selectedWidget)\n {\n drawFocusRectangle(args.vg);\n }\n drawPixels(args.vg);\n }\n}\n\nvoid TeletypeScreenWidget::drawFrame(NVGcontext* vg)\n{\n NVGcolor hiColor = !settings::preferDarkPanels ? nvgRGB(250, 250, 250) : nvgRGB(96, 96, 94);\n NVGcolor loColor = !settings::preferDarkPanels ? nvgRGB(140, 140, 130) : nvgRGB(20, 20, 5);\n\n // draw skeumorphic shadow around screen\n float t = 0.95;\n float r = 2.75;\n nvgBeginPath(vg);\n nvgRoundedRect(vg, box.size.x - t, -t, 2 * t, box.size.y + t, r);\n nvgFillColor(vg, hiColor);\n nvgFill(vg);\n\n nvgBeginPath(vg);\n nvgRoundedRect(vg, -t, -t, box.size.x + 2 * t, 2 * t, r);\n nvgRoundedRect(vg, -t, -t, 2 * t, box.size.y + t, r);\n nvgFillColor(vg, loColor);\n nvgFill(vg);\n\n nvgBeginPath(vg);\n nvgRoundedRect(vg, -t, box.size.y - t, box.size.x + 2 * t, 2 * t, r);\n nvgFillColor(vg, hiColor);\n nvgFill(vg);\n\n // draw the empty screen\n nvgBeginPath(vg);\n nvgRoundedRect(vg, 0, 0, box.size.x, box.size.y, 2);\n nvgFillColor(vg, nvgRGB(0, 0, 0));\n nvgFill(vg);\n}\n\nvoid TeletypeScreenWidget::drawFocusRectangle(NVGcontext* vg)\n{\n // draw keyboard focus highlight rectangle\n NVGcolor color;\n levelToGradient(module->theme, 14, &color, nullptr);\n nvgBeginPath(vg);\n nvgRoundedRect(vg, -2, -2, box.size.x + 4, box.size.y + 4, 2.5);\n nvgStrokeColor(vg, color);\n nvgStrokeWidth(vg, 3.5);\n nvgStroke(vg);\n nvgFillColor(vg, color);\n nvgFill(vg);\n\n // redraw empty screen\n nvgBeginPath(vg);\n nvgRoundedRect(vg, 0, 0, box.size.x, box.size.y, 2);\n nvgFillColor(vg, nvgRGB(0, 0, 0));\n nvgFill(vg);\n}\n\nvoid TeletypeScreenWidget::drawPixels(NVGcontext* vg)\n{\n uint8_t* buffer = module ? module->getScreenBuffer() : exampleScreen;\n GridTheme theme = module ? module->theme : GridTheme::Yellow;\n uint16_t pixel_x = 128;\n uint16_t pixel_y = 64;\n\n if (buffer == NULL || pixel_x == 0 || pixel_y == 0)\n {\n return;\n }\n\n#ifdef SAVE_SCREEN_FILENAME\n std::ofstream ss(SAVE_SCREEN_FILENAME);\n ss << \"unsigned char exampleScreen[128 * 64] = {\\n\" << std::hex;\n for (int i = 0; i < 128 * 64; i++)\n {\n ss << \"0x\" << static_cast(buffer[i]) << \", \";\n }\n ss << \"\\n};\\n\";\n#endif\n\n int margin = 5;\n float pixel_width = (box.size.x - 2 * margin) / (pixel_x * 1.0);\n float pixel_height = (box.size.y - 2 * margin) / (pixel_y * 1.0);\n\n for (int j = 0; j < pixel_y; j++)\n {\n for (int i = 0; i < pixel_x; i++)\n {\n float x = margin + i * pixel_width;\n float y = margin + j * pixel_height;\n\n uint8_t d = *buffer++;\n if (d > 0)\n {\n drawPixel(vg, theme, x, y, pixel_width, pixel_height, d);\n }\n }\n }\n}\n\nvoid TeletypeScreenWidget::drawPixel(NVGcontext* vg, GridTheme theme, float x, float y, float width, float height, int data)\n{\n nvgBeginPath(vg);\n nvgRect(vg, x, y, width * 0.92, height * 0.92);\n NVGcolor color;\n levelToGradient(theme, data, &color, nullptr);\n nvgFillColor(vg, color);\n nvgFill(vg);\n}\n" }, { "path": "src/teletype/screen/TeletypeScreenWidget.hpp", "content": "#include \"LibAVR32Module.hpp\"\n#include \"VirtualGridTheme.hpp\"\n#include \"rack.hpp\"\n\nusing namespace rack;\n\nstruct TeletypeScreenWidget : OpaqueWidget\n{\n TeletypeScreenWidget(LibAVR32Module* module);\n\n virtual void onSelect(const event::Select& e) override;\n virtual void onDeselect(const event::Deselect& e) override;\n virtual void onSelectKey(const event::SelectKey& e) override;\n virtual void draw(const DrawArgs& args) override;\n virtual void drawLayer(const DrawArgs& args, int layer) override;\n\nprotected:\n void drawFrame(NVGcontext* vg);\n void drawFocusRectangle(NVGcontext* vg);\n void drawPixels(NVGcontext* vg);\n void drawPixel(NVGcontext* vg, GridTheme theme, float x, float y, float width, float height, int data);\n\n LibAVR32Module* module;\n};" }, { "path": "src/virtualgrid/VirtualGridKey.hpp", "content": "#include \"rack.hpp\"\n#include \"VirtualGridTheme.hpp\"\n\nstruct VirtualGridKey : rack::app::ParamWidget\n{\n uint8_t* ledAddress;\n GridTheme* theme;\n float margin;\n float pushAmount;\n float cornerRadius;\n\n typedef enum\n {\n OFF,\n PRESSED\n } KeyPressState;\n\n VirtualGridKey()\n : ledAddress(nullptr)\n , theme(nullptr)\n , margin(0.0)\n , pushAmount(0.0)\n , cornerRadius(0.0)\n , _locked(false)\n {\n }\n\n VirtualGridWidget* getGrid()\n {\n return dynamic_cast(parent);\n }\n\n void setKeyAddress(uint8_t* ledByte)\n {\n ledAddress = ledByte;\n }\n\n void draw(const DrawArgs& args) override\n {\n drawLayer(args, 0);\n }\n\n void drawLayer(const DrawArgs& args, int layer) override\n {\n auto vg = args.vg;\n uint8_t val = ledAddress != NULL ? *ledAddress : 0;\n auto rect = box.size;\n rect.x -= 2 * margin;\n rect.y -= 2 * margin;\n float x = margin;\n float y = margin;\n float pushed = isPushed(); // sample this once so it's consistent\n float innerCornerRadius = cornerRadius * 4.0 / 4.3;\n\n NVGcolor color1, color2;\n levelToGradient(\n theme ? *theme : GridTheme::Yellow, \n val,\n &color1, \n &color2\n );\n\n NVGcolor edgeColor = !rack::settings::preferDarkPanels ? nvgRGB(180, 180, 180) : nvgRGB(96, 96, 94);\n NVGcolor shadowColor = !rack::settings::preferDarkPanels ? nvgRGB(140, 140, 140) : nvgRGB(60, 60, 50);\n NVGcolor faceColor = !rack::settings::preferDarkPanels ? nvgRGB(58, 58, 58) : nvgRGB(20, 20, 10);\n\n if (!pushed)\n {\n // highlight top and side edges\n if ((val > 0 && layer == 1) || (val == 0 && layer == 0)) {\n nvgBeginPath(vg);\n nvgRoundedRect(vg, x - 0.3, y - 0.3, rect.x + 0.6, rect.y + 0.3, cornerRadius);\n nvgFillColor(vg, val > 0 ? color1 : edgeColor);\n nvgFill(vg);\n }\n\n // shadow\n if (layer == 0) {\n nvgBeginPath(vg);\n nvgRoundedRect(vg, x, y + pushAmount, rect.x, rect.y - pushAmount + 1.2, innerCornerRadius);\n nvgFillColor(vg, shadowColor);\n nvgFill(vg);\n }\n } else {\n // highlight top and side edges\n if ((val > 0 && layer == 1) || (val == 0 && layer == 0)) {\n nvgBeginPath(vg);\n nvgRoundedRect(vg, x - 0.3, y - 0.3 + pushAmount, rect.x + 0.6, rect.y - pushAmount + 0.3, cornerRadius);\n nvgFillColor(vg, val > 0 ? color1 : edgeColor);\n nvgFill(vg);\n }\n // shadow\n if (layer == 0) {\n nvgBeginPath(vg);\n nvgRoundedRect(vg, x, y + pushAmount, rect.x, rect.y - pushAmount + 0.8, innerCornerRadius);\n nvgFillColor(vg, shadowColor);\n nvgFill(vg);\n }\n }\n\n // button vertical face\n if (!pushed) {\n if ((val > 0 && layer == 1) || (val == 0 && layer == 0)) {\n nvgBeginPath(vg);\n nvgRoundedRect(vg, x, y + rect.y - (pushAmount + 10), rect.x, pushAmount + 10, innerCornerRadius);\n nvgFillColor(vg, val > 0 ? color2 : faceColor);\n nvgFill(vg);\n }\n }\n\n // button top surface\n if (layer == 1) {\n nvgBeginPath(vg);\n auto paint = nvgBoxGradient(vg, x, y + (pushed ? pushAmount : 0), rect.x, rect.y - pushAmount, rect.x * 0.4, rect.x * 1.2, color1, color2);\n nvgRoundedRect(vg, x, y + (pushed ? pushAmount : 0), rect.x, rect.y - pushAmount, innerCornerRadius);\n if (val > 0)\n {\n nvgFillPaint(vg, paint);\n }\n else\n {\n nvgFillColor(vg, nvgRGB(0, 0, 0));\n }\n nvgFill(vg);\n }\n\n if (isLocked())\n {\n NVGcolor lockColor = nvgRGB(0, 0, 0);\n\n if (val < 4)\n {\n levelToGradient(theme ? *theme : GridTheme::Yellow, 14, &lockColor, nullptr);\n }\n\n drawDot(args, x + rect.x / 4, y + 3 * rect.y / 4, rect.x / 4 - 1.5 * margin, lockColor);\n }\n }\n\n void drawDot(const DrawArgs& args, float cx, float cy, float r, NVGcolor& color)\n {\n auto vg = args.vg;\n\n nvgBeginPath(vg);\n nvgCircle(vg, cx, cy, r);\n nvgFillColor(vg, color);\n nvgFill(vg);\n }\n\n rack::engine::ParamQuantity* getSecondaryParamQuantity()\n {\n if (!module)\n return NULL;\n return module->paramQuantities[paramId + 1];\n }\n\n bool isPushed()\n {\n return\n (getParamQuantity() && getParamQuantity()->getValue() == PRESSED) ||\n (getSecondaryParamQuantity() && getSecondaryParamQuantity()->getValue() == PRESSED);\n }\n\n bool isLocked()\n {\n return _locked;\n }\n\n void setLocked(bool b)\n {\n _locked = b;\n }\n\n void beginPress()\n {\n if (getSecondaryParamQuantity())\n {\n // If shift+ctrl is held and this key is not already locked, lock it\n // If the key is locked, unlock it.\n if (isLocked())\n {\n setLocked(false);\n }\n else if ((APP->window->getMods() & GLFW_MOD_SHIFT) == GLFW_MOD_SHIFT &&\n (APP->window->getMods() & RACK_MOD_CTRL) == RACK_MOD_CTRL)\n {\n setLocked(true);\n getSecondaryParamQuantity()->setImmediateValue(PRESSED);\n return;\n }\n\n // if we're Ctrl/Mac-clicking an already-held button, release it\n if ((APP->window->getMods() & RACK_MOD_CTRL) == RACK_MOD_CTRL && getSecondaryParamQuantity()->getValue() > 0)\n {\n getSecondaryParamQuantity()->setImmediateValue(OFF);\n }\n else\n {\n getSecondaryParamQuantity()->setImmediateValue(PRESSED);\n }\n }\n }\n\n void endPress()\n {\n // Ignore mouseup if the key is locked, or when Ctrl is held down\n if (isLocked() || (APP->window->getMods() & RACK_MOD_CTRL) == RACK_MOD_CTRL)\n {\n return;\n }\n\n if (getSecondaryParamQuantity())\n {\n getSecondaryParamQuantity()->setImmediateValue(OFF);\n }\n }\n\n void onButton(const rack::event::Button& e) override\n {\n if (e.button == GLFW_MOUSE_BUTTON_LEFT)\n {\n if (e.action == GLFW_PRESS)\n {\n beginPress();\n }\n else\n {\n endPress();\n }\n }\n else if (e.button == GLFW_MOUSE_BUTTON_RIGHT)\n {\n // If this key has not been MIDI mapped, the right-click menu\n // is not useful, so show the module menu\n auto* paramHandle = module\n ? APP->engine->getParamHandle(module->id, paramId)\n : NULL;\n if (!paramHandle)\n {\n return;\n }\n }\n\n // Repeat logic from ParamWidget::onButton() with minor modifications\n OpaqueWidget::onButton(e);\n\n // Record touch so MIDI mapping works\n if (e.action == GLFW_PRESS && e.button == GLFW_MOUSE_BUTTON_LEFT && (e.mods & RACK_MOD_MASK) == 0)\n {\n if (module)\n {\n APP->scene->rack->touchedParam = this;\n }\n e.consume(this);\n }\n\n if (e.action == GLFW_PRESS && e.button == GLFW_MOUSE_BUTTON_RIGHT && (e.mods & RACK_MOD_MASK) == 0)\n {\n destroyTooltip();\n createContextMenu();\n e.consume(NULL); // replaces e.consume(this), which causes key to get pressed on right click for some reason\n }\n }\n\n void onDragStart(const rack::event::DragStart& e) override\n {\n beginPress();\n }\n\n void onDragEnd(const rack::event::DragEnd& e) override\n {\n if (e.getTarget() == nullptr || e.getTarget()->parent == this->parent)\n {\n endPress();\n }\n }\n\n void onDragLeave(const rack::event::DragLeave& e) override\n {\n if (e.origin->parent == this->parent)\n {\n endPress();\n }\n }\n\n void onDragEnter(const rack::event::DragEnter& e) override\n {\n if (e.origin->parent == this->parent)\n {\n beginPress();\n }\n }\n\n void onEnter(const EnterEvent& e) override\n {\n // override base class to prevent tooltip creation\n }\n\nprotected:\n bool _locked;\n};" }, { "path": "src/virtualgrid/VirtualGridModule.cpp", "content": "#include \"VirtualGridModule.hpp\"\n#include \"LibAVR32Module.hpp\"\n#include \"GridConsumerBase.hpp\"\n\n#include \n#include \n\nstruct MirrorModeGridConsumer : GridConsumerBase\n{\n MirrorModeGridConsumer(VirtualGridModule* module)\n : module(module)\n {\n }\n\n virtual ~MirrorModeGridConsumer()\n {\n }\n\n void gridConnected(Grid* newConnection) override\n {\n if (newConnection == module)\n {\n // don't mirror self\n return;\n }\n\n GridConsumerBase::gridConnected(newConnection);\n\n if (module && newConnection)\n {\n // update initial LED state\n uint8_t leds[64];\n for (int x_offset = 0; x_offset < 16; x_offset += 8)\n {\n for (int y_offset = 0; y_offset < 16; y_offset += 8)\n {\n for (int x = 0; x < 8; x++)\n {\n for (int y = 0; y < 8; y++)\n {\n leds[y * 8 + x] = module->ledBuffer[(y_offset + y) * 16 + x_offset + x];\n }\n }\n newConnection->updateQuadrant(x_offset, y_offset, leds);\n }\n }\n }\n }\n\n void gridButtonEvent(int x, int y, bool state) override\n {\n if (module)\n {\n int w = module->device.width;\n auto param = module->getParamQuantity((x + y * w) * 2);\n if (param)\n {\n module->audioThreadActions.push([param, state]()\n { param->setImmediateValue(state ? 1 : 0); });\n }\n }\n }\n\n void encDeltaEvent(int n, int d) override\n {\n\n }\n\nprotected:\n VirtualGridModule* module;\n};\n\nstd::string formatVirtualDeviceId(int64_t id)\n{\n std::ostringstream ss;\n std::string prefix(\"virt\");\n\n // Rack IDs are in the range 0-2^53\n ss << prefix << std::setw(14) << std::setfill('0') << std::hex << id;\n return ss.str();\n}\n\nVirtualGridModule::VirtualGridModule(unsigned w, unsigned h)\n{\n if (w * h > GRID_MAX_SIZE) {\n FATAL(\"Unsupported grid size\");\n assert(0);\n }\n\n config(w * h * 2, 0, 0, 0);\n\n for (unsigned j = 0; j < h; j++)\n {\n for (unsigned i = 0; i < w; i++)\n {\n int n = i + j * w * 2;\n // first set of params, for midi mapping\n auto param = configButton(n, rack::string::f(\"(%d,%d)\", i , j));\n param->resetEnabled = false;\n param->smoothEnabled = false;\n param->randomizeEnabled = false;\n // second set of params, for interactive use\n param = configButton(n + 1, rack::string::f(\"(%d,%d)\", i, j));\n param->resetEnabled = false;\n param->smoothEnabled = false;\n param->randomizeEnabled = false;\n }\n }\n\n device.width = w;\n device.height = h;\n device.port = 0;\n device.rotation = 0;\n device.id = formatVirtualDeviceId(0);\n device.prefix = \"\";\n device.type = \"virtual \" + std::to_string(w * h);\n device.protocol = PROTOCOL_MEXT;\n\n theme = GridTheme::Yellow;\n\n mirrorModeConsumer = new MirrorModeGridConsumer(this);\n\n clearAll();\n}\n\nVirtualGridModule::~VirtualGridModule()\n{\n GridConnectionManager::get().deregisterGridConsumer(mirrorModeConsumer);\n delete mirrorModeConsumer;\n}\n\nvoid VirtualGridModule::onAdd()\n{\n device.id = formatVirtualDeviceId(id);\n}\n\nvoid VirtualGridModule::process(const ProcessArgs& args)\n{\n while (audioThreadActions.size())\n {\n audioThreadActions.shift()();\n }\n\n std::vector> presses;\n std::vector> releases;\n\n for (int i = 0; i < device.width; i++)\n {\n for (int j = 0; j < device.height; j++)\n {\n // we need to check the pressed state of two parameters per button,\n // one for MIDI mapping, one for interactive presses, in order to\n // prevent midi-mappings from locking a button at 0 and preventing clicking.\n int n = i + (j * device.width);\n int p = n * 2;\n bool state = (params[p].getValue() > 0) || (params[p + 1].getValue() > 0);\n if (state != pressedState[n])\n {\n pressedState[n] = state;\n if (state) {\n presses.push_back(std::make_tuple(i, j));\n } else {\n releases.push_back(std::make_tuple(i, j));\n }\n }\n }\n }\n\n // ensure any near-simultaneous releases and presses are processed releases-first\n std::for_each(releases.begin(), releases.end(), [=](std::tuple c) {\n GridConnectionManager::get().dispatchButtonMessage(&this->device, std::get<0>(c), std::get<1>(c), false);\n });\n\n std::for_each(presses.begin(), presses.end(), [=](std::tuple c) {\n GridConnectionManager::get().dispatchButtonMessage(&this->device, std::get<0>(c), std::get<1>(c), true);\n });\n}\n\njson_t* VirtualGridModule::dataToJson()\n{\n json_t* rootJ = json_object();\n json_object_set_new(rootJ, \"protocol\", json_integer(device.protocol));\n json_object_set_new(rootJ, \"theme\", json_integer(theme));\n\n auto consumer = dynamic_cast(mirrorModeConsumer);\n if (consumer)\n {\n json_t* mirrorJ = json_object();\n consumer->saveGridConnectionToJson(mirrorJ);\n json_object_set_new(rootJ, \"mirror\", mirrorJ);\n }\n\n return rootJ;\n}\n\njson_t* VirtualGridModule::paramsToJson()\n{\n // don't serialize key states\n json_t* rootJ = json_array();\n return rootJ;\n}\n\nvoid VirtualGridModule::dataFromJson(json_t* rootJ)\n{\n auto json_proto = json_object_get(rootJ, \"protocol\");\n if (json_proto)\n {\n device.protocol = static_cast(json_integer_value(json_proto));\n }\n\n auto json_theme = json_object_get(rootJ, \"theme\");\n if (json_theme)\n {\n theme = static_cast(json_integer_value(json_theme));\n }\n\n auto consumer = dynamic_cast(mirrorModeConsumer);\n if (consumer)\n {\n auto json_mirror = json_object_get(rootJ, \"mirror\");\n consumer->loadGridConnectionFromJson(json_mirror);\n GridConnectionManager::get().registerGridConsumer(consumer);\n }\n}\n\nconst MonomeDevice& VirtualGridModule::getDevice()\n{\n return device;\n}\n\nvoid VirtualGridModule::updateRow(int x_offset, int y, uint8_t bitfield)\n{\n if (mirrorModeConsumer)\n {\n auto mirroredGrid = mirrorModeConsumer->gridGetDevice();\n if (mirroredGrid)\n {\n mirroredGrid->updateRow(x_offset, y, bitfield);\n }\n }\n\n uint8_t* ptr = ledBuffer + y * 16 + x_offset;\n for (int i = 0; i < 8; i++)\n {\n *ptr++ = ((bitfield & (1 << i)) > 0) ? 0xF : 0;\n }\n}\n\nvoid VirtualGridModule::updateQuadrant(int x_offset, int y_offset, uint8_t* leds)\n{\n if (mirrorModeConsumer)\n {\n auto mirroredGrid = mirrorModeConsumer->gridGetDevice();\n if (mirroredGrid)\n {\n mirroredGrid->updateQuadrant(x_offset, y_offset, leds);\n }\n }\n\n uint8_t* ptr = ledBuffer + y_offset * 16 + x_offset;\n for (int i = 0; i < 8; i++)\n {\n for (int j = 0; j < 8; j++)\n {\n *ptr++ = *leds++;\n }\n ptr += 8;\n }\n}\n\nvoid VirtualGridModule::clearAll()\n{\n memset(ledBuffer, 0, sizeof(uint8_t) * GRID_MAX_SIZE);\n memset(pressedState, 0, sizeof(uint8_t) * GRID_MAX_SIZE);\n\n for (auto p : params)\n {\n p.setValue(0);\n }\n}\n" }, { "path": "src/virtualgrid/VirtualGridModule.hpp", "content": "#pragma once\n#include \"GridConnection.hpp\"\n#include \"VirtualGridTheme.hpp\"\n#include \"rack.hpp\"\n#include \"ActionQueue.hpp\"\n\n#define GRID_MAX_SIZE 256\n\n\nstruct VirtualGridModule : rack::Module, Grid\n{\n MonomeDevice device;\n GridTheme theme;\n\n uint8_t ledBuffer[GRID_MAX_SIZE];\n bool pressedState[GRID_MAX_SIZE];\n\n VirtualGridModule(unsigned w, unsigned h);\n ~VirtualGridModule();\n\n // rack::Module virtual methods\n void onAdd() override;\n void process(const ProcessArgs& args) override;\n json_t* dataToJson() override;\n json_t* paramsToJson() override;\n void dataFromJson(json_t* rootJ) override;\n\n // Grid virtual methods\n const MonomeDevice& getDevice() override;\n void updateRow(int x_offset, int y, uint8_t bitfield) override;\n void updateQuadrant(int x_offset, int y_offset, uint8_t* leds) override;\n void updateRing(int n, uint8_t leds[64]) override {};\n void clearAll() override;\n bool isHardware() override { return false; }\n\n IGridConsumer* mirrorModeConsumer;\n ActionQueue audioThreadActions;\n};\n\ntemplate \nstruct VirtualGridModuleTemplate : VirtualGridModule\n{\n VirtualGridModuleTemplate()\n : VirtualGridModule(width, height)\n {\n }\n};\n" }, { "path": "src/virtualgrid/VirtualGridTheme.cpp", "content": "#include \"VirtualGridTheme.hpp\"\n\nNVGcolor themeColors[4][16][2];\n\n// e^kx - 1 / e^k - 1 easing function\nint ease(int level, int minval, int maxval, float curve)\n{\n int range = maxval - minval;\n float y = (exp(curve * level / 15.0) - 1) / (exp(curve) - 1);\n return (int)floor(y * range) + minval;\n}\n\nNVGcolor calcColor(int level, float curve, int minR, int maxR, int minG, int maxG, int minB, int maxB)\n{\n return nvgRGB(ease(level, minR, maxR, curve), ease(level, minG, maxG, curve), ease(level, minB, maxB, curve));\n}\n\nvoid initThemes()\n{\n float curve0 = -2.7;\n float curve1 = -2.2;\n\n for (int level = 0; level < 16; level++)\n {\n themeColors[GridTheme::Red][level][0] = calcColor(level, curve0, 20, 255, 15, 175, 5, 30);\n themeColors[GridTheme::Red][level][1] = calcColor(level, curve1, 15, 255, 10, 85, 0, 15);\n\n themeColors[GridTheme::Orange][level][0] = calcColor(level, curve0, 15, 255, 15, 210, 0, 75);\n themeColors[GridTheme::Orange][level][1] = calcColor(level, curve1, 12, 225, 10, 115, 0, 45);\n\n themeColors[GridTheme::White][level][0] = calcColor(level, curve0, 30, 255, 22, 255, 22, 207);\n themeColors[GridTheme::White][level][1] = calcColor(level, curve1, 15, 160, 15, 170, 15, 224);\n\n themeColors[GridTheme::Yellow][level][0] = calcColor(level, curve0, 22, 255, 22, 250, 21, 142);\n themeColors[GridTheme::Yellow][level][1] = calcColor(level, curve1, 9, 203, 3, 176, 6, 217);\n }\n}\n\nvoid levelToGradient(GridTheme theme, uint8_t level, NVGcolor* color1, NVGcolor* color2)\n{\n if (theme >= 0 && theme < 4 && level >= 0 && level < 16)\n {\n if (color1)\n {\n *color1 = themeColors[theme][level][0];\n }\n if (color2)\n {\n *color2 = themeColors[theme][level][1];\n }\n }\n}\n" }, { "path": "src/virtualgrid/VirtualGridTheme.hpp", "content": "#pragma once\n#include \"rack.hpp\"\n\ntypedef enum\n{\n Red,\n Orange,\n Yellow,\n White,\n NUM_THEMES\n} GridTheme;\n\nvoid levelToGradient(GridTheme theme, uint8_t level, NVGcolor* color1, NVGcolor* color2);\nvoid initThemes();" }, { "path": "src/virtualgrid/VirtualGridWidget.cpp", "content": "#include \"VirtualGridWidget.hpp\"\n#include \"Screenshot.hpp\"\n#include \"VirtualGridKey.hpp\"\n#include \"VirtualGridModule.hpp\"\n#include \"VirtualGridTheme.hpp\"\n#include \"GridConnectionMenu.hpp\"\n\nusing namespace rack;\n\nuint8_t samplePattern[] = {\n 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0,\n 0, 15, 0, 14, 0, 0, 0, 0, 0, 15, 0, 14, 0, 0, 0, 0,\n 0, 14, 0, 12, 0, 0, 15, 0, 0, 14, 0, 12, 0, 15, 0, 0,\n 0, 12, 0, 9, 15, 0, 14, 0, 0, 12, 0, 9, 0, 14, 0, 0,\n 15, 9, 0, 5, 14, 0, 12, 0, 0, 9, 0, 5, 0, 12, 0, 15,\n 14, 5, 0, 1, 12, 0, 9, 0, 0, 5, 0, 1, 0, 9, 0, 14,\n 12, 1, 0, 0, 9, 0, 5, 0, 15, 1, 0, 0, 0, 5, 0, 12,\n 9, 0, 0, 0, 5, 0, 1, 0, 14, 0, 0, 0, 0, 1, 0, 9,\n 5, 0, 0, 0, 1, 15, 0, 0, 12, 0, 0, 0, 0, 0, 15, 5,\n 1, 0, 15, 0, 0, 14, 0, 0, 9, 0, 0, 0, 0, 0, 14, 1,\n 0, 0, 14, 0, 0, 12, 0, 0, 5, 0, 15, 0, 0, 0, 12, 0,\n 0, 0, 12, 0, 0, 9, 0, 0, 1, 0, 14, 0, 15, 0, 9, 0,\n 0, 0, 9, 0, 0, 5, 0, 15, 0, 0, 12, 0, 14, 0, 5, 0,\n 0, 0, 5, 0, 0, 1, 0, 14, 0, 0, 9, 0, 12, 0, 1, 0,\n 0, 0, 1, 0, 0, 0, 0, 12, 0, 0, 5, 0, 9, 0, 0, 0,\n 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 1, 0, 5, 0, 0, 0,\n};\n\nGridTheme sampleThemeYellow = GridTheme::Yellow;\nGridTheme sampleThemeOrange = GridTheme::Orange;\nGridTheme sampleThemeRed = GridTheme::Red;\n\nVirtualGridWidget::VirtualGridWidget(VirtualGridModule* module, unsigned w, unsigned h)\n{\n setModule(module);\n if (module)\n {\n VirtualGridModule* grid = dynamic_cast(module);\n assert(grid);\n GridConnectionManager::get().registerGrid(grid);\n id = grid->device.id;\n }\n\n float rackWidth = 0;\n GridTheme* sampleTheme = &sampleThemeYellow;\n\n if (w == h)\n {\n rackWidth = 375;\n margins.x = 13.5;\n margins.y = 16;\n sampleTheme = h == 8 ? &sampleThemeOrange : &sampleThemeRed;\n }\n else if (w == 2 * h)\n {\n rackWidth = 735;\n margins.x = 16;\n margins.y = 16;\n sampleTheme = &sampleThemeYellow;\n }\n else\n {\n FATAL(\"Unsupported grid size\");\n assert(0);\n }\n\n box.size = Vec(rackWidth, 380);\n\n {\n auto panel = new ThemedSvgPanel();\n panel->setBackground(\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/grid.svg\")),\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/grid-dark.svg\")));\n panel->box.size = box.size;\n addChild(panel);\n }\n\n // create an opaque child underneath the keys to defeat module dragging in between the buttons\n auto gridZone = new OpaqueWidget();\n gridZone->setSize(Vec(box.size.x - 2 * margins.x, box.size.y - 2 * margins.y));\n gridZone->setPosition(Vec(margins.x, margins.y));\n addChild(gridZone);\n\n float spacingRatio = 0.14;\n float button_size = (box.size.y - margins.y * 2) / (h + (h - 1) * spacingRatio);\n float spacing = button_size * spacingRatio;\n float keyMargin = 0.5 * spacing;\n\n for (unsigned j = 0; j < h; j++)\n {\n for (unsigned i = 0; i < w; i++)\n {\n float x = margins.x + i * (button_size + spacing) - keyMargin;\n float y = margins.y + j * (button_size + spacing) - keyMargin;\n int n = i + j * w;\n\n VirtualGridKey* key = (VirtualGridKey*)createParam(Vec(x, y), module, n * 2);\n if (module)\n {\n key->setKeyAddress(module->ledBuffer + i + j * 16);\n key->theme = &(module->theme);\n } else {\n key->setKeyAddress(samplePattern + i + j * 16);\n key->theme = sampleTheme;\n }\n key->box.size = Vec(button_size + spacing, button_size + spacing);\n key->margin = keyMargin;\n key->pushAmount = h == 16 ? 2.1 : 3.8;\n key->cornerRadius = h == 16 ? 2.5 : 4.3;\n addParam(key);\n }\n }\n}\n\nVirtualGridWidget::~VirtualGridWidget()\n{\n if (module)\n {\n GridConnectionManager::get().deregisterGrid(id);\n }\n}\n\nvoid VirtualGridWidget::clearHeldKeys()\n{\n for (auto p : getParams())\n {\n auto key = static_cast(p);\n if (key && !key->isLocked())\n {\n key->getSecondaryParamQuantity()->setImmediateValue(VirtualGridKey::OFF);\n }\n }\n}\n\nvoid VirtualGridWidget::clearLockedKeys()\n{\n for (auto p : getParams())\n {\n auto key = static_cast(p);\n if (key && key->isLocked())\n {\n key->setLocked(false);\n key->getSecondaryParamQuantity()->setImmediateValue(VirtualGridKey::OFF);\n }\n }\n}\n\nvoid VirtualGridWidget::onDragEnter(const event::DragEnter& e)\n{\n}\n\nvoid VirtualGridWidget::onDragStart(const event::DragStart& e)\n{\n ModuleWidget::onDragStart(e);\n}\n\nvoid VirtualGridWidget::onDragEnd(const event::DragEnd& e)\n{\n ModuleWidget::onDragEnd(e);\n}\n\nvoid VirtualGridWidget::onDragLeave(const event::DragLeave& e)\n{\n clearHeldKeys();\n ModuleWidget::onDragLeave(e);\n}\n\nvoid VirtualGridWidget::onHoverKey(const rack::Widget::HoverKeyEvent& e)\n{\n#if defined ARCH_MAC\n bool isHoldModifier = e.key == GLFW_KEY_LEFT_SUPER || e.key == GLFW_KEY_RIGHT_SUPER;\n#else\n bool isHoldModifier = e.key == GLFW_KEY_LEFT_CONTROL || e.key == GLFW_KEY_RIGHT_CONTROL;\n#endif\n\n if (isHoldModifier && e.action == GLFW_RELEASE)\n {\n clearHeldKeys();\n }\n else if (e.key == GLFW_KEY_ESCAPE && e.action == GLFW_PRESS)\n {\n clearHeldKeys();\n clearLockedKeys();\n }\n else\n {\n rack::app::ModuleWidget::onHoverKey(e);\n }\n}\n\nvoid VirtualGridWidget::onLeave(const rack::Widget::LeaveEvent& e)\n{\n clearHeldKeys();\n}\n\nvoid setProtocol(VirtualGridModule* grid, MonomeProtocol protocol)\n{\n if (protocol != grid->device.protocol)\n {\n GridConnectionManager::get().deregisterGrid(grid->device.id, false);\n grid->device.protocol = protocol;\n GridConnectionManager::get().registerGrid(grid);\n }\n}\n\nvoid VirtualGridWidget::appendContextMenu(Menu * menu)\n{\n VirtualGridModule* grid = dynamic_cast(module);\n assert(grid);\n\n menu->addChild(new MenuSeparator());\n\n menu->addChild(createMenuItem(\"Save grid screenshot\", \"\", [this]() {\n screenshotModulePNG(this, \"grid-screenshot.png\");\n }));\n\n menu->addChild(createSubmenuItem(\"Mirror hardware grid\", \"\", [=](Menu *childMenu) {\n appendDeviceConnectionMenu(childMenu, grid->mirrorModeConsumer, &grid->audioThreadActions, true);\n childMenu->addChild(createMenuItem(\"Stop mirroring\", \"\",\n [=]() {\n if (grid->mirrorModeConsumer) {\n GridConnectionManager::get().disconnect(grid->mirrorModeConsumer);\n grid->mirrorModeConsumer->setLastDeviceId(\"\");\n }\n },\n !grid->mirrorModeConsumer || grid->mirrorModeConsumer->gridGetDevice() == nullptr\n ));\n }));\n\n menu->addChild(new MenuSeparator());\n menu->addChild(createIndexPtrSubmenuItem(\"Theme\", { \"Red\", \"Orange\", \"Yellow\", \"White\" }, &grid->theme));\n menu->addChild(createIndexSubmenuItem(\"Protocol\", {\"40h\", \"Series\", \"Mext (varibright)\"}, \n [=]() {\n return grid ? grid->device.protocol : 0;\n },\n [=](size_t index) {\n setProtocol(grid, static_cast(index));\n }));\n\n menu->addChild(createMenuItem(\"Release Locked Keys\", \"Esc\", [this]() {\n this->clearLockedKeys();\n }));\n\n menu->addChild(construct(&MenuLabel::text, model->name + \" (\" + id + \")\"));\n}" }, { "path": "src/virtualgrid/VirtualGridWidget.hpp", "content": "#include \"rack.hpp\"\n\n#pragma once\n\nextern rack::Plugin* pluginInstance;\n\nstruct VirtualGridKey;\nstruct VirtualGridModule;\n\nstruct VirtualGridWidget : rack::app::ModuleWidget\n{\n VirtualGridWidget(VirtualGridModule* module, unsigned w, unsigned h);\n ~VirtualGridWidget();\n\n void onDragEnter(const rack::event::DragEnter& e) override;\n void onDragStart(const rack::event::DragStart& e) override;\n void onDragEnd(const rack::event::DragEnd& e) override;\n void onDragLeave(const rack::event::DragLeave& e) override;\n void onHoverKey(const rack::Widget::HoverKeyEvent& e) override;\n void onLeave(const rack::Widget::LeaveEvent& e) override;\n void appendContextMenu(rack::ui::Menu* menu) override;\n\n void clearHeldKeys();\n void clearLockedKeys();\n\nprotected:\n friend struct VirtualGridKey;\n rack::Vec margins;\n std::string id;\n};\n\ntemplate \nstruct VirtualGridWidgetTemplate : VirtualGridWidget\n{\n VirtualGridWidgetTemplate(VirtualGridModule* module)\n : VirtualGridWidget(module, width, height)\n {\n }\n};\n" }, { "path": "src/whitewhale/WhiteWhaleModule.hpp", "content": "#pragma once\n\n#include \"LibAVR32Module.hpp\"\n#include \"Clock12BitParam.hpp\"\n\nstruct WhiteWhaleModule : LibAVR32Module\n{\n enum ParamIds\n {\n CLOCK_PARAM,\n PARAM_PARAM,\n BUTTON_PARAM,\n USB_PARAM,\n NUM_PARAMS\n };\n\n enum InputIds\n {\n CLOCK_INPUT,\n NUM_INPUTS\n };\n\n enum OutputIds\n {\n CLOCK_OUTPUT,\n TR1_OUTPUT,\n TR2_OUTPUT,\n TR3_OUTPUT,\n TR4_OUTPUT,\n CVA_OUTPUT,\n CVB_OUTPUT,\n NUM_OUTPUTS\n };\n\n enum LightIds\n {\n CLOCK_LIGHT,\n TR1_LIGHT,\n TR2_LIGHT,\n TR3_LIGHT,\n TR4_LIGHT,\n CVA_LIGHT,\n CVB_LIGHT,\n NUM_LIGHTS\n };\n\n rack::dsp::SchmittTrigger clockTrigger;\n\n WhiteWhaleModule()\n : LibAVR32Module(\"whitewhale\", \"whitewhale\")\n {\n config(NUM_PARAMS, NUM_INPUTS, NUM_OUTPUTS, NUM_LIGHTS);\n configButton(BUTTON_PARAM, \"PRESET\");\n configParam(PARAM_PARAM, 0.0, 10.0, 5.0, \"PARAM\");\n configParam>(CLOCK_PARAM, 0.0, 10.0, 5.0, \"CLOCK\", \"ms\");\n configInput(CLOCK_INPUT, \"CLOCK\");\n configOutput(CLOCK_OUTPUT, \"CLOCK\");\n configOutput(TR1_OUTPUT, \"TR 1\");\n configOutput(TR2_OUTPUT, \"TR 2\");\n configOutput(TR3_OUTPUT, \"TR 3\");\n configOutput(TR4_OUTPUT, \"TR 4\");\n configOutput(CVA_OUTPUT, \"CV A\");\n configOutput(CVB_OUTPUT, \"CV B\");\n configButton(USB_PARAM, \"USB Device Port\");\n\n setDeviceConnectionParam(USB_PARAM);\n }\n\n void processInputs(const ProcessArgs& args) override\n {\n // Convert clock input jack to GPIO signals for normal connection and value\n bool clockNormal = !inputs[CLOCK_INPUT].isConnected();\n if (clockNormal != firmware.getGPIO(B09))\n {\n firmware.setGPIO(B09, clockNormal);\n firmware.triggerInterrupt(1);\n }\n\n clockTrigger.process(inputs[CLOCK_INPUT].getVoltage(), triggerLowThreshold, triggerHighThreshold);\n bool externalClock = clockTrigger.isHigh();\n if (externalClock != firmware.getGPIO(B08))\n {\n firmware.setGPIO(B08, externalClock);\n firmware.triggerInterrupt(2);\n }\n\n bool frontButton = params[BUTTON_PARAM].getValue() == 0;\n if (frontButton != firmware.getGPIO(NMI))\n {\n firmware.setGPIO(NMI, frontButton);\n firmware.triggerInterrupt(3);\n }\n\n // Convert knob float parameters to 12-bit ADC values\n firmware.setADC(0, voltsToAdc(params[CLOCK_PARAM].getValue()));\n firmware.setADC(1, voltsToAdc(params[PARAM_PARAM].getValue()));\n }\n\n void processOutputs(const ProcessArgs& args) override\n {\n float cv1 = dacToVolts(firmware.getDAC(0));\n float cv2 = dacToVolts(firmware.getDAC(1));\n bool clock = firmware.getGPIO(B10);\n bool tr1 = firmware.getGPIO(B00);\n bool tr2 = firmware.getGPIO(B01);\n bool tr3 = firmware.getGPIO(B02);\n bool tr4 = firmware.getGPIO(B03);\n\n // Update lights from GPIO\n lights[CLOCK_LIGHT].setSmoothBrightness(clock, args.sampleTime);\n lights[TR1_LIGHT].setSmoothBrightness(tr1, args.sampleTime);\n lights[TR2_LIGHT].setSmoothBrightness(tr2, args.sampleTime);\n lights[TR3_LIGHT].setSmoothBrightness(tr3, args.sampleTime);\n lights[TR4_LIGHT].setSmoothBrightness(tr4, args.sampleTime);\n lights[CVA_LIGHT].setSmoothBrightness(cv1 / 10.0, args.sampleTime);\n lights[CVB_LIGHT].setSmoothBrightness(cv2 / 10.0, args.sampleTime);\n\n // Update output jacks from GPIO & DAC\n outputs[CLOCK_OUTPUT].setVoltage(clock * 8.0);\n outputs[TR1_OUTPUT].setVoltage(tr1 * 8.0);\n outputs[TR2_OUTPUT].setVoltage(tr2 * 8.0);\n outputs[TR3_OUTPUT].setVoltage(tr3 * 8.0);\n outputs[TR4_OUTPUT].setVoltage(tr4 * 8.0);\n outputs[CVA_OUTPUT].setVoltage(cv1);\n outputs[CVB_OUTPUT].setVoltage(cv2);\n }\n};" }, { "path": "src/whitewhale/WhiteWhaleWidget.hpp", "content": "#pragma once\n\n#include \"LibAVR32ModuleWidget.hpp\"\n#include \"SifamTPM.hpp\"\n#include \"USBAJack.hpp\"\n#include \"WhiteWhaleModule.hpp\"\n\nusing namespace rack;\n\nstruct WhiteWhaleWidget : LibAVR32ModuleWidget\n{\n WhiteWhaleWidget(WhiteWhaleModule* module)\n {\n setModule(module);\n\n box.size = Vec(15 * 6, 380);\n\n {\n auto panel = new ThemedSvgPanel();\n panel->setBackground(\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/whitewhale.svg\")),\n APP->window->loadSvg(rack::asset::plugin(pluginInstance, \"res/whitewhale-dark.svg\")));\n panel->box.size = box.size;\n addChild(panel);\n }\n\n // Screws positioned for sliding nuts :)\n addChild(createWidget(Vec(RACK_GRID_WIDTH / 2, 0)));\n addChild(createWidget(Vec(RACK_GRID_WIDTH / 2, RACK_GRID_HEIGHT - RACK_GRID_WIDTH)));\n\n addParam(createParam(Vec(7, 333), module, WhiteWhaleModule::USB_PARAM));\n addParam(createParam(Vec(62, 336), module, WhiteWhaleModule::BUTTON_PARAM));\n addParam(createParam(Vec(12, 30), module, WhiteWhaleModule::PARAM_PARAM));\n addParam(createParam(Vec(12, 232), module, WhiteWhaleModule::CLOCK_PARAM));\n\n addOutput(createOutput(Vec(50, 83), module, WhiteWhaleModule::TR1_OUTPUT));\n addOutput(createOutput(Vec(50, 121), module, WhiteWhaleModule::TR2_OUTPUT));\n addOutput(createOutput(Vec(50, 159), module, WhiteWhaleModule::TR3_OUTPUT));\n addOutput(createOutput(Vec(50, 197), module, WhiteWhaleModule::TR4_OUTPUT));\n addOutput(createOutput(Vec(15, 101), module, WhiteWhaleModule::CVA_OUTPUT));\n addOutput(createOutput(Vec(15, 139), module, WhiteWhaleModule::CVB_OUTPUT));\n addInput(createInput(Vec(13, 286), module, WhiteWhaleModule::CLOCK_INPUT));\n addOutput(createOutput(Vec(50, 286), module, WhiteWhaleModule::CLOCK_OUTPUT));\n\n addChild(createLight>(Vec(77, 79), module, WhiteWhaleModule::TR1_LIGHT));\n addChild(createLight>(Vec(77, 117), module, WhiteWhaleModule::TR2_LIGHT));\n addChild(createLight>(Vec(77, 155), module, WhiteWhaleModule::TR3_LIGHT));\n addChild(createLight>(Vec(77, 193), module, WhiteWhaleModule::TR4_LIGHT));\n addChild(createLight>(Vec(77, 282), module, WhiteWhaleModule::CLOCK_LIGHT));\n addChild(createLight>(Vec(3, 117), module, WhiteWhaleModule::CVA_LIGHT));\n addChild(createLight>(Vec(3, 155), module, WhiteWhaleModule::CVB_LIGHT));\n }\n};\n" } ]